1 /* 2 * Copyright (c) 2017 Intel Corporation. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License version 6 * 2 as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 * 13 */ 14 15 #include <linux/acpi.h> 16 #include <linux/i2c.h> 17 #include <linux/module.h> 18 #include <linux/pm_runtime.h> 19 #include <media/v4l2-ctrls.h> 20 #include <media/v4l2-device.h> 21 22 #define OV13858_REG_VALUE_08BIT 1 23 #define OV13858_REG_VALUE_16BIT 2 24 #define OV13858_REG_VALUE_24BIT 3 25 26 #define OV13858_REG_MODE_SELECT 0x0100 27 #define OV13858_MODE_STANDBY 0x00 28 #define OV13858_MODE_STREAMING 0x01 29 30 #define OV13858_REG_SOFTWARE_RST 0x0103 31 #define OV13858_SOFTWARE_RST 0x01 32 33 /* PLL1 generates PCLK and MIPI_PHY_CLK */ 34 #define OV13858_REG_PLL1_CTRL_0 0x0300 35 #define OV13858_REG_PLL1_CTRL_1 0x0301 36 #define OV13858_REG_PLL1_CTRL_2 0x0302 37 #define OV13858_REG_PLL1_CTRL_3 0x0303 38 #define OV13858_REG_PLL1_CTRL_4 0x0304 39 #define OV13858_REG_PLL1_CTRL_5 0x0305 40 41 /* PLL2 generates DAC_CLK, SCLK and SRAM_CLK */ 42 #define OV13858_REG_PLL2_CTRL_B 0x030b 43 #define OV13858_REG_PLL2_CTRL_C 0x030c 44 #define OV13858_REG_PLL2_CTRL_D 0x030d 45 #define OV13858_REG_PLL2_CTRL_E 0x030e 46 #define OV13858_REG_PLL2_CTRL_F 0x030f 47 #define OV13858_REG_PLL2_CTRL_12 0x0312 48 #define OV13858_REG_MIPI_SC_CTRL0 0x3016 49 #define OV13858_REG_MIPI_SC_CTRL1 0x3022 50 51 /* Chip ID */ 52 #define OV13858_REG_CHIP_ID 0x300a 53 #define OV13858_CHIP_ID 0x00d855 54 55 /* V_TIMING internal */ 56 #define OV13858_REG_VTS 0x380e 57 #define OV13858_VTS_30FPS 0x0c8e /* 30 fps */ 58 #define OV13858_VTS_60FPS 0x0648 /* 60 fps */ 59 #define OV13858_VTS_MAX 0x7fff 60 61 /* HBLANK control - read only */ 62 #define OV13858_PPL_270MHZ 2244 63 #define OV13858_PPL_540MHZ 4488 64 65 /* Exposure control */ 66 #define OV13858_REG_EXPOSURE 0x3500 67 #define OV13858_EXPOSURE_MIN 4 68 #define OV13858_EXPOSURE_STEP 1 69 #define OV13858_EXPOSURE_DEFAULT 0x640 70 71 /* Analog gain control */ 72 #define OV13858_REG_ANALOG_GAIN 0x3508 73 #define OV13858_ANA_GAIN_MIN 0 74 #define OV13858_ANA_GAIN_MAX 0x1fff 75 #define OV13858_ANA_GAIN_STEP 1 76 #define OV13858_ANA_GAIN_DEFAULT 0x80 77 78 /* Digital gain control */ 79 #define OV13858_REG_B_MWB_GAIN 0x5100 80 #define OV13858_REG_G_MWB_GAIN 0x5102 81 #define OV13858_REG_R_MWB_GAIN 0x5104 82 #define OV13858_DGTL_GAIN_MIN 0 83 #define OV13858_DGTL_GAIN_MAX 16384 /* Max = 16 X */ 84 #define OV13858_DGTL_GAIN_DEFAULT 1024 /* Default gain = 1 X */ 85 #define OV13858_DGTL_GAIN_STEP 1 /* Each step = 1/1024 */ 86 87 /* Test Pattern Control */ 88 #define OV13858_REG_TEST_PATTERN 0x4503 89 #define OV13858_TEST_PATTERN_ENABLE BIT(7) 90 #define OV13858_TEST_PATTERN_MASK 0xfc 91 92 /* Number of frames to skip */ 93 #define OV13858_NUM_OF_SKIP_FRAMES 2 94 95 struct ov13858_reg { 96 u16 address; 97 u8 val; 98 }; 99 100 struct ov13858_reg_list { 101 u32 num_of_regs; 102 const struct ov13858_reg *regs; 103 }; 104 105 /* Link frequency config */ 106 struct ov13858_link_freq_config { 107 u32 pixel_rate; 108 u32 pixels_per_line; 109 110 /* PLL registers for this link frequency */ 111 struct ov13858_reg_list reg_list; 112 }; 113 114 /* Mode : resolution and related config&values */ 115 struct ov13858_mode { 116 /* Frame width */ 117 u32 width; 118 /* Frame height */ 119 u32 height; 120 121 /* V-timing */ 122 u32 vts_def; 123 u32 vts_min; 124 125 /* Index of Link frequency config to be used */ 126 u32 link_freq_index; 127 /* Default register values */ 128 struct ov13858_reg_list reg_list; 129 }; 130 131 /* 4224x3136 needs 1080Mbps/lane, 4 lanes */ 132 static const struct ov13858_reg mipi_data_rate_1080mbps[] = { 133 /* PLL1 registers */ 134 {OV13858_REG_PLL1_CTRL_0, 0x07}, 135 {OV13858_REG_PLL1_CTRL_1, 0x01}, 136 {OV13858_REG_PLL1_CTRL_2, 0xc2}, 137 {OV13858_REG_PLL1_CTRL_3, 0x00}, 138 {OV13858_REG_PLL1_CTRL_4, 0x00}, 139 {OV13858_REG_PLL1_CTRL_5, 0x01}, 140 141 /* PLL2 registers */ 142 {OV13858_REG_PLL2_CTRL_B, 0x05}, 143 {OV13858_REG_PLL2_CTRL_C, 0x01}, 144 {OV13858_REG_PLL2_CTRL_D, 0x0e}, 145 {OV13858_REG_PLL2_CTRL_E, 0x05}, 146 {OV13858_REG_PLL2_CTRL_F, 0x01}, 147 {OV13858_REG_PLL2_CTRL_12, 0x01}, 148 {OV13858_REG_MIPI_SC_CTRL0, 0x72}, 149 {OV13858_REG_MIPI_SC_CTRL1, 0x01}, 150 }; 151 152 /* 153 * 2112x1568, 2112x1188, 1056x784 need 540Mbps/lane, 154 * 4 lanes 155 */ 156 static const struct ov13858_reg mipi_data_rate_540mbps[] = { 157 /* PLL1 registers */ 158 {OV13858_REG_PLL1_CTRL_0, 0x07}, 159 {OV13858_REG_PLL1_CTRL_1, 0x01}, 160 {OV13858_REG_PLL1_CTRL_2, 0xc2}, 161 {OV13858_REG_PLL1_CTRL_3, 0x01}, 162 {OV13858_REG_PLL1_CTRL_4, 0x00}, 163 {OV13858_REG_PLL1_CTRL_5, 0x01}, 164 165 /* PLL2 registers */ 166 {OV13858_REG_PLL2_CTRL_B, 0x05}, 167 {OV13858_REG_PLL2_CTRL_C, 0x01}, 168 {OV13858_REG_PLL2_CTRL_D, 0x0e}, 169 {OV13858_REG_PLL2_CTRL_E, 0x05}, 170 {OV13858_REG_PLL2_CTRL_F, 0x01}, 171 {OV13858_REG_PLL2_CTRL_12, 0x01}, 172 {OV13858_REG_MIPI_SC_CTRL0, 0x72}, 173 {OV13858_REG_MIPI_SC_CTRL1, 0x01}, 174 }; 175 176 static const struct ov13858_reg mode_4224x3136_regs[] = { 177 {0x3013, 0x32}, 178 {0x301b, 0xf0}, 179 {0x301f, 0xd0}, 180 {0x3106, 0x15}, 181 {0x3107, 0x23}, 182 {0x350a, 0x00}, 183 {0x350e, 0x00}, 184 {0x3510, 0x00}, 185 {0x3511, 0x02}, 186 {0x3512, 0x00}, 187 {0x3600, 0x2b}, 188 {0x3601, 0x52}, 189 {0x3602, 0x60}, 190 {0x3612, 0x05}, 191 {0x3613, 0xa4}, 192 {0x3620, 0x80}, 193 {0x3621, 0x10}, 194 {0x3622, 0x30}, 195 {0x3624, 0x1c}, 196 {0x3640, 0x10}, 197 {0x3641, 0x70}, 198 {0x3661, 0x80}, 199 {0x3662, 0x12}, 200 {0x3664, 0x73}, 201 {0x3665, 0xa7}, 202 {0x366e, 0xff}, 203 {0x366f, 0xf4}, 204 {0x3674, 0x00}, 205 {0x3679, 0x0c}, 206 {0x367f, 0x01}, 207 {0x3680, 0x0c}, 208 {0x3681, 0x50}, 209 {0x3682, 0x50}, 210 {0x3683, 0xa9}, 211 {0x3684, 0xa9}, 212 {0x3709, 0x5f}, 213 {0x3714, 0x24}, 214 {0x371a, 0x3e}, 215 {0x3737, 0x04}, 216 {0x3738, 0xcc}, 217 {0x3739, 0x12}, 218 {0x373d, 0x26}, 219 {0x3764, 0x20}, 220 {0x3765, 0x20}, 221 {0x37a1, 0x36}, 222 {0x37a8, 0x3b}, 223 {0x37ab, 0x31}, 224 {0x37c2, 0x04}, 225 {0x37c3, 0xf1}, 226 {0x37c5, 0x00}, 227 {0x37d8, 0x03}, 228 {0x37d9, 0x0c}, 229 {0x37da, 0xc2}, 230 {0x37dc, 0x02}, 231 {0x37e0, 0x00}, 232 {0x37e1, 0x0a}, 233 {0x37e2, 0x14}, 234 {0x37e3, 0x04}, 235 {0x37e4, 0x2a}, 236 {0x37e5, 0x03}, 237 {0x37e6, 0x04}, 238 {0x3800, 0x00}, 239 {0x3801, 0x00}, 240 {0x3802, 0x00}, 241 {0x3803, 0x00}, 242 {0x3804, 0x10}, 243 {0x3805, 0x9f}, 244 {0x3806, 0x0c}, 245 {0x3807, 0x5f}, 246 {0x3808, 0x10}, 247 {0x3809, 0x80}, 248 {0x380a, 0x0c}, 249 {0x380b, 0x40}, 250 {0x380c, 0x04}, 251 {0x380d, 0x62}, 252 {0x380e, 0x0c}, 253 {0x380f, 0x8e}, 254 {0x3811, 0x04}, 255 {0x3813, 0x05}, 256 {0x3814, 0x01}, 257 {0x3815, 0x01}, 258 {0x3816, 0x01}, 259 {0x3817, 0x01}, 260 {0x3820, 0xa8}, 261 {0x3821, 0x00}, 262 {0x3822, 0xc2}, 263 {0x3823, 0x18}, 264 {0x3826, 0x11}, 265 {0x3827, 0x1c}, 266 {0x3829, 0x03}, 267 {0x3832, 0x00}, 268 {0x3c80, 0x00}, 269 {0x3c87, 0x01}, 270 {0x3c8c, 0x19}, 271 {0x3c8d, 0x1c}, 272 {0x3c90, 0x00}, 273 {0x3c91, 0x00}, 274 {0x3c92, 0x00}, 275 {0x3c93, 0x00}, 276 {0x3c94, 0x40}, 277 {0x3c95, 0x54}, 278 {0x3c96, 0x34}, 279 {0x3c97, 0x04}, 280 {0x3c98, 0x00}, 281 {0x3d8c, 0x73}, 282 {0x3d8d, 0xc0}, 283 {0x3f00, 0x0b}, 284 {0x3f03, 0x00}, 285 {0x4001, 0xe0}, 286 {0x4008, 0x00}, 287 {0x4009, 0x0f}, 288 {0x4011, 0xf0}, 289 {0x4017, 0x08}, 290 {0x4050, 0x04}, 291 {0x4051, 0x0b}, 292 {0x4052, 0x00}, 293 {0x4053, 0x80}, 294 {0x4054, 0x00}, 295 {0x4055, 0x80}, 296 {0x4056, 0x00}, 297 {0x4057, 0x80}, 298 {0x4058, 0x00}, 299 {0x4059, 0x80}, 300 {0x405e, 0x20}, 301 {0x4500, 0x07}, 302 {0x4503, 0x00}, 303 {0x450a, 0x04}, 304 {0x4809, 0x04}, 305 {0x480c, 0x12}, 306 {0x481f, 0x30}, 307 {0x4833, 0x10}, 308 {0x4837, 0x0e}, 309 {0x4902, 0x01}, 310 {0x4d00, 0x03}, 311 {0x4d01, 0xc9}, 312 {0x4d02, 0xbc}, 313 {0x4d03, 0xd7}, 314 {0x4d04, 0xf0}, 315 {0x4d05, 0xa2}, 316 {0x5000, 0xfd}, 317 {0x5001, 0x01}, 318 {0x5040, 0x39}, 319 {0x5041, 0x10}, 320 {0x5042, 0x10}, 321 {0x5043, 0x84}, 322 {0x5044, 0x62}, 323 {0x5180, 0x00}, 324 {0x5181, 0x10}, 325 {0x5182, 0x02}, 326 {0x5183, 0x0f}, 327 {0x5200, 0x1b}, 328 {0x520b, 0x07}, 329 {0x520c, 0x0f}, 330 {0x5300, 0x04}, 331 {0x5301, 0x0c}, 332 {0x5302, 0x0c}, 333 {0x5303, 0x0f}, 334 {0x5304, 0x00}, 335 {0x5305, 0x70}, 336 {0x5306, 0x00}, 337 {0x5307, 0x80}, 338 {0x5308, 0x00}, 339 {0x5309, 0xa5}, 340 {0x530a, 0x00}, 341 {0x530b, 0xd3}, 342 {0x530c, 0x00}, 343 {0x530d, 0xf0}, 344 {0x530e, 0x01}, 345 {0x530f, 0x10}, 346 {0x5310, 0x01}, 347 {0x5311, 0x20}, 348 {0x5312, 0x01}, 349 {0x5313, 0x20}, 350 {0x5314, 0x01}, 351 {0x5315, 0x20}, 352 {0x5316, 0x08}, 353 {0x5317, 0x08}, 354 {0x5318, 0x10}, 355 {0x5319, 0x88}, 356 {0x531a, 0x88}, 357 {0x531b, 0xa9}, 358 {0x531c, 0xaa}, 359 {0x531d, 0x0a}, 360 {0x5405, 0x02}, 361 {0x5406, 0x67}, 362 {0x5407, 0x01}, 363 {0x5408, 0x4a}, 364 }; 365 366 static const struct ov13858_reg mode_2112x1568_regs[] = { 367 {0x3013, 0x32}, 368 {0x301b, 0xf0}, 369 {0x301f, 0xd0}, 370 {0x3106, 0x15}, 371 {0x3107, 0x23}, 372 {0x350a, 0x00}, 373 {0x350e, 0x00}, 374 {0x3510, 0x00}, 375 {0x3511, 0x02}, 376 {0x3512, 0x00}, 377 {0x3600, 0x2b}, 378 {0x3601, 0x52}, 379 {0x3602, 0x60}, 380 {0x3612, 0x05}, 381 {0x3613, 0xa4}, 382 {0x3620, 0x80}, 383 {0x3621, 0x10}, 384 {0x3622, 0x30}, 385 {0x3624, 0x1c}, 386 {0x3640, 0x10}, 387 {0x3641, 0x70}, 388 {0x3661, 0x80}, 389 {0x3662, 0x10}, 390 {0x3664, 0x73}, 391 {0x3665, 0xa7}, 392 {0x366e, 0xff}, 393 {0x366f, 0xf4}, 394 {0x3674, 0x00}, 395 {0x3679, 0x0c}, 396 {0x367f, 0x01}, 397 {0x3680, 0x0c}, 398 {0x3681, 0x50}, 399 {0x3682, 0x50}, 400 {0x3683, 0xa9}, 401 {0x3684, 0xa9}, 402 {0x3709, 0x5f}, 403 {0x3714, 0x28}, 404 {0x371a, 0x3e}, 405 {0x3737, 0x08}, 406 {0x3738, 0xcc}, 407 {0x3739, 0x20}, 408 {0x373d, 0x26}, 409 {0x3764, 0x20}, 410 {0x3765, 0x20}, 411 {0x37a1, 0x36}, 412 {0x37a8, 0x3b}, 413 {0x37ab, 0x31}, 414 {0x37c2, 0x14}, 415 {0x37c3, 0xf1}, 416 {0x37c5, 0x00}, 417 {0x37d8, 0x03}, 418 {0x37d9, 0x0c}, 419 {0x37da, 0xc2}, 420 {0x37dc, 0x02}, 421 {0x37e0, 0x00}, 422 {0x37e1, 0x0a}, 423 {0x37e2, 0x14}, 424 {0x37e3, 0x08}, 425 {0x37e4, 0x38}, 426 {0x37e5, 0x03}, 427 {0x37e6, 0x08}, 428 {0x3800, 0x00}, 429 {0x3801, 0x00}, 430 {0x3802, 0x00}, 431 {0x3803, 0x00}, 432 {0x3804, 0x10}, 433 {0x3805, 0x9f}, 434 {0x3806, 0x0c}, 435 {0x3807, 0x5f}, 436 {0x3808, 0x08}, 437 {0x3809, 0x40}, 438 {0x380a, 0x06}, 439 {0x380b, 0x20}, 440 {0x380c, 0x04}, 441 {0x380d, 0x62}, 442 {0x380e, 0x0c}, 443 {0x380f, 0x8e}, 444 {0x3811, 0x04}, 445 {0x3813, 0x05}, 446 {0x3814, 0x03}, 447 {0x3815, 0x01}, 448 {0x3816, 0x03}, 449 {0x3817, 0x01}, 450 {0x3820, 0xab}, 451 {0x3821, 0x00}, 452 {0x3822, 0xc2}, 453 {0x3823, 0x18}, 454 {0x3826, 0x04}, 455 {0x3827, 0x90}, 456 {0x3829, 0x07}, 457 {0x3832, 0x00}, 458 {0x3c80, 0x00}, 459 {0x3c87, 0x01}, 460 {0x3c8c, 0x19}, 461 {0x3c8d, 0x1c}, 462 {0x3c90, 0x00}, 463 {0x3c91, 0x00}, 464 {0x3c92, 0x00}, 465 {0x3c93, 0x00}, 466 {0x3c94, 0x40}, 467 {0x3c95, 0x54}, 468 {0x3c96, 0x34}, 469 {0x3c97, 0x04}, 470 {0x3c98, 0x00}, 471 {0x3d8c, 0x73}, 472 {0x3d8d, 0xc0}, 473 {0x3f00, 0x0b}, 474 {0x3f03, 0x00}, 475 {0x4001, 0xe0}, 476 {0x4008, 0x00}, 477 {0x4009, 0x0d}, 478 {0x4011, 0xf0}, 479 {0x4017, 0x08}, 480 {0x4050, 0x04}, 481 {0x4051, 0x0b}, 482 {0x4052, 0x00}, 483 {0x4053, 0x80}, 484 {0x4054, 0x00}, 485 {0x4055, 0x80}, 486 {0x4056, 0x00}, 487 {0x4057, 0x80}, 488 {0x4058, 0x00}, 489 {0x4059, 0x80}, 490 {0x405e, 0x20}, 491 {0x4500, 0x07}, 492 {0x4503, 0x00}, 493 {0x450a, 0x04}, 494 {0x4809, 0x04}, 495 {0x480c, 0x12}, 496 {0x481f, 0x30}, 497 {0x4833, 0x10}, 498 {0x4837, 0x1c}, 499 {0x4902, 0x01}, 500 {0x4d00, 0x03}, 501 {0x4d01, 0xc9}, 502 {0x4d02, 0xbc}, 503 {0x4d03, 0xd7}, 504 {0x4d04, 0xf0}, 505 {0x4d05, 0xa2}, 506 {0x5000, 0xfd}, 507 {0x5001, 0x01}, 508 {0x5040, 0x39}, 509 {0x5041, 0x10}, 510 {0x5042, 0x10}, 511 {0x5043, 0x84}, 512 {0x5044, 0x62}, 513 {0x5180, 0x00}, 514 {0x5181, 0x10}, 515 {0x5182, 0x02}, 516 {0x5183, 0x0f}, 517 {0x5200, 0x1b}, 518 {0x520b, 0x07}, 519 {0x520c, 0x0f}, 520 {0x5300, 0x04}, 521 {0x5301, 0x0c}, 522 {0x5302, 0x0c}, 523 {0x5303, 0x0f}, 524 {0x5304, 0x00}, 525 {0x5305, 0x70}, 526 {0x5306, 0x00}, 527 {0x5307, 0x80}, 528 {0x5308, 0x00}, 529 {0x5309, 0xa5}, 530 {0x530a, 0x00}, 531 {0x530b, 0xd3}, 532 {0x530c, 0x00}, 533 {0x530d, 0xf0}, 534 {0x530e, 0x01}, 535 {0x530f, 0x10}, 536 {0x5310, 0x01}, 537 {0x5311, 0x20}, 538 {0x5312, 0x01}, 539 {0x5313, 0x20}, 540 {0x5314, 0x01}, 541 {0x5315, 0x20}, 542 {0x5316, 0x08}, 543 {0x5317, 0x08}, 544 {0x5318, 0x10}, 545 {0x5319, 0x88}, 546 {0x531a, 0x88}, 547 {0x531b, 0xa9}, 548 {0x531c, 0xaa}, 549 {0x531d, 0x0a}, 550 {0x5405, 0x02}, 551 {0x5406, 0x67}, 552 {0x5407, 0x01}, 553 {0x5408, 0x4a}, 554 }; 555 556 static const struct ov13858_reg mode_2112x1188_regs[] = { 557 {0x3013, 0x32}, 558 {0x301b, 0xf0}, 559 {0x301f, 0xd0}, 560 {0x3106, 0x15}, 561 {0x3107, 0x23}, 562 {0x350a, 0x00}, 563 {0x350e, 0x00}, 564 {0x3510, 0x00}, 565 {0x3511, 0x02}, 566 {0x3512, 0x00}, 567 {0x3600, 0x2b}, 568 {0x3601, 0x52}, 569 {0x3602, 0x60}, 570 {0x3612, 0x05}, 571 {0x3613, 0xa4}, 572 {0x3620, 0x80}, 573 {0x3621, 0x10}, 574 {0x3622, 0x30}, 575 {0x3624, 0x1c}, 576 {0x3640, 0x10}, 577 {0x3641, 0x70}, 578 {0x3661, 0x80}, 579 {0x3662, 0x10}, 580 {0x3664, 0x73}, 581 {0x3665, 0xa7}, 582 {0x366e, 0xff}, 583 {0x366f, 0xf4}, 584 {0x3674, 0x00}, 585 {0x3679, 0x0c}, 586 {0x367f, 0x01}, 587 {0x3680, 0x0c}, 588 {0x3681, 0x50}, 589 {0x3682, 0x50}, 590 {0x3683, 0xa9}, 591 {0x3684, 0xa9}, 592 {0x3709, 0x5f}, 593 {0x3714, 0x28}, 594 {0x371a, 0x3e}, 595 {0x3737, 0x08}, 596 {0x3738, 0xcc}, 597 {0x3739, 0x20}, 598 {0x373d, 0x26}, 599 {0x3764, 0x20}, 600 {0x3765, 0x20}, 601 {0x37a1, 0x36}, 602 {0x37a8, 0x3b}, 603 {0x37ab, 0x31}, 604 {0x37c2, 0x14}, 605 {0x37c3, 0xf1}, 606 {0x37c5, 0x00}, 607 {0x37d8, 0x03}, 608 {0x37d9, 0x0c}, 609 {0x37da, 0xc2}, 610 {0x37dc, 0x02}, 611 {0x37e0, 0x00}, 612 {0x37e1, 0x0a}, 613 {0x37e2, 0x14}, 614 {0x37e3, 0x08}, 615 {0x37e4, 0x38}, 616 {0x37e5, 0x03}, 617 {0x37e6, 0x08}, 618 {0x3800, 0x00}, 619 {0x3801, 0x00}, 620 {0x3802, 0x01}, 621 {0x3803, 0x84}, 622 {0x3804, 0x10}, 623 {0x3805, 0x9f}, 624 {0x3806, 0x0a}, 625 {0x3807, 0xd3}, 626 {0x3808, 0x08}, 627 {0x3809, 0x40}, 628 {0x380a, 0x04}, 629 {0x380b, 0xa4}, 630 {0x380c, 0x04}, 631 {0x380d, 0x62}, 632 {0x380e, 0x0c}, 633 {0x380f, 0x8e}, 634 {0x3811, 0x08}, 635 {0x3813, 0x03}, 636 {0x3814, 0x03}, 637 {0x3815, 0x01}, 638 {0x3816, 0x03}, 639 {0x3817, 0x01}, 640 {0x3820, 0xab}, 641 {0x3821, 0x00}, 642 {0x3822, 0xc2}, 643 {0x3823, 0x18}, 644 {0x3826, 0x04}, 645 {0x3827, 0x90}, 646 {0x3829, 0x07}, 647 {0x3832, 0x00}, 648 {0x3c80, 0x00}, 649 {0x3c87, 0x01}, 650 {0x3c8c, 0x19}, 651 {0x3c8d, 0x1c}, 652 {0x3c90, 0x00}, 653 {0x3c91, 0x00}, 654 {0x3c92, 0x00}, 655 {0x3c93, 0x00}, 656 {0x3c94, 0x40}, 657 {0x3c95, 0x54}, 658 {0x3c96, 0x34}, 659 {0x3c97, 0x04}, 660 {0x3c98, 0x00}, 661 {0x3d8c, 0x73}, 662 {0x3d8d, 0xc0}, 663 {0x3f00, 0x0b}, 664 {0x3f03, 0x00}, 665 {0x4001, 0xe0}, 666 {0x4008, 0x00}, 667 {0x4009, 0x0d}, 668 {0x4011, 0xf0}, 669 {0x4017, 0x08}, 670 {0x4050, 0x04}, 671 {0x4051, 0x0b}, 672 {0x4052, 0x00}, 673 {0x4053, 0x80}, 674 {0x4054, 0x00}, 675 {0x4055, 0x80}, 676 {0x4056, 0x00}, 677 {0x4057, 0x80}, 678 {0x4058, 0x00}, 679 {0x4059, 0x80}, 680 {0x405e, 0x20}, 681 {0x4500, 0x07}, 682 {0x4503, 0x00}, 683 {0x450a, 0x04}, 684 {0x4809, 0x04}, 685 {0x480c, 0x12}, 686 {0x481f, 0x30}, 687 {0x4833, 0x10}, 688 {0x4837, 0x1c}, 689 {0x4902, 0x01}, 690 {0x4d00, 0x03}, 691 {0x4d01, 0xc9}, 692 {0x4d02, 0xbc}, 693 {0x4d03, 0xd7}, 694 {0x4d04, 0xf0}, 695 {0x4d05, 0xa2}, 696 {0x5000, 0xfd}, 697 {0x5001, 0x01}, 698 {0x5040, 0x39}, 699 {0x5041, 0x10}, 700 {0x5042, 0x10}, 701 {0x5043, 0x84}, 702 {0x5044, 0x62}, 703 {0x5180, 0x00}, 704 {0x5181, 0x10}, 705 {0x5182, 0x02}, 706 {0x5183, 0x0f}, 707 {0x5200, 0x1b}, 708 {0x520b, 0x07}, 709 {0x520c, 0x0f}, 710 {0x5300, 0x04}, 711 {0x5301, 0x0c}, 712 {0x5302, 0x0c}, 713 {0x5303, 0x0f}, 714 {0x5304, 0x00}, 715 {0x5305, 0x70}, 716 {0x5306, 0x00}, 717 {0x5307, 0x80}, 718 {0x5308, 0x00}, 719 {0x5309, 0xa5}, 720 {0x530a, 0x00}, 721 {0x530b, 0xd3}, 722 {0x530c, 0x00}, 723 {0x530d, 0xf0}, 724 {0x530e, 0x01}, 725 {0x530f, 0x10}, 726 {0x5310, 0x01}, 727 {0x5311, 0x20}, 728 {0x5312, 0x01}, 729 {0x5313, 0x20}, 730 {0x5314, 0x01}, 731 {0x5315, 0x20}, 732 {0x5316, 0x08}, 733 {0x5317, 0x08}, 734 {0x5318, 0x10}, 735 {0x5319, 0x88}, 736 {0x531a, 0x88}, 737 {0x531b, 0xa9}, 738 {0x531c, 0xaa}, 739 {0x531d, 0x0a}, 740 {0x5405, 0x02}, 741 {0x5406, 0x67}, 742 {0x5407, 0x01}, 743 {0x5408, 0x4a}, 744 }; 745 746 static const struct ov13858_reg mode_1056x784_regs[] = { 747 {0x3013, 0x32}, 748 {0x301b, 0xf0}, 749 {0x301f, 0xd0}, 750 {0x3106, 0x15}, 751 {0x3107, 0x23}, 752 {0x350a, 0x00}, 753 {0x350e, 0x00}, 754 {0x3510, 0x00}, 755 {0x3511, 0x02}, 756 {0x3512, 0x00}, 757 {0x3600, 0x2b}, 758 {0x3601, 0x52}, 759 {0x3602, 0x60}, 760 {0x3612, 0x05}, 761 {0x3613, 0xa4}, 762 {0x3620, 0x80}, 763 {0x3621, 0x10}, 764 {0x3622, 0x30}, 765 {0x3624, 0x1c}, 766 {0x3640, 0x10}, 767 {0x3641, 0x70}, 768 {0x3661, 0x80}, 769 {0x3662, 0x08}, 770 {0x3664, 0x73}, 771 {0x3665, 0xa7}, 772 {0x366e, 0xff}, 773 {0x366f, 0xf4}, 774 {0x3674, 0x00}, 775 {0x3679, 0x0c}, 776 {0x367f, 0x01}, 777 {0x3680, 0x0c}, 778 {0x3681, 0x50}, 779 {0x3682, 0x50}, 780 {0x3683, 0xa9}, 781 {0x3684, 0xa9}, 782 {0x3709, 0x5f}, 783 {0x3714, 0x30}, 784 {0x371a, 0x3e}, 785 {0x3737, 0x08}, 786 {0x3738, 0xcc}, 787 {0x3739, 0x20}, 788 {0x373d, 0x26}, 789 {0x3764, 0x20}, 790 {0x3765, 0x20}, 791 {0x37a1, 0x36}, 792 {0x37a8, 0x3b}, 793 {0x37ab, 0x31}, 794 {0x37c2, 0x2c}, 795 {0x37c3, 0xf1}, 796 {0x37c5, 0x00}, 797 {0x37d8, 0x03}, 798 {0x37d9, 0x06}, 799 {0x37da, 0xc2}, 800 {0x37dc, 0x02}, 801 {0x37e0, 0x00}, 802 {0x37e1, 0x0a}, 803 {0x37e2, 0x14}, 804 {0x37e3, 0x08}, 805 {0x37e4, 0x36}, 806 {0x37e5, 0x03}, 807 {0x37e6, 0x08}, 808 {0x3800, 0x00}, 809 {0x3801, 0x00}, 810 {0x3802, 0x00}, 811 {0x3803, 0x00}, 812 {0x3804, 0x10}, 813 {0x3805, 0x9f}, 814 {0x3806, 0x0c}, 815 {0x3807, 0x5f}, 816 {0x3808, 0x04}, 817 {0x3809, 0x20}, 818 {0x380a, 0x03}, 819 {0x380b, 0x10}, 820 {0x380c, 0x04}, 821 {0x380d, 0x62}, 822 {0x380e, 0x0c}, 823 {0x380f, 0x8e}, 824 {0x3811, 0x04}, 825 {0x3813, 0x05}, 826 {0x3814, 0x07}, 827 {0x3815, 0x01}, 828 {0x3816, 0x07}, 829 {0x3817, 0x01}, 830 {0x3820, 0xac}, 831 {0x3821, 0x00}, 832 {0x3822, 0xc2}, 833 {0x3823, 0x18}, 834 {0x3826, 0x04}, 835 {0x3827, 0x48}, 836 {0x3829, 0x03}, 837 {0x3832, 0x00}, 838 {0x3c80, 0x00}, 839 {0x3c87, 0x01}, 840 {0x3c8c, 0x19}, 841 {0x3c8d, 0x1c}, 842 {0x3c90, 0x00}, 843 {0x3c91, 0x00}, 844 {0x3c92, 0x00}, 845 {0x3c93, 0x00}, 846 {0x3c94, 0x40}, 847 {0x3c95, 0x54}, 848 {0x3c96, 0x34}, 849 {0x3c97, 0x04}, 850 {0x3c98, 0x00}, 851 {0x3d8c, 0x73}, 852 {0x3d8d, 0xc0}, 853 {0x3f00, 0x0b}, 854 {0x3f03, 0x00}, 855 {0x4001, 0xe0}, 856 {0x4008, 0x00}, 857 {0x4009, 0x05}, 858 {0x4011, 0xf0}, 859 {0x4017, 0x08}, 860 {0x4050, 0x02}, 861 {0x4051, 0x05}, 862 {0x4052, 0x00}, 863 {0x4053, 0x80}, 864 {0x4054, 0x00}, 865 {0x4055, 0x80}, 866 {0x4056, 0x00}, 867 {0x4057, 0x80}, 868 {0x4058, 0x00}, 869 {0x4059, 0x80}, 870 {0x405e, 0x20}, 871 {0x4500, 0x07}, 872 {0x4503, 0x00}, 873 {0x450a, 0x04}, 874 {0x4809, 0x04}, 875 {0x480c, 0x12}, 876 {0x481f, 0x30}, 877 {0x4833, 0x10}, 878 {0x4837, 0x1e}, 879 {0x4902, 0x02}, 880 {0x4d00, 0x03}, 881 {0x4d01, 0xc9}, 882 {0x4d02, 0xbc}, 883 {0x4d03, 0xd7}, 884 {0x4d04, 0xf0}, 885 {0x4d05, 0xa2}, 886 {0x5000, 0xfd}, 887 {0x5001, 0x01}, 888 {0x5040, 0x39}, 889 {0x5041, 0x10}, 890 {0x5042, 0x10}, 891 {0x5043, 0x84}, 892 {0x5044, 0x62}, 893 {0x5180, 0x00}, 894 {0x5181, 0x10}, 895 {0x5182, 0x02}, 896 {0x5183, 0x0f}, 897 {0x5200, 0x1b}, 898 {0x520b, 0x07}, 899 {0x520c, 0x0f}, 900 {0x5300, 0x04}, 901 {0x5301, 0x0c}, 902 {0x5302, 0x0c}, 903 {0x5303, 0x0f}, 904 {0x5304, 0x00}, 905 {0x5305, 0x70}, 906 {0x5306, 0x00}, 907 {0x5307, 0x80}, 908 {0x5308, 0x00}, 909 {0x5309, 0xa5}, 910 {0x530a, 0x00}, 911 {0x530b, 0xd3}, 912 {0x530c, 0x00}, 913 {0x530d, 0xf0}, 914 {0x530e, 0x01}, 915 {0x530f, 0x10}, 916 {0x5310, 0x01}, 917 {0x5311, 0x20}, 918 {0x5312, 0x01}, 919 {0x5313, 0x20}, 920 {0x5314, 0x01}, 921 {0x5315, 0x20}, 922 {0x5316, 0x08}, 923 {0x5317, 0x08}, 924 {0x5318, 0x10}, 925 {0x5319, 0x88}, 926 {0x531a, 0x88}, 927 {0x531b, 0xa9}, 928 {0x531c, 0xaa}, 929 {0x531d, 0x0a}, 930 {0x5405, 0x02}, 931 {0x5406, 0x67}, 932 {0x5407, 0x01}, 933 {0x5408, 0x4a}, 934 }; 935 936 static const char * const ov13858_test_pattern_menu[] = { 937 "Disabled", 938 "Vertical Color Bar Type 1", 939 "Vertical Color Bar Type 2", 940 "Vertical Color Bar Type 3", 941 "Vertical Color Bar Type 4" 942 }; 943 944 /* Configurations for supported link frequencies */ 945 #define OV13858_NUM_OF_LINK_FREQS 2 946 #define OV13858_LINK_FREQ_540MHZ 540000000ULL 947 #define OV13858_LINK_FREQ_270MHZ 270000000ULL 948 #define OV13858_LINK_FREQ_INDEX_0 0 949 #define OV13858_LINK_FREQ_INDEX_1 1 950 951 /* Menu items for LINK_FREQ V4L2 control */ 952 static const s64 link_freq_menu_items[OV13858_NUM_OF_LINK_FREQS] = { 953 OV13858_LINK_FREQ_540MHZ, 954 OV13858_LINK_FREQ_270MHZ 955 }; 956 957 /* Link frequency configs */ 958 static const struct ov13858_link_freq_config 959 link_freq_configs[OV13858_NUM_OF_LINK_FREQS] = { 960 { 961 /* pixel_rate = link_freq * 2 * nr_of_lanes / bits_per_sample */ 962 .pixel_rate = (OV13858_LINK_FREQ_540MHZ * 2 * 4) / 10, 963 .pixels_per_line = OV13858_PPL_540MHZ, 964 .reg_list = { 965 .num_of_regs = ARRAY_SIZE(mipi_data_rate_1080mbps), 966 .regs = mipi_data_rate_1080mbps, 967 } 968 }, 969 { 970 /* pixel_rate = link_freq * 2 * nr_of_lanes / bits_per_sample */ 971 .pixel_rate = (OV13858_LINK_FREQ_270MHZ * 2 * 4) / 10, 972 .pixels_per_line = OV13858_PPL_270MHZ, 973 .reg_list = { 974 .num_of_regs = ARRAY_SIZE(mipi_data_rate_540mbps), 975 .regs = mipi_data_rate_540mbps, 976 } 977 } 978 }; 979 980 /* Mode configs */ 981 static const struct ov13858_mode supported_modes[] = { 982 { 983 .width = 4224, 984 .height = 3136, 985 .vts_def = OV13858_VTS_30FPS, 986 .vts_min = OV13858_VTS_30FPS, 987 .reg_list = { 988 .num_of_regs = ARRAY_SIZE(mode_4224x3136_regs), 989 .regs = mode_4224x3136_regs, 990 }, 991 .link_freq_index = OV13858_LINK_FREQ_INDEX_0, 992 }, 993 { 994 .width = 2112, 995 .height = 1568, 996 .vts_def = OV13858_VTS_30FPS, 997 .vts_min = 1608, 998 .reg_list = { 999 .num_of_regs = ARRAY_SIZE(mode_2112x1568_regs), 1000 .regs = mode_2112x1568_regs, 1001 }, 1002 .link_freq_index = OV13858_LINK_FREQ_INDEX_1, 1003 }, 1004 { 1005 .width = 2112, 1006 .height = 1188, 1007 .vts_def = OV13858_VTS_30FPS, 1008 .vts_min = 1608, 1009 .reg_list = { 1010 .num_of_regs = ARRAY_SIZE(mode_2112x1188_regs), 1011 .regs = mode_2112x1188_regs, 1012 }, 1013 .link_freq_index = OV13858_LINK_FREQ_INDEX_1, 1014 }, 1015 { 1016 .width = 1056, 1017 .height = 784, 1018 .vts_def = OV13858_VTS_30FPS, 1019 .vts_min = 804, 1020 .reg_list = { 1021 .num_of_regs = ARRAY_SIZE(mode_1056x784_regs), 1022 .regs = mode_1056x784_regs, 1023 }, 1024 .link_freq_index = OV13858_LINK_FREQ_INDEX_1, 1025 } 1026 }; 1027 1028 struct ov13858 { 1029 struct v4l2_subdev sd; 1030 struct media_pad pad; 1031 1032 struct v4l2_ctrl_handler ctrl_handler; 1033 /* V4L2 Controls */ 1034 struct v4l2_ctrl *link_freq; 1035 struct v4l2_ctrl *pixel_rate; 1036 struct v4l2_ctrl *vblank; 1037 struct v4l2_ctrl *hblank; 1038 struct v4l2_ctrl *exposure; 1039 1040 /* Current mode */ 1041 const struct ov13858_mode *cur_mode; 1042 1043 /* Mutex for serialized access */ 1044 struct mutex mutex; 1045 1046 /* Streaming on/off */ 1047 bool streaming; 1048 }; 1049 1050 #define to_ov13858(_sd) container_of(_sd, struct ov13858, sd) 1051 1052 /* Read registers up to 4 at a time */ 1053 static int ov13858_read_reg(struct ov13858 *ov13858, u16 reg, u32 len, u32 *val) 1054 { 1055 struct i2c_client *client = v4l2_get_subdevdata(&ov13858->sd); 1056 struct i2c_msg msgs[2]; 1057 u8 *data_be_p; 1058 int ret; 1059 u32 data_be = 0; 1060 u16 reg_addr_be = cpu_to_be16(reg); 1061 1062 if (len > 4) 1063 return -EINVAL; 1064 1065 data_be_p = (u8 *)&data_be; 1066 /* Write register address */ 1067 msgs[0].addr = client->addr; 1068 msgs[0].flags = 0; 1069 msgs[0].len = 2; 1070 msgs[0].buf = (u8 *)®_addr_be; 1071 1072 /* Read data from register */ 1073 msgs[1].addr = client->addr; 1074 msgs[1].flags = I2C_M_RD; 1075 msgs[1].len = len; 1076 msgs[1].buf = &data_be_p[4 - len]; 1077 1078 ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs)); 1079 if (ret != ARRAY_SIZE(msgs)) 1080 return -EIO; 1081 1082 *val = be32_to_cpu(data_be); 1083 1084 return 0; 1085 } 1086 1087 /* Write registers up to 4 at a time */ 1088 static int ov13858_write_reg(struct ov13858 *ov13858, u16 reg, u32 len, u32 val) 1089 { 1090 struct i2c_client *client = v4l2_get_subdevdata(&ov13858->sd); 1091 int buf_i, val_i; 1092 u8 buf[6], *val_p; 1093 1094 if (len > 4) 1095 return -EINVAL; 1096 1097 buf[0] = reg >> 8; 1098 buf[1] = reg & 0xff; 1099 1100 val = cpu_to_be32(val); 1101 val_p = (u8 *)&val; 1102 buf_i = 2; 1103 val_i = 4 - len; 1104 1105 while (val_i < 4) 1106 buf[buf_i++] = val_p[val_i++]; 1107 1108 if (i2c_master_send(client, buf, len + 2) != len + 2) 1109 return -EIO; 1110 1111 return 0; 1112 } 1113 1114 /* Write a list of registers */ 1115 static int ov13858_write_regs(struct ov13858 *ov13858, 1116 const struct ov13858_reg *regs, u32 len) 1117 { 1118 struct i2c_client *client = v4l2_get_subdevdata(&ov13858->sd); 1119 int ret; 1120 u32 i; 1121 1122 for (i = 0; i < len; i++) { 1123 ret = ov13858_write_reg(ov13858, regs[i].address, 1, 1124 regs[i].val); 1125 if (ret) { 1126 dev_err_ratelimited( 1127 &client->dev, 1128 "Failed to write reg 0x%4.4x. error = %d\n", 1129 regs[i].address, ret); 1130 1131 return ret; 1132 } 1133 } 1134 1135 return 0; 1136 } 1137 1138 static int ov13858_write_reg_list(struct ov13858 *ov13858, 1139 const struct ov13858_reg_list *r_list) 1140 { 1141 return ov13858_write_regs(ov13858, r_list->regs, r_list->num_of_regs); 1142 } 1143 1144 /* Open sub-device */ 1145 static int ov13858_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh) 1146 { 1147 struct ov13858 *ov13858 = to_ov13858(sd); 1148 struct v4l2_mbus_framefmt *try_fmt = v4l2_subdev_get_try_format(sd, 1149 fh->pad, 1150 0); 1151 1152 mutex_lock(&ov13858->mutex); 1153 1154 /* Initialize try_fmt */ 1155 try_fmt->width = ov13858->cur_mode->width; 1156 try_fmt->height = ov13858->cur_mode->height; 1157 try_fmt->code = MEDIA_BUS_FMT_SGRBG10_1X10; 1158 try_fmt->field = V4L2_FIELD_NONE; 1159 1160 /* No crop or compose */ 1161 mutex_unlock(&ov13858->mutex); 1162 1163 return 0; 1164 } 1165 1166 static int ov13858_update_digital_gain(struct ov13858 *ov13858, u32 d_gain) 1167 { 1168 int ret; 1169 1170 ret = ov13858_write_reg(ov13858, OV13858_REG_B_MWB_GAIN, 1171 OV13858_REG_VALUE_16BIT, d_gain); 1172 if (ret) 1173 return ret; 1174 1175 ret = ov13858_write_reg(ov13858, OV13858_REG_G_MWB_GAIN, 1176 OV13858_REG_VALUE_16BIT, d_gain); 1177 if (ret) 1178 return ret; 1179 1180 ret = ov13858_write_reg(ov13858, OV13858_REG_R_MWB_GAIN, 1181 OV13858_REG_VALUE_16BIT, d_gain); 1182 1183 return ret; 1184 } 1185 1186 static int ov13858_enable_test_pattern(struct ov13858 *ov13858, u32 pattern) 1187 { 1188 int ret; 1189 u32 val; 1190 1191 ret = ov13858_read_reg(ov13858, OV13858_REG_TEST_PATTERN, 1192 OV13858_REG_VALUE_08BIT, &val); 1193 if (ret) 1194 return ret; 1195 1196 if (pattern) { 1197 val &= OV13858_TEST_PATTERN_MASK; 1198 val |= (pattern - 1) | OV13858_TEST_PATTERN_ENABLE; 1199 } else { 1200 val &= ~OV13858_TEST_PATTERN_ENABLE; 1201 } 1202 1203 return ov13858_write_reg(ov13858, OV13858_REG_TEST_PATTERN, 1204 OV13858_REG_VALUE_08BIT, val); 1205 } 1206 1207 static int ov13858_set_ctrl(struct v4l2_ctrl *ctrl) 1208 { 1209 struct ov13858 *ov13858 = container_of(ctrl->handler, 1210 struct ov13858, ctrl_handler); 1211 struct i2c_client *client = v4l2_get_subdevdata(&ov13858->sd); 1212 s64 max; 1213 int ret; 1214 1215 /* Propagate change of current control to all related controls */ 1216 switch (ctrl->id) { 1217 case V4L2_CID_VBLANK: 1218 /* Update max exposure while meeting expected vblanking */ 1219 max = ov13858->cur_mode->height + ctrl->val - 8; 1220 __v4l2_ctrl_modify_range(ov13858->exposure, 1221 ov13858->exposure->minimum, 1222 max, ov13858->exposure->step, max); 1223 break; 1224 }; 1225 1226 /* 1227 * Applying V4L2 control value only happens 1228 * when power is up for streaming 1229 */ 1230 if (pm_runtime_get_if_in_use(&client->dev) <= 0) 1231 return 0; 1232 1233 ret = 0; 1234 switch (ctrl->id) { 1235 case V4L2_CID_ANALOGUE_GAIN: 1236 ret = ov13858_write_reg(ov13858, OV13858_REG_ANALOG_GAIN, 1237 OV13858_REG_VALUE_16BIT, ctrl->val); 1238 break; 1239 case V4L2_CID_DIGITAL_GAIN: 1240 ret = ov13858_update_digital_gain(ov13858, ctrl->val); 1241 break; 1242 case V4L2_CID_EXPOSURE: 1243 ret = ov13858_write_reg(ov13858, OV13858_REG_EXPOSURE, 1244 OV13858_REG_VALUE_24BIT, 1245 ctrl->val << 4); 1246 break; 1247 case V4L2_CID_VBLANK: 1248 /* Update VTS that meets expected vertical blanking */ 1249 ret = ov13858_write_reg(ov13858, OV13858_REG_VTS, 1250 OV13858_REG_VALUE_16BIT, 1251 ov13858->cur_mode->height 1252 + ctrl->val); 1253 break; 1254 case V4L2_CID_TEST_PATTERN: 1255 ret = ov13858_enable_test_pattern(ov13858, ctrl->val); 1256 break; 1257 default: 1258 dev_info(&client->dev, 1259 "ctrl(id:0x%x,val:0x%x) is not handled\n", 1260 ctrl->id, ctrl->val); 1261 break; 1262 }; 1263 1264 pm_runtime_put(&client->dev); 1265 1266 return ret; 1267 } 1268 1269 static const struct v4l2_ctrl_ops ov13858_ctrl_ops = { 1270 .s_ctrl = ov13858_set_ctrl, 1271 }; 1272 1273 static int ov13858_enum_mbus_code(struct v4l2_subdev *sd, 1274 struct v4l2_subdev_pad_config *cfg, 1275 struct v4l2_subdev_mbus_code_enum *code) 1276 { 1277 /* Only one bayer order(GRBG) is supported */ 1278 if (code->index > 0) 1279 return -EINVAL; 1280 1281 code->code = MEDIA_BUS_FMT_SGRBG10_1X10; 1282 1283 return 0; 1284 } 1285 1286 static int ov13858_enum_frame_size(struct v4l2_subdev *sd, 1287 struct v4l2_subdev_pad_config *cfg, 1288 struct v4l2_subdev_frame_size_enum *fse) 1289 { 1290 if (fse->index >= ARRAY_SIZE(supported_modes)) 1291 return -EINVAL; 1292 1293 if (fse->code != MEDIA_BUS_FMT_SGRBG10_1X10) 1294 return -EINVAL; 1295 1296 fse->min_width = supported_modes[fse->index].width; 1297 fse->max_width = fse->min_width; 1298 fse->min_height = supported_modes[fse->index].height; 1299 fse->max_height = fse->min_height; 1300 1301 return 0; 1302 } 1303 1304 static void ov13858_update_pad_format(const struct ov13858_mode *mode, 1305 struct v4l2_subdev_format *fmt) 1306 { 1307 fmt->format.width = mode->width; 1308 fmt->format.height = mode->height; 1309 fmt->format.code = MEDIA_BUS_FMT_SGRBG10_1X10; 1310 fmt->format.field = V4L2_FIELD_NONE; 1311 } 1312 1313 static int ov13858_do_get_pad_format(struct ov13858 *ov13858, 1314 struct v4l2_subdev_pad_config *cfg, 1315 struct v4l2_subdev_format *fmt) 1316 { 1317 struct v4l2_mbus_framefmt *framefmt; 1318 struct v4l2_subdev *sd = &ov13858->sd; 1319 1320 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) { 1321 framefmt = v4l2_subdev_get_try_format(sd, cfg, fmt->pad); 1322 fmt->format = *framefmt; 1323 } else { 1324 ov13858_update_pad_format(ov13858->cur_mode, fmt); 1325 } 1326 1327 return 0; 1328 } 1329 1330 static int ov13858_get_pad_format(struct v4l2_subdev *sd, 1331 struct v4l2_subdev_pad_config *cfg, 1332 struct v4l2_subdev_format *fmt) 1333 { 1334 struct ov13858 *ov13858 = to_ov13858(sd); 1335 int ret; 1336 1337 mutex_lock(&ov13858->mutex); 1338 ret = ov13858_do_get_pad_format(ov13858, cfg, fmt); 1339 mutex_unlock(&ov13858->mutex); 1340 1341 return ret; 1342 } 1343 1344 /* 1345 * Calculate resolution distance 1346 */ 1347 static int 1348 ov13858_get_resolution_dist(const struct ov13858_mode *mode, 1349 struct v4l2_mbus_framefmt *framefmt) 1350 { 1351 return abs(mode->width - framefmt->width) + 1352 abs(mode->height - framefmt->height); 1353 } 1354 1355 /* 1356 * Find the closest supported resolution to the requested resolution 1357 */ 1358 static const struct ov13858_mode * 1359 ov13858_find_best_fit(struct ov13858 *ov13858, 1360 struct v4l2_subdev_format *fmt) 1361 { 1362 int i, dist, cur_best_fit = 0, cur_best_fit_dist = -1; 1363 struct v4l2_mbus_framefmt *framefmt = &fmt->format; 1364 1365 for (i = 0; i < ARRAY_SIZE(supported_modes); i++) { 1366 dist = ov13858_get_resolution_dist(&supported_modes[i], 1367 framefmt); 1368 if (cur_best_fit_dist == -1 || dist < cur_best_fit_dist) { 1369 cur_best_fit_dist = dist; 1370 cur_best_fit = i; 1371 } 1372 } 1373 1374 return &supported_modes[cur_best_fit]; 1375 } 1376 1377 static int 1378 ov13858_set_pad_format(struct v4l2_subdev *sd, 1379 struct v4l2_subdev_pad_config *cfg, 1380 struct v4l2_subdev_format *fmt) 1381 { 1382 struct ov13858 *ov13858 = to_ov13858(sd); 1383 const struct ov13858_mode *mode; 1384 struct v4l2_mbus_framefmt *framefmt; 1385 s32 vblank_def; 1386 s32 vblank_min; 1387 s64 h_blank; 1388 1389 mutex_lock(&ov13858->mutex); 1390 1391 /* Only one raw bayer(GRBG) order is supported */ 1392 if (fmt->format.code != MEDIA_BUS_FMT_SGRBG10_1X10) 1393 fmt->format.code = MEDIA_BUS_FMT_SGRBG10_1X10; 1394 1395 mode = ov13858_find_best_fit(ov13858, fmt); 1396 ov13858_update_pad_format(mode, fmt); 1397 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) { 1398 framefmt = v4l2_subdev_get_try_format(sd, cfg, fmt->pad); 1399 *framefmt = fmt->format; 1400 } else { 1401 ov13858->cur_mode = mode; 1402 __v4l2_ctrl_s_ctrl(ov13858->link_freq, mode->link_freq_index); 1403 __v4l2_ctrl_s_ctrl_int64( 1404 ov13858->pixel_rate, 1405 link_freq_configs[mode->link_freq_index].pixel_rate); 1406 /* Update limits and set FPS to default */ 1407 vblank_def = ov13858->cur_mode->vts_def - 1408 ov13858->cur_mode->height; 1409 vblank_min = ov13858->cur_mode->vts_min - 1410 ov13858->cur_mode->height; 1411 __v4l2_ctrl_modify_range( 1412 ov13858->vblank, vblank_min, 1413 OV13858_VTS_MAX - ov13858->cur_mode->height, 1, 1414 vblank_def); 1415 __v4l2_ctrl_s_ctrl(ov13858->vblank, vblank_def); 1416 h_blank = 1417 link_freq_configs[mode->link_freq_index].pixels_per_line 1418 - ov13858->cur_mode->width; 1419 __v4l2_ctrl_modify_range(ov13858->hblank, h_blank, 1420 h_blank, 1, h_blank); 1421 } 1422 1423 mutex_unlock(&ov13858->mutex); 1424 1425 return 0; 1426 } 1427 1428 static int ov13858_get_skip_frames(struct v4l2_subdev *sd, u32 *frames) 1429 { 1430 *frames = OV13858_NUM_OF_SKIP_FRAMES; 1431 1432 return 0; 1433 } 1434 1435 /* Start streaming */ 1436 static int ov13858_start_streaming(struct ov13858 *ov13858) 1437 { 1438 struct i2c_client *client = v4l2_get_subdevdata(&ov13858->sd); 1439 const struct ov13858_reg_list *reg_list; 1440 int ret, link_freq_index; 1441 1442 /* Get out of from software reset */ 1443 ret = ov13858_write_reg(ov13858, OV13858_REG_SOFTWARE_RST, 1444 OV13858_REG_VALUE_08BIT, OV13858_SOFTWARE_RST); 1445 if (ret) { 1446 dev_err(&client->dev, "%s failed to set powerup registers\n", 1447 __func__); 1448 return ret; 1449 } 1450 1451 /* Setup PLL */ 1452 link_freq_index = ov13858->cur_mode->link_freq_index; 1453 reg_list = &link_freq_configs[link_freq_index].reg_list; 1454 ret = ov13858_write_reg_list(ov13858, reg_list); 1455 if (ret) { 1456 dev_err(&client->dev, "%s failed to set plls\n", __func__); 1457 return ret; 1458 } 1459 1460 /* Apply default values of current mode */ 1461 reg_list = &ov13858->cur_mode->reg_list; 1462 ret = ov13858_write_reg_list(ov13858, reg_list); 1463 if (ret) { 1464 dev_err(&client->dev, "%s failed to set mode\n", __func__); 1465 return ret; 1466 } 1467 1468 /* Apply customized values from user */ 1469 ret = __v4l2_ctrl_handler_setup(ov13858->sd.ctrl_handler); 1470 if (ret) 1471 return ret; 1472 1473 return ov13858_write_reg(ov13858, OV13858_REG_MODE_SELECT, 1474 OV13858_REG_VALUE_08BIT, 1475 OV13858_MODE_STREAMING); 1476 } 1477 1478 /* Stop streaming */ 1479 static int ov13858_stop_streaming(struct ov13858 *ov13858) 1480 { 1481 return ov13858_write_reg(ov13858, OV13858_REG_MODE_SELECT, 1482 OV13858_REG_VALUE_08BIT, OV13858_MODE_STANDBY); 1483 } 1484 1485 static int ov13858_set_stream(struct v4l2_subdev *sd, int enable) 1486 { 1487 struct ov13858 *ov13858 = to_ov13858(sd); 1488 struct i2c_client *client = v4l2_get_subdevdata(sd); 1489 int ret = 0; 1490 1491 mutex_lock(&ov13858->mutex); 1492 if (ov13858->streaming == enable) { 1493 mutex_unlock(&ov13858->mutex); 1494 return 0; 1495 } 1496 1497 if (enable) { 1498 ret = pm_runtime_get_sync(&client->dev); 1499 if (ret < 0) { 1500 pm_runtime_put_noidle(&client->dev); 1501 goto err_unlock; 1502 } 1503 1504 /* 1505 * Apply default & customized values 1506 * and then start streaming. 1507 */ 1508 ret = ov13858_start_streaming(ov13858); 1509 if (ret) 1510 goto err_rpm_put; 1511 } else { 1512 ov13858_stop_streaming(ov13858); 1513 pm_runtime_put(&client->dev); 1514 } 1515 1516 ov13858->streaming = enable; 1517 mutex_unlock(&ov13858->mutex); 1518 1519 return ret; 1520 1521 err_rpm_put: 1522 pm_runtime_put(&client->dev); 1523 err_unlock: 1524 mutex_unlock(&ov13858->mutex); 1525 1526 return ret; 1527 } 1528 1529 static int __maybe_unused ov13858_suspend(struct device *dev) 1530 { 1531 struct i2c_client *client = to_i2c_client(dev); 1532 struct v4l2_subdev *sd = i2c_get_clientdata(client); 1533 struct ov13858 *ov13858 = to_ov13858(sd); 1534 1535 if (ov13858->streaming) 1536 ov13858_stop_streaming(ov13858); 1537 1538 return 0; 1539 } 1540 1541 static int __maybe_unused ov13858_resume(struct device *dev) 1542 { 1543 struct i2c_client *client = to_i2c_client(dev); 1544 struct v4l2_subdev *sd = i2c_get_clientdata(client); 1545 struct ov13858 *ov13858 = to_ov13858(sd); 1546 int ret; 1547 1548 if (ov13858->streaming) { 1549 ret = ov13858_start_streaming(ov13858); 1550 if (ret) 1551 goto error; 1552 } 1553 1554 return 0; 1555 1556 error: 1557 ov13858_stop_streaming(ov13858); 1558 ov13858->streaming = 0; 1559 return ret; 1560 } 1561 1562 /* Verify chip ID */ 1563 static int ov13858_identify_module(struct ov13858 *ov13858) 1564 { 1565 struct i2c_client *client = v4l2_get_subdevdata(&ov13858->sd); 1566 int ret; 1567 u32 val; 1568 1569 ret = ov13858_read_reg(ov13858, OV13858_REG_CHIP_ID, 1570 OV13858_REG_VALUE_24BIT, &val); 1571 if (ret) 1572 return ret; 1573 1574 if (val != OV13858_CHIP_ID) { 1575 dev_err(&client->dev, "chip id mismatch: %x!=%x\n", 1576 OV13858_CHIP_ID, val); 1577 return -EIO; 1578 } 1579 1580 return 0; 1581 } 1582 1583 static const struct v4l2_subdev_video_ops ov13858_video_ops = { 1584 .s_stream = ov13858_set_stream, 1585 }; 1586 1587 static const struct v4l2_subdev_pad_ops ov13858_pad_ops = { 1588 .enum_mbus_code = ov13858_enum_mbus_code, 1589 .get_fmt = ov13858_get_pad_format, 1590 .set_fmt = ov13858_set_pad_format, 1591 .enum_frame_size = ov13858_enum_frame_size, 1592 }; 1593 1594 static const struct v4l2_subdev_sensor_ops ov13858_sensor_ops = { 1595 .g_skip_frames = ov13858_get_skip_frames, 1596 }; 1597 1598 static const struct v4l2_subdev_ops ov13858_subdev_ops = { 1599 .video = &ov13858_video_ops, 1600 .pad = &ov13858_pad_ops, 1601 .sensor = &ov13858_sensor_ops, 1602 }; 1603 1604 static const struct media_entity_operations ov13858_subdev_entity_ops = { 1605 .link_validate = v4l2_subdev_link_validate, 1606 }; 1607 1608 static const struct v4l2_subdev_internal_ops ov13858_internal_ops = { 1609 .open = ov13858_open, 1610 }; 1611 1612 /* Initialize control handlers */ 1613 static int ov13858_init_controls(struct ov13858 *ov13858) 1614 { 1615 struct i2c_client *client = v4l2_get_subdevdata(&ov13858->sd); 1616 struct v4l2_ctrl_handler *ctrl_hdlr; 1617 s64 exposure_max; 1618 s64 vblank_def; 1619 s64 vblank_min; 1620 int ret; 1621 1622 ctrl_hdlr = &ov13858->ctrl_handler; 1623 ret = v4l2_ctrl_handler_init(ctrl_hdlr, 8); 1624 if (ret) 1625 return ret; 1626 1627 mutex_init(&ov13858->mutex); 1628 ctrl_hdlr->lock = &ov13858->mutex; 1629 ov13858->link_freq = v4l2_ctrl_new_int_menu(ctrl_hdlr, 1630 &ov13858_ctrl_ops, 1631 V4L2_CID_LINK_FREQ, 1632 OV13858_NUM_OF_LINK_FREQS - 1, 1633 0, 1634 link_freq_menu_items); 1635 ov13858->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY; 1636 1637 /* By default, PIXEL_RATE is read only */ 1638 ov13858->pixel_rate = v4l2_ctrl_new_std(ctrl_hdlr, &ov13858_ctrl_ops, 1639 V4L2_CID_PIXEL_RATE, 0, 1640 link_freq_configs[0].pixel_rate, 1, 1641 link_freq_configs[0].pixel_rate); 1642 1643 vblank_def = ov13858->cur_mode->vts_def - ov13858->cur_mode->height; 1644 vblank_min = ov13858->cur_mode->vts_min - ov13858->cur_mode->height; 1645 ov13858->vblank = v4l2_ctrl_new_std( 1646 ctrl_hdlr, &ov13858_ctrl_ops, V4L2_CID_VBLANK, 1647 vblank_min, 1648 OV13858_VTS_MAX - ov13858->cur_mode->height, 1, 1649 vblank_def); 1650 1651 ov13858->hblank = v4l2_ctrl_new_std( 1652 ctrl_hdlr, &ov13858_ctrl_ops, V4L2_CID_HBLANK, 1653 OV13858_PPL_540MHZ - ov13858->cur_mode->width, 1654 OV13858_PPL_540MHZ - ov13858->cur_mode->width, 1655 1, 1656 OV13858_PPL_540MHZ - ov13858->cur_mode->width); 1657 ov13858->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY; 1658 1659 exposure_max = ov13858->cur_mode->vts_def - 8; 1660 ov13858->exposure = v4l2_ctrl_new_std( 1661 ctrl_hdlr, &ov13858_ctrl_ops, 1662 V4L2_CID_EXPOSURE, OV13858_EXPOSURE_MIN, 1663 exposure_max, OV13858_EXPOSURE_STEP, 1664 OV13858_EXPOSURE_DEFAULT); 1665 1666 v4l2_ctrl_new_std(ctrl_hdlr, &ov13858_ctrl_ops, V4L2_CID_ANALOGUE_GAIN, 1667 OV13858_ANA_GAIN_MIN, OV13858_ANA_GAIN_MAX, 1668 OV13858_ANA_GAIN_STEP, OV13858_ANA_GAIN_DEFAULT); 1669 1670 /* Digital gain */ 1671 v4l2_ctrl_new_std(ctrl_hdlr, &ov13858_ctrl_ops, V4L2_CID_DIGITAL_GAIN, 1672 OV13858_DGTL_GAIN_MIN, OV13858_DGTL_GAIN_MAX, 1673 OV13858_DGTL_GAIN_STEP, OV13858_DGTL_GAIN_DEFAULT); 1674 1675 v4l2_ctrl_new_std_menu_items(ctrl_hdlr, &ov13858_ctrl_ops, 1676 V4L2_CID_TEST_PATTERN, 1677 ARRAY_SIZE(ov13858_test_pattern_menu) - 1, 1678 0, 0, ov13858_test_pattern_menu); 1679 if (ctrl_hdlr->error) { 1680 ret = ctrl_hdlr->error; 1681 dev_err(&client->dev, "%s control init failed (%d)\n", 1682 __func__, ret); 1683 goto error; 1684 } 1685 1686 ov13858->sd.ctrl_handler = ctrl_hdlr; 1687 1688 return 0; 1689 1690 error: 1691 v4l2_ctrl_handler_free(ctrl_hdlr); 1692 mutex_destroy(&ov13858->mutex); 1693 1694 return ret; 1695 } 1696 1697 static void ov13858_free_controls(struct ov13858 *ov13858) 1698 { 1699 v4l2_ctrl_handler_free(ov13858->sd.ctrl_handler); 1700 mutex_destroy(&ov13858->mutex); 1701 } 1702 1703 static int ov13858_probe(struct i2c_client *client, 1704 const struct i2c_device_id *devid) 1705 { 1706 struct ov13858 *ov13858; 1707 int ret; 1708 u32 val = 0; 1709 1710 device_property_read_u32(&client->dev, "clock-frequency", &val); 1711 if (val != 19200000) 1712 return -EINVAL; 1713 1714 ov13858 = devm_kzalloc(&client->dev, sizeof(*ov13858), GFP_KERNEL); 1715 if (!ov13858) 1716 return -ENOMEM; 1717 1718 /* Initialize subdev */ 1719 v4l2_i2c_subdev_init(&ov13858->sd, client, &ov13858_subdev_ops); 1720 1721 /* Check module identity */ 1722 ret = ov13858_identify_module(ov13858); 1723 if (ret) { 1724 dev_err(&client->dev, "failed to find sensor: %d\n", ret); 1725 return ret; 1726 } 1727 1728 /* Set default mode to max resolution */ 1729 ov13858->cur_mode = &supported_modes[0]; 1730 1731 ret = ov13858_init_controls(ov13858); 1732 if (ret) 1733 return ret; 1734 1735 /* Initialize subdev */ 1736 ov13858->sd.internal_ops = &ov13858_internal_ops; 1737 ov13858->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; 1738 ov13858->sd.entity.ops = &ov13858_subdev_entity_ops; 1739 ov13858->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR; 1740 1741 /* Initialize source pad */ 1742 ov13858->pad.flags = MEDIA_PAD_FL_SOURCE; 1743 ret = media_entity_pads_init(&ov13858->sd.entity, 1, &ov13858->pad); 1744 if (ret) { 1745 dev_err(&client->dev, "%s failed:%d\n", __func__, ret); 1746 goto error_handler_free; 1747 } 1748 1749 ret = v4l2_async_register_subdev(&ov13858->sd); 1750 if (ret < 0) 1751 goto error_media_entity; 1752 1753 /* 1754 * Device is already turned on by i2c-core with ACPI domain PM. 1755 * Enable runtime PM and turn off the device. 1756 */ 1757 pm_runtime_get_noresume(&client->dev); 1758 pm_runtime_set_active(&client->dev); 1759 pm_runtime_enable(&client->dev); 1760 pm_runtime_put(&client->dev); 1761 1762 return 0; 1763 1764 error_media_entity: 1765 media_entity_cleanup(&ov13858->sd.entity); 1766 1767 error_handler_free: 1768 ov13858_free_controls(ov13858); 1769 dev_err(&client->dev, "%s failed:%d\n", __func__, ret); 1770 1771 return ret; 1772 } 1773 1774 static int ov13858_remove(struct i2c_client *client) 1775 { 1776 struct v4l2_subdev *sd = i2c_get_clientdata(client); 1777 struct ov13858 *ov13858 = to_ov13858(sd); 1778 1779 v4l2_async_unregister_subdev(sd); 1780 media_entity_cleanup(&sd->entity); 1781 ov13858_free_controls(ov13858); 1782 1783 /* 1784 * Disable runtime PM but keep the device turned on. 1785 * i2c-core with ACPI domain PM will turn off the device. 1786 */ 1787 pm_runtime_get_sync(&client->dev); 1788 pm_runtime_disable(&client->dev); 1789 pm_runtime_set_suspended(&client->dev); 1790 pm_runtime_put_noidle(&client->dev); 1791 1792 return 0; 1793 } 1794 1795 static const struct i2c_device_id ov13858_id_table[] = { 1796 {"ov13858", 0}, 1797 {}, 1798 }; 1799 1800 MODULE_DEVICE_TABLE(i2c, ov13858_id_table); 1801 1802 static const struct dev_pm_ops ov13858_pm_ops = { 1803 SET_SYSTEM_SLEEP_PM_OPS(ov13858_suspend, ov13858_resume) 1804 }; 1805 1806 #ifdef CONFIG_ACPI 1807 static const struct acpi_device_id ov13858_acpi_ids[] = { 1808 {"OVTID858"}, 1809 { /* sentinel */ } 1810 }; 1811 1812 MODULE_DEVICE_TABLE(acpi, ov13858_acpi_ids); 1813 #endif 1814 1815 static struct i2c_driver ov13858_i2c_driver = { 1816 .driver = { 1817 .name = "ov13858", 1818 .owner = THIS_MODULE, 1819 .pm = &ov13858_pm_ops, 1820 .acpi_match_table = ACPI_PTR(ov13858_acpi_ids), 1821 }, 1822 .probe = ov13858_probe, 1823 .remove = ov13858_remove, 1824 .id_table = ov13858_id_table, 1825 }; 1826 1827 module_i2c_driver(ov13858_i2c_driver); 1828 1829 MODULE_AUTHOR("Kan, Chris <chris.kan@intel.com>"); 1830 MODULE_AUTHOR("Rapolu, Chiranjeevi <chiranjeevi.rapolu@intel.com>"); 1831 MODULE_AUTHOR("Yang, Hyungwoo <hyungwoo.yang@intel.com>"); 1832 MODULE_DESCRIPTION("Omnivision ov13858 sensor driver"); 1833 MODULE_LICENSE("GPL v2"); 1834