1 // SPDX-License-Identifier: GPL-2.0 2 // Copyright (c) 2022 Intel Corporation. 3 4 #include <linux/acpi.h> 5 #include <linux/i2c.h> 6 #include <linux/module.h> 7 #include <linux/delay.h> 8 #include <linux/pm_runtime.h> 9 #include <media/v4l2-ctrls.h> 10 #include <media/v4l2-device.h> 11 #include <media/v4l2-fwnode.h> 12 13 #define OV08X40_REG_VALUE_08BIT 1 14 #define OV08X40_REG_VALUE_16BIT 2 15 #define OV08X40_REG_VALUE_24BIT 3 16 17 #define OV08X40_REG_MODE_SELECT 0x0100 18 #define OV08X40_MODE_STANDBY 0x00 19 #define OV08X40_MODE_STREAMING 0x01 20 21 #define OV08X40_REG_AO_STANDBY 0x1000 22 #define OV08X40_AO_STREAMING 0x04 23 24 #define OV08X40_REG_MS_SELECT 0x1001 25 #define OV08X40_MS_STANDBY 0x00 26 #define OV08X40_MS_STREAMING 0x04 27 28 #define OV08X40_REG_SOFTWARE_RST 0x0103 29 #define OV08X40_SOFTWARE_RST 0x01 30 31 /* Chip ID */ 32 #define OV08X40_REG_CHIP_ID 0x300a 33 #define OV08X40_CHIP_ID 0x560858 34 35 /* V_TIMING internal */ 36 #define OV08X40_REG_VTS 0x380e 37 #define OV08X40_VTS_30FPS 0x1388 38 #define OV08X40_VTS_BIN_30FPS 0x115c 39 #define OV08X40_VTS_MAX 0x7fff 40 41 /* H TIMING internal */ 42 #define OV08X40_REG_HTS 0x380c 43 #define OV08X40_HTS_30FPS 0x0280 44 45 /* Exposure control */ 46 #define OV08X40_REG_EXPOSURE 0x3500 47 #define OV08X40_EXPOSURE_MAX_MARGIN 31 48 #define OV08X40_EXPOSURE_MIN 1 49 #define OV08X40_EXPOSURE_STEP 1 50 #define OV08X40_EXPOSURE_DEFAULT 0x40 51 52 /* Short Exposure control */ 53 #define OV08X40_REG_SHORT_EXPOSURE 0x3540 54 55 /* Analog gain control */ 56 #define OV08X40_REG_ANALOG_GAIN 0x3508 57 #define OV08X40_ANA_GAIN_MIN 0x80 58 #define OV08X40_ANA_GAIN_MAX 0x07c0 59 #define OV08X40_ANA_GAIN_STEP 1 60 #define OV08X40_ANA_GAIN_DEFAULT 0x80 61 62 /* Digital gain control */ 63 #define OV08X40_REG_DGTL_GAIN_H 0x350a 64 #define OV08X40_REG_DGTL_GAIN_M 0x350b 65 #define OV08X40_REG_DGTL_GAIN_L 0x350c 66 67 #define OV08X40_DGTL_GAIN_MIN 1024 /* Min = 1 X */ 68 #define OV08X40_DGTL_GAIN_MAX (4096 - 1) /* Max = 4 X */ 69 #define OV08X40_DGTL_GAIN_DEFAULT 2560 /* Default gain = 2.5 X */ 70 #define OV08X40_DGTL_GAIN_STEP 1 /* Each step = 1/1024 */ 71 72 #define OV08X40_DGTL_GAIN_L_SHIFT 6 73 #define OV08X40_DGTL_GAIN_L_MASK 0x3 74 #define OV08X40_DGTL_GAIN_M_SHIFT 2 75 #define OV08X40_DGTL_GAIN_M_MASK 0xff 76 #define OV08X40_DGTL_GAIN_H_SHIFT 10 77 #define OV08X40_DGTL_GAIN_H_MASK 0x1F 78 79 /* Test Pattern Control */ 80 #define OV08X40_REG_TEST_PATTERN 0x50C1 81 #define OV08X40_REG_ISP 0x5000 82 #define OV08X40_REG_SHORT_TEST_PATTERN 0x53C1 83 #define OV08X40_TEST_PATTERN_ENABLE BIT(0) 84 #define OV08X40_TEST_PATTERN_MASK 0xcf 85 #define OV08X40_TEST_PATTERN_BAR_SHIFT 4 86 87 /* Flip Control */ 88 #define OV08X40_REG_VFLIP 0x3820 89 #define OV08X40_REG_MIRROR 0x3821 90 91 /* Horizontal Window Offset */ 92 #define OV08X40_REG_H_WIN_OFFSET 0x3811 93 94 /* Vertical Window Offset */ 95 #define OV08X40_REG_V_WIN_OFFSET 0x3813 96 97 enum { 98 OV08X40_LINK_FREQ_400MHZ_INDEX, 99 }; 100 101 struct ov08x40_reg { 102 u16 address; 103 u8 val; 104 }; 105 106 struct ov08x40_reg_list { 107 u32 num_of_regs; 108 const struct ov08x40_reg *regs; 109 }; 110 111 /* Link frequency config */ 112 struct ov08x40_link_freq_config { 113 /* registers for this link frequency */ 114 struct ov08x40_reg_list reg_list; 115 }; 116 117 /* Mode : resolution and related config&values */ 118 struct ov08x40_mode { 119 /* Frame width */ 120 u32 width; 121 /* Frame height */ 122 u32 height; 123 124 u32 lanes; 125 /* V-timing */ 126 u32 vts_def; 127 u32 vts_min; 128 129 /* HTS */ 130 u32 hts; 131 132 /* Index of Link frequency config to be used */ 133 u32 link_freq_index; 134 /* Default register values */ 135 struct ov08x40_reg_list reg_list; 136 }; 137 138 static const struct ov08x40_reg mipi_data_rate_800mbps[] = { 139 {0x0103, 0x01}, 140 {0x1000, 0x00}, 141 {0x1601, 0xd0}, 142 {0x1001, 0x04}, 143 {0x5004, 0x53}, 144 {0x5110, 0x00}, 145 {0x5111, 0x14}, 146 {0x5112, 0x01}, 147 {0x5113, 0x7b}, 148 {0x5114, 0x00}, 149 {0x5152, 0xa3}, 150 {0x5a52, 0x1f}, 151 {0x5a1a, 0x0e}, 152 {0x5a1b, 0x10}, 153 {0x5a1f, 0x0e}, 154 {0x5a27, 0x0e}, 155 {0x6002, 0x2e}, 156 }; 157 158 static const struct ov08x40_reg mode_3856x2416_regs[] = { 159 {0x5000, 0x5d}, 160 {0x5001, 0x20}, 161 {0x5008, 0xb0}, 162 {0x50c1, 0x00}, 163 {0x53c1, 0x00}, 164 {0x5f40, 0x00}, 165 {0x5f41, 0x40}, 166 {0x0300, 0x3a}, 167 {0x0301, 0xc8}, 168 {0x0302, 0x31}, 169 {0x0303, 0x03}, 170 {0x0304, 0x01}, 171 {0x0305, 0xa1}, 172 {0x0306, 0x04}, 173 {0x0307, 0x01}, 174 {0x0308, 0x03}, 175 {0x0309, 0x03}, 176 {0x0310, 0x0a}, 177 {0x0311, 0x02}, 178 {0x0312, 0x01}, 179 {0x0313, 0x08}, 180 {0x0314, 0x66}, 181 {0x0315, 0x00}, 182 {0x0316, 0x34}, 183 {0x0320, 0x02}, 184 {0x0321, 0x03}, 185 {0x0323, 0x05}, 186 {0x0324, 0x01}, 187 {0x0325, 0xb8}, 188 {0x0326, 0x4a}, 189 {0x0327, 0x04}, 190 {0x0329, 0x00}, 191 {0x032a, 0x05}, 192 {0x032b, 0x00}, 193 {0x032c, 0x00}, 194 {0x032d, 0x00}, 195 {0x032e, 0x02}, 196 {0x032f, 0xa0}, 197 {0x0350, 0x00}, 198 {0x0360, 0x01}, 199 {0x1216, 0x60}, 200 {0x1217, 0x5b}, 201 {0x1218, 0x00}, 202 {0x1220, 0x24}, 203 {0x198a, 0x00}, 204 {0x198b, 0x01}, 205 {0x198e, 0x00}, 206 {0x198f, 0x01}, 207 {0x3009, 0x04}, 208 {0x3012, 0x41}, 209 {0x3015, 0x00}, 210 {0x3016, 0xb0}, 211 {0x3017, 0xf0}, 212 {0x3018, 0xf0}, 213 {0x3019, 0xd2}, 214 {0x301a, 0xb0}, 215 {0x301c, 0x81}, 216 {0x301d, 0x02}, 217 {0x301e, 0x80}, 218 {0x3022, 0xf0}, 219 {0x3025, 0x89}, 220 {0x3030, 0x03}, 221 {0x3044, 0xc2}, 222 {0x3050, 0x35}, 223 {0x3051, 0x60}, 224 {0x3052, 0x25}, 225 {0x3053, 0x00}, 226 {0x3054, 0x00}, 227 {0x3055, 0x02}, 228 {0x3056, 0x80}, 229 {0x3057, 0x80}, 230 {0x3058, 0x80}, 231 {0x3059, 0x00}, 232 {0x3107, 0x86}, 233 {0x3400, 0x1c}, 234 {0x3401, 0x80}, 235 {0x3402, 0x8c}, 236 {0x3419, 0x13}, 237 {0x341a, 0x89}, 238 {0x341b, 0x30}, 239 {0x3420, 0x00}, 240 {0x3421, 0x00}, 241 {0x3422, 0x00}, 242 {0x3423, 0x00}, 243 {0x3424, 0x00}, 244 {0x3425, 0x00}, 245 {0x3426, 0x00}, 246 {0x3427, 0x00}, 247 {0x3428, 0x0f}, 248 {0x3429, 0x00}, 249 {0x342a, 0x00}, 250 {0x342b, 0x00}, 251 {0x342c, 0x00}, 252 {0x342d, 0x00}, 253 {0x342e, 0x00}, 254 {0x342f, 0x11}, 255 {0x3430, 0x11}, 256 {0x3431, 0x10}, 257 {0x3432, 0x00}, 258 {0x3433, 0x00}, 259 {0x3434, 0x00}, 260 {0x3435, 0x00}, 261 {0x3436, 0x00}, 262 {0x3437, 0x00}, 263 {0x3442, 0x02}, 264 {0x3443, 0x02}, 265 {0x3444, 0x07}, 266 {0x3450, 0x00}, 267 {0x3451, 0x00}, 268 {0x3452, 0x18}, 269 {0x3453, 0x18}, 270 {0x3454, 0x00}, 271 {0x3455, 0x80}, 272 {0x3456, 0x08}, 273 {0x3500, 0x00}, 274 {0x3501, 0x02}, 275 {0x3502, 0x00}, 276 {0x3504, 0x4c}, 277 {0x3506, 0x30}, 278 {0x3507, 0x00}, 279 {0x3508, 0x01}, 280 {0x3509, 0x00}, 281 {0x350a, 0x01}, 282 {0x350b, 0x00}, 283 {0x350c, 0x00}, 284 {0x3540, 0x00}, 285 {0x3541, 0x01}, 286 {0x3542, 0x00}, 287 {0x3544, 0x4c}, 288 {0x3546, 0x30}, 289 {0x3547, 0x00}, 290 {0x3548, 0x01}, 291 {0x3549, 0x00}, 292 {0x354a, 0x01}, 293 {0x354b, 0x00}, 294 {0x354c, 0x00}, 295 {0x3688, 0x02}, 296 {0x368a, 0x2e}, 297 {0x368e, 0x71}, 298 {0x3696, 0xd1}, 299 {0x3699, 0x00}, 300 {0x369a, 0x00}, 301 {0x36a4, 0x00}, 302 {0x36a6, 0x00}, 303 {0x3711, 0x00}, 304 {0x3712, 0x51}, 305 {0x3713, 0x00}, 306 {0x3714, 0x24}, 307 {0x3716, 0x00}, 308 {0x3718, 0x07}, 309 {0x371a, 0x1c}, 310 {0x371b, 0x00}, 311 {0x3720, 0x08}, 312 {0x3725, 0x32}, 313 {0x3727, 0x05}, 314 {0x3760, 0x02}, 315 {0x3761, 0x17}, 316 {0x3762, 0x02}, 317 {0x3763, 0x02}, 318 {0x3764, 0x02}, 319 {0x3765, 0x2c}, 320 {0x3766, 0x04}, 321 {0x3767, 0x2c}, 322 {0x3768, 0x02}, 323 {0x3769, 0x00}, 324 {0x376b, 0x20}, 325 {0x376e, 0x03}, 326 {0x37b0, 0x00}, 327 {0x37b1, 0xab}, 328 {0x37b2, 0x01}, 329 {0x37b3, 0x82}, 330 {0x37b4, 0x00}, 331 {0x37b5, 0xe4}, 332 {0x37b6, 0x01}, 333 {0x37b7, 0xee}, 334 {0x3800, 0x00}, 335 {0x3801, 0x00}, 336 {0x3802, 0x00}, 337 {0x3803, 0x00}, 338 {0x3804, 0x0f}, 339 {0x3805, 0x1f}, 340 {0x3806, 0x09}, 341 {0x3807, 0x7f}, 342 {0x3808, 0x0f}, 343 {0x3809, 0x10}, 344 {0x380a, 0x09}, 345 {0x380b, 0x70}, 346 {0x380c, 0x02}, 347 {0x380d, 0x80}, 348 {0x380e, 0x13}, 349 {0x380f, 0x88}, 350 {0x3810, 0x00}, 351 {0x3811, 0x08}, 352 {0x3812, 0x00}, 353 {0x3813, 0x07}, 354 {0x3814, 0x11}, 355 {0x3815, 0x11}, 356 {0x3820, 0x00}, 357 {0x3821, 0x04}, 358 {0x3822, 0x00}, 359 {0x3823, 0x04}, 360 {0x3828, 0x0f}, 361 {0x382a, 0x80}, 362 {0x382e, 0x41}, 363 {0x3837, 0x08}, 364 {0x383a, 0x81}, 365 {0x383b, 0x81}, 366 {0x383c, 0x11}, 367 {0x383d, 0x11}, 368 {0x383e, 0x00}, 369 {0x383f, 0x38}, 370 {0x3840, 0x00}, 371 {0x3847, 0x00}, 372 {0x384a, 0x00}, 373 {0x384c, 0x02}, 374 {0x384d, 0x80}, 375 {0x3856, 0x50}, 376 {0x3857, 0x30}, 377 {0x3858, 0x80}, 378 {0x3859, 0x40}, 379 {0x3860, 0x00}, 380 {0x3888, 0x00}, 381 {0x3889, 0x00}, 382 {0x388a, 0x00}, 383 {0x388b, 0x00}, 384 {0x388c, 0x00}, 385 {0x388d, 0x00}, 386 {0x388e, 0x00}, 387 {0x388f, 0x00}, 388 {0x3894, 0x00}, 389 {0x3895, 0x00}, 390 {0x3c84, 0x00}, 391 {0x3d85, 0x8b}, 392 {0x3daa, 0x80}, 393 {0x3dab, 0x14}, 394 {0x3dac, 0x80}, 395 {0x3dad, 0xc8}, 396 {0x3dae, 0x81}, 397 {0x3daf, 0x7b}, 398 {0x3f00, 0x10}, 399 {0x3f01, 0x11}, 400 {0x3f06, 0x0d}, 401 {0x3f07, 0x0b}, 402 {0x3f08, 0x0d}, 403 {0x3f09, 0x0b}, 404 {0x3f0a, 0x01}, 405 {0x3f0b, 0x11}, 406 {0x3f0c, 0x33}, 407 {0x4001, 0x07}, 408 {0x4007, 0x20}, 409 {0x4008, 0x00}, 410 {0x4009, 0x05}, 411 {0x400a, 0x00}, 412 {0x400b, 0x08}, 413 {0x400c, 0x00}, 414 {0x400d, 0x08}, 415 {0x400e, 0x14}, 416 {0x4010, 0xf4}, 417 {0x4011, 0x03}, 418 {0x4012, 0x55}, 419 {0x4015, 0x00}, 420 {0x4016, 0x2d}, 421 {0x4017, 0x00}, 422 {0x4018, 0x0f}, 423 {0x401b, 0x08}, 424 {0x401c, 0x00}, 425 {0x401d, 0x10}, 426 {0x401e, 0x02}, 427 {0x401f, 0x00}, 428 {0x4050, 0x06}, 429 {0x4051, 0xff}, 430 {0x4052, 0xff}, 431 {0x4053, 0xff}, 432 {0x4054, 0xff}, 433 {0x4055, 0xff}, 434 {0x4056, 0xff}, 435 {0x4057, 0x7f}, 436 {0x4058, 0x00}, 437 {0x4059, 0x00}, 438 {0x405a, 0x00}, 439 {0x405b, 0x00}, 440 {0x405c, 0x07}, 441 {0x405d, 0xff}, 442 {0x405e, 0x07}, 443 {0x405f, 0xff}, 444 {0x4080, 0x78}, 445 {0x4081, 0x78}, 446 {0x4082, 0x78}, 447 {0x4083, 0x78}, 448 {0x4019, 0x00}, 449 {0x401a, 0x40}, 450 {0x4020, 0x04}, 451 {0x4021, 0x00}, 452 {0x4022, 0x04}, 453 {0x4023, 0x00}, 454 {0x4024, 0x04}, 455 {0x4025, 0x00}, 456 {0x4026, 0x04}, 457 {0x4027, 0x00}, 458 {0x4030, 0x00}, 459 {0x4031, 0x00}, 460 {0x4032, 0x00}, 461 {0x4033, 0x00}, 462 {0x4034, 0x00}, 463 {0x4035, 0x00}, 464 {0x4036, 0x00}, 465 {0x4037, 0x00}, 466 {0x4040, 0x00}, 467 {0x4041, 0x80}, 468 {0x4042, 0x00}, 469 {0x4043, 0x80}, 470 {0x4044, 0x00}, 471 {0x4045, 0x80}, 472 {0x4046, 0x00}, 473 {0x4047, 0x80}, 474 {0x4060, 0x00}, 475 {0x4061, 0x00}, 476 {0x4062, 0x00}, 477 {0x4063, 0x00}, 478 {0x4064, 0x00}, 479 {0x4065, 0x00}, 480 {0x4066, 0x00}, 481 {0x4067, 0x00}, 482 {0x4068, 0x00}, 483 {0x4069, 0x00}, 484 {0x406a, 0x00}, 485 {0x406b, 0x00}, 486 {0x406c, 0x00}, 487 {0x406d, 0x00}, 488 {0x406e, 0x00}, 489 {0x406f, 0x00}, 490 {0x4070, 0x00}, 491 {0x4071, 0x00}, 492 {0x4072, 0x00}, 493 {0x4073, 0x00}, 494 {0x4074, 0x00}, 495 {0x4075, 0x00}, 496 {0x4076, 0x00}, 497 {0x4077, 0x00}, 498 {0x4078, 0x00}, 499 {0x4079, 0x00}, 500 {0x407a, 0x00}, 501 {0x407b, 0x00}, 502 {0x407c, 0x00}, 503 {0x407d, 0x00}, 504 {0x407e, 0x00}, 505 {0x407f, 0x00}, 506 {0x40e0, 0x00}, 507 {0x40e1, 0x00}, 508 {0x40e2, 0x00}, 509 {0x40e3, 0x00}, 510 {0x40e4, 0x00}, 511 {0x40e5, 0x00}, 512 {0x40e6, 0x00}, 513 {0x40e7, 0x00}, 514 {0x40e8, 0x00}, 515 {0x40e9, 0x80}, 516 {0x40ea, 0x00}, 517 {0x40eb, 0x80}, 518 {0x40ec, 0x00}, 519 {0x40ed, 0x80}, 520 {0x40ee, 0x00}, 521 {0x40ef, 0x80}, 522 {0x40f0, 0x02}, 523 {0x40f1, 0x04}, 524 {0x4300, 0x00}, 525 {0x4301, 0x00}, 526 {0x4302, 0x00}, 527 {0x4303, 0x00}, 528 {0x4304, 0x00}, 529 {0x4305, 0x00}, 530 {0x4306, 0x00}, 531 {0x4307, 0x00}, 532 {0x4308, 0x00}, 533 {0x4309, 0x00}, 534 {0x430a, 0x00}, 535 {0x430b, 0xff}, 536 {0x430c, 0xff}, 537 {0x430d, 0x00}, 538 {0x430e, 0x00}, 539 {0x4315, 0x00}, 540 {0x4316, 0x00}, 541 {0x4317, 0x00}, 542 {0x4318, 0x00}, 543 {0x4319, 0x00}, 544 {0x431a, 0x00}, 545 {0x431b, 0x00}, 546 {0x431c, 0x00}, 547 {0x4500, 0x07}, 548 {0x4501, 0x00}, 549 {0x4502, 0x00}, 550 {0x4503, 0x0f}, 551 {0x4504, 0x80}, 552 {0x4506, 0x01}, 553 {0x4509, 0x05}, 554 {0x450c, 0x00}, 555 {0x450d, 0x20}, 556 {0x450e, 0x00}, 557 {0x450f, 0x00}, 558 {0x4510, 0x00}, 559 {0x4523, 0x00}, 560 {0x4526, 0x00}, 561 {0x4542, 0x00}, 562 {0x4543, 0x00}, 563 {0x4544, 0x00}, 564 {0x4545, 0x00}, 565 {0x4546, 0x00}, 566 {0x4547, 0x10}, 567 {0x4602, 0x00}, 568 {0x4603, 0x15}, 569 {0x460b, 0x07}, 570 {0x4680, 0x11}, 571 {0x4686, 0x00}, 572 {0x4687, 0x00}, 573 {0x4700, 0x00}, 574 {0x4800, 0x64}, 575 {0x4806, 0x40}, 576 {0x480b, 0x10}, 577 {0x480c, 0x80}, 578 {0x480f, 0x32}, 579 {0x4813, 0xe4}, 580 {0x4837, 0x14}, 581 {0x4850, 0x42}, 582 {0x4884, 0x04}, 583 {0x4c00, 0xf8}, 584 {0x4c01, 0x44}, 585 {0x4c03, 0x00}, 586 {0x4d00, 0x00}, 587 {0x4d01, 0x16}, 588 {0x4d04, 0x10}, 589 {0x4d05, 0x00}, 590 {0x4d06, 0x0c}, 591 {0x4d07, 0x00}, 592 {0x3d84, 0x04}, 593 {0x3680, 0xa4}, 594 {0x3682, 0x80}, 595 {0x3601, 0x40}, 596 {0x3602, 0x90}, 597 {0x3608, 0x0a}, 598 {0x3938, 0x09}, 599 {0x3a74, 0x84}, 600 {0x3a99, 0x84}, 601 {0x3ab9, 0xa6}, 602 {0x3aba, 0xba}, 603 {0x3b12, 0x84}, 604 {0x3b14, 0xbb}, 605 {0x3b15, 0xbf}, 606 {0x3a29, 0x26}, 607 {0x3a1f, 0x8a}, 608 {0x3a22, 0x91}, 609 {0x3a25, 0x96}, 610 {0x3a28, 0xb4}, 611 {0x3a2b, 0xba}, 612 {0x3a2e, 0xbf}, 613 {0x3a31, 0xc1}, 614 {0x3a20, 0x00}, 615 {0x3939, 0x9d}, 616 {0x3902, 0x0e}, 617 {0x3903, 0x0e}, 618 {0x3904, 0x0e}, 619 {0x3905, 0x0e}, 620 {0x3906, 0x07}, 621 {0x3907, 0x0d}, 622 {0x3908, 0x11}, 623 {0x3909, 0x12}, 624 {0x360f, 0x99}, 625 {0x390c, 0x33}, 626 {0x390d, 0x66}, 627 {0x390e, 0xaa}, 628 {0x3911, 0x90}, 629 {0x3913, 0x90}, 630 {0x3915, 0x90}, 631 {0x3917, 0x90}, 632 {0x3b3f, 0x9d}, 633 {0x3b45, 0x9d}, 634 {0x3b1b, 0xc9}, 635 {0x3b21, 0xc9}, 636 {0x3440, 0xa4}, 637 {0x3a23, 0x15}, 638 {0x3a26, 0x1d}, 639 {0x3a2c, 0x4a}, 640 {0x3a2f, 0x18}, 641 {0x3a32, 0x55}, 642 {0x3b0a, 0x01}, 643 {0x3b0b, 0x00}, 644 {0x3b0e, 0x01}, 645 {0x3b0f, 0x00}, 646 {0x392c, 0x02}, 647 {0x392d, 0x02}, 648 {0x392e, 0x04}, 649 {0x392f, 0x03}, 650 {0x3930, 0x08}, 651 {0x3931, 0x07}, 652 {0x3932, 0x10}, 653 {0x3933, 0x0c}, 654 {0x3609, 0x08}, 655 {0x3921, 0x0f}, 656 {0x3928, 0x15}, 657 {0x3929, 0x2a}, 658 {0x392a, 0x54}, 659 {0x392b, 0xa8}, 660 {0x3426, 0x10}, 661 {0x3407, 0x01}, 662 {0x3404, 0x01}, 663 {0x3500, 0x00}, 664 {0x3501, 0x10}, 665 {0x3502, 0x10}, 666 {0x3508, 0x0f}, 667 {0x3509, 0x80}, 668 {0x5a80, 0x75}, 669 {0x5a81, 0x75}, 670 {0x5a82, 0x75}, 671 {0x5a83, 0x75}, 672 {0x5a84, 0x75}, 673 {0x5a85, 0x75}, 674 {0x5a86, 0x75}, 675 {0x5a87, 0x75}, 676 {0x5a88, 0x75}, 677 {0x5a89, 0x75}, 678 {0x5a8a, 0x75}, 679 {0x5a8b, 0x75}, 680 {0x5a8c, 0x75}, 681 {0x5a8d, 0x75}, 682 {0x5a8e, 0x75}, 683 {0x5a8f, 0x75}, 684 {0x5a90, 0x75}, 685 {0x5a91, 0x75}, 686 {0x5a92, 0x75}, 687 {0x5a93, 0x75}, 688 {0x5a94, 0x75}, 689 {0x5a95, 0x75}, 690 {0x5a96, 0x75}, 691 {0x5a97, 0x75}, 692 {0x5a98, 0x75}, 693 {0x5a99, 0x75}, 694 {0x5a9a, 0x75}, 695 {0x5a9b, 0x75}, 696 {0x5a9c, 0x75}, 697 {0x5a9d, 0x75}, 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0x75}, 1616 {0x5e54, 0x75}, 1617 {0x5e55, 0x75}, 1618 {0x5e56, 0x75}, 1619 {0x5e57, 0x75}, 1620 {0x5e58, 0x75}, 1621 {0x5e59, 0x75}, 1622 {0x5e5a, 0x75}, 1623 {0x5e5b, 0x75}, 1624 {0x5e5c, 0x75}, 1625 {0x5e5d, 0x75}, 1626 {0x5e5e, 0x75}, 1627 {0x5e5f, 0x75}, 1628 {0x5e60, 0x75}, 1629 {0x5e61, 0x75}, 1630 {0x5e62, 0x75}, 1631 {0x5e63, 0x75}, 1632 {0x5e64, 0x75}, 1633 {0x5e65, 0x75}, 1634 {0x5e66, 0x75}, 1635 {0x5e67, 0x75}, 1636 {0x5e68, 0x75}, 1637 {0x5e69, 0x75}, 1638 {0x5e6a, 0x75}, 1639 {0x5e6b, 0x75}, 1640 {0x5e6c, 0x75}, 1641 {0x5e6d, 0x75}, 1642 {0x5e6e, 0x75}, 1643 {0x5e6f, 0x75}, 1644 {0x5e70, 0x75}, 1645 {0x5e71, 0x75}, 1646 {0x5e72, 0x75}, 1647 {0x5e73, 0x75}, 1648 {0x5e74, 0x75}, 1649 {0x5e75, 0x75}, 1650 {0x5e76, 0x75}, 1651 {0x5e77, 0x75}, 1652 {0x5e78, 0x75}, 1653 {0x5e79, 0x75}, 1654 {0x5e7a, 0x75}, 1655 {0x5e7b, 0x75}, 1656 {0x5e7c, 0x75}, 1657 {0x5e7d, 0x75}, 1658 {0x5e7e, 0x75}, 1659 {0x5e7f, 0x75}, 1660 {0x5e80, 0x75}, 1661 {0x5e81, 0x75}, 1662 {0x5e82, 0x75}, 1663 {0x5e83, 0x75}, 1664 {0x5e84, 0x75}, 1665 {0x5e85, 0x75}, 1666 {0x5e86, 0x75}, 1667 {0x5e87, 0x75}, 1668 {0x5e88, 0x75}, 1669 {0x5e89, 0x75}, 1670 {0x5e8a, 0x75}, 1671 {0x5e8b, 0x75}, 1672 {0x5e8c, 0x75}, 1673 {0x5e8d, 0x75}, 1674 {0x5e8e, 0x75}, 1675 {0x5e8f, 0x75}, 1676 {0x5e90, 0x75}, 1677 {0x5e91, 0x75}, 1678 {0x5e92, 0x75}, 1679 {0x5e93, 0x75}, 1680 {0x5e94, 0x75}, 1681 {0x5e95, 0x75}, 1682 {0x5e96, 0x75}, 1683 {0x5e97, 0x75}, 1684 {0x5e98, 0x75}, 1685 {0x5e99, 0x75}, 1686 {0x5e9a, 0x75}, 1687 {0x5e9b, 0x75}, 1688 {0x5e9c, 0x75}, 1689 {0x5e9d, 0x75}, 1690 {0x5e9e, 0x75}, 1691 {0x5e9f, 0x75}, 1692 {0x5ea0, 0x75}, 1693 {0x5ea1, 0x75}, 1694 {0x5ea2, 0x75}, 1695 {0x5ea3, 0x75}, 1696 {0x5ea4, 0x75}, 1697 {0x5ea5, 0x75}, 1698 {0x5ea6, 0x75}, 1699 {0x5ea7, 0x75}, 1700 {0x5ea8, 0x75}, 1701 {0x5ea9, 0x75}, 1702 {0x5eaa, 0x75}, 1703 {0x5eab, 0x75}, 1704 {0x5eac, 0x75}, 1705 {0x5ead, 0x75}, 1706 {0x5eae, 0x75}, 1707 {0x5eaf, 0x75}, 1708 {0x5eb0, 0x75}, 1709 {0x5eb1, 0x75}, 1710 {0x5eb2, 0x75}, 1711 {0x5eb3, 0x75}, 1712 {0x5eb4, 0x75}, 1713 {0x5eb5, 0x75}, 1714 {0x5eb6, 0x75}, 1715 {0x5eb7, 0x75}, 1716 {0x5eb8, 0x75}, 1717 {0x5eb9, 0x75}, 1718 {0x5eba, 0x75}, 1719 {0x5ebb, 0x75}, 1720 {0x5ebc, 0x75}, 1721 {0x5ebd, 0x75}, 1722 {0x5ebe, 0x75}, 1723 {0x5ebf, 0x75}, 1724 {0x5ec0, 0x75}, 1725 {0x5ec1, 0x75}, 1726 {0x5ec2, 0x75}, 1727 {0x5ec3, 0x75}, 1728 {0x5ec4, 0x75}, 1729 {0x5ec5, 0x75}, 1730 {0x5ec6, 0x75}, 1731 {0x5ec7, 0x75}, 1732 {0x5ec8, 0x75}, 1733 {0x5ec9, 0x75}, 1734 {0x5eca, 0x75}, 1735 {0x5ecb, 0x75}, 1736 {0x5ecc, 0x75}, 1737 {0x5ecd, 0x75}, 1738 {0x5ece, 0x75}, 1739 {0x5ecf, 0x75}, 1740 {0x5ed0, 0x75}, 1741 {0x5ed1, 0x75}, 1742 {0x5ed2, 0x75}, 1743 {0x5ed3, 0x75}, 1744 {0x5ed4, 0x75}, 1745 {0x5ed5, 0x75}, 1746 {0x5ed6, 0x75}, 1747 {0x5ed7, 0x75}, 1748 {0x5ed8, 0x75}, 1749 {0x5ed9, 0x75}, 1750 {0x5eda, 0x75}, 1751 {0x5edb, 0x75}, 1752 {0x5edc, 0x75}, 1753 {0x5edd, 0x75}, 1754 {0x5ede, 0x75}, 1755 {0x5edf, 0x75}, 1756 {0x5ee0, 0x75}, 1757 {0x5ee1, 0x75}, 1758 {0x5ee2, 0x75}, 1759 {0x5ee3, 0x75}, 1760 {0x5ee4, 0x75}, 1761 {0x5ee5, 0x75}, 1762 {0x5ee6, 0x75}, 1763 {0x5ee7, 0x75}, 1764 {0x5ee8, 0x75}, 1765 {0x5ee9, 0x75}, 1766 {0x5eea, 0x75}, 1767 {0x5eeb, 0x75}, 1768 {0x5eec, 0x75}, 1769 {0x5eed, 0x75}, 1770 {0x5eee, 0x75}, 1771 {0x5eef, 0x75}, 1772 {0x5ef0, 0x75}, 1773 {0x5ef1, 0x75}, 1774 {0x5ef2, 0x75}, 1775 {0x5ef3, 0x75}, 1776 {0x5ef4, 0x75}, 1777 {0x5ef5, 0x75}, 1778 {0x5ef6, 0x75}, 1779 {0x5ef7, 0x75}, 1780 {0x5ef8, 0x75}, 1781 {0x5ef9, 0x75}, 1782 {0x5efa, 0x75}, 1783 {0x5efb, 0x75}, 1784 {0x5efc, 0x75}, 1785 {0x5efd, 0x75}, 1786 {0x5efe, 0x75}, 1787 {0x5eff, 0x75}, 1788 {0x5f00, 0x75}, 1789 {0x5f01, 0x75}, 1790 {0x5f02, 0x75}, 1791 {0x5f03, 0x75}, 1792 {0x5f04, 0x75}, 1793 {0x5f05, 0x75}, 1794 {0x5f06, 0x75}, 1795 {0x5f07, 0x75}, 1796 {0x5f08, 0x75}, 1797 {0x5f09, 0x75}, 1798 {0x5f0a, 0x75}, 1799 {0x5f0b, 0x75}, 1800 {0x5f0c, 0x75}, 1801 {0x5f0d, 0x75}, 1802 {0x5f0e, 0x75}, 1803 {0x5f0f, 0x75}, 1804 {0x5f10, 0x75}, 1805 {0x5f11, 0x75}, 1806 {0x5f12, 0x75}, 1807 {0x5f13, 0x75}, 1808 {0x5f14, 0x75}, 1809 {0x5f15, 0x75}, 1810 {0x5f16, 0x75}, 1811 {0x5f17, 0x75}, 1812 {0x5f18, 0x75}, 1813 {0x5f19, 0x75}, 1814 {0x5f1a, 0x75}, 1815 {0x5f1b, 0x75}, 1816 {0x5f1c, 0x75}, 1817 {0x5f1d, 0x75}, 1818 {0x5f1e, 0x75}, 1819 {0x5f1f, 0x75}, 1820 }; 1821 1822 static const struct ov08x40_reg mode_1928x1208_regs[] = { 1823 {0x5000, 0x55}, 1824 {0x5001, 0x00}, 1825 {0x5008, 0xb0}, 1826 {0x50c1, 0x00}, 1827 {0x53c1, 0x00}, 1828 {0x5f40, 0x00}, 1829 {0x5f41, 0x40}, 1830 {0x0300, 0x3a}, 1831 {0x0301, 0xc8}, 1832 {0x0302, 0x31}, 1833 {0x0303, 0x03}, 1834 {0x0304, 0x01}, 1835 {0x0305, 0xa1}, 1836 {0x0306, 0x04}, 1837 {0x0307, 0x01}, 1838 {0x0308, 0x03}, 1839 {0x0309, 0x03}, 1840 {0x0310, 0x0a}, 1841 {0x0311, 0x02}, 1842 {0x0312, 0x01}, 1843 {0x0313, 0x08}, 1844 {0x0314, 0x66}, 1845 {0x0315, 0x00}, 1846 {0x0316, 0x34}, 1847 {0x0320, 0x02}, 1848 {0x0321, 0x03}, 1849 {0x0323, 0x05}, 1850 {0x0324, 0x01}, 1851 {0x0325, 0xb8}, 1852 {0x0326, 0x4a}, 1853 {0x0327, 0x04}, 1854 {0x0329, 0x00}, 1855 {0x032a, 0x05}, 1856 {0x032b, 0x00}, 1857 {0x032c, 0x00}, 1858 {0x032d, 0x00}, 1859 {0x032e, 0x02}, 1860 {0x032f, 0xa0}, 1861 {0x0350, 0x00}, 1862 {0x0360, 0x01}, 1863 {0x1216, 0x60}, 1864 {0x1217, 0x5b}, 1865 {0x1218, 0x00}, 1866 {0x1220, 0x24}, 1867 {0x198a, 0x00}, 1868 {0x198b, 0x01}, 1869 {0x198e, 0x00}, 1870 {0x198f, 0x01}, 1871 {0x3009, 0x04}, 1872 {0x3012, 0x41}, 1873 {0x3015, 0x00}, 1874 {0x3016, 0xb0}, 1875 {0x3017, 0xf0}, 1876 {0x3018, 0xf0}, 1877 {0x3019, 0xd2}, 1878 {0x301a, 0xb0}, 1879 {0x301c, 0x81}, 1880 {0x301d, 0x02}, 1881 {0x301e, 0x80}, 1882 {0x3022, 0xf0}, 1883 {0x3025, 0x89}, 1884 {0x3030, 0x03}, 1885 {0x3044, 0xc2}, 1886 {0x3050, 0x35}, 1887 {0x3051, 0x60}, 1888 {0x3052, 0x25}, 1889 {0x3053, 0x00}, 1890 {0x3054, 0x00}, 1891 {0x3055, 0x02}, 1892 {0x3056, 0x80}, 1893 {0x3057, 0x80}, 1894 {0x3058, 0x80}, 1895 {0x3059, 0x00}, 1896 {0x3107, 0x86}, 1897 {0x3400, 0x1c}, 1898 {0x3401, 0x80}, 1899 {0x3402, 0x8c}, 1900 {0x3419, 0x08}, 1901 {0x341a, 0xaf}, 1902 {0x341b, 0x30}, 1903 {0x3420, 0x00}, 1904 {0x3421, 0x00}, 1905 {0x3422, 0x00}, 1906 {0x3423, 0x00}, 1907 {0x3424, 0x00}, 1908 {0x3425, 0x00}, 1909 {0x3426, 0x00}, 1910 {0x3427, 0x00}, 1911 {0x3428, 0x0f}, 1912 {0x3429, 0x00}, 1913 {0x342a, 0x00}, 1914 {0x342b, 0x00}, 1915 {0x342c, 0x00}, 1916 {0x342d, 0x00}, 1917 {0x342e, 0x00}, 1918 {0x342f, 0x11}, 1919 {0x3430, 0x11}, 1920 {0x3431, 0x10}, 1921 {0x3432, 0x00}, 1922 {0x3433, 0x00}, 1923 {0x3434, 0x00}, 1924 {0x3435, 0x00}, 1925 {0x3436, 0x00}, 1926 {0x3437, 0x00}, 1927 {0x3442, 0x02}, 1928 {0x3443, 0x02}, 1929 {0x3444, 0x07}, 1930 {0x3450, 0x00}, 1931 {0x3451, 0x00}, 1932 {0x3452, 0x18}, 1933 {0x3453, 0x18}, 1934 {0x3454, 0x00}, 1935 {0x3455, 0x80}, 1936 {0x3456, 0x08}, 1937 {0x3500, 0x00}, 1938 {0x3501, 0x02}, 1939 {0x3502, 0x00}, 1940 {0x3504, 0x4c}, 1941 {0x3506, 0x30}, 1942 {0x3507, 0x00}, 1943 {0x3508, 0x01}, 1944 {0x3509, 0x00}, 1945 {0x350a, 0x01}, 1946 {0x350b, 0x00}, 1947 {0x350c, 0x00}, 1948 {0x3540, 0x00}, 1949 {0x3541, 0x01}, 1950 {0x3542, 0x00}, 1951 {0x3544, 0x4c}, 1952 {0x3546, 0x30}, 1953 {0x3547, 0x00}, 1954 {0x3548, 0x01}, 1955 {0x3549, 0x00}, 1956 {0x354a, 0x01}, 1957 {0x354b, 0x00}, 1958 {0x354c, 0x00}, 1959 {0x3688, 0x02}, 1960 {0x368a, 0x2e}, 1961 {0x368e, 0x71}, 1962 {0x3696, 0xd1}, 1963 {0x3699, 0x00}, 1964 {0x369a, 0x00}, 1965 {0x36a4, 0x00}, 1966 {0x36a6, 0x00}, 1967 {0x3711, 0x00}, 1968 {0x3712, 0x50}, 1969 {0x3713, 0x00}, 1970 {0x3714, 0x21}, 1971 {0x3716, 0x00}, 1972 {0x3718, 0x07}, 1973 {0x371a, 0x1c}, 1974 {0x371b, 0x00}, 1975 {0x3720, 0x08}, 1976 {0x3725, 0x32}, 1977 {0x3727, 0x05}, 1978 {0x3760, 0x02}, 1979 {0x3761, 0x28}, 1980 {0x3762, 0x02}, 1981 {0x3763, 0x02}, 1982 {0x3764, 0x02}, 1983 {0x3765, 0x2c}, 1984 {0x3766, 0x04}, 1985 {0x3767, 0x2c}, 1986 {0x3768, 0x02}, 1987 {0x3769, 0x00}, 1988 {0x376b, 0x20}, 1989 {0x376e, 0x07}, 1990 {0x37b0, 0x01}, 1991 {0x37b1, 0x0f}, 1992 {0x37b2, 0x01}, 1993 {0x37b3, 0xd6}, 1994 {0x37b4, 0x01}, 1995 {0x37b5, 0x48}, 1996 {0x37b6, 0x02}, 1997 {0x37b7, 0x40}, 1998 {0x3800, 0x00}, 1999 {0x3801, 0x00}, 2000 {0x3802, 0x00}, 2001 {0x3803, 0x00}, 2002 {0x3804, 0x0f}, 2003 {0x3805, 0x1f}, 2004 {0x3806, 0x09}, 2005 {0x3807, 0x7f}, 2006 {0x3808, 0x07}, 2007 {0x3809, 0x88}, 2008 {0x380a, 0x04}, 2009 {0x380b, 0xb8}, 2010 {0x380c, 0x02}, 2011 {0x380d, 0xd0}, 2012 {0x380e, 0x11}, 2013 {0x380f, 0x5c}, 2014 {0x3810, 0x00}, 2015 {0x3811, 0x04}, 2016 {0x3812, 0x00}, 2017 {0x3813, 0x03}, 2018 {0x3814, 0x11}, 2019 {0x3815, 0x11}, 2020 {0x3820, 0x02}, 2021 {0x3821, 0x14}, 2022 {0x3822, 0x00}, 2023 {0x3823, 0x04}, 2024 {0x3828, 0x0f}, 2025 {0x382a, 0x80}, 2026 {0x382e, 0x41}, 2027 {0x3837, 0x08}, 2028 {0x383a, 0x81}, 2029 {0x383b, 0x81}, 2030 {0x383c, 0x11}, 2031 {0x383d, 0x11}, 2032 {0x383e, 0x00}, 2033 {0x383f, 0x38}, 2034 {0x3840, 0x00}, 2035 {0x3847, 0x00}, 2036 {0x384a, 0x00}, 2037 {0x384c, 0x02}, 2038 {0x384d, 0xd0}, 2039 {0x3856, 0x50}, 2040 {0x3857, 0x30}, 2041 {0x3858, 0x80}, 2042 {0x3859, 0x40}, 2043 {0x3860, 0x00}, 2044 {0x3888, 0x00}, 2045 {0x3889, 0x00}, 2046 {0x388a, 0x00}, 2047 {0x388b, 0x00}, 2048 {0x388c, 0x00}, 2049 {0x388d, 0x00}, 2050 {0x388e, 0x00}, 2051 {0x388f, 0x00}, 2052 {0x3894, 0x00}, 2053 {0x3895, 0x00}, 2054 {0x3c84, 0x00}, 2055 {0x3d85, 0x8b}, 2056 {0x3daa, 0x80}, 2057 {0x3dab, 0x14}, 2058 {0x3dac, 0x80}, 2059 {0x3dad, 0xc8}, 2060 {0x3dae, 0x81}, 2061 {0x3daf, 0x7b}, 2062 {0x3f00, 0x10}, 2063 {0x3f01, 0x11}, 2064 {0x3f06, 0x0d}, 2065 {0x3f07, 0x0b}, 2066 {0x3f08, 0x0d}, 2067 {0x3f09, 0x0b}, 2068 {0x3f0a, 0x01}, 2069 {0x3f0b, 0x11}, 2070 {0x3f0c, 0x33}, 2071 {0x4001, 0x07}, 2072 {0x4007, 0x20}, 2073 {0x4008, 0x00}, 2074 {0x4009, 0x05}, 2075 {0x400a, 0x00}, 2076 {0x400b, 0x04}, 2077 {0x400c, 0x00}, 2078 {0x400d, 0x04}, 2079 {0x400e, 0x14}, 2080 {0x4010, 0xf4}, 2081 {0x4011, 0x03}, 2082 {0x4012, 0x55}, 2083 {0x4015, 0x00}, 2084 {0x4016, 0x27}, 2085 {0x4017, 0x00}, 2086 {0x4018, 0x0f}, 2087 {0x401b, 0x08}, 2088 {0x401c, 0x00}, 2089 {0x401d, 0x10}, 2090 {0x401e, 0x02}, 2091 {0x401f, 0x00}, 2092 {0x4050, 0x06}, 2093 {0x4051, 0xff}, 2094 {0x4052, 0xff}, 2095 {0x4053, 0xff}, 2096 {0x4054, 0xff}, 2097 {0x4055, 0xff}, 2098 {0x4056, 0xff}, 2099 {0x4057, 0x7f}, 2100 {0x4058, 0x00}, 2101 {0x4059, 0x00}, 2102 {0x405a, 0x00}, 2103 {0x405b, 0x00}, 2104 {0x405c, 0x07}, 2105 {0x405d, 0xff}, 2106 {0x405e, 0x07}, 2107 {0x405f, 0xff}, 2108 {0x4080, 0x78}, 2109 {0x4081, 0x78}, 2110 {0x4082, 0x78}, 2111 {0x4083, 0x78}, 2112 {0x4019, 0x00}, 2113 {0x401a, 0x40}, 2114 {0x4020, 0x04}, 2115 {0x4021, 0x00}, 2116 {0x4022, 0x04}, 2117 {0x4023, 0x00}, 2118 {0x4024, 0x04}, 2119 {0x4025, 0x00}, 2120 {0x4026, 0x04}, 2121 {0x4027, 0x00}, 2122 {0x4030, 0x00}, 2123 {0x4031, 0x00}, 2124 {0x4032, 0x00}, 2125 {0x4033, 0x00}, 2126 {0x4034, 0x00}, 2127 {0x4035, 0x00}, 2128 {0x4036, 0x00}, 2129 {0x4037, 0x00}, 2130 {0x4040, 0x00}, 2131 {0x4041, 0x80}, 2132 {0x4042, 0x00}, 2133 {0x4043, 0x80}, 2134 {0x4044, 0x00}, 2135 {0x4045, 0x80}, 2136 {0x4046, 0x00}, 2137 {0x4047, 0x80}, 2138 {0x4060, 0x00}, 2139 {0x4061, 0x00}, 2140 {0x4062, 0x00}, 2141 {0x4063, 0x00}, 2142 {0x4064, 0x00}, 2143 {0x4065, 0x00}, 2144 {0x4066, 0x00}, 2145 {0x4067, 0x00}, 2146 {0x4068, 0x00}, 2147 {0x4069, 0x00}, 2148 {0x406a, 0x00}, 2149 {0x406b, 0x00}, 2150 {0x406c, 0x00}, 2151 {0x406d, 0x00}, 2152 {0x406e, 0x00}, 2153 {0x406f, 0x00}, 2154 {0x4070, 0x00}, 2155 {0x4071, 0x00}, 2156 {0x4072, 0x00}, 2157 {0x4073, 0x00}, 2158 {0x4074, 0x00}, 2159 {0x4075, 0x00}, 2160 {0x4076, 0x00}, 2161 {0x4077, 0x00}, 2162 {0x4078, 0x00}, 2163 {0x4079, 0x00}, 2164 {0x407a, 0x00}, 2165 {0x407b, 0x00}, 2166 {0x407c, 0x00}, 2167 {0x407d, 0x00}, 2168 {0x407e, 0x00}, 2169 {0x407f, 0x00}, 2170 {0x40e0, 0x00}, 2171 {0x40e1, 0x00}, 2172 {0x40e2, 0x00}, 2173 {0x40e3, 0x00}, 2174 {0x40e4, 0x00}, 2175 {0x40e5, 0x00}, 2176 {0x40e6, 0x00}, 2177 {0x40e7, 0x00}, 2178 {0x40e8, 0x00}, 2179 {0x40e9, 0x80}, 2180 {0x40ea, 0x00}, 2181 {0x40eb, 0x80}, 2182 {0x40ec, 0x00}, 2183 {0x40ed, 0x80}, 2184 {0x40ee, 0x00}, 2185 {0x40ef, 0x80}, 2186 {0x40f0, 0x02}, 2187 {0x40f1, 0x04}, 2188 {0x4300, 0x00}, 2189 {0x4301, 0x00}, 2190 {0x4302, 0x00}, 2191 {0x4303, 0x00}, 2192 {0x4304, 0x00}, 2193 {0x4305, 0x00}, 2194 {0x4306, 0x00}, 2195 {0x4307, 0x00}, 2196 {0x4308, 0x00}, 2197 {0x4309, 0x00}, 2198 {0x430a, 0x00}, 2199 {0x430b, 0xff}, 2200 {0x430c, 0xff}, 2201 {0x430d, 0x00}, 2202 {0x430e, 0x00}, 2203 {0x4315, 0x00}, 2204 {0x4316, 0x00}, 2205 {0x4317, 0x00}, 2206 {0x4318, 0x00}, 2207 {0x4319, 0x00}, 2208 {0x431a, 0x00}, 2209 {0x431b, 0x00}, 2210 {0x431c, 0x00}, 2211 {0x4500, 0x07}, 2212 {0x4501, 0x10}, 2213 {0x4502, 0x00}, 2214 {0x4503, 0x0f}, 2215 {0x4504, 0x80}, 2216 {0x4506, 0x01}, 2217 {0x4509, 0x05}, 2218 {0x450c, 0x00}, 2219 {0x450d, 0x20}, 2220 {0x450e, 0x00}, 2221 {0x450f, 0x00}, 2222 {0x4510, 0x00}, 2223 {0x4523, 0x00}, 2224 {0x4526, 0x00}, 2225 {0x4542, 0x00}, 2226 {0x4543, 0x00}, 2227 {0x4544, 0x00}, 2228 {0x4545, 0x00}, 2229 {0x4546, 0x00}, 2230 {0x4547, 0x10}, 2231 {0x4602, 0x00}, 2232 {0x4603, 0x15}, 2233 {0x460b, 0x07}, 2234 {0x4680, 0x11}, 2235 {0x4686, 0x00}, 2236 {0x4687, 0x00}, 2237 {0x4700, 0x00}, 2238 {0x4800, 0x64}, 2239 {0x4806, 0x40}, 2240 {0x480b, 0x10}, 2241 {0x480c, 0x80}, 2242 {0x480f, 0x32}, 2243 {0x4813, 0xe4}, 2244 {0x4837, 0x14}, 2245 {0x4850, 0x42}, 2246 {0x4884, 0x04}, 2247 {0x4c00, 0xf8}, 2248 {0x4c01, 0x44}, 2249 {0x4c03, 0x00}, 2250 {0x4d00, 0x00}, 2251 {0x4d01, 0x16}, 2252 {0x4d04, 0x10}, 2253 {0x4d05, 0x00}, 2254 {0x4d06, 0x0c}, 2255 {0x4d07, 0x00}, 2256 {0x3d84, 0x04}, 2257 {0x3680, 0xa4}, 2258 {0x3682, 0x80}, 2259 {0x3601, 0x40}, 2260 {0x3602, 0x90}, 2261 {0x3608, 0x0a}, 2262 {0x3938, 0x09}, 2263 {0x3a74, 0x84}, 2264 {0x3a99, 0x84}, 2265 {0x3ab9, 0xa6}, 2266 {0x3aba, 0xba}, 2267 {0x3b12, 0x84}, 2268 {0x3b14, 0xbb}, 2269 {0x3b15, 0xbf}, 2270 {0x3a29, 0x26}, 2271 {0x3a1f, 0x8a}, 2272 {0x3a22, 0x91}, 2273 {0x3a25, 0x96}, 2274 {0x3a28, 0xb4}, 2275 {0x3a2b, 0xba}, 2276 {0x3a2e, 0xbf}, 2277 {0x3a31, 0xc1}, 2278 {0x3a20, 0x05}, 2279 {0x3939, 0x6b}, 2280 {0x3902, 0x10}, 2281 {0x3903, 0x10}, 2282 {0x3904, 0x10}, 2283 {0x3905, 0x10}, 2284 {0x3906, 0x01}, 2285 {0x3907, 0x0b}, 2286 {0x3908, 0x10}, 2287 {0x3909, 0x13}, 2288 {0x360f, 0x99}, 2289 {0x390b, 0x11}, 2290 {0x390c, 0x21}, 2291 {0x390d, 0x32}, 2292 {0x390e, 0x76}, 2293 {0x3911, 0x90}, 2294 {0x3913, 0x90}, 2295 {0x3b3f, 0x9d}, 2296 {0x3b45, 0x9d}, 2297 {0x3b1b, 0xc9}, 2298 {0x3b21, 0xc9}, 2299 {0x3a1a, 0x1c}, 2300 {0x3a23, 0x15}, 2301 {0x3a26, 0x17}, 2302 {0x3a2c, 0x50}, 2303 {0x3a2f, 0x18}, 2304 {0x3a32, 0x4f}, 2305 {0x3ace, 0x01}, 2306 {0x3ad2, 0x01}, 2307 {0x3ad6, 0x01}, 2308 {0x3ada, 0x01}, 2309 {0x3ade, 0x01}, 2310 {0x3ae2, 0x01}, 2311 {0x3aee, 0x01}, 2312 {0x3af2, 0x01}, 2313 {0x3af6, 0x01}, 2314 {0x3afa, 0x01}, 2315 {0x3afe, 0x01}, 2316 {0x3b02, 0x01}, 2317 {0x3b06, 0x01}, 2318 {0x3b0a, 0x01}, 2319 {0x3b0b, 0x00}, 2320 {0x3b0e, 0x01}, 2321 {0x3b0f, 0x00}, 2322 {0x392c, 0x02}, 2323 {0x392d, 0x01}, 2324 {0x392e, 0x04}, 2325 {0x392f, 0x03}, 2326 {0x3930, 0x09}, 2327 {0x3931, 0x07}, 2328 {0x3932, 0x10}, 2329 {0x3933, 0x0d}, 2330 {0x3609, 0x08}, 2331 {0x3921, 0x0f}, 2332 {0x3928, 0x15}, 2333 {0x3929, 0x2a}, 2334 {0x392a, 0x52}, 2335 {0x392b, 0xa3}, 2336 {0x340b, 0x1b}, 2337 {0x3426, 0x10}, 2338 {0x3407, 0x01}, 2339 {0x3404, 0x01}, 2340 {0x3500, 0x00}, 2341 {0x3501, 0x08}, 2342 {0x3502, 0x10}, 2343 {0x3508, 0x04}, 2344 {0x3509, 0x00}, 2345 }; 2346 2347 static const char * const ov08x40_test_pattern_menu[] = { 2348 "Disabled", 2349 "Vertical Color Bar Type 1", 2350 "Vertical Color Bar Type 2", 2351 "Vertical Color Bar Type 3", 2352 "Vertical Color Bar Type 4" 2353 }; 2354 2355 /* Configurations for supported link frequencies */ 2356 #define OV08X40_LINK_FREQ_400MHZ 400000000ULL 2357 2358 #define OV08X40_EXT_CLK 19200000 2359 #define OV08X40_DATA_LANES 4 2360 2361 /* 2362 * pixel_rate = link_freq * data-rate * nr_of_lanes / bits_per_sample 2363 * data rate => double data rate; number of lanes => 4; bits per pixel => 10 2364 */ 2365 static u64 link_freq_to_pixel_rate(u64 f) 2366 { 2367 f *= 2 * OV08X40_DATA_LANES; 2368 do_div(f, 10); 2369 2370 return f; 2371 } 2372 2373 /* Menu items for LINK_FREQ V4L2 control */ 2374 static const s64 link_freq_menu_items[] = { 2375 OV08X40_LINK_FREQ_400MHZ, 2376 }; 2377 2378 /* Link frequency configs */ 2379 static const struct ov08x40_link_freq_config link_freq_configs[] = { 2380 [OV08X40_LINK_FREQ_400MHZ_INDEX] = { 2381 .reg_list = { 2382 .num_of_regs = ARRAY_SIZE(mipi_data_rate_800mbps), 2383 .regs = mipi_data_rate_800mbps, 2384 } 2385 }, 2386 }; 2387 2388 /* Mode configs */ 2389 static const struct ov08x40_mode supported_modes[] = { 2390 { 2391 .width = 3856, 2392 .height = 2416, 2393 .vts_def = OV08X40_VTS_30FPS, 2394 .vts_min = OV08X40_VTS_30FPS, 2395 .hts = 640, 2396 .lanes = 4, 2397 .reg_list = { 2398 .num_of_regs = ARRAY_SIZE(mode_3856x2416_regs), 2399 .regs = mode_3856x2416_regs, 2400 }, 2401 .link_freq_index = OV08X40_LINK_FREQ_400MHZ_INDEX, 2402 }, 2403 { 2404 .width = 1928, 2405 .height = 1208, 2406 .vts_def = OV08X40_VTS_BIN_30FPS, 2407 .vts_min = OV08X40_VTS_BIN_30FPS, 2408 .hts = 720, 2409 .lanes = 4, 2410 .reg_list = { 2411 .num_of_regs = ARRAY_SIZE(mode_1928x1208_regs), 2412 .regs = mode_1928x1208_regs, 2413 }, 2414 .link_freq_index = OV08X40_LINK_FREQ_400MHZ_INDEX, 2415 }, 2416 }; 2417 2418 struct ov08x40 { 2419 struct v4l2_subdev sd; 2420 struct media_pad pad; 2421 2422 struct v4l2_ctrl_handler ctrl_handler; 2423 /* V4L2 Controls */ 2424 struct v4l2_ctrl *link_freq; 2425 struct v4l2_ctrl *pixel_rate; 2426 struct v4l2_ctrl *vblank; 2427 struct v4l2_ctrl *hblank; 2428 struct v4l2_ctrl *exposure; 2429 2430 /* Current mode */ 2431 const struct ov08x40_mode *cur_mode; 2432 2433 /* Mutex for serialized access */ 2434 struct mutex mutex; 2435 2436 /* Streaming on/off */ 2437 bool streaming; 2438 }; 2439 2440 #define to_ov08x40(_sd) container_of(_sd, struct ov08x40, sd) 2441 2442 /* Read registers up to 4 at a time */ 2443 static int ov08x40_read_reg(struct ov08x40 *ov08x, 2444 u16 reg, u32 len, u32 *val) 2445 { 2446 struct i2c_client *client = v4l2_get_subdevdata(&ov08x->sd); 2447 struct i2c_msg msgs[2]; 2448 u8 *data_be_p; 2449 int ret; 2450 __be32 data_be = 0; 2451 __be16 reg_addr_be = cpu_to_be16(reg); 2452 2453 if (len > 4) 2454 return -EINVAL; 2455 2456 data_be_p = (u8 *)&data_be; 2457 /* Write register address */ 2458 msgs[0].addr = client->addr; 2459 msgs[0].flags = 0; 2460 msgs[0].len = 2; 2461 msgs[0].buf = (u8 *)®_addr_be; 2462 2463 /* Read data from register */ 2464 msgs[1].addr = client->addr; 2465 msgs[1].flags = I2C_M_RD; 2466 msgs[1].len = len; 2467 msgs[1].buf = &data_be_p[4 - len]; 2468 2469 ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs)); 2470 if (ret != ARRAY_SIZE(msgs)) 2471 return -EIO; 2472 2473 *val = be32_to_cpu(data_be); 2474 2475 return 0; 2476 } 2477 2478 /* Write registers up to 4 at a time */ 2479 static int ov08x40_write_reg(struct ov08x40 *ov08x, 2480 u16 reg, u32 len, u32 __val) 2481 { 2482 struct i2c_client *client = v4l2_get_subdevdata(&ov08x->sd); 2483 int buf_i, val_i; 2484 u8 buf[6], *val_p; 2485 __be32 val; 2486 2487 if (len > 4) 2488 return -EINVAL; 2489 2490 buf[0] = reg >> 8; 2491 buf[1] = reg & 0xff; 2492 2493 val = cpu_to_be32(__val); 2494 val_p = (u8 *)&val; 2495 buf_i = 2; 2496 val_i = 4 - len; 2497 2498 while (val_i < 4) 2499 buf[buf_i++] = val_p[val_i++]; 2500 2501 if (i2c_master_send(client, buf, len + 2) != len + 2) 2502 return -EIO; 2503 2504 return 0; 2505 } 2506 2507 /* Write a list of registers */ 2508 static int ov08x40_write_regs(struct ov08x40 *ov08x, 2509 const struct ov08x40_reg *regs, u32 len) 2510 { 2511 struct i2c_client *client = v4l2_get_subdevdata(&ov08x->sd); 2512 int ret; 2513 u32 i; 2514 2515 for (i = 0; i < len; i++) { 2516 ret = ov08x40_write_reg(ov08x, regs[i].address, 1, 2517 regs[i].val); 2518 2519 if (ret) { 2520 dev_err_ratelimited(&client->dev, 2521 "Failed to write reg 0x%4.4x. error = %d\n", 2522 regs[i].address, ret); 2523 2524 return ret; 2525 } 2526 } 2527 2528 return 0; 2529 } 2530 2531 static int ov08x40_write_reg_list(struct ov08x40 *ov08x, 2532 const struct ov08x40_reg_list *r_list) 2533 { 2534 return ov08x40_write_regs(ov08x, r_list->regs, r_list->num_of_regs); 2535 } 2536 2537 static int ov08x40_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh) 2538 { 2539 const struct ov08x40_mode *default_mode = &supported_modes[0]; 2540 struct ov08x40 *ov08x = to_ov08x40(sd); 2541 struct v4l2_mbus_framefmt *try_fmt = 2542 v4l2_subdev_get_try_format(sd, fh->state, 0); 2543 2544 mutex_lock(&ov08x->mutex); 2545 2546 /* Initialize try_fmt */ 2547 try_fmt->width = default_mode->width; 2548 try_fmt->height = default_mode->height; 2549 try_fmt->code = MEDIA_BUS_FMT_SGRBG10_1X10; 2550 try_fmt->field = V4L2_FIELD_NONE; 2551 2552 /* No crop or compose */ 2553 mutex_unlock(&ov08x->mutex); 2554 2555 return 0; 2556 } 2557 2558 static int ov08x40_update_digital_gain(struct ov08x40 *ov08x, u32 d_gain) 2559 { 2560 int ret; 2561 u32 val; 2562 2563 /* 2564 * 0x350C[1:0], 0x350B[7:0], 0x350A[4:0] 2565 */ 2566 2567 val = (d_gain & OV08X40_DGTL_GAIN_L_MASK) << OV08X40_DGTL_GAIN_L_SHIFT; 2568 ret = ov08x40_write_reg(ov08x, OV08X40_REG_DGTL_GAIN_L, 2569 OV08X40_REG_VALUE_08BIT, val); 2570 if (ret) 2571 return ret; 2572 2573 val = (d_gain >> OV08X40_DGTL_GAIN_M_SHIFT) & OV08X40_DGTL_GAIN_M_MASK; 2574 ret = ov08x40_write_reg(ov08x, OV08X40_REG_DGTL_GAIN_M, 2575 OV08X40_REG_VALUE_08BIT, val); 2576 if (ret) 2577 return ret; 2578 2579 val = (d_gain >> OV08X40_DGTL_GAIN_H_SHIFT) & OV08X40_DGTL_GAIN_H_MASK; 2580 2581 return ov08x40_write_reg(ov08x, OV08X40_REG_DGTL_GAIN_H, 2582 OV08X40_REG_VALUE_08BIT, val); 2583 } 2584 2585 static int ov08x40_enable_test_pattern(struct ov08x40 *ov08x, u32 pattern) 2586 { 2587 int ret; 2588 u32 val; 2589 2590 ret = ov08x40_read_reg(ov08x, OV08X40_REG_TEST_PATTERN, 2591 OV08X40_REG_VALUE_08BIT, &val); 2592 if (ret) 2593 return ret; 2594 2595 if (pattern) { 2596 ret = ov08x40_read_reg(ov08x, OV08X40_REG_ISP, 2597 OV08X40_REG_VALUE_08BIT, &val); 2598 if (ret) 2599 return ret; 2600 2601 ret = ov08x40_write_reg(ov08x, OV08X40_REG_ISP, 2602 OV08X40_REG_VALUE_08BIT, 2603 val | BIT(1)); 2604 if (ret) 2605 return ret; 2606 2607 ret = ov08x40_read_reg(ov08x, OV08X40_REG_SHORT_TEST_PATTERN, 2608 OV08X40_REG_VALUE_08BIT, &val); 2609 if (ret) 2610 return ret; 2611 2612 ret = ov08x40_write_reg(ov08x, OV08X40_REG_SHORT_TEST_PATTERN, 2613 OV08X40_REG_VALUE_08BIT, 2614 val | BIT(0)); 2615 if (ret) 2616 return ret; 2617 2618 ret = ov08x40_read_reg(ov08x, OV08X40_REG_TEST_PATTERN, 2619 OV08X40_REG_VALUE_08BIT, &val); 2620 if (ret) 2621 return ret; 2622 2623 val &= OV08X40_TEST_PATTERN_MASK; 2624 val |= ((pattern - 1) << OV08X40_TEST_PATTERN_BAR_SHIFT) | 2625 OV08X40_TEST_PATTERN_ENABLE; 2626 } else { 2627 val &= ~OV08X40_TEST_PATTERN_ENABLE; 2628 } 2629 2630 return ov08x40_write_reg(ov08x, OV08X40_REG_TEST_PATTERN, 2631 OV08X40_REG_VALUE_08BIT, val); 2632 } 2633 2634 static int ov08x40_set_ctrl_hflip(struct ov08x40 *ov08x, u32 ctrl_val) 2635 { 2636 int ret; 2637 u32 val; 2638 2639 ret = ov08x40_read_reg(ov08x, OV08X40_REG_MIRROR, 2640 OV08X40_REG_VALUE_08BIT, &val); 2641 if (ret) 2642 return ret; 2643 2644 return ov08x40_write_reg(ov08x, OV08X40_REG_MIRROR, 2645 OV08X40_REG_VALUE_08BIT, 2646 ctrl_val ? val | BIT(2) : val & ~BIT(2)); 2647 } 2648 2649 static int ov08x40_set_ctrl_vflip(struct ov08x40 *ov08x, u32 ctrl_val) 2650 { 2651 int ret; 2652 u32 val; 2653 2654 ret = ov08x40_read_reg(ov08x, OV08X40_REG_VFLIP, 2655 OV08X40_REG_VALUE_08BIT, &val); 2656 if (ret) 2657 return ret; 2658 2659 return ov08x40_write_reg(ov08x, OV08X40_REG_VFLIP, 2660 OV08X40_REG_VALUE_08BIT, 2661 ctrl_val ? val | BIT(2) : val & ~BIT(2)); 2662 } 2663 2664 static int ov08x40_set_ctrl(struct v4l2_ctrl *ctrl) 2665 { 2666 struct ov08x40 *ov08x = container_of(ctrl->handler, 2667 struct ov08x40, ctrl_handler); 2668 struct i2c_client *client = v4l2_get_subdevdata(&ov08x->sd); 2669 s64 max; 2670 int ret = 0; 2671 2672 /* Propagate change of current control to all related controls */ 2673 switch (ctrl->id) { 2674 case V4L2_CID_VBLANK: 2675 /* Update max exposure while meeting expected vblanking */ 2676 max = ov08x->cur_mode->height + ctrl->val - OV08X40_EXPOSURE_MAX_MARGIN; 2677 __v4l2_ctrl_modify_range(ov08x->exposure, 2678 ov08x->exposure->minimum, 2679 max, ov08x->exposure->step, max); 2680 break; 2681 } 2682 2683 /* 2684 * Applying V4L2 control value only happens 2685 * when power is up for streaming 2686 */ 2687 if (!pm_runtime_get_if_in_use(&client->dev)) 2688 return 0; 2689 2690 switch (ctrl->id) { 2691 case V4L2_CID_ANALOGUE_GAIN: 2692 ret = ov08x40_write_reg(ov08x, OV08X40_REG_ANALOG_GAIN, 2693 OV08X40_REG_VALUE_16BIT, 2694 ctrl->val << 1); 2695 break; 2696 case V4L2_CID_DIGITAL_GAIN: 2697 ret = ov08x40_update_digital_gain(ov08x, ctrl->val); 2698 break; 2699 case V4L2_CID_EXPOSURE: 2700 ret = ov08x40_write_reg(ov08x, OV08X40_REG_EXPOSURE, 2701 OV08X40_REG_VALUE_24BIT, 2702 ctrl->val); 2703 break; 2704 case V4L2_CID_VBLANK: 2705 ret = ov08x40_write_reg(ov08x, OV08X40_REG_VTS, 2706 OV08X40_REG_VALUE_16BIT, 2707 ov08x->cur_mode->height 2708 + ctrl->val); 2709 break; 2710 case V4L2_CID_TEST_PATTERN: 2711 ret = ov08x40_enable_test_pattern(ov08x, ctrl->val); 2712 break; 2713 case V4L2_CID_HFLIP: 2714 ov08x40_set_ctrl_hflip(ov08x, ctrl->val); 2715 break; 2716 case V4L2_CID_VFLIP: 2717 ov08x40_set_ctrl_vflip(ov08x, ctrl->val); 2718 break; 2719 default: 2720 dev_info(&client->dev, 2721 "ctrl(id:0x%x,val:0x%x) is not handled\n", 2722 ctrl->id, ctrl->val); 2723 break; 2724 } 2725 2726 pm_runtime_put(&client->dev); 2727 2728 return ret; 2729 } 2730 2731 static const struct v4l2_ctrl_ops ov08x40_ctrl_ops = { 2732 .s_ctrl = ov08x40_set_ctrl, 2733 }; 2734 2735 static int ov08x40_enum_mbus_code(struct v4l2_subdev *sd, 2736 struct v4l2_subdev_state *sd_state, 2737 struct v4l2_subdev_mbus_code_enum *code) 2738 { 2739 /* Only one bayer order(GRBG) is supported */ 2740 if (code->index > 0) 2741 return -EINVAL; 2742 2743 code->code = MEDIA_BUS_FMT_SGRBG10_1X10; 2744 2745 return 0; 2746 } 2747 2748 static int ov08x40_enum_frame_size(struct v4l2_subdev *sd, 2749 struct v4l2_subdev_state *sd_state, 2750 struct v4l2_subdev_frame_size_enum *fse) 2751 { 2752 if (fse->index >= ARRAY_SIZE(supported_modes)) 2753 return -EINVAL; 2754 2755 if (fse->code != MEDIA_BUS_FMT_SGRBG10_1X10) 2756 return -EINVAL; 2757 2758 fse->min_width = supported_modes[fse->index].width; 2759 fse->max_width = fse->min_width; 2760 fse->min_height = supported_modes[fse->index].height; 2761 fse->max_height = fse->min_height; 2762 2763 return 0; 2764 } 2765 2766 static void ov08x40_update_pad_format(const struct ov08x40_mode *mode, 2767 struct v4l2_subdev_format *fmt) 2768 { 2769 fmt->format.width = mode->width; 2770 fmt->format.height = mode->height; 2771 fmt->format.code = MEDIA_BUS_FMT_SGRBG10_1X10; 2772 fmt->format.field = V4L2_FIELD_NONE; 2773 } 2774 2775 static int ov08x40_do_get_pad_format(struct ov08x40 *ov08x, 2776 struct v4l2_subdev_state *sd_state, 2777 struct v4l2_subdev_format *fmt) 2778 { 2779 struct v4l2_mbus_framefmt *framefmt; 2780 struct v4l2_subdev *sd = &ov08x->sd; 2781 2782 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) { 2783 framefmt = v4l2_subdev_get_try_format(sd, sd_state, fmt->pad); 2784 fmt->format = *framefmt; 2785 } else { 2786 ov08x40_update_pad_format(ov08x->cur_mode, fmt); 2787 } 2788 2789 return 0; 2790 } 2791 2792 static int ov08x40_get_pad_format(struct v4l2_subdev *sd, 2793 struct v4l2_subdev_state *sd_state, 2794 struct v4l2_subdev_format *fmt) 2795 { 2796 struct ov08x40 *ov08x = to_ov08x40(sd); 2797 int ret; 2798 2799 mutex_lock(&ov08x->mutex); 2800 ret = ov08x40_do_get_pad_format(ov08x, sd_state, fmt); 2801 mutex_unlock(&ov08x->mutex); 2802 2803 return ret; 2804 } 2805 2806 static int 2807 ov08x40_set_pad_format(struct v4l2_subdev *sd, 2808 struct v4l2_subdev_state *sd_state, 2809 struct v4l2_subdev_format *fmt) 2810 { 2811 struct ov08x40 *ov08x = to_ov08x40(sd); 2812 const struct ov08x40_mode *mode; 2813 struct v4l2_mbus_framefmt *framefmt; 2814 s32 vblank_def; 2815 s32 vblank_min; 2816 s64 h_blank; 2817 s64 pixel_rate; 2818 s64 link_freq; 2819 2820 mutex_lock(&ov08x->mutex); 2821 2822 /* Only one raw bayer(GRBG) order is supported */ 2823 if (fmt->format.code != MEDIA_BUS_FMT_SGRBG10_1X10) 2824 fmt->format.code = MEDIA_BUS_FMT_SGRBG10_1X10; 2825 2826 mode = v4l2_find_nearest_size(supported_modes, 2827 ARRAY_SIZE(supported_modes), 2828 width, height, 2829 fmt->format.width, fmt->format.height); 2830 ov08x40_update_pad_format(mode, fmt); 2831 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) { 2832 framefmt = v4l2_subdev_get_try_format(sd, sd_state, fmt->pad); 2833 *framefmt = fmt->format; 2834 } else { 2835 ov08x->cur_mode = mode; 2836 __v4l2_ctrl_s_ctrl(ov08x->link_freq, mode->link_freq_index); 2837 link_freq = link_freq_menu_items[mode->link_freq_index]; 2838 pixel_rate = link_freq_to_pixel_rate(link_freq); 2839 __v4l2_ctrl_s_ctrl_int64(ov08x->pixel_rate, pixel_rate); 2840 2841 /* Update limits and set FPS to default */ 2842 vblank_def = ov08x->cur_mode->vts_def - 2843 ov08x->cur_mode->height; 2844 vblank_min = ov08x->cur_mode->vts_min - 2845 ov08x->cur_mode->height; 2846 __v4l2_ctrl_modify_range(ov08x->vblank, vblank_min, 2847 OV08X40_VTS_MAX 2848 - ov08x->cur_mode->height, 2849 1, 2850 vblank_def); 2851 __v4l2_ctrl_s_ctrl(ov08x->vblank, vblank_def); 2852 h_blank = ov08x->cur_mode->hts; 2853 __v4l2_ctrl_modify_range(ov08x->hblank, h_blank, 2854 h_blank, 1, h_blank); 2855 } 2856 2857 mutex_unlock(&ov08x->mutex); 2858 2859 return 0; 2860 } 2861 2862 static int ov08x40_start_streaming(struct ov08x40 *ov08x) 2863 { 2864 struct i2c_client *client = v4l2_get_subdevdata(&ov08x->sd); 2865 const struct ov08x40_reg_list *reg_list; 2866 int ret, link_freq_index; 2867 2868 /* Get out of from software reset */ 2869 ret = ov08x40_write_reg(ov08x, OV08X40_REG_SOFTWARE_RST, 2870 OV08X40_REG_VALUE_08BIT, OV08X40_SOFTWARE_RST); 2871 if (ret) { 2872 dev_err(&client->dev, "%s failed to set powerup registers\n", 2873 __func__); 2874 return ret; 2875 } 2876 2877 link_freq_index = ov08x->cur_mode->link_freq_index; 2878 reg_list = &link_freq_configs[link_freq_index].reg_list; 2879 2880 ret = ov08x40_write_reg_list(ov08x, reg_list); 2881 if (ret) { 2882 dev_err(&client->dev, "%s failed to set plls\n", __func__); 2883 return ret; 2884 } 2885 2886 /* Apply default values of current mode */ 2887 reg_list = &ov08x->cur_mode->reg_list; 2888 ret = ov08x40_write_reg_list(ov08x, reg_list); 2889 if (ret) { 2890 dev_err(&client->dev, "%s failed to set mode\n", __func__); 2891 return ret; 2892 } 2893 2894 /* Apply customized values from user */ 2895 ret = __v4l2_ctrl_handler_setup(ov08x->sd.ctrl_handler); 2896 if (ret) 2897 return ret; 2898 2899 return ov08x40_write_reg(ov08x, OV08X40_REG_MODE_SELECT, 2900 OV08X40_REG_VALUE_08BIT, 2901 OV08X40_MODE_STREAMING); 2902 } 2903 2904 /* Stop streaming */ 2905 static int ov08x40_stop_streaming(struct ov08x40 *ov08x) 2906 { 2907 return ov08x40_write_reg(ov08x, OV08X40_REG_MODE_SELECT, 2908 OV08X40_REG_VALUE_08BIT, OV08X40_MODE_STANDBY); 2909 } 2910 2911 static int ov08x40_set_stream(struct v4l2_subdev *sd, int enable) 2912 { 2913 struct ov08x40 *ov08x = to_ov08x40(sd); 2914 struct i2c_client *client = v4l2_get_subdevdata(sd); 2915 int ret = 0; 2916 2917 mutex_lock(&ov08x->mutex); 2918 if (ov08x->streaming == enable) { 2919 mutex_unlock(&ov08x->mutex); 2920 return 0; 2921 } 2922 2923 if (enable) { 2924 ret = pm_runtime_resume_and_get(&client->dev); 2925 if (ret < 0) 2926 goto err_unlock; 2927 2928 /* 2929 * Apply default & customized values 2930 * and then start streaming. 2931 */ 2932 ret = ov08x40_start_streaming(ov08x); 2933 if (ret) 2934 goto err_rpm_put; 2935 } else { 2936 ov08x40_stop_streaming(ov08x); 2937 pm_runtime_put(&client->dev); 2938 } 2939 2940 ov08x->streaming = enable; 2941 mutex_unlock(&ov08x->mutex); 2942 2943 return ret; 2944 2945 err_rpm_put: 2946 pm_runtime_put(&client->dev); 2947 err_unlock: 2948 mutex_unlock(&ov08x->mutex); 2949 2950 return ret; 2951 } 2952 2953 static int __maybe_unused ov08x40_suspend(struct device *dev) 2954 { 2955 struct v4l2_subdev *sd = dev_get_drvdata(dev); 2956 struct ov08x40 *ov08x = to_ov08x40(sd); 2957 2958 if (ov08x->streaming) 2959 ov08x40_stop_streaming(ov08x); 2960 2961 return 0; 2962 } 2963 2964 static int __maybe_unused ov08x40_resume(struct device *dev) 2965 { 2966 struct v4l2_subdev *sd = dev_get_drvdata(dev); 2967 struct ov08x40 *ov08x = to_ov08x40(sd); 2968 int ret; 2969 2970 if (ov08x->streaming) { 2971 ret = ov08x40_start_streaming(ov08x); 2972 if (ret) 2973 goto error; 2974 } 2975 2976 return 0; 2977 2978 error: 2979 ov08x40_stop_streaming(ov08x); 2980 ov08x->streaming = false; 2981 return ret; 2982 } 2983 2984 /* Verify chip ID */ 2985 static int ov08x40_identify_module(struct ov08x40 *ov08x) 2986 { 2987 struct i2c_client *client = v4l2_get_subdevdata(&ov08x->sd); 2988 int ret; 2989 u32 val; 2990 2991 ret = ov08x40_read_reg(ov08x, OV08X40_REG_CHIP_ID, 2992 OV08X40_REG_VALUE_24BIT, &val); 2993 if (ret) 2994 return ret; 2995 2996 if (val != OV08X40_CHIP_ID) { 2997 dev_err(&client->dev, "chip id mismatch: %x!=%x\n", 2998 OV08X40_CHIP_ID, val); 2999 return -EIO; 3000 } 3001 3002 return 0; 3003 } 3004 3005 static const struct v4l2_subdev_video_ops ov08x40_video_ops = { 3006 .s_stream = ov08x40_set_stream, 3007 }; 3008 3009 static const struct v4l2_subdev_pad_ops ov08x40_pad_ops = { 3010 .enum_mbus_code = ov08x40_enum_mbus_code, 3011 .get_fmt = ov08x40_get_pad_format, 3012 .set_fmt = ov08x40_set_pad_format, 3013 .enum_frame_size = ov08x40_enum_frame_size, 3014 }; 3015 3016 static const struct v4l2_subdev_ops ov08x40_subdev_ops = { 3017 .video = &ov08x40_video_ops, 3018 .pad = &ov08x40_pad_ops, 3019 }; 3020 3021 static const struct media_entity_operations ov08x40_subdev_entity_ops = { 3022 .link_validate = v4l2_subdev_link_validate, 3023 }; 3024 3025 static const struct v4l2_subdev_internal_ops ov08x40_internal_ops = { 3026 .open = ov08x40_open, 3027 }; 3028 3029 static int ov08x40_init_controls(struct ov08x40 *ov08x) 3030 { 3031 struct i2c_client *client = v4l2_get_subdevdata(&ov08x->sd); 3032 struct v4l2_fwnode_device_properties props; 3033 struct v4l2_ctrl_handler *ctrl_hdlr; 3034 s64 exposure_max; 3035 s64 vblank_def; 3036 s64 vblank_min; 3037 s64 hblank; 3038 s64 pixel_rate_min; 3039 s64 pixel_rate_max; 3040 const struct ov08x40_mode *mode; 3041 u32 max; 3042 int ret; 3043 3044 ctrl_hdlr = &ov08x->ctrl_handler; 3045 ret = v4l2_ctrl_handler_init(ctrl_hdlr, 10); 3046 if (ret) 3047 return ret; 3048 3049 mutex_init(&ov08x->mutex); 3050 ctrl_hdlr->lock = &ov08x->mutex; 3051 max = ARRAY_SIZE(link_freq_menu_items) - 1; 3052 ov08x->link_freq = v4l2_ctrl_new_int_menu(ctrl_hdlr, 3053 &ov08x40_ctrl_ops, 3054 V4L2_CID_LINK_FREQ, 3055 max, 3056 0, 3057 link_freq_menu_items); 3058 if (ov08x->link_freq) 3059 ov08x->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY; 3060 3061 pixel_rate_max = link_freq_to_pixel_rate(link_freq_menu_items[0]); 3062 pixel_rate_min = 0; 3063 /* By default, PIXEL_RATE is read only */ 3064 ov08x->pixel_rate = v4l2_ctrl_new_std(ctrl_hdlr, &ov08x40_ctrl_ops, 3065 V4L2_CID_PIXEL_RATE, 3066 pixel_rate_min, pixel_rate_max, 3067 1, pixel_rate_max); 3068 3069 mode = ov08x->cur_mode; 3070 vblank_def = mode->vts_def - mode->height; 3071 vblank_min = mode->vts_min - mode->height; 3072 ov08x->vblank = v4l2_ctrl_new_std(ctrl_hdlr, &ov08x40_ctrl_ops, 3073 V4L2_CID_VBLANK, 3074 vblank_min, 3075 OV08X40_VTS_MAX - mode->height, 1, 3076 vblank_def); 3077 3078 hblank = ov08x->cur_mode->hts; 3079 ov08x->hblank = v4l2_ctrl_new_std(ctrl_hdlr, &ov08x40_ctrl_ops, 3080 V4L2_CID_HBLANK, 3081 hblank, hblank, 1, hblank); 3082 if (ov08x->hblank) 3083 ov08x->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY; 3084 3085 exposure_max = mode->vts_def - OV08X40_EXPOSURE_MAX_MARGIN; 3086 ov08x->exposure = v4l2_ctrl_new_std(ctrl_hdlr, &ov08x40_ctrl_ops, 3087 V4L2_CID_EXPOSURE, 3088 OV08X40_EXPOSURE_MIN, 3089 exposure_max, OV08X40_EXPOSURE_STEP, 3090 exposure_max); 3091 3092 v4l2_ctrl_new_std(ctrl_hdlr, &ov08x40_ctrl_ops, V4L2_CID_ANALOGUE_GAIN, 3093 OV08X40_ANA_GAIN_MIN, OV08X40_ANA_GAIN_MAX, 3094 OV08X40_ANA_GAIN_STEP, OV08X40_ANA_GAIN_DEFAULT); 3095 3096 /* Digital gain */ 3097 v4l2_ctrl_new_std(ctrl_hdlr, &ov08x40_ctrl_ops, V4L2_CID_DIGITAL_GAIN, 3098 OV08X40_DGTL_GAIN_MIN, OV08X40_DGTL_GAIN_MAX, 3099 OV08X40_DGTL_GAIN_STEP, OV08X40_DGTL_GAIN_DEFAULT); 3100 3101 v4l2_ctrl_new_std_menu_items(ctrl_hdlr, &ov08x40_ctrl_ops, 3102 V4L2_CID_TEST_PATTERN, 3103 ARRAY_SIZE(ov08x40_test_pattern_menu) - 1, 3104 0, 0, ov08x40_test_pattern_menu); 3105 3106 v4l2_ctrl_new_std(ctrl_hdlr, &ov08x40_ctrl_ops, 3107 V4L2_CID_HFLIP, 0, 1, 1, 0); 3108 v4l2_ctrl_new_std(ctrl_hdlr, &ov08x40_ctrl_ops, 3109 V4L2_CID_VFLIP, 0, 1, 1, 0); 3110 3111 if (ctrl_hdlr->error) { 3112 ret = ctrl_hdlr->error; 3113 dev_err(&client->dev, "%s control init failed (%d)\n", 3114 __func__, ret); 3115 goto error; 3116 } 3117 3118 ret = v4l2_fwnode_device_parse(&client->dev, &props); 3119 if (ret) 3120 goto error; 3121 3122 ret = v4l2_ctrl_new_fwnode_properties(ctrl_hdlr, &ov08x40_ctrl_ops, 3123 &props); 3124 if (ret) 3125 goto error; 3126 3127 ov08x->sd.ctrl_handler = ctrl_hdlr; 3128 3129 return 0; 3130 3131 error: 3132 v4l2_ctrl_handler_free(ctrl_hdlr); 3133 mutex_destroy(&ov08x->mutex); 3134 3135 return ret; 3136 } 3137 3138 static void ov08x40_free_controls(struct ov08x40 *ov08x) 3139 { 3140 v4l2_ctrl_handler_free(ov08x->sd.ctrl_handler); 3141 mutex_destroy(&ov08x->mutex); 3142 } 3143 3144 static int ov08x40_check_hwcfg(struct device *dev) 3145 { 3146 struct v4l2_fwnode_endpoint bus_cfg = { 3147 .bus_type = V4L2_MBUS_CSI2_DPHY 3148 }; 3149 struct fwnode_handle *ep; 3150 struct fwnode_handle *fwnode = dev_fwnode(dev); 3151 unsigned int i, j; 3152 int ret; 3153 u32 ext_clk; 3154 3155 if (!fwnode) 3156 return -ENXIO; 3157 3158 ret = fwnode_property_read_u32(dev_fwnode(dev), "clock-frequency", 3159 &ext_clk); 3160 if (ret) { 3161 dev_err(dev, "can't get clock frequency"); 3162 return ret; 3163 } 3164 3165 if (ext_clk != OV08X40_EXT_CLK) { 3166 dev_err(dev, "external clock %d is not supported", 3167 ext_clk); 3168 return -EINVAL; 3169 } 3170 3171 ep = fwnode_graph_get_next_endpoint(fwnode, NULL); 3172 if (!ep) 3173 return -ENXIO; 3174 3175 ret = v4l2_fwnode_endpoint_alloc_parse(ep, &bus_cfg); 3176 fwnode_handle_put(ep); 3177 if (ret) 3178 return ret; 3179 3180 if (bus_cfg.bus.mipi_csi2.num_data_lanes != OV08X40_DATA_LANES) { 3181 dev_err(dev, "number of CSI2 data lanes %d is not supported", 3182 bus_cfg.bus.mipi_csi2.num_data_lanes); 3183 ret = -EINVAL; 3184 goto out_err; 3185 } 3186 3187 if (!bus_cfg.nr_of_link_frequencies) { 3188 dev_err(dev, "no link frequencies defined"); 3189 ret = -EINVAL; 3190 goto out_err; 3191 } 3192 3193 for (i = 0; i < ARRAY_SIZE(link_freq_menu_items); i++) { 3194 for (j = 0; j < bus_cfg.nr_of_link_frequencies; j++) { 3195 if (link_freq_menu_items[i] == 3196 bus_cfg.link_frequencies[j]) 3197 break; 3198 } 3199 3200 if (j == bus_cfg.nr_of_link_frequencies) { 3201 dev_err(dev, "no link frequency %lld supported", 3202 link_freq_menu_items[i]); 3203 ret = -EINVAL; 3204 goto out_err; 3205 } 3206 } 3207 3208 out_err: 3209 v4l2_fwnode_endpoint_free(&bus_cfg); 3210 3211 return ret; 3212 } 3213 3214 static int ov08x40_probe(struct i2c_client *client) 3215 { 3216 struct ov08x40 *ov08x; 3217 int ret; 3218 3219 /* Check HW config */ 3220 ret = ov08x40_check_hwcfg(&client->dev); 3221 if (ret) { 3222 dev_err(&client->dev, "failed to check hwcfg: %d", ret); 3223 return ret; 3224 } 3225 3226 ov08x = devm_kzalloc(&client->dev, sizeof(*ov08x), GFP_KERNEL); 3227 if (!ov08x) 3228 return -ENOMEM; 3229 3230 /* Initialize subdev */ 3231 v4l2_i2c_subdev_init(&ov08x->sd, client, &ov08x40_subdev_ops); 3232 3233 /* Check module identity */ 3234 ret = ov08x40_identify_module(ov08x); 3235 if (ret) { 3236 dev_err(&client->dev, "failed to find sensor: %d\n", ret); 3237 return ret; 3238 } 3239 3240 /* Set default mode to max resolution */ 3241 ov08x->cur_mode = &supported_modes[0]; 3242 3243 ret = ov08x40_init_controls(ov08x); 3244 if (ret) 3245 return ret; 3246 3247 /* Initialize subdev */ 3248 ov08x->sd.internal_ops = &ov08x40_internal_ops; 3249 ov08x->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; 3250 ov08x->sd.entity.ops = &ov08x40_subdev_entity_ops; 3251 ov08x->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR; 3252 3253 /* Initialize source pad */ 3254 ov08x->pad.flags = MEDIA_PAD_FL_SOURCE; 3255 ret = media_entity_pads_init(&ov08x->sd.entity, 1, &ov08x->pad); 3256 if (ret) { 3257 dev_err(&client->dev, "%s failed:%d\n", __func__, ret); 3258 goto error_handler_free; 3259 } 3260 3261 ret = v4l2_async_register_subdev_sensor(&ov08x->sd); 3262 if (ret < 0) 3263 goto error_media_entity; 3264 3265 /* 3266 * Device is already turned on by i2c-core with ACPI domain PM. 3267 * Enable runtime PM and turn off the device. 3268 */ 3269 pm_runtime_set_active(&client->dev); 3270 pm_runtime_enable(&client->dev); 3271 pm_runtime_idle(&client->dev); 3272 3273 return 0; 3274 3275 error_media_entity: 3276 media_entity_cleanup(&ov08x->sd.entity); 3277 3278 error_handler_free: 3279 ov08x40_free_controls(ov08x); 3280 3281 return ret; 3282 } 3283 3284 static void ov08x40_remove(struct i2c_client *client) 3285 { 3286 struct v4l2_subdev *sd = i2c_get_clientdata(client); 3287 struct ov08x40 *ov08x = to_ov08x40(sd); 3288 3289 v4l2_async_unregister_subdev(sd); 3290 media_entity_cleanup(&sd->entity); 3291 ov08x40_free_controls(ov08x); 3292 3293 pm_runtime_disable(&client->dev); 3294 pm_runtime_set_suspended(&client->dev); 3295 } 3296 3297 static const struct dev_pm_ops ov08x40_pm_ops = { 3298 SET_SYSTEM_SLEEP_PM_OPS(ov08x40_suspend, ov08x40_resume) 3299 }; 3300 3301 #ifdef CONFIG_ACPI 3302 static const struct acpi_device_id ov08x40_acpi_ids[] = { 3303 {"OVTI08F4"}, 3304 { /* sentinel */ } 3305 }; 3306 3307 MODULE_DEVICE_TABLE(acpi, ov08x40_acpi_ids); 3308 #endif 3309 3310 static struct i2c_driver ov08x40_i2c_driver = { 3311 .driver = { 3312 .name = "ov08x40", 3313 .pm = &ov08x40_pm_ops, 3314 .acpi_match_table = ACPI_PTR(ov08x40_acpi_ids), 3315 }, 3316 .probe = ov08x40_probe, 3317 .remove = ov08x40_remove, 3318 }; 3319 3320 module_i2c_driver(ov08x40_i2c_driver); 3321 3322 MODULE_AUTHOR("Jason Chen <jason.z.chen@intel.com>"); 3323 MODULE_AUTHOR("Shawn Tu"); 3324 MODULE_DESCRIPTION("OmniVision OV08X40 sensor driver"); 3325 MODULE_LICENSE("GPL"); 3326