1472377feSShawn Tu // SPDX-License-Identifier: GPL-2.0
2472377feSShawn Tu // Copyright (c) 2022 Intel Corporation.
3472377feSShawn Tu
4472377feSShawn Tu #include <asm/unaligned.h>
5472377feSShawn Tu #include <linux/acpi.h>
6472377feSShawn Tu #include <linux/delay.h>
7472377feSShawn Tu #include <linux/i2c.h>
8472377feSShawn Tu #include <linux/module.h>
9472377feSShawn Tu #include <linux/pm_runtime.h>
10472377feSShawn Tu #include <media/v4l2-ctrls.h>
11472377feSShawn Tu #include <media/v4l2-device.h>
12472377feSShawn Tu #include <media/v4l2-fwnode.h>
13472377feSShawn Tu
14472377feSShawn Tu #define OG01A1B_REG_VALUE_08BIT 1
15472377feSShawn Tu #define OG01A1B_REG_VALUE_16BIT 2
16472377feSShawn Tu #define OG01A1B_REG_VALUE_24BIT 3
17472377feSShawn Tu
18472377feSShawn Tu #define OG01A1B_LINK_FREQ_500MHZ 500000000ULL
19472377feSShawn Tu #define OG01A1B_SCLK 120000000LL
20472377feSShawn Tu #define OG01A1B_MCLK 19200000
21472377feSShawn Tu #define OG01A1B_DATA_LANES 2
22472377feSShawn Tu #define OG01A1B_RGB_DEPTH 10
23472377feSShawn Tu
24472377feSShawn Tu #define OG01A1B_REG_CHIP_ID 0x300a
25472377feSShawn Tu #define OG01A1B_CHIP_ID 0x470141
26472377feSShawn Tu
27472377feSShawn Tu #define OG01A1B_REG_MODE_SELECT 0x0100
28472377feSShawn Tu #define OG01A1B_MODE_STANDBY 0x00
29472377feSShawn Tu #define OG01A1B_MODE_STREAMING 0x01
30472377feSShawn Tu
31472377feSShawn Tu /* vertical-timings from sensor */
32472377feSShawn Tu #define OG01A1B_REG_VTS 0x380e
33472377feSShawn Tu #define OG01A1B_VTS_120FPS 0x0498
34472377feSShawn Tu #define OG01A1B_VTS_120FPS_MIN 0x0498
35472377feSShawn Tu #define OG01A1B_VTS_MAX 0x7fff
36472377feSShawn Tu
37472377feSShawn Tu /* horizontal-timings from sensor */
38472377feSShawn Tu #define OG01A1B_REG_HTS 0x380c
39472377feSShawn Tu
40472377feSShawn Tu /* Exposure controls from sensor */
41472377feSShawn Tu #define OG01A1B_REG_EXPOSURE 0x3501
42472377feSShawn Tu #define OG01A1B_EXPOSURE_MIN 1
43472377feSShawn Tu #define OG01A1B_EXPOSURE_MAX_MARGIN 14
44472377feSShawn Tu #define OG01A1B_EXPOSURE_STEP 1
45472377feSShawn Tu
46472377feSShawn Tu /* Analog gain controls from sensor */
47472377feSShawn Tu #define OG01A1B_REG_ANALOG_GAIN 0x3508
48472377feSShawn Tu #define OG01A1B_ANAL_GAIN_MIN 16
49472377feSShawn Tu #define OG01A1B_ANAL_GAIN_MAX 248 /* Max = 15.5x */
50472377feSShawn Tu #define OG01A1B_ANAL_GAIN_STEP 1
51472377feSShawn Tu
52472377feSShawn Tu /* Digital gain controls from sensor */
53472377feSShawn Tu #define OG01A1B_REG_DIG_GAIN 0x350a
54472377feSShawn Tu #define OG01A1B_DGTL_GAIN_MIN 1024
55472377feSShawn Tu #define OG01A1B_DGTL_GAIN_MAX 16384 /* Max = 16x */
56472377feSShawn Tu #define OG01A1B_DGTL_GAIN_STEP 1
57472377feSShawn Tu #define OG01A1B_DGTL_GAIN_DEFAULT 1024
58472377feSShawn Tu
59472377feSShawn Tu /* Group Access */
60472377feSShawn Tu #define OG01A1B_REG_GROUP_ACCESS 0x3208
61472377feSShawn Tu #define OG01A1B_GROUP_HOLD_START 0x0
62472377feSShawn Tu #define OG01A1B_GROUP_HOLD_END 0x10
63472377feSShawn Tu #define OG01A1B_GROUP_HOLD_LAUNCH 0xa0
64472377feSShawn Tu
65472377feSShawn Tu /* Test Pattern Control */
66472377feSShawn Tu #define OG01A1B_REG_TEST_PATTERN 0x5100
67472377feSShawn Tu #define OG01A1B_TEST_PATTERN_ENABLE BIT(7)
68472377feSShawn Tu #define OG01A1B_TEST_PATTERN_BAR_SHIFT 2
69472377feSShawn Tu
70472377feSShawn Tu #define to_og01a1b(_sd) container_of(_sd, struct og01a1b, sd)
71472377feSShawn Tu
72472377feSShawn Tu enum {
73472377feSShawn Tu OG01A1B_LINK_FREQ_1000MBPS,
74472377feSShawn Tu };
75472377feSShawn Tu
76472377feSShawn Tu struct og01a1b_reg {
77472377feSShawn Tu u16 address;
78472377feSShawn Tu u8 val;
79472377feSShawn Tu };
80472377feSShawn Tu
81472377feSShawn Tu struct og01a1b_reg_list {
82472377feSShawn Tu u32 num_of_regs;
83472377feSShawn Tu const struct og01a1b_reg *regs;
84472377feSShawn Tu };
85472377feSShawn Tu
86472377feSShawn Tu struct og01a1b_link_freq_config {
87472377feSShawn Tu const struct og01a1b_reg_list reg_list;
88472377feSShawn Tu };
89472377feSShawn Tu
90472377feSShawn Tu struct og01a1b_mode {
91472377feSShawn Tu /* Frame width in pixels */
92472377feSShawn Tu u32 width;
93472377feSShawn Tu
94472377feSShawn Tu /* Frame height in pixels */
95472377feSShawn Tu u32 height;
96472377feSShawn Tu
97472377feSShawn Tu /* Horizontal timining size */
98472377feSShawn Tu u32 hts;
99472377feSShawn Tu
100472377feSShawn Tu /* Default vertical timining size */
101472377feSShawn Tu u32 vts_def;
102472377feSShawn Tu
103472377feSShawn Tu /* Min vertical timining size */
104472377feSShawn Tu u32 vts_min;
105472377feSShawn Tu
106472377feSShawn Tu /* Link frequency needed for this resolution */
107472377feSShawn Tu u32 link_freq_index;
108472377feSShawn Tu
109472377feSShawn Tu /* Sensor register settings for this resolution */
110472377feSShawn Tu const struct og01a1b_reg_list reg_list;
111472377feSShawn Tu };
112472377feSShawn Tu
113472377feSShawn Tu static const struct og01a1b_reg mipi_data_rate_1000mbps[] = {
114472377feSShawn Tu {0x0103, 0x01},
115472377feSShawn Tu {0x0303, 0x02},
116472377feSShawn Tu {0x0304, 0x00},
117472377feSShawn Tu {0x0305, 0xd2},
118472377feSShawn Tu {0x0323, 0x02},
119472377feSShawn Tu {0x0324, 0x01},
120472377feSShawn Tu {0x0325, 0x77},
121472377feSShawn Tu };
122472377feSShawn Tu
123472377feSShawn Tu static const struct og01a1b_reg mode_1280x1024_regs[] = {
124472377feSShawn Tu {0x0300, 0x0a},
125472377feSShawn Tu {0x0301, 0x29},
126472377feSShawn Tu {0x0302, 0x31},
127472377feSShawn Tu {0x0303, 0x02},
128472377feSShawn Tu {0x0304, 0x00},
129472377feSShawn Tu {0x0305, 0xd2},
130472377feSShawn Tu {0x0306, 0x00},
131472377feSShawn Tu {0x0307, 0x01},
132472377feSShawn Tu {0x0308, 0x02},
133472377feSShawn Tu {0x0309, 0x00},
134472377feSShawn Tu {0x0310, 0x00},
135472377feSShawn Tu {0x0311, 0x00},
136472377feSShawn Tu {0x0312, 0x07},
137472377feSShawn Tu {0x0313, 0x00},
138472377feSShawn Tu {0x0314, 0x00},
139472377feSShawn Tu {0x0315, 0x00},
140472377feSShawn Tu {0x0320, 0x02},
141472377feSShawn Tu {0x0321, 0x01},
142472377feSShawn Tu {0x0322, 0x01},
143472377feSShawn Tu {0x0323, 0x02},
144472377feSShawn Tu {0x0324, 0x01},
145472377feSShawn Tu {0x0325, 0x77},
146472377feSShawn Tu {0x0326, 0xce},
147472377feSShawn Tu {0x0327, 0x04},
148472377feSShawn Tu {0x0329, 0x02},
149472377feSShawn Tu {0x032a, 0x04},
150472377feSShawn Tu {0x032b, 0x04},
151472377feSShawn Tu {0x032c, 0x02},
152472377feSShawn Tu {0x032d, 0x01},
153472377feSShawn Tu {0x032e, 0x00},
154472377feSShawn Tu {0x300d, 0x02},
155472377feSShawn Tu {0x300e, 0x04},
156472377feSShawn Tu {0x3021, 0x08},
157472377feSShawn Tu {0x301e, 0x03},
158472377feSShawn Tu {0x3103, 0x00},
159472377feSShawn Tu {0x3106, 0x08},
160472377feSShawn Tu {0x3107, 0x40},
161472377feSShawn Tu {0x3216, 0x01},
162472377feSShawn Tu {0x3217, 0x00},
163472377feSShawn Tu {0x3218, 0xc0},
164472377feSShawn Tu {0x3219, 0x55},
165472377feSShawn Tu {0x3500, 0x00},
166472377feSShawn Tu {0x3501, 0x04},
167472377feSShawn Tu {0x3502, 0x8a},
168472377feSShawn Tu {0x3506, 0x01},
169472377feSShawn Tu {0x3507, 0x72},
170472377feSShawn Tu {0x3508, 0x01},
171472377feSShawn Tu {0x3509, 0x00},
172472377feSShawn Tu {0x350a, 0x01},
173472377feSShawn Tu {0x350b, 0x00},
174472377feSShawn Tu {0x350c, 0x00},
175472377feSShawn Tu {0x3541, 0x00},
176472377feSShawn Tu {0x3542, 0x40},
177472377feSShawn Tu {0x3605, 0xe0},
178472377feSShawn Tu {0x3606, 0x41},
179472377feSShawn Tu {0x3614, 0x20},
180472377feSShawn Tu {0x3620, 0x0b},
181472377feSShawn Tu {0x3630, 0x07},
182472377feSShawn Tu {0x3636, 0xa0},
183472377feSShawn Tu {0x3637, 0xf9},
184472377feSShawn Tu {0x3638, 0x09},
185472377feSShawn Tu {0x3639, 0x38},
186472377feSShawn Tu {0x363f, 0x09},
187472377feSShawn Tu {0x3640, 0x17},
188472377feSShawn Tu {0x3662, 0x04},
189472377feSShawn Tu {0x3665, 0x80},
190472377feSShawn Tu {0x3670, 0x68},
191472377feSShawn Tu {0x3674, 0x00},
192472377feSShawn Tu {0x3677, 0x3f},
193472377feSShawn Tu {0x3679, 0x00},
194472377feSShawn Tu {0x369f, 0x19},
195472377feSShawn Tu {0x36a0, 0x03},
196472377feSShawn Tu {0x36a2, 0x19},
197472377feSShawn Tu {0x36a3, 0x03},
198472377feSShawn Tu {0x370d, 0x66},
199472377feSShawn Tu {0x370f, 0x00},
200472377feSShawn Tu {0x3710, 0x03},
201472377feSShawn Tu {0x3715, 0x03},
202472377feSShawn Tu {0x3716, 0x03},
203472377feSShawn Tu {0x3717, 0x06},
204472377feSShawn Tu {0x3733, 0x00},
205472377feSShawn Tu {0x3778, 0x00},
206472377feSShawn Tu {0x37a8, 0x0f},
207472377feSShawn Tu {0x37a9, 0x01},
208472377feSShawn Tu {0x37aa, 0x07},
209472377feSShawn Tu {0x37bd, 0x1c},
210472377feSShawn Tu {0x37c1, 0x2f},
211472377feSShawn Tu {0x37c3, 0x09},
212472377feSShawn Tu {0x37c8, 0x1d},
213472377feSShawn Tu {0x37ca, 0x30},
214472377feSShawn Tu {0x37df, 0x00},
215472377feSShawn Tu {0x3800, 0x00},
216472377feSShawn Tu {0x3801, 0x00},
217472377feSShawn Tu {0x3802, 0x00},
218472377feSShawn Tu {0x3803, 0x00},
219472377feSShawn Tu {0x3804, 0x05},
220472377feSShawn Tu {0x3805, 0x0f},
221472377feSShawn Tu {0x3806, 0x04},
222472377feSShawn Tu {0x3807, 0x0f},
223472377feSShawn Tu {0x3808, 0x05},
224472377feSShawn Tu {0x3809, 0x00},
225472377feSShawn Tu {0x380a, 0x04},
226472377feSShawn Tu {0x380b, 0x00},
227472377feSShawn Tu {0x380c, 0x03},
228472377feSShawn Tu {0x380d, 0x50},
229472377feSShawn Tu {0x380e, 0x04},
230472377feSShawn Tu {0x380f, 0x98},
231472377feSShawn Tu {0x3810, 0x00},
232472377feSShawn Tu {0x3811, 0x08},
233472377feSShawn Tu {0x3812, 0x00},
234472377feSShawn Tu {0x3813, 0x08},
235472377feSShawn Tu {0x3814, 0x11},
236472377feSShawn Tu {0x3815, 0x11},
237472377feSShawn Tu {0x3820, 0x40},
238472377feSShawn Tu {0x3821, 0x04},
239472377feSShawn Tu {0x3826, 0x00},
240472377feSShawn Tu {0x3827, 0x00},
241472377feSShawn Tu {0x382a, 0x08},
242472377feSShawn Tu {0x382b, 0x52},
243472377feSShawn Tu {0x382d, 0xba},
244472377feSShawn Tu {0x383d, 0x14},
245472377feSShawn Tu {0x384a, 0xa2},
246472377feSShawn Tu {0x3866, 0x0e},
247472377feSShawn Tu {0x3867, 0x07},
248472377feSShawn Tu {0x3884, 0x00},
249472377feSShawn Tu {0x3885, 0x08},
250472377feSShawn Tu {0x3893, 0x68},
251472377feSShawn Tu {0x3894, 0x2a},
252472377feSShawn Tu {0x3898, 0x00},
253472377feSShawn Tu {0x3899, 0x31},
254472377feSShawn Tu {0x389a, 0x04},
255472377feSShawn Tu {0x389b, 0x00},
256472377feSShawn Tu {0x389c, 0x0b},
257472377feSShawn Tu {0x389d, 0xad},
258472377feSShawn Tu {0x389f, 0x08},
259472377feSShawn Tu {0x38a0, 0x00},
260472377feSShawn Tu {0x38a1, 0x00},
261472377feSShawn Tu {0x38a8, 0x70},
262472377feSShawn Tu {0x38ac, 0xea},
263472377feSShawn Tu {0x38b2, 0x00},
264472377feSShawn Tu {0x38b3, 0x08},
265472377feSShawn Tu {0x38bc, 0x20},
266472377feSShawn Tu {0x38c4, 0x0c},
267472377feSShawn Tu {0x38c5, 0x3a},
268472377feSShawn Tu {0x38c7, 0x3a},
269472377feSShawn Tu {0x38e1, 0xc0},
270472377feSShawn Tu {0x38ec, 0x3c},
271472377feSShawn Tu {0x38f0, 0x09},
272472377feSShawn Tu {0x38f1, 0x6f},
273472377feSShawn Tu {0x38fe, 0x3c},
274472377feSShawn Tu {0x391e, 0x00},
275472377feSShawn Tu {0x391f, 0x00},
276472377feSShawn Tu {0x3920, 0xa5},
277472377feSShawn Tu {0x3921, 0x00},
278472377feSShawn Tu {0x3922, 0x00},
279472377feSShawn Tu {0x3923, 0x00},
280472377feSShawn Tu {0x3924, 0x05},
281472377feSShawn Tu {0x3925, 0x00},
282472377feSShawn Tu {0x3926, 0x00},
283472377feSShawn Tu {0x3927, 0x00},
284472377feSShawn Tu {0x3928, 0x1a},
285472377feSShawn Tu {0x3929, 0x01},
286472377feSShawn Tu {0x392a, 0xb4},
287472377feSShawn Tu {0x392b, 0x00},
288472377feSShawn Tu {0x392c, 0x10},
289472377feSShawn Tu {0x392f, 0x40},
290472377feSShawn Tu {0x4000, 0xcf},
291472377feSShawn Tu {0x4003, 0x40},
292472377feSShawn Tu {0x4008, 0x00},
293472377feSShawn Tu {0x4009, 0x07},
294472377feSShawn Tu {0x400a, 0x02},
295472377feSShawn Tu {0x400b, 0x54},
296472377feSShawn Tu {0x400c, 0x00},
297472377feSShawn Tu {0x400d, 0x07},
298472377feSShawn Tu {0x4010, 0xc0},
299472377feSShawn Tu {0x4012, 0x02},
300472377feSShawn Tu {0x4014, 0x04},
301472377feSShawn Tu {0x4015, 0x04},
302472377feSShawn Tu {0x4017, 0x02},
303472377feSShawn Tu {0x4042, 0x01},
304472377feSShawn Tu {0x4306, 0x04},
305472377feSShawn Tu {0x4307, 0x12},
306472377feSShawn Tu {0x4509, 0x00},
307472377feSShawn Tu {0x450b, 0x83},
308472377feSShawn Tu {0x4604, 0x68},
309472377feSShawn Tu {0x4608, 0x0a},
310472377feSShawn Tu {0x4700, 0x06},
311472377feSShawn Tu {0x4800, 0x64},
312472377feSShawn Tu {0x481b, 0x3c},
313472377feSShawn Tu {0x4825, 0x32},
314472377feSShawn Tu {0x4833, 0x18},
315472377feSShawn Tu {0x4837, 0x0f},
316472377feSShawn Tu {0x4850, 0x40},
317472377feSShawn Tu {0x4860, 0x00},
318472377feSShawn Tu {0x4861, 0xec},
319472377feSShawn Tu {0x4864, 0x00},
320472377feSShawn Tu {0x4883, 0x00},
321472377feSShawn Tu {0x4888, 0x90},
322472377feSShawn Tu {0x4889, 0x05},
323472377feSShawn Tu {0x488b, 0x04},
324472377feSShawn Tu {0x4f00, 0x04},
325472377feSShawn Tu {0x4f10, 0x04},
326472377feSShawn Tu {0x4f21, 0x01},
327472377feSShawn Tu {0x4f22, 0x40},
328472377feSShawn Tu {0x4f23, 0x44},
329472377feSShawn Tu {0x4f24, 0x51},
330472377feSShawn Tu {0x4f25, 0x41},
331472377feSShawn Tu {0x5000, 0x1f},
332472377feSShawn Tu {0x500a, 0x00},
333472377feSShawn Tu {0x5100, 0x00},
334472377feSShawn Tu {0x5111, 0x20},
335472377feSShawn Tu {0x3020, 0x20},
336472377feSShawn Tu {0x3613, 0x03},
337472377feSShawn Tu {0x38c9, 0x02},
338472377feSShawn Tu {0x5304, 0x01},
339472377feSShawn Tu {0x3620, 0x08},
340472377feSShawn Tu {0x3639, 0x58},
341472377feSShawn Tu {0x363a, 0x10},
342472377feSShawn Tu {0x3674, 0x04},
343472377feSShawn Tu {0x3780, 0xff},
344472377feSShawn Tu {0x3781, 0xff},
345472377feSShawn Tu {0x3782, 0x00},
346472377feSShawn Tu {0x3783, 0x01},
347472377feSShawn Tu {0x3798, 0xa3},
348472377feSShawn Tu {0x37aa, 0x10},
349472377feSShawn Tu {0x38a8, 0xf0},
350472377feSShawn Tu {0x38c4, 0x09},
351472377feSShawn Tu {0x38c5, 0xb0},
352472377feSShawn Tu {0x38df, 0x80},
353472377feSShawn Tu {0x38ff, 0x05},
354472377feSShawn Tu {0x4010, 0xf1},
355472377feSShawn Tu {0x4011, 0x70},
356472377feSShawn Tu {0x3667, 0x80},
357472377feSShawn Tu {0x4d00, 0x4a},
358472377feSShawn Tu {0x4d01, 0x18},
359472377feSShawn Tu {0x4d02, 0xbb},
360472377feSShawn Tu {0x4d03, 0xde},
361472377feSShawn Tu {0x4d04, 0x93},
362472377feSShawn Tu {0x4d05, 0xff},
363472377feSShawn Tu {0x4d09, 0x0a},
364472377feSShawn Tu {0x37aa, 0x16},
365472377feSShawn Tu {0x3606, 0x42},
366472377feSShawn Tu {0x3605, 0x00},
367472377feSShawn Tu {0x36a2, 0x17},
368472377feSShawn Tu {0x300d, 0x0a},
369472377feSShawn Tu {0x4d00, 0x4d},
370472377feSShawn Tu {0x4d01, 0x95},
371472377feSShawn Tu {0x3d8C, 0x70},
372472377feSShawn Tu {0x3d8d, 0xE9},
373472377feSShawn Tu {0x5300, 0x00},
374472377feSShawn Tu {0x5301, 0x10},
375472377feSShawn Tu {0x5302, 0x00},
376472377feSShawn Tu {0x5303, 0xE3},
377472377feSShawn Tu {0x3d88, 0x00},
378472377feSShawn Tu {0x3d89, 0x10},
379472377feSShawn Tu {0x3d8a, 0x00},
380472377feSShawn Tu {0x3d8b, 0xE3},
381472377feSShawn Tu {0x4f22, 0x00},
382472377feSShawn Tu };
383472377feSShawn Tu
384472377feSShawn Tu static const char * const og01a1b_test_pattern_menu[] = {
385472377feSShawn Tu "Disabled",
386472377feSShawn Tu "Standard Color Bar",
387472377feSShawn Tu "Top-Bottom Darker Color Bar",
388472377feSShawn Tu "Right-Left Darker Color Bar",
389472377feSShawn Tu "Bottom-Top Darker Color Bar"
390472377feSShawn Tu };
391472377feSShawn Tu
392472377feSShawn Tu static const s64 link_freq_menu_items[] = {
393472377feSShawn Tu OG01A1B_LINK_FREQ_500MHZ,
394472377feSShawn Tu };
395472377feSShawn Tu
396472377feSShawn Tu static const struct og01a1b_link_freq_config link_freq_configs[] = {
397472377feSShawn Tu [OG01A1B_LINK_FREQ_1000MBPS] = {
398472377feSShawn Tu .reg_list = {
399472377feSShawn Tu .num_of_regs = ARRAY_SIZE(mipi_data_rate_1000mbps),
400472377feSShawn Tu .regs = mipi_data_rate_1000mbps,
401472377feSShawn Tu }
402472377feSShawn Tu }
403472377feSShawn Tu };
404472377feSShawn Tu
405472377feSShawn Tu static const struct og01a1b_mode supported_modes[] = {
406472377feSShawn Tu {
407472377feSShawn Tu .width = 1280,
408472377feSShawn Tu .height = 1024,
409472377feSShawn Tu .hts = 848,
410472377feSShawn Tu .vts_def = OG01A1B_VTS_120FPS,
411472377feSShawn Tu .vts_min = OG01A1B_VTS_120FPS_MIN,
412472377feSShawn Tu .reg_list = {
413472377feSShawn Tu .num_of_regs = ARRAY_SIZE(mode_1280x1024_regs),
414472377feSShawn Tu .regs = mode_1280x1024_regs,
415472377feSShawn Tu },
416472377feSShawn Tu .link_freq_index = OG01A1B_LINK_FREQ_1000MBPS,
417472377feSShawn Tu },
418472377feSShawn Tu };
419472377feSShawn Tu
420472377feSShawn Tu struct og01a1b {
421472377feSShawn Tu struct v4l2_subdev sd;
422472377feSShawn Tu struct media_pad pad;
423472377feSShawn Tu struct v4l2_ctrl_handler ctrl_handler;
424472377feSShawn Tu
425472377feSShawn Tu /* V4L2 Controls */
426472377feSShawn Tu struct v4l2_ctrl *link_freq;
427472377feSShawn Tu struct v4l2_ctrl *pixel_rate;
428472377feSShawn Tu struct v4l2_ctrl *vblank;
429472377feSShawn Tu struct v4l2_ctrl *hblank;
430472377feSShawn Tu struct v4l2_ctrl *exposure;
431472377feSShawn Tu
432472377feSShawn Tu /* Current mode */
433472377feSShawn Tu const struct og01a1b_mode *cur_mode;
434472377feSShawn Tu
435472377feSShawn Tu /* To serialize asynchronus callbacks */
436472377feSShawn Tu struct mutex mutex;
437472377feSShawn Tu
438472377feSShawn Tu /* Streaming on/off */
439472377feSShawn Tu bool streaming;
440472377feSShawn Tu };
441472377feSShawn Tu
to_pixel_rate(u32 f_index)442472377feSShawn Tu static u64 to_pixel_rate(u32 f_index)
443472377feSShawn Tu {
444472377feSShawn Tu u64 pixel_rate = link_freq_menu_items[f_index] * 2 * OG01A1B_DATA_LANES;
445472377feSShawn Tu
446472377feSShawn Tu do_div(pixel_rate, OG01A1B_RGB_DEPTH);
447472377feSShawn Tu
448472377feSShawn Tu return pixel_rate;
449472377feSShawn Tu }
450472377feSShawn Tu
to_pixels_per_line(u32 hts,u32 f_index)451472377feSShawn Tu static u64 to_pixels_per_line(u32 hts, u32 f_index)
452472377feSShawn Tu {
453472377feSShawn Tu u64 ppl = hts * to_pixel_rate(f_index);
454472377feSShawn Tu
455472377feSShawn Tu do_div(ppl, OG01A1B_SCLK);
456472377feSShawn Tu
457472377feSShawn Tu return ppl;
458472377feSShawn Tu }
459472377feSShawn Tu
og01a1b_read_reg(struct og01a1b * og01a1b,u16 reg,u16 len,u32 * val)460472377feSShawn Tu static int og01a1b_read_reg(struct og01a1b *og01a1b, u16 reg, u16 len, u32 *val)
461472377feSShawn Tu {
462472377feSShawn Tu struct i2c_client *client = v4l2_get_subdevdata(&og01a1b->sd);
463472377feSShawn Tu struct i2c_msg msgs[2];
464472377feSShawn Tu u8 addr_buf[2];
465472377feSShawn Tu u8 data_buf[4] = {0};
466472377feSShawn Tu int ret;
467472377feSShawn Tu
468472377feSShawn Tu if (len > 4)
469472377feSShawn Tu return -EINVAL;
470472377feSShawn Tu
471472377feSShawn Tu put_unaligned_be16(reg, addr_buf);
472472377feSShawn Tu msgs[0].addr = client->addr;
473472377feSShawn Tu msgs[0].flags = 0;
474472377feSShawn Tu msgs[0].len = sizeof(addr_buf);
475472377feSShawn Tu msgs[0].buf = addr_buf;
476472377feSShawn Tu msgs[1].addr = client->addr;
477472377feSShawn Tu msgs[1].flags = I2C_M_RD;
478472377feSShawn Tu msgs[1].len = len;
479472377feSShawn Tu msgs[1].buf = &data_buf[4 - len];
480472377feSShawn Tu
481472377feSShawn Tu ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
482472377feSShawn Tu if (ret != ARRAY_SIZE(msgs))
483472377feSShawn Tu return -EIO;
484472377feSShawn Tu
485472377feSShawn Tu *val = get_unaligned_be32(data_buf);
486472377feSShawn Tu
487472377feSShawn Tu return 0;
488472377feSShawn Tu }
489472377feSShawn Tu
og01a1b_write_reg(struct og01a1b * og01a1b,u16 reg,u16 len,u32 val)490472377feSShawn Tu static int og01a1b_write_reg(struct og01a1b *og01a1b, u16 reg, u16 len, u32 val)
491472377feSShawn Tu {
492472377feSShawn Tu struct i2c_client *client = v4l2_get_subdevdata(&og01a1b->sd);
493472377feSShawn Tu u8 buf[6];
494472377feSShawn Tu
495472377feSShawn Tu if (len > 4)
496472377feSShawn Tu return -EINVAL;
497472377feSShawn Tu
498472377feSShawn Tu put_unaligned_be16(reg, buf);
499472377feSShawn Tu put_unaligned_be32(val << 8 * (4 - len), buf + 2);
500472377feSShawn Tu if (i2c_master_send(client, buf, len + 2) != len + 2)
501472377feSShawn Tu return -EIO;
502472377feSShawn Tu
503472377feSShawn Tu return 0;
504472377feSShawn Tu }
505472377feSShawn Tu
og01a1b_write_reg_list(struct og01a1b * og01a1b,const struct og01a1b_reg_list * r_list)506472377feSShawn Tu static int og01a1b_write_reg_list(struct og01a1b *og01a1b,
507472377feSShawn Tu const struct og01a1b_reg_list *r_list)
508472377feSShawn Tu {
509472377feSShawn Tu struct i2c_client *client = v4l2_get_subdevdata(&og01a1b->sd);
510472377feSShawn Tu unsigned int i;
511472377feSShawn Tu int ret;
512472377feSShawn Tu
513472377feSShawn Tu for (i = 0; i < r_list->num_of_regs; i++) {
514472377feSShawn Tu ret = og01a1b_write_reg(og01a1b, r_list->regs[i].address, 1,
515472377feSShawn Tu r_list->regs[i].val);
516472377feSShawn Tu if (ret) {
517472377feSShawn Tu dev_err_ratelimited(&client->dev,
518472377feSShawn Tu "failed to write reg 0x%4.4x. error = %d",
519472377feSShawn Tu r_list->regs[i].address, ret);
520472377feSShawn Tu return ret;
521472377feSShawn Tu }
522472377feSShawn Tu }
523472377feSShawn Tu
524472377feSShawn Tu return 0;
525472377feSShawn Tu }
526472377feSShawn Tu
og01a1b_test_pattern(struct og01a1b * og01a1b,u32 pattern)527472377feSShawn Tu static int og01a1b_test_pattern(struct og01a1b *og01a1b, u32 pattern)
528472377feSShawn Tu {
529472377feSShawn Tu if (pattern)
530472377feSShawn Tu pattern = (pattern - 1) << OG01A1B_TEST_PATTERN_BAR_SHIFT |
531472377feSShawn Tu OG01A1B_TEST_PATTERN_ENABLE;
532472377feSShawn Tu
533472377feSShawn Tu return og01a1b_write_reg(og01a1b, OG01A1B_REG_TEST_PATTERN,
534472377feSShawn Tu OG01A1B_REG_VALUE_08BIT, pattern);
535472377feSShawn Tu }
536472377feSShawn Tu
og01a1b_set_ctrl(struct v4l2_ctrl * ctrl)537472377feSShawn Tu static int og01a1b_set_ctrl(struct v4l2_ctrl *ctrl)
538472377feSShawn Tu {
539472377feSShawn Tu struct og01a1b *og01a1b = container_of(ctrl->handler,
540472377feSShawn Tu struct og01a1b, ctrl_handler);
541472377feSShawn Tu struct i2c_client *client = v4l2_get_subdevdata(&og01a1b->sd);
542472377feSShawn Tu s64 exposure_max;
543472377feSShawn Tu int ret = 0;
544472377feSShawn Tu
545472377feSShawn Tu /* Propagate change of current control to all related controls */
546472377feSShawn Tu if (ctrl->id == V4L2_CID_VBLANK) {
547472377feSShawn Tu /* Update max exposure while meeting expected vblanking */
548472377feSShawn Tu exposure_max = og01a1b->cur_mode->height + ctrl->val -
549472377feSShawn Tu OG01A1B_EXPOSURE_MAX_MARGIN;
550472377feSShawn Tu __v4l2_ctrl_modify_range(og01a1b->exposure,
551472377feSShawn Tu og01a1b->exposure->minimum,
552472377feSShawn Tu exposure_max, og01a1b->exposure->step,
553472377feSShawn Tu exposure_max);
554472377feSShawn Tu }
555472377feSShawn Tu
556472377feSShawn Tu /* V4L2 controls values will be applied only when power is already up */
557472377feSShawn Tu if (!pm_runtime_get_if_in_use(&client->dev))
558472377feSShawn Tu return 0;
559472377feSShawn Tu
560472377feSShawn Tu switch (ctrl->id) {
561472377feSShawn Tu case V4L2_CID_ANALOGUE_GAIN:
562472377feSShawn Tu ret = og01a1b_write_reg(og01a1b, OG01A1B_REG_ANALOG_GAIN,
563472377feSShawn Tu OG01A1B_REG_VALUE_16BIT,
564472377feSShawn Tu ctrl->val << 4);
565472377feSShawn Tu break;
566472377feSShawn Tu
567472377feSShawn Tu case V4L2_CID_DIGITAL_GAIN:
568472377feSShawn Tu ret = og01a1b_write_reg(og01a1b, OG01A1B_REG_DIG_GAIN,
569472377feSShawn Tu OG01A1B_REG_VALUE_24BIT,
570472377feSShawn Tu ctrl->val << 6);
571472377feSShawn Tu break;
572472377feSShawn Tu
573472377feSShawn Tu case V4L2_CID_EXPOSURE:
574472377feSShawn Tu ret = og01a1b_write_reg(og01a1b, OG01A1B_REG_EXPOSURE,
575472377feSShawn Tu OG01A1B_REG_VALUE_16BIT, ctrl->val);
576472377feSShawn Tu break;
577472377feSShawn Tu
578472377feSShawn Tu case V4L2_CID_VBLANK:
579472377feSShawn Tu ret = og01a1b_write_reg(og01a1b, OG01A1B_REG_VTS,
580472377feSShawn Tu OG01A1B_REG_VALUE_16BIT,
581472377feSShawn Tu og01a1b->cur_mode->height + ctrl->val);
582472377feSShawn Tu break;
583472377feSShawn Tu
584472377feSShawn Tu case V4L2_CID_TEST_PATTERN:
585472377feSShawn Tu ret = og01a1b_test_pattern(og01a1b, ctrl->val);
586472377feSShawn Tu break;
587472377feSShawn Tu
588472377feSShawn Tu default:
589472377feSShawn Tu ret = -EINVAL;
590472377feSShawn Tu break;
591472377feSShawn Tu }
592472377feSShawn Tu
593472377feSShawn Tu pm_runtime_put(&client->dev);
594472377feSShawn Tu
595472377feSShawn Tu return ret;
596472377feSShawn Tu }
597472377feSShawn Tu
598472377feSShawn Tu static const struct v4l2_ctrl_ops og01a1b_ctrl_ops = {
599472377feSShawn Tu .s_ctrl = og01a1b_set_ctrl,
600472377feSShawn Tu };
601472377feSShawn Tu
og01a1b_init_controls(struct og01a1b * og01a1b)602472377feSShawn Tu static int og01a1b_init_controls(struct og01a1b *og01a1b)
603472377feSShawn Tu {
604472377feSShawn Tu struct v4l2_ctrl_handler *ctrl_hdlr;
605472377feSShawn Tu s64 exposure_max, h_blank;
606472377feSShawn Tu int ret;
607472377feSShawn Tu
608472377feSShawn Tu ctrl_hdlr = &og01a1b->ctrl_handler;
609472377feSShawn Tu ret = v4l2_ctrl_handler_init(ctrl_hdlr, 8);
610472377feSShawn Tu if (ret)
611472377feSShawn Tu return ret;
612472377feSShawn Tu
613472377feSShawn Tu ctrl_hdlr->lock = &og01a1b->mutex;
614472377feSShawn Tu og01a1b->link_freq = v4l2_ctrl_new_int_menu(ctrl_hdlr,
615472377feSShawn Tu &og01a1b_ctrl_ops,
616472377feSShawn Tu V4L2_CID_LINK_FREQ,
617472377feSShawn Tu ARRAY_SIZE
618472377feSShawn Tu (link_freq_menu_items) - 1,
619472377feSShawn Tu 0, link_freq_menu_items);
620472377feSShawn Tu if (og01a1b->link_freq)
621472377feSShawn Tu og01a1b->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY;
622472377feSShawn Tu
623472377feSShawn Tu og01a1b->pixel_rate = v4l2_ctrl_new_std(ctrl_hdlr, &og01a1b_ctrl_ops,
624472377feSShawn Tu V4L2_CID_PIXEL_RATE, 0,
625472377feSShawn Tu to_pixel_rate
626472377feSShawn Tu (OG01A1B_LINK_FREQ_1000MBPS),
627472377feSShawn Tu 1,
628472377feSShawn Tu to_pixel_rate
629472377feSShawn Tu (OG01A1B_LINK_FREQ_1000MBPS));
630472377feSShawn Tu og01a1b->vblank = v4l2_ctrl_new_std(ctrl_hdlr, &og01a1b_ctrl_ops,
631472377feSShawn Tu V4L2_CID_VBLANK,
632472377feSShawn Tu og01a1b->cur_mode->vts_min -
633472377feSShawn Tu og01a1b->cur_mode->height,
634472377feSShawn Tu OG01A1B_VTS_MAX -
635472377feSShawn Tu og01a1b->cur_mode->height, 1,
636472377feSShawn Tu og01a1b->cur_mode->vts_def -
637472377feSShawn Tu og01a1b->cur_mode->height);
638472377feSShawn Tu h_blank = to_pixels_per_line(og01a1b->cur_mode->hts,
639472377feSShawn Tu og01a1b->cur_mode->link_freq_index) -
640472377feSShawn Tu og01a1b->cur_mode->width;
641472377feSShawn Tu og01a1b->hblank = v4l2_ctrl_new_std(ctrl_hdlr, &og01a1b_ctrl_ops,
642472377feSShawn Tu V4L2_CID_HBLANK, h_blank, h_blank,
643472377feSShawn Tu 1, h_blank);
644472377feSShawn Tu if (og01a1b->hblank)
645472377feSShawn Tu og01a1b->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
646472377feSShawn Tu
647472377feSShawn Tu v4l2_ctrl_new_std(ctrl_hdlr, &og01a1b_ctrl_ops, V4L2_CID_ANALOGUE_GAIN,
648472377feSShawn Tu OG01A1B_ANAL_GAIN_MIN, OG01A1B_ANAL_GAIN_MAX,
649472377feSShawn Tu OG01A1B_ANAL_GAIN_STEP, OG01A1B_ANAL_GAIN_MIN);
650472377feSShawn Tu v4l2_ctrl_new_std(ctrl_hdlr, &og01a1b_ctrl_ops, V4L2_CID_DIGITAL_GAIN,
651472377feSShawn Tu OG01A1B_DGTL_GAIN_MIN, OG01A1B_DGTL_GAIN_MAX,
652472377feSShawn Tu OG01A1B_DGTL_GAIN_STEP, OG01A1B_DGTL_GAIN_DEFAULT);
653472377feSShawn Tu exposure_max = (og01a1b->cur_mode->vts_def -
654472377feSShawn Tu OG01A1B_EXPOSURE_MAX_MARGIN);
655472377feSShawn Tu og01a1b->exposure = v4l2_ctrl_new_std(ctrl_hdlr, &og01a1b_ctrl_ops,
656472377feSShawn Tu V4L2_CID_EXPOSURE,
657472377feSShawn Tu OG01A1B_EXPOSURE_MIN,
658472377feSShawn Tu exposure_max,
659472377feSShawn Tu OG01A1B_EXPOSURE_STEP,
660472377feSShawn Tu exposure_max);
661472377feSShawn Tu v4l2_ctrl_new_std_menu_items(ctrl_hdlr, &og01a1b_ctrl_ops,
662472377feSShawn Tu V4L2_CID_TEST_PATTERN,
663472377feSShawn Tu ARRAY_SIZE(og01a1b_test_pattern_menu) - 1,
664472377feSShawn Tu 0, 0, og01a1b_test_pattern_menu);
665472377feSShawn Tu
666472377feSShawn Tu if (ctrl_hdlr->error)
667472377feSShawn Tu return ctrl_hdlr->error;
668472377feSShawn Tu
669472377feSShawn Tu og01a1b->sd.ctrl_handler = ctrl_hdlr;
670472377feSShawn Tu
671472377feSShawn Tu return 0;
672472377feSShawn Tu }
673472377feSShawn Tu
og01a1b_update_pad_format(const struct og01a1b_mode * mode,struct v4l2_mbus_framefmt * fmt)674472377feSShawn Tu static void og01a1b_update_pad_format(const struct og01a1b_mode *mode,
675472377feSShawn Tu struct v4l2_mbus_framefmt *fmt)
676472377feSShawn Tu {
677472377feSShawn Tu fmt->width = mode->width;
678472377feSShawn Tu fmt->height = mode->height;
679472377feSShawn Tu fmt->code = MEDIA_BUS_FMT_SGRBG10_1X10;
680472377feSShawn Tu fmt->field = V4L2_FIELD_NONE;
681472377feSShawn Tu }
682472377feSShawn Tu
og01a1b_start_streaming(struct og01a1b * og01a1b)683472377feSShawn Tu static int og01a1b_start_streaming(struct og01a1b *og01a1b)
684472377feSShawn Tu {
685472377feSShawn Tu struct i2c_client *client = v4l2_get_subdevdata(&og01a1b->sd);
686472377feSShawn Tu const struct og01a1b_reg_list *reg_list;
687472377feSShawn Tu int link_freq_index, ret;
688472377feSShawn Tu
689472377feSShawn Tu link_freq_index = og01a1b->cur_mode->link_freq_index;
690472377feSShawn Tu reg_list = &link_freq_configs[link_freq_index].reg_list;
691472377feSShawn Tu
692472377feSShawn Tu ret = og01a1b_write_reg_list(og01a1b, reg_list);
693472377feSShawn Tu if (ret) {
694472377feSShawn Tu dev_err(&client->dev, "failed to set plls");
695472377feSShawn Tu return ret;
696472377feSShawn Tu }
697472377feSShawn Tu
698472377feSShawn Tu reg_list = &og01a1b->cur_mode->reg_list;
699472377feSShawn Tu ret = og01a1b_write_reg_list(og01a1b, reg_list);
700472377feSShawn Tu if (ret) {
701472377feSShawn Tu dev_err(&client->dev, "failed to set mode");
702472377feSShawn Tu return ret;
703472377feSShawn Tu }
704472377feSShawn Tu
705472377feSShawn Tu ret = __v4l2_ctrl_handler_setup(og01a1b->sd.ctrl_handler);
706472377feSShawn Tu if (ret)
707472377feSShawn Tu return ret;
708472377feSShawn Tu
709472377feSShawn Tu ret = og01a1b_write_reg(og01a1b, OG01A1B_REG_MODE_SELECT,
710472377feSShawn Tu OG01A1B_REG_VALUE_08BIT,
711472377feSShawn Tu OG01A1B_MODE_STREAMING);
712472377feSShawn Tu if (ret) {
713472377feSShawn Tu dev_err(&client->dev, "failed to set stream");
714472377feSShawn Tu return ret;
715472377feSShawn Tu }
716472377feSShawn Tu
717472377feSShawn Tu return 0;
718472377feSShawn Tu }
719472377feSShawn Tu
og01a1b_stop_streaming(struct og01a1b * og01a1b)720472377feSShawn Tu static void og01a1b_stop_streaming(struct og01a1b *og01a1b)
721472377feSShawn Tu {
722472377feSShawn Tu struct i2c_client *client = v4l2_get_subdevdata(&og01a1b->sd);
723472377feSShawn Tu
724472377feSShawn Tu if (og01a1b_write_reg(og01a1b, OG01A1B_REG_MODE_SELECT,
725472377feSShawn Tu OG01A1B_REG_VALUE_08BIT, OG01A1B_MODE_STANDBY))
726472377feSShawn Tu dev_err(&client->dev, "failed to set stream");
727472377feSShawn Tu }
728472377feSShawn Tu
og01a1b_set_stream(struct v4l2_subdev * sd,int enable)729472377feSShawn Tu static int og01a1b_set_stream(struct v4l2_subdev *sd, int enable)
730472377feSShawn Tu {
731472377feSShawn Tu struct og01a1b *og01a1b = to_og01a1b(sd);
732472377feSShawn Tu struct i2c_client *client = v4l2_get_subdevdata(sd);
733472377feSShawn Tu int ret = 0;
734472377feSShawn Tu
735472377feSShawn Tu if (og01a1b->streaming == enable)
736472377feSShawn Tu return 0;
737472377feSShawn Tu
738472377feSShawn Tu mutex_lock(&og01a1b->mutex);
739472377feSShawn Tu if (enable) {
740472377feSShawn Tu ret = pm_runtime_get_sync(&client->dev);
741472377feSShawn Tu if (ret < 0) {
742472377feSShawn Tu pm_runtime_put_noidle(&client->dev);
743472377feSShawn Tu mutex_unlock(&og01a1b->mutex);
744472377feSShawn Tu return ret;
745472377feSShawn Tu }
746472377feSShawn Tu
747472377feSShawn Tu ret = og01a1b_start_streaming(og01a1b);
748472377feSShawn Tu if (ret) {
749472377feSShawn Tu enable = 0;
750472377feSShawn Tu og01a1b_stop_streaming(og01a1b);
751472377feSShawn Tu pm_runtime_put(&client->dev);
752472377feSShawn Tu }
753472377feSShawn Tu } else {
754472377feSShawn Tu og01a1b_stop_streaming(og01a1b);
755472377feSShawn Tu pm_runtime_put(&client->dev);
756472377feSShawn Tu }
757472377feSShawn Tu
758472377feSShawn Tu og01a1b->streaming = enable;
759472377feSShawn Tu mutex_unlock(&og01a1b->mutex);
760472377feSShawn Tu
761472377feSShawn Tu return ret;
762472377feSShawn Tu }
763472377feSShawn Tu
og01a1b_suspend(struct device * dev)764472377feSShawn Tu static int __maybe_unused og01a1b_suspend(struct device *dev)
765472377feSShawn Tu {
766472377feSShawn Tu struct i2c_client *client = to_i2c_client(dev);
767472377feSShawn Tu struct v4l2_subdev *sd = i2c_get_clientdata(client);
768472377feSShawn Tu struct og01a1b *og01a1b = to_og01a1b(sd);
769472377feSShawn Tu
770472377feSShawn Tu mutex_lock(&og01a1b->mutex);
771472377feSShawn Tu if (og01a1b->streaming)
772472377feSShawn Tu og01a1b_stop_streaming(og01a1b);
773472377feSShawn Tu
774472377feSShawn Tu mutex_unlock(&og01a1b->mutex);
775472377feSShawn Tu
776472377feSShawn Tu return 0;
777472377feSShawn Tu }
778472377feSShawn Tu
og01a1b_resume(struct device * dev)779472377feSShawn Tu static int __maybe_unused og01a1b_resume(struct device *dev)
780472377feSShawn Tu {
781472377feSShawn Tu struct i2c_client *client = to_i2c_client(dev);
782472377feSShawn Tu struct v4l2_subdev *sd = i2c_get_clientdata(client);
783472377feSShawn Tu struct og01a1b *og01a1b = to_og01a1b(sd);
784472377feSShawn Tu int ret;
785472377feSShawn Tu
786472377feSShawn Tu mutex_lock(&og01a1b->mutex);
787472377feSShawn Tu if (og01a1b->streaming) {
788472377feSShawn Tu ret = og01a1b_start_streaming(og01a1b);
789472377feSShawn Tu if (ret) {
790472377feSShawn Tu og01a1b->streaming = false;
791472377feSShawn Tu og01a1b_stop_streaming(og01a1b);
792472377feSShawn Tu mutex_unlock(&og01a1b->mutex);
793472377feSShawn Tu return ret;
794472377feSShawn Tu }
795472377feSShawn Tu }
796472377feSShawn Tu
797472377feSShawn Tu mutex_unlock(&og01a1b->mutex);
798472377feSShawn Tu
799472377feSShawn Tu return 0;
800472377feSShawn Tu }
801472377feSShawn Tu
og01a1b_set_format(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_format * fmt)802472377feSShawn Tu static int og01a1b_set_format(struct v4l2_subdev *sd,
803472377feSShawn Tu struct v4l2_subdev_state *sd_state,
804472377feSShawn Tu struct v4l2_subdev_format *fmt)
805472377feSShawn Tu {
806472377feSShawn Tu struct og01a1b *og01a1b = to_og01a1b(sd);
807472377feSShawn Tu const struct og01a1b_mode *mode;
808472377feSShawn Tu s32 vblank_def, h_blank;
809472377feSShawn Tu
810472377feSShawn Tu mode = v4l2_find_nearest_size(supported_modes,
811472377feSShawn Tu ARRAY_SIZE(supported_modes), width,
812472377feSShawn Tu height, fmt->format.width,
813472377feSShawn Tu fmt->format.height);
814472377feSShawn Tu
815472377feSShawn Tu mutex_lock(&og01a1b->mutex);
816472377feSShawn Tu og01a1b_update_pad_format(mode, &fmt->format);
817472377feSShawn Tu if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
818472377feSShawn Tu *v4l2_subdev_get_try_format(sd, sd_state,
819472377feSShawn Tu fmt->pad) = fmt->format;
820472377feSShawn Tu } else {
821472377feSShawn Tu og01a1b->cur_mode = mode;
822472377feSShawn Tu __v4l2_ctrl_s_ctrl(og01a1b->link_freq, mode->link_freq_index);
823472377feSShawn Tu __v4l2_ctrl_s_ctrl_int64(og01a1b->pixel_rate,
824472377feSShawn Tu to_pixel_rate(mode->link_freq_index));
825472377feSShawn Tu
826472377feSShawn Tu /* Update limits and set FPS to default */
827472377feSShawn Tu vblank_def = mode->vts_def - mode->height;
828472377feSShawn Tu __v4l2_ctrl_modify_range(og01a1b->vblank,
829472377feSShawn Tu mode->vts_min - mode->height,
830472377feSShawn Tu OG01A1B_VTS_MAX - mode->height, 1,
831472377feSShawn Tu vblank_def);
832472377feSShawn Tu __v4l2_ctrl_s_ctrl(og01a1b->vblank, vblank_def);
833472377feSShawn Tu h_blank = to_pixels_per_line(mode->hts, mode->link_freq_index) -
834472377feSShawn Tu mode->width;
835472377feSShawn Tu __v4l2_ctrl_modify_range(og01a1b->hblank, h_blank, h_blank, 1,
836472377feSShawn Tu h_blank);
837472377feSShawn Tu }
838472377feSShawn Tu
839472377feSShawn Tu mutex_unlock(&og01a1b->mutex);
840472377feSShawn Tu
841472377feSShawn Tu return 0;
842472377feSShawn Tu }
843472377feSShawn Tu
og01a1b_get_format(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_format * fmt)844472377feSShawn Tu static int og01a1b_get_format(struct v4l2_subdev *sd,
845472377feSShawn Tu struct v4l2_subdev_state *sd_state,
846472377feSShawn Tu struct v4l2_subdev_format *fmt)
847472377feSShawn Tu {
848472377feSShawn Tu struct og01a1b *og01a1b = to_og01a1b(sd);
849472377feSShawn Tu
850472377feSShawn Tu mutex_lock(&og01a1b->mutex);
851472377feSShawn Tu if (fmt->which == V4L2_SUBDEV_FORMAT_TRY)
852472377feSShawn Tu fmt->format = *v4l2_subdev_get_try_format(&og01a1b->sd,
853472377feSShawn Tu sd_state,
854472377feSShawn Tu fmt->pad);
855472377feSShawn Tu else
856472377feSShawn Tu og01a1b_update_pad_format(og01a1b->cur_mode, &fmt->format);
857472377feSShawn Tu
858472377feSShawn Tu mutex_unlock(&og01a1b->mutex);
859472377feSShawn Tu
860472377feSShawn Tu return 0;
861472377feSShawn Tu }
862472377feSShawn Tu
og01a1b_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_mbus_code_enum * code)863472377feSShawn Tu static int og01a1b_enum_mbus_code(struct v4l2_subdev *sd,
864472377feSShawn Tu struct v4l2_subdev_state *sd_state,
865472377feSShawn Tu struct v4l2_subdev_mbus_code_enum *code)
866472377feSShawn Tu {
867472377feSShawn Tu if (code->index > 0)
868472377feSShawn Tu return -EINVAL;
869472377feSShawn Tu
870472377feSShawn Tu code->code = MEDIA_BUS_FMT_SGRBG10_1X10;
871472377feSShawn Tu
872472377feSShawn Tu return 0;
873472377feSShawn Tu }
874472377feSShawn Tu
og01a1b_enum_frame_size(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_frame_size_enum * fse)875472377feSShawn Tu static int og01a1b_enum_frame_size(struct v4l2_subdev *sd,
876472377feSShawn Tu struct v4l2_subdev_state *sd_state,
877472377feSShawn Tu struct v4l2_subdev_frame_size_enum *fse)
878472377feSShawn Tu {
879472377feSShawn Tu if (fse->index >= ARRAY_SIZE(supported_modes))
880472377feSShawn Tu return -EINVAL;
881472377feSShawn Tu
882472377feSShawn Tu if (fse->code != MEDIA_BUS_FMT_SGRBG10_1X10)
883472377feSShawn Tu return -EINVAL;
884472377feSShawn Tu
885472377feSShawn Tu fse->min_width = supported_modes[fse->index].width;
886472377feSShawn Tu fse->max_width = fse->min_width;
887472377feSShawn Tu fse->min_height = supported_modes[fse->index].height;
888472377feSShawn Tu fse->max_height = fse->min_height;
889472377feSShawn Tu
890472377feSShawn Tu return 0;
891472377feSShawn Tu }
892472377feSShawn Tu
og01a1b_open(struct v4l2_subdev * sd,struct v4l2_subdev_fh * fh)893472377feSShawn Tu static int og01a1b_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
894472377feSShawn Tu {
895472377feSShawn Tu struct og01a1b *og01a1b = to_og01a1b(sd);
896472377feSShawn Tu
897472377feSShawn Tu mutex_lock(&og01a1b->mutex);
898472377feSShawn Tu og01a1b_update_pad_format(&supported_modes[0],
899472377feSShawn Tu v4l2_subdev_get_try_format(sd, fh->state, 0));
900472377feSShawn Tu mutex_unlock(&og01a1b->mutex);
901472377feSShawn Tu
902472377feSShawn Tu return 0;
903472377feSShawn Tu }
904472377feSShawn Tu
905472377feSShawn Tu static const struct v4l2_subdev_video_ops og01a1b_video_ops = {
906472377feSShawn Tu .s_stream = og01a1b_set_stream,
907472377feSShawn Tu };
908472377feSShawn Tu
909472377feSShawn Tu static const struct v4l2_subdev_pad_ops og01a1b_pad_ops = {
910472377feSShawn Tu .set_fmt = og01a1b_set_format,
911472377feSShawn Tu .get_fmt = og01a1b_get_format,
912472377feSShawn Tu .enum_mbus_code = og01a1b_enum_mbus_code,
913472377feSShawn Tu .enum_frame_size = og01a1b_enum_frame_size,
914472377feSShawn Tu };
915472377feSShawn Tu
916472377feSShawn Tu static const struct v4l2_subdev_ops og01a1b_subdev_ops = {
917472377feSShawn Tu .video = &og01a1b_video_ops,
918472377feSShawn Tu .pad = &og01a1b_pad_ops,
919472377feSShawn Tu };
920472377feSShawn Tu
921472377feSShawn Tu static const struct media_entity_operations og01a1b_subdev_entity_ops = {
922472377feSShawn Tu .link_validate = v4l2_subdev_link_validate,
923472377feSShawn Tu };
924472377feSShawn Tu
925472377feSShawn Tu static const struct v4l2_subdev_internal_ops og01a1b_internal_ops = {
926472377feSShawn Tu .open = og01a1b_open,
927472377feSShawn Tu };
928472377feSShawn Tu
og01a1b_identify_module(struct og01a1b * og01a1b)929472377feSShawn Tu static int og01a1b_identify_module(struct og01a1b *og01a1b)
930472377feSShawn Tu {
931472377feSShawn Tu struct i2c_client *client = v4l2_get_subdevdata(&og01a1b->sd);
932472377feSShawn Tu int ret;
933472377feSShawn Tu u32 val;
934472377feSShawn Tu
935472377feSShawn Tu ret = og01a1b_read_reg(og01a1b, OG01A1B_REG_CHIP_ID,
936472377feSShawn Tu OG01A1B_REG_VALUE_24BIT, &val);
937472377feSShawn Tu if (ret)
938472377feSShawn Tu return ret;
939472377feSShawn Tu
940472377feSShawn Tu if (val != OG01A1B_CHIP_ID) {
941472377feSShawn Tu dev_err(&client->dev, "chip id mismatch: %x!=%x",
942472377feSShawn Tu OG01A1B_CHIP_ID, val);
943472377feSShawn Tu return -ENXIO;
944472377feSShawn Tu }
945472377feSShawn Tu
946472377feSShawn Tu return 0;
947472377feSShawn Tu }
948472377feSShawn Tu
og01a1b_check_hwcfg(struct device * dev)949472377feSShawn Tu static int og01a1b_check_hwcfg(struct device *dev)
950472377feSShawn Tu {
951472377feSShawn Tu struct fwnode_handle *ep;
952472377feSShawn Tu struct fwnode_handle *fwnode = dev_fwnode(dev);
953472377feSShawn Tu struct v4l2_fwnode_endpoint bus_cfg = {
954472377feSShawn Tu .bus_type = V4L2_MBUS_CSI2_DPHY
955472377feSShawn Tu };
956472377feSShawn Tu u32 mclk;
957472377feSShawn Tu int ret;
958472377feSShawn Tu unsigned int i, j;
959472377feSShawn Tu
960472377feSShawn Tu if (!fwnode)
961472377feSShawn Tu return -ENXIO;
962472377feSShawn Tu
963472377feSShawn Tu ret = fwnode_property_read_u32(fwnode, "clock-frequency", &mclk);
964472377feSShawn Tu
965472377feSShawn Tu if (ret) {
966472377feSShawn Tu dev_err(dev, "can't get clock frequency");
967472377feSShawn Tu return ret;
968472377feSShawn Tu }
969472377feSShawn Tu
970472377feSShawn Tu if (mclk != OG01A1B_MCLK) {
971472377feSShawn Tu dev_err(dev, "external clock %d is not supported", mclk);
972472377feSShawn Tu return -EINVAL;
973472377feSShawn Tu }
974472377feSShawn Tu
975472377feSShawn Tu ep = fwnode_graph_get_next_endpoint(fwnode, NULL);
976472377feSShawn Tu if (!ep)
977472377feSShawn Tu return -ENXIO;
978472377feSShawn Tu
979472377feSShawn Tu ret = v4l2_fwnode_endpoint_alloc_parse(ep, &bus_cfg);
980472377feSShawn Tu fwnode_handle_put(ep);
981472377feSShawn Tu if (ret)
982472377feSShawn Tu return ret;
983472377feSShawn Tu
984472377feSShawn Tu if (bus_cfg.bus.mipi_csi2.num_data_lanes != OG01A1B_DATA_LANES) {
985472377feSShawn Tu dev_err(dev, "number of CSI2 data lanes %d is not supported",
986472377feSShawn Tu bus_cfg.bus.mipi_csi2.num_data_lanes);
987472377feSShawn Tu ret = -EINVAL;
988472377feSShawn Tu goto check_hwcfg_error;
989472377feSShawn Tu }
990472377feSShawn Tu
991472377feSShawn Tu if (!bus_cfg.nr_of_link_frequencies) {
992472377feSShawn Tu dev_err(dev, "no link frequencies defined");
993472377feSShawn Tu ret = -EINVAL;
994472377feSShawn Tu goto check_hwcfg_error;
995472377feSShawn Tu }
996472377feSShawn Tu
997472377feSShawn Tu for (i = 0; i < ARRAY_SIZE(link_freq_menu_items); i++) {
998472377feSShawn Tu for (j = 0; j < bus_cfg.nr_of_link_frequencies; j++) {
999472377feSShawn Tu if (link_freq_menu_items[i] ==
1000472377feSShawn Tu bus_cfg.link_frequencies[j])
1001472377feSShawn Tu break;
1002472377feSShawn Tu }
1003472377feSShawn Tu
1004472377feSShawn Tu if (j == bus_cfg.nr_of_link_frequencies) {
1005472377feSShawn Tu dev_err(dev, "no link frequency %lld supported",
1006472377feSShawn Tu link_freq_menu_items[i]);
1007472377feSShawn Tu ret = -EINVAL;
1008472377feSShawn Tu goto check_hwcfg_error;
1009472377feSShawn Tu }
1010472377feSShawn Tu }
1011472377feSShawn Tu
1012472377feSShawn Tu check_hwcfg_error:
1013472377feSShawn Tu v4l2_fwnode_endpoint_free(&bus_cfg);
1014472377feSShawn Tu
1015472377feSShawn Tu return ret;
1016472377feSShawn Tu }
1017472377feSShawn Tu
og01a1b_remove(struct i2c_client * client)1018ed5c2f5fSUwe Kleine-König static void og01a1b_remove(struct i2c_client *client)
1019472377feSShawn Tu {
1020472377feSShawn Tu struct v4l2_subdev *sd = i2c_get_clientdata(client);
1021472377feSShawn Tu struct og01a1b *og01a1b = to_og01a1b(sd);
1022472377feSShawn Tu
1023472377feSShawn Tu v4l2_async_unregister_subdev(sd);
1024472377feSShawn Tu media_entity_cleanup(&sd->entity);
1025472377feSShawn Tu v4l2_ctrl_handler_free(sd->ctrl_handler);
1026472377feSShawn Tu pm_runtime_disable(&client->dev);
1027472377feSShawn Tu mutex_destroy(&og01a1b->mutex);
1028472377feSShawn Tu }
1029472377feSShawn Tu
og01a1b_probe(struct i2c_client * client)1030472377feSShawn Tu static int og01a1b_probe(struct i2c_client *client)
1031472377feSShawn Tu {
1032472377feSShawn Tu struct og01a1b *og01a1b;
1033472377feSShawn Tu int ret;
1034472377feSShawn Tu
1035472377feSShawn Tu ret = og01a1b_check_hwcfg(&client->dev);
1036472377feSShawn Tu if (ret) {
1037472377feSShawn Tu dev_err(&client->dev, "failed to check HW configuration: %d",
1038472377feSShawn Tu ret);
1039472377feSShawn Tu return ret;
1040472377feSShawn Tu }
1041472377feSShawn Tu
1042472377feSShawn Tu og01a1b = devm_kzalloc(&client->dev, sizeof(*og01a1b), GFP_KERNEL);
1043472377feSShawn Tu if (!og01a1b)
1044472377feSShawn Tu return -ENOMEM;
1045472377feSShawn Tu
1046472377feSShawn Tu v4l2_i2c_subdev_init(&og01a1b->sd, client, &og01a1b_subdev_ops);
1047472377feSShawn Tu ret = og01a1b_identify_module(og01a1b);
1048472377feSShawn Tu if (ret) {
1049472377feSShawn Tu dev_err(&client->dev, "failed to find sensor: %d", ret);
1050472377feSShawn Tu return ret;
1051472377feSShawn Tu }
1052472377feSShawn Tu
1053472377feSShawn Tu mutex_init(&og01a1b->mutex);
1054472377feSShawn Tu og01a1b->cur_mode = &supported_modes[0];
1055472377feSShawn Tu ret = og01a1b_init_controls(og01a1b);
1056472377feSShawn Tu if (ret) {
1057472377feSShawn Tu dev_err(&client->dev, "failed to init controls: %d", ret);
1058472377feSShawn Tu goto probe_error_v4l2_ctrl_handler_free;
1059472377feSShawn Tu }
1060472377feSShawn Tu
1061472377feSShawn Tu og01a1b->sd.internal_ops = &og01a1b_internal_ops;
1062472377feSShawn Tu og01a1b->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1063472377feSShawn Tu og01a1b->sd.entity.ops = &og01a1b_subdev_entity_ops;
1064472377feSShawn Tu og01a1b->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
1065472377feSShawn Tu og01a1b->pad.flags = MEDIA_PAD_FL_SOURCE;
1066472377feSShawn Tu ret = media_entity_pads_init(&og01a1b->sd.entity, 1, &og01a1b->pad);
1067472377feSShawn Tu if (ret) {
1068472377feSShawn Tu dev_err(&client->dev, "failed to init entity pads: %d", ret);
1069472377feSShawn Tu goto probe_error_v4l2_ctrl_handler_free;
1070472377feSShawn Tu }
1071472377feSShawn Tu
1072472377feSShawn Tu ret = v4l2_async_register_subdev_sensor(&og01a1b->sd);
1073472377feSShawn Tu if (ret < 0) {
1074472377feSShawn Tu dev_err(&client->dev, "failed to register V4L2 subdev: %d",
1075472377feSShawn Tu ret);
1076472377feSShawn Tu goto probe_error_media_entity_cleanup;
1077472377feSShawn Tu }
1078472377feSShawn Tu
1079472377feSShawn Tu /*
1080472377feSShawn Tu * Device is already turned on by i2c-core with ACPI domain PM.
1081472377feSShawn Tu * Enable runtime PM and turn off the device.
1082472377feSShawn Tu */
1083472377feSShawn Tu pm_runtime_set_active(&client->dev);
1084472377feSShawn Tu pm_runtime_enable(&client->dev);
1085472377feSShawn Tu pm_runtime_idle(&client->dev);
1086472377feSShawn Tu
1087472377feSShawn Tu return 0;
1088472377feSShawn Tu
1089472377feSShawn Tu probe_error_media_entity_cleanup:
1090472377feSShawn Tu media_entity_cleanup(&og01a1b->sd.entity);
1091472377feSShawn Tu
1092472377feSShawn Tu probe_error_v4l2_ctrl_handler_free:
1093472377feSShawn Tu v4l2_ctrl_handler_free(og01a1b->sd.ctrl_handler);
1094472377feSShawn Tu mutex_destroy(&og01a1b->mutex);
1095472377feSShawn Tu
1096472377feSShawn Tu return ret;
1097472377feSShawn Tu }
1098472377feSShawn Tu
1099472377feSShawn Tu static const struct dev_pm_ops og01a1b_pm_ops = {
1100472377feSShawn Tu SET_SYSTEM_SLEEP_PM_OPS(og01a1b_suspend, og01a1b_resume)
1101472377feSShawn Tu };
1102472377feSShawn Tu
1103472377feSShawn Tu #ifdef CONFIG_ACPI
1104472377feSShawn Tu static const struct acpi_device_id og01a1b_acpi_ids[] = {
1105472377feSShawn Tu {"OVTI01AC"},
1106472377feSShawn Tu {}
1107472377feSShawn Tu };
1108472377feSShawn Tu
1109472377feSShawn Tu MODULE_DEVICE_TABLE(acpi, og01a1b_acpi_ids);
1110472377feSShawn Tu #endif
1111472377feSShawn Tu
1112472377feSShawn Tu static struct i2c_driver og01a1b_i2c_driver = {
1113472377feSShawn Tu .driver = {
1114472377feSShawn Tu .name = "og01a1b",
1115472377feSShawn Tu .pm = &og01a1b_pm_ops,
1116472377feSShawn Tu .acpi_match_table = ACPI_PTR(og01a1b_acpi_ids),
1117472377feSShawn Tu },
1118aaeb31c0SUwe Kleine-König .probe = og01a1b_probe,
1119472377feSShawn Tu .remove = og01a1b_remove,
1120472377feSShawn Tu };
1121472377feSShawn Tu
1122472377feSShawn Tu module_i2c_driver(og01a1b_i2c_driver);
1123472377feSShawn Tu
1124*4106cd72SSakari Ailus MODULE_AUTHOR("Shawn Tu");
1125472377feSShawn Tu MODULE_DESCRIPTION("OmniVision OG01A1B sensor driver");
1126472377feSShawn Tu MODULE_LICENSE("GPL v2");
1127