1 /* 2 * Driver for MT9V022, MT9V024, MT9V032, and MT9V034 CMOS Image Sensors 3 * 4 * Copyright (C) 2010, Laurent Pinchart <laurent.pinchart@ideasonboard.com> 5 * 6 * Based on the MT9M001 driver, 7 * 8 * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de> 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License version 2 as 12 * published by the Free Software Foundation. 13 */ 14 15 #include <linux/clk.h> 16 #include <linux/delay.h> 17 #include <linux/i2c.h> 18 #include <linux/log2.h> 19 #include <linux/mutex.h> 20 #include <linux/regmap.h> 21 #include <linux/slab.h> 22 #include <linux/videodev2.h> 23 #include <linux/v4l2-mediabus.h> 24 #include <linux/module.h> 25 26 #include <media/mt9v032.h> 27 #include <media/v4l2-ctrls.h> 28 #include <media/v4l2-device.h> 29 #include <media/v4l2-subdev.h> 30 31 /* The first four rows are black rows. The active area spans 753x481 pixels. */ 32 #define MT9V032_PIXEL_ARRAY_HEIGHT 485 33 #define MT9V032_PIXEL_ARRAY_WIDTH 753 34 35 #define MT9V032_SYSCLK_FREQ_DEF 26600000 36 37 #define MT9V032_CHIP_VERSION 0x00 38 #define MT9V032_CHIP_ID_REV1 0x1311 39 #define MT9V032_CHIP_ID_REV3 0x1313 40 #define MT9V034_CHIP_ID_REV1 0X1324 41 #define MT9V032_COLUMN_START 0x01 42 #define MT9V032_COLUMN_START_MIN 1 43 #define MT9V032_COLUMN_START_DEF 1 44 #define MT9V032_COLUMN_START_MAX 752 45 #define MT9V032_ROW_START 0x02 46 #define MT9V032_ROW_START_MIN 4 47 #define MT9V032_ROW_START_DEF 5 48 #define MT9V032_ROW_START_MAX 482 49 #define MT9V032_WINDOW_HEIGHT 0x03 50 #define MT9V032_WINDOW_HEIGHT_MIN 1 51 #define MT9V032_WINDOW_HEIGHT_DEF 480 52 #define MT9V032_WINDOW_HEIGHT_MAX 480 53 #define MT9V032_WINDOW_WIDTH 0x04 54 #define MT9V032_WINDOW_WIDTH_MIN 1 55 #define MT9V032_WINDOW_WIDTH_DEF 752 56 #define MT9V032_WINDOW_WIDTH_MAX 752 57 #define MT9V032_HORIZONTAL_BLANKING 0x05 58 #define MT9V032_HORIZONTAL_BLANKING_MIN 43 59 #define MT9V034_HORIZONTAL_BLANKING_MIN 61 60 #define MT9V032_HORIZONTAL_BLANKING_DEF 94 61 #define MT9V032_HORIZONTAL_BLANKING_MAX 1023 62 #define MT9V032_VERTICAL_BLANKING 0x06 63 #define MT9V032_VERTICAL_BLANKING_MIN 4 64 #define MT9V034_VERTICAL_BLANKING_MIN 2 65 #define MT9V032_VERTICAL_BLANKING_DEF 45 66 #define MT9V032_VERTICAL_BLANKING_MAX 3000 67 #define MT9V034_VERTICAL_BLANKING_MAX 32288 68 #define MT9V032_CHIP_CONTROL 0x07 69 #define MT9V032_CHIP_CONTROL_MASTER_MODE (1 << 3) 70 #define MT9V032_CHIP_CONTROL_DOUT_ENABLE (1 << 7) 71 #define MT9V032_CHIP_CONTROL_SEQUENTIAL (1 << 8) 72 #define MT9V032_SHUTTER_WIDTH1 0x08 73 #define MT9V032_SHUTTER_WIDTH2 0x09 74 #define MT9V032_SHUTTER_WIDTH_CONTROL 0x0a 75 #define MT9V032_TOTAL_SHUTTER_WIDTH 0x0b 76 #define MT9V032_TOTAL_SHUTTER_WIDTH_MIN 1 77 #define MT9V034_TOTAL_SHUTTER_WIDTH_MIN 0 78 #define MT9V032_TOTAL_SHUTTER_WIDTH_DEF 480 79 #define MT9V032_TOTAL_SHUTTER_WIDTH_MAX 32767 80 #define MT9V034_TOTAL_SHUTTER_WIDTH_MAX 32765 81 #define MT9V032_RESET 0x0c 82 #define MT9V032_READ_MODE 0x0d 83 #define MT9V032_READ_MODE_ROW_BIN_MASK (3 << 0) 84 #define MT9V032_READ_MODE_ROW_BIN_SHIFT 0 85 #define MT9V032_READ_MODE_COLUMN_BIN_MASK (3 << 2) 86 #define MT9V032_READ_MODE_COLUMN_BIN_SHIFT 2 87 #define MT9V032_READ_MODE_ROW_FLIP (1 << 4) 88 #define MT9V032_READ_MODE_COLUMN_FLIP (1 << 5) 89 #define MT9V032_READ_MODE_DARK_COLUMNS (1 << 6) 90 #define MT9V032_READ_MODE_DARK_ROWS (1 << 7) 91 #define MT9V032_READ_MODE_RESERVED 0x0300 92 #define MT9V032_PIXEL_OPERATION_MODE 0x0f 93 #define MT9V034_PIXEL_OPERATION_MODE_HDR (1 << 0) 94 #define MT9V034_PIXEL_OPERATION_MODE_COLOR (1 << 1) 95 #define MT9V032_PIXEL_OPERATION_MODE_COLOR (1 << 2) 96 #define MT9V032_PIXEL_OPERATION_MODE_HDR (1 << 6) 97 #define MT9V032_ANALOG_GAIN 0x35 98 #define MT9V032_ANALOG_GAIN_MIN 16 99 #define MT9V032_ANALOG_GAIN_DEF 16 100 #define MT9V032_ANALOG_GAIN_MAX 64 101 #define MT9V032_MAX_ANALOG_GAIN 0x36 102 #define MT9V032_MAX_ANALOG_GAIN_MAX 127 103 #define MT9V032_FRAME_DARK_AVERAGE 0x42 104 #define MT9V032_DARK_AVG_THRESH 0x46 105 #define MT9V032_DARK_AVG_LOW_THRESH_MASK (255 << 0) 106 #define MT9V032_DARK_AVG_LOW_THRESH_SHIFT 0 107 #define MT9V032_DARK_AVG_HIGH_THRESH_MASK (255 << 8) 108 #define MT9V032_DARK_AVG_HIGH_THRESH_SHIFT 8 109 #define MT9V032_ROW_NOISE_CORR_CONTROL 0x70 110 #define MT9V034_ROW_NOISE_CORR_ENABLE (1 << 0) 111 #define MT9V034_ROW_NOISE_CORR_USE_BLK_AVG (1 << 1) 112 #define MT9V032_ROW_NOISE_CORR_ENABLE (1 << 5) 113 #define MT9V032_ROW_NOISE_CORR_USE_BLK_AVG (1 << 7) 114 #define MT9V032_PIXEL_CLOCK 0x74 115 #define MT9V034_PIXEL_CLOCK 0x72 116 #define MT9V032_PIXEL_CLOCK_INV_LINE (1 << 0) 117 #define MT9V032_PIXEL_CLOCK_INV_FRAME (1 << 1) 118 #define MT9V032_PIXEL_CLOCK_XOR_LINE (1 << 2) 119 #define MT9V032_PIXEL_CLOCK_CONT_LINE (1 << 3) 120 #define MT9V032_PIXEL_CLOCK_INV_PXL_CLK (1 << 4) 121 #define MT9V032_TEST_PATTERN 0x7f 122 #define MT9V032_TEST_PATTERN_DATA_MASK (1023 << 0) 123 #define MT9V032_TEST_PATTERN_DATA_SHIFT 0 124 #define MT9V032_TEST_PATTERN_USE_DATA (1 << 10) 125 #define MT9V032_TEST_PATTERN_GRAY_MASK (3 << 11) 126 #define MT9V032_TEST_PATTERN_GRAY_NONE (0 << 11) 127 #define MT9V032_TEST_PATTERN_GRAY_VERTICAL (1 << 11) 128 #define MT9V032_TEST_PATTERN_GRAY_HORIZONTAL (2 << 11) 129 #define MT9V032_TEST_PATTERN_GRAY_DIAGONAL (3 << 11) 130 #define MT9V032_TEST_PATTERN_ENABLE (1 << 13) 131 #define MT9V032_TEST_PATTERN_FLIP (1 << 14) 132 #define MT9V032_AEC_AGC_ENABLE 0xaf 133 #define MT9V032_AEC_ENABLE (1 << 0) 134 #define MT9V032_AGC_ENABLE (1 << 1) 135 #define MT9V032_THERMAL_INFO 0xc1 136 137 enum mt9v032_model { 138 MT9V032_MODEL_V022_COLOR, /* MT9V022IX7ATC */ 139 MT9V032_MODEL_V022_MONO, /* MT9V022IX7ATM */ 140 MT9V032_MODEL_V024_COLOR, /* MT9V024IA7XTC */ 141 MT9V032_MODEL_V024_MONO, /* MT9V024IA7XTM */ 142 MT9V032_MODEL_V032_COLOR, /* MT9V032C12STM */ 143 MT9V032_MODEL_V032_MONO, /* MT9V032C12STC */ 144 MT9V032_MODEL_V034_COLOR, 145 MT9V032_MODEL_V034_MONO, 146 }; 147 148 struct mt9v032_model_version { 149 unsigned int version; 150 const char *name; 151 }; 152 153 struct mt9v032_model_data { 154 unsigned int min_row_time; 155 unsigned int min_hblank; 156 unsigned int min_vblank; 157 unsigned int max_vblank; 158 unsigned int min_shutter; 159 unsigned int max_shutter; 160 unsigned int pclk_reg; 161 }; 162 163 struct mt9v032_model_info { 164 const struct mt9v032_model_data *data; 165 bool color; 166 }; 167 168 static const struct mt9v032_model_version mt9v032_versions[] = { 169 { MT9V032_CHIP_ID_REV1, "MT9V022/MT9V032 rev1/2" }, 170 { MT9V032_CHIP_ID_REV3, "MT9V022/MT9V032 rev3" }, 171 { MT9V034_CHIP_ID_REV1, "MT9V024/MT9V034 rev1" }, 172 }; 173 174 static const struct mt9v032_model_data mt9v032_model_data[] = { 175 { 176 /* MT9V022, MT9V032 revisions 1/2/3 */ 177 .min_row_time = 660, 178 .min_hblank = MT9V032_HORIZONTAL_BLANKING_MIN, 179 .min_vblank = MT9V032_VERTICAL_BLANKING_MIN, 180 .max_vblank = MT9V032_VERTICAL_BLANKING_MAX, 181 .min_shutter = MT9V032_TOTAL_SHUTTER_WIDTH_MIN, 182 .max_shutter = MT9V032_TOTAL_SHUTTER_WIDTH_MAX, 183 .pclk_reg = MT9V032_PIXEL_CLOCK, 184 }, { 185 /* MT9V024, MT9V034 */ 186 .min_row_time = 690, 187 .min_hblank = MT9V034_HORIZONTAL_BLANKING_MIN, 188 .min_vblank = MT9V034_VERTICAL_BLANKING_MIN, 189 .max_vblank = MT9V034_VERTICAL_BLANKING_MAX, 190 .min_shutter = MT9V034_TOTAL_SHUTTER_WIDTH_MIN, 191 .max_shutter = MT9V034_TOTAL_SHUTTER_WIDTH_MAX, 192 .pclk_reg = MT9V034_PIXEL_CLOCK, 193 }, 194 }; 195 196 static const struct mt9v032_model_info mt9v032_models[] = { 197 [MT9V032_MODEL_V022_COLOR] = { 198 .data = &mt9v032_model_data[0], 199 .color = true, 200 }, 201 [MT9V032_MODEL_V022_MONO] = { 202 .data = &mt9v032_model_data[0], 203 .color = false, 204 }, 205 [MT9V032_MODEL_V024_COLOR] = { 206 .data = &mt9v032_model_data[1], 207 .color = true, 208 }, 209 [MT9V032_MODEL_V024_MONO] = { 210 .data = &mt9v032_model_data[1], 211 .color = false, 212 }, 213 [MT9V032_MODEL_V032_COLOR] = { 214 .data = &mt9v032_model_data[0], 215 .color = true, 216 }, 217 [MT9V032_MODEL_V032_MONO] = { 218 .data = &mt9v032_model_data[0], 219 .color = false, 220 }, 221 [MT9V032_MODEL_V034_COLOR] = { 222 .data = &mt9v032_model_data[1], 223 .color = true, 224 }, 225 [MT9V032_MODEL_V034_MONO] = { 226 .data = &mt9v032_model_data[1], 227 .color = false, 228 }, 229 }; 230 231 struct mt9v032 { 232 struct v4l2_subdev subdev; 233 struct media_pad pad; 234 235 struct v4l2_mbus_framefmt format; 236 struct v4l2_rect crop; 237 unsigned int hratio; 238 unsigned int vratio; 239 240 struct v4l2_ctrl_handler ctrls; 241 struct { 242 struct v4l2_ctrl *link_freq; 243 struct v4l2_ctrl *pixel_rate; 244 }; 245 246 struct mutex power_lock; 247 int power_count; 248 249 struct regmap *regmap; 250 struct clk *clk; 251 252 struct mt9v032_platform_data *pdata; 253 const struct mt9v032_model_info *model; 254 const struct mt9v032_model_version *version; 255 256 u32 sysclk; 257 u16 aec_agc; 258 u16 hblank; 259 struct { 260 struct v4l2_ctrl *test_pattern; 261 struct v4l2_ctrl *test_pattern_color; 262 }; 263 }; 264 265 static struct mt9v032 *to_mt9v032(struct v4l2_subdev *sd) 266 { 267 return container_of(sd, struct mt9v032, subdev); 268 } 269 270 static int 271 mt9v032_update_aec_agc(struct mt9v032 *mt9v032, u16 which, int enable) 272 { 273 struct regmap *map = mt9v032->regmap; 274 u16 value = mt9v032->aec_agc; 275 int ret; 276 277 if (enable) 278 value |= which; 279 else 280 value &= ~which; 281 282 ret = regmap_write(map, MT9V032_AEC_AGC_ENABLE, value); 283 if (ret < 0) 284 return ret; 285 286 mt9v032->aec_agc = value; 287 return 0; 288 } 289 290 static int 291 mt9v032_update_hblank(struct mt9v032 *mt9v032) 292 { 293 struct v4l2_rect *crop = &mt9v032->crop; 294 unsigned int min_hblank = mt9v032->model->data->min_hblank; 295 unsigned int hblank; 296 297 if (mt9v032->version->version == MT9V034_CHIP_ID_REV1) 298 min_hblank += (mt9v032->hratio - 1) * 10; 299 min_hblank = max_t(int, mt9v032->model->data->min_row_time - crop->width, 300 min_hblank); 301 hblank = max_t(unsigned int, mt9v032->hblank, min_hblank); 302 303 return regmap_write(mt9v032->regmap, MT9V032_HORIZONTAL_BLANKING, 304 hblank); 305 } 306 307 static int mt9v032_power_on(struct mt9v032 *mt9v032) 308 { 309 struct regmap *map = mt9v032->regmap; 310 int ret; 311 312 ret = clk_set_rate(mt9v032->clk, mt9v032->sysclk); 313 if (ret < 0) 314 return ret; 315 316 ret = clk_prepare_enable(mt9v032->clk); 317 if (ret) 318 return ret; 319 320 udelay(1); 321 322 /* Reset the chip and stop data read out */ 323 ret = regmap_write(map, MT9V032_RESET, 1); 324 if (ret < 0) 325 return ret; 326 327 ret = regmap_write(map, MT9V032_RESET, 0); 328 if (ret < 0) 329 return ret; 330 331 return regmap_write(map, MT9V032_CHIP_CONTROL, 0); 332 } 333 334 static void mt9v032_power_off(struct mt9v032 *mt9v032) 335 { 336 clk_disable_unprepare(mt9v032->clk); 337 } 338 339 static int __mt9v032_set_power(struct mt9v032 *mt9v032, bool on) 340 { 341 struct regmap *map = mt9v032->regmap; 342 int ret; 343 344 if (!on) { 345 mt9v032_power_off(mt9v032); 346 return 0; 347 } 348 349 ret = mt9v032_power_on(mt9v032); 350 if (ret < 0) 351 return ret; 352 353 /* Configure the pixel clock polarity */ 354 if (mt9v032->pdata && mt9v032->pdata->clk_pol) { 355 ret = regmap_write(map, mt9v032->model->data->pclk_reg, 356 MT9V032_PIXEL_CLOCK_INV_PXL_CLK); 357 if (ret < 0) 358 return ret; 359 } 360 361 /* Disable the noise correction algorithm and restore the controls. */ 362 ret = regmap_write(map, MT9V032_ROW_NOISE_CORR_CONTROL, 0); 363 if (ret < 0) 364 return ret; 365 366 return v4l2_ctrl_handler_setup(&mt9v032->ctrls); 367 } 368 369 /* ----------------------------------------------------------------------------- 370 * V4L2 subdev video operations 371 */ 372 373 static struct v4l2_mbus_framefmt * 374 __mt9v032_get_pad_format(struct mt9v032 *mt9v032, struct v4l2_subdev_fh *fh, 375 unsigned int pad, enum v4l2_subdev_format_whence which) 376 { 377 switch (which) { 378 case V4L2_SUBDEV_FORMAT_TRY: 379 return v4l2_subdev_get_try_format(fh, pad); 380 case V4L2_SUBDEV_FORMAT_ACTIVE: 381 return &mt9v032->format; 382 default: 383 return NULL; 384 } 385 } 386 387 static struct v4l2_rect * 388 __mt9v032_get_pad_crop(struct mt9v032 *mt9v032, struct v4l2_subdev_fh *fh, 389 unsigned int pad, enum v4l2_subdev_format_whence which) 390 { 391 switch (which) { 392 case V4L2_SUBDEV_FORMAT_TRY: 393 return v4l2_subdev_get_try_crop(fh, pad); 394 case V4L2_SUBDEV_FORMAT_ACTIVE: 395 return &mt9v032->crop; 396 default: 397 return NULL; 398 } 399 } 400 401 static int mt9v032_s_stream(struct v4l2_subdev *subdev, int enable) 402 { 403 const u16 mode = MT9V032_CHIP_CONTROL_MASTER_MODE 404 | MT9V032_CHIP_CONTROL_DOUT_ENABLE 405 | MT9V032_CHIP_CONTROL_SEQUENTIAL; 406 struct mt9v032 *mt9v032 = to_mt9v032(subdev); 407 struct v4l2_rect *crop = &mt9v032->crop; 408 struct regmap *map = mt9v032->regmap; 409 unsigned int hbin; 410 unsigned int vbin; 411 int ret; 412 413 if (!enable) 414 return regmap_update_bits(map, MT9V032_CHIP_CONTROL, mode, 0); 415 416 /* Configure the window size and row/column bin */ 417 hbin = fls(mt9v032->hratio) - 1; 418 vbin = fls(mt9v032->vratio) - 1; 419 ret = regmap_update_bits(map, MT9V032_READ_MODE, 420 ~MT9V032_READ_MODE_RESERVED, 421 hbin << MT9V032_READ_MODE_COLUMN_BIN_SHIFT | 422 vbin << MT9V032_READ_MODE_ROW_BIN_SHIFT); 423 if (ret < 0) 424 return ret; 425 426 ret = regmap_write(map, MT9V032_COLUMN_START, crop->left); 427 if (ret < 0) 428 return ret; 429 430 ret = regmap_write(map, MT9V032_ROW_START, crop->top); 431 if (ret < 0) 432 return ret; 433 434 ret = regmap_write(map, MT9V032_WINDOW_WIDTH, crop->width); 435 if (ret < 0) 436 return ret; 437 438 ret = regmap_write(map, MT9V032_WINDOW_HEIGHT, crop->height); 439 if (ret < 0) 440 return ret; 441 442 ret = mt9v032_update_hblank(mt9v032); 443 if (ret < 0) 444 return ret; 445 446 /* Switch to master "normal" mode */ 447 return regmap_update_bits(map, MT9V032_CHIP_CONTROL, mode, mode); 448 } 449 450 static int mt9v032_enum_mbus_code(struct v4l2_subdev *subdev, 451 struct v4l2_subdev_fh *fh, 452 struct v4l2_subdev_mbus_code_enum *code) 453 { 454 if (code->index > 0) 455 return -EINVAL; 456 457 code->code = MEDIA_BUS_FMT_SGRBG10_1X10; 458 return 0; 459 } 460 461 static int mt9v032_enum_frame_size(struct v4l2_subdev *subdev, 462 struct v4l2_subdev_fh *fh, 463 struct v4l2_subdev_frame_size_enum *fse) 464 { 465 if (fse->index >= 3 || fse->code != MEDIA_BUS_FMT_SGRBG10_1X10) 466 return -EINVAL; 467 468 fse->min_width = MT9V032_WINDOW_WIDTH_DEF / (1 << fse->index); 469 fse->max_width = fse->min_width; 470 fse->min_height = MT9V032_WINDOW_HEIGHT_DEF / (1 << fse->index); 471 fse->max_height = fse->min_height; 472 473 return 0; 474 } 475 476 static int mt9v032_get_format(struct v4l2_subdev *subdev, 477 struct v4l2_subdev_fh *fh, 478 struct v4l2_subdev_format *format) 479 { 480 struct mt9v032 *mt9v032 = to_mt9v032(subdev); 481 482 format->format = *__mt9v032_get_pad_format(mt9v032, fh, format->pad, 483 format->which); 484 return 0; 485 } 486 487 static void mt9v032_configure_pixel_rate(struct mt9v032 *mt9v032) 488 { 489 struct i2c_client *client = v4l2_get_subdevdata(&mt9v032->subdev); 490 int ret; 491 492 ret = v4l2_ctrl_s_ctrl_int64(mt9v032->pixel_rate, 493 mt9v032->sysclk / mt9v032->hratio); 494 if (ret < 0) 495 dev_warn(&client->dev, "failed to set pixel rate (%d)\n", ret); 496 } 497 498 static unsigned int mt9v032_calc_ratio(unsigned int input, unsigned int output) 499 { 500 /* Compute the power-of-two binning factor closest to the input size to 501 * output size ratio. Given that the output size is bounded by input/4 502 * and input, a generic implementation would be an ineffective luxury. 503 */ 504 if (output * 3 > input * 2) 505 return 1; 506 if (output * 3 > input) 507 return 2; 508 return 4; 509 } 510 511 static int mt9v032_set_format(struct v4l2_subdev *subdev, 512 struct v4l2_subdev_fh *fh, 513 struct v4l2_subdev_format *format) 514 { 515 struct mt9v032 *mt9v032 = to_mt9v032(subdev); 516 struct v4l2_mbus_framefmt *__format; 517 struct v4l2_rect *__crop; 518 unsigned int width; 519 unsigned int height; 520 unsigned int hratio; 521 unsigned int vratio; 522 523 __crop = __mt9v032_get_pad_crop(mt9v032, fh, format->pad, 524 format->which); 525 526 /* Clamp the width and height to avoid dividing by zero. */ 527 width = clamp(ALIGN(format->format.width, 2), 528 max_t(unsigned int, __crop->width / 4, 529 MT9V032_WINDOW_WIDTH_MIN), 530 __crop->width); 531 height = clamp(ALIGN(format->format.height, 2), 532 max_t(unsigned int, __crop->height / 4, 533 MT9V032_WINDOW_HEIGHT_MIN), 534 __crop->height); 535 536 hratio = mt9v032_calc_ratio(__crop->width, width); 537 vratio = mt9v032_calc_ratio(__crop->height, height); 538 539 __format = __mt9v032_get_pad_format(mt9v032, fh, format->pad, 540 format->which); 541 __format->width = __crop->width / hratio; 542 __format->height = __crop->height / vratio; 543 544 if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE) { 545 mt9v032->hratio = hratio; 546 mt9v032->vratio = vratio; 547 mt9v032_configure_pixel_rate(mt9v032); 548 } 549 550 format->format = *__format; 551 552 return 0; 553 } 554 555 static int mt9v032_get_crop(struct v4l2_subdev *subdev, 556 struct v4l2_subdev_fh *fh, 557 struct v4l2_subdev_crop *crop) 558 { 559 struct mt9v032 *mt9v032 = to_mt9v032(subdev); 560 561 crop->rect = *__mt9v032_get_pad_crop(mt9v032, fh, crop->pad, 562 crop->which); 563 return 0; 564 } 565 566 static int mt9v032_set_crop(struct v4l2_subdev *subdev, 567 struct v4l2_subdev_fh *fh, 568 struct v4l2_subdev_crop *crop) 569 { 570 struct mt9v032 *mt9v032 = to_mt9v032(subdev); 571 struct v4l2_mbus_framefmt *__format; 572 struct v4l2_rect *__crop; 573 struct v4l2_rect rect; 574 575 /* Clamp the crop rectangle boundaries and align them to a non multiple 576 * of 2 pixels to ensure a GRBG Bayer pattern. 577 */ 578 rect.left = clamp(ALIGN(crop->rect.left + 1, 2) - 1, 579 MT9V032_COLUMN_START_MIN, 580 MT9V032_COLUMN_START_MAX); 581 rect.top = clamp(ALIGN(crop->rect.top + 1, 2) - 1, 582 MT9V032_ROW_START_MIN, 583 MT9V032_ROW_START_MAX); 584 rect.width = clamp_t(unsigned int, ALIGN(crop->rect.width, 2), 585 MT9V032_WINDOW_WIDTH_MIN, 586 MT9V032_WINDOW_WIDTH_MAX); 587 rect.height = clamp_t(unsigned int, ALIGN(crop->rect.height, 2), 588 MT9V032_WINDOW_HEIGHT_MIN, 589 MT9V032_WINDOW_HEIGHT_MAX); 590 591 rect.width = min_t(unsigned int, 592 rect.width, MT9V032_PIXEL_ARRAY_WIDTH - rect.left); 593 rect.height = min_t(unsigned int, 594 rect.height, MT9V032_PIXEL_ARRAY_HEIGHT - rect.top); 595 596 __crop = __mt9v032_get_pad_crop(mt9v032, fh, crop->pad, crop->which); 597 598 if (rect.width != __crop->width || rect.height != __crop->height) { 599 /* Reset the output image size if the crop rectangle size has 600 * been modified. 601 */ 602 __format = __mt9v032_get_pad_format(mt9v032, fh, crop->pad, 603 crop->which); 604 __format->width = rect.width; 605 __format->height = rect.height; 606 if (crop->which == V4L2_SUBDEV_FORMAT_ACTIVE) { 607 mt9v032->hratio = 1; 608 mt9v032->vratio = 1; 609 mt9v032_configure_pixel_rate(mt9v032); 610 } 611 } 612 613 *__crop = rect; 614 crop->rect = rect; 615 616 return 0; 617 } 618 619 /* ----------------------------------------------------------------------------- 620 * V4L2 subdev control operations 621 */ 622 623 #define V4L2_CID_TEST_PATTERN_COLOR (V4L2_CID_USER_BASE | 0x1001) 624 625 static int mt9v032_s_ctrl(struct v4l2_ctrl *ctrl) 626 { 627 struct mt9v032 *mt9v032 = 628 container_of(ctrl->handler, struct mt9v032, ctrls); 629 struct regmap *map = mt9v032->regmap; 630 u32 freq; 631 u16 data; 632 633 switch (ctrl->id) { 634 case V4L2_CID_AUTOGAIN: 635 return mt9v032_update_aec_agc(mt9v032, MT9V032_AGC_ENABLE, 636 ctrl->val); 637 638 case V4L2_CID_GAIN: 639 return regmap_write(map, MT9V032_ANALOG_GAIN, ctrl->val); 640 641 case V4L2_CID_EXPOSURE_AUTO: 642 return mt9v032_update_aec_agc(mt9v032, MT9V032_AEC_ENABLE, 643 !ctrl->val); 644 645 case V4L2_CID_EXPOSURE: 646 return regmap_write(map, MT9V032_TOTAL_SHUTTER_WIDTH, 647 ctrl->val); 648 649 case V4L2_CID_HBLANK: 650 mt9v032->hblank = ctrl->val; 651 return mt9v032_update_hblank(mt9v032); 652 653 case V4L2_CID_VBLANK: 654 return regmap_write(map, MT9V032_VERTICAL_BLANKING, 655 ctrl->val); 656 657 case V4L2_CID_PIXEL_RATE: 658 case V4L2_CID_LINK_FREQ: 659 if (mt9v032->link_freq == NULL) 660 break; 661 662 freq = mt9v032->pdata->link_freqs[mt9v032->link_freq->val]; 663 *mt9v032->pixel_rate->p_new.p_s64 = freq; 664 mt9v032->sysclk = freq; 665 break; 666 667 case V4L2_CID_TEST_PATTERN: 668 switch (mt9v032->test_pattern->val) { 669 case 0: 670 data = 0; 671 break; 672 case 1: 673 data = MT9V032_TEST_PATTERN_GRAY_VERTICAL 674 | MT9V032_TEST_PATTERN_ENABLE; 675 break; 676 case 2: 677 data = MT9V032_TEST_PATTERN_GRAY_HORIZONTAL 678 | MT9V032_TEST_PATTERN_ENABLE; 679 break; 680 case 3: 681 data = MT9V032_TEST_PATTERN_GRAY_DIAGONAL 682 | MT9V032_TEST_PATTERN_ENABLE; 683 break; 684 default: 685 data = (mt9v032->test_pattern_color->val << 686 MT9V032_TEST_PATTERN_DATA_SHIFT) 687 | MT9V032_TEST_PATTERN_USE_DATA 688 | MT9V032_TEST_PATTERN_ENABLE 689 | MT9V032_TEST_PATTERN_FLIP; 690 break; 691 } 692 return regmap_write(map, MT9V032_TEST_PATTERN, data); 693 } 694 695 return 0; 696 } 697 698 static struct v4l2_ctrl_ops mt9v032_ctrl_ops = { 699 .s_ctrl = mt9v032_s_ctrl, 700 }; 701 702 static const char * const mt9v032_test_pattern_menu[] = { 703 "Disabled", 704 "Gray Vertical Shade", 705 "Gray Horizontal Shade", 706 "Gray Diagonal Shade", 707 "Plain", 708 }; 709 710 static const struct v4l2_ctrl_config mt9v032_test_pattern_color = { 711 .ops = &mt9v032_ctrl_ops, 712 .id = V4L2_CID_TEST_PATTERN_COLOR, 713 .type = V4L2_CTRL_TYPE_INTEGER, 714 .name = "Test Pattern Color", 715 .min = 0, 716 .max = 1023, 717 .step = 1, 718 .def = 0, 719 .flags = 0, 720 }; 721 722 /* ----------------------------------------------------------------------------- 723 * V4L2 subdev core operations 724 */ 725 726 static int mt9v032_set_power(struct v4l2_subdev *subdev, int on) 727 { 728 struct mt9v032 *mt9v032 = to_mt9v032(subdev); 729 int ret = 0; 730 731 mutex_lock(&mt9v032->power_lock); 732 733 /* If the power count is modified from 0 to != 0 or from != 0 to 0, 734 * update the power state. 735 */ 736 if (mt9v032->power_count == !on) { 737 ret = __mt9v032_set_power(mt9v032, !!on); 738 if (ret < 0) 739 goto done; 740 } 741 742 /* Update the power count. */ 743 mt9v032->power_count += on ? 1 : -1; 744 WARN_ON(mt9v032->power_count < 0); 745 746 done: 747 mutex_unlock(&mt9v032->power_lock); 748 return ret; 749 } 750 751 /* ----------------------------------------------------------------------------- 752 * V4L2 subdev internal operations 753 */ 754 755 static int mt9v032_registered(struct v4l2_subdev *subdev) 756 { 757 struct i2c_client *client = v4l2_get_subdevdata(subdev); 758 struct mt9v032 *mt9v032 = to_mt9v032(subdev); 759 unsigned int i; 760 u32 version; 761 int ret; 762 763 dev_info(&client->dev, "Probing MT9V032 at address 0x%02x\n", 764 client->addr); 765 766 ret = mt9v032_power_on(mt9v032); 767 if (ret < 0) { 768 dev_err(&client->dev, "MT9V032 power up failed\n"); 769 return ret; 770 } 771 772 /* Read and check the sensor version */ 773 ret = regmap_read(mt9v032->regmap, MT9V032_CHIP_VERSION, &version); 774 if (ret < 0) { 775 dev_err(&client->dev, "Failed reading chip version\n"); 776 return ret; 777 } 778 779 for (i = 0; i < ARRAY_SIZE(mt9v032_versions); ++i) { 780 if (mt9v032_versions[i].version == version) { 781 mt9v032->version = &mt9v032_versions[i]; 782 break; 783 } 784 } 785 786 if (mt9v032->version == NULL) { 787 dev_err(&client->dev, "Unsupported chip version 0x%04x\n", 788 version); 789 return -ENODEV; 790 } 791 792 mt9v032_power_off(mt9v032); 793 794 dev_info(&client->dev, "%s detected at address 0x%02x\n", 795 mt9v032->version->name, client->addr); 796 797 mt9v032_configure_pixel_rate(mt9v032); 798 799 return ret; 800 } 801 802 static int mt9v032_open(struct v4l2_subdev *subdev, struct v4l2_subdev_fh *fh) 803 { 804 struct mt9v032 *mt9v032 = to_mt9v032(subdev); 805 struct v4l2_mbus_framefmt *format; 806 struct v4l2_rect *crop; 807 808 crop = v4l2_subdev_get_try_crop(fh, 0); 809 crop->left = MT9V032_COLUMN_START_DEF; 810 crop->top = MT9V032_ROW_START_DEF; 811 crop->width = MT9V032_WINDOW_WIDTH_DEF; 812 crop->height = MT9V032_WINDOW_HEIGHT_DEF; 813 814 format = v4l2_subdev_get_try_format(fh, 0); 815 816 if (mt9v032->model->color) 817 format->code = MEDIA_BUS_FMT_SGRBG10_1X10; 818 else 819 format->code = MEDIA_BUS_FMT_Y10_1X10; 820 821 format->width = MT9V032_WINDOW_WIDTH_DEF; 822 format->height = MT9V032_WINDOW_HEIGHT_DEF; 823 format->field = V4L2_FIELD_NONE; 824 format->colorspace = V4L2_COLORSPACE_SRGB; 825 826 return mt9v032_set_power(subdev, 1); 827 } 828 829 static int mt9v032_close(struct v4l2_subdev *subdev, struct v4l2_subdev_fh *fh) 830 { 831 return mt9v032_set_power(subdev, 0); 832 } 833 834 static struct v4l2_subdev_core_ops mt9v032_subdev_core_ops = { 835 .s_power = mt9v032_set_power, 836 }; 837 838 static struct v4l2_subdev_video_ops mt9v032_subdev_video_ops = { 839 .s_stream = mt9v032_s_stream, 840 }; 841 842 static struct v4l2_subdev_pad_ops mt9v032_subdev_pad_ops = { 843 .enum_mbus_code = mt9v032_enum_mbus_code, 844 .enum_frame_size = mt9v032_enum_frame_size, 845 .get_fmt = mt9v032_get_format, 846 .set_fmt = mt9v032_set_format, 847 .get_crop = mt9v032_get_crop, 848 .set_crop = mt9v032_set_crop, 849 }; 850 851 static struct v4l2_subdev_ops mt9v032_subdev_ops = { 852 .core = &mt9v032_subdev_core_ops, 853 .video = &mt9v032_subdev_video_ops, 854 .pad = &mt9v032_subdev_pad_ops, 855 }; 856 857 static const struct v4l2_subdev_internal_ops mt9v032_subdev_internal_ops = { 858 .registered = mt9v032_registered, 859 .open = mt9v032_open, 860 .close = mt9v032_close, 861 }; 862 863 static const struct regmap_config mt9v032_regmap_config = { 864 .reg_bits = 8, 865 .val_bits = 16, 866 .max_register = 0xff, 867 .cache_type = REGCACHE_RBTREE, 868 }; 869 870 /* ----------------------------------------------------------------------------- 871 * Driver initialization and probing 872 */ 873 874 static int mt9v032_probe(struct i2c_client *client, 875 const struct i2c_device_id *did) 876 { 877 struct mt9v032_platform_data *pdata = client->dev.platform_data; 878 struct mt9v032 *mt9v032; 879 unsigned int i; 880 int ret; 881 882 if (!i2c_check_functionality(client->adapter, 883 I2C_FUNC_SMBUS_WORD_DATA)) { 884 dev_warn(&client->adapter->dev, 885 "I2C-Adapter doesn't support I2C_FUNC_SMBUS_WORD\n"); 886 return -EIO; 887 } 888 889 mt9v032 = devm_kzalloc(&client->dev, sizeof(*mt9v032), GFP_KERNEL); 890 if (!mt9v032) 891 return -ENOMEM; 892 893 mt9v032->regmap = devm_regmap_init_i2c(client, &mt9v032_regmap_config); 894 if (IS_ERR(mt9v032->regmap)) 895 return PTR_ERR(mt9v032->regmap); 896 897 mt9v032->clk = devm_clk_get(&client->dev, NULL); 898 if (IS_ERR(mt9v032->clk)) 899 return PTR_ERR(mt9v032->clk); 900 901 mutex_init(&mt9v032->power_lock); 902 mt9v032->pdata = pdata; 903 mt9v032->model = (const void *)did->driver_data; 904 905 v4l2_ctrl_handler_init(&mt9v032->ctrls, 10); 906 907 v4l2_ctrl_new_std(&mt9v032->ctrls, &mt9v032_ctrl_ops, 908 V4L2_CID_AUTOGAIN, 0, 1, 1, 1); 909 v4l2_ctrl_new_std(&mt9v032->ctrls, &mt9v032_ctrl_ops, 910 V4L2_CID_GAIN, MT9V032_ANALOG_GAIN_MIN, 911 MT9V032_ANALOG_GAIN_MAX, 1, MT9V032_ANALOG_GAIN_DEF); 912 v4l2_ctrl_new_std_menu(&mt9v032->ctrls, &mt9v032_ctrl_ops, 913 V4L2_CID_EXPOSURE_AUTO, V4L2_EXPOSURE_MANUAL, 0, 914 V4L2_EXPOSURE_AUTO); 915 v4l2_ctrl_new_std(&mt9v032->ctrls, &mt9v032_ctrl_ops, 916 V4L2_CID_EXPOSURE, mt9v032->model->data->min_shutter, 917 mt9v032->model->data->max_shutter, 1, 918 MT9V032_TOTAL_SHUTTER_WIDTH_DEF); 919 v4l2_ctrl_new_std(&mt9v032->ctrls, &mt9v032_ctrl_ops, 920 V4L2_CID_HBLANK, mt9v032->model->data->min_hblank, 921 MT9V032_HORIZONTAL_BLANKING_MAX, 1, 922 MT9V032_HORIZONTAL_BLANKING_DEF); 923 v4l2_ctrl_new_std(&mt9v032->ctrls, &mt9v032_ctrl_ops, 924 V4L2_CID_VBLANK, mt9v032->model->data->min_vblank, 925 mt9v032->model->data->max_vblank, 1, 926 MT9V032_VERTICAL_BLANKING_DEF); 927 mt9v032->test_pattern = v4l2_ctrl_new_std_menu_items(&mt9v032->ctrls, 928 &mt9v032_ctrl_ops, V4L2_CID_TEST_PATTERN, 929 ARRAY_SIZE(mt9v032_test_pattern_menu) - 1, 0, 0, 930 mt9v032_test_pattern_menu); 931 mt9v032->test_pattern_color = v4l2_ctrl_new_custom(&mt9v032->ctrls, 932 &mt9v032_test_pattern_color, NULL); 933 934 v4l2_ctrl_cluster(2, &mt9v032->test_pattern); 935 936 mt9v032->pixel_rate = 937 v4l2_ctrl_new_std(&mt9v032->ctrls, &mt9v032_ctrl_ops, 938 V4L2_CID_PIXEL_RATE, 1, INT_MAX, 1, 1); 939 940 if (pdata && pdata->link_freqs) { 941 unsigned int def = 0; 942 943 for (i = 0; pdata->link_freqs[i]; ++i) { 944 if (pdata->link_freqs[i] == pdata->link_def_freq) 945 def = i; 946 } 947 948 mt9v032->link_freq = 949 v4l2_ctrl_new_int_menu(&mt9v032->ctrls, 950 &mt9v032_ctrl_ops, 951 V4L2_CID_LINK_FREQ, i - 1, def, 952 pdata->link_freqs); 953 v4l2_ctrl_cluster(2, &mt9v032->link_freq); 954 } 955 956 957 mt9v032->subdev.ctrl_handler = &mt9v032->ctrls; 958 959 if (mt9v032->ctrls.error) 960 printk(KERN_INFO "%s: control initialization error %d\n", 961 __func__, mt9v032->ctrls.error); 962 963 mt9v032->crop.left = MT9V032_COLUMN_START_DEF; 964 mt9v032->crop.top = MT9V032_ROW_START_DEF; 965 mt9v032->crop.width = MT9V032_WINDOW_WIDTH_DEF; 966 mt9v032->crop.height = MT9V032_WINDOW_HEIGHT_DEF; 967 968 if (mt9v032->model->color) 969 mt9v032->format.code = MEDIA_BUS_FMT_SGRBG10_1X10; 970 else 971 mt9v032->format.code = MEDIA_BUS_FMT_Y10_1X10; 972 973 mt9v032->format.width = MT9V032_WINDOW_WIDTH_DEF; 974 mt9v032->format.height = MT9V032_WINDOW_HEIGHT_DEF; 975 mt9v032->format.field = V4L2_FIELD_NONE; 976 mt9v032->format.colorspace = V4L2_COLORSPACE_SRGB; 977 978 mt9v032->hratio = 1; 979 mt9v032->vratio = 1; 980 981 mt9v032->aec_agc = MT9V032_AEC_ENABLE | MT9V032_AGC_ENABLE; 982 mt9v032->hblank = MT9V032_HORIZONTAL_BLANKING_DEF; 983 mt9v032->sysclk = MT9V032_SYSCLK_FREQ_DEF; 984 985 v4l2_i2c_subdev_init(&mt9v032->subdev, client, &mt9v032_subdev_ops); 986 mt9v032->subdev.internal_ops = &mt9v032_subdev_internal_ops; 987 mt9v032->subdev.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; 988 989 mt9v032->pad.flags = MEDIA_PAD_FL_SOURCE; 990 ret = media_entity_init(&mt9v032->subdev.entity, 1, &mt9v032->pad, 0); 991 if (ret < 0) 992 goto err; 993 994 mt9v032->subdev.dev = &client->dev; 995 ret = v4l2_async_register_subdev(&mt9v032->subdev); 996 if (ret < 0) 997 goto err; 998 999 return 0; 1000 1001 err: 1002 media_entity_cleanup(&mt9v032->subdev.entity); 1003 v4l2_ctrl_handler_free(&mt9v032->ctrls); 1004 return ret; 1005 } 1006 1007 static int mt9v032_remove(struct i2c_client *client) 1008 { 1009 struct v4l2_subdev *subdev = i2c_get_clientdata(client); 1010 struct mt9v032 *mt9v032 = to_mt9v032(subdev); 1011 1012 v4l2_async_unregister_subdev(subdev); 1013 v4l2_ctrl_handler_free(&mt9v032->ctrls); 1014 v4l2_device_unregister_subdev(subdev); 1015 media_entity_cleanup(&subdev->entity); 1016 1017 return 0; 1018 } 1019 1020 static const struct i2c_device_id mt9v032_id[] = { 1021 { "mt9v022", (kernel_ulong_t)&mt9v032_models[MT9V032_MODEL_V022_COLOR] }, 1022 { "mt9v022m", (kernel_ulong_t)&mt9v032_models[MT9V032_MODEL_V022_MONO] }, 1023 { "mt9v024", (kernel_ulong_t)&mt9v032_models[MT9V032_MODEL_V024_COLOR] }, 1024 { "mt9v024m", (kernel_ulong_t)&mt9v032_models[MT9V032_MODEL_V024_MONO] }, 1025 { "mt9v032", (kernel_ulong_t)&mt9v032_models[MT9V032_MODEL_V032_COLOR] }, 1026 { "mt9v032m", (kernel_ulong_t)&mt9v032_models[MT9V032_MODEL_V032_MONO] }, 1027 { "mt9v034", (kernel_ulong_t)&mt9v032_models[MT9V032_MODEL_V034_COLOR] }, 1028 { "mt9v034m", (kernel_ulong_t)&mt9v032_models[MT9V032_MODEL_V034_MONO] }, 1029 { } 1030 }; 1031 MODULE_DEVICE_TABLE(i2c, mt9v032_id); 1032 1033 static struct i2c_driver mt9v032_driver = { 1034 .driver = { 1035 .name = "mt9v032", 1036 }, 1037 .probe = mt9v032_probe, 1038 .remove = mt9v032_remove, 1039 .id_table = mt9v032_id, 1040 }; 1041 1042 module_i2c_driver(mt9v032_driver); 1043 1044 MODULE_DESCRIPTION("Aptina MT9V032 Camera driver"); 1045 MODULE_AUTHOR("Laurent Pinchart <laurent.pinchart@ideasonboard.com>"); 1046 MODULE_LICENSE("GPL"); 1047