1 /* 2 * Driver for MT9V022, MT9V024, MT9V032, and MT9V034 CMOS Image Sensors 3 * 4 * Copyright (C) 2010, Laurent Pinchart <laurent.pinchart@ideasonboard.com> 5 * 6 * Based on the MT9M001 driver, 7 * 8 * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de> 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License version 2 as 12 * published by the Free Software Foundation. 13 */ 14 15 #include <linux/clk.h> 16 #include <linux/delay.h> 17 #include <linux/gpio/consumer.h> 18 #include <linux/i2c.h> 19 #include <linux/log2.h> 20 #include <linux/mutex.h> 21 #include <linux/of.h> 22 #include <linux/regmap.h> 23 #include <linux/slab.h> 24 #include <linux/videodev2.h> 25 #include <linux/v4l2-mediabus.h> 26 #include <linux/module.h> 27 28 #include <media/i2c/mt9v032.h> 29 #include <media/v4l2-ctrls.h> 30 #include <media/v4l2-device.h> 31 #include <media/v4l2-of.h> 32 #include <media/v4l2-subdev.h> 33 34 /* The first four rows are black rows. The active area spans 753x481 pixels. */ 35 #define MT9V032_PIXEL_ARRAY_HEIGHT 485 36 #define MT9V032_PIXEL_ARRAY_WIDTH 753 37 38 #define MT9V032_SYSCLK_FREQ_DEF 26600000 39 40 #define MT9V032_CHIP_VERSION 0x00 41 #define MT9V032_CHIP_ID_REV1 0x1311 42 #define MT9V032_CHIP_ID_REV3 0x1313 43 #define MT9V034_CHIP_ID_REV1 0X1324 44 #define MT9V032_COLUMN_START 0x01 45 #define MT9V032_COLUMN_START_MIN 1 46 #define MT9V032_COLUMN_START_DEF 1 47 #define MT9V032_COLUMN_START_MAX 752 48 #define MT9V032_ROW_START 0x02 49 #define MT9V032_ROW_START_MIN 4 50 #define MT9V032_ROW_START_DEF 5 51 #define MT9V032_ROW_START_MAX 482 52 #define MT9V032_WINDOW_HEIGHT 0x03 53 #define MT9V032_WINDOW_HEIGHT_MIN 1 54 #define MT9V032_WINDOW_HEIGHT_DEF 480 55 #define MT9V032_WINDOW_HEIGHT_MAX 480 56 #define MT9V032_WINDOW_WIDTH 0x04 57 #define MT9V032_WINDOW_WIDTH_MIN 1 58 #define MT9V032_WINDOW_WIDTH_DEF 752 59 #define MT9V032_WINDOW_WIDTH_MAX 752 60 #define MT9V032_HORIZONTAL_BLANKING 0x05 61 #define MT9V032_HORIZONTAL_BLANKING_MIN 43 62 #define MT9V034_HORIZONTAL_BLANKING_MIN 61 63 #define MT9V032_HORIZONTAL_BLANKING_DEF 94 64 #define MT9V032_HORIZONTAL_BLANKING_MAX 1023 65 #define MT9V032_VERTICAL_BLANKING 0x06 66 #define MT9V032_VERTICAL_BLANKING_MIN 4 67 #define MT9V034_VERTICAL_BLANKING_MIN 2 68 #define MT9V032_VERTICAL_BLANKING_DEF 45 69 #define MT9V032_VERTICAL_BLANKING_MAX 3000 70 #define MT9V034_VERTICAL_BLANKING_MAX 32288 71 #define MT9V032_CHIP_CONTROL 0x07 72 #define MT9V032_CHIP_CONTROL_MASTER_MODE (1 << 3) 73 #define MT9V032_CHIP_CONTROL_DOUT_ENABLE (1 << 7) 74 #define MT9V032_CHIP_CONTROL_SEQUENTIAL (1 << 8) 75 #define MT9V032_SHUTTER_WIDTH1 0x08 76 #define MT9V032_SHUTTER_WIDTH2 0x09 77 #define MT9V032_SHUTTER_WIDTH_CONTROL 0x0a 78 #define MT9V032_TOTAL_SHUTTER_WIDTH 0x0b 79 #define MT9V032_TOTAL_SHUTTER_WIDTH_MIN 1 80 #define MT9V034_TOTAL_SHUTTER_WIDTH_MIN 0 81 #define MT9V032_TOTAL_SHUTTER_WIDTH_DEF 480 82 #define MT9V032_TOTAL_SHUTTER_WIDTH_MAX 32767 83 #define MT9V034_TOTAL_SHUTTER_WIDTH_MAX 32765 84 #define MT9V032_RESET 0x0c 85 #define MT9V032_READ_MODE 0x0d 86 #define MT9V032_READ_MODE_ROW_BIN_MASK (3 << 0) 87 #define MT9V032_READ_MODE_ROW_BIN_SHIFT 0 88 #define MT9V032_READ_MODE_COLUMN_BIN_MASK (3 << 2) 89 #define MT9V032_READ_MODE_COLUMN_BIN_SHIFT 2 90 #define MT9V032_READ_MODE_ROW_FLIP (1 << 4) 91 #define MT9V032_READ_MODE_COLUMN_FLIP (1 << 5) 92 #define MT9V032_READ_MODE_DARK_COLUMNS (1 << 6) 93 #define MT9V032_READ_MODE_DARK_ROWS (1 << 7) 94 #define MT9V032_READ_MODE_RESERVED 0x0300 95 #define MT9V032_PIXEL_OPERATION_MODE 0x0f 96 #define MT9V034_PIXEL_OPERATION_MODE_HDR (1 << 0) 97 #define MT9V034_PIXEL_OPERATION_MODE_COLOR (1 << 1) 98 #define MT9V032_PIXEL_OPERATION_MODE_COLOR (1 << 2) 99 #define MT9V032_PIXEL_OPERATION_MODE_HDR (1 << 6) 100 #define MT9V032_ANALOG_GAIN 0x35 101 #define MT9V032_ANALOG_GAIN_MIN 16 102 #define MT9V032_ANALOG_GAIN_DEF 16 103 #define MT9V032_ANALOG_GAIN_MAX 64 104 #define MT9V032_MAX_ANALOG_GAIN 0x36 105 #define MT9V032_MAX_ANALOG_GAIN_MAX 127 106 #define MT9V032_FRAME_DARK_AVERAGE 0x42 107 #define MT9V032_DARK_AVG_THRESH 0x46 108 #define MT9V032_DARK_AVG_LOW_THRESH_MASK (255 << 0) 109 #define MT9V032_DARK_AVG_LOW_THRESH_SHIFT 0 110 #define MT9V032_DARK_AVG_HIGH_THRESH_MASK (255 << 8) 111 #define MT9V032_DARK_AVG_HIGH_THRESH_SHIFT 8 112 #define MT9V032_ROW_NOISE_CORR_CONTROL 0x70 113 #define MT9V034_ROW_NOISE_CORR_ENABLE (1 << 0) 114 #define MT9V034_ROW_NOISE_CORR_USE_BLK_AVG (1 << 1) 115 #define MT9V032_ROW_NOISE_CORR_ENABLE (1 << 5) 116 #define MT9V032_ROW_NOISE_CORR_USE_BLK_AVG (1 << 7) 117 #define MT9V032_PIXEL_CLOCK 0x74 118 #define MT9V034_PIXEL_CLOCK 0x72 119 #define MT9V032_PIXEL_CLOCK_INV_LINE (1 << 0) 120 #define MT9V032_PIXEL_CLOCK_INV_FRAME (1 << 1) 121 #define MT9V032_PIXEL_CLOCK_XOR_LINE (1 << 2) 122 #define MT9V032_PIXEL_CLOCK_CONT_LINE (1 << 3) 123 #define MT9V032_PIXEL_CLOCK_INV_PXL_CLK (1 << 4) 124 #define MT9V032_TEST_PATTERN 0x7f 125 #define MT9V032_TEST_PATTERN_DATA_MASK (1023 << 0) 126 #define MT9V032_TEST_PATTERN_DATA_SHIFT 0 127 #define MT9V032_TEST_PATTERN_USE_DATA (1 << 10) 128 #define MT9V032_TEST_PATTERN_GRAY_MASK (3 << 11) 129 #define MT9V032_TEST_PATTERN_GRAY_NONE (0 << 11) 130 #define MT9V032_TEST_PATTERN_GRAY_VERTICAL (1 << 11) 131 #define MT9V032_TEST_PATTERN_GRAY_HORIZONTAL (2 << 11) 132 #define MT9V032_TEST_PATTERN_GRAY_DIAGONAL (3 << 11) 133 #define MT9V032_TEST_PATTERN_ENABLE (1 << 13) 134 #define MT9V032_TEST_PATTERN_FLIP (1 << 14) 135 #define MT9V032_AEGC_DESIRED_BIN 0xa5 136 #define MT9V032_AEC_UPDATE_FREQUENCY 0xa6 137 #define MT9V032_AEC_LPF 0xa8 138 #define MT9V032_AGC_UPDATE_FREQUENCY 0xa9 139 #define MT9V032_AGC_LPF 0xaa 140 #define MT9V032_AEC_AGC_ENABLE 0xaf 141 #define MT9V032_AEC_ENABLE (1 << 0) 142 #define MT9V032_AGC_ENABLE (1 << 1) 143 #define MT9V034_AEC_MAX_SHUTTER_WIDTH 0xad 144 #define MT9V032_AEC_MAX_SHUTTER_WIDTH 0xbd 145 #define MT9V032_THERMAL_INFO 0xc1 146 147 enum mt9v032_model { 148 MT9V032_MODEL_V022_COLOR, /* MT9V022IX7ATC */ 149 MT9V032_MODEL_V022_MONO, /* MT9V022IX7ATM */ 150 MT9V032_MODEL_V024_COLOR, /* MT9V024IA7XTC */ 151 MT9V032_MODEL_V024_MONO, /* MT9V024IA7XTM */ 152 MT9V032_MODEL_V032_COLOR, /* MT9V032C12STM */ 153 MT9V032_MODEL_V032_MONO, /* MT9V032C12STC */ 154 MT9V032_MODEL_V034_COLOR, 155 MT9V032_MODEL_V034_MONO, 156 }; 157 158 struct mt9v032_model_version { 159 unsigned int version; 160 const char *name; 161 }; 162 163 struct mt9v032_model_data { 164 unsigned int min_row_time; 165 unsigned int min_hblank; 166 unsigned int min_vblank; 167 unsigned int max_vblank; 168 unsigned int min_shutter; 169 unsigned int max_shutter; 170 unsigned int pclk_reg; 171 unsigned int aec_max_shutter_reg; 172 const struct v4l2_ctrl_config * const aec_max_shutter_v4l2_ctrl; 173 }; 174 175 struct mt9v032_model_info { 176 const struct mt9v032_model_data *data; 177 bool color; 178 }; 179 180 static const struct mt9v032_model_version mt9v032_versions[] = { 181 { MT9V032_CHIP_ID_REV1, "MT9V022/MT9V032 rev1/2" }, 182 { MT9V032_CHIP_ID_REV3, "MT9V022/MT9V032 rev3" }, 183 { MT9V034_CHIP_ID_REV1, "MT9V024/MT9V034 rev1" }, 184 }; 185 186 struct mt9v032 { 187 struct v4l2_subdev subdev; 188 struct media_pad pad; 189 190 struct v4l2_mbus_framefmt format; 191 struct v4l2_rect crop; 192 unsigned int hratio; 193 unsigned int vratio; 194 195 struct v4l2_ctrl_handler ctrls; 196 struct { 197 struct v4l2_ctrl *link_freq; 198 struct v4l2_ctrl *pixel_rate; 199 }; 200 201 struct mutex power_lock; 202 int power_count; 203 204 struct regmap *regmap; 205 struct clk *clk; 206 struct gpio_desc *reset_gpio; 207 struct gpio_desc *standby_gpio; 208 209 struct mt9v032_platform_data *pdata; 210 const struct mt9v032_model_info *model; 211 const struct mt9v032_model_version *version; 212 213 u32 sysclk; 214 u16 aec_agc; 215 u16 hblank; 216 struct { 217 struct v4l2_ctrl *test_pattern; 218 struct v4l2_ctrl *test_pattern_color; 219 }; 220 }; 221 222 static struct mt9v032 *to_mt9v032(struct v4l2_subdev *sd) 223 { 224 return container_of(sd, struct mt9v032, subdev); 225 } 226 227 static int 228 mt9v032_update_aec_agc(struct mt9v032 *mt9v032, u16 which, int enable) 229 { 230 struct regmap *map = mt9v032->regmap; 231 u16 value = mt9v032->aec_agc; 232 int ret; 233 234 if (enable) 235 value |= which; 236 else 237 value &= ~which; 238 239 ret = regmap_write(map, MT9V032_AEC_AGC_ENABLE, value); 240 if (ret < 0) 241 return ret; 242 243 mt9v032->aec_agc = value; 244 return 0; 245 } 246 247 static int 248 mt9v032_update_hblank(struct mt9v032 *mt9v032) 249 { 250 struct v4l2_rect *crop = &mt9v032->crop; 251 unsigned int min_hblank = mt9v032->model->data->min_hblank; 252 unsigned int hblank; 253 254 if (mt9v032->version->version == MT9V034_CHIP_ID_REV1) 255 min_hblank += (mt9v032->hratio - 1) * 10; 256 min_hblank = max_t(int, mt9v032->model->data->min_row_time - crop->width, 257 min_hblank); 258 hblank = max_t(unsigned int, mt9v032->hblank, min_hblank); 259 260 return regmap_write(mt9v032->regmap, MT9V032_HORIZONTAL_BLANKING, 261 hblank); 262 } 263 264 static int mt9v032_power_on(struct mt9v032 *mt9v032) 265 { 266 struct regmap *map = mt9v032->regmap; 267 int ret; 268 269 gpiod_set_value_cansleep(mt9v032->reset_gpio, 1); 270 271 ret = clk_set_rate(mt9v032->clk, mt9v032->sysclk); 272 if (ret < 0) 273 return ret; 274 275 /* System clock has to be enabled before releasing the reset */ 276 ret = clk_prepare_enable(mt9v032->clk); 277 if (ret) 278 return ret; 279 280 udelay(1); 281 282 if (mt9v032->reset_gpio) { 283 gpiod_set_value_cansleep(mt9v032->reset_gpio, 0); 284 285 /* After releasing reset we need to wait 10 clock cycles 286 * before accessing the sensor over I2C. As the minimum SYSCLK 287 * frequency is 13MHz, waiting 1µs will be enough in the worst 288 * case. 289 */ 290 udelay(1); 291 } 292 293 /* Reset the chip and stop data read out */ 294 ret = regmap_write(map, MT9V032_RESET, 1); 295 if (ret < 0) 296 return ret; 297 298 ret = regmap_write(map, MT9V032_RESET, 0); 299 if (ret < 0) 300 return ret; 301 302 return regmap_write(map, MT9V032_CHIP_CONTROL, 303 MT9V032_CHIP_CONTROL_MASTER_MODE); 304 } 305 306 static void mt9v032_power_off(struct mt9v032 *mt9v032) 307 { 308 clk_disable_unprepare(mt9v032->clk); 309 } 310 311 static int __mt9v032_set_power(struct mt9v032 *mt9v032, bool on) 312 { 313 struct regmap *map = mt9v032->regmap; 314 int ret; 315 316 if (!on) { 317 mt9v032_power_off(mt9v032); 318 return 0; 319 } 320 321 ret = mt9v032_power_on(mt9v032); 322 if (ret < 0) 323 return ret; 324 325 /* Configure the pixel clock polarity */ 326 if (mt9v032->pdata && mt9v032->pdata->clk_pol) { 327 ret = regmap_write(map, mt9v032->model->data->pclk_reg, 328 MT9V032_PIXEL_CLOCK_INV_PXL_CLK); 329 if (ret < 0) 330 return ret; 331 } 332 333 /* Disable the noise correction algorithm and restore the controls. */ 334 ret = regmap_write(map, MT9V032_ROW_NOISE_CORR_CONTROL, 0); 335 if (ret < 0) 336 return ret; 337 338 return v4l2_ctrl_handler_setup(&mt9v032->ctrls); 339 } 340 341 /* ----------------------------------------------------------------------------- 342 * V4L2 subdev video operations 343 */ 344 345 static struct v4l2_mbus_framefmt * 346 __mt9v032_get_pad_format(struct mt9v032 *mt9v032, struct v4l2_subdev_pad_config *cfg, 347 unsigned int pad, enum v4l2_subdev_format_whence which) 348 { 349 switch (which) { 350 case V4L2_SUBDEV_FORMAT_TRY: 351 return v4l2_subdev_get_try_format(&mt9v032->subdev, cfg, pad); 352 case V4L2_SUBDEV_FORMAT_ACTIVE: 353 return &mt9v032->format; 354 default: 355 return NULL; 356 } 357 } 358 359 static struct v4l2_rect * 360 __mt9v032_get_pad_crop(struct mt9v032 *mt9v032, struct v4l2_subdev_pad_config *cfg, 361 unsigned int pad, enum v4l2_subdev_format_whence which) 362 { 363 switch (which) { 364 case V4L2_SUBDEV_FORMAT_TRY: 365 return v4l2_subdev_get_try_crop(&mt9v032->subdev, cfg, pad); 366 case V4L2_SUBDEV_FORMAT_ACTIVE: 367 return &mt9v032->crop; 368 default: 369 return NULL; 370 } 371 } 372 373 static int mt9v032_s_stream(struct v4l2_subdev *subdev, int enable) 374 { 375 const u16 mode = MT9V032_CHIP_CONTROL_DOUT_ENABLE 376 | MT9V032_CHIP_CONTROL_SEQUENTIAL; 377 struct mt9v032 *mt9v032 = to_mt9v032(subdev); 378 struct v4l2_rect *crop = &mt9v032->crop; 379 struct regmap *map = mt9v032->regmap; 380 unsigned int hbin; 381 unsigned int vbin; 382 int ret; 383 384 if (!enable) 385 return regmap_update_bits(map, MT9V032_CHIP_CONTROL, mode, 0); 386 387 /* Configure the window size and row/column bin */ 388 hbin = fls(mt9v032->hratio) - 1; 389 vbin = fls(mt9v032->vratio) - 1; 390 ret = regmap_update_bits(map, MT9V032_READ_MODE, 391 ~MT9V032_READ_MODE_RESERVED, 392 hbin << MT9V032_READ_MODE_COLUMN_BIN_SHIFT | 393 vbin << MT9V032_READ_MODE_ROW_BIN_SHIFT); 394 if (ret < 0) 395 return ret; 396 397 ret = regmap_write(map, MT9V032_COLUMN_START, crop->left); 398 if (ret < 0) 399 return ret; 400 401 ret = regmap_write(map, MT9V032_ROW_START, crop->top); 402 if (ret < 0) 403 return ret; 404 405 ret = regmap_write(map, MT9V032_WINDOW_WIDTH, crop->width); 406 if (ret < 0) 407 return ret; 408 409 ret = regmap_write(map, MT9V032_WINDOW_HEIGHT, crop->height); 410 if (ret < 0) 411 return ret; 412 413 ret = mt9v032_update_hblank(mt9v032); 414 if (ret < 0) 415 return ret; 416 417 /* Switch to master "normal" mode */ 418 return regmap_update_bits(map, MT9V032_CHIP_CONTROL, mode, mode); 419 } 420 421 static int mt9v032_enum_mbus_code(struct v4l2_subdev *subdev, 422 struct v4l2_subdev_pad_config *cfg, 423 struct v4l2_subdev_mbus_code_enum *code) 424 { 425 if (code->index > 0) 426 return -EINVAL; 427 428 code->code = MEDIA_BUS_FMT_SGRBG10_1X10; 429 return 0; 430 } 431 432 static int mt9v032_enum_frame_size(struct v4l2_subdev *subdev, 433 struct v4l2_subdev_pad_config *cfg, 434 struct v4l2_subdev_frame_size_enum *fse) 435 { 436 if (fse->index >= 3 || fse->code != MEDIA_BUS_FMT_SGRBG10_1X10) 437 return -EINVAL; 438 439 fse->min_width = MT9V032_WINDOW_WIDTH_DEF / (1 << fse->index); 440 fse->max_width = fse->min_width; 441 fse->min_height = MT9V032_WINDOW_HEIGHT_DEF / (1 << fse->index); 442 fse->max_height = fse->min_height; 443 444 return 0; 445 } 446 447 static int mt9v032_get_format(struct v4l2_subdev *subdev, 448 struct v4l2_subdev_pad_config *cfg, 449 struct v4l2_subdev_format *format) 450 { 451 struct mt9v032 *mt9v032 = to_mt9v032(subdev); 452 453 format->format = *__mt9v032_get_pad_format(mt9v032, cfg, format->pad, 454 format->which); 455 return 0; 456 } 457 458 static void mt9v032_configure_pixel_rate(struct mt9v032 *mt9v032) 459 { 460 struct i2c_client *client = v4l2_get_subdevdata(&mt9v032->subdev); 461 int ret; 462 463 ret = v4l2_ctrl_s_ctrl_int64(mt9v032->pixel_rate, 464 mt9v032->sysclk / mt9v032->hratio); 465 if (ret < 0) 466 dev_warn(&client->dev, "failed to set pixel rate (%d)\n", ret); 467 } 468 469 static unsigned int mt9v032_calc_ratio(unsigned int input, unsigned int output) 470 { 471 /* Compute the power-of-two binning factor closest to the input size to 472 * output size ratio. Given that the output size is bounded by input/4 473 * and input, a generic implementation would be an ineffective luxury. 474 */ 475 if (output * 3 > input * 2) 476 return 1; 477 if (output * 3 > input) 478 return 2; 479 return 4; 480 } 481 482 static int mt9v032_set_format(struct v4l2_subdev *subdev, 483 struct v4l2_subdev_pad_config *cfg, 484 struct v4l2_subdev_format *format) 485 { 486 struct mt9v032 *mt9v032 = to_mt9v032(subdev); 487 struct v4l2_mbus_framefmt *__format; 488 struct v4l2_rect *__crop; 489 unsigned int width; 490 unsigned int height; 491 unsigned int hratio; 492 unsigned int vratio; 493 494 __crop = __mt9v032_get_pad_crop(mt9v032, cfg, format->pad, 495 format->which); 496 497 /* Clamp the width and height to avoid dividing by zero. */ 498 width = clamp(ALIGN(format->format.width, 2), 499 max_t(unsigned int, __crop->width / 4, 500 MT9V032_WINDOW_WIDTH_MIN), 501 __crop->width); 502 height = clamp(ALIGN(format->format.height, 2), 503 max_t(unsigned int, __crop->height / 4, 504 MT9V032_WINDOW_HEIGHT_MIN), 505 __crop->height); 506 507 hratio = mt9v032_calc_ratio(__crop->width, width); 508 vratio = mt9v032_calc_ratio(__crop->height, height); 509 510 __format = __mt9v032_get_pad_format(mt9v032, cfg, format->pad, 511 format->which); 512 __format->width = __crop->width / hratio; 513 __format->height = __crop->height / vratio; 514 515 if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE) { 516 mt9v032->hratio = hratio; 517 mt9v032->vratio = vratio; 518 mt9v032_configure_pixel_rate(mt9v032); 519 } 520 521 format->format = *__format; 522 523 return 0; 524 } 525 526 static int mt9v032_get_selection(struct v4l2_subdev *subdev, 527 struct v4l2_subdev_pad_config *cfg, 528 struct v4l2_subdev_selection *sel) 529 { 530 struct mt9v032 *mt9v032 = to_mt9v032(subdev); 531 532 if (sel->target != V4L2_SEL_TGT_CROP) 533 return -EINVAL; 534 535 sel->r = *__mt9v032_get_pad_crop(mt9v032, cfg, sel->pad, sel->which); 536 return 0; 537 } 538 539 static int mt9v032_set_selection(struct v4l2_subdev *subdev, 540 struct v4l2_subdev_pad_config *cfg, 541 struct v4l2_subdev_selection *sel) 542 { 543 struct mt9v032 *mt9v032 = to_mt9v032(subdev); 544 struct v4l2_mbus_framefmt *__format; 545 struct v4l2_rect *__crop; 546 struct v4l2_rect rect; 547 548 if (sel->target != V4L2_SEL_TGT_CROP) 549 return -EINVAL; 550 551 /* Clamp the crop rectangle boundaries and align them to a non multiple 552 * of 2 pixels to ensure a GRBG Bayer pattern. 553 */ 554 rect.left = clamp(ALIGN(sel->r.left + 1, 2) - 1, 555 MT9V032_COLUMN_START_MIN, 556 MT9V032_COLUMN_START_MAX); 557 rect.top = clamp(ALIGN(sel->r.top + 1, 2) - 1, 558 MT9V032_ROW_START_MIN, 559 MT9V032_ROW_START_MAX); 560 rect.width = clamp_t(unsigned int, ALIGN(sel->r.width, 2), 561 MT9V032_WINDOW_WIDTH_MIN, 562 MT9V032_WINDOW_WIDTH_MAX); 563 rect.height = clamp_t(unsigned int, ALIGN(sel->r.height, 2), 564 MT9V032_WINDOW_HEIGHT_MIN, 565 MT9V032_WINDOW_HEIGHT_MAX); 566 567 rect.width = min_t(unsigned int, 568 rect.width, MT9V032_PIXEL_ARRAY_WIDTH - rect.left); 569 rect.height = min_t(unsigned int, 570 rect.height, MT9V032_PIXEL_ARRAY_HEIGHT - rect.top); 571 572 __crop = __mt9v032_get_pad_crop(mt9v032, cfg, sel->pad, sel->which); 573 574 if (rect.width != __crop->width || rect.height != __crop->height) { 575 /* Reset the output image size if the crop rectangle size has 576 * been modified. 577 */ 578 __format = __mt9v032_get_pad_format(mt9v032, cfg, sel->pad, 579 sel->which); 580 __format->width = rect.width; 581 __format->height = rect.height; 582 if (sel->which == V4L2_SUBDEV_FORMAT_ACTIVE) { 583 mt9v032->hratio = 1; 584 mt9v032->vratio = 1; 585 mt9v032_configure_pixel_rate(mt9v032); 586 } 587 } 588 589 *__crop = rect; 590 sel->r = rect; 591 592 return 0; 593 } 594 595 /* ----------------------------------------------------------------------------- 596 * V4L2 subdev control operations 597 */ 598 599 #define V4L2_CID_TEST_PATTERN_COLOR (V4L2_CID_USER_BASE | 0x1001) 600 /* 601 * Value between 1 and 64 to set the desired bin. This is effectively a measure 602 * of how bright the image is supposed to be. Both AGC and AEC try to reach 603 * this. 604 */ 605 #define V4L2_CID_AEGC_DESIRED_BIN (V4L2_CID_USER_BASE | 0x1002) 606 /* 607 * LPF is the low pass filter capability of the chip. Both AEC and AGC have 608 * this setting. This limits the speed in which AGC/AEC adjust their settings. 609 * Possible values are 0-2. 0 means no LPF. For 1 and 2 this equation is used: 610 * 611 * if |(calculated new exp - current exp)| > (current exp / 4) 612 * next exp = calculated new exp 613 * else 614 * next exp = current exp + ((calculated new exp - current exp) / 2^LPF) 615 */ 616 #define V4L2_CID_AEC_LPF (V4L2_CID_USER_BASE | 0x1003) 617 #define V4L2_CID_AGC_LPF (V4L2_CID_USER_BASE | 0x1004) 618 /* 619 * Value between 0 and 15. This is the number of frames being skipped before 620 * updating the auto exposure/gain. 621 */ 622 #define V4L2_CID_AEC_UPDATE_INTERVAL (V4L2_CID_USER_BASE | 0x1005) 623 #define V4L2_CID_AGC_UPDATE_INTERVAL (V4L2_CID_USER_BASE | 0x1006) 624 /* 625 * Maximum shutter width used for AEC. 626 */ 627 #define V4L2_CID_AEC_MAX_SHUTTER_WIDTH (V4L2_CID_USER_BASE | 0x1007) 628 629 static int mt9v032_s_ctrl(struct v4l2_ctrl *ctrl) 630 { 631 struct mt9v032 *mt9v032 = 632 container_of(ctrl->handler, struct mt9v032, ctrls); 633 struct regmap *map = mt9v032->regmap; 634 u32 freq; 635 u16 data; 636 637 switch (ctrl->id) { 638 case V4L2_CID_AUTOGAIN: 639 return mt9v032_update_aec_agc(mt9v032, MT9V032_AGC_ENABLE, 640 ctrl->val); 641 642 case V4L2_CID_GAIN: 643 return regmap_write(map, MT9V032_ANALOG_GAIN, ctrl->val); 644 645 case V4L2_CID_EXPOSURE_AUTO: 646 return mt9v032_update_aec_agc(mt9v032, MT9V032_AEC_ENABLE, 647 !ctrl->val); 648 649 case V4L2_CID_EXPOSURE: 650 return regmap_write(map, MT9V032_TOTAL_SHUTTER_WIDTH, 651 ctrl->val); 652 653 case V4L2_CID_HBLANK: 654 mt9v032->hblank = ctrl->val; 655 return mt9v032_update_hblank(mt9v032); 656 657 case V4L2_CID_VBLANK: 658 return regmap_write(map, MT9V032_VERTICAL_BLANKING, 659 ctrl->val); 660 661 case V4L2_CID_PIXEL_RATE: 662 case V4L2_CID_LINK_FREQ: 663 if (mt9v032->link_freq == NULL) 664 break; 665 666 freq = mt9v032->pdata->link_freqs[mt9v032->link_freq->val]; 667 *mt9v032->pixel_rate->p_new.p_s64 = freq; 668 mt9v032->sysclk = freq; 669 break; 670 671 case V4L2_CID_TEST_PATTERN: 672 switch (mt9v032->test_pattern->val) { 673 case 0: 674 data = 0; 675 break; 676 case 1: 677 data = MT9V032_TEST_PATTERN_GRAY_VERTICAL 678 | MT9V032_TEST_PATTERN_ENABLE; 679 break; 680 case 2: 681 data = MT9V032_TEST_PATTERN_GRAY_HORIZONTAL 682 | MT9V032_TEST_PATTERN_ENABLE; 683 break; 684 case 3: 685 data = MT9V032_TEST_PATTERN_GRAY_DIAGONAL 686 | MT9V032_TEST_PATTERN_ENABLE; 687 break; 688 default: 689 data = (mt9v032->test_pattern_color->val << 690 MT9V032_TEST_PATTERN_DATA_SHIFT) 691 | MT9V032_TEST_PATTERN_USE_DATA 692 | MT9V032_TEST_PATTERN_ENABLE 693 | MT9V032_TEST_PATTERN_FLIP; 694 break; 695 } 696 return regmap_write(map, MT9V032_TEST_PATTERN, data); 697 698 case V4L2_CID_AEGC_DESIRED_BIN: 699 return regmap_write(map, MT9V032_AEGC_DESIRED_BIN, ctrl->val); 700 701 case V4L2_CID_AEC_LPF: 702 return regmap_write(map, MT9V032_AEC_LPF, ctrl->val); 703 704 case V4L2_CID_AGC_LPF: 705 return regmap_write(map, MT9V032_AGC_LPF, ctrl->val); 706 707 case V4L2_CID_AEC_UPDATE_INTERVAL: 708 return regmap_write(map, MT9V032_AEC_UPDATE_FREQUENCY, 709 ctrl->val); 710 711 case V4L2_CID_AGC_UPDATE_INTERVAL: 712 return regmap_write(map, MT9V032_AGC_UPDATE_FREQUENCY, 713 ctrl->val); 714 715 case V4L2_CID_AEC_MAX_SHUTTER_WIDTH: 716 return regmap_write(map, 717 mt9v032->model->data->aec_max_shutter_reg, 718 ctrl->val); 719 } 720 721 return 0; 722 } 723 724 static const struct v4l2_ctrl_ops mt9v032_ctrl_ops = { 725 .s_ctrl = mt9v032_s_ctrl, 726 }; 727 728 static const char * const mt9v032_test_pattern_menu[] = { 729 "Disabled", 730 "Gray Vertical Shade", 731 "Gray Horizontal Shade", 732 "Gray Diagonal Shade", 733 "Plain", 734 }; 735 736 static const struct v4l2_ctrl_config mt9v032_test_pattern_color = { 737 .ops = &mt9v032_ctrl_ops, 738 .id = V4L2_CID_TEST_PATTERN_COLOR, 739 .type = V4L2_CTRL_TYPE_INTEGER, 740 .name = "Test Pattern Color", 741 .min = 0, 742 .max = 1023, 743 .step = 1, 744 .def = 0, 745 .flags = 0, 746 }; 747 748 static const struct v4l2_ctrl_config mt9v032_aegc_controls[] = { 749 { 750 .ops = &mt9v032_ctrl_ops, 751 .id = V4L2_CID_AEGC_DESIRED_BIN, 752 .type = V4L2_CTRL_TYPE_INTEGER, 753 .name = "AEC/AGC Desired Bin", 754 .min = 1, 755 .max = 64, 756 .step = 1, 757 .def = 58, 758 .flags = 0, 759 }, { 760 .ops = &mt9v032_ctrl_ops, 761 .id = V4L2_CID_AEC_LPF, 762 .type = V4L2_CTRL_TYPE_INTEGER, 763 .name = "AEC Low Pass Filter", 764 .min = 0, 765 .max = 2, 766 .step = 1, 767 .def = 0, 768 .flags = 0, 769 }, { 770 .ops = &mt9v032_ctrl_ops, 771 .id = V4L2_CID_AGC_LPF, 772 .type = V4L2_CTRL_TYPE_INTEGER, 773 .name = "AGC Low Pass Filter", 774 .min = 0, 775 .max = 2, 776 .step = 1, 777 .def = 2, 778 .flags = 0, 779 }, { 780 .ops = &mt9v032_ctrl_ops, 781 .id = V4L2_CID_AEC_UPDATE_INTERVAL, 782 .type = V4L2_CTRL_TYPE_INTEGER, 783 .name = "AEC Update Interval", 784 .min = 0, 785 .max = 16, 786 .step = 1, 787 .def = 2, 788 .flags = 0, 789 }, { 790 .ops = &mt9v032_ctrl_ops, 791 .id = V4L2_CID_AGC_UPDATE_INTERVAL, 792 .type = V4L2_CTRL_TYPE_INTEGER, 793 .name = "AGC Update Interval", 794 .min = 0, 795 .max = 16, 796 .step = 1, 797 .def = 2, 798 .flags = 0, 799 } 800 }; 801 802 static const struct v4l2_ctrl_config mt9v032_aec_max_shutter_width = { 803 .ops = &mt9v032_ctrl_ops, 804 .id = V4L2_CID_AEC_MAX_SHUTTER_WIDTH, 805 .type = V4L2_CTRL_TYPE_INTEGER, 806 .name = "AEC Max Shutter Width", 807 .min = 1, 808 .max = 2047, 809 .step = 1, 810 .def = 480, 811 .flags = 0, 812 }; 813 814 static const struct v4l2_ctrl_config mt9v034_aec_max_shutter_width = { 815 .ops = &mt9v032_ctrl_ops, 816 .id = V4L2_CID_AEC_MAX_SHUTTER_WIDTH, 817 .type = V4L2_CTRL_TYPE_INTEGER, 818 .name = "AEC Max Shutter Width", 819 .min = 1, 820 .max = 32765, 821 .step = 1, 822 .def = 480, 823 .flags = 0, 824 }; 825 826 /* ----------------------------------------------------------------------------- 827 * V4L2 subdev core operations 828 */ 829 830 static int mt9v032_set_power(struct v4l2_subdev *subdev, int on) 831 { 832 struct mt9v032 *mt9v032 = to_mt9v032(subdev); 833 int ret = 0; 834 835 mutex_lock(&mt9v032->power_lock); 836 837 /* If the power count is modified from 0 to != 0 or from != 0 to 0, 838 * update the power state. 839 */ 840 if (mt9v032->power_count == !on) { 841 ret = __mt9v032_set_power(mt9v032, !!on); 842 if (ret < 0) 843 goto done; 844 } 845 846 /* Update the power count. */ 847 mt9v032->power_count += on ? 1 : -1; 848 WARN_ON(mt9v032->power_count < 0); 849 850 done: 851 mutex_unlock(&mt9v032->power_lock); 852 return ret; 853 } 854 855 /* ----------------------------------------------------------------------------- 856 * V4L2 subdev internal operations 857 */ 858 859 static int mt9v032_registered(struct v4l2_subdev *subdev) 860 { 861 struct i2c_client *client = v4l2_get_subdevdata(subdev); 862 struct mt9v032 *mt9v032 = to_mt9v032(subdev); 863 unsigned int i; 864 u32 version; 865 int ret; 866 867 dev_info(&client->dev, "Probing MT9V032 at address 0x%02x\n", 868 client->addr); 869 870 ret = mt9v032_power_on(mt9v032); 871 if (ret < 0) { 872 dev_err(&client->dev, "MT9V032 power up failed\n"); 873 return ret; 874 } 875 876 /* Read and check the sensor version */ 877 ret = regmap_read(mt9v032->regmap, MT9V032_CHIP_VERSION, &version); 878 if (ret < 0) { 879 dev_err(&client->dev, "Failed reading chip version\n"); 880 return ret; 881 } 882 883 for (i = 0; i < ARRAY_SIZE(mt9v032_versions); ++i) { 884 if (mt9v032_versions[i].version == version) { 885 mt9v032->version = &mt9v032_versions[i]; 886 break; 887 } 888 } 889 890 if (mt9v032->version == NULL) { 891 dev_err(&client->dev, "Unsupported chip version 0x%04x\n", 892 version); 893 return -ENODEV; 894 } 895 896 mt9v032_power_off(mt9v032); 897 898 dev_info(&client->dev, "%s detected at address 0x%02x\n", 899 mt9v032->version->name, client->addr); 900 901 mt9v032_configure_pixel_rate(mt9v032); 902 903 return ret; 904 } 905 906 static int mt9v032_open(struct v4l2_subdev *subdev, struct v4l2_subdev_fh *fh) 907 { 908 struct mt9v032 *mt9v032 = to_mt9v032(subdev); 909 struct v4l2_mbus_framefmt *format; 910 struct v4l2_rect *crop; 911 912 crop = v4l2_subdev_get_try_crop(subdev, fh->pad, 0); 913 crop->left = MT9V032_COLUMN_START_DEF; 914 crop->top = MT9V032_ROW_START_DEF; 915 crop->width = MT9V032_WINDOW_WIDTH_DEF; 916 crop->height = MT9V032_WINDOW_HEIGHT_DEF; 917 918 format = v4l2_subdev_get_try_format(subdev, fh->pad, 0); 919 920 if (mt9v032->model->color) 921 format->code = MEDIA_BUS_FMT_SGRBG10_1X10; 922 else 923 format->code = MEDIA_BUS_FMT_Y10_1X10; 924 925 format->width = MT9V032_WINDOW_WIDTH_DEF; 926 format->height = MT9V032_WINDOW_HEIGHT_DEF; 927 format->field = V4L2_FIELD_NONE; 928 format->colorspace = V4L2_COLORSPACE_SRGB; 929 930 return mt9v032_set_power(subdev, 1); 931 } 932 933 static int mt9v032_close(struct v4l2_subdev *subdev, struct v4l2_subdev_fh *fh) 934 { 935 return mt9v032_set_power(subdev, 0); 936 } 937 938 static const struct v4l2_subdev_core_ops mt9v032_subdev_core_ops = { 939 .s_power = mt9v032_set_power, 940 }; 941 942 static const struct v4l2_subdev_video_ops mt9v032_subdev_video_ops = { 943 .s_stream = mt9v032_s_stream, 944 }; 945 946 static const struct v4l2_subdev_pad_ops mt9v032_subdev_pad_ops = { 947 .enum_mbus_code = mt9v032_enum_mbus_code, 948 .enum_frame_size = mt9v032_enum_frame_size, 949 .get_fmt = mt9v032_get_format, 950 .set_fmt = mt9v032_set_format, 951 .get_selection = mt9v032_get_selection, 952 .set_selection = mt9v032_set_selection, 953 }; 954 955 static const struct v4l2_subdev_ops mt9v032_subdev_ops = { 956 .core = &mt9v032_subdev_core_ops, 957 .video = &mt9v032_subdev_video_ops, 958 .pad = &mt9v032_subdev_pad_ops, 959 }; 960 961 static const struct v4l2_subdev_internal_ops mt9v032_subdev_internal_ops = { 962 .registered = mt9v032_registered, 963 .open = mt9v032_open, 964 .close = mt9v032_close, 965 }; 966 967 static const struct regmap_config mt9v032_regmap_config = { 968 .reg_bits = 8, 969 .val_bits = 16, 970 .max_register = 0xff, 971 .cache_type = REGCACHE_RBTREE, 972 }; 973 974 /* ----------------------------------------------------------------------------- 975 * Driver initialization and probing 976 */ 977 978 static struct mt9v032_platform_data * 979 mt9v032_get_pdata(struct i2c_client *client) 980 { 981 struct mt9v032_platform_data *pdata = NULL; 982 struct v4l2_of_endpoint endpoint; 983 struct device_node *np; 984 struct property *prop; 985 986 if (!IS_ENABLED(CONFIG_OF) || !client->dev.of_node) 987 return client->dev.platform_data; 988 989 np = of_graph_get_next_endpoint(client->dev.of_node, NULL); 990 if (!np) 991 return NULL; 992 993 if (v4l2_of_parse_endpoint(np, &endpoint) < 0) 994 goto done; 995 996 pdata = devm_kzalloc(&client->dev, sizeof(*pdata), GFP_KERNEL); 997 if (!pdata) 998 goto done; 999 1000 prop = of_find_property(np, "link-frequencies", NULL); 1001 if (prop) { 1002 u64 *link_freqs; 1003 size_t size = prop->length / sizeof(*link_freqs); 1004 1005 link_freqs = devm_kcalloc(&client->dev, size, 1006 sizeof(*link_freqs), GFP_KERNEL); 1007 if (!link_freqs) 1008 goto done; 1009 1010 if (of_property_read_u64_array(np, "link-frequencies", 1011 link_freqs, size) < 0) 1012 goto done; 1013 1014 pdata->link_freqs = link_freqs; 1015 pdata->link_def_freq = link_freqs[0]; 1016 } 1017 1018 pdata->clk_pol = !!(endpoint.bus.parallel.flags & 1019 V4L2_MBUS_PCLK_SAMPLE_RISING); 1020 1021 done: 1022 of_node_put(np); 1023 return pdata; 1024 } 1025 1026 static int mt9v032_probe(struct i2c_client *client, 1027 const struct i2c_device_id *did) 1028 { 1029 struct mt9v032_platform_data *pdata = mt9v032_get_pdata(client); 1030 struct mt9v032 *mt9v032; 1031 unsigned int i; 1032 int ret; 1033 1034 mt9v032 = devm_kzalloc(&client->dev, sizeof(*mt9v032), GFP_KERNEL); 1035 if (!mt9v032) 1036 return -ENOMEM; 1037 1038 mt9v032->regmap = devm_regmap_init_i2c(client, &mt9v032_regmap_config); 1039 if (IS_ERR(mt9v032->regmap)) 1040 return PTR_ERR(mt9v032->regmap); 1041 1042 mt9v032->clk = devm_clk_get(&client->dev, NULL); 1043 if (IS_ERR(mt9v032->clk)) 1044 return PTR_ERR(mt9v032->clk); 1045 1046 mt9v032->reset_gpio = devm_gpiod_get_optional(&client->dev, "reset", 1047 GPIOD_OUT_HIGH); 1048 if (IS_ERR(mt9v032->reset_gpio)) 1049 return PTR_ERR(mt9v032->reset_gpio); 1050 1051 mt9v032->standby_gpio = devm_gpiod_get_optional(&client->dev, "standby", 1052 GPIOD_OUT_LOW); 1053 if (IS_ERR(mt9v032->standby_gpio)) 1054 return PTR_ERR(mt9v032->standby_gpio); 1055 1056 mutex_init(&mt9v032->power_lock); 1057 mt9v032->pdata = pdata; 1058 mt9v032->model = (const void *)did->driver_data; 1059 1060 v4l2_ctrl_handler_init(&mt9v032->ctrls, 11 + 1061 ARRAY_SIZE(mt9v032_aegc_controls)); 1062 1063 v4l2_ctrl_new_std(&mt9v032->ctrls, &mt9v032_ctrl_ops, 1064 V4L2_CID_AUTOGAIN, 0, 1, 1, 1); 1065 v4l2_ctrl_new_std(&mt9v032->ctrls, &mt9v032_ctrl_ops, 1066 V4L2_CID_GAIN, MT9V032_ANALOG_GAIN_MIN, 1067 MT9V032_ANALOG_GAIN_MAX, 1, MT9V032_ANALOG_GAIN_DEF); 1068 v4l2_ctrl_new_std_menu(&mt9v032->ctrls, &mt9v032_ctrl_ops, 1069 V4L2_CID_EXPOSURE_AUTO, V4L2_EXPOSURE_MANUAL, 0, 1070 V4L2_EXPOSURE_AUTO); 1071 v4l2_ctrl_new_std(&mt9v032->ctrls, &mt9v032_ctrl_ops, 1072 V4L2_CID_EXPOSURE, mt9v032->model->data->min_shutter, 1073 mt9v032->model->data->max_shutter, 1, 1074 MT9V032_TOTAL_SHUTTER_WIDTH_DEF); 1075 v4l2_ctrl_new_std(&mt9v032->ctrls, &mt9v032_ctrl_ops, 1076 V4L2_CID_HBLANK, mt9v032->model->data->min_hblank, 1077 MT9V032_HORIZONTAL_BLANKING_MAX, 1, 1078 MT9V032_HORIZONTAL_BLANKING_DEF); 1079 v4l2_ctrl_new_std(&mt9v032->ctrls, &mt9v032_ctrl_ops, 1080 V4L2_CID_VBLANK, mt9v032->model->data->min_vblank, 1081 mt9v032->model->data->max_vblank, 1, 1082 MT9V032_VERTICAL_BLANKING_DEF); 1083 mt9v032->test_pattern = v4l2_ctrl_new_std_menu_items(&mt9v032->ctrls, 1084 &mt9v032_ctrl_ops, V4L2_CID_TEST_PATTERN, 1085 ARRAY_SIZE(mt9v032_test_pattern_menu) - 1, 0, 0, 1086 mt9v032_test_pattern_menu); 1087 mt9v032->test_pattern_color = v4l2_ctrl_new_custom(&mt9v032->ctrls, 1088 &mt9v032_test_pattern_color, NULL); 1089 1090 v4l2_ctrl_new_custom(&mt9v032->ctrls, 1091 mt9v032->model->data->aec_max_shutter_v4l2_ctrl, 1092 NULL); 1093 for (i = 0; i < ARRAY_SIZE(mt9v032_aegc_controls); ++i) 1094 v4l2_ctrl_new_custom(&mt9v032->ctrls, &mt9v032_aegc_controls[i], 1095 NULL); 1096 1097 v4l2_ctrl_cluster(2, &mt9v032->test_pattern); 1098 1099 mt9v032->pixel_rate = 1100 v4l2_ctrl_new_std(&mt9v032->ctrls, &mt9v032_ctrl_ops, 1101 V4L2_CID_PIXEL_RATE, 1, INT_MAX, 1, 1); 1102 1103 if (pdata && pdata->link_freqs) { 1104 unsigned int def = 0; 1105 1106 for (i = 0; pdata->link_freqs[i]; ++i) { 1107 if (pdata->link_freqs[i] == pdata->link_def_freq) 1108 def = i; 1109 } 1110 1111 mt9v032->link_freq = 1112 v4l2_ctrl_new_int_menu(&mt9v032->ctrls, 1113 &mt9v032_ctrl_ops, 1114 V4L2_CID_LINK_FREQ, i - 1, def, 1115 pdata->link_freqs); 1116 v4l2_ctrl_cluster(2, &mt9v032->link_freq); 1117 } 1118 1119 1120 mt9v032->subdev.ctrl_handler = &mt9v032->ctrls; 1121 1122 if (mt9v032->ctrls.error) { 1123 dev_err(&client->dev, "control initialization error %d\n", 1124 mt9v032->ctrls.error); 1125 ret = mt9v032->ctrls.error; 1126 goto err; 1127 } 1128 1129 mt9v032->crop.left = MT9V032_COLUMN_START_DEF; 1130 mt9v032->crop.top = MT9V032_ROW_START_DEF; 1131 mt9v032->crop.width = MT9V032_WINDOW_WIDTH_DEF; 1132 mt9v032->crop.height = MT9V032_WINDOW_HEIGHT_DEF; 1133 1134 if (mt9v032->model->color) 1135 mt9v032->format.code = MEDIA_BUS_FMT_SGRBG10_1X10; 1136 else 1137 mt9v032->format.code = MEDIA_BUS_FMT_Y10_1X10; 1138 1139 mt9v032->format.width = MT9V032_WINDOW_WIDTH_DEF; 1140 mt9v032->format.height = MT9V032_WINDOW_HEIGHT_DEF; 1141 mt9v032->format.field = V4L2_FIELD_NONE; 1142 mt9v032->format.colorspace = V4L2_COLORSPACE_SRGB; 1143 1144 mt9v032->hratio = 1; 1145 mt9v032->vratio = 1; 1146 1147 mt9v032->aec_agc = MT9V032_AEC_ENABLE | MT9V032_AGC_ENABLE; 1148 mt9v032->hblank = MT9V032_HORIZONTAL_BLANKING_DEF; 1149 mt9v032->sysclk = MT9V032_SYSCLK_FREQ_DEF; 1150 1151 v4l2_i2c_subdev_init(&mt9v032->subdev, client, &mt9v032_subdev_ops); 1152 mt9v032->subdev.internal_ops = &mt9v032_subdev_internal_ops; 1153 mt9v032->subdev.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; 1154 1155 mt9v032->pad.flags = MEDIA_PAD_FL_SOURCE; 1156 ret = media_entity_pads_init(&mt9v032->subdev.entity, 1, &mt9v032->pad); 1157 if (ret < 0) 1158 goto err; 1159 1160 mt9v032->subdev.dev = &client->dev; 1161 ret = v4l2_async_register_subdev(&mt9v032->subdev); 1162 if (ret < 0) 1163 goto err; 1164 1165 return 0; 1166 1167 err: 1168 media_entity_cleanup(&mt9v032->subdev.entity); 1169 v4l2_ctrl_handler_free(&mt9v032->ctrls); 1170 return ret; 1171 } 1172 1173 static int mt9v032_remove(struct i2c_client *client) 1174 { 1175 struct v4l2_subdev *subdev = i2c_get_clientdata(client); 1176 struct mt9v032 *mt9v032 = to_mt9v032(subdev); 1177 1178 v4l2_async_unregister_subdev(subdev); 1179 v4l2_ctrl_handler_free(&mt9v032->ctrls); 1180 media_entity_cleanup(&subdev->entity); 1181 1182 return 0; 1183 } 1184 1185 static const struct mt9v032_model_data mt9v032_model_data[] = { 1186 { 1187 /* MT9V022, MT9V032 revisions 1/2/3 */ 1188 .min_row_time = 660, 1189 .min_hblank = MT9V032_HORIZONTAL_BLANKING_MIN, 1190 .min_vblank = MT9V032_VERTICAL_BLANKING_MIN, 1191 .max_vblank = MT9V032_VERTICAL_BLANKING_MAX, 1192 .min_shutter = MT9V032_TOTAL_SHUTTER_WIDTH_MIN, 1193 .max_shutter = MT9V032_TOTAL_SHUTTER_WIDTH_MAX, 1194 .pclk_reg = MT9V032_PIXEL_CLOCK, 1195 .aec_max_shutter_reg = MT9V032_AEC_MAX_SHUTTER_WIDTH, 1196 .aec_max_shutter_v4l2_ctrl = &mt9v032_aec_max_shutter_width, 1197 }, { 1198 /* MT9V024, MT9V034 */ 1199 .min_row_time = 690, 1200 .min_hblank = MT9V034_HORIZONTAL_BLANKING_MIN, 1201 .min_vblank = MT9V034_VERTICAL_BLANKING_MIN, 1202 .max_vblank = MT9V034_VERTICAL_BLANKING_MAX, 1203 .min_shutter = MT9V034_TOTAL_SHUTTER_WIDTH_MIN, 1204 .max_shutter = MT9V034_TOTAL_SHUTTER_WIDTH_MAX, 1205 .pclk_reg = MT9V034_PIXEL_CLOCK, 1206 .aec_max_shutter_reg = MT9V034_AEC_MAX_SHUTTER_WIDTH, 1207 .aec_max_shutter_v4l2_ctrl = &mt9v034_aec_max_shutter_width, 1208 }, 1209 }; 1210 1211 static const struct mt9v032_model_info mt9v032_models[] = { 1212 [MT9V032_MODEL_V022_COLOR] = { 1213 .data = &mt9v032_model_data[0], 1214 .color = true, 1215 }, 1216 [MT9V032_MODEL_V022_MONO] = { 1217 .data = &mt9v032_model_data[0], 1218 .color = false, 1219 }, 1220 [MT9V032_MODEL_V024_COLOR] = { 1221 .data = &mt9v032_model_data[1], 1222 .color = true, 1223 }, 1224 [MT9V032_MODEL_V024_MONO] = { 1225 .data = &mt9v032_model_data[1], 1226 .color = false, 1227 }, 1228 [MT9V032_MODEL_V032_COLOR] = { 1229 .data = &mt9v032_model_data[0], 1230 .color = true, 1231 }, 1232 [MT9V032_MODEL_V032_MONO] = { 1233 .data = &mt9v032_model_data[0], 1234 .color = false, 1235 }, 1236 [MT9V032_MODEL_V034_COLOR] = { 1237 .data = &mt9v032_model_data[1], 1238 .color = true, 1239 }, 1240 [MT9V032_MODEL_V034_MONO] = { 1241 .data = &mt9v032_model_data[1], 1242 .color = false, 1243 }, 1244 }; 1245 1246 static const struct i2c_device_id mt9v032_id[] = { 1247 { "mt9v022", (kernel_ulong_t)&mt9v032_models[MT9V032_MODEL_V022_COLOR] }, 1248 { "mt9v022m", (kernel_ulong_t)&mt9v032_models[MT9V032_MODEL_V022_MONO] }, 1249 { "mt9v024", (kernel_ulong_t)&mt9v032_models[MT9V032_MODEL_V024_COLOR] }, 1250 { "mt9v024m", (kernel_ulong_t)&mt9v032_models[MT9V032_MODEL_V024_MONO] }, 1251 { "mt9v032", (kernel_ulong_t)&mt9v032_models[MT9V032_MODEL_V032_COLOR] }, 1252 { "mt9v032m", (kernel_ulong_t)&mt9v032_models[MT9V032_MODEL_V032_MONO] }, 1253 { "mt9v034", (kernel_ulong_t)&mt9v032_models[MT9V032_MODEL_V034_COLOR] }, 1254 { "mt9v034m", (kernel_ulong_t)&mt9v032_models[MT9V032_MODEL_V034_MONO] }, 1255 { } 1256 }; 1257 MODULE_DEVICE_TABLE(i2c, mt9v032_id); 1258 1259 #if IS_ENABLED(CONFIG_OF) 1260 static const struct of_device_id mt9v032_of_match[] = { 1261 { .compatible = "aptina,mt9v022" }, 1262 { .compatible = "aptina,mt9v022m" }, 1263 { .compatible = "aptina,mt9v024" }, 1264 { .compatible = "aptina,mt9v024m" }, 1265 { .compatible = "aptina,mt9v032" }, 1266 { .compatible = "aptina,mt9v032m" }, 1267 { .compatible = "aptina,mt9v034" }, 1268 { .compatible = "aptina,mt9v034m" }, 1269 { /* Sentinel */ } 1270 }; 1271 MODULE_DEVICE_TABLE(of, mt9v032_of_match); 1272 #endif 1273 1274 static struct i2c_driver mt9v032_driver = { 1275 .driver = { 1276 .name = "mt9v032", 1277 .of_match_table = of_match_ptr(mt9v032_of_match), 1278 }, 1279 .probe = mt9v032_probe, 1280 .remove = mt9v032_remove, 1281 .id_table = mt9v032_id, 1282 }; 1283 1284 module_i2c_driver(mt9v032_driver); 1285 1286 MODULE_DESCRIPTION("Aptina MT9V032 Camera driver"); 1287 MODULE_AUTHOR("Laurent Pinchart <laurent.pinchart@ideasonboard.com>"); 1288 MODULE_LICENSE("GPL"); 1289