1 /* 2 * mt9t112 Camera Driver 3 * 4 * Copyright (C) 2009 Renesas Solutions Corp. 5 * Kuninori Morimoto <morimoto.kuninori@renesas.com> 6 * 7 * Based on ov772x driver, mt9m111 driver, 8 * 9 * Copyright (C) 2008 Kuninori Morimoto <morimoto.kuninori@renesas.com> 10 * Copyright (C) 2008, Robert Jarzmik <robert.jarzmik@free.fr> 11 * Copyright 2006-7 Jonathan Corbet <corbet@lwn.net> 12 * Copyright (C) 2008 Magnus Damm 13 * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de> 14 * 15 * This program is free software; you can redistribute it and/or modify 16 * it under the terms of the GNU General Public License version 2 as 17 * published by the Free Software Foundation. 18 */ 19 20 #include <linux/delay.h> 21 #include <linux/i2c.h> 22 #include <linux/init.h> 23 #include <linux/module.h> 24 #include <linux/slab.h> 25 #include <linux/v4l2-mediabus.h> 26 #include <linux/videodev2.h> 27 28 #include <media/i2c/mt9t112.h> 29 #include <media/soc_camera.h> 30 #include <media/v4l2-clk.h> 31 #include <media/v4l2-common.h> 32 #include <media/v4l2-image-sizes.h> 33 34 /* you can check PLL/clock info */ 35 /* #define EXT_CLOCK 24000000 */ 36 37 /************************************************************************ 38 macro 39 ************************************************************************/ 40 /* 41 * frame size 42 */ 43 #define MAX_WIDTH 2048 44 #define MAX_HEIGHT 1536 45 46 /* 47 * macro of read/write 48 */ 49 #define ECHECKER(ret, x) \ 50 do { \ 51 (ret) = (x); \ 52 if ((ret) < 0) \ 53 return (ret); \ 54 } while (0) 55 56 #define mt9t112_reg_write(ret, client, a, b) \ 57 ECHECKER(ret, __mt9t112_reg_write(client, a, b)) 58 #define mt9t112_mcu_write(ret, client, a, b) \ 59 ECHECKER(ret, __mt9t112_mcu_write(client, a, b)) 60 61 #define mt9t112_reg_mask_set(ret, client, a, b, c) \ 62 ECHECKER(ret, __mt9t112_reg_mask_set(client, a, b, c)) 63 #define mt9t112_mcu_mask_set(ret, client, a, b, c) \ 64 ECHECKER(ret, __mt9t112_mcu_mask_set(client, a, b, c)) 65 66 #define mt9t112_reg_read(ret, client, a) \ 67 ECHECKER(ret, __mt9t112_reg_read(client, a)) 68 69 /* 70 * Logical address 71 */ 72 #define _VAR(id, offset, base) (base | (id & 0x1f) << 10 | (offset & 0x3ff)) 73 #define VAR(id, offset) _VAR(id, offset, 0x0000) 74 #define VAR8(id, offset) _VAR(id, offset, 0x8000) 75 76 /************************************************************************ 77 struct 78 ************************************************************************/ 79 struct mt9t112_format { 80 u32 code; 81 enum v4l2_colorspace colorspace; 82 u16 fmt; 83 u16 order; 84 }; 85 86 struct mt9t112_priv { 87 struct v4l2_subdev subdev; 88 struct mt9t112_camera_info *info; 89 struct i2c_client *client; 90 struct v4l2_rect frame; 91 struct v4l2_clk *clk; 92 const struct mt9t112_format *format; 93 int num_formats; 94 u32 flags; 95 /* for flags */ 96 #define INIT_DONE (1 << 0) 97 #define PCLK_RISING (1 << 1) 98 }; 99 100 /************************************************************************ 101 supported format 102 ************************************************************************/ 103 104 static const struct mt9t112_format mt9t112_cfmts[] = { 105 { 106 .code = MEDIA_BUS_FMT_UYVY8_2X8, 107 .colorspace = V4L2_COLORSPACE_SRGB, 108 .fmt = 1, 109 .order = 0, 110 }, { 111 .code = MEDIA_BUS_FMT_VYUY8_2X8, 112 .colorspace = V4L2_COLORSPACE_SRGB, 113 .fmt = 1, 114 .order = 1, 115 }, { 116 .code = MEDIA_BUS_FMT_YUYV8_2X8, 117 .colorspace = V4L2_COLORSPACE_SRGB, 118 .fmt = 1, 119 .order = 2, 120 }, { 121 .code = MEDIA_BUS_FMT_YVYU8_2X8, 122 .colorspace = V4L2_COLORSPACE_SRGB, 123 .fmt = 1, 124 .order = 3, 125 }, { 126 .code = MEDIA_BUS_FMT_RGB555_2X8_PADHI_LE, 127 .colorspace = V4L2_COLORSPACE_SRGB, 128 .fmt = 8, 129 .order = 2, 130 }, { 131 .code = MEDIA_BUS_FMT_RGB565_2X8_LE, 132 .colorspace = V4L2_COLORSPACE_SRGB, 133 .fmt = 4, 134 .order = 2, 135 }, 136 }; 137 138 /************************************************************************ 139 general function 140 ************************************************************************/ 141 static struct mt9t112_priv *to_mt9t112(const struct i2c_client *client) 142 { 143 return container_of(i2c_get_clientdata(client), 144 struct mt9t112_priv, 145 subdev); 146 } 147 148 static int __mt9t112_reg_read(const struct i2c_client *client, u16 command) 149 { 150 struct i2c_msg msg[2]; 151 u8 buf[2]; 152 int ret; 153 154 command = swab16(command); 155 156 msg[0].addr = client->addr; 157 msg[0].flags = 0; 158 msg[0].len = 2; 159 msg[0].buf = (u8 *)&command; 160 161 msg[1].addr = client->addr; 162 msg[1].flags = I2C_M_RD; 163 msg[1].len = 2; 164 msg[1].buf = buf; 165 166 /* 167 * if return value of this function is < 0, 168 * it mean error. 169 * else, under 16bit is valid data. 170 */ 171 ret = i2c_transfer(client->adapter, msg, 2); 172 if (ret < 0) 173 return ret; 174 175 memcpy(&ret, buf, 2); 176 return swab16(ret); 177 } 178 179 static int __mt9t112_reg_write(const struct i2c_client *client, 180 u16 command, u16 data) 181 { 182 struct i2c_msg msg; 183 u8 buf[4]; 184 int ret; 185 186 command = swab16(command); 187 data = swab16(data); 188 189 memcpy(buf + 0, &command, 2); 190 memcpy(buf + 2, &data, 2); 191 192 msg.addr = client->addr; 193 msg.flags = 0; 194 msg.len = 4; 195 msg.buf = buf; 196 197 /* 198 * i2c_transfer return message length, 199 * but this function should return 0 if correct case 200 */ 201 ret = i2c_transfer(client->adapter, &msg, 1); 202 if (ret >= 0) 203 ret = 0; 204 205 return ret; 206 } 207 208 static int __mt9t112_reg_mask_set(const struct i2c_client *client, 209 u16 command, 210 u16 mask, 211 u16 set) 212 { 213 int val = __mt9t112_reg_read(client, command); 214 if (val < 0) 215 return val; 216 217 val &= ~mask; 218 val |= set & mask; 219 220 return __mt9t112_reg_write(client, command, val); 221 } 222 223 /* mcu access */ 224 static int __mt9t112_mcu_read(const struct i2c_client *client, u16 command) 225 { 226 int ret; 227 228 ret = __mt9t112_reg_write(client, 0x098E, command); 229 if (ret < 0) 230 return ret; 231 232 return __mt9t112_reg_read(client, 0x0990); 233 } 234 235 static int __mt9t112_mcu_write(const struct i2c_client *client, 236 u16 command, u16 data) 237 { 238 int ret; 239 240 ret = __mt9t112_reg_write(client, 0x098E, command); 241 if (ret < 0) 242 return ret; 243 244 return __mt9t112_reg_write(client, 0x0990, data); 245 } 246 247 static int __mt9t112_mcu_mask_set(const struct i2c_client *client, 248 u16 command, 249 u16 mask, 250 u16 set) 251 { 252 int val = __mt9t112_mcu_read(client, command); 253 if (val < 0) 254 return val; 255 256 val &= ~mask; 257 val |= set & mask; 258 259 return __mt9t112_mcu_write(client, command, val); 260 } 261 262 static int mt9t112_reset(const struct i2c_client *client) 263 { 264 int ret; 265 266 mt9t112_reg_mask_set(ret, client, 0x001a, 0x0001, 0x0001); 267 msleep(1); 268 mt9t112_reg_mask_set(ret, client, 0x001a, 0x0001, 0x0000); 269 270 return ret; 271 } 272 273 #ifndef EXT_CLOCK 274 #define CLOCK_INFO(a, b) 275 #else 276 #define CLOCK_INFO(a, b) mt9t112_clock_info(a, b) 277 static int mt9t112_clock_info(const struct i2c_client *client, u32 ext) 278 { 279 int m, n, p1, p2, p3, p4, p5, p6, p7; 280 u32 vco, clk; 281 char *enable; 282 283 ext /= 1000; /* kbyte order */ 284 285 mt9t112_reg_read(n, client, 0x0012); 286 p1 = n & 0x000f; 287 n = n >> 4; 288 p2 = n & 0x000f; 289 n = n >> 4; 290 p3 = n & 0x000f; 291 292 mt9t112_reg_read(n, client, 0x002a); 293 p4 = n & 0x000f; 294 n = n >> 4; 295 p5 = n & 0x000f; 296 n = n >> 4; 297 p6 = n & 0x000f; 298 299 mt9t112_reg_read(n, client, 0x002c); 300 p7 = n & 0x000f; 301 302 mt9t112_reg_read(n, client, 0x0010); 303 m = n & 0x00ff; 304 n = (n >> 8) & 0x003f; 305 306 enable = ((6000 > ext) || (54000 < ext)) ? "X" : ""; 307 dev_dbg(&client->dev, "EXTCLK : %10u K %s\n", ext, enable); 308 309 vco = 2 * m * ext / (n+1); 310 enable = ((384000 > vco) || (768000 < vco)) ? "X" : ""; 311 dev_dbg(&client->dev, "VCO : %10u K %s\n", vco, enable); 312 313 clk = vco / (p1+1) / (p2+1); 314 enable = (96000 < clk) ? "X" : ""; 315 dev_dbg(&client->dev, "PIXCLK : %10u K %s\n", clk, enable); 316 317 clk = vco / (p3+1); 318 enable = (768000 < clk) ? "X" : ""; 319 dev_dbg(&client->dev, "MIPICLK : %10u K %s\n", clk, enable); 320 321 clk = vco / (p6+1); 322 enable = (96000 < clk) ? "X" : ""; 323 dev_dbg(&client->dev, "MCU CLK : %10u K %s\n", clk, enable); 324 325 clk = vco / (p5+1); 326 enable = (54000 < clk) ? "X" : ""; 327 dev_dbg(&client->dev, "SOC CLK : %10u K %s\n", clk, enable); 328 329 clk = vco / (p4+1); 330 enable = (70000 < clk) ? "X" : ""; 331 dev_dbg(&client->dev, "Sensor CLK : %10u K %s\n", clk, enable); 332 333 clk = vco / (p7+1); 334 dev_dbg(&client->dev, "External sensor : %10u K\n", clk); 335 336 clk = ext / (n+1); 337 enable = ((2000 > clk) || (24000 < clk)) ? "X" : ""; 338 dev_dbg(&client->dev, "PFD : %10u K %s\n", clk, enable); 339 340 return 0; 341 } 342 #endif 343 344 static void mt9t112_frame_check(u32 *width, u32 *height, u32 *left, u32 *top) 345 { 346 soc_camera_limit_side(left, width, 0, 0, MAX_WIDTH); 347 soc_camera_limit_side(top, height, 0, 0, MAX_HEIGHT); 348 } 349 350 static int mt9t112_set_a_frame_size(const struct i2c_client *client, 351 u16 width, 352 u16 height) 353 { 354 int ret; 355 u16 wstart = (MAX_WIDTH - width) / 2; 356 u16 hstart = (MAX_HEIGHT - height) / 2; 357 358 /* (Context A) Image Width/Height */ 359 mt9t112_mcu_write(ret, client, VAR(26, 0), width); 360 mt9t112_mcu_write(ret, client, VAR(26, 2), height); 361 362 /* (Context A) Output Width/Height */ 363 mt9t112_mcu_write(ret, client, VAR(18, 43), 8 + width); 364 mt9t112_mcu_write(ret, client, VAR(18, 45), 8 + height); 365 366 /* (Context A) Start Row/Column */ 367 mt9t112_mcu_write(ret, client, VAR(18, 2), 4 + hstart); 368 mt9t112_mcu_write(ret, client, VAR(18, 4), 4 + wstart); 369 370 /* (Context A) End Row/Column */ 371 mt9t112_mcu_write(ret, client, VAR(18, 6), 11 + height + hstart); 372 mt9t112_mcu_write(ret, client, VAR(18, 8), 11 + width + wstart); 373 374 mt9t112_mcu_write(ret, client, VAR8(1, 0), 0x06); 375 376 return ret; 377 } 378 379 static int mt9t112_set_pll_dividers(const struct i2c_client *client, 380 u8 m, u8 n, 381 u8 p1, u8 p2, u8 p3, 382 u8 p4, u8 p5, u8 p6, 383 u8 p7) 384 { 385 int ret; 386 u16 val; 387 388 /* N/M */ 389 val = (n << 8) | 390 (m << 0); 391 mt9t112_reg_mask_set(ret, client, 0x0010, 0x3fff, val); 392 393 /* P1/P2/P3 */ 394 val = ((p3 & 0x0F) << 8) | 395 ((p2 & 0x0F) << 4) | 396 ((p1 & 0x0F) << 0); 397 mt9t112_reg_mask_set(ret, client, 0x0012, 0x0fff, val); 398 399 /* P4/P5/P6 */ 400 val = (0x7 << 12) | 401 ((p6 & 0x0F) << 8) | 402 ((p5 & 0x0F) << 4) | 403 ((p4 & 0x0F) << 0); 404 mt9t112_reg_mask_set(ret, client, 0x002A, 0x7fff, val); 405 406 /* P7 */ 407 val = (0x1 << 12) | 408 ((p7 & 0x0F) << 0); 409 mt9t112_reg_mask_set(ret, client, 0x002C, 0x100f, val); 410 411 return ret; 412 } 413 414 static int mt9t112_init_pll(const struct i2c_client *client) 415 { 416 struct mt9t112_priv *priv = to_mt9t112(client); 417 int data, i, ret; 418 419 mt9t112_reg_mask_set(ret, client, 0x0014, 0x003, 0x0001); 420 421 /* PLL control: BYPASS PLL = 8517 */ 422 mt9t112_reg_write(ret, client, 0x0014, 0x2145); 423 424 /* Replace these registers when new timing parameters are generated */ 425 mt9t112_set_pll_dividers(client, 426 priv->info->divider.m, 427 priv->info->divider.n, 428 priv->info->divider.p1, 429 priv->info->divider.p2, 430 priv->info->divider.p3, 431 priv->info->divider.p4, 432 priv->info->divider.p5, 433 priv->info->divider.p6, 434 priv->info->divider.p7); 435 436 /* 437 * TEST_BYPASS on 438 * PLL_ENABLE on 439 * SEL_LOCK_DET on 440 * TEST_BYPASS off 441 */ 442 mt9t112_reg_write(ret, client, 0x0014, 0x2525); 443 mt9t112_reg_write(ret, client, 0x0014, 0x2527); 444 mt9t112_reg_write(ret, client, 0x0014, 0x3427); 445 mt9t112_reg_write(ret, client, 0x0014, 0x3027); 446 447 mdelay(10); 448 449 /* 450 * PLL_BYPASS off 451 * Reference clock count 452 * I2C Master Clock Divider 453 */ 454 mt9t112_reg_write(ret, client, 0x0014, 0x3046); 455 mt9t112_reg_write(ret, client, 0x0016, 0x0400); /* JPEG initialization workaround */ 456 mt9t112_reg_write(ret, client, 0x0022, 0x0190); 457 mt9t112_reg_write(ret, client, 0x3B84, 0x0212); 458 459 /* External sensor clock is PLL bypass */ 460 mt9t112_reg_write(ret, client, 0x002E, 0x0500); 461 462 mt9t112_reg_mask_set(ret, client, 0x0018, 0x0002, 0x0002); 463 mt9t112_reg_mask_set(ret, client, 0x3B82, 0x0004, 0x0004); 464 465 /* MCU disabled */ 466 mt9t112_reg_mask_set(ret, client, 0x0018, 0x0004, 0x0004); 467 468 /* out of standby */ 469 mt9t112_reg_mask_set(ret, client, 0x0018, 0x0001, 0); 470 471 mdelay(50); 472 473 /* 474 * Standby Workaround 475 * Disable Secondary I2C Pads 476 */ 477 mt9t112_reg_write(ret, client, 0x0614, 0x0001); 478 mdelay(1); 479 mt9t112_reg_write(ret, client, 0x0614, 0x0001); 480 mdelay(1); 481 mt9t112_reg_write(ret, client, 0x0614, 0x0001); 482 mdelay(1); 483 mt9t112_reg_write(ret, client, 0x0614, 0x0001); 484 mdelay(1); 485 mt9t112_reg_write(ret, client, 0x0614, 0x0001); 486 mdelay(1); 487 mt9t112_reg_write(ret, client, 0x0614, 0x0001); 488 mdelay(1); 489 490 /* poll to verify out of standby. Must Poll this bit */ 491 for (i = 0; i < 100; i++) { 492 mt9t112_reg_read(data, client, 0x0018); 493 if (!(0x4000 & data)) 494 break; 495 496 mdelay(10); 497 } 498 499 return ret; 500 } 501 502 static int mt9t112_init_setting(const struct i2c_client *client) 503 { 504 505 int ret; 506 507 /* Adaptive Output Clock (A) */ 508 mt9t112_mcu_mask_set(ret, client, VAR(26, 160), 0x0040, 0x0000); 509 510 /* Read Mode (A) */ 511 mt9t112_mcu_write(ret, client, VAR(18, 12), 0x0024); 512 513 /* Fine Correction (A) */ 514 mt9t112_mcu_write(ret, client, VAR(18, 15), 0x00CC); 515 516 /* Fine IT Min (A) */ 517 mt9t112_mcu_write(ret, client, VAR(18, 17), 0x01f1); 518 519 /* Fine IT Max Margin (A) */ 520 mt9t112_mcu_write(ret, client, VAR(18, 19), 0x00fF); 521 522 /* Base Frame Lines (A) */ 523 mt9t112_mcu_write(ret, client, VAR(18, 29), 0x032D); 524 525 /* Min Line Length (A) */ 526 mt9t112_mcu_write(ret, client, VAR(18, 31), 0x073a); 527 528 /* Line Length (A) */ 529 mt9t112_mcu_write(ret, client, VAR(18, 37), 0x07d0); 530 531 /* Adaptive Output Clock (B) */ 532 mt9t112_mcu_mask_set(ret, client, VAR(27, 160), 0x0040, 0x0000); 533 534 /* Row Start (B) */ 535 mt9t112_mcu_write(ret, client, VAR(18, 74), 0x004); 536 537 /* Column Start (B) */ 538 mt9t112_mcu_write(ret, client, VAR(18, 76), 0x004); 539 540 /* Row End (B) */ 541 mt9t112_mcu_write(ret, client, VAR(18, 78), 0x60B); 542 543 /* Column End (B) */ 544 mt9t112_mcu_write(ret, client, VAR(18, 80), 0x80B); 545 546 /* Fine Correction (B) */ 547 mt9t112_mcu_write(ret, client, VAR(18, 87), 0x008C); 548 549 /* Fine IT Min (B) */ 550 mt9t112_mcu_write(ret, client, VAR(18, 89), 0x01F1); 551 552 /* Fine IT Max Margin (B) */ 553 mt9t112_mcu_write(ret, client, VAR(18, 91), 0x00FF); 554 555 /* Base Frame Lines (B) */ 556 mt9t112_mcu_write(ret, client, VAR(18, 101), 0x0668); 557 558 /* Min Line Length (B) */ 559 mt9t112_mcu_write(ret, client, VAR(18, 103), 0x0AF0); 560 561 /* Line Length (B) */ 562 mt9t112_mcu_write(ret, client, VAR(18, 109), 0x0AF0); 563 564 /* 565 * Flicker Dectection registers 566 * This section should be replaced whenever new Timing file is generated 567 * All the following registers need to be replaced 568 * Following registers are generated from Register Wizard but user can 569 * modify them. For detail see auto flicker detection tuning 570 */ 571 572 /* FD_FDPERIOD_SELECT */ 573 mt9t112_mcu_write(ret, client, VAR8(8, 5), 0x01); 574 575 /* PRI_B_CONFIG_FD_ALGO_RUN */ 576 mt9t112_mcu_write(ret, client, VAR(27, 17), 0x0003); 577 578 /* PRI_A_CONFIG_FD_ALGO_RUN */ 579 mt9t112_mcu_write(ret, client, VAR(26, 17), 0x0003); 580 581 /* 582 * AFD range detection tuning registers 583 */ 584 585 /* search_f1_50 */ 586 mt9t112_mcu_write(ret, client, VAR8(18, 165), 0x25); 587 588 /* search_f2_50 */ 589 mt9t112_mcu_write(ret, client, VAR8(18, 166), 0x28); 590 591 /* search_f1_60 */ 592 mt9t112_mcu_write(ret, client, VAR8(18, 167), 0x2C); 593 594 /* search_f2_60 */ 595 mt9t112_mcu_write(ret, client, VAR8(18, 168), 0x2F); 596 597 /* period_50Hz (A) */ 598 mt9t112_mcu_write(ret, client, VAR8(18, 68), 0xBA); 599 600 /* secret register by aptina */ 601 /* period_50Hz (A MSB) */ 602 mt9t112_mcu_write(ret, client, VAR8(18, 303), 0x00); 603 604 /* period_60Hz (A) */ 605 mt9t112_mcu_write(ret, client, VAR8(18, 69), 0x9B); 606 607 /* secret register by aptina */ 608 /* period_60Hz (A MSB) */ 609 mt9t112_mcu_write(ret, client, VAR8(18, 301), 0x00); 610 611 /* period_50Hz (B) */ 612 mt9t112_mcu_write(ret, client, VAR8(18, 140), 0x82); 613 614 /* secret register by aptina */ 615 /* period_50Hz (B) MSB */ 616 mt9t112_mcu_write(ret, client, VAR8(18, 304), 0x00); 617 618 /* period_60Hz (B) */ 619 mt9t112_mcu_write(ret, client, VAR8(18, 141), 0x6D); 620 621 /* secret register by aptina */ 622 /* period_60Hz (B) MSB */ 623 mt9t112_mcu_write(ret, client, VAR8(18, 302), 0x00); 624 625 /* FD Mode */ 626 mt9t112_mcu_write(ret, client, VAR8(8, 2), 0x10); 627 628 /* Stat_min */ 629 mt9t112_mcu_write(ret, client, VAR8(8, 9), 0x02); 630 631 /* Stat_max */ 632 mt9t112_mcu_write(ret, client, VAR8(8, 10), 0x03); 633 634 /* Min_amplitude */ 635 mt9t112_mcu_write(ret, client, VAR8(8, 12), 0x0A); 636 637 /* RX FIFO Watermark (A) */ 638 mt9t112_mcu_write(ret, client, VAR(18, 70), 0x0014); 639 640 /* RX FIFO Watermark (B) */ 641 mt9t112_mcu_write(ret, client, VAR(18, 142), 0x0014); 642 643 /* MCLK: 16MHz 644 * PCLK: 73MHz 645 * CorePixCLK: 36.5 MHz 646 */ 647 mt9t112_mcu_write(ret, client, VAR8(18, 0x0044), 133); 648 mt9t112_mcu_write(ret, client, VAR8(18, 0x0045), 110); 649 mt9t112_mcu_write(ret, client, VAR8(18, 0x008c), 130); 650 mt9t112_mcu_write(ret, client, VAR8(18, 0x008d), 108); 651 652 mt9t112_mcu_write(ret, client, VAR8(18, 0x00A5), 27); 653 mt9t112_mcu_write(ret, client, VAR8(18, 0x00a6), 30); 654 mt9t112_mcu_write(ret, client, VAR8(18, 0x00a7), 32); 655 mt9t112_mcu_write(ret, client, VAR8(18, 0x00a8), 35); 656 657 return ret; 658 } 659 660 static int mt9t112_auto_focus_setting(const struct i2c_client *client) 661 { 662 int ret; 663 664 mt9t112_mcu_write(ret, client, VAR(12, 13), 0x000F); 665 mt9t112_mcu_write(ret, client, VAR(12, 23), 0x0F0F); 666 mt9t112_mcu_write(ret, client, VAR8(1, 0), 0x06); 667 668 mt9t112_reg_write(ret, client, 0x0614, 0x0000); 669 670 mt9t112_mcu_write(ret, client, VAR8(1, 0), 0x05); 671 mt9t112_mcu_write(ret, client, VAR8(12, 2), 0x02); 672 mt9t112_mcu_write(ret, client, VAR(12, 3), 0x0002); 673 mt9t112_mcu_write(ret, client, VAR(17, 3), 0x8001); 674 mt9t112_mcu_write(ret, client, VAR(17, 11), 0x0025); 675 mt9t112_mcu_write(ret, client, VAR(17, 13), 0x0193); 676 mt9t112_mcu_write(ret, client, VAR8(17, 33), 0x18); 677 mt9t112_mcu_write(ret, client, VAR8(1, 0), 0x05); 678 679 return ret; 680 } 681 682 static int mt9t112_auto_focus_trigger(const struct i2c_client *client) 683 { 684 int ret; 685 686 mt9t112_mcu_write(ret, client, VAR8(12, 25), 0x01); 687 688 return ret; 689 } 690 691 static int mt9t112_init_camera(const struct i2c_client *client) 692 { 693 int ret; 694 695 ECHECKER(ret, mt9t112_reset(client)); 696 697 ECHECKER(ret, mt9t112_init_pll(client)); 698 699 ECHECKER(ret, mt9t112_init_setting(client)); 700 701 ECHECKER(ret, mt9t112_auto_focus_setting(client)); 702 703 mt9t112_reg_mask_set(ret, client, 0x0018, 0x0004, 0); 704 705 /* Analog setting B */ 706 mt9t112_reg_write(ret, client, 0x3084, 0x2409); 707 mt9t112_reg_write(ret, client, 0x3092, 0x0A49); 708 mt9t112_reg_write(ret, client, 0x3094, 0x4949); 709 mt9t112_reg_write(ret, client, 0x3096, 0x4950); 710 711 /* 712 * Disable adaptive clock 713 * PRI_A_CONFIG_JPEG_OB_TX_CONTROL_VAR 714 * PRI_B_CONFIG_JPEG_OB_TX_CONTROL_VAR 715 */ 716 mt9t112_mcu_write(ret, client, VAR(26, 160), 0x0A2E); 717 mt9t112_mcu_write(ret, client, VAR(27, 160), 0x0A2E); 718 719 /* Configure STatus in Status_before_length Format and enable header */ 720 /* PRI_B_CONFIG_JPEG_OB_TX_CONTROL_VAR */ 721 mt9t112_mcu_write(ret, client, VAR(27, 144), 0x0CB4); 722 723 /* Enable JPEG in context B */ 724 /* PRI_B_CONFIG_JPEG_OB_TX_CONTROL_VAR */ 725 mt9t112_mcu_write(ret, client, VAR8(27, 142), 0x01); 726 727 /* Disable Dac_TXLO */ 728 mt9t112_reg_write(ret, client, 0x316C, 0x350F); 729 730 /* Set max slew rates */ 731 mt9t112_reg_write(ret, client, 0x1E, 0x777); 732 733 return ret; 734 } 735 736 /************************************************************************ 737 v4l2_subdev_core_ops 738 ************************************************************************/ 739 740 #ifdef CONFIG_VIDEO_ADV_DEBUG 741 static int mt9t112_g_register(struct v4l2_subdev *sd, 742 struct v4l2_dbg_register *reg) 743 { 744 struct i2c_client *client = v4l2_get_subdevdata(sd); 745 int ret; 746 747 reg->size = 2; 748 mt9t112_reg_read(ret, client, reg->reg); 749 750 reg->val = (__u64)ret; 751 752 return 0; 753 } 754 755 static int mt9t112_s_register(struct v4l2_subdev *sd, 756 const struct v4l2_dbg_register *reg) 757 { 758 struct i2c_client *client = v4l2_get_subdevdata(sd); 759 int ret; 760 761 mt9t112_reg_write(ret, client, reg->reg, reg->val); 762 763 return ret; 764 } 765 #endif 766 767 static int mt9t112_s_power(struct v4l2_subdev *sd, int on) 768 { 769 struct i2c_client *client = v4l2_get_subdevdata(sd); 770 struct soc_camera_subdev_desc *ssdd = soc_camera_i2c_to_desc(client); 771 struct mt9t112_priv *priv = to_mt9t112(client); 772 773 return soc_camera_set_power(&client->dev, ssdd, priv->clk, on); 774 } 775 776 static const struct v4l2_subdev_core_ops mt9t112_subdev_core_ops = { 777 #ifdef CONFIG_VIDEO_ADV_DEBUG 778 .g_register = mt9t112_g_register, 779 .s_register = mt9t112_s_register, 780 #endif 781 .s_power = mt9t112_s_power, 782 }; 783 784 785 /************************************************************************ 786 v4l2_subdev_video_ops 787 ************************************************************************/ 788 static int mt9t112_s_stream(struct v4l2_subdev *sd, int enable) 789 { 790 struct i2c_client *client = v4l2_get_subdevdata(sd); 791 struct mt9t112_priv *priv = to_mt9t112(client); 792 int ret = 0; 793 794 if (!enable) { 795 /* FIXME 796 * 797 * If user selected large output size, 798 * and used it long time, 799 * mt9t112 camera will be very warm. 800 * 801 * But current driver can not stop mt9t112 camera. 802 * So, set small size here to solve this problem. 803 */ 804 mt9t112_set_a_frame_size(client, VGA_WIDTH, VGA_HEIGHT); 805 return ret; 806 } 807 808 if (!(priv->flags & INIT_DONE)) { 809 u16 param = PCLK_RISING & priv->flags ? 0x0001 : 0x0000; 810 811 ECHECKER(ret, mt9t112_init_camera(client)); 812 813 /* Invert PCLK (Data sampled on falling edge of pixclk) */ 814 mt9t112_reg_write(ret, client, 0x3C20, param); 815 816 mdelay(5); 817 818 priv->flags |= INIT_DONE; 819 } 820 821 mt9t112_mcu_write(ret, client, VAR(26, 7), priv->format->fmt); 822 mt9t112_mcu_write(ret, client, VAR(26, 9), priv->format->order); 823 mt9t112_mcu_write(ret, client, VAR8(1, 0), 0x06); 824 825 mt9t112_set_a_frame_size(client, 826 priv->frame.width, 827 priv->frame.height); 828 829 ECHECKER(ret, mt9t112_auto_focus_trigger(client)); 830 831 dev_dbg(&client->dev, "format : %d\n", priv->format->code); 832 dev_dbg(&client->dev, "size : %d x %d\n", 833 priv->frame.width, 834 priv->frame.height); 835 836 CLOCK_INFO(client, EXT_CLOCK); 837 838 return ret; 839 } 840 841 static int mt9t112_set_params(struct mt9t112_priv *priv, 842 const struct v4l2_rect *rect, 843 u32 code) 844 { 845 int i; 846 847 /* 848 * get color format 849 */ 850 for (i = 0; i < priv->num_formats; i++) 851 if (mt9t112_cfmts[i].code == code) 852 break; 853 854 if (i == priv->num_formats) 855 return -EINVAL; 856 857 priv->frame = *rect; 858 859 /* 860 * frame size check 861 */ 862 mt9t112_frame_check(&priv->frame.width, &priv->frame.height, 863 &priv->frame.left, &priv->frame.top); 864 865 priv->format = mt9t112_cfmts + i; 866 867 return 0; 868 } 869 870 static int mt9t112_get_selection(struct v4l2_subdev *sd, 871 struct v4l2_subdev_pad_config *cfg, 872 struct v4l2_subdev_selection *sel) 873 { 874 struct i2c_client *client = v4l2_get_subdevdata(sd); 875 struct mt9t112_priv *priv = to_mt9t112(client); 876 877 if (sel->which != V4L2_SUBDEV_FORMAT_ACTIVE) 878 return -EINVAL; 879 880 switch (sel->target) { 881 case V4L2_SEL_TGT_CROP_BOUNDS: 882 sel->r.left = 0; 883 sel->r.top = 0; 884 sel->r.width = MAX_WIDTH; 885 sel->r.height = MAX_HEIGHT; 886 return 0; 887 case V4L2_SEL_TGT_CROP_DEFAULT: 888 sel->r.left = 0; 889 sel->r.top = 0; 890 sel->r.width = VGA_WIDTH; 891 sel->r.height = VGA_HEIGHT; 892 return 0; 893 case V4L2_SEL_TGT_CROP: 894 sel->r = priv->frame; 895 return 0; 896 default: 897 return -EINVAL; 898 } 899 } 900 901 static int mt9t112_set_selection(struct v4l2_subdev *sd, 902 struct v4l2_subdev_pad_config *cfg, 903 struct v4l2_subdev_selection *sel) 904 { 905 struct i2c_client *client = v4l2_get_subdevdata(sd); 906 struct mt9t112_priv *priv = to_mt9t112(client); 907 const struct v4l2_rect *rect = &sel->r; 908 909 if (sel->which != V4L2_SUBDEV_FORMAT_ACTIVE || 910 sel->target != V4L2_SEL_TGT_CROP) 911 return -EINVAL; 912 913 return mt9t112_set_params(priv, rect, priv->format->code); 914 } 915 916 static int mt9t112_get_fmt(struct v4l2_subdev *sd, 917 struct v4l2_subdev_pad_config *cfg, 918 struct v4l2_subdev_format *format) 919 { 920 struct v4l2_mbus_framefmt *mf = &format->format; 921 struct i2c_client *client = v4l2_get_subdevdata(sd); 922 struct mt9t112_priv *priv = to_mt9t112(client); 923 924 if (format->pad) 925 return -EINVAL; 926 927 mf->width = priv->frame.width; 928 mf->height = priv->frame.height; 929 mf->colorspace = priv->format->colorspace; 930 mf->code = priv->format->code; 931 mf->field = V4L2_FIELD_NONE; 932 933 return 0; 934 } 935 936 static int mt9t112_s_fmt(struct v4l2_subdev *sd, 937 struct v4l2_mbus_framefmt *mf) 938 { 939 struct i2c_client *client = v4l2_get_subdevdata(sd); 940 struct mt9t112_priv *priv = to_mt9t112(client); 941 struct v4l2_rect rect = { 942 .width = mf->width, 943 .height = mf->height, 944 .left = priv->frame.left, 945 .top = priv->frame.top, 946 }; 947 int ret; 948 949 ret = mt9t112_set_params(priv, &rect, mf->code); 950 951 if (!ret) 952 mf->colorspace = priv->format->colorspace; 953 954 return ret; 955 } 956 957 static int mt9t112_set_fmt(struct v4l2_subdev *sd, 958 struct v4l2_subdev_pad_config *cfg, 959 struct v4l2_subdev_format *format) 960 { 961 struct v4l2_mbus_framefmt *mf = &format->format; 962 struct i2c_client *client = v4l2_get_subdevdata(sd); 963 struct mt9t112_priv *priv = to_mt9t112(client); 964 unsigned int top, left; 965 int i; 966 967 if (format->pad) 968 return -EINVAL; 969 970 for (i = 0; i < priv->num_formats; i++) 971 if (mt9t112_cfmts[i].code == mf->code) 972 break; 973 974 if (i == priv->num_formats) { 975 mf->code = MEDIA_BUS_FMT_UYVY8_2X8; 976 mf->colorspace = V4L2_COLORSPACE_JPEG; 977 } else { 978 mf->colorspace = mt9t112_cfmts[i].colorspace; 979 } 980 981 mt9t112_frame_check(&mf->width, &mf->height, &left, &top); 982 983 mf->field = V4L2_FIELD_NONE; 984 985 if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE) 986 return mt9t112_s_fmt(sd, mf); 987 cfg->try_fmt = *mf; 988 return 0; 989 } 990 991 static int mt9t112_enum_mbus_code(struct v4l2_subdev *sd, 992 struct v4l2_subdev_pad_config *cfg, 993 struct v4l2_subdev_mbus_code_enum *code) 994 { 995 struct i2c_client *client = v4l2_get_subdevdata(sd); 996 struct mt9t112_priv *priv = to_mt9t112(client); 997 998 if (code->pad || code->index >= priv->num_formats) 999 return -EINVAL; 1000 1001 code->code = mt9t112_cfmts[code->index].code; 1002 1003 return 0; 1004 } 1005 1006 static int mt9t112_g_mbus_config(struct v4l2_subdev *sd, 1007 struct v4l2_mbus_config *cfg) 1008 { 1009 struct i2c_client *client = v4l2_get_subdevdata(sd); 1010 struct soc_camera_subdev_desc *ssdd = soc_camera_i2c_to_desc(client); 1011 1012 cfg->flags = V4L2_MBUS_MASTER | V4L2_MBUS_VSYNC_ACTIVE_HIGH | 1013 V4L2_MBUS_HSYNC_ACTIVE_HIGH | V4L2_MBUS_DATA_ACTIVE_HIGH | 1014 V4L2_MBUS_PCLK_SAMPLE_RISING | V4L2_MBUS_PCLK_SAMPLE_FALLING; 1015 cfg->type = V4L2_MBUS_PARALLEL; 1016 cfg->flags = soc_camera_apply_board_flags(ssdd, cfg); 1017 1018 return 0; 1019 } 1020 1021 static int mt9t112_s_mbus_config(struct v4l2_subdev *sd, 1022 const struct v4l2_mbus_config *cfg) 1023 { 1024 struct i2c_client *client = v4l2_get_subdevdata(sd); 1025 struct soc_camera_subdev_desc *ssdd = soc_camera_i2c_to_desc(client); 1026 struct mt9t112_priv *priv = to_mt9t112(client); 1027 1028 if (soc_camera_apply_board_flags(ssdd, cfg) & V4L2_MBUS_PCLK_SAMPLE_RISING) 1029 priv->flags |= PCLK_RISING; 1030 1031 return 0; 1032 } 1033 1034 static const struct v4l2_subdev_video_ops mt9t112_subdev_video_ops = { 1035 .s_stream = mt9t112_s_stream, 1036 .g_mbus_config = mt9t112_g_mbus_config, 1037 .s_mbus_config = mt9t112_s_mbus_config, 1038 }; 1039 1040 static const struct v4l2_subdev_pad_ops mt9t112_subdev_pad_ops = { 1041 .enum_mbus_code = mt9t112_enum_mbus_code, 1042 .get_selection = mt9t112_get_selection, 1043 .set_selection = mt9t112_set_selection, 1044 .get_fmt = mt9t112_get_fmt, 1045 .set_fmt = mt9t112_set_fmt, 1046 }; 1047 1048 /************************************************************************ 1049 i2c driver 1050 ************************************************************************/ 1051 static const struct v4l2_subdev_ops mt9t112_subdev_ops = { 1052 .core = &mt9t112_subdev_core_ops, 1053 .video = &mt9t112_subdev_video_ops, 1054 .pad = &mt9t112_subdev_pad_ops, 1055 }; 1056 1057 static int mt9t112_camera_probe(struct i2c_client *client) 1058 { 1059 struct mt9t112_priv *priv = to_mt9t112(client); 1060 const char *devname; 1061 int chipid; 1062 int ret; 1063 1064 ret = mt9t112_s_power(&priv->subdev, 1); 1065 if (ret < 0) 1066 return ret; 1067 1068 /* 1069 * check and show chip ID 1070 */ 1071 mt9t112_reg_read(chipid, client, 0x0000); 1072 1073 switch (chipid) { 1074 case 0x2680: 1075 devname = "mt9t111"; 1076 priv->num_formats = 1; 1077 break; 1078 case 0x2682: 1079 devname = "mt9t112"; 1080 priv->num_formats = ARRAY_SIZE(mt9t112_cfmts); 1081 break; 1082 default: 1083 dev_err(&client->dev, "Product ID error %04x\n", chipid); 1084 ret = -ENODEV; 1085 goto done; 1086 } 1087 1088 dev_info(&client->dev, "%s chip ID %04x\n", devname, chipid); 1089 1090 done: 1091 mt9t112_s_power(&priv->subdev, 0); 1092 return ret; 1093 } 1094 1095 static int mt9t112_probe(struct i2c_client *client, 1096 const struct i2c_device_id *did) 1097 { 1098 struct mt9t112_priv *priv; 1099 struct soc_camera_subdev_desc *ssdd = soc_camera_i2c_to_desc(client); 1100 struct v4l2_rect rect = { 1101 .width = VGA_WIDTH, 1102 .height = VGA_HEIGHT, 1103 .left = (MAX_WIDTH - VGA_WIDTH) / 2, 1104 .top = (MAX_HEIGHT - VGA_HEIGHT) / 2, 1105 }; 1106 int ret; 1107 1108 if (!ssdd || !ssdd->drv_priv) { 1109 dev_err(&client->dev, "mt9t112: missing platform data!\n"); 1110 return -EINVAL; 1111 } 1112 1113 priv = devm_kzalloc(&client->dev, sizeof(*priv), GFP_KERNEL); 1114 if (!priv) 1115 return -ENOMEM; 1116 1117 priv->info = ssdd->drv_priv; 1118 1119 v4l2_i2c_subdev_init(&priv->subdev, client, &mt9t112_subdev_ops); 1120 1121 priv->clk = v4l2_clk_get(&client->dev, "mclk"); 1122 if (IS_ERR(priv->clk)) 1123 return PTR_ERR(priv->clk); 1124 1125 ret = mt9t112_camera_probe(client); 1126 1127 /* Cannot fail: using the default supported pixel code */ 1128 if (!ret) 1129 mt9t112_set_params(priv, &rect, MEDIA_BUS_FMT_UYVY8_2X8); 1130 else 1131 v4l2_clk_put(priv->clk); 1132 1133 return ret; 1134 } 1135 1136 static int mt9t112_remove(struct i2c_client *client) 1137 { 1138 struct mt9t112_priv *priv = to_mt9t112(client); 1139 1140 v4l2_clk_put(priv->clk); 1141 return 0; 1142 } 1143 1144 static const struct i2c_device_id mt9t112_id[] = { 1145 { "mt9t112", 0 }, 1146 { } 1147 }; 1148 MODULE_DEVICE_TABLE(i2c, mt9t112_id); 1149 1150 static struct i2c_driver mt9t112_i2c_driver = { 1151 .driver = { 1152 .name = "mt9t112", 1153 }, 1154 .probe = mt9t112_probe, 1155 .remove = mt9t112_remove, 1156 .id_table = mt9t112_id, 1157 }; 1158 1159 module_i2c_driver(mt9t112_i2c_driver); 1160 1161 MODULE_DESCRIPTION("SoC Camera driver for mt9t112"); 1162 MODULE_AUTHOR("Kuninori Morimoto"); 1163 MODULE_LICENSE("GPL v2"); 1164