1 /* 2 * Driver for MT9P031 CMOS Image Sensor from Aptina 3 * 4 * Copyright (C) 2011, Laurent Pinchart <laurent.pinchart@ideasonboard.com> 5 * Copyright (C) 2011, Javier Martin <javier.martin@vista-silicon.com> 6 * Copyright (C) 2011, Guennadi Liakhovetski <g.liakhovetski@gmx.de> 7 * 8 * Based on the MT9V032 driver and Bastian Hecht's code. 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License version 2 as 12 * published by the Free Software Foundation. 13 */ 14 15 #include <linux/clk.h> 16 #include <linux/delay.h> 17 #include <linux/device.h> 18 #include <linux/gpio.h> 19 #include <linux/module.h> 20 #include <linux/i2c.h> 21 #include <linux/log2.h> 22 #include <linux/pm.h> 23 #include <linux/regulator/consumer.h> 24 #include <linux/slab.h> 25 #include <linux/videodev2.h> 26 27 #include <media/mt9p031.h> 28 #include <media/v4l2-ctrls.h> 29 #include <media/v4l2-device.h> 30 #include <media/v4l2-subdev.h> 31 32 #include "aptina-pll.h" 33 34 #define MT9P031_PIXEL_ARRAY_WIDTH 2752 35 #define MT9P031_PIXEL_ARRAY_HEIGHT 2004 36 37 #define MT9P031_CHIP_VERSION 0x00 38 #define MT9P031_CHIP_VERSION_VALUE 0x1801 39 #define MT9P031_ROW_START 0x01 40 #define MT9P031_ROW_START_MIN 0 41 #define MT9P031_ROW_START_MAX 2004 42 #define MT9P031_ROW_START_DEF 54 43 #define MT9P031_COLUMN_START 0x02 44 #define MT9P031_COLUMN_START_MIN 0 45 #define MT9P031_COLUMN_START_MAX 2750 46 #define MT9P031_COLUMN_START_DEF 16 47 #define MT9P031_WINDOW_HEIGHT 0x03 48 #define MT9P031_WINDOW_HEIGHT_MIN 2 49 #define MT9P031_WINDOW_HEIGHT_MAX 2006 50 #define MT9P031_WINDOW_HEIGHT_DEF 1944 51 #define MT9P031_WINDOW_WIDTH 0x04 52 #define MT9P031_WINDOW_WIDTH_MIN 2 53 #define MT9P031_WINDOW_WIDTH_MAX 2752 54 #define MT9P031_WINDOW_WIDTH_DEF 2592 55 #define MT9P031_HORIZONTAL_BLANK 0x05 56 #define MT9P031_HORIZONTAL_BLANK_MIN 0 57 #define MT9P031_HORIZONTAL_BLANK_MAX 4095 58 #define MT9P031_VERTICAL_BLANK 0x06 59 #define MT9P031_VERTICAL_BLANK_MIN 1 60 #define MT9P031_VERTICAL_BLANK_MAX 4096 61 #define MT9P031_VERTICAL_BLANK_DEF 26 62 #define MT9P031_OUTPUT_CONTROL 0x07 63 #define MT9P031_OUTPUT_CONTROL_CEN 2 64 #define MT9P031_OUTPUT_CONTROL_SYN 1 65 #define MT9P031_OUTPUT_CONTROL_DEF 0x1f82 66 #define MT9P031_SHUTTER_WIDTH_UPPER 0x08 67 #define MT9P031_SHUTTER_WIDTH_LOWER 0x09 68 #define MT9P031_SHUTTER_WIDTH_MIN 1 69 #define MT9P031_SHUTTER_WIDTH_MAX 1048575 70 #define MT9P031_SHUTTER_WIDTH_DEF 1943 71 #define MT9P031_PLL_CONTROL 0x10 72 #define MT9P031_PLL_CONTROL_PWROFF 0x0050 73 #define MT9P031_PLL_CONTROL_PWRON 0x0051 74 #define MT9P031_PLL_CONTROL_USEPLL 0x0052 75 #define MT9P031_PLL_CONFIG_1 0x11 76 #define MT9P031_PLL_CONFIG_2 0x12 77 #define MT9P031_PIXEL_CLOCK_CONTROL 0x0a 78 #define MT9P031_FRAME_RESTART 0x0b 79 #define MT9P031_SHUTTER_DELAY 0x0c 80 #define MT9P031_RST 0x0d 81 #define MT9P031_RST_ENABLE 1 82 #define MT9P031_RST_DISABLE 0 83 #define MT9P031_READ_MODE_1 0x1e 84 #define MT9P031_READ_MODE_2 0x20 85 #define MT9P031_READ_MODE_2_ROW_MIR (1 << 15) 86 #define MT9P031_READ_MODE_2_COL_MIR (1 << 14) 87 #define MT9P031_READ_MODE_2_ROW_BLC (1 << 6) 88 #define MT9P031_ROW_ADDRESS_MODE 0x22 89 #define MT9P031_COLUMN_ADDRESS_MODE 0x23 90 #define MT9P031_GLOBAL_GAIN 0x35 91 #define MT9P031_GLOBAL_GAIN_MIN 8 92 #define MT9P031_GLOBAL_GAIN_MAX 1024 93 #define MT9P031_GLOBAL_GAIN_DEF 8 94 #define MT9P031_GLOBAL_GAIN_MULT (1 << 6) 95 #define MT9P031_ROW_BLACK_TARGET 0x49 96 #define MT9P031_ROW_BLACK_DEF_OFFSET 0x4b 97 #define MT9P031_GREEN1_OFFSET 0x60 98 #define MT9P031_GREEN2_OFFSET 0x61 99 #define MT9P031_BLACK_LEVEL_CALIBRATION 0x62 100 #define MT9P031_BLC_MANUAL_BLC (1 << 0) 101 #define MT9P031_RED_OFFSET 0x63 102 #define MT9P031_BLUE_OFFSET 0x64 103 #define MT9P031_TEST_PATTERN 0xa0 104 #define MT9P031_TEST_PATTERN_SHIFT 3 105 #define MT9P031_TEST_PATTERN_ENABLE (1 << 0) 106 #define MT9P031_TEST_PATTERN_DISABLE (0 << 0) 107 #define MT9P031_TEST_PATTERN_GREEN 0xa1 108 #define MT9P031_TEST_PATTERN_RED 0xa2 109 #define MT9P031_TEST_PATTERN_BLUE 0xa3 110 111 enum mt9p031_model { 112 MT9P031_MODEL_COLOR, 113 MT9P031_MODEL_MONOCHROME, 114 }; 115 116 struct mt9p031 { 117 struct v4l2_subdev subdev; 118 struct media_pad pad; 119 struct v4l2_rect crop; /* Sensor window */ 120 struct v4l2_mbus_framefmt format; 121 struct mt9p031_platform_data *pdata; 122 struct mutex power_lock; /* lock to protect power_count */ 123 int power_count; 124 125 struct clk *clk; 126 struct regulator *vaa; 127 struct regulator *vdd; 128 struct regulator *vdd_io; 129 130 enum mt9p031_model model; 131 struct aptina_pll pll; 132 int reset; 133 134 struct v4l2_ctrl_handler ctrls; 135 struct v4l2_ctrl *blc_auto; 136 struct v4l2_ctrl *blc_offset; 137 138 /* Registers cache */ 139 u16 output_control; 140 u16 mode2; 141 }; 142 143 static struct mt9p031 *to_mt9p031(struct v4l2_subdev *sd) 144 { 145 return container_of(sd, struct mt9p031, subdev); 146 } 147 148 static int mt9p031_read(struct i2c_client *client, u8 reg) 149 { 150 return i2c_smbus_read_word_swapped(client, reg); 151 } 152 153 static int mt9p031_write(struct i2c_client *client, u8 reg, u16 data) 154 { 155 return i2c_smbus_write_word_swapped(client, reg, data); 156 } 157 158 static int mt9p031_set_output_control(struct mt9p031 *mt9p031, u16 clear, 159 u16 set) 160 { 161 struct i2c_client *client = v4l2_get_subdevdata(&mt9p031->subdev); 162 u16 value = (mt9p031->output_control & ~clear) | set; 163 int ret; 164 165 ret = mt9p031_write(client, MT9P031_OUTPUT_CONTROL, value); 166 if (ret < 0) 167 return ret; 168 169 mt9p031->output_control = value; 170 return 0; 171 } 172 173 static int mt9p031_set_mode2(struct mt9p031 *mt9p031, u16 clear, u16 set) 174 { 175 struct i2c_client *client = v4l2_get_subdevdata(&mt9p031->subdev); 176 u16 value = (mt9p031->mode2 & ~clear) | set; 177 int ret; 178 179 ret = mt9p031_write(client, MT9P031_READ_MODE_2, value); 180 if (ret < 0) 181 return ret; 182 183 mt9p031->mode2 = value; 184 return 0; 185 } 186 187 static int mt9p031_reset(struct mt9p031 *mt9p031) 188 { 189 struct i2c_client *client = v4l2_get_subdevdata(&mt9p031->subdev); 190 int ret; 191 192 /* Disable chip output, synchronous option update */ 193 ret = mt9p031_write(client, MT9P031_RST, MT9P031_RST_ENABLE); 194 if (ret < 0) 195 return ret; 196 ret = mt9p031_write(client, MT9P031_RST, MT9P031_RST_DISABLE); 197 if (ret < 0) 198 return ret; 199 200 return mt9p031_set_output_control(mt9p031, MT9P031_OUTPUT_CONTROL_CEN, 201 0); 202 } 203 204 static int mt9p031_clk_setup(struct mt9p031 *mt9p031) 205 { 206 static const struct aptina_pll_limits limits = { 207 .ext_clock_min = 6000000, 208 .ext_clock_max = 27000000, 209 .int_clock_min = 2000000, 210 .int_clock_max = 13500000, 211 .out_clock_min = 180000000, 212 .out_clock_max = 360000000, 213 .pix_clock_max = 96000000, 214 .n_min = 1, 215 .n_max = 64, 216 .m_min = 16, 217 .m_max = 255, 218 .p1_min = 1, 219 .p1_max = 128, 220 }; 221 222 struct i2c_client *client = v4l2_get_subdevdata(&mt9p031->subdev); 223 struct mt9p031_platform_data *pdata = mt9p031->pdata; 224 225 mt9p031->clk = devm_clk_get(&client->dev, NULL); 226 if (IS_ERR(mt9p031->clk)) 227 return PTR_ERR(mt9p031->clk); 228 229 clk_set_rate(mt9p031->clk, pdata->ext_freq); 230 231 mt9p031->pll.ext_clock = pdata->ext_freq; 232 mt9p031->pll.pix_clock = pdata->target_freq; 233 234 return aptina_pll_calculate(&client->dev, &limits, &mt9p031->pll); 235 } 236 237 static int mt9p031_pll_enable(struct mt9p031 *mt9p031) 238 { 239 struct i2c_client *client = v4l2_get_subdevdata(&mt9p031->subdev); 240 int ret; 241 242 ret = mt9p031_write(client, MT9P031_PLL_CONTROL, 243 MT9P031_PLL_CONTROL_PWRON); 244 if (ret < 0) 245 return ret; 246 247 ret = mt9p031_write(client, MT9P031_PLL_CONFIG_1, 248 (mt9p031->pll.m << 8) | (mt9p031->pll.n - 1)); 249 if (ret < 0) 250 return ret; 251 252 ret = mt9p031_write(client, MT9P031_PLL_CONFIG_2, mt9p031->pll.p1 - 1); 253 if (ret < 0) 254 return ret; 255 256 usleep_range(1000, 2000); 257 ret = mt9p031_write(client, MT9P031_PLL_CONTROL, 258 MT9P031_PLL_CONTROL_PWRON | 259 MT9P031_PLL_CONTROL_USEPLL); 260 return ret; 261 } 262 263 static inline int mt9p031_pll_disable(struct mt9p031 *mt9p031) 264 { 265 struct i2c_client *client = v4l2_get_subdevdata(&mt9p031->subdev); 266 267 return mt9p031_write(client, MT9P031_PLL_CONTROL, 268 MT9P031_PLL_CONTROL_PWROFF); 269 } 270 271 static int mt9p031_power_on(struct mt9p031 *mt9p031) 272 { 273 /* Ensure RESET_BAR is low */ 274 if (gpio_is_valid(mt9p031->reset)) { 275 gpio_set_value(mt9p031->reset, 0); 276 usleep_range(1000, 2000); 277 } 278 279 /* Bring up the supplies */ 280 regulator_enable(mt9p031->vdd); 281 regulator_enable(mt9p031->vdd_io); 282 regulator_enable(mt9p031->vaa); 283 284 /* Emable clock */ 285 if (mt9p031->clk) 286 clk_prepare_enable(mt9p031->clk); 287 288 /* Now RESET_BAR must be high */ 289 if (gpio_is_valid(mt9p031->reset)) { 290 gpio_set_value(mt9p031->reset, 1); 291 usleep_range(1000, 2000); 292 } 293 294 return 0; 295 } 296 297 static void mt9p031_power_off(struct mt9p031 *mt9p031) 298 { 299 if (gpio_is_valid(mt9p031->reset)) { 300 gpio_set_value(mt9p031->reset, 0); 301 usleep_range(1000, 2000); 302 } 303 304 regulator_disable(mt9p031->vaa); 305 regulator_disable(mt9p031->vdd_io); 306 regulator_disable(mt9p031->vdd); 307 308 if (mt9p031->clk) 309 clk_disable_unprepare(mt9p031->clk); 310 } 311 312 static int __mt9p031_set_power(struct mt9p031 *mt9p031, bool on) 313 { 314 struct i2c_client *client = v4l2_get_subdevdata(&mt9p031->subdev); 315 int ret; 316 317 if (!on) { 318 mt9p031_power_off(mt9p031); 319 return 0; 320 } 321 322 ret = mt9p031_power_on(mt9p031); 323 if (ret < 0) 324 return ret; 325 326 ret = mt9p031_reset(mt9p031); 327 if (ret < 0) { 328 dev_err(&client->dev, "Failed to reset the camera\n"); 329 return ret; 330 } 331 332 return v4l2_ctrl_handler_setup(&mt9p031->ctrls); 333 } 334 335 /* ----------------------------------------------------------------------------- 336 * V4L2 subdev video operations 337 */ 338 339 static int mt9p031_set_params(struct mt9p031 *mt9p031) 340 { 341 struct i2c_client *client = v4l2_get_subdevdata(&mt9p031->subdev); 342 struct v4l2_mbus_framefmt *format = &mt9p031->format; 343 const struct v4l2_rect *crop = &mt9p031->crop; 344 unsigned int hblank; 345 unsigned int vblank; 346 unsigned int xskip; 347 unsigned int yskip; 348 unsigned int xbin; 349 unsigned int ybin; 350 int ret; 351 352 /* Windows position and size. 353 * 354 * TODO: Make sure the start coordinates and window size match the 355 * skipping, binning and mirroring (see description of registers 2 and 4 356 * in table 13, and Binning section on page 41). 357 */ 358 ret = mt9p031_write(client, MT9P031_COLUMN_START, crop->left); 359 if (ret < 0) 360 return ret; 361 ret = mt9p031_write(client, MT9P031_ROW_START, crop->top); 362 if (ret < 0) 363 return ret; 364 ret = mt9p031_write(client, MT9P031_WINDOW_WIDTH, crop->width - 1); 365 if (ret < 0) 366 return ret; 367 ret = mt9p031_write(client, MT9P031_WINDOW_HEIGHT, crop->height - 1); 368 if (ret < 0) 369 return ret; 370 371 /* Row and column binning and skipping. Use the maximum binning value 372 * compatible with the skipping settings. 373 */ 374 xskip = DIV_ROUND_CLOSEST(crop->width, format->width); 375 yskip = DIV_ROUND_CLOSEST(crop->height, format->height); 376 xbin = 1 << (ffs(xskip) - 1); 377 ybin = 1 << (ffs(yskip) - 1); 378 379 ret = mt9p031_write(client, MT9P031_COLUMN_ADDRESS_MODE, 380 ((xbin - 1) << 4) | (xskip - 1)); 381 if (ret < 0) 382 return ret; 383 ret = mt9p031_write(client, MT9P031_ROW_ADDRESS_MODE, 384 ((ybin - 1) << 4) | (yskip - 1)); 385 if (ret < 0) 386 return ret; 387 388 /* Blanking - use minimum value for horizontal blanking and default 389 * value for vertical blanking. 390 */ 391 hblank = 346 * ybin + 64 + (80 >> min_t(unsigned int, xbin, 3)); 392 vblank = MT9P031_VERTICAL_BLANK_DEF; 393 394 ret = mt9p031_write(client, MT9P031_HORIZONTAL_BLANK, hblank - 1); 395 if (ret < 0) 396 return ret; 397 ret = mt9p031_write(client, MT9P031_VERTICAL_BLANK, vblank - 1); 398 if (ret < 0) 399 return ret; 400 401 return ret; 402 } 403 404 static int mt9p031_s_stream(struct v4l2_subdev *subdev, int enable) 405 { 406 struct mt9p031 *mt9p031 = to_mt9p031(subdev); 407 int ret; 408 409 if (!enable) { 410 /* Stop sensor readout */ 411 ret = mt9p031_set_output_control(mt9p031, 412 MT9P031_OUTPUT_CONTROL_CEN, 0); 413 if (ret < 0) 414 return ret; 415 416 return mt9p031_pll_disable(mt9p031); 417 } 418 419 ret = mt9p031_set_params(mt9p031); 420 if (ret < 0) 421 return ret; 422 423 /* Switch to master "normal" mode */ 424 ret = mt9p031_set_output_control(mt9p031, 0, 425 MT9P031_OUTPUT_CONTROL_CEN); 426 if (ret < 0) 427 return ret; 428 429 return mt9p031_pll_enable(mt9p031); 430 } 431 432 static int mt9p031_enum_mbus_code(struct v4l2_subdev *subdev, 433 struct v4l2_subdev_fh *fh, 434 struct v4l2_subdev_mbus_code_enum *code) 435 { 436 struct mt9p031 *mt9p031 = to_mt9p031(subdev); 437 438 if (code->pad || code->index) 439 return -EINVAL; 440 441 code->code = mt9p031->format.code; 442 return 0; 443 } 444 445 static int mt9p031_enum_frame_size(struct v4l2_subdev *subdev, 446 struct v4l2_subdev_fh *fh, 447 struct v4l2_subdev_frame_size_enum *fse) 448 { 449 struct mt9p031 *mt9p031 = to_mt9p031(subdev); 450 451 if (fse->index >= 8 || fse->code != mt9p031->format.code) 452 return -EINVAL; 453 454 fse->min_width = MT9P031_WINDOW_WIDTH_DEF 455 / min_t(unsigned int, 7, fse->index + 1); 456 fse->max_width = fse->min_width; 457 fse->min_height = MT9P031_WINDOW_HEIGHT_DEF / (fse->index + 1); 458 fse->max_height = fse->min_height; 459 460 return 0; 461 } 462 463 static struct v4l2_mbus_framefmt * 464 __mt9p031_get_pad_format(struct mt9p031 *mt9p031, struct v4l2_subdev_fh *fh, 465 unsigned int pad, u32 which) 466 { 467 switch (which) { 468 case V4L2_SUBDEV_FORMAT_TRY: 469 return v4l2_subdev_get_try_format(fh, pad); 470 case V4L2_SUBDEV_FORMAT_ACTIVE: 471 return &mt9p031->format; 472 default: 473 return NULL; 474 } 475 } 476 477 static struct v4l2_rect * 478 __mt9p031_get_pad_crop(struct mt9p031 *mt9p031, struct v4l2_subdev_fh *fh, 479 unsigned int pad, u32 which) 480 { 481 switch (which) { 482 case V4L2_SUBDEV_FORMAT_TRY: 483 return v4l2_subdev_get_try_crop(fh, pad); 484 case V4L2_SUBDEV_FORMAT_ACTIVE: 485 return &mt9p031->crop; 486 default: 487 return NULL; 488 } 489 } 490 491 static int mt9p031_get_format(struct v4l2_subdev *subdev, 492 struct v4l2_subdev_fh *fh, 493 struct v4l2_subdev_format *fmt) 494 { 495 struct mt9p031 *mt9p031 = to_mt9p031(subdev); 496 497 fmt->format = *__mt9p031_get_pad_format(mt9p031, fh, fmt->pad, 498 fmt->which); 499 return 0; 500 } 501 502 static int mt9p031_set_format(struct v4l2_subdev *subdev, 503 struct v4l2_subdev_fh *fh, 504 struct v4l2_subdev_format *format) 505 { 506 struct mt9p031 *mt9p031 = to_mt9p031(subdev); 507 struct v4l2_mbus_framefmt *__format; 508 struct v4l2_rect *__crop; 509 unsigned int width; 510 unsigned int height; 511 unsigned int hratio; 512 unsigned int vratio; 513 514 __crop = __mt9p031_get_pad_crop(mt9p031, fh, format->pad, 515 format->which); 516 517 /* Clamp the width and height to avoid dividing by zero. */ 518 width = clamp_t(unsigned int, ALIGN(format->format.width, 2), 519 max(__crop->width / 7, MT9P031_WINDOW_WIDTH_MIN), 520 __crop->width); 521 height = clamp_t(unsigned int, ALIGN(format->format.height, 2), 522 max(__crop->height / 8, MT9P031_WINDOW_HEIGHT_MIN), 523 __crop->height); 524 525 hratio = DIV_ROUND_CLOSEST(__crop->width, width); 526 vratio = DIV_ROUND_CLOSEST(__crop->height, height); 527 528 __format = __mt9p031_get_pad_format(mt9p031, fh, format->pad, 529 format->which); 530 __format->width = __crop->width / hratio; 531 __format->height = __crop->height / vratio; 532 533 format->format = *__format; 534 535 return 0; 536 } 537 538 static int mt9p031_get_crop(struct v4l2_subdev *subdev, 539 struct v4l2_subdev_fh *fh, 540 struct v4l2_subdev_crop *crop) 541 { 542 struct mt9p031 *mt9p031 = to_mt9p031(subdev); 543 544 crop->rect = *__mt9p031_get_pad_crop(mt9p031, fh, crop->pad, 545 crop->which); 546 return 0; 547 } 548 549 static int mt9p031_set_crop(struct v4l2_subdev *subdev, 550 struct v4l2_subdev_fh *fh, 551 struct v4l2_subdev_crop *crop) 552 { 553 struct mt9p031 *mt9p031 = to_mt9p031(subdev); 554 struct v4l2_mbus_framefmt *__format; 555 struct v4l2_rect *__crop; 556 struct v4l2_rect rect; 557 558 /* Clamp the crop rectangle boundaries and align them to a multiple of 2 559 * pixels to ensure a GRBG Bayer pattern. 560 */ 561 rect.left = clamp(ALIGN(crop->rect.left, 2), MT9P031_COLUMN_START_MIN, 562 MT9P031_COLUMN_START_MAX); 563 rect.top = clamp(ALIGN(crop->rect.top, 2), MT9P031_ROW_START_MIN, 564 MT9P031_ROW_START_MAX); 565 rect.width = clamp(ALIGN(crop->rect.width, 2), 566 MT9P031_WINDOW_WIDTH_MIN, 567 MT9P031_WINDOW_WIDTH_MAX); 568 rect.height = clamp(ALIGN(crop->rect.height, 2), 569 MT9P031_WINDOW_HEIGHT_MIN, 570 MT9P031_WINDOW_HEIGHT_MAX); 571 572 rect.width = min(rect.width, MT9P031_PIXEL_ARRAY_WIDTH - rect.left); 573 rect.height = min(rect.height, MT9P031_PIXEL_ARRAY_HEIGHT - rect.top); 574 575 __crop = __mt9p031_get_pad_crop(mt9p031, fh, crop->pad, crop->which); 576 577 if (rect.width != __crop->width || rect.height != __crop->height) { 578 /* Reset the output image size if the crop rectangle size has 579 * been modified. 580 */ 581 __format = __mt9p031_get_pad_format(mt9p031, fh, crop->pad, 582 crop->which); 583 __format->width = rect.width; 584 __format->height = rect.height; 585 } 586 587 *__crop = rect; 588 crop->rect = rect; 589 590 return 0; 591 } 592 593 /* ----------------------------------------------------------------------------- 594 * V4L2 subdev control operations 595 */ 596 597 #define V4L2_CID_BLC_AUTO (V4L2_CID_USER_BASE | 0x1002) 598 #define V4L2_CID_BLC_TARGET_LEVEL (V4L2_CID_USER_BASE | 0x1003) 599 #define V4L2_CID_BLC_ANALOG_OFFSET (V4L2_CID_USER_BASE | 0x1004) 600 #define V4L2_CID_BLC_DIGITAL_OFFSET (V4L2_CID_USER_BASE | 0x1005) 601 602 static int mt9p031_s_ctrl(struct v4l2_ctrl *ctrl) 603 { 604 struct mt9p031 *mt9p031 = 605 container_of(ctrl->handler, struct mt9p031, ctrls); 606 struct i2c_client *client = v4l2_get_subdevdata(&mt9p031->subdev); 607 u16 data; 608 int ret; 609 610 switch (ctrl->id) { 611 case V4L2_CID_EXPOSURE: 612 ret = mt9p031_write(client, MT9P031_SHUTTER_WIDTH_UPPER, 613 (ctrl->val >> 16) & 0xffff); 614 if (ret < 0) 615 return ret; 616 617 return mt9p031_write(client, MT9P031_SHUTTER_WIDTH_LOWER, 618 ctrl->val & 0xffff); 619 620 case V4L2_CID_GAIN: 621 /* Gain is controlled by 2 analog stages and a digital stage. 622 * Valid values for the 3 stages are 623 * 624 * Stage Min Max Step 625 * ------------------------------------------ 626 * First analog stage x1 x2 1 627 * Second analog stage x1 x4 0.125 628 * Digital stage x1 x16 0.125 629 * 630 * To minimize noise, the gain stages should be used in the 631 * second analog stage, first analog stage, digital stage order. 632 * Gain from a previous stage should be pushed to its maximum 633 * value before the next stage is used. 634 */ 635 if (ctrl->val <= 32) { 636 data = ctrl->val; 637 } else if (ctrl->val <= 64) { 638 ctrl->val &= ~1; 639 data = (1 << 6) | (ctrl->val >> 1); 640 } else { 641 ctrl->val &= ~7; 642 data = ((ctrl->val - 64) << 5) | (1 << 6) | 32; 643 } 644 645 return mt9p031_write(client, MT9P031_GLOBAL_GAIN, data); 646 647 case V4L2_CID_HFLIP: 648 if (ctrl->val) 649 return mt9p031_set_mode2(mt9p031, 650 0, MT9P031_READ_MODE_2_COL_MIR); 651 else 652 return mt9p031_set_mode2(mt9p031, 653 MT9P031_READ_MODE_2_COL_MIR, 0); 654 655 case V4L2_CID_VFLIP: 656 if (ctrl->val) 657 return mt9p031_set_mode2(mt9p031, 658 0, MT9P031_READ_MODE_2_ROW_MIR); 659 else 660 return mt9p031_set_mode2(mt9p031, 661 MT9P031_READ_MODE_2_ROW_MIR, 0); 662 663 case V4L2_CID_TEST_PATTERN: 664 if (!ctrl->val) { 665 /* Restore the black level compensation settings. */ 666 if (mt9p031->blc_auto->cur.val != 0) { 667 ret = mt9p031_s_ctrl(mt9p031->blc_auto); 668 if (ret < 0) 669 return ret; 670 } 671 if (mt9p031->blc_offset->cur.val != 0) { 672 ret = mt9p031_s_ctrl(mt9p031->blc_offset); 673 if (ret < 0) 674 return ret; 675 } 676 return mt9p031_write(client, MT9P031_TEST_PATTERN, 677 MT9P031_TEST_PATTERN_DISABLE); 678 } 679 680 ret = mt9p031_write(client, MT9P031_TEST_PATTERN_GREEN, 0x05a0); 681 if (ret < 0) 682 return ret; 683 ret = mt9p031_write(client, MT9P031_TEST_PATTERN_RED, 0x0a50); 684 if (ret < 0) 685 return ret; 686 ret = mt9p031_write(client, MT9P031_TEST_PATTERN_BLUE, 0x0aa0); 687 if (ret < 0) 688 return ret; 689 690 /* Disable digital black level compensation when using a test 691 * pattern. 692 */ 693 ret = mt9p031_set_mode2(mt9p031, MT9P031_READ_MODE_2_ROW_BLC, 694 0); 695 if (ret < 0) 696 return ret; 697 698 ret = mt9p031_write(client, MT9P031_ROW_BLACK_DEF_OFFSET, 0); 699 if (ret < 0) 700 return ret; 701 702 return mt9p031_write(client, MT9P031_TEST_PATTERN, 703 ((ctrl->val - 1) << MT9P031_TEST_PATTERN_SHIFT) 704 | MT9P031_TEST_PATTERN_ENABLE); 705 706 case V4L2_CID_BLC_AUTO: 707 ret = mt9p031_set_mode2(mt9p031, 708 ctrl->val ? 0 : MT9P031_READ_MODE_2_ROW_BLC, 709 ctrl->val ? MT9P031_READ_MODE_2_ROW_BLC : 0); 710 if (ret < 0) 711 return ret; 712 713 return mt9p031_write(client, MT9P031_BLACK_LEVEL_CALIBRATION, 714 ctrl->val ? 0 : MT9P031_BLC_MANUAL_BLC); 715 716 case V4L2_CID_BLC_TARGET_LEVEL: 717 return mt9p031_write(client, MT9P031_ROW_BLACK_TARGET, 718 ctrl->val); 719 720 case V4L2_CID_BLC_ANALOG_OFFSET: 721 data = ctrl->val & ((1 << 9) - 1); 722 723 ret = mt9p031_write(client, MT9P031_GREEN1_OFFSET, data); 724 if (ret < 0) 725 return ret; 726 ret = mt9p031_write(client, MT9P031_GREEN2_OFFSET, data); 727 if (ret < 0) 728 return ret; 729 ret = mt9p031_write(client, MT9P031_RED_OFFSET, data); 730 if (ret < 0) 731 return ret; 732 return mt9p031_write(client, MT9P031_BLUE_OFFSET, data); 733 734 case V4L2_CID_BLC_DIGITAL_OFFSET: 735 return mt9p031_write(client, MT9P031_ROW_BLACK_DEF_OFFSET, 736 ctrl->val & ((1 << 12) - 1)); 737 } 738 739 return 0; 740 } 741 742 static struct v4l2_ctrl_ops mt9p031_ctrl_ops = { 743 .s_ctrl = mt9p031_s_ctrl, 744 }; 745 746 static const char * const mt9p031_test_pattern_menu[] = { 747 "Disabled", 748 "Color Field", 749 "Horizontal Gradient", 750 "Vertical Gradient", 751 "Diagonal Gradient", 752 "Classic Test Pattern", 753 "Walking 1s", 754 "Monochrome Horizontal Bars", 755 "Monochrome Vertical Bars", 756 "Vertical Color Bars", 757 }; 758 759 static const struct v4l2_ctrl_config mt9p031_ctrls[] = { 760 { 761 .ops = &mt9p031_ctrl_ops, 762 .id = V4L2_CID_BLC_AUTO, 763 .type = V4L2_CTRL_TYPE_BOOLEAN, 764 .name = "BLC, Auto", 765 .min = 0, 766 .max = 1, 767 .step = 1, 768 .def = 1, 769 .flags = 0, 770 }, { 771 .ops = &mt9p031_ctrl_ops, 772 .id = V4L2_CID_BLC_TARGET_LEVEL, 773 .type = V4L2_CTRL_TYPE_INTEGER, 774 .name = "BLC Target Level", 775 .min = 0, 776 .max = 4095, 777 .step = 1, 778 .def = 168, 779 .flags = 0, 780 }, { 781 .ops = &mt9p031_ctrl_ops, 782 .id = V4L2_CID_BLC_ANALOG_OFFSET, 783 .type = V4L2_CTRL_TYPE_INTEGER, 784 .name = "BLC Analog Offset", 785 .min = -255, 786 .max = 255, 787 .step = 1, 788 .def = 32, 789 .flags = 0, 790 }, { 791 .ops = &mt9p031_ctrl_ops, 792 .id = V4L2_CID_BLC_DIGITAL_OFFSET, 793 .type = V4L2_CTRL_TYPE_INTEGER, 794 .name = "BLC Digital Offset", 795 .min = -2048, 796 .max = 2047, 797 .step = 1, 798 .def = 40, 799 .flags = 0, 800 } 801 }; 802 803 /* ----------------------------------------------------------------------------- 804 * V4L2 subdev core operations 805 */ 806 807 static int mt9p031_set_power(struct v4l2_subdev *subdev, int on) 808 { 809 struct mt9p031 *mt9p031 = to_mt9p031(subdev); 810 int ret = 0; 811 812 mutex_lock(&mt9p031->power_lock); 813 814 /* If the power count is modified from 0 to != 0 or from != 0 to 0, 815 * update the power state. 816 */ 817 if (mt9p031->power_count == !on) { 818 ret = __mt9p031_set_power(mt9p031, !!on); 819 if (ret < 0) 820 goto out; 821 } 822 823 /* Update the power count. */ 824 mt9p031->power_count += on ? 1 : -1; 825 WARN_ON(mt9p031->power_count < 0); 826 827 out: 828 mutex_unlock(&mt9p031->power_lock); 829 return ret; 830 } 831 832 /* ----------------------------------------------------------------------------- 833 * V4L2 subdev internal operations 834 */ 835 836 static int mt9p031_registered(struct v4l2_subdev *subdev) 837 { 838 struct i2c_client *client = v4l2_get_subdevdata(subdev); 839 struct mt9p031 *mt9p031 = to_mt9p031(subdev); 840 s32 data; 841 int ret; 842 843 ret = mt9p031_power_on(mt9p031); 844 if (ret < 0) { 845 dev_err(&client->dev, "MT9P031 power up failed\n"); 846 return ret; 847 } 848 849 /* Read out the chip version register */ 850 data = mt9p031_read(client, MT9P031_CHIP_VERSION); 851 mt9p031_power_off(mt9p031); 852 853 if (data != MT9P031_CHIP_VERSION_VALUE) { 854 dev_err(&client->dev, "MT9P031 not detected, wrong version " 855 "0x%04x\n", data); 856 return -ENODEV; 857 } 858 859 dev_info(&client->dev, "MT9P031 detected at address 0x%02x\n", 860 client->addr); 861 862 return 0; 863 } 864 865 static int mt9p031_open(struct v4l2_subdev *subdev, struct v4l2_subdev_fh *fh) 866 { 867 struct mt9p031 *mt9p031 = to_mt9p031(subdev); 868 struct v4l2_mbus_framefmt *format; 869 struct v4l2_rect *crop; 870 871 crop = v4l2_subdev_get_try_crop(fh, 0); 872 crop->left = MT9P031_COLUMN_START_DEF; 873 crop->top = MT9P031_ROW_START_DEF; 874 crop->width = MT9P031_WINDOW_WIDTH_DEF; 875 crop->height = MT9P031_WINDOW_HEIGHT_DEF; 876 877 format = v4l2_subdev_get_try_format(fh, 0); 878 879 if (mt9p031->model == MT9P031_MODEL_MONOCHROME) 880 format->code = V4L2_MBUS_FMT_Y12_1X12; 881 else 882 format->code = V4L2_MBUS_FMT_SGRBG12_1X12; 883 884 format->width = MT9P031_WINDOW_WIDTH_DEF; 885 format->height = MT9P031_WINDOW_HEIGHT_DEF; 886 format->field = V4L2_FIELD_NONE; 887 format->colorspace = V4L2_COLORSPACE_SRGB; 888 889 return mt9p031_set_power(subdev, 1); 890 } 891 892 static int mt9p031_close(struct v4l2_subdev *subdev, struct v4l2_subdev_fh *fh) 893 { 894 return mt9p031_set_power(subdev, 0); 895 } 896 897 static struct v4l2_subdev_core_ops mt9p031_subdev_core_ops = { 898 .s_power = mt9p031_set_power, 899 }; 900 901 static struct v4l2_subdev_video_ops mt9p031_subdev_video_ops = { 902 .s_stream = mt9p031_s_stream, 903 }; 904 905 static struct v4l2_subdev_pad_ops mt9p031_subdev_pad_ops = { 906 .enum_mbus_code = mt9p031_enum_mbus_code, 907 .enum_frame_size = mt9p031_enum_frame_size, 908 .get_fmt = mt9p031_get_format, 909 .set_fmt = mt9p031_set_format, 910 .get_crop = mt9p031_get_crop, 911 .set_crop = mt9p031_set_crop, 912 }; 913 914 static struct v4l2_subdev_ops mt9p031_subdev_ops = { 915 .core = &mt9p031_subdev_core_ops, 916 .video = &mt9p031_subdev_video_ops, 917 .pad = &mt9p031_subdev_pad_ops, 918 }; 919 920 static const struct v4l2_subdev_internal_ops mt9p031_subdev_internal_ops = { 921 .registered = mt9p031_registered, 922 .open = mt9p031_open, 923 .close = mt9p031_close, 924 }; 925 926 /* ----------------------------------------------------------------------------- 927 * Driver initialization and probing 928 */ 929 930 static int mt9p031_probe(struct i2c_client *client, 931 const struct i2c_device_id *did) 932 { 933 struct mt9p031_platform_data *pdata = client->dev.platform_data; 934 struct i2c_adapter *adapter = to_i2c_adapter(client->dev.parent); 935 struct mt9p031 *mt9p031; 936 unsigned int i; 937 int ret; 938 939 if (pdata == NULL) { 940 dev_err(&client->dev, "No platform data\n"); 941 return -EINVAL; 942 } 943 944 if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_WORD_DATA)) { 945 dev_warn(&client->dev, 946 "I2C-Adapter doesn't support I2C_FUNC_SMBUS_WORD\n"); 947 return -EIO; 948 } 949 950 mt9p031 = devm_kzalloc(&client->dev, sizeof(*mt9p031), GFP_KERNEL); 951 if (mt9p031 == NULL) 952 return -ENOMEM; 953 954 mt9p031->pdata = pdata; 955 mt9p031->output_control = MT9P031_OUTPUT_CONTROL_DEF; 956 mt9p031->mode2 = MT9P031_READ_MODE_2_ROW_BLC; 957 mt9p031->model = did->driver_data; 958 mt9p031->reset = -1; 959 960 mt9p031->vaa = devm_regulator_get(&client->dev, "vaa"); 961 mt9p031->vdd = devm_regulator_get(&client->dev, "vdd"); 962 mt9p031->vdd_io = devm_regulator_get(&client->dev, "vdd_io"); 963 964 if (IS_ERR(mt9p031->vaa) || IS_ERR(mt9p031->vdd) || 965 IS_ERR(mt9p031->vdd_io)) { 966 dev_err(&client->dev, "Unable to get regulators\n"); 967 return -ENODEV; 968 } 969 970 v4l2_ctrl_handler_init(&mt9p031->ctrls, ARRAY_SIZE(mt9p031_ctrls) + 6); 971 972 v4l2_ctrl_new_std(&mt9p031->ctrls, &mt9p031_ctrl_ops, 973 V4L2_CID_EXPOSURE, MT9P031_SHUTTER_WIDTH_MIN, 974 MT9P031_SHUTTER_WIDTH_MAX, 1, 975 MT9P031_SHUTTER_WIDTH_DEF); 976 v4l2_ctrl_new_std(&mt9p031->ctrls, &mt9p031_ctrl_ops, 977 V4L2_CID_GAIN, MT9P031_GLOBAL_GAIN_MIN, 978 MT9P031_GLOBAL_GAIN_MAX, 1, MT9P031_GLOBAL_GAIN_DEF); 979 v4l2_ctrl_new_std(&mt9p031->ctrls, &mt9p031_ctrl_ops, 980 V4L2_CID_HFLIP, 0, 1, 1, 0); 981 v4l2_ctrl_new_std(&mt9p031->ctrls, &mt9p031_ctrl_ops, 982 V4L2_CID_VFLIP, 0, 1, 1, 0); 983 v4l2_ctrl_new_std(&mt9p031->ctrls, &mt9p031_ctrl_ops, 984 V4L2_CID_PIXEL_RATE, pdata->target_freq, 985 pdata->target_freq, 1, pdata->target_freq); 986 v4l2_ctrl_new_std_menu_items(&mt9p031->ctrls, &mt9p031_ctrl_ops, 987 V4L2_CID_TEST_PATTERN, 988 ARRAY_SIZE(mt9p031_test_pattern_menu) - 1, 0, 989 0, mt9p031_test_pattern_menu); 990 991 for (i = 0; i < ARRAY_SIZE(mt9p031_ctrls); ++i) 992 v4l2_ctrl_new_custom(&mt9p031->ctrls, &mt9p031_ctrls[i], NULL); 993 994 mt9p031->subdev.ctrl_handler = &mt9p031->ctrls; 995 996 if (mt9p031->ctrls.error) { 997 printk(KERN_INFO "%s: control initialization error %d\n", 998 __func__, mt9p031->ctrls.error); 999 ret = mt9p031->ctrls.error; 1000 goto done; 1001 } 1002 1003 mt9p031->blc_auto = v4l2_ctrl_find(&mt9p031->ctrls, V4L2_CID_BLC_AUTO); 1004 mt9p031->blc_offset = v4l2_ctrl_find(&mt9p031->ctrls, 1005 V4L2_CID_BLC_DIGITAL_OFFSET); 1006 1007 mutex_init(&mt9p031->power_lock); 1008 v4l2_i2c_subdev_init(&mt9p031->subdev, client, &mt9p031_subdev_ops); 1009 mt9p031->subdev.internal_ops = &mt9p031_subdev_internal_ops; 1010 1011 mt9p031->pad.flags = MEDIA_PAD_FL_SOURCE; 1012 ret = media_entity_init(&mt9p031->subdev.entity, 1, &mt9p031->pad, 0); 1013 if (ret < 0) 1014 goto done; 1015 1016 mt9p031->subdev.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; 1017 1018 mt9p031->crop.width = MT9P031_WINDOW_WIDTH_DEF; 1019 mt9p031->crop.height = MT9P031_WINDOW_HEIGHT_DEF; 1020 mt9p031->crop.left = MT9P031_COLUMN_START_DEF; 1021 mt9p031->crop.top = MT9P031_ROW_START_DEF; 1022 1023 if (mt9p031->model == MT9P031_MODEL_MONOCHROME) 1024 mt9p031->format.code = V4L2_MBUS_FMT_Y12_1X12; 1025 else 1026 mt9p031->format.code = V4L2_MBUS_FMT_SGRBG12_1X12; 1027 1028 mt9p031->format.width = MT9P031_WINDOW_WIDTH_DEF; 1029 mt9p031->format.height = MT9P031_WINDOW_HEIGHT_DEF; 1030 mt9p031->format.field = V4L2_FIELD_NONE; 1031 mt9p031->format.colorspace = V4L2_COLORSPACE_SRGB; 1032 1033 if (gpio_is_valid(pdata->reset)) { 1034 ret = devm_gpio_request_one(&client->dev, pdata->reset, 1035 GPIOF_OUT_INIT_LOW, "mt9p031_rst"); 1036 if (ret < 0) 1037 goto done; 1038 1039 mt9p031->reset = pdata->reset; 1040 } 1041 1042 ret = mt9p031_clk_setup(mt9p031); 1043 1044 done: 1045 if (ret < 0) { 1046 v4l2_ctrl_handler_free(&mt9p031->ctrls); 1047 media_entity_cleanup(&mt9p031->subdev.entity); 1048 } 1049 1050 return ret; 1051 } 1052 1053 static int mt9p031_remove(struct i2c_client *client) 1054 { 1055 struct v4l2_subdev *subdev = i2c_get_clientdata(client); 1056 struct mt9p031 *mt9p031 = to_mt9p031(subdev); 1057 1058 v4l2_ctrl_handler_free(&mt9p031->ctrls); 1059 v4l2_device_unregister_subdev(subdev); 1060 media_entity_cleanup(&subdev->entity); 1061 1062 return 0; 1063 } 1064 1065 static const struct i2c_device_id mt9p031_id[] = { 1066 { "mt9p031", MT9P031_MODEL_COLOR }, 1067 { "mt9p031m", MT9P031_MODEL_MONOCHROME }, 1068 { } 1069 }; 1070 MODULE_DEVICE_TABLE(i2c, mt9p031_id); 1071 1072 static struct i2c_driver mt9p031_i2c_driver = { 1073 .driver = { 1074 .name = "mt9p031", 1075 }, 1076 .probe = mt9p031_probe, 1077 .remove = mt9p031_remove, 1078 .id_table = mt9p031_id, 1079 }; 1080 1081 module_i2c_driver(mt9p031_i2c_driver); 1082 1083 MODULE_DESCRIPTION("Aptina MT9P031 Camera driver"); 1084 MODULE_AUTHOR("Bastian Hecht <hechtb@gmail.com>"); 1085 MODULE_LICENSE("GPL v2"); 1086