1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Driver for MT9P031 CMOS Image Sensor from Aptina 4 * 5 * Copyright (C) 2011, Laurent Pinchart <laurent.pinchart@ideasonboard.com> 6 * Copyright (C) 2011, Javier Martin <javier.martin@vista-silicon.com> 7 * Copyright (C) 2011, Guennadi Liakhovetski <g.liakhovetski@gmx.de> 8 * 9 * Based on the MT9V032 driver and Bastian Hecht's code. 10 */ 11 12 #include <linux/clk.h> 13 #include <linux/delay.h> 14 #include <linux/device.h> 15 #include <linux/gpio/consumer.h> 16 #include <linux/i2c.h> 17 #include <linux/log2.h> 18 #include <linux/module.h> 19 #include <linux/of.h> 20 #include <linux/of_graph.h> 21 #include <linux/pm.h> 22 #include <linux/regulator/consumer.h> 23 #include <linux/slab.h> 24 #include <linux/videodev2.h> 25 26 #include <media/i2c/mt9p031.h> 27 #include <media/v4l2-async.h> 28 #include <media/v4l2-ctrls.h> 29 #include <media/v4l2-device.h> 30 #include <media/v4l2-fwnode.h> 31 #include <media/v4l2-subdev.h> 32 33 #include "aptina-pll.h" 34 35 #define MT9P031_PIXEL_ARRAY_WIDTH 2752 36 #define MT9P031_PIXEL_ARRAY_HEIGHT 2004 37 38 #define MT9P031_CHIP_VERSION 0x00 39 #define MT9P031_CHIP_VERSION_VALUE 0x1801 40 #define MT9P031_ROW_START 0x01 41 #define MT9P031_ROW_START_MIN 0 42 #define MT9P031_ROW_START_MAX 2004 43 #define MT9P031_ROW_START_DEF 54 44 #define MT9P031_COLUMN_START 0x02 45 #define MT9P031_COLUMN_START_MIN 0 46 #define MT9P031_COLUMN_START_MAX 2750 47 #define MT9P031_COLUMN_START_DEF 16 48 #define MT9P031_WINDOW_HEIGHT 0x03 49 #define MT9P031_WINDOW_HEIGHT_MIN 2 50 #define MT9P031_WINDOW_HEIGHT_MAX 2006 51 #define MT9P031_WINDOW_HEIGHT_DEF 1944 52 #define MT9P031_WINDOW_WIDTH 0x04 53 #define MT9P031_WINDOW_WIDTH_MIN 2 54 #define MT9P031_WINDOW_WIDTH_MAX 2752 55 #define MT9P031_WINDOW_WIDTH_DEF 2592 56 #define MT9P031_HORIZONTAL_BLANK 0x05 57 #define MT9P031_HORIZONTAL_BLANK_MIN 0 58 #define MT9P031_HORIZONTAL_BLANK_MAX 4095 59 #define MT9P031_VERTICAL_BLANK 0x06 60 #define MT9P031_VERTICAL_BLANK_MIN 1 61 #define MT9P031_VERTICAL_BLANK_MAX 4096 62 #define MT9P031_VERTICAL_BLANK_DEF 26 63 #define MT9P031_OUTPUT_CONTROL 0x07 64 #define MT9P031_OUTPUT_CONTROL_CEN 2 65 #define MT9P031_OUTPUT_CONTROL_SYN 1 66 #define MT9P031_OUTPUT_CONTROL_DEF 0x1f82 67 #define MT9P031_SHUTTER_WIDTH_UPPER 0x08 68 #define MT9P031_SHUTTER_WIDTH_LOWER 0x09 69 #define MT9P031_SHUTTER_WIDTH_MIN 1 70 #define MT9P031_SHUTTER_WIDTH_MAX 1048575 71 #define MT9P031_SHUTTER_WIDTH_DEF 1943 72 #define MT9P031_PLL_CONTROL 0x10 73 #define MT9P031_PLL_CONTROL_PWROFF 0x0050 74 #define MT9P031_PLL_CONTROL_PWRON 0x0051 75 #define MT9P031_PLL_CONTROL_USEPLL 0x0052 76 #define MT9P031_PLL_CONFIG_1 0x11 77 #define MT9P031_PLL_CONFIG_2 0x12 78 #define MT9P031_PIXEL_CLOCK_CONTROL 0x0a 79 #define MT9P031_PIXEL_CLOCK_INVERT (1 << 15) 80 #define MT9P031_PIXEL_CLOCK_SHIFT(n) ((n) << 8) 81 #define MT9P031_PIXEL_CLOCK_DIVIDE(n) ((n) << 0) 82 #define MT9P031_FRAME_RESTART 0x0b 83 #define MT9P031_SHUTTER_DELAY 0x0c 84 #define MT9P031_RST 0x0d 85 #define MT9P031_RST_ENABLE 1 86 #define MT9P031_RST_DISABLE 0 87 #define MT9P031_READ_MODE_1 0x1e 88 #define MT9P031_READ_MODE_2 0x20 89 #define MT9P031_READ_MODE_2_ROW_MIR (1 << 15) 90 #define MT9P031_READ_MODE_2_COL_MIR (1 << 14) 91 #define MT9P031_READ_MODE_2_ROW_BLC (1 << 6) 92 #define MT9P031_ROW_ADDRESS_MODE 0x22 93 #define MT9P031_COLUMN_ADDRESS_MODE 0x23 94 #define MT9P031_GLOBAL_GAIN 0x35 95 #define MT9P031_GLOBAL_GAIN_MIN 8 96 #define MT9P031_GLOBAL_GAIN_MAX 1024 97 #define MT9P031_GLOBAL_GAIN_DEF 8 98 #define MT9P031_GLOBAL_GAIN_MULT (1 << 6) 99 #define MT9P031_ROW_BLACK_TARGET 0x49 100 #define MT9P031_ROW_BLACK_DEF_OFFSET 0x4b 101 #define MT9P031_GREEN1_OFFSET 0x60 102 #define MT9P031_GREEN2_OFFSET 0x61 103 #define MT9P031_BLACK_LEVEL_CALIBRATION 0x62 104 #define MT9P031_BLC_MANUAL_BLC (1 << 0) 105 #define MT9P031_RED_OFFSET 0x63 106 #define MT9P031_BLUE_OFFSET 0x64 107 #define MT9P031_TEST_PATTERN 0xa0 108 #define MT9P031_TEST_PATTERN_SHIFT 3 109 #define MT9P031_TEST_PATTERN_ENABLE (1 << 0) 110 #define MT9P031_TEST_PATTERN_DISABLE (0 << 0) 111 #define MT9P031_TEST_PATTERN_GREEN 0xa1 112 #define MT9P031_TEST_PATTERN_RED 0xa2 113 #define MT9P031_TEST_PATTERN_BLUE 0xa3 114 115 enum mt9p031_model { 116 MT9P031_MODEL_COLOR, 117 MT9P031_MODEL_MONOCHROME, 118 }; 119 120 struct mt9p031 { 121 struct v4l2_subdev subdev; 122 struct media_pad pad; 123 struct v4l2_rect crop; /* Sensor window */ 124 struct v4l2_mbus_framefmt format; 125 struct mt9p031_platform_data *pdata; 126 struct mutex power_lock; /* lock to protect power_count */ 127 int power_count; 128 129 struct clk *clk; 130 struct regulator_bulk_data regulators[3]; 131 132 enum mt9p031_model model; 133 struct aptina_pll pll; 134 unsigned int clk_div; 135 bool use_pll; 136 struct gpio_desc *reset; 137 138 struct v4l2_ctrl_handler ctrls; 139 struct v4l2_ctrl *blc_auto; 140 struct v4l2_ctrl *blc_offset; 141 142 /* Registers cache */ 143 u16 output_control; 144 u16 mode2; 145 }; 146 147 static struct mt9p031 *to_mt9p031(struct v4l2_subdev *sd) 148 { 149 return container_of(sd, struct mt9p031, subdev); 150 } 151 152 static int mt9p031_read(struct i2c_client *client, u8 reg) 153 { 154 return i2c_smbus_read_word_swapped(client, reg); 155 } 156 157 static int mt9p031_write(struct i2c_client *client, u8 reg, u16 data) 158 { 159 return i2c_smbus_write_word_swapped(client, reg, data); 160 } 161 162 static int mt9p031_set_output_control(struct mt9p031 *mt9p031, u16 clear, 163 u16 set) 164 { 165 struct i2c_client *client = v4l2_get_subdevdata(&mt9p031->subdev); 166 u16 value = (mt9p031->output_control & ~clear) | set; 167 int ret; 168 169 ret = mt9p031_write(client, MT9P031_OUTPUT_CONTROL, value); 170 if (ret < 0) 171 return ret; 172 173 mt9p031->output_control = value; 174 return 0; 175 } 176 177 static int mt9p031_set_mode2(struct mt9p031 *mt9p031, u16 clear, u16 set) 178 { 179 struct i2c_client *client = v4l2_get_subdevdata(&mt9p031->subdev); 180 u16 value = (mt9p031->mode2 & ~clear) | set; 181 int ret; 182 183 ret = mt9p031_write(client, MT9P031_READ_MODE_2, value); 184 if (ret < 0) 185 return ret; 186 187 mt9p031->mode2 = value; 188 return 0; 189 } 190 191 static int mt9p031_reset(struct mt9p031 *mt9p031) 192 { 193 struct i2c_client *client = v4l2_get_subdevdata(&mt9p031->subdev); 194 int ret; 195 196 /* Disable chip output, synchronous option update */ 197 ret = mt9p031_write(client, MT9P031_RST, MT9P031_RST_ENABLE); 198 if (ret < 0) 199 return ret; 200 ret = mt9p031_write(client, MT9P031_RST, MT9P031_RST_DISABLE); 201 if (ret < 0) 202 return ret; 203 204 ret = mt9p031_write(client, MT9P031_PIXEL_CLOCK_CONTROL, 205 MT9P031_PIXEL_CLOCK_DIVIDE(mt9p031->clk_div)); 206 if (ret < 0) 207 return ret; 208 209 return mt9p031_set_output_control(mt9p031, MT9P031_OUTPUT_CONTROL_CEN, 210 0); 211 } 212 213 static int mt9p031_clk_setup(struct mt9p031 *mt9p031) 214 { 215 static const struct aptina_pll_limits limits = { 216 .ext_clock_min = 6000000, 217 .ext_clock_max = 27000000, 218 .int_clock_min = 2000000, 219 .int_clock_max = 13500000, 220 .out_clock_min = 180000000, 221 .out_clock_max = 360000000, 222 .pix_clock_max = 96000000, 223 .n_min = 1, 224 .n_max = 64, 225 .m_min = 16, 226 .m_max = 255, 227 .p1_min = 1, 228 .p1_max = 128, 229 }; 230 231 struct i2c_client *client = v4l2_get_subdevdata(&mt9p031->subdev); 232 struct mt9p031_platform_data *pdata = mt9p031->pdata; 233 unsigned long ext_freq; 234 int ret; 235 236 mt9p031->clk = devm_clk_get(&client->dev, NULL); 237 if (IS_ERR(mt9p031->clk)) 238 return PTR_ERR(mt9p031->clk); 239 240 ret = clk_set_rate(mt9p031->clk, pdata->ext_freq); 241 if (ret < 0) 242 return ret; 243 244 ext_freq = clk_get_rate(mt9p031->clk); 245 246 /* If the external clock frequency is out of bounds for the PLL use the 247 * pixel clock divider only and disable the PLL. 248 */ 249 if (ext_freq > limits.ext_clock_max) { 250 unsigned int div; 251 252 div = DIV_ROUND_UP(ext_freq, pdata->target_freq); 253 div = roundup_pow_of_two(div) / 2; 254 255 mt9p031->clk_div = min_t(unsigned int, div, 64); 256 mt9p031->use_pll = false; 257 258 return 0; 259 } 260 261 mt9p031->pll.ext_clock = ext_freq; 262 mt9p031->pll.pix_clock = pdata->target_freq; 263 mt9p031->use_pll = true; 264 265 return aptina_pll_calculate(&client->dev, &limits, &mt9p031->pll); 266 } 267 268 static int mt9p031_pll_enable(struct mt9p031 *mt9p031) 269 { 270 struct i2c_client *client = v4l2_get_subdevdata(&mt9p031->subdev); 271 int ret; 272 273 if (!mt9p031->use_pll) 274 return 0; 275 276 ret = mt9p031_write(client, MT9P031_PLL_CONTROL, 277 MT9P031_PLL_CONTROL_PWRON); 278 if (ret < 0) 279 return ret; 280 281 ret = mt9p031_write(client, MT9P031_PLL_CONFIG_1, 282 (mt9p031->pll.m << 8) | (mt9p031->pll.n - 1)); 283 if (ret < 0) 284 return ret; 285 286 ret = mt9p031_write(client, MT9P031_PLL_CONFIG_2, mt9p031->pll.p1 - 1); 287 if (ret < 0) 288 return ret; 289 290 usleep_range(1000, 2000); 291 ret = mt9p031_write(client, MT9P031_PLL_CONTROL, 292 MT9P031_PLL_CONTROL_PWRON | 293 MT9P031_PLL_CONTROL_USEPLL); 294 return ret; 295 } 296 297 static inline int mt9p031_pll_disable(struct mt9p031 *mt9p031) 298 { 299 struct i2c_client *client = v4l2_get_subdevdata(&mt9p031->subdev); 300 301 if (!mt9p031->use_pll) 302 return 0; 303 304 return mt9p031_write(client, MT9P031_PLL_CONTROL, 305 MT9P031_PLL_CONTROL_PWROFF); 306 } 307 308 static int mt9p031_power_on(struct mt9p031 *mt9p031) 309 { 310 int ret; 311 312 /* Ensure RESET_BAR is active */ 313 if (mt9p031->reset) { 314 gpiod_set_value(mt9p031->reset, 1); 315 usleep_range(1000, 2000); 316 } 317 318 /* Bring up the supplies */ 319 ret = regulator_bulk_enable(ARRAY_SIZE(mt9p031->regulators), 320 mt9p031->regulators); 321 if (ret < 0) 322 return ret; 323 324 /* Enable clock */ 325 if (mt9p031->clk) { 326 ret = clk_prepare_enable(mt9p031->clk); 327 if (ret) { 328 regulator_bulk_disable(ARRAY_SIZE(mt9p031->regulators), 329 mt9p031->regulators); 330 return ret; 331 } 332 } 333 334 /* Now RESET_BAR must be high */ 335 if (mt9p031->reset) { 336 gpiod_set_value(mt9p031->reset, 0); 337 usleep_range(1000, 2000); 338 } 339 340 return 0; 341 } 342 343 static void mt9p031_power_off(struct mt9p031 *mt9p031) 344 { 345 if (mt9p031->reset) { 346 gpiod_set_value(mt9p031->reset, 1); 347 usleep_range(1000, 2000); 348 } 349 350 regulator_bulk_disable(ARRAY_SIZE(mt9p031->regulators), 351 mt9p031->regulators); 352 353 clk_disable_unprepare(mt9p031->clk); 354 } 355 356 static int __mt9p031_set_power(struct mt9p031 *mt9p031, bool on) 357 { 358 struct i2c_client *client = v4l2_get_subdevdata(&mt9p031->subdev); 359 int ret; 360 361 if (!on) { 362 mt9p031_power_off(mt9p031); 363 return 0; 364 } 365 366 ret = mt9p031_power_on(mt9p031); 367 if (ret < 0) 368 return ret; 369 370 ret = mt9p031_reset(mt9p031); 371 if (ret < 0) { 372 dev_err(&client->dev, "Failed to reset the camera\n"); 373 return ret; 374 } 375 376 /* Configure the pixel clock polarity */ 377 if (mt9p031->pdata && mt9p031->pdata->pixclk_pol) { 378 ret = mt9p031_write(client, MT9P031_PIXEL_CLOCK_CONTROL, 379 MT9P031_PIXEL_CLOCK_INVERT); 380 if (ret < 0) 381 return ret; 382 } 383 384 return v4l2_ctrl_handler_setup(&mt9p031->ctrls); 385 } 386 387 /* ----------------------------------------------------------------------------- 388 * V4L2 subdev video operations 389 */ 390 391 static int mt9p031_set_params(struct mt9p031 *mt9p031) 392 { 393 struct i2c_client *client = v4l2_get_subdevdata(&mt9p031->subdev); 394 struct v4l2_mbus_framefmt *format = &mt9p031->format; 395 const struct v4l2_rect *crop = &mt9p031->crop; 396 unsigned int hblank; 397 unsigned int vblank; 398 unsigned int xskip; 399 unsigned int yskip; 400 unsigned int xbin; 401 unsigned int ybin; 402 int ret; 403 404 /* Windows position and size. 405 * 406 * TODO: Make sure the start coordinates and window size match the 407 * skipping, binning and mirroring (see description of registers 2 and 4 408 * in table 13, and Binning section on page 41). 409 */ 410 ret = mt9p031_write(client, MT9P031_COLUMN_START, crop->left); 411 if (ret < 0) 412 return ret; 413 ret = mt9p031_write(client, MT9P031_ROW_START, crop->top); 414 if (ret < 0) 415 return ret; 416 ret = mt9p031_write(client, MT9P031_WINDOW_WIDTH, crop->width - 1); 417 if (ret < 0) 418 return ret; 419 ret = mt9p031_write(client, MT9P031_WINDOW_HEIGHT, crop->height - 1); 420 if (ret < 0) 421 return ret; 422 423 /* Row and column binning and skipping. Use the maximum binning value 424 * compatible with the skipping settings. 425 */ 426 xskip = DIV_ROUND_CLOSEST(crop->width, format->width); 427 yskip = DIV_ROUND_CLOSEST(crop->height, format->height); 428 xbin = 1 << (ffs(xskip) - 1); 429 ybin = 1 << (ffs(yskip) - 1); 430 431 ret = mt9p031_write(client, MT9P031_COLUMN_ADDRESS_MODE, 432 ((xbin - 1) << 4) | (xskip - 1)); 433 if (ret < 0) 434 return ret; 435 ret = mt9p031_write(client, MT9P031_ROW_ADDRESS_MODE, 436 ((ybin - 1) << 4) | (yskip - 1)); 437 if (ret < 0) 438 return ret; 439 440 /* Blanking - use minimum value for horizontal blanking and default 441 * value for vertical blanking. 442 */ 443 hblank = 346 * ybin + 64 + (80 >> min_t(unsigned int, xbin, 3)); 444 vblank = MT9P031_VERTICAL_BLANK_DEF; 445 446 ret = mt9p031_write(client, MT9P031_HORIZONTAL_BLANK, hblank - 1); 447 if (ret < 0) 448 return ret; 449 ret = mt9p031_write(client, MT9P031_VERTICAL_BLANK, vblank - 1); 450 if (ret < 0) 451 return ret; 452 453 return ret; 454 } 455 456 static int mt9p031_s_stream(struct v4l2_subdev *subdev, int enable) 457 { 458 struct mt9p031 *mt9p031 = to_mt9p031(subdev); 459 int ret; 460 461 if (!enable) { 462 /* Stop sensor readout */ 463 ret = mt9p031_set_output_control(mt9p031, 464 MT9P031_OUTPUT_CONTROL_CEN, 0); 465 if (ret < 0) 466 return ret; 467 468 return mt9p031_pll_disable(mt9p031); 469 } 470 471 ret = mt9p031_set_params(mt9p031); 472 if (ret < 0) 473 return ret; 474 475 /* Switch to master "normal" mode */ 476 ret = mt9p031_set_output_control(mt9p031, 0, 477 MT9P031_OUTPUT_CONTROL_CEN); 478 if (ret < 0) 479 return ret; 480 481 return mt9p031_pll_enable(mt9p031); 482 } 483 484 static int mt9p031_enum_mbus_code(struct v4l2_subdev *subdev, 485 struct v4l2_subdev_state *sd_state, 486 struct v4l2_subdev_mbus_code_enum *code) 487 { 488 struct mt9p031 *mt9p031 = to_mt9p031(subdev); 489 490 if (code->pad || code->index) 491 return -EINVAL; 492 493 code->code = mt9p031->format.code; 494 return 0; 495 } 496 497 static int mt9p031_enum_frame_size(struct v4l2_subdev *subdev, 498 struct v4l2_subdev_state *sd_state, 499 struct v4l2_subdev_frame_size_enum *fse) 500 { 501 struct mt9p031 *mt9p031 = to_mt9p031(subdev); 502 503 if (fse->index >= 8 || fse->code != mt9p031->format.code) 504 return -EINVAL; 505 506 fse->min_width = MT9P031_WINDOW_WIDTH_DEF 507 / min_t(unsigned int, 7, fse->index + 1); 508 fse->max_width = fse->min_width; 509 fse->min_height = MT9P031_WINDOW_HEIGHT_DEF / (fse->index + 1); 510 fse->max_height = fse->min_height; 511 512 return 0; 513 } 514 515 static struct v4l2_mbus_framefmt * 516 __mt9p031_get_pad_format(struct mt9p031 *mt9p031, 517 struct v4l2_subdev_state *sd_state, 518 unsigned int pad, u32 which) 519 { 520 switch (which) { 521 case V4L2_SUBDEV_FORMAT_TRY: 522 return v4l2_subdev_get_try_format(&mt9p031->subdev, sd_state, 523 pad); 524 case V4L2_SUBDEV_FORMAT_ACTIVE: 525 return &mt9p031->format; 526 default: 527 return NULL; 528 } 529 } 530 531 static struct v4l2_rect * 532 __mt9p031_get_pad_crop(struct mt9p031 *mt9p031, 533 struct v4l2_subdev_state *sd_state, 534 unsigned int pad, u32 which) 535 { 536 switch (which) { 537 case V4L2_SUBDEV_FORMAT_TRY: 538 return v4l2_subdev_get_try_crop(&mt9p031->subdev, sd_state, 539 pad); 540 case V4L2_SUBDEV_FORMAT_ACTIVE: 541 return &mt9p031->crop; 542 default: 543 return NULL; 544 } 545 } 546 547 static int mt9p031_get_format(struct v4l2_subdev *subdev, 548 struct v4l2_subdev_state *sd_state, 549 struct v4l2_subdev_format *fmt) 550 { 551 struct mt9p031 *mt9p031 = to_mt9p031(subdev); 552 553 fmt->format = *__mt9p031_get_pad_format(mt9p031, sd_state, fmt->pad, 554 fmt->which); 555 return 0; 556 } 557 558 static int mt9p031_set_format(struct v4l2_subdev *subdev, 559 struct v4l2_subdev_state *sd_state, 560 struct v4l2_subdev_format *format) 561 { 562 struct mt9p031 *mt9p031 = to_mt9p031(subdev); 563 struct v4l2_mbus_framefmt *__format; 564 struct v4l2_rect *__crop; 565 unsigned int width; 566 unsigned int height; 567 unsigned int hratio; 568 unsigned int vratio; 569 570 __crop = __mt9p031_get_pad_crop(mt9p031, sd_state, format->pad, 571 format->which); 572 573 /* Clamp the width and height to avoid dividing by zero. */ 574 width = clamp_t(unsigned int, ALIGN(format->format.width, 2), 575 max_t(unsigned int, __crop->width / 7, 576 MT9P031_WINDOW_WIDTH_MIN), 577 __crop->width); 578 height = clamp_t(unsigned int, ALIGN(format->format.height, 2), 579 max_t(unsigned int, __crop->height / 8, 580 MT9P031_WINDOW_HEIGHT_MIN), 581 __crop->height); 582 583 hratio = DIV_ROUND_CLOSEST(__crop->width, width); 584 vratio = DIV_ROUND_CLOSEST(__crop->height, height); 585 586 __format = __mt9p031_get_pad_format(mt9p031, sd_state, format->pad, 587 format->which); 588 __format->width = __crop->width / hratio; 589 __format->height = __crop->height / vratio; 590 591 format->format = *__format; 592 593 return 0; 594 } 595 596 static int mt9p031_get_selection(struct v4l2_subdev *subdev, 597 struct v4l2_subdev_state *sd_state, 598 struct v4l2_subdev_selection *sel) 599 { 600 struct mt9p031 *mt9p031 = to_mt9p031(subdev); 601 602 if (sel->target != V4L2_SEL_TGT_CROP) 603 return -EINVAL; 604 605 sel->r = *__mt9p031_get_pad_crop(mt9p031, sd_state, sel->pad, 606 sel->which); 607 return 0; 608 } 609 610 static int mt9p031_set_selection(struct v4l2_subdev *subdev, 611 struct v4l2_subdev_state *sd_state, 612 struct v4l2_subdev_selection *sel) 613 { 614 struct mt9p031 *mt9p031 = to_mt9p031(subdev); 615 struct v4l2_mbus_framefmt *__format; 616 struct v4l2_rect *__crop; 617 struct v4l2_rect rect; 618 619 if (sel->target != V4L2_SEL_TGT_CROP) 620 return -EINVAL; 621 622 /* Clamp the crop rectangle boundaries and align them to a multiple of 2 623 * pixels to ensure a GRBG Bayer pattern. 624 */ 625 rect.left = clamp(ALIGN(sel->r.left, 2), MT9P031_COLUMN_START_MIN, 626 MT9P031_COLUMN_START_MAX); 627 rect.top = clamp(ALIGN(sel->r.top, 2), MT9P031_ROW_START_MIN, 628 MT9P031_ROW_START_MAX); 629 rect.width = clamp_t(unsigned int, ALIGN(sel->r.width, 2), 630 MT9P031_WINDOW_WIDTH_MIN, 631 MT9P031_WINDOW_WIDTH_MAX); 632 rect.height = clamp_t(unsigned int, ALIGN(sel->r.height, 2), 633 MT9P031_WINDOW_HEIGHT_MIN, 634 MT9P031_WINDOW_HEIGHT_MAX); 635 636 rect.width = min_t(unsigned int, rect.width, 637 MT9P031_PIXEL_ARRAY_WIDTH - rect.left); 638 rect.height = min_t(unsigned int, rect.height, 639 MT9P031_PIXEL_ARRAY_HEIGHT - rect.top); 640 641 __crop = __mt9p031_get_pad_crop(mt9p031, sd_state, sel->pad, 642 sel->which); 643 644 if (rect.width != __crop->width || rect.height != __crop->height) { 645 /* Reset the output image size if the crop rectangle size has 646 * been modified. 647 */ 648 __format = __mt9p031_get_pad_format(mt9p031, sd_state, 649 sel->pad, 650 sel->which); 651 __format->width = rect.width; 652 __format->height = rect.height; 653 } 654 655 *__crop = rect; 656 sel->r = rect; 657 658 return 0; 659 } 660 661 /* ----------------------------------------------------------------------------- 662 * V4L2 subdev control operations 663 */ 664 665 #define V4L2_CID_BLC_AUTO (V4L2_CID_USER_BASE | 0x1002) 666 #define V4L2_CID_BLC_TARGET_LEVEL (V4L2_CID_USER_BASE | 0x1003) 667 #define V4L2_CID_BLC_ANALOG_OFFSET (V4L2_CID_USER_BASE | 0x1004) 668 #define V4L2_CID_BLC_DIGITAL_OFFSET (V4L2_CID_USER_BASE | 0x1005) 669 670 static int mt9p031_restore_blc(struct mt9p031 *mt9p031) 671 { 672 struct i2c_client *client = v4l2_get_subdevdata(&mt9p031->subdev); 673 int ret; 674 675 if (mt9p031->blc_auto->cur.val != 0) { 676 ret = mt9p031_set_mode2(mt9p031, 0, 677 MT9P031_READ_MODE_2_ROW_BLC); 678 if (ret < 0) 679 return ret; 680 } 681 682 if (mt9p031->blc_offset->cur.val != 0) { 683 ret = mt9p031_write(client, MT9P031_ROW_BLACK_TARGET, 684 mt9p031->blc_offset->cur.val); 685 if (ret < 0) 686 return ret; 687 } 688 689 return 0; 690 } 691 692 static int mt9p031_s_ctrl(struct v4l2_ctrl *ctrl) 693 { 694 struct mt9p031 *mt9p031 = 695 container_of(ctrl->handler, struct mt9p031, ctrls); 696 struct i2c_client *client = v4l2_get_subdevdata(&mt9p031->subdev); 697 u16 data; 698 int ret; 699 700 if (ctrl->flags & V4L2_CTRL_FLAG_INACTIVE) 701 return 0; 702 703 switch (ctrl->id) { 704 case V4L2_CID_EXPOSURE: 705 ret = mt9p031_write(client, MT9P031_SHUTTER_WIDTH_UPPER, 706 (ctrl->val >> 16) & 0xffff); 707 if (ret < 0) 708 return ret; 709 710 return mt9p031_write(client, MT9P031_SHUTTER_WIDTH_LOWER, 711 ctrl->val & 0xffff); 712 713 case V4L2_CID_GAIN: 714 /* Gain is controlled by 2 analog stages and a digital stage. 715 * Valid values for the 3 stages are 716 * 717 * Stage Min Max Step 718 * ------------------------------------------ 719 * First analog stage x1 x2 1 720 * Second analog stage x1 x4 0.125 721 * Digital stage x1 x16 0.125 722 * 723 * To minimize noise, the gain stages should be used in the 724 * second analog stage, first analog stage, digital stage order. 725 * Gain from a previous stage should be pushed to its maximum 726 * value before the next stage is used. 727 */ 728 if (ctrl->val <= 32) { 729 data = ctrl->val; 730 } else if (ctrl->val <= 64) { 731 ctrl->val &= ~1; 732 data = (1 << 6) | (ctrl->val >> 1); 733 } else { 734 ctrl->val &= ~7; 735 data = ((ctrl->val - 64) << 5) | (1 << 6) | 32; 736 } 737 738 return mt9p031_write(client, MT9P031_GLOBAL_GAIN, data); 739 740 case V4L2_CID_HFLIP: 741 if (ctrl->val) 742 return mt9p031_set_mode2(mt9p031, 743 0, MT9P031_READ_MODE_2_COL_MIR); 744 else 745 return mt9p031_set_mode2(mt9p031, 746 MT9P031_READ_MODE_2_COL_MIR, 0); 747 748 case V4L2_CID_VFLIP: 749 if (ctrl->val) 750 return mt9p031_set_mode2(mt9p031, 751 0, MT9P031_READ_MODE_2_ROW_MIR); 752 else 753 return mt9p031_set_mode2(mt9p031, 754 MT9P031_READ_MODE_2_ROW_MIR, 0); 755 756 case V4L2_CID_TEST_PATTERN: 757 /* The digital side of the Black Level Calibration function must 758 * be disabled when generating a test pattern to avoid artifacts 759 * in the image. Activate (deactivate) the BLC-related controls 760 * when the test pattern is enabled (disabled). 761 */ 762 v4l2_ctrl_activate(mt9p031->blc_auto, ctrl->val == 0); 763 v4l2_ctrl_activate(mt9p031->blc_offset, ctrl->val == 0); 764 765 if (!ctrl->val) { 766 /* Restore the BLC settings. */ 767 ret = mt9p031_restore_blc(mt9p031); 768 if (ret < 0) 769 return ret; 770 771 return mt9p031_write(client, MT9P031_TEST_PATTERN, 772 MT9P031_TEST_PATTERN_DISABLE); 773 } 774 775 ret = mt9p031_write(client, MT9P031_TEST_PATTERN_GREEN, 0x05a0); 776 if (ret < 0) 777 return ret; 778 ret = mt9p031_write(client, MT9P031_TEST_PATTERN_RED, 0x0a50); 779 if (ret < 0) 780 return ret; 781 ret = mt9p031_write(client, MT9P031_TEST_PATTERN_BLUE, 0x0aa0); 782 if (ret < 0) 783 return ret; 784 785 /* Disable digital BLC when generating a test pattern. */ 786 ret = mt9p031_set_mode2(mt9p031, MT9P031_READ_MODE_2_ROW_BLC, 787 0); 788 if (ret < 0) 789 return ret; 790 791 ret = mt9p031_write(client, MT9P031_ROW_BLACK_DEF_OFFSET, 0); 792 if (ret < 0) 793 return ret; 794 795 return mt9p031_write(client, MT9P031_TEST_PATTERN, 796 ((ctrl->val - 1) << MT9P031_TEST_PATTERN_SHIFT) 797 | MT9P031_TEST_PATTERN_ENABLE); 798 799 case V4L2_CID_BLC_AUTO: 800 ret = mt9p031_set_mode2(mt9p031, 801 ctrl->val ? 0 : MT9P031_READ_MODE_2_ROW_BLC, 802 ctrl->val ? MT9P031_READ_MODE_2_ROW_BLC : 0); 803 if (ret < 0) 804 return ret; 805 806 return mt9p031_write(client, MT9P031_BLACK_LEVEL_CALIBRATION, 807 ctrl->val ? 0 : MT9P031_BLC_MANUAL_BLC); 808 809 case V4L2_CID_BLC_TARGET_LEVEL: 810 return mt9p031_write(client, MT9P031_ROW_BLACK_TARGET, 811 ctrl->val); 812 813 case V4L2_CID_BLC_ANALOG_OFFSET: 814 data = ctrl->val & ((1 << 9) - 1); 815 816 ret = mt9p031_write(client, MT9P031_GREEN1_OFFSET, data); 817 if (ret < 0) 818 return ret; 819 ret = mt9p031_write(client, MT9P031_GREEN2_OFFSET, data); 820 if (ret < 0) 821 return ret; 822 ret = mt9p031_write(client, MT9P031_RED_OFFSET, data); 823 if (ret < 0) 824 return ret; 825 return mt9p031_write(client, MT9P031_BLUE_OFFSET, data); 826 827 case V4L2_CID_BLC_DIGITAL_OFFSET: 828 return mt9p031_write(client, MT9P031_ROW_BLACK_DEF_OFFSET, 829 ctrl->val & ((1 << 12) - 1)); 830 } 831 832 return 0; 833 } 834 835 static const struct v4l2_ctrl_ops mt9p031_ctrl_ops = { 836 .s_ctrl = mt9p031_s_ctrl, 837 }; 838 839 static const char * const mt9p031_test_pattern_menu[] = { 840 "Disabled", 841 "Color Field", 842 "Horizontal Gradient", 843 "Vertical Gradient", 844 "Diagonal Gradient", 845 "Classic Test Pattern", 846 "Walking 1s", 847 "Monochrome Horizontal Bars", 848 "Monochrome Vertical Bars", 849 "Vertical Color Bars", 850 }; 851 852 static const struct v4l2_ctrl_config mt9p031_ctrls[] = { 853 { 854 .ops = &mt9p031_ctrl_ops, 855 .id = V4L2_CID_BLC_AUTO, 856 .type = V4L2_CTRL_TYPE_BOOLEAN, 857 .name = "BLC, Auto", 858 .min = 0, 859 .max = 1, 860 .step = 1, 861 .def = 1, 862 .flags = 0, 863 }, { 864 .ops = &mt9p031_ctrl_ops, 865 .id = V4L2_CID_BLC_TARGET_LEVEL, 866 .type = V4L2_CTRL_TYPE_INTEGER, 867 .name = "BLC Target Level", 868 .min = 0, 869 .max = 4095, 870 .step = 1, 871 .def = 168, 872 .flags = 0, 873 }, { 874 .ops = &mt9p031_ctrl_ops, 875 .id = V4L2_CID_BLC_ANALOG_OFFSET, 876 .type = V4L2_CTRL_TYPE_INTEGER, 877 .name = "BLC Analog Offset", 878 .min = -255, 879 .max = 255, 880 .step = 1, 881 .def = 32, 882 .flags = 0, 883 }, { 884 .ops = &mt9p031_ctrl_ops, 885 .id = V4L2_CID_BLC_DIGITAL_OFFSET, 886 .type = V4L2_CTRL_TYPE_INTEGER, 887 .name = "BLC Digital Offset", 888 .min = -2048, 889 .max = 2047, 890 .step = 1, 891 .def = 40, 892 .flags = 0, 893 } 894 }; 895 896 /* ----------------------------------------------------------------------------- 897 * V4L2 subdev core operations 898 */ 899 900 static int mt9p031_set_power(struct v4l2_subdev *subdev, int on) 901 { 902 struct mt9p031 *mt9p031 = to_mt9p031(subdev); 903 int ret = 0; 904 905 mutex_lock(&mt9p031->power_lock); 906 907 /* If the power count is modified from 0 to != 0 or from != 0 to 0, 908 * update the power state. 909 */ 910 if (mt9p031->power_count == !on) { 911 ret = __mt9p031_set_power(mt9p031, !!on); 912 if (ret < 0) 913 goto out; 914 } 915 916 /* Update the power count. */ 917 mt9p031->power_count += on ? 1 : -1; 918 WARN_ON(mt9p031->power_count < 0); 919 920 out: 921 mutex_unlock(&mt9p031->power_lock); 922 return ret; 923 } 924 925 /* ----------------------------------------------------------------------------- 926 * V4L2 subdev internal operations 927 */ 928 929 static int mt9p031_registered(struct v4l2_subdev *subdev) 930 { 931 struct i2c_client *client = v4l2_get_subdevdata(subdev); 932 struct mt9p031 *mt9p031 = to_mt9p031(subdev); 933 s32 data; 934 int ret; 935 936 ret = mt9p031_power_on(mt9p031); 937 if (ret < 0) { 938 dev_err(&client->dev, "MT9P031 power up failed\n"); 939 return ret; 940 } 941 942 /* Read out the chip version register */ 943 data = mt9p031_read(client, MT9P031_CHIP_VERSION); 944 mt9p031_power_off(mt9p031); 945 946 if (data != MT9P031_CHIP_VERSION_VALUE) { 947 dev_err(&client->dev, "MT9P031 not detected, wrong version " 948 "0x%04x\n", data); 949 return -ENODEV; 950 } 951 952 dev_info(&client->dev, "MT9P031 detected at address 0x%02x\n", 953 client->addr); 954 955 return 0; 956 } 957 958 static int mt9p031_open(struct v4l2_subdev *subdev, struct v4l2_subdev_fh *fh) 959 { 960 struct mt9p031 *mt9p031 = to_mt9p031(subdev); 961 struct v4l2_mbus_framefmt *format; 962 struct v4l2_rect *crop; 963 964 crop = v4l2_subdev_get_try_crop(subdev, fh->state, 0); 965 crop->left = MT9P031_COLUMN_START_DEF; 966 crop->top = MT9P031_ROW_START_DEF; 967 crop->width = MT9P031_WINDOW_WIDTH_DEF; 968 crop->height = MT9P031_WINDOW_HEIGHT_DEF; 969 970 format = v4l2_subdev_get_try_format(subdev, fh->state, 0); 971 972 if (mt9p031->model == MT9P031_MODEL_MONOCHROME) 973 format->code = MEDIA_BUS_FMT_Y12_1X12; 974 else 975 format->code = MEDIA_BUS_FMT_SGRBG12_1X12; 976 977 format->width = MT9P031_WINDOW_WIDTH_DEF; 978 format->height = MT9P031_WINDOW_HEIGHT_DEF; 979 format->field = V4L2_FIELD_NONE; 980 format->colorspace = V4L2_COLORSPACE_SRGB; 981 982 return mt9p031_set_power(subdev, 1); 983 } 984 985 static int mt9p031_close(struct v4l2_subdev *subdev, struct v4l2_subdev_fh *fh) 986 { 987 return mt9p031_set_power(subdev, 0); 988 } 989 990 static const struct v4l2_subdev_core_ops mt9p031_subdev_core_ops = { 991 .s_power = mt9p031_set_power, 992 }; 993 994 static const struct v4l2_subdev_video_ops mt9p031_subdev_video_ops = { 995 .s_stream = mt9p031_s_stream, 996 }; 997 998 static const struct v4l2_subdev_pad_ops mt9p031_subdev_pad_ops = { 999 .enum_mbus_code = mt9p031_enum_mbus_code, 1000 .enum_frame_size = mt9p031_enum_frame_size, 1001 .get_fmt = mt9p031_get_format, 1002 .set_fmt = mt9p031_set_format, 1003 .get_selection = mt9p031_get_selection, 1004 .set_selection = mt9p031_set_selection, 1005 }; 1006 1007 static const struct v4l2_subdev_ops mt9p031_subdev_ops = { 1008 .core = &mt9p031_subdev_core_ops, 1009 .video = &mt9p031_subdev_video_ops, 1010 .pad = &mt9p031_subdev_pad_ops, 1011 }; 1012 1013 static const struct v4l2_subdev_internal_ops mt9p031_subdev_internal_ops = { 1014 .registered = mt9p031_registered, 1015 .open = mt9p031_open, 1016 .close = mt9p031_close, 1017 }; 1018 1019 /* ----------------------------------------------------------------------------- 1020 * Driver initialization and probing 1021 */ 1022 1023 static struct mt9p031_platform_data * 1024 mt9p031_get_pdata(struct i2c_client *client) 1025 { 1026 struct mt9p031_platform_data *pdata = NULL; 1027 struct device_node *np; 1028 struct v4l2_fwnode_endpoint endpoint = { 1029 .bus_type = V4L2_MBUS_PARALLEL 1030 }; 1031 1032 if (!IS_ENABLED(CONFIG_OF) || !client->dev.of_node) 1033 return client->dev.platform_data; 1034 1035 np = of_graph_get_next_endpoint(client->dev.of_node, NULL); 1036 if (!np) 1037 return NULL; 1038 1039 if (v4l2_fwnode_endpoint_parse(of_fwnode_handle(np), &endpoint) < 0) 1040 goto done; 1041 1042 pdata = devm_kzalloc(&client->dev, sizeof(*pdata), GFP_KERNEL); 1043 if (!pdata) 1044 goto done; 1045 1046 of_property_read_u32(np, "input-clock-frequency", &pdata->ext_freq); 1047 of_property_read_u32(np, "pixel-clock-frequency", &pdata->target_freq); 1048 1049 pdata->pixclk_pol = !!(endpoint.bus.parallel.flags & 1050 V4L2_MBUS_PCLK_SAMPLE_RISING); 1051 1052 done: 1053 of_node_put(np); 1054 return pdata; 1055 } 1056 1057 static int mt9p031_probe(struct i2c_client *client, 1058 const struct i2c_device_id *did) 1059 { 1060 struct mt9p031_platform_data *pdata = mt9p031_get_pdata(client); 1061 struct i2c_adapter *adapter = client->adapter; 1062 struct mt9p031 *mt9p031; 1063 unsigned int i; 1064 int ret; 1065 1066 if (pdata == NULL) { 1067 dev_err(&client->dev, "No platform data\n"); 1068 return -EINVAL; 1069 } 1070 1071 if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_WORD_DATA)) { 1072 dev_warn(&client->dev, 1073 "I2C-Adapter doesn't support I2C_FUNC_SMBUS_WORD\n"); 1074 return -EIO; 1075 } 1076 1077 mt9p031 = devm_kzalloc(&client->dev, sizeof(*mt9p031), GFP_KERNEL); 1078 if (mt9p031 == NULL) 1079 return -ENOMEM; 1080 1081 mt9p031->pdata = pdata; 1082 mt9p031->output_control = MT9P031_OUTPUT_CONTROL_DEF; 1083 mt9p031->mode2 = MT9P031_READ_MODE_2_ROW_BLC; 1084 mt9p031->model = did->driver_data; 1085 1086 mt9p031->regulators[0].supply = "vdd"; 1087 mt9p031->regulators[1].supply = "vdd_io"; 1088 mt9p031->regulators[2].supply = "vaa"; 1089 1090 ret = devm_regulator_bulk_get(&client->dev, 3, mt9p031->regulators); 1091 if (ret < 0) { 1092 dev_err(&client->dev, "Unable to get regulators\n"); 1093 return ret; 1094 } 1095 1096 mutex_init(&mt9p031->power_lock); 1097 1098 v4l2_ctrl_handler_init(&mt9p031->ctrls, ARRAY_SIZE(mt9p031_ctrls) + 6); 1099 1100 v4l2_ctrl_new_std(&mt9p031->ctrls, &mt9p031_ctrl_ops, 1101 V4L2_CID_EXPOSURE, MT9P031_SHUTTER_WIDTH_MIN, 1102 MT9P031_SHUTTER_WIDTH_MAX, 1, 1103 MT9P031_SHUTTER_WIDTH_DEF); 1104 v4l2_ctrl_new_std(&mt9p031->ctrls, &mt9p031_ctrl_ops, 1105 V4L2_CID_GAIN, MT9P031_GLOBAL_GAIN_MIN, 1106 MT9P031_GLOBAL_GAIN_MAX, 1, MT9P031_GLOBAL_GAIN_DEF); 1107 v4l2_ctrl_new_std(&mt9p031->ctrls, &mt9p031_ctrl_ops, 1108 V4L2_CID_HFLIP, 0, 1, 1, 0); 1109 v4l2_ctrl_new_std(&mt9p031->ctrls, &mt9p031_ctrl_ops, 1110 V4L2_CID_VFLIP, 0, 1, 1, 0); 1111 v4l2_ctrl_new_std(&mt9p031->ctrls, &mt9p031_ctrl_ops, 1112 V4L2_CID_PIXEL_RATE, pdata->target_freq, 1113 pdata->target_freq, 1, pdata->target_freq); 1114 v4l2_ctrl_new_std_menu_items(&mt9p031->ctrls, &mt9p031_ctrl_ops, 1115 V4L2_CID_TEST_PATTERN, 1116 ARRAY_SIZE(mt9p031_test_pattern_menu) - 1, 0, 1117 0, mt9p031_test_pattern_menu); 1118 1119 for (i = 0; i < ARRAY_SIZE(mt9p031_ctrls); ++i) 1120 v4l2_ctrl_new_custom(&mt9p031->ctrls, &mt9p031_ctrls[i], NULL); 1121 1122 mt9p031->subdev.ctrl_handler = &mt9p031->ctrls; 1123 1124 if (mt9p031->ctrls.error) { 1125 printk(KERN_INFO "%s: control initialization error %d\n", 1126 __func__, mt9p031->ctrls.error); 1127 ret = mt9p031->ctrls.error; 1128 goto done; 1129 } 1130 1131 mt9p031->blc_auto = v4l2_ctrl_find(&mt9p031->ctrls, V4L2_CID_BLC_AUTO); 1132 mt9p031->blc_offset = v4l2_ctrl_find(&mt9p031->ctrls, 1133 V4L2_CID_BLC_DIGITAL_OFFSET); 1134 1135 v4l2_i2c_subdev_init(&mt9p031->subdev, client, &mt9p031_subdev_ops); 1136 mt9p031->subdev.internal_ops = &mt9p031_subdev_internal_ops; 1137 1138 mt9p031->subdev.entity.function = MEDIA_ENT_F_CAM_SENSOR; 1139 mt9p031->pad.flags = MEDIA_PAD_FL_SOURCE; 1140 ret = media_entity_pads_init(&mt9p031->subdev.entity, 1, &mt9p031->pad); 1141 if (ret < 0) 1142 goto done; 1143 1144 mt9p031->subdev.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; 1145 1146 mt9p031->crop.width = MT9P031_WINDOW_WIDTH_DEF; 1147 mt9p031->crop.height = MT9P031_WINDOW_HEIGHT_DEF; 1148 mt9p031->crop.left = MT9P031_COLUMN_START_DEF; 1149 mt9p031->crop.top = MT9P031_ROW_START_DEF; 1150 1151 if (mt9p031->model == MT9P031_MODEL_MONOCHROME) 1152 mt9p031->format.code = MEDIA_BUS_FMT_Y12_1X12; 1153 else 1154 mt9p031->format.code = MEDIA_BUS_FMT_SGRBG12_1X12; 1155 1156 mt9p031->format.width = MT9P031_WINDOW_WIDTH_DEF; 1157 mt9p031->format.height = MT9P031_WINDOW_HEIGHT_DEF; 1158 mt9p031->format.field = V4L2_FIELD_NONE; 1159 mt9p031->format.colorspace = V4L2_COLORSPACE_SRGB; 1160 1161 mt9p031->reset = devm_gpiod_get_optional(&client->dev, "reset", 1162 GPIOD_OUT_HIGH); 1163 1164 ret = mt9p031_clk_setup(mt9p031); 1165 if (ret) 1166 goto done; 1167 1168 ret = v4l2_async_register_subdev(&mt9p031->subdev); 1169 1170 done: 1171 if (ret < 0) { 1172 v4l2_ctrl_handler_free(&mt9p031->ctrls); 1173 media_entity_cleanup(&mt9p031->subdev.entity); 1174 mutex_destroy(&mt9p031->power_lock); 1175 } 1176 1177 return ret; 1178 } 1179 1180 static int mt9p031_remove(struct i2c_client *client) 1181 { 1182 struct v4l2_subdev *subdev = i2c_get_clientdata(client); 1183 struct mt9p031 *mt9p031 = to_mt9p031(subdev); 1184 1185 v4l2_ctrl_handler_free(&mt9p031->ctrls); 1186 v4l2_async_unregister_subdev(subdev); 1187 media_entity_cleanup(&subdev->entity); 1188 mutex_destroy(&mt9p031->power_lock); 1189 1190 return 0; 1191 } 1192 1193 static const struct i2c_device_id mt9p031_id[] = { 1194 { "mt9p031", MT9P031_MODEL_COLOR }, 1195 { "mt9p031m", MT9P031_MODEL_MONOCHROME }, 1196 { } 1197 }; 1198 MODULE_DEVICE_TABLE(i2c, mt9p031_id); 1199 1200 #if IS_ENABLED(CONFIG_OF) 1201 static const struct of_device_id mt9p031_of_match[] = { 1202 { .compatible = "aptina,mt9p031", }, 1203 { .compatible = "aptina,mt9p031m", }, 1204 { /* sentinel */ }, 1205 }; 1206 MODULE_DEVICE_TABLE(of, mt9p031_of_match); 1207 #endif 1208 1209 static struct i2c_driver mt9p031_i2c_driver = { 1210 .driver = { 1211 .of_match_table = of_match_ptr(mt9p031_of_match), 1212 .name = "mt9p031", 1213 }, 1214 .probe = mt9p031_probe, 1215 .remove = mt9p031_remove, 1216 .id_table = mt9p031_id, 1217 }; 1218 1219 module_i2c_driver(mt9p031_i2c_driver); 1220 1221 MODULE_DESCRIPTION("Aptina MT9P031 Camera driver"); 1222 MODULE_AUTHOR("Bastian Hecht <hechtb@gmail.com>"); 1223 MODULE_LICENSE("GPL v2"); 1224