1 /* 2 * Driver for MT9P031 CMOS Image Sensor from Aptina 3 * 4 * Copyright (C) 2011, Laurent Pinchart <laurent.pinchart@ideasonboard.com> 5 * Copyright (C) 2011, Javier Martin <javier.martin@vista-silicon.com> 6 * Copyright (C) 2011, Guennadi Liakhovetski <g.liakhovetski@gmx.de> 7 * 8 * Based on the MT9V032 driver and Bastian Hecht's code. 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License version 2 as 12 * published by the Free Software Foundation. 13 */ 14 15 #include <linux/clk.h> 16 #include <linux/delay.h> 17 #include <linux/device.h> 18 #include <linux/gpio.h> 19 #include <linux/i2c.h> 20 #include <linux/log2.h> 21 #include <linux/module.h> 22 #include <linux/of.h> 23 #include <linux/of_gpio.h> 24 #include <linux/of_graph.h> 25 #include <linux/pm.h> 26 #include <linux/regulator/consumer.h> 27 #include <linux/slab.h> 28 #include <linux/videodev2.h> 29 30 #include <media/mt9p031.h> 31 #include <media/v4l2-async.h> 32 #include <media/v4l2-ctrls.h> 33 #include <media/v4l2-device.h> 34 #include <media/v4l2-subdev.h> 35 36 #include "aptina-pll.h" 37 38 #define MT9P031_PIXEL_ARRAY_WIDTH 2752 39 #define MT9P031_PIXEL_ARRAY_HEIGHT 2004 40 41 #define MT9P031_CHIP_VERSION 0x00 42 #define MT9P031_CHIP_VERSION_VALUE 0x1801 43 #define MT9P031_ROW_START 0x01 44 #define MT9P031_ROW_START_MIN 0 45 #define MT9P031_ROW_START_MAX 2004 46 #define MT9P031_ROW_START_DEF 54 47 #define MT9P031_COLUMN_START 0x02 48 #define MT9P031_COLUMN_START_MIN 0 49 #define MT9P031_COLUMN_START_MAX 2750 50 #define MT9P031_COLUMN_START_DEF 16 51 #define MT9P031_WINDOW_HEIGHT 0x03 52 #define MT9P031_WINDOW_HEIGHT_MIN 2 53 #define MT9P031_WINDOW_HEIGHT_MAX 2006 54 #define MT9P031_WINDOW_HEIGHT_DEF 1944 55 #define MT9P031_WINDOW_WIDTH 0x04 56 #define MT9P031_WINDOW_WIDTH_MIN 2 57 #define MT9P031_WINDOW_WIDTH_MAX 2752 58 #define MT9P031_WINDOW_WIDTH_DEF 2592 59 #define MT9P031_HORIZONTAL_BLANK 0x05 60 #define MT9P031_HORIZONTAL_BLANK_MIN 0 61 #define MT9P031_HORIZONTAL_BLANK_MAX 4095 62 #define MT9P031_VERTICAL_BLANK 0x06 63 #define MT9P031_VERTICAL_BLANK_MIN 1 64 #define MT9P031_VERTICAL_BLANK_MAX 4096 65 #define MT9P031_VERTICAL_BLANK_DEF 26 66 #define MT9P031_OUTPUT_CONTROL 0x07 67 #define MT9P031_OUTPUT_CONTROL_CEN 2 68 #define MT9P031_OUTPUT_CONTROL_SYN 1 69 #define MT9P031_OUTPUT_CONTROL_DEF 0x1f82 70 #define MT9P031_SHUTTER_WIDTH_UPPER 0x08 71 #define MT9P031_SHUTTER_WIDTH_LOWER 0x09 72 #define MT9P031_SHUTTER_WIDTH_MIN 1 73 #define MT9P031_SHUTTER_WIDTH_MAX 1048575 74 #define MT9P031_SHUTTER_WIDTH_DEF 1943 75 #define MT9P031_PLL_CONTROL 0x10 76 #define MT9P031_PLL_CONTROL_PWROFF 0x0050 77 #define MT9P031_PLL_CONTROL_PWRON 0x0051 78 #define MT9P031_PLL_CONTROL_USEPLL 0x0052 79 #define MT9P031_PLL_CONFIG_1 0x11 80 #define MT9P031_PLL_CONFIG_2 0x12 81 #define MT9P031_PIXEL_CLOCK_CONTROL 0x0a 82 #define MT9P031_PIXEL_CLOCK_INVERT (1 << 15) 83 #define MT9P031_PIXEL_CLOCK_SHIFT(n) ((n) << 8) 84 #define MT9P031_PIXEL_CLOCK_DIVIDE(n) ((n) << 0) 85 #define MT9P031_FRAME_RESTART 0x0b 86 #define MT9P031_SHUTTER_DELAY 0x0c 87 #define MT9P031_RST 0x0d 88 #define MT9P031_RST_ENABLE 1 89 #define MT9P031_RST_DISABLE 0 90 #define MT9P031_READ_MODE_1 0x1e 91 #define MT9P031_READ_MODE_2 0x20 92 #define MT9P031_READ_MODE_2_ROW_MIR (1 << 15) 93 #define MT9P031_READ_MODE_2_COL_MIR (1 << 14) 94 #define MT9P031_READ_MODE_2_ROW_BLC (1 << 6) 95 #define MT9P031_ROW_ADDRESS_MODE 0x22 96 #define MT9P031_COLUMN_ADDRESS_MODE 0x23 97 #define MT9P031_GLOBAL_GAIN 0x35 98 #define MT9P031_GLOBAL_GAIN_MIN 8 99 #define MT9P031_GLOBAL_GAIN_MAX 1024 100 #define MT9P031_GLOBAL_GAIN_DEF 8 101 #define MT9P031_GLOBAL_GAIN_MULT (1 << 6) 102 #define MT9P031_ROW_BLACK_TARGET 0x49 103 #define MT9P031_ROW_BLACK_DEF_OFFSET 0x4b 104 #define MT9P031_GREEN1_OFFSET 0x60 105 #define MT9P031_GREEN2_OFFSET 0x61 106 #define MT9P031_BLACK_LEVEL_CALIBRATION 0x62 107 #define MT9P031_BLC_MANUAL_BLC (1 << 0) 108 #define MT9P031_RED_OFFSET 0x63 109 #define MT9P031_BLUE_OFFSET 0x64 110 #define MT9P031_TEST_PATTERN 0xa0 111 #define MT9P031_TEST_PATTERN_SHIFT 3 112 #define MT9P031_TEST_PATTERN_ENABLE (1 << 0) 113 #define MT9P031_TEST_PATTERN_DISABLE (0 << 0) 114 #define MT9P031_TEST_PATTERN_GREEN 0xa1 115 #define MT9P031_TEST_PATTERN_RED 0xa2 116 #define MT9P031_TEST_PATTERN_BLUE 0xa3 117 118 enum mt9p031_model { 119 MT9P031_MODEL_COLOR, 120 MT9P031_MODEL_MONOCHROME, 121 }; 122 123 struct mt9p031 { 124 struct v4l2_subdev subdev; 125 struct media_pad pad; 126 struct v4l2_rect crop; /* Sensor window */ 127 struct v4l2_mbus_framefmt format; 128 struct mt9p031_platform_data *pdata; 129 struct mutex power_lock; /* lock to protect power_count */ 130 int power_count; 131 132 struct clk *clk; 133 struct regulator_bulk_data regulators[3]; 134 135 enum mt9p031_model model; 136 struct aptina_pll pll; 137 unsigned int clk_div; 138 bool use_pll; 139 int reset; 140 141 struct v4l2_ctrl_handler ctrls; 142 struct v4l2_ctrl *blc_auto; 143 struct v4l2_ctrl *blc_offset; 144 145 /* Registers cache */ 146 u16 output_control; 147 u16 mode2; 148 }; 149 150 static struct mt9p031 *to_mt9p031(struct v4l2_subdev *sd) 151 { 152 return container_of(sd, struct mt9p031, subdev); 153 } 154 155 static int mt9p031_read(struct i2c_client *client, u8 reg) 156 { 157 return i2c_smbus_read_word_swapped(client, reg); 158 } 159 160 static int mt9p031_write(struct i2c_client *client, u8 reg, u16 data) 161 { 162 return i2c_smbus_write_word_swapped(client, reg, data); 163 } 164 165 static int mt9p031_set_output_control(struct mt9p031 *mt9p031, u16 clear, 166 u16 set) 167 { 168 struct i2c_client *client = v4l2_get_subdevdata(&mt9p031->subdev); 169 u16 value = (mt9p031->output_control & ~clear) | set; 170 int ret; 171 172 ret = mt9p031_write(client, MT9P031_OUTPUT_CONTROL, value); 173 if (ret < 0) 174 return ret; 175 176 mt9p031->output_control = value; 177 return 0; 178 } 179 180 static int mt9p031_set_mode2(struct mt9p031 *mt9p031, u16 clear, u16 set) 181 { 182 struct i2c_client *client = v4l2_get_subdevdata(&mt9p031->subdev); 183 u16 value = (mt9p031->mode2 & ~clear) | set; 184 int ret; 185 186 ret = mt9p031_write(client, MT9P031_READ_MODE_2, value); 187 if (ret < 0) 188 return ret; 189 190 mt9p031->mode2 = value; 191 return 0; 192 } 193 194 static int mt9p031_reset(struct mt9p031 *mt9p031) 195 { 196 struct i2c_client *client = v4l2_get_subdevdata(&mt9p031->subdev); 197 int ret; 198 199 /* Disable chip output, synchronous option update */ 200 ret = mt9p031_write(client, MT9P031_RST, MT9P031_RST_ENABLE); 201 if (ret < 0) 202 return ret; 203 ret = mt9p031_write(client, MT9P031_RST, MT9P031_RST_DISABLE); 204 if (ret < 0) 205 return ret; 206 207 ret = mt9p031_write(client, MT9P031_PIXEL_CLOCK_CONTROL, 208 MT9P031_PIXEL_CLOCK_DIVIDE(mt9p031->clk_div)); 209 if (ret < 0) 210 return ret; 211 212 return mt9p031_set_output_control(mt9p031, MT9P031_OUTPUT_CONTROL_CEN, 213 0); 214 } 215 216 static int mt9p031_clk_setup(struct mt9p031 *mt9p031) 217 { 218 static const struct aptina_pll_limits limits = { 219 .ext_clock_min = 6000000, 220 .ext_clock_max = 27000000, 221 .int_clock_min = 2000000, 222 .int_clock_max = 13500000, 223 .out_clock_min = 180000000, 224 .out_clock_max = 360000000, 225 .pix_clock_max = 96000000, 226 .n_min = 1, 227 .n_max = 64, 228 .m_min = 16, 229 .m_max = 255, 230 .p1_min = 1, 231 .p1_max = 128, 232 }; 233 234 struct i2c_client *client = v4l2_get_subdevdata(&mt9p031->subdev); 235 struct mt9p031_platform_data *pdata = mt9p031->pdata; 236 int ret; 237 238 mt9p031->clk = devm_clk_get(&client->dev, NULL); 239 if (IS_ERR(mt9p031->clk)) 240 return PTR_ERR(mt9p031->clk); 241 242 ret = clk_set_rate(mt9p031->clk, pdata->ext_freq); 243 if (ret < 0) 244 return ret; 245 246 /* If the external clock frequency is out of bounds for the PLL use the 247 * pixel clock divider only and disable the PLL. 248 */ 249 if (pdata->ext_freq > limits.ext_clock_max) { 250 unsigned int div; 251 252 div = DIV_ROUND_UP(pdata->ext_freq, pdata->target_freq); 253 div = roundup_pow_of_two(div) / 2; 254 255 mt9p031->clk_div = min_t(unsigned int, div, 64); 256 mt9p031->use_pll = false; 257 258 return 0; 259 } 260 261 mt9p031->pll.ext_clock = pdata->ext_freq; 262 mt9p031->pll.pix_clock = pdata->target_freq; 263 mt9p031->use_pll = true; 264 265 return aptina_pll_calculate(&client->dev, &limits, &mt9p031->pll); 266 } 267 268 static int mt9p031_pll_enable(struct mt9p031 *mt9p031) 269 { 270 struct i2c_client *client = v4l2_get_subdevdata(&mt9p031->subdev); 271 int ret; 272 273 if (!mt9p031->use_pll) 274 return 0; 275 276 ret = mt9p031_write(client, MT9P031_PLL_CONTROL, 277 MT9P031_PLL_CONTROL_PWRON); 278 if (ret < 0) 279 return ret; 280 281 ret = mt9p031_write(client, MT9P031_PLL_CONFIG_1, 282 (mt9p031->pll.m << 8) | (mt9p031->pll.n - 1)); 283 if (ret < 0) 284 return ret; 285 286 ret = mt9p031_write(client, MT9P031_PLL_CONFIG_2, mt9p031->pll.p1 - 1); 287 if (ret < 0) 288 return ret; 289 290 usleep_range(1000, 2000); 291 ret = mt9p031_write(client, MT9P031_PLL_CONTROL, 292 MT9P031_PLL_CONTROL_PWRON | 293 MT9P031_PLL_CONTROL_USEPLL); 294 return ret; 295 } 296 297 static inline int mt9p031_pll_disable(struct mt9p031 *mt9p031) 298 { 299 struct i2c_client *client = v4l2_get_subdevdata(&mt9p031->subdev); 300 301 if (!mt9p031->use_pll) 302 return 0; 303 304 return mt9p031_write(client, MT9P031_PLL_CONTROL, 305 MT9P031_PLL_CONTROL_PWROFF); 306 } 307 308 static int mt9p031_power_on(struct mt9p031 *mt9p031) 309 { 310 int ret; 311 312 /* Ensure RESET_BAR is low */ 313 if (gpio_is_valid(mt9p031->reset)) { 314 gpio_set_value(mt9p031->reset, 0); 315 usleep_range(1000, 2000); 316 } 317 318 /* Bring up the supplies */ 319 ret = regulator_bulk_enable(ARRAY_SIZE(mt9p031->regulators), 320 mt9p031->regulators); 321 if (ret < 0) 322 return ret; 323 324 /* Enable clock */ 325 if (mt9p031->clk) { 326 ret = clk_prepare_enable(mt9p031->clk); 327 if (ret) { 328 regulator_bulk_disable(ARRAY_SIZE(mt9p031->regulators), 329 mt9p031->regulators); 330 return ret; 331 } 332 } 333 334 /* Now RESET_BAR must be high */ 335 if (gpio_is_valid(mt9p031->reset)) { 336 gpio_set_value(mt9p031->reset, 1); 337 usleep_range(1000, 2000); 338 } 339 340 return 0; 341 } 342 343 static void mt9p031_power_off(struct mt9p031 *mt9p031) 344 { 345 if (gpio_is_valid(mt9p031->reset)) { 346 gpio_set_value(mt9p031->reset, 0); 347 usleep_range(1000, 2000); 348 } 349 350 regulator_bulk_disable(ARRAY_SIZE(mt9p031->regulators), 351 mt9p031->regulators); 352 353 if (mt9p031->clk) 354 clk_disable_unprepare(mt9p031->clk); 355 } 356 357 static int __mt9p031_set_power(struct mt9p031 *mt9p031, bool on) 358 { 359 struct i2c_client *client = v4l2_get_subdevdata(&mt9p031->subdev); 360 int ret; 361 362 if (!on) { 363 mt9p031_power_off(mt9p031); 364 return 0; 365 } 366 367 ret = mt9p031_power_on(mt9p031); 368 if (ret < 0) 369 return ret; 370 371 ret = mt9p031_reset(mt9p031); 372 if (ret < 0) { 373 dev_err(&client->dev, "Failed to reset the camera\n"); 374 return ret; 375 } 376 377 return v4l2_ctrl_handler_setup(&mt9p031->ctrls); 378 } 379 380 /* ----------------------------------------------------------------------------- 381 * V4L2 subdev video operations 382 */ 383 384 static int mt9p031_set_params(struct mt9p031 *mt9p031) 385 { 386 struct i2c_client *client = v4l2_get_subdevdata(&mt9p031->subdev); 387 struct v4l2_mbus_framefmt *format = &mt9p031->format; 388 const struct v4l2_rect *crop = &mt9p031->crop; 389 unsigned int hblank; 390 unsigned int vblank; 391 unsigned int xskip; 392 unsigned int yskip; 393 unsigned int xbin; 394 unsigned int ybin; 395 int ret; 396 397 /* Windows position and size. 398 * 399 * TODO: Make sure the start coordinates and window size match the 400 * skipping, binning and mirroring (see description of registers 2 and 4 401 * in table 13, and Binning section on page 41). 402 */ 403 ret = mt9p031_write(client, MT9P031_COLUMN_START, crop->left); 404 if (ret < 0) 405 return ret; 406 ret = mt9p031_write(client, MT9P031_ROW_START, crop->top); 407 if (ret < 0) 408 return ret; 409 ret = mt9p031_write(client, MT9P031_WINDOW_WIDTH, crop->width - 1); 410 if (ret < 0) 411 return ret; 412 ret = mt9p031_write(client, MT9P031_WINDOW_HEIGHT, crop->height - 1); 413 if (ret < 0) 414 return ret; 415 416 /* Row and column binning and skipping. Use the maximum binning value 417 * compatible with the skipping settings. 418 */ 419 xskip = DIV_ROUND_CLOSEST(crop->width, format->width); 420 yskip = DIV_ROUND_CLOSEST(crop->height, format->height); 421 xbin = 1 << (ffs(xskip) - 1); 422 ybin = 1 << (ffs(yskip) - 1); 423 424 ret = mt9p031_write(client, MT9P031_COLUMN_ADDRESS_MODE, 425 ((xbin - 1) << 4) | (xskip - 1)); 426 if (ret < 0) 427 return ret; 428 ret = mt9p031_write(client, MT9P031_ROW_ADDRESS_MODE, 429 ((ybin - 1) << 4) | (yskip - 1)); 430 if (ret < 0) 431 return ret; 432 433 /* Blanking - use minimum value for horizontal blanking and default 434 * value for vertical blanking. 435 */ 436 hblank = 346 * ybin + 64 + (80 >> min_t(unsigned int, xbin, 3)); 437 vblank = MT9P031_VERTICAL_BLANK_DEF; 438 439 ret = mt9p031_write(client, MT9P031_HORIZONTAL_BLANK, hblank - 1); 440 if (ret < 0) 441 return ret; 442 ret = mt9p031_write(client, MT9P031_VERTICAL_BLANK, vblank - 1); 443 if (ret < 0) 444 return ret; 445 446 return ret; 447 } 448 449 static int mt9p031_s_stream(struct v4l2_subdev *subdev, int enable) 450 { 451 struct mt9p031 *mt9p031 = to_mt9p031(subdev); 452 int ret; 453 454 if (!enable) { 455 /* Stop sensor readout */ 456 ret = mt9p031_set_output_control(mt9p031, 457 MT9P031_OUTPUT_CONTROL_CEN, 0); 458 if (ret < 0) 459 return ret; 460 461 return mt9p031_pll_disable(mt9p031); 462 } 463 464 ret = mt9p031_set_params(mt9p031); 465 if (ret < 0) 466 return ret; 467 468 /* Switch to master "normal" mode */ 469 ret = mt9p031_set_output_control(mt9p031, 0, 470 MT9P031_OUTPUT_CONTROL_CEN); 471 if (ret < 0) 472 return ret; 473 474 return mt9p031_pll_enable(mt9p031); 475 } 476 477 static int mt9p031_enum_mbus_code(struct v4l2_subdev *subdev, 478 struct v4l2_subdev_pad_config *cfg, 479 struct v4l2_subdev_mbus_code_enum *code) 480 { 481 struct mt9p031 *mt9p031 = to_mt9p031(subdev); 482 483 if (code->pad || code->index) 484 return -EINVAL; 485 486 code->code = mt9p031->format.code; 487 return 0; 488 } 489 490 static int mt9p031_enum_frame_size(struct v4l2_subdev *subdev, 491 struct v4l2_subdev_pad_config *cfg, 492 struct v4l2_subdev_frame_size_enum *fse) 493 { 494 struct mt9p031 *mt9p031 = to_mt9p031(subdev); 495 496 if (fse->index >= 8 || fse->code != mt9p031->format.code) 497 return -EINVAL; 498 499 fse->min_width = MT9P031_WINDOW_WIDTH_DEF 500 / min_t(unsigned int, 7, fse->index + 1); 501 fse->max_width = fse->min_width; 502 fse->min_height = MT9P031_WINDOW_HEIGHT_DEF / (fse->index + 1); 503 fse->max_height = fse->min_height; 504 505 return 0; 506 } 507 508 static struct v4l2_mbus_framefmt * 509 __mt9p031_get_pad_format(struct mt9p031 *mt9p031, struct v4l2_subdev_pad_config *cfg, 510 unsigned int pad, u32 which) 511 { 512 switch (which) { 513 case V4L2_SUBDEV_FORMAT_TRY: 514 return v4l2_subdev_get_try_format(&mt9p031->subdev, cfg, pad); 515 case V4L2_SUBDEV_FORMAT_ACTIVE: 516 return &mt9p031->format; 517 default: 518 return NULL; 519 } 520 } 521 522 static struct v4l2_rect * 523 __mt9p031_get_pad_crop(struct mt9p031 *mt9p031, struct v4l2_subdev_pad_config *cfg, 524 unsigned int pad, u32 which) 525 { 526 switch (which) { 527 case V4L2_SUBDEV_FORMAT_TRY: 528 return v4l2_subdev_get_try_crop(&mt9p031->subdev, cfg, pad); 529 case V4L2_SUBDEV_FORMAT_ACTIVE: 530 return &mt9p031->crop; 531 default: 532 return NULL; 533 } 534 } 535 536 static int mt9p031_get_format(struct v4l2_subdev *subdev, 537 struct v4l2_subdev_pad_config *cfg, 538 struct v4l2_subdev_format *fmt) 539 { 540 struct mt9p031 *mt9p031 = to_mt9p031(subdev); 541 542 fmt->format = *__mt9p031_get_pad_format(mt9p031, cfg, fmt->pad, 543 fmt->which); 544 return 0; 545 } 546 547 static int mt9p031_set_format(struct v4l2_subdev *subdev, 548 struct v4l2_subdev_pad_config *cfg, 549 struct v4l2_subdev_format *format) 550 { 551 struct mt9p031 *mt9p031 = to_mt9p031(subdev); 552 struct v4l2_mbus_framefmt *__format; 553 struct v4l2_rect *__crop; 554 unsigned int width; 555 unsigned int height; 556 unsigned int hratio; 557 unsigned int vratio; 558 559 __crop = __mt9p031_get_pad_crop(mt9p031, cfg, format->pad, 560 format->which); 561 562 /* Clamp the width and height to avoid dividing by zero. */ 563 width = clamp_t(unsigned int, ALIGN(format->format.width, 2), 564 max_t(unsigned int, __crop->width / 7, 565 MT9P031_WINDOW_WIDTH_MIN), 566 __crop->width); 567 height = clamp_t(unsigned int, ALIGN(format->format.height, 2), 568 max_t(unsigned int, __crop->height / 8, 569 MT9P031_WINDOW_HEIGHT_MIN), 570 __crop->height); 571 572 hratio = DIV_ROUND_CLOSEST(__crop->width, width); 573 vratio = DIV_ROUND_CLOSEST(__crop->height, height); 574 575 __format = __mt9p031_get_pad_format(mt9p031, cfg, format->pad, 576 format->which); 577 __format->width = __crop->width / hratio; 578 __format->height = __crop->height / vratio; 579 580 format->format = *__format; 581 582 return 0; 583 } 584 585 static int mt9p031_get_selection(struct v4l2_subdev *subdev, 586 struct v4l2_subdev_pad_config *cfg, 587 struct v4l2_subdev_selection *sel) 588 { 589 struct mt9p031 *mt9p031 = to_mt9p031(subdev); 590 591 if (sel->target != V4L2_SEL_TGT_CROP) 592 return -EINVAL; 593 594 sel->r = *__mt9p031_get_pad_crop(mt9p031, cfg, sel->pad, sel->which); 595 return 0; 596 } 597 598 static int mt9p031_set_selection(struct v4l2_subdev *subdev, 599 struct v4l2_subdev_pad_config *cfg, 600 struct v4l2_subdev_selection *sel) 601 { 602 struct mt9p031 *mt9p031 = to_mt9p031(subdev); 603 struct v4l2_mbus_framefmt *__format; 604 struct v4l2_rect *__crop; 605 struct v4l2_rect rect; 606 607 if (sel->target != V4L2_SEL_TGT_CROP) 608 return -EINVAL; 609 610 /* Clamp the crop rectangle boundaries and align them to a multiple of 2 611 * pixels to ensure a GRBG Bayer pattern. 612 */ 613 rect.left = clamp(ALIGN(sel->r.left, 2), MT9P031_COLUMN_START_MIN, 614 MT9P031_COLUMN_START_MAX); 615 rect.top = clamp(ALIGN(sel->r.top, 2), MT9P031_ROW_START_MIN, 616 MT9P031_ROW_START_MAX); 617 rect.width = clamp_t(unsigned int, ALIGN(sel->r.width, 2), 618 MT9P031_WINDOW_WIDTH_MIN, 619 MT9P031_WINDOW_WIDTH_MAX); 620 rect.height = clamp_t(unsigned int, ALIGN(sel->r.height, 2), 621 MT9P031_WINDOW_HEIGHT_MIN, 622 MT9P031_WINDOW_HEIGHT_MAX); 623 624 rect.width = min_t(unsigned int, rect.width, 625 MT9P031_PIXEL_ARRAY_WIDTH - rect.left); 626 rect.height = min_t(unsigned int, rect.height, 627 MT9P031_PIXEL_ARRAY_HEIGHT - rect.top); 628 629 __crop = __mt9p031_get_pad_crop(mt9p031, cfg, sel->pad, sel->which); 630 631 if (rect.width != __crop->width || rect.height != __crop->height) { 632 /* Reset the output image size if the crop rectangle size has 633 * been modified. 634 */ 635 __format = __mt9p031_get_pad_format(mt9p031, cfg, sel->pad, 636 sel->which); 637 __format->width = rect.width; 638 __format->height = rect.height; 639 } 640 641 *__crop = rect; 642 sel->r = rect; 643 644 return 0; 645 } 646 647 /* ----------------------------------------------------------------------------- 648 * V4L2 subdev control operations 649 */ 650 651 #define V4L2_CID_BLC_AUTO (V4L2_CID_USER_BASE | 0x1002) 652 #define V4L2_CID_BLC_TARGET_LEVEL (V4L2_CID_USER_BASE | 0x1003) 653 #define V4L2_CID_BLC_ANALOG_OFFSET (V4L2_CID_USER_BASE | 0x1004) 654 #define V4L2_CID_BLC_DIGITAL_OFFSET (V4L2_CID_USER_BASE | 0x1005) 655 656 static int mt9p031_restore_blc(struct mt9p031 *mt9p031) 657 { 658 struct i2c_client *client = v4l2_get_subdevdata(&mt9p031->subdev); 659 int ret; 660 661 if (mt9p031->blc_auto->cur.val != 0) { 662 ret = mt9p031_set_mode2(mt9p031, 0, 663 MT9P031_READ_MODE_2_ROW_BLC); 664 if (ret < 0) 665 return ret; 666 } 667 668 if (mt9p031->blc_offset->cur.val != 0) { 669 ret = mt9p031_write(client, MT9P031_ROW_BLACK_TARGET, 670 mt9p031->blc_offset->cur.val); 671 if (ret < 0) 672 return ret; 673 } 674 675 return 0; 676 } 677 678 static int mt9p031_s_ctrl(struct v4l2_ctrl *ctrl) 679 { 680 struct mt9p031 *mt9p031 = 681 container_of(ctrl->handler, struct mt9p031, ctrls); 682 struct i2c_client *client = v4l2_get_subdevdata(&mt9p031->subdev); 683 u16 data; 684 int ret; 685 686 if (ctrl->flags & V4L2_CTRL_FLAG_INACTIVE) 687 return 0; 688 689 switch (ctrl->id) { 690 case V4L2_CID_EXPOSURE: 691 ret = mt9p031_write(client, MT9P031_SHUTTER_WIDTH_UPPER, 692 (ctrl->val >> 16) & 0xffff); 693 if (ret < 0) 694 return ret; 695 696 return mt9p031_write(client, MT9P031_SHUTTER_WIDTH_LOWER, 697 ctrl->val & 0xffff); 698 699 case V4L2_CID_GAIN: 700 /* Gain is controlled by 2 analog stages and a digital stage. 701 * Valid values for the 3 stages are 702 * 703 * Stage Min Max Step 704 * ------------------------------------------ 705 * First analog stage x1 x2 1 706 * Second analog stage x1 x4 0.125 707 * Digital stage x1 x16 0.125 708 * 709 * To minimize noise, the gain stages should be used in the 710 * second analog stage, first analog stage, digital stage order. 711 * Gain from a previous stage should be pushed to its maximum 712 * value before the next stage is used. 713 */ 714 if (ctrl->val <= 32) { 715 data = ctrl->val; 716 } else if (ctrl->val <= 64) { 717 ctrl->val &= ~1; 718 data = (1 << 6) | (ctrl->val >> 1); 719 } else { 720 ctrl->val &= ~7; 721 data = ((ctrl->val - 64) << 5) | (1 << 6) | 32; 722 } 723 724 return mt9p031_write(client, MT9P031_GLOBAL_GAIN, data); 725 726 case V4L2_CID_HFLIP: 727 if (ctrl->val) 728 return mt9p031_set_mode2(mt9p031, 729 0, MT9P031_READ_MODE_2_COL_MIR); 730 else 731 return mt9p031_set_mode2(mt9p031, 732 MT9P031_READ_MODE_2_COL_MIR, 0); 733 734 case V4L2_CID_VFLIP: 735 if (ctrl->val) 736 return mt9p031_set_mode2(mt9p031, 737 0, MT9P031_READ_MODE_2_ROW_MIR); 738 else 739 return mt9p031_set_mode2(mt9p031, 740 MT9P031_READ_MODE_2_ROW_MIR, 0); 741 742 case V4L2_CID_TEST_PATTERN: 743 /* The digital side of the Black Level Calibration function must 744 * be disabled when generating a test pattern to avoid artifacts 745 * in the image. Activate (deactivate) the BLC-related controls 746 * when the test pattern is enabled (disabled). 747 */ 748 v4l2_ctrl_activate(mt9p031->blc_auto, ctrl->val == 0); 749 v4l2_ctrl_activate(mt9p031->blc_offset, ctrl->val == 0); 750 751 if (!ctrl->val) { 752 /* Restore the BLC settings. */ 753 ret = mt9p031_restore_blc(mt9p031); 754 if (ret < 0) 755 return ret; 756 757 return mt9p031_write(client, MT9P031_TEST_PATTERN, 758 MT9P031_TEST_PATTERN_DISABLE); 759 } 760 761 ret = mt9p031_write(client, MT9P031_TEST_PATTERN_GREEN, 0x05a0); 762 if (ret < 0) 763 return ret; 764 ret = mt9p031_write(client, MT9P031_TEST_PATTERN_RED, 0x0a50); 765 if (ret < 0) 766 return ret; 767 ret = mt9p031_write(client, MT9P031_TEST_PATTERN_BLUE, 0x0aa0); 768 if (ret < 0) 769 return ret; 770 771 /* Disable digital BLC when generating a test pattern. */ 772 ret = mt9p031_set_mode2(mt9p031, MT9P031_READ_MODE_2_ROW_BLC, 773 0); 774 if (ret < 0) 775 return ret; 776 777 ret = mt9p031_write(client, MT9P031_ROW_BLACK_DEF_OFFSET, 0); 778 if (ret < 0) 779 return ret; 780 781 return mt9p031_write(client, MT9P031_TEST_PATTERN, 782 ((ctrl->val - 1) << MT9P031_TEST_PATTERN_SHIFT) 783 | MT9P031_TEST_PATTERN_ENABLE); 784 785 case V4L2_CID_BLC_AUTO: 786 ret = mt9p031_set_mode2(mt9p031, 787 ctrl->val ? 0 : MT9P031_READ_MODE_2_ROW_BLC, 788 ctrl->val ? MT9P031_READ_MODE_2_ROW_BLC : 0); 789 if (ret < 0) 790 return ret; 791 792 return mt9p031_write(client, MT9P031_BLACK_LEVEL_CALIBRATION, 793 ctrl->val ? 0 : MT9P031_BLC_MANUAL_BLC); 794 795 case V4L2_CID_BLC_TARGET_LEVEL: 796 return mt9p031_write(client, MT9P031_ROW_BLACK_TARGET, 797 ctrl->val); 798 799 case V4L2_CID_BLC_ANALOG_OFFSET: 800 data = ctrl->val & ((1 << 9) - 1); 801 802 ret = mt9p031_write(client, MT9P031_GREEN1_OFFSET, data); 803 if (ret < 0) 804 return ret; 805 ret = mt9p031_write(client, MT9P031_GREEN2_OFFSET, data); 806 if (ret < 0) 807 return ret; 808 ret = mt9p031_write(client, MT9P031_RED_OFFSET, data); 809 if (ret < 0) 810 return ret; 811 return mt9p031_write(client, MT9P031_BLUE_OFFSET, data); 812 813 case V4L2_CID_BLC_DIGITAL_OFFSET: 814 return mt9p031_write(client, MT9P031_ROW_BLACK_DEF_OFFSET, 815 ctrl->val & ((1 << 12) - 1)); 816 } 817 818 return 0; 819 } 820 821 static struct v4l2_ctrl_ops mt9p031_ctrl_ops = { 822 .s_ctrl = mt9p031_s_ctrl, 823 }; 824 825 static const char * const mt9p031_test_pattern_menu[] = { 826 "Disabled", 827 "Color Field", 828 "Horizontal Gradient", 829 "Vertical Gradient", 830 "Diagonal Gradient", 831 "Classic Test Pattern", 832 "Walking 1s", 833 "Monochrome Horizontal Bars", 834 "Monochrome Vertical Bars", 835 "Vertical Color Bars", 836 }; 837 838 static const struct v4l2_ctrl_config mt9p031_ctrls[] = { 839 { 840 .ops = &mt9p031_ctrl_ops, 841 .id = V4L2_CID_BLC_AUTO, 842 .type = V4L2_CTRL_TYPE_BOOLEAN, 843 .name = "BLC, Auto", 844 .min = 0, 845 .max = 1, 846 .step = 1, 847 .def = 1, 848 .flags = 0, 849 }, { 850 .ops = &mt9p031_ctrl_ops, 851 .id = V4L2_CID_BLC_TARGET_LEVEL, 852 .type = V4L2_CTRL_TYPE_INTEGER, 853 .name = "BLC Target Level", 854 .min = 0, 855 .max = 4095, 856 .step = 1, 857 .def = 168, 858 .flags = 0, 859 }, { 860 .ops = &mt9p031_ctrl_ops, 861 .id = V4L2_CID_BLC_ANALOG_OFFSET, 862 .type = V4L2_CTRL_TYPE_INTEGER, 863 .name = "BLC Analog Offset", 864 .min = -255, 865 .max = 255, 866 .step = 1, 867 .def = 32, 868 .flags = 0, 869 }, { 870 .ops = &mt9p031_ctrl_ops, 871 .id = V4L2_CID_BLC_DIGITAL_OFFSET, 872 .type = V4L2_CTRL_TYPE_INTEGER, 873 .name = "BLC Digital Offset", 874 .min = -2048, 875 .max = 2047, 876 .step = 1, 877 .def = 40, 878 .flags = 0, 879 } 880 }; 881 882 /* ----------------------------------------------------------------------------- 883 * V4L2 subdev core operations 884 */ 885 886 static int mt9p031_set_power(struct v4l2_subdev *subdev, int on) 887 { 888 struct mt9p031 *mt9p031 = to_mt9p031(subdev); 889 int ret = 0; 890 891 mutex_lock(&mt9p031->power_lock); 892 893 /* If the power count is modified from 0 to != 0 or from != 0 to 0, 894 * update the power state. 895 */ 896 if (mt9p031->power_count == !on) { 897 ret = __mt9p031_set_power(mt9p031, !!on); 898 if (ret < 0) 899 goto out; 900 } 901 902 /* Update the power count. */ 903 mt9p031->power_count += on ? 1 : -1; 904 WARN_ON(mt9p031->power_count < 0); 905 906 out: 907 mutex_unlock(&mt9p031->power_lock); 908 return ret; 909 } 910 911 /* ----------------------------------------------------------------------------- 912 * V4L2 subdev internal operations 913 */ 914 915 static int mt9p031_registered(struct v4l2_subdev *subdev) 916 { 917 struct i2c_client *client = v4l2_get_subdevdata(subdev); 918 struct mt9p031 *mt9p031 = to_mt9p031(subdev); 919 s32 data; 920 int ret; 921 922 ret = mt9p031_power_on(mt9p031); 923 if (ret < 0) { 924 dev_err(&client->dev, "MT9P031 power up failed\n"); 925 return ret; 926 } 927 928 /* Read out the chip version register */ 929 data = mt9p031_read(client, MT9P031_CHIP_VERSION); 930 mt9p031_power_off(mt9p031); 931 932 if (data != MT9P031_CHIP_VERSION_VALUE) { 933 dev_err(&client->dev, "MT9P031 not detected, wrong version " 934 "0x%04x\n", data); 935 return -ENODEV; 936 } 937 938 dev_info(&client->dev, "MT9P031 detected at address 0x%02x\n", 939 client->addr); 940 941 return 0; 942 } 943 944 static int mt9p031_open(struct v4l2_subdev *subdev, struct v4l2_subdev_fh *fh) 945 { 946 struct mt9p031 *mt9p031 = to_mt9p031(subdev); 947 struct v4l2_mbus_framefmt *format; 948 struct v4l2_rect *crop; 949 950 crop = v4l2_subdev_get_try_crop(subdev, fh->pad, 0); 951 crop->left = MT9P031_COLUMN_START_DEF; 952 crop->top = MT9P031_ROW_START_DEF; 953 crop->width = MT9P031_WINDOW_WIDTH_DEF; 954 crop->height = MT9P031_WINDOW_HEIGHT_DEF; 955 956 format = v4l2_subdev_get_try_format(subdev, fh->pad, 0); 957 958 if (mt9p031->model == MT9P031_MODEL_MONOCHROME) 959 format->code = MEDIA_BUS_FMT_Y12_1X12; 960 else 961 format->code = MEDIA_BUS_FMT_SGRBG12_1X12; 962 963 format->width = MT9P031_WINDOW_WIDTH_DEF; 964 format->height = MT9P031_WINDOW_HEIGHT_DEF; 965 format->field = V4L2_FIELD_NONE; 966 format->colorspace = V4L2_COLORSPACE_SRGB; 967 968 return mt9p031_set_power(subdev, 1); 969 } 970 971 static int mt9p031_close(struct v4l2_subdev *subdev, struct v4l2_subdev_fh *fh) 972 { 973 return mt9p031_set_power(subdev, 0); 974 } 975 976 static struct v4l2_subdev_core_ops mt9p031_subdev_core_ops = { 977 .s_power = mt9p031_set_power, 978 }; 979 980 static struct v4l2_subdev_video_ops mt9p031_subdev_video_ops = { 981 .s_stream = mt9p031_s_stream, 982 }; 983 984 static struct v4l2_subdev_pad_ops mt9p031_subdev_pad_ops = { 985 .enum_mbus_code = mt9p031_enum_mbus_code, 986 .enum_frame_size = mt9p031_enum_frame_size, 987 .get_fmt = mt9p031_get_format, 988 .set_fmt = mt9p031_set_format, 989 .get_selection = mt9p031_get_selection, 990 .set_selection = mt9p031_set_selection, 991 }; 992 993 static struct v4l2_subdev_ops mt9p031_subdev_ops = { 994 .core = &mt9p031_subdev_core_ops, 995 .video = &mt9p031_subdev_video_ops, 996 .pad = &mt9p031_subdev_pad_ops, 997 }; 998 999 static const struct v4l2_subdev_internal_ops mt9p031_subdev_internal_ops = { 1000 .registered = mt9p031_registered, 1001 .open = mt9p031_open, 1002 .close = mt9p031_close, 1003 }; 1004 1005 /* ----------------------------------------------------------------------------- 1006 * Driver initialization and probing 1007 */ 1008 1009 static struct mt9p031_platform_data * 1010 mt9p031_get_pdata(struct i2c_client *client) 1011 { 1012 struct mt9p031_platform_data *pdata; 1013 struct device_node *np; 1014 1015 if (!IS_ENABLED(CONFIG_OF) || !client->dev.of_node) 1016 return client->dev.platform_data; 1017 1018 np = of_graph_get_next_endpoint(client->dev.of_node, NULL); 1019 if (!np) 1020 return NULL; 1021 1022 pdata = devm_kzalloc(&client->dev, sizeof(*pdata), GFP_KERNEL); 1023 if (!pdata) 1024 goto done; 1025 1026 pdata->reset = of_get_named_gpio(client->dev.of_node, "reset-gpios", 0); 1027 of_property_read_u32(np, "input-clock-frequency", &pdata->ext_freq); 1028 of_property_read_u32(np, "pixel-clock-frequency", &pdata->target_freq); 1029 1030 done: 1031 of_node_put(np); 1032 return pdata; 1033 } 1034 1035 static int mt9p031_probe(struct i2c_client *client, 1036 const struct i2c_device_id *did) 1037 { 1038 struct mt9p031_platform_data *pdata = mt9p031_get_pdata(client); 1039 struct i2c_adapter *adapter = to_i2c_adapter(client->dev.parent); 1040 struct mt9p031 *mt9p031; 1041 unsigned int i; 1042 int ret; 1043 1044 if (pdata == NULL) { 1045 dev_err(&client->dev, "No platform data\n"); 1046 return -EINVAL; 1047 } 1048 1049 if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_WORD_DATA)) { 1050 dev_warn(&client->dev, 1051 "I2C-Adapter doesn't support I2C_FUNC_SMBUS_WORD\n"); 1052 return -EIO; 1053 } 1054 1055 mt9p031 = devm_kzalloc(&client->dev, sizeof(*mt9p031), GFP_KERNEL); 1056 if (mt9p031 == NULL) 1057 return -ENOMEM; 1058 1059 mt9p031->pdata = pdata; 1060 mt9p031->output_control = MT9P031_OUTPUT_CONTROL_DEF; 1061 mt9p031->mode2 = MT9P031_READ_MODE_2_ROW_BLC; 1062 mt9p031->model = did->driver_data; 1063 mt9p031->reset = -1; 1064 1065 mt9p031->regulators[0].supply = "vdd"; 1066 mt9p031->regulators[1].supply = "vdd_io"; 1067 mt9p031->regulators[2].supply = "vaa"; 1068 1069 ret = devm_regulator_bulk_get(&client->dev, 3, mt9p031->regulators); 1070 if (ret < 0) { 1071 dev_err(&client->dev, "Unable to get regulators\n"); 1072 return ret; 1073 } 1074 1075 mutex_init(&mt9p031->power_lock); 1076 1077 v4l2_ctrl_handler_init(&mt9p031->ctrls, ARRAY_SIZE(mt9p031_ctrls) + 6); 1078 1079 v4l2_ctrl_new_std(&mt9p031->ctrls, &mt9p031_ctrl_ops, 1080 V4L2_CID_EXPOSURE, MT9P031_SHUTTER_WIDTH_MIN, 1081 MT9P031_SHUTTER_WIDTH_MAX, 1, 1082 MT9P031_SHUTTER_WIDTH_DEF); 1083 v4l2_ctrl_new_std(&mt9p031->ctrls, &mt9p031_ctrl_ops, 1084 V4L2_CID_GAIN, MT9P031_GLOBAL_GAIN_MIN, 1085 MT9P031_GLOBAL_GAIN_MAX, 1, MT9P031_GLOBAL_GAIN_DEF); 1086 v4l2_ctrl_new_std(&mt9p031->ctrls, &mt9p031_ctrl_ops, 1087 V4L2_CID_HFLIP, 0, 1, 1, 0); 1088 v4l2_ctrl_new_std(&mt9p031->ctrls, &mt9p031_ctrl_ops, 1089 V4L2_CID_VFLIP, 0, 1, 1, 0); 1090 v4l2_ctrl_new_std(&mt9p031->ctrls, &mt9p031_ctrl_ops, 1091 V4L2_CID_PIXEL_RATE, pdata->target_freq, 1092 pdata->target_freq, 1, pdata->target_freq); 1093 v4l2_ctrl_new_std_menu_items(&mt9p031->ctrls, &mt9p031_ctrl_ops, 1094 V4L2_CID_TEST_PATTERN, 1095 ARRAY_SIZE(mt9p031_test_pattern_menu) - 1, 0, 1096 0, mt9p031_test_pattern_menu); 1097 1098 for (i = 0; i < ARRAY_SIZE(mt9p031_ctrls); ++i) 1099 v4l2_ctrl_new_custom(&mt9p031->ctrls, &mt9p031_ctrls[i], NULL); 1100 1101 mt9p031->subdev.ctrl_handler = &mt9p031->ctrls; 1102 1103 if (mt9p031->ctrls.error) { 1104 printk(KERN_INFO "%s: control initialization error %d\n", 1105 __func__, mt9p031->ctrls.error); 1106 ret = mt9p031->ctrls.error; 1107 goto done; 1108 } 1109 1110 mt9p031->blc_auto = v4l2_ctrl_find(&mt9p031->ctrls, V4L2_CID_BLC_AUTO); 1111 mt9p031->blc_offset = v4l2_ctrl_find(&mt9p031->ctrls, 1112 V4L2_CID_BLC_DIGITAL_OFFSET); 1113 1114 v4l2_i2c_subdev_init(&mt9p031->subdev, client, &mt9p031_subdev_ops); 1115 mt9p031->subdev.internal_ops = &mt9p031_subdev_internal_ops; 1116 1117 mt9p031->pad.flags = MEDIA_PAD_FL_SOURCE; 1118 ret = media_entity_init(&mt9p031->subdev.entity, 1, &mt9p031->pad, 0); 1119 if (ret < 0) 1120 goto done; 1121 1122 mt9p031->subdev.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; 1123 1124 mt9p031->crop.width = MT9P031_WINDOW_WIDTH_DEF; 1125 mt9p031->crop.height = MT9P031_WINDOW_HEIGHT_DEF; 1126 mt9p031->crop.left = MT9P031_COLUMN_START_DEF; 1127 mt9p031->crop.top = MT9P031_ROW_START_DEF; 1128 1129 if (mt9p031->model == MT9P031_MODEL_MONOCHROME) 1130 mt9p031->format.code = MEDIA_BUS_FMT_Y12_1X12; 1131 else 1132 mt9p031->format.code = MEDIA_BUS_FMT_SGRBG12_1X12; 1133 1134 mt9p031->format.width = MT9P031_WINDOW_WIDTH_DEF; 1135 mt9p031->format.height = MT9P031_WINDOW_HEIGHT_DEF; 1136 mt9p031->format.field = V4L2_FIELD_NONE; 1137 mt9p031->format.colorspace = V4L2_COLORSPACE_SRGB; 1138 1139 if (gpio_is_valid(pdata->reset)) { 1140 ret = devm_gpio_request_one(&client->dev, pdata->reset, 1141 GPIOF_OUT_INIT_LOW, "mt9p031_rst"); 1142 if (ret < 0) 1143 goto done; 1144 1145 mt9p031->reset = pdata->reset; 1146 } 1147 1148 ret = mt9p031_clk_setup(mt9p031); 1149 if (ret) 1150 goto done; 1151 1152 ret = v4l2_async_register_subdev(&mt9p031->subdev); 1153 1154 done: 1155 if (ret < 0) { 1156 v4l2_ctrl_handler_free(&mt9p031->ctrls); 1157 media_entity_cleanup(&mt9p031->subdev.entity); 1158 mutex_destroy(&mt9p031->power_lock); 1159 } 1160 1161 return ret; 1162 } 1163 1164 static int mt9p031_remove(struct i2c_client *client) 1165 { 1166 struct v4l2_subdev *subdev = i2c_get_clientdata(client); 1167 struct mt9p031 *mt9p031 = to_mt9p031(subdev); 1168 1169 v4l2_ctrl_handler_free(&mt9p031->ctrls); 1170 v4l2_async_unregister_subdev(subdev); 1171 media_entity_cleanup(&subdev->entity); 1172 mutex_destroy(&mt9p031->power_lock); 1173 1174 return 0; 1175 } 1176 1177 static const struct i2c_device_id mt9p031_id[] = { 1178 { "mt9p031", MT9P031_MODEL_COLOR }, 1179 { "mt9p031m", MT9P031_MODEL_MONOCHROME }, 1180 { } 1181 }; 1182 MODULE_DEVICE_TABLE(i2c, mt9p031_id); 1183 1184 #if IS_ENABLED(CONFIG_OF) 1185 static const struct of_device_id mt9p031_of_match[] = { 1186 { .compatible = "aptina,mt9p031", }, 1187 { .compatible = "aptina,mt9p031m", }, 1188 { /* sentinel */ }, 1189 }; 1190 MODULE_DEVICE_TABLE(of, mt9p031_of_match); 1191 #endif 1192 1193 static struct i2c_driver mt9p031_i2c_driver = { 1194 .driver = { 1195 .of_match_table = of_match_ptr(mt9p031_of_match), 1196 .name = "mt9p031", 1197 }, 1198 .probe = mt9p031_probe, 1199 .remove = mt9p031_remove, 1200 .id_table = mt9p031_id, 1201 }; 1202 1203 module_i2c_driver(mt9p031_i2c_driver); 1204 1205 MODULE_DESCRIPTION("Aptina MT9P031 Camera driver"); 1206 MODULE_AUTHOR("Bastian Hecht <hechtb@gmail.com>"); 1207 MODULE_LICENSE("GPL v2"); 1208