1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Driver for MT9P031 CMOS Image Sensor from Aptina 4 * 5 * Copyright (C) 2011, Laurent Pinchart <laurent.pinchart@ideasonboard.com> 6 * Copyright (C) 2011, Javier Martin <javier.martin@vista-silicon.com> 7 * Copyright (C) 2011, Guennadi Liakhovetski <g.liakhovetski@gmx.de> 8 * 9 * Based on the MT9V032 driver and Bastian Hecht's code. 10 */ 11 12 #include <linux/clk.h> 13 #include <linux/delay.h> 14 #include <linux/device.h> 15 #include <linux/gpio/consumer.h> 16 #include <linux/i2c.h> 17 #include <linux/log2.h> 18 #include <linux/module.h> 19 #include <linux/of.h> 20 #include <linux/of_graph.h> 21 #include <linux/pm.h> 22 #include <linux/regulator/consumer.h> 23 #include <linux/slab.h> 24 #include <linux/videodev2.h> 25 26 #include <media/i2c/mt9p031.h> 27 #include <media/v4l2-async.h> 28 #include <media/v4l2-ctrls.h> 29 #include <media/v4l2-device.h> 30 #include <media/v4l2-fwnode.h> 31 #include <media/v4l2-subdev.h> 32 33 #include "aptina-pll.h" 34 35 #define MT9P031_PIXEL_ARRAY_WIDTH 2752 36 #define MT9P031_PIXEL_ARRAY_HEIGHT 2004 37 38 #define MT9P031_CHIP_VERSION 0x00 39 #define MT9P031_CHIP_VERSION_VALUE 0x1801 40 #define MT9P031_ROW_START 0x01 41 #define MT9P031_ROW_START_MIN 0 42 #define MT9P031_ROW_START_MAX 2004 43 #define MT9P031_ROW_START_DEF 54 44 #define MT9P031_COLUMN_START 0x02 45 #define MT9P031_COLUMN_START_MIN 0 46 #define MT9P031_COLUMN_START_MAX 2750 47 #define MT9P031_COLUMN_START_DEF 16 48 #define MT9P031_WINDOW_HEIGHT 0x03 49 #define MT9P031_WINDOW_HEIGHT_MIN 2 50 #define MT9P031_WINDOW_HEIGHT_MAX 2006 51 #define MT9P031_WINDOW_HEIGHT_DEF 1944 52 #define MT9P031_WINDOW_WIDTH 0x04 53 #define MT9P031_WINDOW_WIDTH_MIN 2 54 #define MT9P031_WINDOW_WIDTH_MAX 2752 55 #define MT9P031_WINDOW_WIDTH_DEF 2592 56 #define MT9P031_HORIZONTAL_BLANK 0x05 57 #define MT9P031_HORIZONTAL_BLANK_MIN 0 58 #define MT9P031_HORIZONTAL_BLANK_MAX 4095 59 #define MT9P031_VERTICAL_BLANK 0x06 60 #define MT9P031_VERTICAL_BLANK_MIN 1 61 #define MT9P031_VERTICAL_BLANK_MAX 4096 62 #define MT9P031_VERTICAL_BLANK_DEF 26 63 #define MT9P031_OUTPUT_CONTROL 0x07 64 #define MT9P031_OUTPUT_CONTROL_CEN 2 65 #define MT9P031_OUTPUT_CONTROL_SYN 1 66 #define MT9P031_OUTPUT_CONTROL_DEF 0x1f82 67 #define MT9P031_SHUTTER_WIDTH_UPPER 0x08 68 #define MT9P031_SHUTTER_WIDTH_LOWER 0x09 69 #define MT9P031_SHUTTER_WIDTH_MIN 1 70 #define MT9P031_SHUTTER_WIDTH_MAX 1048575 71 #define MT9P031_SHUTTER_WIDTH_DEF 1943 72 #define MT9P031_PLL_CONTROL 0x10 73 #define MT9P031_PLL_CONTROL_PWROFF 0x0050 74 #define MT9P031_PLL_CONTROL_PWRON 0x0051 75 #define MT9P031_PLL_CONTROL_USEPLL 0x0052 76 #define MT9P031_PLL_CONFIG_1 0x11 77 #define MT9P031_PLL_CONFIG_2 0x12 78 #define MT9P031_PIXEL_CLOCK_CONTROL 0x0a 79 #define MT9P031_PIXEL_CLOCK_INVERT (1 << 15) 80 #define MT9P031_PIXEL_CLOCK_SHIFT(n) ((n) << 8) 81 #define MT9P031_PIXEL_CLOCK_DIVIDE(n) ((n) << 0) 82 #define MT9P031_RESTART 0x0b 83 #define MT9P031_FRAME_PAUSE_RESTART (1 << 1) 84 #define MT9P031_FRAME_RESTART (1 << 0) 85 #define MT9P031_SHUTTER_DELAY 0x0c 86 #define MT9P031_RST 0x0d 87 #define MT9P031_RST_ENABLE 1 88 #define MT9P031_RST_DISABLE 0 89 #define MT9P031_READ_MODE_1 0x1e 90 #define MT9P031_READ_MODE_2 0x20 91 #define MT9P031_READ_MODE_2_ROW_MIR (1 << 15) 92 #define MT9P031_READ_MODE_2_COL_MIR (1 << 14) 93 #define MT9P031_READ_MODE_2_ROW_BLC (1 << 6) 94 #define MT9P031_ROW_ADDRESS_MODE 0x22 95 #define MT9P031_COLUMN_ADDRESS_MODE 0x23 96 #define MT9P031_GLOBAL_GAIN 0x35 97 #define MT9P031_GLOBAL_GAIN_MIN 8 98 #define MT9P031_GLOBAL_GAIN_MAX 1024 99 #define MT9P031_GLOBAL_GAIN_DEF 8 100 #define MT9P031_GLOBAL_GAIN_MULT (1 << 6) 101 #define MT9P031_ROW_BLACK_TARGET 0x49 102 #define MT9P031_ROW_BLACK_DEF_OFFSET 0x4b 103 #define MT9P031_GREEN1_OFFSET 0x60 104 #define MT9P031_GREEN2_OFFSET 0x61 105 #define MT9P031_BLACK_LEVEL_CALIBRATION 0x62 106 #define MT9P031_BLC_MANUAL_BLC (1 << 0) 107 #define MT9P031_RED_OFFSET 0x63 108 #define MT9P031_BLUE_OFFSET 0x64 109 #define MT9P031_TEST_PATTERN 0xa0 110 #define MT9P031_TEST_PATTERN_SHIFT 3 111 #define MT9P031_TEST_PATTERN_ENABLE (1 << 0) 112 #define MT9P031_TEST_PATTERN_DISABLE (0 << 0) 113 #define MT9P031_TEST_PATTERN_GREEN 0xa1 114 #define MT9P031_TEST_PATTERN_RED 0xa2 115 #define MT9P031_TEST_PATTERN_BLUE 0xa3 116 117 enum mt9p031_model { 118 MT9P031_MODEL_COLOR, 119 MT9P031_MODEL_MONOCHROME, 120 }; 121 122 struct mt9p031 { 123 struct v4l2_subdev subdev; 124 struct media_pad pad; 125 struct v4l2_rect crop; /* Sensor window */ 126 struct v4l2_mbus_framefmt format; 127 struct mt9p031_platform_data *pdata; 128 struct mutex power_lock; /* lock to protect power_count */ 129 int power_count; 130 131 struct clk *clk; 132 struct regulator_bulk_data regulators[3]; 133 134 enum mt9p031_model model; 135 struct aptina_pll pll; 136 unsigned int clk_div; 137 bool use_pll; 138 struct gpio_desc *reset; 139 140 struct v4l2_ctrl_handler ctrls; 141 struct v4l2_ctrl *blc_auto; 142 struct v4l2_ctrl *blc_offset; 143 144 /* Registers cache */ 145 u16 output_control; 146 u16 mode2; 147 }; 148 149 static struct mt9p031 *to_mt9p031(struct v4l2_subdev *sd) 150 { 151 return container_of(sd, struct mt9p031, subdev); 152 } 153 154 static int mt9p031_read(struct i2c_client *client, u8 reg) 155 { 156 return i2c_smbus_read_word_swapped(client, reg); 157 } 158 159 static int mt9p031_write(struct i2c_client *client, u8 reg, u16 data) 160 { 161 return i2c_smbus_write_word_swapped(client, reg, data); 162 } 163 164 static int mt9p031_set_output_control(struct mt9p031 *mt9p031, u16 clear, 165 u16 set) 166 { 167 struct i2c_client *client = v4l2_get_subdevdata(&mt9p031->subdev); 168 u16 value = (mt9p031->output_control & ~clear) | set; 169 int ret; 170 171 ret = mt9p031_write(client, MT9P031_OUTPUT_CONTROL, value); 172 if (ret < 0) 173 return ret; 174 175 mt9p031->output_control = value; 176 return 0; 177 } 178 179 static int mt9p031_set_mode2(struct mt9p031 *mt9p031, u16 clear, u16 set) 180 { 181 struct i2c_client *client = v4l2_get_subdevdata(&mt9p031->subdev); 182 u16 value = (mt9p031->mode2 & ~clear) | set; 183 int ret; 184 185 ret = mt9p031_write(client, MT9P031_READ_MODE_2, value); 186 if (ret < 0) 187 return ret; 188 189 mt9p031->mode2 = value; 190 return 0; 191 } 192 193 static int mt9p031_reset(struct mt9p031 *mt9p031) 194 { 195 struct i2c_client *client = v4l2_get_subdevdata(&mt9p031->subdev); 196 int ret; 197 198 /* Disable chip output, synchronous option update */ 199 ret = mt9p031_write(client, MT9P031_RST, MT9P031_RST_ENABLE); 200 if (ret < 0) 201 return ret; 202 ret = mt9p031_write(client, MT9P031_RST, MT9P031_RST_DISABLE); 203 if (ret < 0) 204 return ret; 205 206 ret = mt9p031_write(client, MT9P031_PIXEL_CLOCK_CONTROL, 207 MT9P031_PIXEL_CLOCK_DIVIDE(mt9p031->clk_div)); 208 if (ret < 0) 209 return ret; 210 211 return mt9p031_set_output_control(mt9p031, MT9P031_OUTPUT_CONTROL_CEN, 212 0); 213 } 214 215 static int mt9p031_clk_setup(struct mt9p031 *mt9p031) 216 { 217 static const struct aptina_pll_limits limits = { 218 .ext_clock_min = 6000000, 219 .ext_clock_max = 27000000, 220 .int_clock_min = 2000000, 221 .int_clock_max = 13500000, 222 .out_clock_min = 180000000, 223 .out_clock_max = 360000000, 224 .pix_clock_max = 96000000, 225 .n_min = 1, 226 .n_max = 64, 227 .m_min = 16, 228 .m_max = 255, 229 .p1_min = 1, 230 .p1_max = 128, 231 }; 232 233 struct i2c_client *client = v4l2_get_subdevdata(&mt9p031->subdev); 234 struct mt9p031_platform_data *pdata = mt9p031->pdata; 235 unsigned long ext_freq; 236 int ret; 237 238 mt9p031->clk = devm_clk_get(&client->dev, NULL); 239 if (IS_ERR(mt9p031->clk)) 240 return PTR_ERR(mt9p031->clk); 241 242 ret = clk_set_rate(mt9p031->clk, pdata->ext_freq); 243 if (ret < 0) 244 return ret; 245 246 ext_freq = clk_get_rate(mt9p031->clk); 247 248 /* If the external clock frequency is out of bounds for the PLL use the 249 * pixel clock divider only and disable the PLL. 250 */ 251 if (ext_freq > limits.ext_clock_max) { 252 unsigned int div; 253 254 div = DIV_ROUND_UP(ext_freq, pdata->target_freq); 255 div = roundup_pow_of_two(div) / 2; 256 257 mt9p031->clk_div = min_t(unsigned int, div, 64); 258 mt9p031->use_pll = false; 259 260 return 0; 261 } 262 263 mt9p031->pll.ext_clock = ext_freq; 264 mt9p031->pll.pix_clock = pdata->target_freq; 265 mt9p031->use_pll = true; 266 267 return aptina_pll_calculate(&client->dev, &limits, &mt9p031->pll); 268 } 269 270 static int mt9p031_pll_enable(struct mt9p031 *mt9p031) 271 { 272 struct i2c_client *client = v4l2_get_subdevdata(&mt9p031->subdev); 273 int ret; 274 275 if (!mt9p031->use_pll) 276 return 0; 277 278 ret = mt9p031_write(client, MT9P031_PLL_CONTROL, 279 MT9P031_PLL_CONTROL_PWRON); 280 if (ret < 0) 281 return ret; 282 283 ret = mt9p031_write(client, MT9P031_PLL_CONFIG_1, 284 (mt9p031->pll.m << 8) | (mt9p031->pll.n - 1)); 285 if (ret < 0) 286 return ret; 287 288 ret = mt9p031_write(client, MT9P031_PLL_CONFIG_2, mt9p031->pll.p1 - 1); 289 if (ret < 0) 290 return ret; 291 292 usleep_range(1000, 2000); 293 ret = mt9p031_write(client, MT9P031_PLL_CONTROL, 294 MT9P031_PLL_CONTROL_PWRON | 295 MT9P031_PLL_CONTROL_USEPLL); 296 return ret; 297 } 298 299 static inline int mt9p031_pll_disable(struct mt9p031 *mt9p031) 300 { 301 struct i2c_client *client = v4l2_get_subdevdata(&mt9p031->subdev); 302 303 if (!mt9p031->use_pll) 304 return 0; 305 306 return mt9p031_write(client, MT9P031_PLL_CONTROL, 307 MT9P031_PLL_CONTROL_PWROFF); 308 } 309 310 static int mt9p031_power_on(struct mt9p031 *mt9p031) 311 { 312 int ret; 313 314 /* Ensure RESET_BAR is active */ 315 if (mt9p031->reset) { 316 gpiod_set_value(mt9p031->reset, 1); 317 usleep_range(1000, 2000); 318 } 319 320 /* Bring up the supplies */ 321 ret = regulator_bulk_enable(ARRAY_SIZE(mt9p031->regulators), 322 mt9p031->regulators); 323 if (ret < 0) 324 return ret; 325 326 /* Enable clock */ 327 if (mt9p031->clk) { 328 ret = clk_prepare_enable(mt9p031->clk); 329 if (ret) { 330 regulator_bulk_disable(ARRAY_SIZE(mt9p031->regulators), 331 mt9p031->regulators); 332 return ret; 333 } 334 } 335 336 /* Now RESET_BAR must be high */ 337 if (mt9p031->reset) { 338 gpiod_set_value(mt9p031->reset, 0); 339 usleep_range(1000, 2000); 340 } 341 342 return 0; 343 } 344 345 static void mt9p031_power_off(struct mt9p031 *mt9p031) 346 { 347 if (mt9p031->reset) { 348 gpiod_set_value(mt9p031->reset, 1); 349 usleep_range(1000, 2000); 350 } 351 352 regulator_bulk_disable(ARRAY_SIZE(mt9p031->regulators), 353 mt9p031->regulators); 354 355 clk_disable_unprepare(mt9p031->clk); 356 } 357 358 static int __mt9p031_set_power(struct mt9p031 *mt9p031, bool on) 359 { 360 struct i2c_client *client = v4l2_get_subdevdata(&mt9p031->subdev); 361 int ret; 362 363 if (!on) { 364 mt9p031_power_off(mt9p031); 365 return 0; 366 } 367 368 ret = mt9p031_power_on(mt9p031); 369 if (ret < 0) 370 return ret; 371 372 ret = mt9p031_reset(mt9p031); 373 if (ret < 0) { 374 dev_err(&client->dev, "Failed to reset the camera\n"); 375 return ret; 376 } 377 378 /* Configure the pixel clock polarity */ 379 if (mt9p031->pdata && mt9p031->pdata->pixclk_pol) { 380 ret = mt9p031_write(client, MT9P031_PIXEL_CLOCK_CONTROL, 381 MT9P031_PIXEL_CLOCK_INVERT); 382 if (ret < 0) 383 return ret; 384 } 385 386 return v4l2_ctrl_handler_setup(&mt9p031->ctrls); 387 } 388 389 /* ----------------------------------------------------------------------------- 390 * V4L2 subdev video operations 391 */ 392 393 static int mt9p031_set_params(struct mt9p031 *mt9p031) 394 { 395 struct i2c_client *client = v4l2_get_subdevdata(&mt9p031->subdev); 396 struct v4l2_mbus_framefmt *format = &mt9p031->format; 397 const struct v4l2_rect *crop = &mt9p031->crop; 398 unsigned int hblank; 399 unsigned int vblank; 400 unsigned int xskip; 401 unsigned int yskip; 402 unsigned int xbin; 403 unsigned int ybin; 404 int ret; 405 406 /* Windows position and size. 407 * 408 * TODO: Make sure the start coordinates and window size match the 409 * skipping, binning and mirroring (see description of registers 2 and 4 410 * in table 13, and Binning section on page 41). 411 */ 412 ret = mt9p031_write(client, MT9P031_COLUMN_START, crop->left); 413 if (ret < 0) 414 return ret; 415 ret = mt9p031_write(client, MT9P031_ROW_START, crop->top); 416 if (ret < 0) 417 return ret; 418 ret = mt9p031_write(client, MT9P031_WINDOW_WIDTH, crop->width - 1); 419 if (ret < 0) 420 return ret; 421 ret = mt9p031_write(client, MT9P031_WINDOW_HEIGHT, crop->height - 1); 422 if (ret < 0) 423 return ret; 424 425 /* Row and column binning and skipping. Use the maximum binning value 426 * compatible with the skipping settings. 427 */ 428 xskip = DIV_ROUND_CLOSEST(crop->width, format->width); 429 yskip = DIV_ROUND_CLOSEST(crop->height, format->height); 430 xbin = 1 << (ffs(xskip) - 1); 431 ybin = 1 << (ffs(yskip) - 1); 432 433 ret = mt9p031_write(client, MT9P031_COLUMN_ADDRESS_MODE, 434 ((xbin - 1) << 4) | (xskip - 1)); 435 if (ret < 0) 436 return ret; 437 ret = mt9p031_write(client, MT9P031_ROW_ADDRESS_MODE, 438 ((ybin - 1) << 4) | (yskip - 1)); 439 if (ret < 0) 440 return ret; 441 442 /* Blanking - use minimum value for horizontal blanking and default 443 * value for vertical blanking. 444 */ 445 hblank = 346 * ybin + 64 + (80 >> min_t(unsigned int, xbin, 3)); 446 vblank = MT9P031_VERTICAL_BLANK_DEF; 447 448 ret = mt9p031_write(client, MT9P031_HORIZONTAL_BLANK, hblank - 1); 449 if (ret < 0) 450 return ret; 451 ret = mt9p031_write(client, MT9P031_VERTICAL_BLANK, vblank - 1); 452 if (ret < 0) 453 return ret; 454 455 return ret; 456 } 457 458 static int mt9p031_s_stream(struct v4l2_subdev *subdev, int enable) 459 { 460 struct mt9p031 *mt9p031 = to_mt9p031(subdev); 461 struct i2c_client *client = v4l2_get_subdevdata(subdev); 462 int val; 463 int ret; 464 465 if (!enable) { 466 /* enable pause restart */ 467 val = MT9P031_FRAME_PAUSE_RESTART; 468 ret = mt9p031_write(client, MT9P031_RESTART, val); 469 if (ret < 0) 470 return ret; 471 472 /* enable restart + keep pause restart set */ 473 val |= MT9P031_FRAME_RESTART; 474 ret = mt9p031_write(client, MT9P031_RESTART, val); 475 if (ret < 0) 476 return ret; 477 478 /* Stop sensor readout */ 479 ret = mt9p031_set_output_control(mt9p031, 480 MT9P031_OUTPUT_CONTROL_CEN, 0); 481 if (ret < 0) 482 return ret; 483 484 return mt9p031_pll_disable(mt9p031); 485 } 486 487 ret = mt9p031_set_params(mt9p031); 488 if (ret < 0) 489 return ret; 490 491 /* Switch to master "normal" mode */ 492 ret = mt9p031_set_output_control(mt9p031, 0, 493 MT9P031_OUTPUT_CONTROL_CEN); 494 if (ret < 0) 495 return ret; 496 497 /* 498 * - clear pause restart 499 * - don't clear restart as clearing restart manually can cause 500 * undefined behavior 501 */ 502 val = MT9P031_FRAME_RESTART; 503 ret = mt9p031_write(client, MT9P031_RESTART, val); 504 if (ret < 0) 505 return ret; 506 507 return mt9p031_pll_enable(mt9p031); 508 } 509 510 static int mt9p031_enum_mbus_code(struct v4l2_subdev *subdev, 511 struct v4l2_subdev_state *sd_state, 512 struct v4l2_subdev_mbus_code_enum *code) 513 { 514 struct mt9p031 *mt9p031 = to_mt9p031(subdev); 515 516 if (code->pad || code->index) 517 return -EINVAL; 518 519 code->code = mt9p031->format.code; 520 return 0; 521 } 522 523 static int mt9p031_enum_frame_size(struct v4l2_subdev *subdev, 524 struct v4l2_subdev_state *sd_state, 525 struct v4l2_subdev_frame_size_enum *fse) 526 { 527 struct mt9p031 *mt9p031 = to_mt9p031(subdev); 528 529 if (fse->index >= 8 || fse->code != mt9p031->format.code) 530 return -EINVAL; 531 532 fse->min_width = MT9P031_WINDOW_WIDTH_DEF 533 / min_t(unsigned int, 7, fse->index + 1); 534 fse->max_width = fse->min_width; 535 fse->min_height = MT9P031_WINDOW_HEIGHT_DEF / (fse->index + 1); 536 fse->max_height = fse->min_height; 537 538 return 0; 539 } 540 541 static struct v4l2_mbus_framefmt * 542 __mt9p031_get_pad_format(struct mt9p031 *mt9p031, 543 struct v4l2_subdev_state *sd_state, 544 unsigned int pad, u32 which) 545 { 546 switch (which) { 547 case V4L2_SUBDEV_FORMAT_TRY: 548 return v4l2_subdev_get_try_format(&mt9p031->subdev, sd_state, 549 pad); 550 case V4L2_SUBDEV_FORMAT_ACTIVE: 551 return &mt9p031->format; 552 default: 553 return NULL; 554 } 555 } 556 557 static struct v4l2_rect * 558 __mt9p031_get_pad_crop(struct mt9p031 *mt9p031, 559 struct v4l2_subdev_state *sd_state, 560 unsigned int pad, u32 which) 561 { 562 switch (which) { 563 case V4L2_SUBDEV_FORMAT_TRY: 564 return v4l2_subdev_get_try_crop(&mt9p031->subdev, sd_state, 565 pad); 566 case V4L2_SUBDEV_FORMAT_ACTIVE: 567 return &mt9p031->crop; 568 default: 569 return NULL; 570 } 571 } 572 573 static int mt9p031_get_format(struct v4l2_subdev *subdev, 574 struct v4l2_subdev_state *sd_state, 575 struct v4l2_subdev_format *fmt) 576 { 577 struct mt9p031 *mt9p031 = to_mt9p031(subdev); 578 579 fmt->format = *__mt9p031_get_pad_format(mt9p031, sd_state, fmt->pad, 580 fmt->which); 581 return 0; 582 } 583 584 static int mt9p031_set_format(struct v4l2_subdev *subdev, 585 struct v4l2_subdev_state *sd_state, 586 struct v4l2_subdev_format *format) 587 { 588 struct mt9p031 *mt9p031 = to_mt9p031(subdev); 589 struct v4l2_mbus_framefmt *__format; 590 struct v4l2_rect *__crop; 591 unsigned int width; 592 unsigned int height; 593 unsigned int hratio; 594 unsigned int vratio; 595 596 __crop = __mt9p031_get_pad_crop(mt9p031, sd_state, format->pad, 597 format->which); 598 599 /* Clamp the width and height to avoid dividing by zero. */ 600 width = clamp_t(unsigned int, ALIGN(format->format.width, 2), 601 max_t(unsigned int, __crop->width / 7, 602 MT9P031_WINDOW_WIDTH_MIN), 603 __crop->width); 604 height = clamp_t(unsigned int, ALIGN(format->format.height, 2), 605 max_t(unsigned int, __crop->height / 8, 606 MT9P031_WINDOW_HEIGHT_MIN), 607 __crop->height); 608 609 hratio = DIV_ROUND_CLOSEST(__crop->width, width); 610 vratio = DIV_ROUND_CLOSEST(__crop->height, height); 611 612 __format = __mt9p031_get_pad_format(mt9p031, sd_state, format->pad, 613 format->which); 614 __format->width = __crop->width / hratio; 615 __format->height = __crop->height / vratio; 616 617 format->format = *__format; 618 619 return 0; 620 } 621 622 static int mt9p031_get_selection(struct v4l2_subdev *subdev, 623 struct v4l2_subdev_state *sd_state, 624 struct v4l2_subdev_selection *sel) 625 { 626 struct mt9p031 *mt9p031 = to_mt9p031(subdev); 627 628 if (sel->target != V4L2_SEL_TGT_CROP) 629 return -EINVAL; 630 631 sel->r = *__mt9p031_get_pad_crop(mt9p031, sd_state, sel->pad, 632 sel->which); 633 return 0; 634 } 635 636 static int mt9p031_set_selection(struct v4l2_subdev *subdev, 637 struct v4l2_subdev_state *sd_state, 638 struct v4l2_subdev_selection *sel) 639 { 640 struct mt9p031 *mt9p031 = to_mt9p031(subdev); 641 struct v4l2_mbus_framefmt *__format; 642 struct v4l2_rect *__crop; 643 struct v4l2_rect rect; 644 645 if (sel->target != V4L2_SEL_TGT_CROP) 646 return -EINVAL; 647 648 /* Clamp the crop rectangle boundaries and align them to a multiple of 2 649 * pixels to ensure a GRBG Bayer pattern. 650 */ 651 rect.left = clamp(ALIGN(sel->r.left, 2), MT9P031_COLUMN_START_MIN, 652 MT9P031_COLUMN_START_MAX); 653 rect.top = clamp(ALIGN(sel->r.top, 2), MT9P031_ROW_START_MIN, 654 MT9P031_ROW_START_MAX); 655 rect.width = clamp_t(unsigned int, ALIGN(sel->r.width, 2), 656 MT9P031_WINDOW_WIDTH_MIN, 657 MT9P031_WINDOW_WIDTH_MAX); 658 rect.height = clamp_t(unsigned int, ALIGN(sel->r.height, 2), 659 MT9P031_WINDOW_HEIGHT_MIN, 660 MT9P031_WINDOW_HEIGHT_MAX); 661 662 rect.width = min_t(unsigned int, rect.width, 663 MT9P031_PIXEL_ARRAY_WIDTH - rect.left); 664 rect.height = min_t(unsigned int, rect.height, 665 MT9P031_PIXEL_ARRAY_HEIGHT - rect.top); 666 667 __crop = __mt9p031_get_pad_crop(mt9p031, sd_state, sel->pad, 668 sel->which); 669 670 if (rect.width != __crop->width || rect.height != __crop->height) { 671 /* Reset the output image size if the crop rectangle size has 672 * been modified. 673 */ 674 __format = __mt9p031_get_pad_format(mt9p031, sd_state, 675 sel->pad, 676 sel->which); 677 __format->width = rect.width; 678 __format->height = rect.height; 679 } 680 681 *__crop = rect; 682 sel->r = rect; 683 684 return 0; 685 } 686 687 /* ----------------------------------------------------------------------------- 688 * V4L2 subdev control operations 689 */ 690 691 #define V4L2_CID_BLC_AUTO (V4L2_CID_USER_BASE | 0x1002) 692 #define V4L2_CID_BLC_TARGET_LEVEL (V4L2_CID_USER_BASE | 0x1003) 693 #define V4L2_CID_BLC_ANALOG_OFFSET (V4L2_CID_USER_BASE | 0x1004) 694 #define V4L2_CID_BLC_DIGITAL_OFFSET (V4L2_CID_USER_BASE | 0x1005) 695 696 static int mt9p031_restore_blc(struct mt9p031 *mt9p031) 697 { 698 struct i2c_client *client = v4l2_get_subdevdata(&mt9p031->subdev); 699 int ret; 700 701 if (mt9p031->blc_auto->cur.val != 0) { 702 ret = mt9p031_set_mode2(mt9p031, 0, 703 MT9P031_READ_MODE_2_ROW_BLC); 704 if (ret < 0) 705 return ret; 706 } 707 708 if (mt9p031->blc_offset->cur.val != 0) { 709 ret = mt9p031_write(client, MT9P031_ROW_BLACK_TARGET, 710 mt9p031->blc_offset->cur.val); 711 if (ret < 0) 712 return ret; 713 } 714 715 return 0; 716 } 717 718 static int mt9p031_s_ctrl(struct v4l2_ctrl *ctrl) 719 { 720 struct mt9p031 *mt9p031 = 721 container_of(ctrl->handler, struct mt9p031, ctrls); 722 struct i2c_client *client = v4l2_get_subdevdata(&mt9p031->subdev); 723 u16 data; 724 int ret; 725 726 if (ctrl->flags & V4L2_CTRL_FLAG_INACTIVE) 727 return 0; 728 729 switch (ctrl->id) { 730 case V4L2_CID_EXPOSURE: 731 ret = mt9p031_write(client, MT9P031_SHUTTER_WIDTH_UPPER, 732 (ctrl->val >> 16) & 0xffff); 733 if (ret < 0) 734 return ret; 735 736 return mt9p031_write(client, MT9P031_SHUTTER_WIDTH_LOWER, 737 ctrl->val & 0xffff); 738 739 case V4L2_CID_GAIN: 740 /* Gain is controlled by 2 analog stages and a digital stage. 741 * Valid values for the 3 stages are 742 * 743 * Stage Min Max Step 744 * ------------------------------------------ 745 * First analog stage x1 x2 1 746 * Second analog stage x1 x4 0.125 747 * Digital stage x1 x16 0.125 748 * 749 * To minimize noise, the gain stages should be used in the 750 * second analog stage, first analog stage, digital stage order. 751 * Gain from a previous stage should be pushed to its maximum 752 * value before the next stage is used. 753 */ 754 if (ctrl->val <= 32) { 755 data = ctrl->val; 756 } else if (ctrl->val <= 64) { 757 ctrl->val &= ~1; 758 data = (1 << 6) | (ctrl->val >> 1); 759 } else { 760 ctrl->val &= ~7; 761 data = ((ctrl->val - 64) << 5) | (1 << 6) | 32; 762 } 763 764 return mt9p031_write(client, MT9P031_GLOBAL_GAIN, data); 765 766 case V4L2_CID_HFLIP: 767 if (ctrl->val) 768 return mt9p031_set_mode2(mt9p031, 769 0, MT9P031_READ_MODE_2_COL_MIR); 770 else 771 return mt9p031_set_mode2(mt9p031, 772 MT9P031_READ_MODE_2_COL_MIR, 0); 773 774 case V4L2_CID_VFLIP: 775 if (ctrl->val) 776 return mt9p031_set_mode2(mt9p031, 777 0, MT9P031_READ_MODE_2_ROW_MIR); 778 else 779 return mt9p031_set_mode2(mt9p031, 780 MT9P031_READ_MODE_2_ROW_MIR, 0); 781 782 case V4L2_CID_TEST_PATTERN: 783 /* The digital side of the Black Level Calibration function must 784 * be disabled when generating a test pattern to avoid artifacts 785 * in the image. Activate (deactivate) the BLC-related controls 786 * when the test pattern is enabled (disabled). 787 */ 788 v4l2_ctrl_activate(mt9p031->blc_auto, ctrl->val == 0); 789 v4l2_ctrl_activate(mt9p031->blc_offset, ctrl->val == 0); 790 791 if (!ctrl->val) { 792 /* Restore the BLC settings. */ 793 ret = mt9p031_restore_blc(mt9p031); 794 if (ret < 0) 795 return ret; 796 797 return mt9p031_write(client, MT9P031_TEST_PATTERN, 798 MT9P031_TEST_PATTERN_DISABLE); 799 } 800 801 ret = mt9p031_write(client, MT9P031_TEST_PATTERN_GREEN, 0x05a0); 802 if (ret < 0) 803 return ret; 804 ret = mt9p031_write(client, MT9P031_TEST_PATTERN_RED, 0x0a50); 805 if (ret < 0) 806 return ret; 807 ret = mt9p031_write(client, MT9P031_TEST_PATTERN_BLUE, 0x0aa0); 808 if (ret < 0) 809 return ret; 810 811 /* Disable digital BLC when generating a test pattern. */ 812 ret = mt9p031_set_mode2(mt9p031, MT9P031_READ_MODE_2_ROW_BLC, 813 0); 814 if (ret < 0) 815 return ret; 816 817 ret = mt9p031_write(client, MT9P031_ROW_BLACK_DEF_OFFSET, 0); 818 if (ret < 0) 819 return ret; 820 821 return mt9p031_write(client, MT9P031_TEST_PATTERN, 822 ((ctrl->val - 1) << MT9P031_TEST_PATTERN_SHIFT) 823 | MT9P031_TEST_PATTERN_ENABLE); 824 825 case V4L2_CID_BLC_AUTO: 826 ret = mt9p031_set_mode2(mt9p031, 827 ctrl->val ? 0 : MT9P031_READ_MODE_2_ROW_BLC, 828 ctrl->val ? MT9P031_READ_MODE_2_ROW_BLC : 0); 829 if (ret < 0) 830 return ret; 831 832 return mt9p031_write(client, MT9P031_BLACK_LEVEL_CALIBRATION, 833 ctrl->val ? 0 : MT9P031_BLC_MANUAL_BLC); 834 835 case V4L2_CID_BLC_TARGET_LEVEL: 836 return mt9p031_write(client, MT9P031_ROW_BLACK_TARGET, 837 ctrl->val); 838 839 case V4L2_CID_BLC_ANALOG_OFFSET: 840 data = ctrl->val & ((1 << 9) - 1); 841 842 ret = mt9p031_write(client, MT9P031_GREEN1_OFFSET, data); 843 if (ret < 0) 844 return ret; 845 ret = mt9p031_write(client, MT9P031_GREEN2_OFFSET, data); 846 if (ret < 0) 847 return ret; 848 ret = mt9p031_write(client, MT9P031_RED_OFFSET, data); 849 if (ret < 0) 850 return ret; 851 return mt9p031_write(client, MT9P031_BLUE_OFFSET, data); 852 853 case V4L2_CID_BLC_DIGITAL_OFFSET: 854 return mt9p031_write(client, MT9P031_ROW_BLACK_DEF_OFFSET, 855 ctrl->val & ((1 << 12) - 1)); 856 } 857 858 return 0; 859 } 860 861 static const struct v4l2_ctrl_ops mt9p031_ctrl_ops = { 862 .s_ctrl = mt9p031_s_ctrl, 863 }; 864 865 static const char * const mt9p031_test_pattern_menu[] = { 866 "Disabled", 867 "Color Field", 868 "Horizontal Gradient", 869 "Vertical Gradient", 870 "Diagonal Gradient", 871 "Classic Test Pattern", 872 "Walking 1s", 873 "Monochrome Horizontal Bars", 874 "Monochrome Vertical Bars", 875 "Vertical Color Bars", 876 }; 877 878 static const struct v4l2_ctrl_config mt9p031_ctrls[] = { 879 { 880 .ops = &mt9p031_ctrl_ops, 881 .id = V4L2_CID_BLC_AUTO, 882 .type = V4L2_CTRL_TYPE_BOOLEAN, 883 .name = "BLC, Auto", 884 .min = 0, 885 .max = 1, 886 .step = 1, 887 .def = 1, 888 .flags = 0, 889 }, { 890 .ops = &mt9p031_ctrl_ops, 891 .id = V4L2_CID_BLC_TARGET_LEVEL, 892 .type = V4L2_CTRL_TYPE_INTEGER, 893 .name = "BLC Target Level", 894 .min = 0, 895 .max = 4095, 896 .step = 1, 897 .def = 168, 898 .flags = 0, 899 }, { 900 .ops = &mt9p031_ctrl_ops, 901 .id = V4L2_CID_BLC_ANALOG_OFFSET, 902 .type = V4L2_CTRL_TYPE_INTEGER, 903 .name = "BLC Analog Offset", 904 .min = -255, 905 .max = 255, 906 .step = 1, 907 .def = 32, 908 .flags = 0, 909 }, { 910 .ops = &mt9p031_ctrl_ops, 911 .id = V4L2_CID_BLC_DIGITAL_OFFSET, 912 .type = V4L2_CTRL_TYPE_INTEGER, 913 .name = "BLC Digital Offset", 914 .min = -2048, 915 .max = 2047, 916 .step = 1, 917 .def = 40, 918 .flags = 0, 919 } 920 }; 921 922 /* ----------------------------------------------------------------------------- 923 * V4L2 subdev core operations 924 */ 925 926 static int mt9p031_set_power(struct v4l2_subdev *subdev, int on) 927 { 928 struct mt9p031 *mt9p031 = to_mt9p031(subdev); 929 int ret = 0; 930 931 mutex_lock(&mt9p031->power_lock); 932 933 /* If the power count is modified from 0 to != 0 or from != 0 to 0, 934 * update the power state. 935 */ 936 if (mt9p031->power_count == !on) { 937 ret = __mt9p031_set_power(mt9p031, !!on); 938 if (ret < 0) 939 goto out; 940 } 941 942 /* Update the power count. */ 943 mt9p031->power_count += on ? 1 : -1; 944 WARN_ON(mt9p031->power_count < 0); 945 946 out: 947 mutex_unlock(&mt9p031->power_lock); 948 return ret; 949 } 950 951 /* ----------------------------------------------------------------------------- 952 * V4L2 subdev internal operations 953 */ 954 955 static int mt9p031_registered(struct v4l2_subdev *subdev) 956 { 957 struct i2c_client *client = v4l2_get_subdevdata(subdev); 958 struct mt9p031 *mt9p031 = to_mt9p031(subdev); 959 s32 data; 960 int ret; 961 962 ret = mt9p031_power_on(mt9p031); 963 if (ret < 0) { 964 dev_err(&client->dev, "MT9P031 power up failed\n"); 965 return ret; 966 } 967 968 /* Read out the chip version register */ 969 data = mt9p031_read(client, MT9P031_CHIP_VERSION); 970 mt9p031_power_off(mt9p031); 971 972 if (data != MT9P031_CHIP_VERSION_VALUE) { 973 dev_err(&client->dev, "MT9P031 not detected, wrong version " 974 "0x%04x\n", data); 975 return -ENODEV; 976 } 977 978 dev_info(&client->dev, "MT9P031 detected at address 0x%02x\n", 979 client->addr); 980 981 return 0; 982 } 983 984 static int mt9p031_open(struct v4l2_subdev *subdev, struct v4l2_subdev_fh *fh) 985 { 986 struct mt9p031 *mt9p031 = to_mt9p031(subdev); 987 struct v4l2_mbus_framefmt *format; 988 struct v4l2_rect *crop; 989 990 crop = v4l2_subdev_get_try_crop(subdev, fh->state, 0); 991 crop->left = MT9P031_COLUMN_START_DEF; 992 crop->top = MT9P031_ROW_START_DEF; 993 crop->width = MT9P031_WINDOW_WIDTH_DEF; 994 crop->height = MT9P031_WINDOW_HEIGHT_DEF; 995 996 format = v4l2_subdev_get_try_format(subdev, fh->state, 0); 997 998 if (mt9p031->model == MT9P031_MODEL_MONOCHROME) 999 format->code = MEDIA_BUS_FMT_Y12_1X12; 1000 else 1001 format->code = MEDIA_BUS_FMT_SGRBG12_1X12; 1002 1003 format->width = MT9P031_WINDOW_WIDTH_DEF; 1004 format->height = MT9P031_WINDOW_HEIGHT_DEF; 1005 format->field = V4L2_FIELD_NONE; 1006 format->colorspace = V4L2_COLORSPACE_SRGB; 1007 1008 return mt9p031_set_power(subdev, 1); 1009 } 1010 1011 static int mt9p031_close(struct v4l2_subdev *subdev, struct v4l2_subdev_fh *fh) 1012 { 1013 return mt9p031_set_power(subdev, 0); 1014 } 1015 1016 static const struct v4l2_subdev_core_ops mt9p031_subdev_core_ops = { 1017 .s_power = mt9p031_set_power, 1018 }; 1019 1020 static const struct v4l2_subdev_video_ops mt9p031_subdev_video_ops = { 1021 .s_stream = mt9p031_s_stream, 1022 }; 1023 1024 static const struct v4l2_subdev_pad_ops mt9p031_subdev_pad_ops = { 1025 .enum_mbus_code = mt9p031_enum_mbus_code, 1026 .enum_frame_size = mt9p031_enum_frame_size, 1027 .get_fmt = mt9p031_get_format, 1028 .set_fmt = mt9p031_set_format, 1029 .get_selection = mt9p031_get_selection, 1030 .set_selection = mt9p031_set_selection, 1031 }; 1032 1033 static const struct v4l2_subdev_ops mt9p031_subdev_ops = { 1034 .core = &mt9p031_subdev_core_ops, 1035 .video = &mt9p031_subdev_video_ops, 1036 .pad = &mt9p031_subdev_pad_ops, 1037 }; 1038 1039 static const struct v4l2_subdev_internal_ops mt9p031_subdev_internal_ops = { 1040 .registered = mt9p031_registered, 1041 .open = mt9p031_open, 1042 .close = mt9p031_close, 1043 }; 1044 1045 /* ----------------------------------------------------------------------------- 1046 * Driver initialization and probing 1047 */ 1048 1049 static struct mt9p031_platform_data * 1050 mt9p031_get_pdata(struct i2c_client *client) 1051 { 1052 struct mt9p031_platform_data *pdata = NULL; 1053 struct device_node *np; 1054 struct v4l2_fwnode_endpoint endpoint = { 1055 .bus_type = V4L2_MBUS_PARALLEL 1056 }; 1057 1058 if (!IS_ENABLED(CONFIG_OF) || !client->dev.of_node) 1059 return client->dev.platform_data; 1060 1061 np = of_graph_get_next_endpoint(client->dev.of_node, NULL); 1062 if (!np) 1063 return NULL; 1064 1065 if (v4l2_fwnode_endpoint_parse(of_fwnode_handle(np), &endpoint) < 0) 1066 goto done; 1067 1068 pdata = devm_kzalloc(&client->dev, sizeof(*pdata), GFP_KERNEL); 1069 if (!pdata) 1070 goto done; 1071 1072 of_property_read_u32(np, "input-clock-frequency", &pdata->ext_freq); 1073 of_property_read_u32(np, "pixel-clock-frequency", &pdata->target_freq); 1074 1075 pdata->pixclk_pol = !!(endpoint.bus.parallel.flags & 1076 V4L2_MBUS_PCLK_SAMPLE_RISING); 1077 1078 done: 1079 of_node_put(np); 1080 return pdata; 1081 } 1082 1083 static int mt9p031_probe(struct i2c_client *client, 1084 const struct i2c_device_id *did) 1085 { 1086 struct mt9p031_platform_data *pdata = mt9p031_get_pdata(client); 1087 struct i2c_adapter *adapter = client->adapter; 1088 struct mt9p031 *mt9p031; 1089 unsigned int i; 1090 int ret; 1091 1092 if (pdata == NULL) { 1093 dev_err(&client->dev, "No platform data\n"); 1094 return -EINVAL; 1095 } 1096 1097 if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_WORD_DATA)) { 1098 dev_warn(&client->dev, 1099 "I2C-Adapter doesn't support I2C_FUNC_SMBUS_WORD\n"); 1100 return -EIO; 1101 } 1102 1103 mt9p031 = devm_kzalloc(&client->dev, sizeof(*mt9p031), GFP_KERNEL); 1104 if (mt9p031 == NULL) 1105 return -ENOMEM; 1106 1107 mt9p031->pdata = pdata; 1108 mt9p031->output_control = MT9P031_OUTPUT_CONTROL_DEF; 1109 mt9p031->mode2 = MT9P031_READ_MODE_2_ROW_BLC; 1110 mt9p031->model = did->driver_data; 1111 1112 mt9p031->regulators[0].supply = "vdd"; 1113 mt9p031->regulators[1].supply = "vdd_io"; 1114 mt9p031->regulators[2].supply = "vaa"; 1115 1116 ret = devm_regulator_bulk_get(&client->dev, 3, mt9p031->regulators); 1117 if (ret < 0) { 1118 dev_err(&client->dev, "Unable to get regulators\n"); 1119 return ret; 1120 } 1121 1122 mutex_init(&mt9p031->power_lock); 1123 1124 v4l2_ctrl_handler_init(&mt9p031->ctrls, ARRAY_SIZE(mt9p031_ctrls) + 6); 1125 1126 v4l2_ctrl_new_std(&mt9p031->ctrls, &mt9p031_ctrl_ops, 1127 V4L2_CID_EXPOSURE, MT9P031_SHUTTER_WIDTH_MIN, 1128 MT9P031_SHUTTER_WIDTH_MAX, 1, 1129 MT9P031_SHUTTER_WIDTH_DEF); 1130 v4l2_ctrl_new_std(&mt9p031->ctrls, &mt9p031_ctrl_ops, 1131 V4L2_CID_GAIN, MT9P031_GLOBAL_GAIN_MIN, 1132 MT9P031_GLOBAL_GAIN_MAX, 1, MT9P031_GLOBAL_GAIN_DEF); 1133 v4l2_ctrl_new_std(&mt9p031->ctrls, &mt9p031_ctrl_ops, 1134 V4L2_CID_HFLIP, 0, 1, 1, 0); 1135 v4l2_ctrl_new_std(&mt9p031->ctrls, &mt9p031_ctrl_ops, 1136 V4L2_CID_VFLIP, 0, 1, 1, 0); 1137 v4l2_ctrl_new_std(&mt9p031->ctrls, &mt9p031_ctrl_ops, 1138 V4L2_CID_PIXEL_RATE, pdata->target_freq, 1139 pdata->target_freq, 1, pdata->target_freq); 1140 v4l2_ctrl_new_std_menu_items(&mt9p031->ctrls, &mt9p031_ctrl_ops, 1141 V4L2_CID_TEST_PATTERN, 1142 ARRAY_SIZE(mt9p031_test_pattern_menu) - 1, 0, 1143 0, mt9p031_test_pattern_menu); 1144 1145 for (i = 0; i < ARRAY_SIZE(mt9p031_ctrls); ++i) 1146 v4l2_ctrl_new_custom(&mt9p031->ctrls, &mt9p031_ctrls[i], NULL); 1147 1148 mt9p031->subdev.ctrl_handler = &mt9p031->ctrls; 1149 1150 if (mt9p031->ctrls.error) { 1151 printk(KERN_INFO "%s: control initialization error %d\n", 1152 __func__, mt9p031->ctrls.error); 1153 ret = mt9p031->ctrls.error; 1154 goto done; 1155 } 1156 1157 mt9p031->blc_auto = v4l2_ctrl_find(&mt9p031->ctrls, V4L2_CID_BLC_AUTO); 1158 mt9p031->blc_offset = v4l2_ctrl_find(&mt9p031->ctrls, 1159 V4L2_CID_BLC_DIGITAL_OFFSET); 1160 1161 v4l2_i2c_subdev_init(&mt9p031->subdev, client, &mt9p031_subdev_ops); 1162 mt9p031->subdev.internal_ops = &mt9p031_subdev_internal_ops; 1163 1164 mt9p031->subdev.entity.function = MEDIA_ENT_F_CAM_SENSOR; 1165 mt9p031->pad.flags = MEDIA_PAD_FL_SOURCE; 1166 ret = media_entity_pads_init(&mt9p031->subdev.entity, 1, &mt9p031->pad); 1167 if (ret < 0) 1168 goto done; 1169 1170 mt9p031->subdev.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; 1171 1172 mt9p031->crop.width = MT9P031_WINDOW_WIDTH_DEF; 1173 mt9p031->crop.height = MT9P031_WINDOW_HEIGHT_DEF; 1174 mt9p031->crop.left = MT9P031_COLUMN_START_DEF; 1175 mt9p031->crop.top = MT9P031_ROW_START_DEF; 1176 1177 if (mt9p031->model == MT9P031_MODEL_MONOCHROME) 1178 mt9p031->format.code = MEDIA_BUS_FMT_Y12_1X12; 1179 else 1180 mt9p031->format.code = MEDIA_BUS_FMT_SGRBG12_1X12; 1181 1182 mt9p031->format.width = MT9P031_WINDOW_WIDTH_DEF; 1183 mt9p031->format.height = MT9P031_WINDOW_HEIGHT_DEF; 1184 mt9p031->format.field = V4L2_FIELD_NONE; 1185 mt9p031->format.colorspace = V4L2_COLORSPACE_SRGB; 1186 1187 mt9p031->reset = devm_gpiod_get_optional(&client->dev, "reset", 1188 GPIOD_OUT_HIGH); 1189 1190 ret = mt9p031_clk_setup(mt9p031); 1191 if (ret) 1192 goto done; 1193 1194 ret = v4l2_async_register_subdev(&mt9p031->subdev); 1195 1196 done: 1197 if (ret < 0) { 1198 v4l2_ctrl_handler_free(&mt9p031->ctrls); 1199 media_entity_cleanup(&mt9p031->subdev.entity); 1200 mutex_destroy(&mt9p031->power_lock); 1201 } 1202 1203 return ret; 1204 } 1205 1206 static int mt9p031_remove(struct i2c_client *client) 1207 { 1208 struct v4l2_subdev *subdev = i2c_get_clientdata(client); 1209 struct mt9p031 *mt9p031 = to_mt9p031(subdev); 1210 1211 v4l2_ctrl_handler_free(&mt9p031->ctrls); 1212 v4l2_async_unregister_subdev(subdev); 1213 media_entity_cleanup(&subdev->entity); 1214 mutex_destroy(&mt9p031->power_lock); 1215 1216 return 0; 1217 } 1218 1219 static const struct i2c_device_id mt9p031_id[] = { 1220 { "mt9p031", MT9P031_MODEL_COLOR }, 1221 { "mt9p031m", MT9P031_MODEL_MONOCHROME }, 1222 { } 1223 }; 1224 MODULE_DEVICE_TABLE(i2c, mt9p031_id); 1225 1226 #if IS_ENABLED(CONFIG_OF) 1227 static const struct of_device_id mt9p031_of_match[] = { 1228 { .compatible = "aptina,mt9p031", }, 1229 { .compatible = "aptina,mt9p031m", }, 1230 { /* sentinel */ }, 1231 }; 1232 MODULE_DEVICE_TABLE(of, mt9p031_of_match); 1233 #endif 1234 1235 static struct i2c_driver mt9p031_i2c_driver = { 1236 .driver = { 1237 .of_match_table = of_match_ptr(mt9p031_of_match), 1238 .name = "mt9p031", 1239 }, 1240 .probe = mt9p031_probe, 1241 .remove = mt9p031_remove, 1242 .id_table = mt9p031_id, 1243 }; 1244 1245 module_i2c_driver(mt9p031_i2c_driver); 1246 1247 MODULE_DESCRIPTION("Aptina MT9P031 Camera driver"); 1248 MODULE_AUTHOR("Bastian Hecht <hechtb@gmail.com>"); 1249 MODULE_LICENSE("GPL v2"); 1250