1 /* 2 * Driver for MT9M111/MT9M112/MT9M131 CMOS Image Sensor from Micron/Aptina 3 * 4 * Copyright (C) 2008, Robert Jarzmik <robert.jarzmik@free.fr> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 #include <linux/videodev2.h> 11 #include <linux/slab.h> 12 #include <linux/i2c.h> 13 #include <linux/log2.h> 14 #include <linux/gpio.h> 15 #include <linux/delay.h> 16 #include <linux/v4l2-mediabus.h> 17 #include <linux/module.h> 18 #include <linux/property.h> 19 20 #include <media/v4l2-async.h> 21 #include <media/v4l2-clk.h> 22 #include <media/v4l2-common.h> 23 #include <media/v4l2-ctrls.h> 24 #include <media/v4l2-device.h> 25 #include <media/v4l2-event.h> 26 #include <media/v4l2-fwnode.h> 27 28 /* 29 * MT9M111, MT9M112 and MT9M131: 30 * i2c address is 0x48 or 0x5d (depending on SADDR pin) 31 * The platform has to define struct i2c_board_info objects and link to them 32 * from struct soc_camera_host_desc 33 */ 34 35 /* 36 * Sensor core register addresses (0x000..0x0ff) 37 */ 38 #define MT9M111_CHIP_VERSION 0x000 39 #define MT9M111_ROW_START 0x001 40 #define MT9M111_COLUMN_START 0x002 41 #define MT9M111_WINDOW_HEIGHT 0x003 42 #define MT9M111_WINDOW_WIDTH 0x004 43 #define MT9M111_HORIZONTAL_BLANKING_B 0x005 44 #define MT9M111_VERTICAL_BLANKING_B 0x006 45 #define MT9M111_HORIZONTAL_BLANKING_A 0x007 46 #define MT9M111_VERTICAL_BLANKING_A 0x008 47 #define MT9M111_SHUTTER_WIDTH 0x009 48 #define MT9M111_ROW_SPEED 0x00a 49 #define MT9M111_EXTRA_DELAY 0x00b 50 #define MT9M111_SHUTTER_DELAY 0x00c 51 #define MT9M111_RESET 0x00d 52 #define MT9M111_READ_MODE_B 0x020 53 #define MT9M111_READ_MODE_A 0x021 54 #define MT9M111_FLASH_CONTROL 0x023 55 #define MT9M111_GREEN1_GAIN 0x02b 56 #define MT9M111_BLUE_GAIN 0x02c 57 #define MT9M111_RED_GAIN 0x02d 58 #define MT9M111_GREEN2_GAIN 0x02e 59 #define MT9M111_GLOBAL_GAIN 0x02f 60 #define MT9M111_CONTEXT_CONTROL 0x0c8 61 #define MT9M111_PAGE_MAP 0x0f0 62 #define MT9M111_BYTE_WISE_ADDR 0x0f1 63 64 #define MT9M111_RESET_SYNC_CHANGES (1 << 15) 65 #define MT9M111_RESET_RESTART_BAD_FRAME (1 << 9) 66 #define MT9M111_RESET_SHOW_BAD_FRAMES (1 << 8) 67 #define MT9M111_RESET_RESET_SOC (1 << 5) 68 #define MT9M111_RESET_OUTPUT_DISABLE (1 << 4) 69 #define MT9M111_RESET_CHIP_ENABLE (1 << 3) 70 #define MT9M111_RESET_ANALOG_STANDBY (1 << 2) 71 #define MT9M111_RESET_RESTART_FRAME (1 << 1) 72 #define MT9M111_RESET_RESET_MODE (1 << 0) 73 74 #define MT9M111_RM_FULL_POWER_RD (0 << 10) 75 #define MT9M111_RM_LOW_POWER_RD (1 << 10) 76 #define MT9M111_RM_COL_SKIP_4X (1 << 5) 77 #define MT9M111_RM_ROW_SKIP_4X (1 << 4) 78 #define MT9M111_RM_COL_SKIP_2X (1 << 3) 79 #define MT9M111_RM_ROW_SKIP_2X (1 << 2) 80 #define MT9M111_RMB_MIRROR_COLS (1 << 1) 81 #define MT9M111_RMB_MIRROR_ROWS (1 << 0) 82 #define MT9M111_CTXT_CTRL_RESTART (1 << 15) 83 #define MT9M111_CTXT_CTRL_DEFECTCOR_B (1 << 12) 84 #define MT9M111_CTXT_CTRL_RESIZE_B (1 << 10) 85 #define MT9M111_CTXT_CTRL_CTRL2_B (1 << 9) 86 #define MT9M111_CTXT_CTRL_GAMMA_B (1 << 8) 87 #define MT9M111_CTXT_CTRL_XENON_EN (1 << 7) 88 #define MT9M111_CTXT_CTRL_READ_MODE_B (1 << 3) 89 #define MT9M111_CTXT_CTRL_LED_FLASH_EN (1 << 2) 90 #define MT9M111_CTXT_CTRL_VBLANK_SEL_B (1 << 1) 91 #define MT9M111_CTXT_CTRL_HBLANK_SEL_B (1 << 0) 92 93 /* 94 * Colorpipe register addresses (0x100..0x1ff) 95 */ 96 #define MT9M111_OPER_MODE_CTRL 0x106 97 #define MT9M111_OUTPUT_FORMAT_CTRL 0x108 98 #define MT9M111_TPG_CTRL 0x148 99 #define MT9M111_REDUCER_XZOOM_B 0x1a0 100 #define MT9M111_REDUCER_XSIZE_B 0x1a1 101 #define MT9M111_REDUCER_YZOOM_B 0x1a3 102 #define MT9M111_REDUCER_YSIZE_B 0x1a4 103 #define MT9M111_REDUCER_XZOOM_A 0x1a6 104 #define MT9M111_REDUCER_XSIZE_A 0x1a7 105 #define MT9M111_REDUCER_YZOOM_A 0x1a9 106 #define MT9M111_REDUCER_YSIZE_A 0x1aa 107 #define MT9M111_EFFECTS_MODE 0x1e2 108 109 #define MT9M111_OUTPUT_FORMAT_CTRL2_A 0x13a 110 #define MT9M111_OUTPUT_FORMAT_CTRL2_B 0x19b 111 112 #define MT9M111_OPMODE_AUTOEXPO_EN (1 << 14) 113 #define MT9M111_OPMODE_AUTOWHITEBAL_EN (1 << 1) 114 #define MT9M111_OUTFMT_FLIP_BAYER_COL (1 << 9) 115 #define MT9M111_OUTFMT_FLIP_BAYER_ROW (1 << 8) 116 #define MT9M111_OUTFMT_PROCESSED_BAYER (1 << 14) 117 #define MT9M111_OUTFMT_BYPASS_IFP (1 << 10) 118 #define MT9M111_OUTFMT_INV_PIX_CLOCK (1 << 9) 119 #define MT9M111_OUTFMT_RGB (1 << 8) 120 #define MT9M111_OUTFMT_RGB565 (0 << 6) 121 #define MT9M111_OUTFMT_RGB555 (1 << 6) 122 #define MT9M111_OUTFMT_RGB444x (2 << 6) 123 #define MT9M111_OUTFMT_RGBx444 (3 << 6) 124 #define MT9M111_OUTFMT_TST_RAMP_OFF (0 << 4) 125 #define MT9M111_OUTFMT_TST_RAMP_COL (1 << 4) 126 #define MT9M111_OUTFMT_TST_RAMP_ROW (2 << 4) 127 #define MT9M111_OUTFMT_TST_RAMP_FRAME (3 << 4) 128 #define MT9M111_OUTFMT_SHIFT_3_UP (1 << 3) 129 #define MT9M111_OUTFMT_AVG_CHROMA (1 << 2) 130 #define MT9M111_OUTFMT_SWAP_YCbCr_C_Y_RGB_EVEN (1 << 1) 131 #define MT9M111_OUTFMT_SWAP_YCbCr_Cb_Cr_RGB_R_B (1 << 0) 132 #define MT9M111_TPG_SEL_MASK GENMASK(2, 0) 133 #define MT9M111_EFFECTS_MODE_MASK GENMASK(2, 0) 134 #define MT9M111_RM_PWR_MASK BIT(10) 135 #define MT9M111_RM_SKIP2_MASK GENMASK(3, 2) 136 137 /* 138 * Camera control register addresses (0x200..0x2ff not implemented) 139 */ 140 141 #define reg_read(reg) mt9m111_reg_read(client, MT9M111_##reg) 142 #define reg_write(reg, val) mt9m111_reg_write(client, MT9M111_##reg, (val)) 143 #define reg_set(reg, val) mt9m111_reg_set(client, MT9M111_##reg, (val)) 144 #define reg_clear(reg, val) mt9m111_reg_clear(client, MT9M111_##reg, (val)) 145 #define reg_mask(reg, val, mask) mt9m111_reg_mask(client, MT9M111_##reg, \ 146 (val), (mask)) 147 148 #define MT9M111_MIN_DARK_ROWS 8 149 #define MT9M111_MIN_DARK_COLS 26 150 #define MT9M111_MAX_HEIGHT 1024 151 #define MT9M111_MAX_WIDTH 1280 152 153 struct mt9m111_context { 154 u16 read_mode; 155 u16 blanking_h; 156 u16 blanking_v; 157 u16 reducer_xzoom; 158 u16 reducer_yzoom; 159 u16 reducer_xsize; 160 u16 reducer_ysize; 161 u16 output_fmt_ctrl2; 162 u16 control; 163 }; 164 165 static struct mt9m111_context context_a = { 166 .read_mode = MT9M111_READ_MODE_A, 167 .blanking_h = MT9M111_HORIZONTAL_BLANKING_A, 168 .blanking_v = MT9M111_VERTICAL_BLANKING_A, 169 .reducer_xzoom = MT9M111_REDUCER_XZOOM_A, 170 .reducer_yzoom = MT9M111_REDUCER_YZOOM_A, 171 .reducer_xsize = MT9M111_REDUCER_XSIZE_A, 172 .reducer_ysize = MT9M111_REDUCER_YSIZE_A, 173 .output_fmt_ctrl2 = MT9M111_OUTPUT_FORMAT_CTRL2_A, 174 .control = MT9M111_CTXT_CTRL_RESTART, 175 }; 176 177 static struct mt9m111_context context_b = { 178 .read_mode = MT9M111_READ_MODE_B, 179 .blanking_h = MT9M111_HORIZONTAL_BLANKING_B, 180 .blanking_v = MT9M111_VERTICAL_BLANKING_B, 181 .reducer_xzoom = MT9M111_REDUCER_XZOOM_B, 182 .reducer_yzoom = MT9M111_REDUCER_YZOOM_B, 183 .reducer_xsize = MT9M111_REDUCER_XSIZE_B, 184 .reducer_ysize = MT9M111_REDUCER_YSIZE_B, 185 .output_fmt_ctrl2 = MT9M111_OUTPUT_FORMAT_CTRL2_B, 186 .control = MT9M111_CTXT_CTRL_RESTART | 187 MT9M111_CTXT_CTRL_DEFECTCOR_B | MT9M111_CTXT_CTRL_RESIZE_B | 188 MT9M111_CTXT_CTRL_CTRL2_B | MT9M111_CTXT_CTRL_GAMMA_B | 189 MT9M111_CTXT_CTRL_READ_MODE_B | MT9M111_CTXT_CTRL_VBLANK_SEL_B | 190 MT9M111_CTXT_CTRL_HBLANK_SEL_B, 191 }; 192 193 /* MT9M111 has only one fixed colorspace per pixelcode */ 194 struct mt9m111_datafmt { 195 u32 code; 196 enum v4l2_colorspace colorspace; 197 }; 198 199 static const struct mt9m111_datafmt mt9m111_colour_fmts[] = { 200 {MEDIA_BUS_FMT_YUYV8_2X8, V4L2_COLORSPACE_SRGB}, 201 {MEDIA_BUS_FMT_YVYU8_2X8, V4L2_COLORSPACE_SRGB}, 202 {MEDIA_BUS_FMT_UYVY8_2X8, V4L2_COLORSPACE_SRGB}, 203 {MEDIA_BUS_FMT_VYUY8_2X8, V4L2_COLORSPACE_SRGB}, 204 {MEDIA_BUS_FMT_RGB555_2X8_PADHI_LE, V4L2_COLORSPACE_SRGB}, 205 {MEDIA_BUS_FMT_RGB555_2X8_PADHI_BE, V4L2_COLORSPACE_SRGB}, 206 {MEDIA_BUS_FMT_RGB565_2X8_LE, V4L2_COLORSPACE_SRGB}, 207 {MEDIA_BUS_FMT_RGB565_2X8_BE, V4L2_COLORSPACE_SRGB}, 208 {MEDIA_BUS_FMT_BGR565_2X8_LE, V4L2_COLORSPACE_SRGB}, 209 {MEDIA_BUS_FMT_BGR565_2X8_BE, V4L2_COLORSPACE_SRGB}, 210 {MEDIA_BUS_FMT_SBGGR8_1X8, V4L2_COLORSPACE_SRGB}, 211 {MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_LE, V4L2_COLORSPACE_SRGB}, 212 }; 213 214 enum mt9m111_mode_id { 215 MT9M111_MODE_SXGA_8FPS, 216 MT9M111_MODE_SXGA_15FPS, 217 MT9M111_MODE_QSXGA_30FPS, 218 MT9M111_NUM_MODES, 219 }; 220 221 struct mt9m111_mode_info { 222 unsigned int sensor_w; 223 unsigned int sensor_h; 224 unsigned int max_image_w; 225 unsigned int max_image_h; 226 unsigned int max_fps; 227 unsigned int reg_val; 228 unsigned int reg_mask; 229 }; 230 231 struct mt9m111 { 232 struct v4l2_subdev subdev; 233 struct v4l2_ctrl_handler hdl; 234 struct v4l2_ctrl *gain; 235 struct mt9m111_context *ctx; 236 struct v4l2_rect rect; /* cropping rectangle */ 237 struct v4l2_clk *clk; 238 unsigned int width; /* output */ 239 unsigned int height; /* sizes */ 240 struct v4l2_fract frame_interval; 241 const struct mt9m111_mode_info *current_mode; 242 struct mutex power_lock; /* lock to protect power_count */ 243 int power_count; 244 const struct mt9m111_datafmt *fmt; 245 int lastpage; /* PageMap cache value */ 246 bool is_streaming; 247 /* user point of view - 0: falling 1: rising edge */ 248 unsigned int pclk_sample:1; 249 #ifdef CONFIG_MEDIA_CONTROLLER 250 struct media_pad pad; 251 #endif 252 }; 253 254 static const struct mt9m111_mode_info mt9m111_mode_data[MT9M111_NUM_MODES] = { 255 [MT9M111_MODE_SXGA_8FPS] = { 256 .sensor_w = 1280, 257 .sensor_h = 1024, 258 .max_image_w = 1280, 259 .max_image_h = 1024, 260 .max_fps = 8, 261 .reg_val = MT9M111_RM_LOW_POWER_RD, 262 .reg_mask = MT9M111_RM_PWR_MASK | MT9M111_RM_SKIP2_MASK, 263 }, 264 [MT9M111_MODE_SXGA_15FPS] = { 265 .sensor_w = 1280, 266 .sensor_h = 1024, 267 .max_image_w = 1280, 268 .max_image_h = 1024, 269 .max_fps = 15, 270 .reg_val = MT9M111_RM_FULL_POWER_RD, 271 .reg_mask = MT9M111_RM_PWR_MASK | MT9M111_RM_SKIP2_MASK, 272 }, 273 [MT9M111_MODE_QSXGA_30FPS] = { 274 .sensor_w = 1280, 275 .sensor_h = 1024, 276 .max_image_w = 640, 277 .max_image_h = 512, 278 .max_fps = 30, 279 .reg_val = MT9M111_RM_LOW_POWER_RD | MT9M111_RM_COL_SKIP_2X | 280 MT9M111_RM_ROW_SKIP_2X, 281 .reg_mask = MT9M111_RM_PWR_MASK | MT9M111_RM_SKIP2_MASK, 282 }, 283 }; 284 285 /* Find a data format by a pixel code */ 286 static const struct mt9m111_datafmt *mt9m111_find_datafmt(struct mt9m111 *mt9m111, 287 u32 code) 288 { 289 int i; 290 for (i = 0; i < ARRAY_SIZE(mt9m111_colour_fmts); i++) 291 if (mt9m111_colour_fmts[i].code == code) 292 return mt9m111_colour_fmts + i; 293 294 return mt9m111->fmt; 295 } 296 297 static struct mt9m111 *to_mt9m111(const struct i2c_client *client) 298 { 299 return container_of(i2c_get_clientdata(client), struct mt9m111, subdev); 300 } 301 302 static int reg_page_map_set(struct i2c_client *client, const u16 reg) 303 { 304 int ret; 305 u16 page; 306 struct mt9m111 *mt9m111 = to_mt9m111(client); 307 308 page = (reg >> 8); 309 if (page == mt9m111->lastpage) 310 return 0; 311 if (page > 2) 312 return -EINVAL; 313 314 ret = i2c_smbus_write_word_swapped(client, MT9M111_PAGE_MAP, page); 315 if (!ret) 316 mt9m111->lastpage = page; 317 return ret; 318 } 319 320 static int mt9m111_reg_read(struct i2c_client *client, const u16 reg) 321 { 322 int ret; 323 324 ret = reg_page_map_set(client, reg); 325 if (!ret) 326 ret = i2c_smbus_read_word_swapped(client, reg & 0xff); 327 328 dev_dbg(&client->dev, "read reg.%03x -> %04x\n", reg, ret); 329 return ret; 330 } 331 332 static int mt9m111_reg_write(struct i2c_client *client, const u16 reg, 333 const u16 data) 334 { 335 int ret; 336 337 ret = reg_page_map_set(client, reg); 338 if (!ret) 339 ret = i2c_smbus_write_word_swapped(client, reg & 0xff, data); 340 dev_dbg(&client->dev, "write reg.%03x = %04x -> %d\n", reg, data, ret); 341 return ret; 342 } 343 344 static int mt9m111_reg_set(struct i2c_client *client, const u16 reg, 345 const u16 data) 346 { 347 int ret; 348 349 ret = mt9m111_reg_read(client, reg); 350 if (ret >= 0) 351 ret = mt9m111_reg_write(client, reg, ret | data); 352 return ret; 353 } 354 355 static int mt9m111_reg_clear(struct i2c_client *client, const u16 reg, 356 const u16 data) 357 { 358 int ret; 359 360 ret = mt9m111_reg_read(client, reg); 361 if (ret >= 0) 362 ret = mt9m111_reg_write(client, reg, ret & ~data); 363 return ret; 364 } 365 366 static int mt9m111_reg_mask(struct i2c_client *client, const u16 reg, 367 const u16 data, const u16 mask) 368 { 369 int ret; 370 371 ret = mt9m111_reg_read(client, reg); 372 if (ret >= 0) 373 ret = mt9m111_reg_write(client, reg, (ret & ~mask) | data); 374 return ret; 375 } 376 377 static int mt9m111_set_context(struct mt9m111 *mt9m111, 378 struct mt9m111_context *ctx) 379 { 380 struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev); 381 return reg_write(CONTEXT_CONTROL, ctx->control); 382 } 383 384 static int mt9m111_setup_rect_ctx(struct mt9m111 *mt9m111, 385 struct mt9m111_context *ctx, struct v4l2_rect *rect, 386 unsigned int width, unsigned int height) 387 { 388 struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev); 389 int ret = mt9m111_reg_write(client, ctx->reducer_xzoom, rect->width); 390 if (!ret) 391 ret = mt9m111_reg_write(client, ctx->reducer_yzoom, rect->height); 392 if (!ret) 393 ret = mt9m111_reg_write(client, ctx->reducer_xsize, width); 394 if (!ret) 395 ret = mt9m111_reg_write(client, ctx->reducer_ysize, height); 396 return ret; 397 } 398 399 static int mt9m111_setup_geometry(struct mt9m111 *mt9m111, struct v4l2_rect *rect, 400 int width, int height, u32 code) 401 { 402 struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev); 403 int ret; 404 405 ret = reg_write(COLUMN_START, rect->left); 406 if (!ret) 407 ret = reg_write(ROW_START, rect->top); 408 409 if (!ret) 410 ret = reg_write(WINDOW_WIDTH, rect->width); 411 if (!ret) 412 ret = reg_write(WINDOW_HEIGHT, rect->height); 413 414 if (code != MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_LE) { 415 /* IFP in use, down-scaling possible */ 416 if (!ret) 417 ret = mt9m111_setup_rect_ctx(mt9m111, &context_b, 418 rect, width, height); 419 if (!ret) 420 ret = mt9m111_setup_rect_ctx(mt9m111, &context_a, 421 rect, width, height); 422 } 423 424 dev_dbg(&client->dev, "%s(%x): %ux%u@%u:%u -> %ux%u = %d\n", 425 __func__, code, rect->width, rect->height, rect->left, rect->top, 426 width, height, ret); 427 428 return ret; 429 } 430 431 static int mt9m111_enable(struct mt9m111 *mt9m111) 432 { 433 struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev); 434 return reg_write(RESET, MT9M111_RESET_CHIP_ENABLE); 435 } 436 437 static int mt9m111_reset(struct mt9m111 *mt9m111) 438 { 439 struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev); 440 int ret; 441 442 ret = reg_set(RESET, MT9M111_RESET_RESET_MODE); 443 if (!ret) 444 ret = reg_set(RESET, MT9M111_RESET_RESET_SOC); 445 if (!ret) 446 ret = reg_clear(RESET, MT9M111_RESET_RESET_MODE 447 | MT9M111_RESET_RESET_SOC); 448 449 return ret; 450 } 451 452 static int mt9m111_set_selection(struct v4l2_subdev *sd, 453 struct v4l2_subdev_pad_config *cfg, 454 struct v4l2_subdev_selection *sel) 455 { 456 struct i2c_client *client = v4l2_get_subdevdata(sd); 457 struct mt9m111 *mt9m111 = to_mt9m111(client); 458 struct v4l2_rect rect = sel->r; 459 int width, height; 460 int ret, align = 0; 461 462 if (sel->which != V4L2_SUBDEV_FORMAT_ACTIVE || 463 sel->target != V4L2_SEL_TGT_CROP) 464 return -EINVAL; 465 466 if (mt9m111->fmt->code == MEDIA_BUS_FMT_SBGGR8_1X8 || 467 mt9m111->fmt->code == MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_LE) { 468 /* Bayer format - even size lengths */ 469 align = 1; 470 /* Let the user play with the starting pixel */ 471 } 472 473 /* FIXME: the datasheet doesn't specify minimum sizes */ 474 v4l_bound_align_image(&rect.width, 2, MT9M111_MAX_WIDTH, align, 475 &rect.height, 2, MT9M111_MAX_HEIGHT, align, 0); 476 rect.left = clamp(rect.left, MT9M111_MIN_DARK_COLS, 477 MT9M111_MIN_DARK_COLS + MT9M111_MAX_WIDTH - 478 (__s32)rect.width); 479 rect.top = clamp(rect.top, MT9M111_MIN_DARK_ROWS, 480 MT9M111_MIN_DARK_ROWS + MT9M111_MAX_HEIGHT - 481 (__s32)rect.height); 482 483 width = min(mt9m111->width, rect.width); 484 height = min(mt9m111->height, rect.height); 485 486 ret = mt9m111_setup_geometry(mt9m111, &rect, width, height, mt9m111->fmt->code); 487 if (!ret) { 488 mt9m111->rect = rect; 489 mt9m111->width = width; 490 mt9m111->height = height; 491 } 492 493 return ret; 494 } 495 496 static int mt9m111_get_selection(struct v4l2_subdev *sd, 497 struct v4l2_subdev_pad_config *cfg, 498 struct v4l2_subdev_selection *sel) 499 { 500 struct i2c_client *client = v4l2_get_subdevdata(sd); 501 struct mt9m111 *mt9m111 = to_mt9m111(client); 502 503 if (sel->which != V4L2_SUBDEV_FORMAT_ACTIVE) 504 return -EINVAL; 505 506 switch (sel->target) { 507 case V4L2_SEL_TGT_CROP_BOUNDS: 508 sel->r.left = MT9M111_MIN_DARK_COLS; 509 sel->r.top = MT9M111_MIN_DARK_ROWS; 510 sel->r.width = MT9M111_MAX_WIDTH; 511 sel->r.height = MT9M111_MAX_HEIGHT; 512 return 0; 513 case V4L2_SEL_TGT_CROP: 514 sel->r = mt9m111->rect; 515 return 0; 516 default: 517 return -EINVAL; 518 } 519 } 520 521 static int mt9m111_get_fmt(struct v4l2_subdev *sd, 522 struct v4l2_subdev_pad_config *cfg, 523 struct v4l2_subdev_format *format) 524 { 525 struct v4l2_mbus_framefmt *mf = &format->format; 526 struct mt9m111 *mt9m111 = container_of(sd, struct mt9m111, subdev); 527 528 if (format->pad) 529 return -EINVAL; 530 531 mf->width = mt9m111->width; 532 mf->height = mt9m111->height; 533 mf->code = mt9m111->fmt->code; 534 mf->colorspace = mt9m111->fmt->colorspace; 535 mf->field = V4L2_FIELD_NONE; 536 537 return 0; 538 } 539 540 static int mt9m111_set_pixfmt(struct mt9m111 *mt9m111, 541 u32 code) 542 { 543 struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev); 544 u16 data_outfmt2, mask_outfmt2 = MT9M111_OUTFMT_PROCESSED_BAYER | 545 MT9M111_OUTFMT_BYPASS_IFP | MT9M111_OUTFMT_RGB | 546 MT9M111_OUTFMT_RGB565 | MT9M111_OUTFMT_RGB555 | 547 MT9M111_OUTFMT_RGB444x | MT9M111_OUTFMT_RGBx444 | 548 MT9M111_OUTFMT_SWAP_YCbCr_C_Y_RGB_EVEN | 549 MT9M111_OUTFMT_SWAP_YCbCr_Cb_Cr_RGB_R_B; 550 int ret; 551 552 switch (code) { 553 case MEDIA_BUS_FMT_SBGGR8_1X8: 554 data_outfmt2 = MT9M111_OUTFMT_PROCESSED_BAYER | 555 MT9M111_OUTFMT_RGB; 556 break; 557 case MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_LE: 558 data_outfmt2 = MT9M111_OUTFMT_BYPASS_IFP | MT9M111_OUTFMT_RGB; 559 break; 560 case MEDIA_BUS_FMT_RGB555_2X8_PADHI_LE: 561 data_outfmt2 = MT9M111_OUTFMT_RGB | MT9M111_OUTFMT_RGB555 | 562 MT9M111_OUTFMT_SWAP_YCbCr_C_Y_RGB_EVEN; 563 break; 564 case MEDIA_BUS_FMT_RGB555_2X8_PADHI_BE: 565 data_outfmt2 = MT9M111_OUTFMT_RGB | MT9M111_OUTFMT_RGB555; 566 break; 567 case MEDIA_BUS_FMT_RGB565_2X8_LE: 568 data_outfmt2 = MT9M111_OUTFMT_RGB | MT9M111_OUTFMT_RGB565 | 569 MT9M111_OUTFMT_SWAP_YCbCr_C_Y_RGB_EVEN; 570 break; 571 case MEDIA_BUS_FMT_RGB565_2X8_BE: 572 data_outfmt2 = MT9M111_OUTFMT_RGB | MT9M111_OUTFMT_RGB565; 573 break; 574 case MEDIA_BUS_FMT_BGR565_2X8_BE: 575 data_outfmt2 = MT9M111_OUTFMT_RGB | MT9M111_OUTFMT_RGB565 | 576 MT9M111_OUTFMT_SWAP_YCbCr_Cb_Cr_RGB_R_B; 577 break; 578 case MEDIA_BUS_FMT_BGR565_2X8_LE: 579 data_outfmt2 = MT9M111_OUTFMT_RGB | MT9M111_OUTFMT_RGB565 | 580 MT9M111_OUTFMT_SWAP_YCbCr_C_Y_RGB_EVEN | 581 MT9M111_OUTFMT_SWAP_YCbCr_Cb_Cr_RGB_R_B; 582 break; 583 case MEDIA_BUS_FMT_UYVY8_2X8: 584 data_outfmt2 = 0; 585 break; 586 case MEDIA_BUS_FMT_VYUY8_2X8: 587 data_outfmt2 = MT9M111_OUTFMT_SWAP_YCbCr_Cb_Cr_RGB_R_B; 588 break; 589 case MEDIA_BUS_FMT_YUYV8_2X8: 590 data_outfmt2 = MT9M111_OUTFMT_SWAP_YCbCr_C_Y_RGB_EVEN; 591 break; 592 case MEDIA_BUS_FMT_YVYU8_2X8: 593 data_outfmt2 = MT9M111_OUTFMT_SWAP_YCbCr_C_Y_RGB_EVEN | 594 MT9M111_OUTFMT_SWAP_YCbCr_Cb_Cr_RGB_R_B; 595 break; 596 default: 597 dev_err(&client->dev, "Pixel format not handled: %x\n", code); 598 return -EINVAL; 599 } 600 601 /* receiver samples on falling edge, chip-hw default is rising */ 602 if (mt9m111->pclk_sample == 0) 603 mask_outfmt2 |= MT9M111_OUTFMT_INV_PIX_CLOCK; 604 605 ret = mt9m111_reg_mask(client, context_a.output_fmt_ctrl2, 606 data_outfmt2, mask_outfmt2); 607 if (!ret) 608 ret = mt9m111_reg_mask(client, context_b.output_fmt_ctrl2, 609 data_outfmt2, mask_outfmt2); 610 611 return ret; 612 } 613 614 static int mt9m111_set_fmt(struct v4l2_subdev *sd, 615 struct v4l2_subdev_pad_config *cfg, 616 struct v4l2_subdev_format *format) 617 { 618 struct v4l2_mbus_framefmt *mf = &format->format; 619 struct i2c_client *client = v4l2_get_subdevdata(sd); 620 struct mt9m111 *mt9m111 = container_of(sd, struct mt9m111, subdev); 621 const struct mt9m111_datafmt *fmt; 622 struct v4l2_rect *rect = &mt9m111->rect; 623 bool bayer; 624 int ret; 625 626 if (mt9m111->is_streaming) 627 return -EBUSY; 628 629 if (format->pad) 630 return -EINVAL; 631 632 fmt = mt9m111_find_datafmt(mt9m111, mf->code); 633 634 bayer = fmt->code == MEDIA_BUS_FMT_SBGGR8_1X8 || 635 fmt->code == MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_LE; 636 637 /* 638 * With Bayer format enforce even side lengths, but let the user play 639 * with the starting pixel 640 */ 641 if (bayer) { 642 rect->width = ALIGN(rect->width, 2); 643 rect->height = ALIGN(rect->height, 2); 644 } 645 646 if (fmt->code == MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_LE) { 647 /* IFP bypass mode, no scaling */ 648 mf->width = rect->width; 649 mf->height = rect->height; 650 } else { 651 /* No upscaling */ 652 if (mf->width > rect->width) 653 mf->width = rect->width; 654 if (mf->height > rect->height) 655 mf->height = rect->height; 656 } 657 658 dev_dbg(&client->dev, "%s(): %ux%u, code=%x\n", __func__, 659 mf->width, mf->height, fmt->code); 660 661 mf->code = fmt->code; 662 mf->colorspace = fmt->colorspace; 663 664 if (format->which == V4L2_SUBDEV_FORMAT_TRY) { 665 cfg->try_fmt = *mf; 666 return 0; 667 } 668 669 ret = mt9m111_setup_geometry(mt9m111, rect, mf->width, mf->height, mf->code); 670 if (!ret) 671 ret = mt9m111_set_pixfmt(mt9m111, mf->code); 672 if (!ret) { 673 mt9m111->width = mf->width; 674 mt9m111->height = mf->height; 675 mt9m111->fmt = fmt; 676 } 677 678 return ret; 679 } 680 681 static const struct mt9m111_mode_info * 682 mt9m111_find_mode(struct mt9m111 *mt9m111, unsigned int req_fps, 683 unsigned int width, unsigned int height) 684 { 685 const struct mt9m111_mode_info *mode; 686 struct v4l2_rect *sensor_rect = &mt9m111->rect; 687 unsigned int gap, gap_best = (unsigned int) -1; 688 int i, best_gap_idx = MT9M111_MODE_SXGA_15FPS; 689 bool skip_30fps = false; 690 691 /* 692 * The fps selection is based on the row, column skipping mechanism. 693 * So ensure that the sensor window is set to default else the fps 694 * aren't calculated correctly within the sensor hw. 695 */ 696 if (sensor_rect->width != MT9M111_MAX_WIDTH || 697 sensor_rect->height != MT9M111_MAX_HEIGHT) { 698 dev_info(mt9m111->subdev.dev, 699 "Framerate selection is not supported for cropped " 700 "images\n"); 701 return NULL; 702 } 703 704 /* 30fps only supported for images not exceeding 640x512 */ 705 if (width > MT9M111_MAX_WIDTH / 2 || height > MT9M111_MAX_HEIGHT / 2) { 706 dev_dbg(mt9m111->subdev.dev, 707 "Framerates > 15fps are supported only for images " 708 "not exceeding 640x512\n"); 709 skip_30fps = true; 710 } 711 712 /* find best matched fps */ 713 for (i = 0; i < MT9M111_NUM_MODES; i++) { 714 unsigned int fps = mt9m111_mode_data[i].max_fps; 715 716 if (fps == 30 && skip_30fps) 717 continue; 718 719 gap = abs(fps - req_fps); 720 if (gap < gap_best) { 721 best_gap_idx = i; 722 gap_best = gap; 723 } 724 } 725 726 /* 727 * Use context a/b default timing values instead of calculate blanking 728 * timing values. 729 */ 730 mode = &mt9m111_mode_data[best_gap_idx]; 731 mt9m111->ctx = (best_gap_idx == MT9M111_MODE_QSXGA_30FPS) ? &context_a : 732 &context_b; 733 return mode; 734 } 735 736 #ifdef CONFIG_VIDEO_ADV_DEBUG 737 static int mt9m111_g_register(struct v4l2_subdev *sd, 738 struct v4l2_dbg_register *reg) 739 { 740 struct i2c_client *client = v4l2_get_subdevdata(sd); 741 int val; 742 743 if (reg->reg > 0x2ff) 744 return -EINVAL; 745 746 val = mt9m111_reg_read(client, reg->reg); 747 reg->size = 2; 748 reg->val = (u64)val; 749 750 if (reg->val > 0xffff) 751 return -EIO; 752 753 return 0; 754 } 755 756 static int mt9m111_s_register(struct v4l2_subdev *sd, 757 const struct v4l2_dbg_register *reg) 758 { 759 struct i2c_client *client = v4l2_get_subdevdata(sd); 760 761 if (reg->reg > 0x2ff) 762 return -EINVAL; 763 764 if (mt9m111_reg_write(client, reg->reg, reg->val) < 0) 765 return -EIO; 766 767 return 0; 768 } 769 #endif 770 771 static int mt9m111_set_flip(struct mt9m111 *mt9m111, int flip, int mask) 772 { 773 struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev); 774 int ret; 775 776 if (flip) 777 ret = mt9m111_reg_set(client, mt9m111->ctx->read_mode, mask); 778 else 779 ret = mt9m111_reg_clear(client, mt9m111->ctx->read_mode, mask); 780 781 return ret; 782 } 783 784 static int mt9m111_get_global_gain(struct mt9m111 *mt9m111) 785 { 786 struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev); 787 int data; 788 789 data = reg_read(GLOBAL_GAIN); 790 if (data >= 0) 791 return (data & 0x2f) * (1 << ((data >> 10) & 1)) * 792 (1 << ((data >> 9) & 1)); 793 return data; 794 } 795 796 static int mt9m111_set_global_gain(struct mt9m111 *mt9m111, int gain) 797 { 798 struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev); 799 u16 val; 800 801 if (gain > 63 * 2 * 2) 802 return -EINVAL; 803 804 if ((gain >= 64 * 2) && (gain < 63 * 2 * 2)) 805 val = (1 << 10) | (1 << 9) | (gain / 4); 806 else if ((gain >= 64) && (gain < 64 * 2)) 807 val = (1 << 9) | (gain / 2); 808 else 809 val = gain; 810 811 return reg_write(GLOBAL_GAIN, val); 812 } 813 814 static int mt9m111_set_autoexposure(struct mt9m111 *mt9m111, int val) 815 { 816 struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev); 817 818 if (val == V4L2_EXPOSURE_AUTO) 819 return reg_set(OPER_MODE_CTRL, MT9M111_OPMODE_AUTOEXPO_EN); 820 return reg_clear(OPER_MODE_CTRL, MT9M111_OPMODE_AUTOEXPO_EN); 821 } 822 823 static int mt9m111_set_autowhitebalance(struct mt9m111 *mt9m111, int on) 824 { 825 struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev); 826 827 if (on) 828 return reg_set(OPER_MODE_CTRL, MT9M111_OPMODE_AUTOWHITEBAL_EN); 829 return reg_clear(OPER_MODE_CTRL, MT9M111_OPMODE_AUTOWHITEBAL_EN); 830 } 831 832 static const char * const mt9m111_test_pattern_menu[] = { 833 "Disabled", 834 "Vertical monochrome gradient", 835 "Flat color type 1", 836 "Flat color type 2", 837 "Flat color type 3", 838 "Flat color type 4", 839 "Flat color type 5", 840 "Color bar", 841 }; 842 843 static int mt9m111_set_test_pattern(struct mt9m111 *mt9m111, int val) 844 { 845 struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev); 846 847 return mt9m111_reg_mask(client, MT9M111_TPG_CTRL, val, 848 MT9M111_TPG_SEL_MASK); 849 } 850 851 static int mt9m111_set_colorfx(struct mt9m111 *mt9m111, int val) 852 { 853 struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev); 854 static const struct v4l2_control colorfx[] = { 855 { V4L2_COLORFX_NONE, 0 }, 856 { V4L2_COLORFX_BW, 1 }, 857 { V4L2_COLORFX_SEPIA, 2 }, 858 { V4L2_COLORFX_NEGATIVE, 3 }, 859 { V4L2_COLORFX_SOLARIZATION, 4 }, 860 }; 861 int i; 862 863 for (i = 0; i < ARRAY_SIZE(colorfx); i++) { 864 if (colorfx[i].id == val) { 865 return mt9m111_reg_mask(client, MT9M111_EFFECTS_MODE, 866 colorfx[i].value, 867 MT9M111_EFFECTS_MODE_MASK); 868 } 869 } 870 871 return -EINVAL; 872 } 873 874 static int mt9m111_s_ctrl(struct v4l2_ctrl *ctrl) 875 { 876 struct mt9m111 *mt9m111 = container_of(ctrl->handler, 877 struct mt9m111, hdl); 878 879 switch (ctrl->id) { 880 case V4L2_CID_VFLIP: 881 return mt9m111_set_flip(mt9m111, ctrl->val, 882 MT9M111_RMB_MIRROR_ROWS); 883 case V4L2_CID_HFLIP: 884 return mt9m111_set_flip(mt9m111, ctrl->val, 885 MT9M111_RMB_MIRROR_COLS); 886 case V4L2_CID_GAIN: 887 return mt9m111_set_global_gain(mt9m111, ctrl->val); 888 case V4L2_CID_EXPOSURE_AUTO: 889 return mt9m111_set_autoexposure(mt9m111, ctrl->val); 890 case V4L2_CID_AUTO_WHITE_BALANCE: 891 return mt9m111_set_autowhitebalance(mt9m111, ctrl->val); 892 case V4L2_CID_TEST_PATTERN: 893 return mt9m111_set_test_pattern(mt9m111, ctrl->val); 894 case V4L2_CID_COLORFX: 895 return mt9m111_set_colorfx(mt9m111, ctrl->val); 896 } 897 898 return -EINVAL; 899 } 900 901 static int mt9m111_suspend(struct mt9m111 *mt9m111) 902 { 903 struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev); 904 int ret; 905 906 v4l2_ctrl_s_ctrl(mt9m111->gain, mt9m111_get_global_gain(mt9m111)); 907 908 ret = reg_set(RESET, MT9M111_RESET_RESET_MODE); 909 if (!ret) 910 ret = reg_set(RESET, MT9M111_RESET_RESET_SOC | 911 MT9M111_RESET_OUTPUT_DISABLE | 912 MT9M111_RESET_ANALOG_STANDBY); 913 if (!ret) 914 ret = reg_clear(RESET, MT9M111_RESET_CHIP_ENABLE); 915 916 return ret; 917 } 918 919 static void mt9m111_restore_state(struct mt9m111 *mt9m111) 920 { 921 struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev); 922 923 mt9m111_set_context(mt9m111, mt9m111->ctx); 924 mt9m111_set_pixfmt(mt9m111, mt9m111->fmt->code); 925 mt9m111_setup_geometry(mt9m111, &mt9m111->rect, 926 mt9m111->width, mt9m111->height, mt9m111->fmt->code); 927 v4l2_ctrl_handler_setup(&mt9m111->hdl); 928 mt9m111_reg_mask(client, mt9m111->ctx->read_mode, 929 mt9m111->current_mode->reg_val, 930 mt9m111->current_mode->reg_mask); 931 } 932 933 static int mt9m111_resume(struct mt9m111 *mt9m111) 934 { 935 int ret = mt9m111_enable(mt9m111); 936 if (!ret) 937 ret = mt9m111_reset(mt9m111); 938 if (!ret) 939 mt9m111_restore_state(mt9m111); 940 941 return ret; 942 } 943 944 static int mt9m111_init(struct mt9m111 *mt9m111) 945 { 946 struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev); 947 int ret; 948 949 ret = mt9m111_enable(mt9m111); 950 if (!ret) 951 ret = mt9m111_reset(mt9m111); 952 if (!ret) 953 ret = mt9m111_set_context(mt9m111, mt9m111->ctx); 954 if (ret) 955 dev_err(&client->dev, "mt9m111 init failed: %d\n", ret); 956 return ret; 957 } 958 959 static int mt9m111_power_on(struct mt9m111 *mt9m111) 960 { 961 struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev); 962 int ret; 963 964 ret = v4l2_clk_enable(mt9m111->clk); 965 if (ret < 0) 966 return ret; 967 968 ret = mt9m111_resume(mt9m111); 969 if (ret < 0) { 970 dev_err(&client->dev, "Failed to resume the sensor: %d\n", ret); 971 v4l2_clk_disable(mt9m111->clk); 972 } 973 974 return ret; 975 } 976 977 static void mt9m111_power_off(struct mt9m111 *mt9m111) 978 { 979 mt9m111_suspend(mt9m111); 980 v4l2_clk_disable(mt9m111->clk); 981 } 982 983 static int mt9m111_s_power(struct v4l2_subdev *sd, int on) 984 { 985 struct mt9m111 *mt9m111 = container_of(sd, struct mt9m111, subdev); 986 int ret = 0; 987 988 mutex_lock(&mt9m111->power_lock); 989 990 /* 991 * If the power count is modified from 0 to != 0 or from != 0 to 0, 992 * update the power state. 993 */ 994 if (mt9m111->power_count == !on) { 995 if (on) 996 ret = mt9m111_power_on(mt9m111); 997 else 998 mt9m111_power_off(mt9m111); 999 } 1000 1001 if (!ret) { 1002 /* Update the power count. */ 1003 mt9m111->power_count += on ? 1 : -1; 1004 WARN_ON(mt9m111->power_count < 0); 1005 } 1006 1007 mutex_unlock(&mt9m111->power_lock); 1008 return ret; 1009 } 1010 1011 static const struct v4l2_ctrl_ops mt9m111_ctrl_ops = { 1012 .s_ctrl = mt9m111_s_ctrl, 1013 }; 1014 1015 static const struct v4l2_subdev_core_ops mt9m111_subdev_core_ops = { 1016 .s_power = mt9m111_s_power, 1017 .log_status = v4l2_ctrl_subdev_log_status, 1018 .subscribe_event = v4l2_ctrl_subdev_subscribe_event, 1019 .unsubscribe_event = v4l2_event_subdev_unsubscribe, 1020 #ifdef CONFIG_VIDEO_ADV_DEBUG 1021 .g_register = mt9m111_g_register, 1022 .s_register = mt9m111_s_register, 1023 #endif 1024 }; 1025 1026 static int mt9m111_g_frame_interval(struct v4l2_subdev *sd, 1027 struct v4l2_subdev_frame_interval *fi) 1028 { 1029 struct mt9m111 *mt9m111 = container_of(sd, struct mt9m111, subdev); 1030 1031 fi->interval = mt9m111->frame_interval; 1032 1033 return 0; 1034 } 1035 1036 static int mt9m111_s_frame_interval(struct v4l2_subdev *sd, 1037 struct v4l2_subdev_frame_interval *fi) 1038 { 1039 struct mt9m111 *mt9m111 = container_of(sd, struct mt9m111, subdev); 1040 const struct mt9m111_mode_info *mode; 1041 struct v4l2_fract *fract = &fi->interval; 1042 int fps; 1043 1044 if (mt9m111->is_streaming) 1045 return -EBUSY; 1046 1047 if (fi->pad != 0) 1048 return -EINVAL; 1049 1050 if (fract->numerator == 0) { 1051 fract->denominator = 30; 1052 fract->numerator = 1; 1053 } 1054 1055 fps = DIV_ROUND_CLOSEST(fract->denominator, fract->numerator); 1056 1057 /* Find best fitting mode. Do not update the mode if no one was found. */ 1058 mode = mt9m111_find_mode(mt9m111, fps, mt9m111->width, mt9m111->height); 1059 if (!mode) 1060 return 0; 1061 1062 if (mode->max_fps != fps) { 1063 fract->denominator = mode->max_fps; 1064 fract->numerator = 1; 1065 } 1066 1067 mt9m111->current_mode = mode; 1068 mt9m111->frame_interval = fi->interval; 1069 1070 return 0; 1071 } 1072 1073 static int mt9m111_enum_mbus_code(struct v4l2_subdev *sd, 1074 struct v4l2_subdev_pad_config *cfg, 1075 struct v4l2_subdev_mbus_code_enum *code) 1076 { 1077 if (code->pad || code->index >= ARRAY_SIZE(mt9m111_colour_fmts)) 1078 return -EINVAL; 1079 1080 code->code = mt9m111_colour_fmts[code->index].code; 1081 return 0; 1082 } 1083 1084 static int mt9m111_s_stream(struct v4l2_subdev *sd, int enable) 1085 { 1086 struct mt9m111 *mt9m111 = container_of(sd, struct mt9m111, subdev); 1087 1088 mt9m111->is_streaming = !!enable; 1089 return 0; 1090 } 1091 1092 static int mt9m111_g_mbus_config(struct v4l2_subdev *sd, 1093 struct v4l2_mbus_config *cfg) 1094 { 1095 struct mt9m111 *mt9m111 = container_of(sd, struct mt9m111, subdev); 1096 1097 cfg->flags = V4L2_MBUS_MASTER | 1098 V4L2_MBUS_HSYNC_ACTIVE_HIGH | V4L2_MBUS_VSYNC_ACTIVE_HIGH | 1099 V4L2_MBUS_DATA_ACTIVE_HIGH; 1100 1101 cfg->flags |= mt9m111->pclk_sample ? V4L2_MBUS_PCLK_SAMPLE_RISING : 1102 V4L2_MBUS_PCLK_SAMPLE_FALLING; 1103 1104 cfg->type = V4L2_MBUS_PARALLEL; 1105 1106 return 0; 1107 } 1108 1109 static const struct v4l2_subdev_video_ops mt9m111_subdev_video_ops = { 1110 .g_mbus_config = mt9m111_g_mbus_config, 1111 .s_stream = mt9m111_s_stream, 1112 .g_frame_interval = mt9m111_g_frame_interval, 1113 .s_frame_interval = mt9m111_s_frame_interval, 1114 }; 1115 1116 static const struct v4l2_subdev_pad_ops mt9m111_subdev_pad_ops = { 1117 .enum_mbus_code = mt9m111_enum_mbus_code, 1118 .get_selection = mt9m111_get_selection, 1119 .set_selection = mt9m111_set_selection, 1120 .get_fmt = mt9m111_get_fmt, 1121 .set_fmt = mt9m111_set_fmt, 1122 }; 1123 1124 static const struct v4l2_subdev_ops mt9m111_subdev_ops = { 1125 .core = &mt9m111_subdev_core_ops, 1126 .video = &mt9m111_subdev_video_ops, 1127 .pad = &mt9m111_subdev_pad_ops, 1128 }; 1129 1130 /* 1131 * Interface active, can use i2c. If it fails, it can indeed mean, that 1132 * this wasn't our capture interface, so, we wait for the right one 1133 */ 1134 static int mt9m111_video_probe(struct i2c_client *client) 1135 { 1136 struct mt9m111 *mt9m111 = to_mt9m111(client); 1137 s32 data; 1138 int ret; 1139 1140 ret = mt9m111_s_power(&mt9m111->subdev, 1); 1141 if (ret < 0) 1142 return ret; 1143 1144 data = reg_read(CHIP_VERSION); 1145 1146 switch (data) { 1147 case 0x143a: /* MT9M111 or MT9M131 */ 1148 dev_info(&client->dev, 1149 "Detected a MT9M111/MT9M131 chip ID %x\n", data); 1150 break; 1151 case 0x148c: /* MT9M112 */ 1152 dev_info(&client->dev, "Detected a MT9M112 chip ID %x\n", data); 1153 break; 1154 default: 1155 dev_err(&client->dev, 1156 "No MT9M111/MT9M112/MT9M131 chip detected register read %x\n", 1157 data); 1158 ret = -ENODEV; 1159 goto done; 1160 } 1161 1162 ret = mt9m111_init(mt9m111); 1163 if (ret) 1164 goto done; 1165 1166 ret = v4l2_ctrl_handler_setup(&mt9m111->hdl); 1167 1168 done: 1169 mt9m111_s_power(&mt9m111->subdev, 0); 1170 return ret; 1171 } 1172 1173 static int mt9m111_probe_fw(struct i2c_client *client, struct mt9m111 *mt9m111) 1174 { 1175 struct v4l2_fwnode_endpoint bus_cfg = { 1176 .bus_type = V4L2_MBUS_PARALLEL 1177 }; 1178 struct fwnode_handle *np; 1179 int ret; 1180 1181 np = fwnode_graph_get_next_endpoint(dev_fwnode(&client->dev), NULL); 1182 if (!np) 1183 return -EINVAL; 1184 1185 ret = v4l2_fwnode_endpoint_parse(np, &bus_cfg); 1186 if (ret) 1187 goto out_put_fw; 1188 1189 mt9m111->pclk_sample = !!(bus_cfg.bus.parallel.flags & 1190 V4L2_MBUS_PCLK_SAMPLE_RISING); 1191 1192 out_put_fw: 1193 fwnode_handle_put(np); 1194 return ret; 1195 } 1196 1197 static int mt9m111_probe(struct i2c_client *client, 1198 const struct i2c_device_id *did) 1199 { 1200 struct mt9m111 *mt9m111; 1201 struct i2c_adapter *adapter = to_i2c_adapter(client->dev.parent); 1202 int ret; 1203 1204 if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_WORD_DATA)) { 1205 dev_warn(&adapter->dev, 1206 "I2C-Adapter doesn't support I2C_FUNC_SMBUS_WORD\n"); 1207 return -EIO; 1208 } 1209 1210 mt9m111 = devm_kzalloc(&client->dev, sizeof(struct mt9m111), GFP_KERNEL); 1211 if (!mt9m111) 1212 return -ENOMEM; 1213 1214 ret = mt9m111_probe_fw(client, mt9m111); 1215 if (ret) 1216 return ret; 1217 1218 mt9m111->clk = v4l2_clk_get(&client->dev, "mclk"); 1219 if (IS_ERR(mt9m111->clk)) 1220 return PTR_ERR(mt9m111->clk); 1221 1222 /* Default HIGHPOWER context */ 1223 mt9m111->ctx = &context_b; 1224 1225 v4l2_i2c_subdev_init(&mt9m111->subdev, client, &mt9m111_subdev_ops); 1226 mt9m111->subdev.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | 1227 V4L2_SUBDEV_FL_HAS_EVENTS; 1228 1229 v4l2_ctrl_handler_init(&mt9m111->hdl, 7); 1230 v4l2_ctrl_new_std(&mt9m111->hdl, &mt9m111_ctrl_ops, 1231 V4L2_CID_VFLIP, 0, 1, 1, 0); 1232 v4l2_ctrl_new_std(&mt9m111->hdl, &mt9m111_ctrl_ops, 1233 V4L2_CID_HFLIP, 0, 1, 1, 0); 1234 v4l2_ctrl_new_std(&mt9m111->hdl, &mt9m111_ctrl_ops, 1235 V4L2_CID_AUTO_WHITE_BALANCE, 0, 1, 1, 1); 1236 mt9m111->gain = v4l2_ctrl_new_std(&mt9m111->hdl, &mt9m111_ctrl_ops, 1237 V4L2_CID_GAIN, 0, 63 * 2 * 2, 1, 32); 1238 v4l2_ctrl_new_std_menu(&mt9m111->hdl, 1239 &mt9m111_ctrl_ops, V4L2_CID_EXPOSURE_AUTO, 1, 0, 1240 V4L2_EXPOSURE_AUTO); 1241 v4l2_ctrl_new_std_menu_items(&mt9m111->hdl, 1242 &mt9m111_ctrl_ops, V4L2_CID_TEST_PATTERN, 1243 ARRAY_SIZE(mt9m111_test_pattern_menu) - 1, 0, 0, 1244 mt9m111_test_pattern_menu); 1245 v4l2_ctrl_new_std_menu(&mt9m111->hdl, &mt9m111_ctrl_ops, 1246 V4L2_CID_COLORFX, V4L2_COLORFX_SOLARIZATION, 1247 ~(BIT(V4L2_COLORFX_NONE) | 1248 BIT(V4L2_COLORFX_BW) | 1249 BIT(V4L2_COLORFX_SEPIA) | 1250 BIT(V4L2_COLORFX_NEGATIVE) | 1251 BIT(V4L2_COLORFX_SOLARIZATION)), 1252 V4L2_COLORFX_NONE); 1253 mt9m111->subdev.ctrl_handler = &mt9m111->hdl; 1254 if (mt9m111->hdl.error) { 1255 ret = mt9m111->hdl.error; 1256 goto out_clkput; 1257 } 1258 1259 #ifdef CONFIG_MEDIA_CONTROLLER 1260 mt9m111->pad.flags = MEDIA_PAD_FL_SOURCE; 1261 mt9m111->subdev.entity.function = MEDIA_ENT_F_CAM_SENSOR; 1262 ret = media_entity_pads_init(&mt9m111->subdev.entity, 1, &mt9m111->pad); 1263 if (ret < 0) 1264 goto out_hdlfree; 1265 #endif 1266 1267 mt9m111->current_mode = &mt9m111_mode_data[MT9M111_MODE_SXGA_15FPS]; 1268 mt9m111->frame_interval.numerator = 1; 1269 mt9m111->frame_interval.denominator = mt9m111->current_mode->max_fps; 1270 1271 /* Second stage probe - when a capture adapter is there */ 1272 mt9m111->rect.left = MT9M111_MIN_DARK_COLS; 1273 mt9m111->rect.top = MT9M111_MIN_DARK_ROWS; 1274 mt9m111->rect.width = MT9M111_MAX_WIDTH; 1275 mt9m111->rect.height = MT9M111_MAX_HEIGHT; 1276 mt9m111->fmt = &mt9m111_colour_fmts[0]; 1277 mt9m111->lastpage = -1; 1278 mutex_init(&mt9m111->power_lock); 1279 1280 ret = mt9m111_video_probe(client); 1281 if (ret < 0) 1282 goto out_entityclean; 1283 1284 mt9m111->subdev.dev = &client->dev; 1285 ret = v4l2_async_register_subdev(&mt9m111->subdev); 1286 if (ret < 0) 1287 goto out_entityclean; 1288 1289 return 0; 1290 1291 out_entityclean: 1292 #ifdef CONFIG_MEDIA_CONTROLLER 1293 media_entity_cleanup(&mt9m111->subdev.entity); 1294 out_hdlfree: 1295 #endif 1296 v4l2_ctrl_handler_free(&mt9m111->hdl); 1297 out_clkput: 1298 v4l2_clk_put(mt9m111->clk); 1299 1300 return ret; 1301 } 1302 1303 static int mt9m111_remove(struct i2c_client *client) 1304 { 1305 struct mt9m111 *mt9m111 = to_mt9m111(client); 1306 1307 v4l2_async_unregister_subdev(&mt9m111->subdev); 1308 media_entity_cleanup(&mt9m111->subdev.entity); 1309 v4l2_clk_put(mt9m111->clk); 1310 v4l2_ctrl_handler_free(&mt9m111->hdl); 1311 1312 return 0; 1313 } 1314 static const struct of_device_id mt9m111_of_match[] = { 1315 { .compatible = "micron,mt9m111", }, 1316 {}, 1317 }; 1318 MODULE_DEVICE_TABLE(of, mt9m111_of_match); 1319 1320 static const struct i2c_device_id mt9m111_id[] = { 1321 { "mt9m111", 0 }, 1322 { } 1323 }; 1324 MODULE_DEVICE_TABLE(i2c, mt9m111_id); 1325 1326 static struct i2c_driver mt9m111_i2c_driver = { 1327 .driver = { 1328 .name = "mt9m111", 1329 .of_match_table = of_match_ptr(mt9m111_of_match), 1330 }, 1331 .probe = mt9m111_probe, 1332 .remove = mt9m111_remove, 1333 .id_table = mt9m111_id, 1334 }; 1335 1336 module_i2c_driver(mt9m111_i2c_driver); 1337 1338 MODULE_DESCRIPTION("Micron/Aptina MT9M111/MT9M112/MT9M131 Camera driver"); 1339 MODULE_AUTHOR("Robert Jarzmik"); 1340 MODULE_LICENSE("GPL"); 1341