1 /* 2 * Driver for MT9M111/MT9M112/MT9M131 CMOS Image Sensor from Micron/Aptina 3 * 4 * Copyright (C) 2008, Robert Jarzmik <robert.jarzmik@free.fr> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 #include <linux/videodev2.h> 11 #include <linux/slab.h> 12 #include <linux/i2c.h> 13 #include <linux/log2.h> 14 #include <linux/gpio.h> 15 #include <linux/delay.h> 16 #include <linux/regulator/consumer.h> 17 #include <linux/v4l2-mediabus.h> 18 #include <linux/module.h> 19 #include <linux/property.h> 20 21 #include <media/v4l2-async.h> 22 #include <media/v4l2-clk.h> 23 #include <media/v4l2-common.h> 24 #include <media/v4l2-ctrls.h> 25 #include <media/v4l2-device.h> 26 #include <media/v4l2-event.h> 27 #include <media/v4l2-fwnode.h> 28 29 /* 30 * MT9M111, MT9M112 and MT9M131: 31 * i2c address is 0x48 or 0x5d (depending on SADDR pin) 32 * The platform has to define struct i2c_board_info objects and link to them 33 * from struct soc_camera_host_desc 34 */ 35 36 /* 37 * Sensor core register addresses (0x000..0x0ff) 38 */ 39 #define MT9M111_CHIP_VERSION 0x000 40 #define MT9M111_ROW_START 0x001 41 #define MT9M111_COLUMN_START 0x002 42 #define MT9M111_WINDOW_HEIGHT 0x003 43 #define MT9M111_WINDOW_WIDTH 0x004 44 #define MT9M111_HORIZONTAL_BLANKING_B 0x005 45 #define MT9M111_VERTICAL_BLANKING_B 0x006 46 #define MT9M111_HORIZONTAL_BLANKING_A 0x007 47 #define MT9M111_VERTICAL_BLANKING_A 0x008 48 #define MT9M111_SHUTTER_WIDTH 0x009 49 #define MT9M111_ROW_SPEED 0x00a 50 #define MT9M111_EXTRA_DELAY 0x00b 51 #define MT9M111_SHUTTER_DELAY 0x00c 52 #define MT9M111_RESET 0x00d 53 #define MT9M111_READ_MODE_B 0x020 54 #define MT9M111_READ_MODE_A 0x021 55 #define MT9M111_FLASH_CONTROL 0x023 56 #define MT9M111_GREEN1_GAIN 0x02b 57 #define MT9M111_BLUE_GAIN 0x02c 58 #define MT9M111_RED_GAIN 0x02d 59 #define MT9M111_GREEN2_GAIN 0x02e 60 #define MT9M111_GLOBAL_GAIN 0x02f 61 #define MT9M111_CONTEXT_CONTROL 0x0c8 62 #define MT9M111_PAGE_MAP 0x0f0 63 #define MT9M111_BYTE_WISE_ADDR 0x0f1 64 65 #define MT9M111_RESET_SYNC_CHANGES (1 << 15) 66 #define MT9M111_RESET_RESTART_BAD_FRAME (1 << 9) 67 #define MT9M111_RESET_SHOW_BAD_FRAMES (1 << 8) 68 #define MT9M111_RESET_RESET_SOC (1 << 5) 69 #define MT9M111_RESET_OUTPUT_DISABLE (1 << 4) 70 #define MT9M111_RESET_CHIP_ENABLE (1 << 3) 71 #define MT9M111_RESET_ANALOG_STANDBY (1 << 2) 72 #define MT9M111_RESET_RESTART_FRAME (1 << 1) 73 #define MT9M111_RESET_RESET_MODE (1 << 0) 74 75 #define MT9M111_RM_FULL_POWER_RD (0 << 10) 76 #define MT9M111_RM_LOW_POWER_RD (1 << 10) 77 #define MT9M111_RM_COL_SKIP_4X (1 << 5) 78 #define MT9M111_RM_ROW_SKIP_4X (1 << 4) 79 #define MT9M111_RM_COL_SKIP_2X (1 << 3) 80 #define MT9M111_RM_ROW_SKIP_2X (1 << 2) 81 #define MT9M111_RMB_MIRROR_COLS (1 << 1) 82 #define MT9M111_RMB_MIRROR_ROWS (1 << 0) 83 #define MT9M111_CTXT_CTRL_RESTART (1 << 15) 84 #define MT9M111_CTXT_CTRL_DEFECTCOR_B (1 << 12) 85 #define MT9M111_CTXT_CTRL_RESIZE_B (1 << 10) 86 #define MT9M111_CTXT_CTRL_CTRL2_B (1 << 9) 87 #define MT9M111_CTXT_CTRL_GAMMA_B (1 << 8) 88 #define MT9M111_CTXT_CTRL_XENON_EN (1 << 7) 89 #define MT9M111_CTXT_CTRL_READ_MODE_B (1 << 3) 90 #define MT9M111_CTXT_CTRL_LED_FLASH_EN (1 << 2) 91 #define MT9M111_CTXT_CTRL_VBLANK_SEL_B (1 << 1) 92 #define MT9M111_CTXT_CTRL_HBLANK_SEL_B (1 << 0) 93 94 /* 95 * Colorpipe register addresses (0x100..0x1ff) 96 */ 97 #define MT9M111_OPER_MODE_CTRL 0x106 98 #define MT9M111_OUTPUT_FORMAT_CTRL 0x108 99 #define MT9M111_TPG_CTRL 0x148 100 #define MT9M111_REDUCER_XZOOM_B 0x1a0 101 #define MT9M111_REDUCER_XSIZE_B 0x1a1 102 #define MT9M111_REDUCER_YZOOM_B 0x1a3 103 #define MT9M111_REDUCER_YSIZE_B 0x1a4 104 #define MT9M111_REDUCER_XZOOM_A 0x1a6 105 #define MT9M111_REDUCER_XSIZE_A 0x1a7 106 #define MT9M111_REDUCER_YZOOM_A 0x1a9 107 #define MT9M111_REDUCER_YSIZE_A 0x1aa 108 #define MT9M111_EFFECTS_MODE 0x1e2 109 110 #define MT9M111_OUTPUT_FORMAT_CTRL2_A 0x13a 111 #define MT9M111_OUTPUT_FORMAT_CTRL2_B 0x19b 112 113 #define MT9M111_OPMODE_AUTOEXPO_EN (1 << 14) 114 #define MT9M111_OPMODE_AUTOWHITEBAL_EN (1 << 1) 115 #define MT9M111_OUTFMT_FLIP_BAYER_COL (1 << 9) 116 #define MT9M111_OUTFMT_FLIP_BAYER_ROW (1 << 8) 117 #define MT9M111_OUTFMT_PROCESSED_BAYER (1 << 14) 118 #define MT9M111_OUTFMT_BYPASS_IFP (1 << 10) 119 #define MT9M111_OUTFMT_INV_PIX_CLOCK (1 << 9) 120 #define MT9M111_OUTFMT_RGB (1 << 8) 121 #define MT9M111_OUTFMT_RGB565 (0 << 6) 122 #define MT9M111_OUTFMT_RGB555 (1 << 6) 123 #define MT9M111_OUTFMT_RGB444x (2 << 6) 124 #define MT9M111_OUTFMT_RGBx444 (3 << 6) 125 #define MT9M111_OUTFMT_TST_RAMP_OFF (0 << 4) 126 #define MT9M111_OUTFMT_TST_RAMP_COL (1 << 4) 127 #define MT9M111_OUTFMT_TST_RAMP_ROW (2 << 4) 128 #define MT9M111_OUTFMT_TST_RAMP_FRAME (3 << 4) 129 #define MT9M111_OUTFMT_SHIFT_3_UP (1 << 3) 130 #define MT9M111_OUTFMT_AVG_CHROMA (1 << 2) 131 #define MT9M111_OUTFMT_SWAP_YCbCr_C_Y_RGB_EVEN (1 << 1) 132 #define MT9M111_OUTFMT_SWAP_YCbCr_Cb_Cr_RGB_R_B (1 << 0) 133 #define MT9M111_TPG_SEL_MASK GENMASK(2, 0) 134 #define MT9M111_EFFECTS_MODE_MASK GENMASK(2, 0) 135 #define MT9M111_RM_PWR_MASK BIT(10) 136 #define MT9M111_RM_SKIP2_MASK GENMASK(3, 2) 137 138 /* 139 * Camera control register addresses (0x200..0x2ff not implemented) 140 */ 141 142 #define reg_read(reg) mt9m111_reg_read(client, MT9M111_##reg) 143 #define reg_write(reg, val) mt9m111_reg_write(client, MT9M111_##reg, (val)) 144 #define reg_set(reg, val) mt9m111_reg_set(client, MT9M111_##reg, (val)) 145 #define reg_clear(reg, val) mt9m111_reg_clear(client, MT9M111_##reg, (val)) 146 #define reg_mask(reg, val, mask) mt9m111_reg_mask(client, MT9M111_##reg, \ 147 (val), (mask)) 148 149 #define MT9M111_MIN_DARK_ROWS 8 150 #define MT9M111_MIN_DARK_COLS 26 151 #define MT9M111_MAX_HEIGHT 1024 152 #define MT9M111_MAX_WIDTH 1280 153 154 struct mt9m111_context { 155 u16 read_mode; 156 u16 blanking_h; 157 u16 blanking_v; 158 u16 reducer_xzoom; 159 u16 reducer_yzoom; 160 u16 reducer_xsize; 161 u16 reducer_ysize; 162 u16 output_fmt_ctrl2; 163 u16 control; 164 }; 165 166 static struct mt9m111_context context_a = { 167 .read_mode = MT9M111_READ_MODE_A, 168 .blanking_h = MT9M111_HORIZONTAL_BLANKING_A, 169 .blanking_v = MT9M111_VERTICAL_BLANKING_A, 170 .reducer_xzoom = MT9M111_REDUCER_XZOOM_A, 171 .reducer_yzoom = MT9M111_REDUCER_YZOOM_A, 172 .reducer_xsize = MT9M111_REDUCER_XSIZE_A, 173 .reducer_ysize = MT9M111_REDUCER_YSIZE_A, 174 .output_fmt_ctrl2 = MT9M111_OUTPUT_FORMAT_CTRL2_A, 175 .control = MT9M111_CTXT_CTRL_RESTART, 176 }; 177 178 static struct mt9m111_context context_b = { 179 .read_mode = MT9M111_READ_MODE_B, 180 .blanking_h = MT9M111_HORIZONTAL_BLANKING_B, 181 .blanking_v = MT9M111_VERTICAL_BLANKING_B, 182 .reducer_xzoom = MT9M111_REDUCER_XZOOM_B, 183 .reducer_yzoom = MT9M111_REDUCER_YZOOM_B, 184 .reducer_xsize = MT9M111_REDUCER_XSIZE_B, 185 .reducer_ysize = MT9M111_REDUCER_YSIZE_B, 186 .output_fmt_ctrl2 = MT9M111_OUTPUT_FORMAT_CTRL2_B, 187 .control = MT9M111_CTXT_CTRL_RESTART | 188 MT9M111_CTXT_CTRL_DEFECTCOR_B | MT9M111_CTXT_CTRL_RESIZE_B | 189 MT9M111_CTXT_CTRL_CTRL2_B | MT9M111_CTXT_CTRL_GAMMA_B | 190 MT9M111_CTXT_CTRL_READ_MODE_B | MT9M111_CTXT_CTRL_VBLANK_SEL_B | 191 MT9M111_CTXT_CTRL_HBLANK_SEL_B, 192 }; 193 194 /* MT9M111 has only one fixed colorspace per pixelcode */ 195 struct mt9m111_datafmt { 196 u32 code; 197 enum v4l2_colorspace colorspace; 198 }; 199 200 static const struct mt9m111_datafmt mt9m111_colour_fmts[] = { 201 {MEDIA_BUS_FMT_YUYV8_2X8, V4L2_COLORSPACE_SRGB}, 202 {MEDIA_BUS_FMT_YVYU8_2X8, V4L2_COLORSPACE_SRGB}, 203 {MEDIA_BUS_FMT_UYVY8_2X8, V4L2_COLORSPACE_SRGB}, 204 {MEDIA_BUS_FMT_VYUY8_2X8, V4L2_COLORSPACE_SRGB}, 205 {MEDIA_BUS_FMT_RGB555_2X8_PADHI_LE, V4L2_COLORSPACE_SRGB}, 206 {MEDIA_BUS_FMT_RGB555_2X8_PADHI_BE, V4L2_COLORSPACE_SRGB}, 207 {MEDIA_BUS_FMT_RGB565_2X8_LE, V4L2_COLORSPACE_SRGB}, 208 {MEDIA_BUS_FMT_RGB565_2X8_BE, V4L2_COLORSPACE_SRGB}, 209 {MEDIA_BUS_FMT_BGR565_2X8_LE, V4L2_COLORSPACE_SRGB}, 210 {MEDIA_BUS_FMT_BGR565_2X8_BE, V4L2_COLORSPACE_SRGB}, 211 {MEDIA_BUS_FMT_SBGGR8_1X8, V4L2_COLORSPACE_SRGB}, 212 {MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_LE, V4L2_COLORSPACE_SRGB}, 213 }; 214 215 enum mt9m111_mode_id { 216 MT9M111_MODE_SXGA_8FPS, 217 MT9M111_MODE_SXGA_15FPS, 218 MT9M111_MODE_QSXGA_30FPS, 219 MT9M111_NUM_MODES, 220 }; 221 222 struct mt9m111_mode_info { 223 unsigned int sensor_w; 224 unsigned int sensor_h; 225 unsigned int max_image_w; 226 unsigned int max_image_h; 227 unsigned int max_fps; 228 unsigned int reg_val; 229 unsigned int reg_mask; 230 }; 231 232 struct mt9m111 { 233 struct v4l2_subdev subdev; 234 struct v4l2_ctrl_handler hdl; 235 struct v4l2_ctrl *gain; 236 struct mt9m111_context *ctx; 237 struct v4l2_rect rect; /* cropping rectangle */ 238 struct v4l2_clk *clk; 239 unsigned int width; /* output */ 240 unsigned int height; /* sizes */ 241 struct v4l2_fract frame_interval; 242 const struct mt9m111_mode_info *current_mode; 243 struct mutex power_lock; /* lock to protect power_count */ 244 int power_count; 245 const struct mt9m111_datafmt *fmt; 246 int lastpage; /* PageMap cache value */ 247 struct regulator *regulator; 248 bool is_streaming; 249 /* user point of view - 0: falling 1: rising edge */ 250 unsigned int pclk_sample:1; 251 #ifdef CONFIG_MEDIA_CONTROLLER 252 struct media_pad pad; 253 #endif 254 }; 255 256 static const struct mt9m111_mode_info mt9m111_mode_data[MT9M111_NUM_MODES] = { 257 [MT9M111_MODE_SXGA_8FPS] = { 258 .sensor_w = 1280, 259 .sensor_h = 1024, 260 .max_image_w = 1280, 261 .max_image_h = 1024, 262 .max_fps = 8, 263 .reg_val = MT9M111_RM_LOW_POWER_RD, 264 .reg_mask = MT9M111_RM_PWR_MASK | MT9M111_RM_SKIP2_MASK, 265 }, 266 [MT9M111_MODE_SXGA_15FPS] = { 267 .sensor_w = 1280, 268 .sensor_h = 1024, 269 .max_image_w = 1280, 270 .max_image_h = 1024, 271 .max_fps = 15, 272 .reg_val = MT9M111_RM_FULL_POWER_RD, 273 .reg_mask = MT9M111_RM_PWR_MASK | MT9M111_RM_SKIP2_MASK, 274 }, 275 [MT9M111_MODE_QSXGA_30FPS] = { 276 .sensor_w = 1280, 277 .sensor_h = 1024, 278 .max_image_w = 640, 279 .max_image_h = 512, 280 .max_fps = 30, 281 .reg_val = MT9M111_RM_LOW_POWER_RD | MT9M111_RM_COL_SKIP_2X | 282 MT9M111_RM_ROW_SKIP_2X, 283 .reg_mask = MT9M111_RM_PWR_MASK | MT9M111_RM_SKIP2_MASK, 284 }, 285 }; 286 287 /* Find a data format by a pixel code */ 288 static const struct mt9m111_datafmt *mt9m111_find_datafmt(struct mt9m111 *mt9m111, 289 u32 code) 290 { 291 int i; 292 for (i = 0; i < ARRAY_SIZE(mt9m111_colour_fmts); i++) 293 if (mt9m111_colour_fmts[i].code == code) 294 return mt9m111_colour_fmts + i; 295 296 return mt9m111->fmt; 297 } 298 299 static struct mt9m111 *to_mt9m111(const struct i2c_client *client) 300 { 301 return container_of(i2c_get_clientdata(client), struct mt9m111, subdev); 302 } 303 304 static int reg_page_map_set(struct i2c_client *client, const u16 reg) 305 { 306 int ret; 307 u16 page; 308 struct mt9m111 *mt9m111 = to_mt9m111(client); 309 310 page = (reg >> 8); 311 if (page == mt9m111->lastpage) 312 return 0; 313 if (page > 2) 314 return -EINVAL; 315 316 ret = i2c_smbus_write_word_swapped(client, MT9M111_PAGE_MAP, page); 317 if (!ret) 318 mt9m111->lastpage = page; 319 return ret; 320 } 321 322 static int mt9m111_reg_read(struct i2c_client *client, const u16 reg) 323 { 324 int ret; 325 326 ret = reg_page_map_set(client, reg); 327 if (!ret) 328 ret = i2c_smbus_read_word_swapped(client, reg & 0xff); 329 330 dev_dbg(&client->dev, "read reg.%03x -> %04x\n", reg, ret); 331 return ret; 332 } 333 334 static int mt9m111_reg_write(struct i2c_client *client, const u16 reg, 335 const u16 data) 336 { 337 int ret; 338 339 ret = reg_page_map_set(client, reg); 340 if (!ret) 341 ret = i2c_smbus_write_word_swapped(client, reg & 0xff, data); 342 dev_dbg(&client->dev, "write reg.%03x = %04x -> %d\n", reg, data, ret); 343 return ret; 344 } 345 346 static int mt9m111_reg_set(struct i2c_client *client, const u16 reg, 347 const u16 data) 348 { 349 int ret; 350 351 ret = mt9m111_reg_read(client, reg); 352 if (ret >= 0) 353 ret = mt9m111_reg_write(client, reg, ret | data); 354 return ret; 355 } 356 357 static int mt9m111_reg_clear(struct i2c_client *client, const u16 reg, 358 const u16 data) 359 { 360 int ret; 361 362 ret = mt9m111_reg_read(client, reg); 363 if (ret >= 0) 364 ret = mt9m111_reg_write(client, reg, ret & ~data); 365 return ret; 366 } 367 368 static int mt9m111_reg_mask(struct i2c_client *client, const u16 reg, 369 const u16 data, const u16 mask) 370 { 371 int ret; 372 373 ret = mt9m111_reg_read(client, reg); 374 if (ret >= 0) 375 ret = mt9m111_reg_write(client, reg, (ret & ~mask) | data); 376 return ret; 377 } 378 379 static int mt9m111_set_context(struct mt9m111 *mt9m111, 380 struct mt9m111_context *ctx) 381 { 382 struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev); 383 return reg_write(CONTEXT_CONTROL, ctx->control); 384 } 385 386 static int mt9m111_setup_rect_ctx(struct mt9m111 *mt9m111, 387 struct mt9m111_context *ctx, struct v4l2_rect *rect, 388 unsigned int width, unsigned int height) 389 { 390 struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev); 391 int ret = mt9m111_reg_write(client, ctx->reducer_xzoom, rect->width); 392 if (!ret) 393 ret = mt9m111_reg_write(client, ctx->reducer_yzoom, rect->height); 394 if (!ret) 395 ret = mt9m111_reg_write(client, ctx->reducer_xsize, width); 396 if (!ret) 397 ret = mt9m111_reg_write(client, ctx->reducer_ysize, height); 398 return ret; 399 } 400 401 static int mt9m111_setup_geometry(struct mt9m111 *mt9m111, struct v4l2_rect *rect, 402 int width, int height, u32 code) 403 { 404 struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev); 405 int ret; 406 407 ret = reg_write(COLUMN_START, rect->left); 408 if (!ret) 409 ret = reg_write(ROW_START, rect->top); 410 411 if (!ret) 412 ret = reg_write(WINDOW_WIDTH, rect->width); 413 if (!ret) 414 ret = reg_write(WINDOW_HEIGHT, rect->height); 415 416 if (code != MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_LE) { 417 /* IFP in use, down-scaling possible */ 418 if (!ret) 419 ret = mt9m111_setup_rect_ctx(mt9m111, &context_b, 420 rect, width, height); 421 if (!ret) 422 ret = mt9m111_setup_rect_ctx(mt9m111, &context_a, 423 rect, width, height); 424 } 425 426 dev_dbg(&client->dev, "%s(%x): %ux%u@%u:%u -> %ux%u = %d\n", 427 __func__, code, rect->width, rect->height, rect->left, rect->top, 428 width, height, ret); 429 430 return ret; 431 } 432 433 static int mt9m111_enable(struct mt9m111 *mt9m111) 434 { 435 struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev); 436 return reg_write(RESET, MT9M111_RESET_CHIP_ENABLE); 437 } 438 439 static int mt9m111_reset(struct mt9m111 *mt9m111) 440 { 441 struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev); 442 int ret; 443 444 ret = reg_set(RESET, MT9M111_RESET_RESET_MODE); 445 if (!ret) 446 ret = reg_set(RESET, MT9M111_RESET_RESET_SOC); 447 if (!ret) 448 ret = reg_clear(RESET, MT9M111_RESET_RESET_MODE 449 | MT9M111_RESET_RESET_SOC); 450 451 return ret; 452 } 453 454 static int mt9m111_set_selection(struct v4l2_subdev *sd, 455 struct v4l2_subdev_pad_config *cfg, 456 struct v4l2_subdev_selection *sel) 457 { 458 struct i2c_client *client = v4l2_get_subdevdata(sd); 459 struct mt9m111 *mt9m111 = to_mt9m111(client); 460 struct v4l2_rect rect = sel->r; 461 int width, height; 462 int ret, align = 0; 463 464 if (sel->which != V4L2_SUBDEV_FORMAT_ACTIVE || 465 sel->target != V4L2_SEL_TGT_CROP) 466 return -EINVAL; 467 468 if (mt9m111->fmt->code == MEDIA_BUS_FMT_SBGGR8_1X8 || 469 mt9m111->fmt->code == MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_LE) { 470 /* Bayer format - even size lengths */ 471 align = 1; 472 /* Let the user play with the starting pixel */ 473 } 474 475 /* FIXME: the datasheet doesn't specify minimum sizes */ 476 v4l_bound_align_image(&rect.width, 2, MT9M111_MAX_WIDTH, align, 477 &rect.height, 2, MT9M111_MAX_HEIGHT, align, 0); 478 rect.left = clamp(rect.left, MT9M111_MIN_DARK_COLS, 479 MT9M111_MIN_DARK_COLS + MT9M111_MAX_WIDTH - 480 (__s32)rect.width); 481 rect.top = clamp(rect.top, MT9M111_MIN_DARK_ROWS, 482 MT9M111_MIN_DARK_ROWS + MT9M111_MAX_HEIGHT - 483 (__s32)rect.height); 484 485 width = min(mt9m111->width, rect.width); 486 height = min(mt9m111->height, rect.height); 487 488 ret = mt9m111_setup_geometry(mt9m111, &rect, width, height, mt9m111->fmt->code); 489 if (!ret) { 490 mt9m111->rect = rect; 491 mt9m111->width = width; 492 mt9m111->height = height; 493 } 494 495 return ret; 496 } 497 498 static int mt9m111_get_selection(struct v4l2_subdev *sd, 499 struct v4l2_subdev_pad_config *cfg, 500 struct v4l2_subdev_selection *sel) 501 { 502 struct i2c_client *client = v4l2_get_subdevdata(sd); 503 struct mt9m111 *mt9m111 = to_mt9m111(client); 504 505 if (sel->which != V4L2_SUBDEV_FORMAT_ACTIVE) 506 return -EINVAL; 507 508 switch (sel->target) { 509 case V4L2_SEL_TGT_CROP_BOUNDS: 510 sel->r.left = MT9M111_MIN_DARK_COLS; 511 sel->r.top = MT9M111_MIN_DARK_ROWS; 512 sel->r.width = MT9M111_MAX_WIDTH; 513 sel->r.height = MT9M111_MAX_HEIGHT; 514 return 0; 515 case V4L2_SEL_TGT_CROP: 516 sel->r = mt9m111->rect; 517 return 0; 518 default: 519 return -EINVAL; 520 } 521 } 522 523 static int mt9m111_get_fmt(struct v4l2_subdev *sd, 524 struct v4l2_subdev_pad_config *cfg, 525 struct v4l2_subdev_format *format) 526 { 527 struct v4l2_mbus_framefmt *mf = &format->format; 528 struct mt9m111 *mt9m111 = container_of(sd, struct mt9m111, subdev); 529 530 if (format->pad) 531 return -EINVAL; 532 533 if (format->which == V4L2_SUBDEV_FORMAT_TRY) { 534 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API 535 mf = v4l2_subdev_get_try_format(sd, cfg, format->pad); 536 format->format = *mf; 537 return 0; 538 #else 539 return -ENOTTY; 540 #endif 541 } 542 543 mf->width = mt9m111->width; 544 mf->height = mt9m111->height; 545 mf->code = mt9m111->fmt->code; 546 mf->colorspace = mt9m111->fmt->colorspace; 547 mf->field = V4L2_FIELD_NONE; 548 mf->ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT; 549 mf->quantization = V4L2_QUANTIZATION_DEFAULT; 550 mf->xfer_func = V4L2_XFER_FUNC_DEFAULT; 551 552 return 0; 553 } 554 555 static int mt9m111_set_pixfmt(struct mt9m111 *mt9m111, 556 u32 code) 557 { 558 struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev); 559 u16 data_outfmt2, mask_outfmt2 = MT9M111_OUTFMT_PROCESSED_BAYER | 560 MT9M111_OUTFMT_BYPASS_IFP | MT9M111_OUTFMT_RGB | 561 MT9M111_OUTFMT_RGB565 | MT9M111_OUTFMT_RGB555 | 562 MT9M111_OUTFMT_RGB444x | MT9M111_OUTFMT_RGBx444 | 563 MT9M111_OUTFMT_SWAP_YCbCr_C_Y_RGB_EVEN | 564 MT9M111_OUTFMT_SWAP_YCbCr_Cb_Cr_RGB_R_B; 565 int ret; 566 567 switch (code) { 568 case MEDIA_BUS_FMT_SBGGR8_1X8: 569 data_outfmt2 = MT9M111_OUTFMT_PROCESSED_BAYER | 570 MT9M111_OUTFMT_RGB; 571 break; 572 case MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_LE: 573 data_outfmt2 = MT9M111_OUTFMT_BYPASS_IFP | MT9M111_OUTFMT_RGB; 574 break; 575 case MEDIA_BUS_FMT_RGB555_2X8_PADHI_LE: 576 data_outfmt2 = MT9M111_OUTFMT_RGB | MT9M111_OUTFMT_RGB555 | 577 MT9M111_OUTFMT_SWAP_YCbCr_C_Y_RGB_EVEN; 578 break; 579 case MEDIA_BUS_FMT_RGB555_2X8_PADHI_BE: 580 data_outfmt2 = MT9M111_OUTFMT_RGB | MT9M111_OUTFMT_RGB555; 581 break; 582 case MEDIA_BUS_FMT_RGB565_2X8_LE: 583 data_outfmt2 = MT9M111_OUTFMT_RGB | MT9M111_OUTFMT_RGB565 | 584 MT9M111_OUTFMT_SWAP_YCbCr_C_Y_RGB_EVEN; 585 break; 586 case MEDIA_BUS_FMT_RGB565_2X8_BE: 587 data_outfmt2 = MT9M111_OUTFMT_RGB | MT9M111_OUTFMT_RGB565; 588 break; 589 case MEDIA_BUS_FMT_BGR565_2X8_BE: 590 data_outfmt2 = MT9M111_OUTFMT_RGB | MT9M111_OUTFMT_RGB565 | 591 MT9M111_OUTFMT_SWAP_YCbCr_Cb_Cr_RGB_R_B; 592 break; 593 case MEDIA_BUS_FMT_BGR565_2X8_LE: 594 data_outfmt2 = MT9M111_OUTFMT_RGB | MT9M111_OUTFMT_RGB565 | 595 MT9M111_OUTFMT_SWAP_YCbCr_C_Y_RGB_EVEN | 596 MT9M111_OUTFMT_SWAP_YCbCr_Cb_Cr_RGB_R_B; 597 break; 598 case MEDIA_BUS_FMT_UYVY8_2X8: 599 data_outfmt2 = 0; 600 break; 601 case MEDIA_BUS_FMT_VYUY8_2X8: 602 data_outfmt2 = MT9M111_OUTFMT_SWAP_YCbCr_Cb_Cr_RGB_R_B; 603 break; 604 case MEDIA_BUS_FMT_YUYV8_2X8: 605 data_outfmt2 = MT9M111_OUTFMT_SWAP_YCbCr_C_Y_RGB_EVEN; 606 break; 607 case MEDIA_BUS_FMT_YVYU8_2X8: 608 data_outfmt2 = MT9M111_OUTFMT_SWAP_YCbCr_C_Y_RGB_EVEN | 609 MT9M111_OUTFMT_SWAP_YCbCr_Cb_Cr_RGB_R_B; 610 break; 611 default: 612 dev_err(&client->dev, "Pixel format not handled: %x\n", code); 613 return -EINVAL; 614 } 615 616 /* receiver samples on falling edge, chip-hw default is rising */ 617 if (mt9m111->pclk_sample == 0) 618 mask_outfmt2 |= MT9M111_OUTFMT_INV_PIX_CLOCK; 619 620 ret = mt9m111_reg_mask(client, context_a.output_fmt_ctrl2, 621 data_outfmt2, mask_outfmt2); 622 if (!ret) 623 ret = mt9m111_reg_mask(client, context_b.output_fmt_ctrl2, 624 data_outfmt2, mask_outfmt2); 625 626 return ret; 627 } 628 629 static int mt9m111_set_fmt(struct v4l2_subdev *sd, 630 struct v4l2_subdev_pad_config *cfg, 631 struct v4l2_subdev_format *format) 632 { 633 struct v4l2_mbus_framefmt *mf = &format->format; 634 struct i2c_client *client = v4l2_get_subdevdata(sd); 635 struct mt9m111 *mt9m111 = container_of(sd, struct mt9m111, subdev); 636 const struct mt9m111_datafmt *fmt; 637 struct v4l2_rect *rect = &mt9m111->rect; 638 bool bayer; 639 int ret; 640 641 if (mt9m111->is_streaming) 642 return -EBUSY; 643 644 if (format->pad) 645 return -EINVAL; 646 647 fmt = mt9m111_find_datafmt(mt9m111, mf->code); 648 649 bayer = fmt->code == MEDIA_BUS_FMT_SBGGR8_1X8 || 650 fmt->code == MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_LE; 651 652 /* 653 * With Bayer format enforce even side lengths, but let the user play 654 * with the starting pixel 655 */ 656 if (bayer) { 657 rect->width = ALIGN(rect->width, 2); 658 rect->height = ALIGN(rect->height, 2); 659 } 660 661 if (fmt->code == MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_LE) { 662 /* IFP bypass mode, no scaling */ 663 mf->width = rect->width; 664 mf->height = rect->height; 665 } else { 666 /* No upscaling */ 667 if (mf->width > rect->width) 668 mf->width = rect->width; 669 if (mf->height > rect->height) 670 mf->height = rect->height; 671 } 672 673 dev_dbg(&client->dev, "%s(): %ux%u, code=%x\n", __func__, 674 mf->width, mf->height, fmt->code); 675 676 mf->code = fmt->code; 677 mf->colorspace = fmt->colorspace; 678 mf->field = V4L2_FIELD_NONE; 679 mf->ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT; 680 mf->quantization = V4L2_QUANTIZATION_DEFAULT; 681 mf->xfer_func = V4L2_XFER_FUNC_DEFAULT; 682 683 if (format->which == V4L2_SUBDEV_FORMAT_TRY) { 684 cfg->try_fmt = *mf; 685 return 0; 686 } 687 688 ret = mt9m111_setup_geometry(mt9m111, rect, mf->width, mf->height, mf->code); 689 if (!ret) 690 ret = mt9m111_set_pixfmt(mt9m111, mf->code); 691 if (!ret) { 692 mt9m111->width = mf->width; 693 mt9m111->height = mf->height; 694 mt9m111->fmt = fmt; 695 } 696 697 return ret; 698 } 699 700 static const struct mt9m111_mode_info * 701 mt9m111_find_mode(struct mt9m111 *mt9m111, unsigned int req_fps, 702 unsigned int width, unsigned int height) 703 { 704 const struct mt9m111_mode_info *mode; 705 struct v4l2_rect *sensor_rect = &mt9m111->rect; 706 unsigned int gap, gap_best = (unsigned int) -1; 707 int i, best_gap_idx = MT9M111_MODE_SXGA_15FPS; 708 bool skip_30fps = false; 709 710 /* 711 * The fps selection is based on the row, column skipping mechanism. 712 * So ensure that the sensor window is set to default else the fps 713 * aren't calculated correctly within the sensor hw. 714 */ 715 if (sensor_rect->width != MT9M111_MAX_WIDTH || 716 sensor_rect->height != MT9M111_MAX_HEIGHT) { 717 dev_info(mt9m111->subdev.dev, 718 "Framerate selection is not supported for cropped " 719 "images\n"); 720 return NULL; 721 } 722 723 /* 30fps only supported for images not exceeding 640x512 */ 724 if (width > MT9M111_MAX_WIDTH / 2 || height > MT9M111_MAX_HEIGHT / 2) { 725 dev_dbg(mt9m111->subdev.dev, 726 "Framerates > 15fps are supported only for images " 727 "not exceeding 640x512\n"); 728 skip_30fps = true; 729 } 730 731 /* find best matched fps */ 732 for (i = 0; i < MT9M111_NUM_MODES; i++) { 733 unsigned int fps = mt9m111_mode_data[i].max_fps; 734 735 if (fps == 30 && skip_30fps) 736 continue; 737 738 gap = abs(fps - req_fps); 739 if (gap < gap_best) { 740 best_gap_idx = i; 741 gap_best = gap; 742 } 743 } 744 745 /* 746 * Use context a/b default timing values instead of calculate blanking 747 * timing values. 748 */ 749 mode = &mt9m111_mode_data[best_gap_idx]; 750 mt9m111->ctx = (best_gap_idx == MT9M111_MODE_QSXGA_30FPS) ? &context_a : 751 &context_b; 752 return mode; 753 } 754 755 #ifdef CONFIG_VIDEO_ADV_DEBUG 756 static int mt9m111_g_register(struct v4l2_subdev *sd, 757 struct v4l2_dbg_register *reg) 758 { 759 struct i2c_client *client = v4l2_get_subdevdata(sd); 760 int val; 761 762 if (reg->reg > 0x2ff) 763 return -EINVAL; 764 765 val = mt9m111_reg_read(client, reg->reg); 766 reg->size = 2; 767 reg->val = (u64)val; 768 769 if (reg->val > 0xffff) 770 return -EIO; 771 772 return 0; 773 } 774 775 static int mt9m111_s_register(struct v4l2_subdev *sd, 776 const struct v4l2_dbg_register *reg) 777 { 778 struct i2c_client *client = v4l2_get_subdevdata(sd); 779 780 if (reg->reg > 0x2ff) 781 return -EINVAL; 782 783 if (mt9m111_reg_write(client, reg->reg, reg->val) < 0) 784 return -EIO; 785 786 return 0; 787 } 788 #endif 789 790 static int mt9m111_set_flip(struct mt9m111 *mt9m111, int flip, int mask) 791 { 792 struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev); 793 int ret; 794 795 if (flip) 796 ret = mt9m111_reg_set(client, mt9m111->ctx->read_mode, mask); 797 else 798 ret = mt9m111_reg_clear(client, mt9m111->ctx->read_mode, mask); 799 800 return ret; 801 } 802 803 static int mt9m111_get_global_gain(struct mt9m111 *mt9m111) 804 { 805 struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev); 806 int data; 807 808 data = reg_read(GLOBAL_GAIN); 809 if (data >= 0) 810 return (data & 0x2f) * (1 << ((data >> 10) & 1)) * 811 (1 << ((data >> 9) & 1)); 812 return data; 813 } 814 815 static int mt9m111_set_global_gain(struct mt9m111 *mt9m111, int gain) 816 { 817 struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev); 818 u16 val; 819 820 if (gain > 63 * 2 * 2) 821 return -EINVAL; 822 823 if ((gain >= 64 * 2) && (gain < 63 * 2 * 2)) 824 val = (1 << 10) | (1 << 9) | (gain / 4); 825 else if ((gain >= 64) && (gain < 64 * 2)) 826 val = (1 << 9) | (gain / 2); 827 else 828 val = gain; 829 830 return reg_write(GLOBAL_GAIN, val); 831 } 832 833 static int mt9m111_set_autoexposure(struct mt9m111 *mt9m111, int val) 834 { 835 struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev); 836 837 if (val == V4L2_EXPOSURE_AUTO) 838 return reg_set(OPER_MODE_CTRL, MT9M111_OPMODE_AUTOEXPO_EN); 839 return reg_clear(OPER_MODE_CTRL, MT9M111_OPMODE_AUTOEXPO_EN); 840 } 841 842 static int mt9m111_set_autowhitebalance(struct mt9m111 *mt9m111, int on) 843 { 844 struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev); 845 846 if (on) 847 return reg_set(OPER_MODE_CTRL, MT9M111_OPMODE_AUTOWHITEBAL_EN); 848 return reg_clear(OPER_MODE_CTRL, MT9M111_OPMODE_AUTOWHITEBAL_EN); 849 } 850 851 static const char * const mt9m111_test_pattern_menu[] = { 852 "Disabled", 853 "Vertical monochrome gradient", 854 "Flat color type 1", 855 "Flat color type 2", 856 "Flat color type 3", 857 "Flat color type 4", 858 "Flat color type 5", 859 "Color bar", 860 }; 861 862 static int mt9m111_set_test_pattern(struct mt9m111 *mt9m111, int val) 863 { 864 struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev); 865 866 return mt9m111_reg_mask(client, MT9M111_TPG_CTRL, val, 867 MT9M111_TPG_SEL_MASK); 868 } 869 870 static int mt9m111_set_colorfx(struct mt9m111 *mt9m111, int val) 871 { 872 struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev); 873 static const struct v4l2_control colorfx[] = { 874 { V4L2_COLORFX_NONE, 0 }, 875 { V4L2_COLORFX_BW, 1 }, 876 { V4L2_COLORFX_SEPIA, 2 }, 877 { V4L2_COLORFX_NEGATIVE, 3 }, 878 { V4L2_COLORFX_SOLARIZATION, 4 }, 879 }; 880 int i; 881 882 for (i = 0; i < ARRAY_SIZE(colorfx); i++) { 883 if (colorfx[i].id == val) { 884 return mt9m111_reg_mask(client, MT9M111_EFFECTS_MODE, 885 colorfx[i].value, 886 MT9M111_EFFECTS_MODE_MASK); 887 } 888 } 889 890 return -EINVAL; 891 } 892 893 static int mt9m111_s_ctrl(struct v4l2_ctrl *ctrl) 894 { 895 struct mt9m111 *mt9m111 = container_of(ctrl->handler, 896 struct mt9m111, hdl); 897 898 switch (ctrl->id) { 899 case V4L2_CID_VFLIP: 900 return mt9m111_set_flip(mt9m111, ctrl->val, 901 MT9M111_RMB_MIRROR_ROWS); 902 case V4L2_CID_HFLIP: 903 return mt9m111_set_flip(mt9m111, ctrl->val, 904 MT9M111_RMB_MIRROR_COLS); 905 case V4L2_CID_GAIN: 906 return mt9m111_set_global_gain(mt9m111, ctrl->val); 907 case V4L2_CID_EXPOSURE_AUTO: 908 return mt9m111_set_autoexposure(mt9m111, ctrl->val); 909 case V4L2_CID_AUTO_WHITE_BALANCE: 910 return mt9m111_set_autowhitebalance(mt9m111, ctrl->val); 911 case V4L2_CID_TEST_PATTERN: 912 return mt9m111_set_test_pattern(mt9m111, ctrl->val); 913 case V4L2_CID_COLORFX: 914 return mt9m111_set_colorfx(mt9m111, ctrl->val); 915 } 916 917 return -EINVAL; 918 } 919 920 static int mt9m111_suspend(struct mt9m111 *mt9m111) 921 { 922 struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev); 923 int ret; 924 925 v4l2_ctrl_s_ctrl(mt9m111->gain, mt9m111_get_global_gain(mt9m111)); 926 927 ret = reg_set(RESET, MT9M111_RESET_RESET_MODE); 928 if (!ret) 929 ret = reg_set(RESET, MT9M111_RESET_RESET_SOC | 930 MT9M111_RESET_OUTPUT_DISABLE | 931 MT9M111_RESET_ANALOG_STANDBY); 932 if (!ret) 933 ret = reg_clear(RESET, MT9M111_RESET_CHIP_ENABLE); 934 935 return ret; 936 } 937 938 static void mt9m111_restore_state(struct mt9m111 *mt9m111) 939 { 940 struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev); 941 942 mt9m111_set_context(mt9m111, mt9m111->ctx); 943 mt9m111_set_pixfmt(mt9m111, mt9m111->fmt->code); 944 mt9m111_setup_geometry(mt9m111, &mt9m111->rect, 945 mt9m111->width, mt9m111->height, mt9m111->fmt->code); 946 v4l2_ctrl_handler_setup(&mt9m111->hdl); 947 mt9m111_reg_mask(client, mt9m111->ctx->read_mode, 948 mt9m111->current_mode->reg_val, 949 mt9m111->current_mode->reg_mask); 950 } 951 952 static int mt9m111_resume(struct mt9m111 *mt9m111) 953 { 954 int ret = mt9m111_enable(mt9m111); 955 if (!ret) 956 ret = mt9m111_reset(mt9m111); 957 if (!ret) 958 mt9m111_restore_state(mt9m111); 959 960 return ret; 961 } 962 963 static int mt9m111_init(struct mt9m111 *mt9m111) 964 { 965 struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev); 966 int ret; 967 968 ret = mt9m111_enable(mt9m111); 969 if (!ret) 970 ret = mt9m111_reset(mt9m111); 971 if (!ret) 972 ret = mt9m111_set_context(mt9m111, mt9m111->ctx); 973 if (ret) 974 dev_err(&client->dev, "mt9m111 init failed: %d\n", ret); 975 return ret; 976 } 977 978 static int mt9m111_power_on(struct mt9m111 *mt9m111) 979 { 980 struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev); 981 int ret; 982 983 ret = v4l2_clk_enable(mt9m111->clk); 984 if (ret < 0) 985 return ret; 986 987 ret = regulator_enable(mt9m111->regulator); 988 if (ret < 0) 989 goto out_clk_disable; 990 991 ret = mt9m111_resume(mt9m111); 992 if (ret < 0) 993 goto out_regulator_disable; 994 995 return 0; 996 997 out_regulator_disable: 998 regulator_disable(mt9m111->regulator); 999 1000 out_clk_disable: 1001 v4l2_clk_disable(mt9m111->clk); 1002 1003 dev_err(&client->dev, "Failed to resume the sensor: %d\n", ret); 1004 1005 return ret; 1006 } 1007 1008 static void mt9m111_power_off(struct mt9m111 *mt9m111) 1009 { 1010 mt9m111_suspend(mt9m111); 1011 regulator_disable(mt9m111->regulator); 1012 v4l2_clk_disable(mt9m111->clk); 1013 } 1014 1015 static int mt9m111_s_power(struct v4l2_subdev *sd, int on) 1016 { 1017 struct mt9m111 *mt9m111 = container_of(sd, struct mt9m111, subdev); 1018 int ret = 0; 1019 1020 mutex_lock(&mt9m111->power_lock); 1021 1022 /* 1023 * If the power count is modified from 0 to != 0 or from != 0 to 0, 1024 * update the power state. 1025 */ 1026 if (mt9m111->power_count == !on) { 1027 if (on) 1028 ret = mt9m111_power_on(mt9m111); 1029 else 1030 mt9m111_power_off(mt9m111); 1031 } 1032 1033 if (!ret) { 1034 /* Update the power count. */ 1035 mt9m111->power_count += on ? 1 : -1; 1036 WARN_ON(mt9m111->power_count < 0); 1037 } 1038 1039 mutex_unlock(&mt9m111->power_lock); 1040 return ret; 1041 } 1042 1043 static const struct v4l2_ctrl_ops mt9m111_ctrl_ops = { 1044 .s_ctrl = mt9m111_s_ctrl, 1045 }; 1046 1047 static const struct v4l2_subdev_core_ops mt9m111_subdev_core_ops = { 1048 .s_power = mt9m111_s_power, 1049 .log_status = v4l2_ctrl_subdev_log_status, 1050 .subscribe_event = v4l2_ctrl_subdev_subscribe_event, 1051 .unsubscribe_event = v4l2_event_subdev_unsubscribe, 1052 #ifdef CONFIG_VIDEO_ADV_DEBUG 1053 .g_register = mt9m111_g_register, 1054 .s_register = mt9m111_s_register, 1055 #endif 1056 }; 1057 1058 static int mt9m111_g_frame_interval(struct v4l2_subdev *sd, 1059 struct v4l2_subdev_frame_interval *fi) 1060 { 1061 struct mt9m111 *mt9m111 = container_of(sd, struct mt9m111, subdev); 1062 1063 fi->interval = mt9m111->frame_interval; 1064 1065 return 0; 1066 } 1067 1068 static int mt9m111_s_frame_interval(struct v4l2_subdev *sd, 1069 struct v4l2_subdev_frame_interval *fi) 1070 { 1071 struct mt9m111 *mt9m111 = container_of(sd, struct mt9m111, subdev); 1072 const struct mt9m111_mode_info *mode; 1073 struct v4l2_fract *fract = &fi->interval; 1074 int fps; 1075 1076 if (mt9m111->is_streaming) 1077 return -EBUSY; 1078 1079 if (fi->pad != 0) 1080 return -EINVAL; 1081 1082 if (fract->numerator == 0) { 1083 fract->denominator = 30; 1084 fract->numerator = 1; 1085 } 1086 1087 fps = DIV_ROUND_CLOSEST(fract->denominator, fract->numerator); 1088 1089 /* Find best fitting mode. Do not update the mode if no one was found. */ 1090 mode = mt9m111_find_mode(mt9m111, fps, mt9m111->width, mt9m111->height); 1091 if (!mode) 1092 return 0; 1093 1094 if (mode->max_fps != fps) { 1095 fract->denominator = mode->max_fps; 1096 fract->numerator = 1; 1097 } 1098 1099 mt9m111->current_mode = mode; 1100 mt9m111->frame_interval = fi->interval; 1101 1102 return 0; 1103 } 1104 1105 static int mt9m111_enum_mbus_code(struct v4l2_subdev *sd, 1106 struct v4l2_subdev_pad_config *cfg, 1107 struct v4l2_subdev_mbus_code_enum *code) 1108 { 1109 if (code->pad || code->index >= ARRAY_SIZE(mt9m111_colour_fmts)) 1110 return -EINVAL; 1111 1112 code->code = mt9m111_colour_fmts[code->index].code; 1113 return 0; 1114 } 1115 1116 static int mt9m111_s_stream(struct v4l2_subdev *sd, int enable) 1117 { 1118 struct mt9m111 *mt9m111 = container_of(sd, struct mt9m111, subdev); 1119 1120 mt9m111->is_streaming = !!enable; 1121 return 0; 1122 } 1123 1124 static int mt9m111_init_cfg(struct v4l2_subdev *sd, 1125 struct v4l2_subdev_pad_config *cfg) 1126 { 1127 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API 1128 struct v4l2_mbus_framefmt *format = 1129 v4l2_subdev_get_try_format(sd, cfg, 0); 1130 1131 format->width = MT9M111_MAX_WIDTH; 1132 format->height = MT9M111_MAX_HEIGHT; 1133 format->code = mt9m111_colour_fmts[0].code; 1134 format->colorspace = mt9m111_colour_fmts[0].colorspace; 1135 format->field = V4L2_FIELD_NONE; 1136 format->ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT; 1137 format->quantization = V4L2_QUANTIZATION_DEFAULT; 1138 format->xfer_func = V4L2_XFER_FUNC_DEFAULT; 1139 #endif 1140 return 0; 1141 } 1142 1143 static int mt9m111_g_mbus_config(struct v4l2_subdev *sd, 1144 struct v4l2_mbus_config *cfg) 1145 { 1146 struct mt9m111 *mt9m111 = container_of(sd, struct mt9m111, subdev); 1147 1148 cfg->flags = V4L2_MBUS_MASTER | 1149 V4L2_MBUS_HSYNC_ACTIVE_HIGH | V4L2_MBUS_VSYNC_ACTIVE_HIGH | 1150 V4L2_MBUS_DATA_ACTIVE_HIGH; 1151 1152 cfg->flags |= mt9m111->pclk_sample ? V4L2_MBUS_PCLK_SAMPLE_RISING : 1153 V4L2_MBUS_PCLK_SAMPLE_FALLING; 1154 1155 cfg->type = V4L2_MBUS_PARALLEL; 1156 1157 return 0; 1158 } 1159 1160 static const struct v4l2_subdev_video_ops mt9m111_subdev_video_ops = { 1161 .g_mbus_config = mt9m111_g_mbus_config, 1162 .s_stream = mt9m111_s_stream, 1163 .g_frame_interval = mt9m111_g_frame_interval, 1164 .s_frame_interval = mt9m111_s_frame_interval, 1165 }; 1166 1167 static const struct v4l2_subdev_pad_ops mt9m111_subdev_pad_ops = { 1168 .init_cfg = mt9m111_init_cfg, 1169 .enum_mbus_code = mt9m111_enum_mbus_code, 1170 .get_selection = mt9m111_get_selection, 1171 .set_selection = mt9m111_set_selection, 1172 .get_fmt = mt9m111_get_fmt, 1173 .set_fmt = mt9m111_set_fmt, 1174 }; 1175 1176 static const struct v4l2_subdev_ops mt9m111_subdev_ops = { 1177 .core = &mt9m111_subdev_core_ops, 1178 .video = &mt9m111_subdev_video_ops, 1179 .pad = &mt9m111_subdev_pad_ops, 1180 }; 1181 1182 /* 1183 * Interface active, can use i2c. If it fails, it can indeed mean, that 1184 * this wasn't our capture interface, so, we wait for the right one 1185 */ 1186 static int mt9m111_video_probe(struct i2c_client *client) 1187 { 1188 struct mt9m111 *mt9m111 = to_mt9m111(client); 1189 s32 data; 1190 int ret; 1191 1192 ret = mt9m111_s_power(&mt9m111->subdev, 1); 1193 if (ret < 0) 1194 return ret; 1195 1196 data = reg_read(CHIP_VERSION); 1197 1198 switch (data) { 1199 case 0x143a: /* MT9M111 or MT9M131 */ 1200 dev_info(&client->dev, 1201 "Detected a MT9M111/MT9M131 chip ID %x\n", data); 1202 break; 1203 case 0x148c: /* MT9M112 */ 1204 dev_info(&client->dev, "Detected a MT9M112 chip ID %x\n", data); 1205 break; 1206 default: 1207 dev_err(&client->dev, 1208 "No MT9M111/MT9M112/MT9M131 chip detected register read %x\n", 1209 data); 1210 ret = -ENODEV; 1211 goto done; 1212 } 1213 1214 ret = mt9m111_init(mt9m111); 1215 if (ret) 1216 goto done; 1217 1218 ret = v4l2_ctrl_handler_setup(&mt9m111->hdl); 1219 1220 done: 1221 mt9m111_s_power(&mt9m111->subdev, 0); 1222 return ret; 1223 } 1224 1225 static int mt9m111_probe_fw(struct i2c_client *client, struct mt9m111 *mt9m111) 1226 { 1227 struct v4l2_fwnode_endpoint bus_cfg = { 1228 .bus_type = V4L2_MBUS_PARALLEL 1229 }; 1230 struct fwnode_handle *np; 1231 int ret; 1232 1233 np = fwnode_graph_get_next_endpoint(dev_fwnode(&client->dev), NULL); 1234 if (!np) 1235 return -EINVAL; 1236 1237 ret = v4l2_fwnode_endpoint_parse(np, &bus_cfg); 1238 if (ret) 1239 goto out_put_fw; 1240 1241 mt9m111->pclk_sample = !!(bus_cfg.bus.parallel.flags & 1242 V4L2_MBUS_PCLK_SAMPLE_RISING); 1243 1244 out_put_fw: 1245 fwnode_handle_put(np); 1246 return ret; 1247 } 1248 1249 static int mt9m111_probe(struct i2c_client *client, 1250 const struct i2c_device_id *did) 1251 { 1252 struct mt9m111 *mt9m111; 1253 struct i2c_adapter *adapter = client->adapter; 1254 int ret; 1255 1256 if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_WORD_DATA)) { 1257 dev_warn(&adapter->dev, 1258 "I2C-Adapter doesn't support I2C_FUNC_SMBUS_WORD\n"); 1259 return -EIO; 1260 } 1261 1262 mt9m111 = devm_kzalloc(&client->dev, sizeof(struct mt9m111), GFP_KERNEL); 1263 if (!mt9m111) 1264 return -ENOMEM; 1265 1266 if (dev_fwnode(&client->dev)) { 1267 ret = mt9m111_probe_fw(client, mt9m111); 1268 if (ret) 1269 return ret; 1270 } 1271 1272 mt9m111->clk = v4l2_clk_get(&client->dev, "mclk"); 1273 if (IS_ERR(mt9m111->clk)) 1274 return PTR_ERR(mt9m111->clk); 1275 1276 mt9m111->regulator = devm_regulator_get(&client->dev, "vdd"); 1277 if (IS_ERR(mt9m111->regulator)) { 1278 dev_err(&client->dev, "regulator not found: %ld\n", 1279 PTR_ERR(mt9m111->regulator)); 1280 return PTR_ERR(mt9m111->regulator); 1281 } 1282 1283 /* Default HIGHPOWER context */ 1284 mt9m111->ctx = &context_b; 1285 1286 v4l2_i2c_subdev_init(&mt9m111->subdev, client, &mt9m111_subdev_ops); 1287 mt9m111->subdev.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | 1288 V4L2_SUBDEV_FL_HAS_EVENTS; 1289 1290 v4l2_ctrl_handler_init(&mt9m111->hdl, 7); 1291 v4l2_ctrl_new_std(&mt9m111->hdl, &mt9m111_ctrl_ops, 1292 V4L2_CID_VFLIP, 0, 1, 1, 0); 1293 v4l2_ctrl_new_std(&mt9m111->hdl, &mt9m111_ctrl_ops, 1294 V4L2_CID_HFLIP, 0, 1, 1, 0); 1295 v4l2_ctrl_new_std(&mt9m111->hdl, &mt9m111_ctrl_ops, 1296 V4L2_CID_AUTO_WHITE_BALANCE, 0, 1, 1, 1); 1297 mt9m111->gain = v4l2_ctrl_new_std(&mt9m111->hdl, &mt9m111_ctrl_ops, 1298 V4L2_CID_GAIN, 0, 63 * 2 * 2, 1, 32); 1299 v4l2_ctrl_new_std_menu(&mt9m111->hdl, 1300 &mt9m111_ctrl_ops, V4L2_CID_EXPOSURE_AUTO, 1, 0, 1301 V4L2_EXPOSURE_AUTO); 1302 v4l2_ctrl_new_std_menu_items(&mt9m111->hdl, 1303 &mt9m111_ctrl_ops, V4L2_CID_TEST_PATTERN, 1304 ARRAY_SIZE(mt9m111_test_pattern_menu) - 1, 0, 0, 1305 mt9m111_test_pattern_menu); 1306 v4l2_ctrl_new_std_menu(&mt9m111->hdl, &mt9m111_ctrl_ops, 1307 V4L2_CID_COLORFX, V4L2_COLORFX_SOLARIZATION, 1308 ~(BIT(V4L2_COLORFX_NONE) | 1309 BIT(V4L2_COLORFX_BW) | 1310 BIT(V4L2_COLORFX_SEPIA) | 1311 BIT(V4L2_COLORFX_NEGATIVE) | 1312 BIT(V4L2_COLORFX_SOLARIZATION)), 1313 V4L2_COLORFX_NONE); 1314 mt9m111->subdev.ctrl_handler = &mt9m111->hdl; 1315 if (mt9m111->hdl.error) { 1316 ret = mt9m111->hdl.error; 1317 goto out_clkput; 1318 } 1319 1320 #ifdef CONFIG_MEDIA_CONTROLLER 1321 mt9m111->pad.flags = MEDIA_PAD_FL_SOURCE; 1322 mt9m111->subdev.entity.function = MEDIA_ENT_F_CAM_SENSOR; 1323 ret = media_entity_pads_init(&mt9m111->subdev.entity, 1, &mt9m111->pad); 1324 if (ret < 0) 1325 goto out_hdlfree; 1326 #endif 1327 1328 mt9m111->current_mode = &mt9m111_mode_data[MT9M111_MODE_SXGA_15FPS]; 1329 mt9m111->frame_interval.numerator = 1; 1330 mt9m111->frame_interval.denominator = mt9m111->current_mode->max_fps; 1331 1332 /* Second stage probe - when a capture adapter is there */ 1333 mt9m111->rect.left = MT9M111_MIN_DARK_COLS; 1334 mt9m111->rect.top = MT9M111_MIN_DARK_ROWS; 1335 mt9m111->rect.width = MT9M111_MAX_WIDTH; 1336 mt9m111->rect.height = MT9M111_MAX_HEIGHT; 1337 mt9m111->width = mt9m111->rect.width; 1338 mt9m111->height = mt9m111->rect.height; 1339 mt9m111->fmt = &mt9m111_colour_fmts[0]; 1340 mt9m111->lastpage = -1; 1341 mutex_init(&mt9m111->power_lock); 1342 1343 ret = mt9m111_video_probe(client); 1344 if (ret < 0) 1345 goto out_entityclean; 1346 1347 mt9m111->subdev.dev = &client->dev; 1348 ret = v4l2_async_register_subdev(&mt9m111->subdev); 1349 if (ret < 0) 1350 goto out_entityclean; 1351 1352 return 0; 1353 1354 out_entityclean: 1355 #ifdef CONFIG_MEDIA_CONTROLLER 1356 media_entity_cleanup(&mt9m111->subdev.entity); 1357 out_hdlfree: 1358 #endif 1359 v4l2_ctrl_handler_free(&mt9m111->hdl); 1360 out_clkput: 1361 v4l2_clk_put(mt9m111->clk); 1362 1363 return ret; 1364 } 1365 1366 static int mt9m111_remove(struct i2c_client *client) 1367 { 1368 struct mt9m111 *mt9m111 = to_mt9m111(client); 1369 1370 v4l2_async_unregister_subdev(&mt9m111->subdev); 1371 media_entity_cleanup(&mt9m111->subdev.entity); 1372 v4l2_clk_put(mt9m111->clk); 1373 v4l2_ctrl_handler_free(&mt9m111->hdl); 1374 1375 return 0; 1376 } 1377 static const struct of_device_id mt9m111_of_match[] = { 1378 { .compatible = "micron,mt9m111", }, 1379 {}, 1380 }; 1381 MODULE_DEVICE_TABLE(of, mt9m111_of_match); 1382 1383 static const struct i2c_device_id mt9m111_id[] = { 1384 { "mt9m111", 0 }, 1385 { } 1386 }; 1387 MODULE_DEVICE_TABLE(i2c, mt9m111_id); 1388 1389 static struct i2c_driver mt9m111_i2c_driver = { 1390 .driver = { 1391 .name = "mt9m111", 1392 .of_match_table = of_match_ptr(mt9m111_of_match), 1393 }, 1394 .probe = mt9m111_probe, 1395 .remove = mt9m111_remove, 1396 .id_table = mt9m111_id, 1397 }; 1398 1399 module_i2c_driver(mt9m111_i2c_driver); 1400 1401 MODULE_DESCRIPTION("Micron/Aptina MT9M111/MT9M112/MT9M131 Camera driver"); 1402 MODULE_AUTHOR("Robert Jarzmik"); 1403 MODULE_LICENSE("GPL"); 1404