1 /* 2 * OKI Semiconductor ML86V7667 video decoder driver 3 * 4 * Author: Vladimir Barinov <source@cogentembedded.com> 5 * Copyright (C) 2013 Cogent Embedded, Inc. 6 * Copyright (C) 2013 Renesas Solutions Corp. 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms of the GNU General Public License as published by the 10 * Free Software Foundation; either version 2 of the License, or (at your 11 * option) any later version. 12 */ 13 14 #include <linux/init.h> 15 #include <linux/module.h> 16 #include <linux/i2c.h> 17 #include <linux/slab.h> 18 #include <linux/videodev2.h> 19 #include <media/v4l2-subdev.h> 20 #include <media/v4l2-device.h> 21 #include <media/v4l2-ioctl.h> 22 #include <media/v4l2-ctrls.h> 23 24 #define DRV_NAME "ml86v7667" 25 26 /* Subaddresses */ 27 #define MRA_REG 0x00 /* Mode Register A */ 28 #define MRC_REG 0x02 /* Mode Register C */ 29 #define LUMC_REG 0x0C /* Luminance Control */ 30 #define CLC_REG 0x10 /* Contrast level control */ 31 #define SSEPL_REG 0x11 /* Sync separation level */ 32 #define CHRCA_REG 0x12 /* Chrominance Control A */ 33 #define ACCC_REG 0x14 /* ACC Loop filter & Chrominance control */ 34 #define ACCRC_REG 0x15 /* ACC Reference level control */ 35 #define HUE_REG 0x16 /* Hue control */ 36 #define ADC2_REG 0x1F /* ADC Register 2 */ 37 #define PLLR1_REG 0x20 /* PLL Register 1 */ 38 #define STATUS_REG 0x2C /* STATUS Register */ 39 40 /* Mode Register A register bits */ 41 #define MRA_OUTPUT_MODE_MASK (3 << 6) 42 #define MRA_ITUR_BT601 (1 << 6) 43 #define MRA_ITUR_BT656 (0 << 6) 44 #define MRA_INPUT_MODE_MASK (7 << 3) 45 #define MRA_PAL_BT601 (4 << 3) 46 #define MRA_NTSC_BT601 (0 << 3) 47 #define MRA_REGISTER_MODE (1 << 0) 48 49 /* Mode Register C register bits */ 50 #define MRC_AUTOSELECT (1 << 7) 51 52 /* Luminance Control register bits */ 53 #define LUMC_ONOFF_SHIFT 7 54 #define LUMC_ONOFF_MASK (1 << 7) 55 56 /* Contrast level control register bits */ 57 #define CLC_CONTRAST_ONOFF (1 << 7) 58 #define CLC_CONTRAST_MASK 0x0F 59 60 /* Sync separation level register bits */ 61 #define SSEPL_LUMINANCE_ONOFF (1 << 7) 62 #define SSEPL_LUMINANCE_MASK 0x7F 63 64 /* Chrominance Control A register bits */ 65 #define CHRCA_MODE_SHIFT 6 66 #define CHRCA_MODE_MASK (1 << 6) 67 68 /* ACC Loop filter & Chrominance control register bits */ 69 #define ACCC_CHROMA_CR_SHIFT 3 70 #define ACCC_CHROMA_CR_MASK (7 << 3) 71 #define ACCC_CHROMA_CB_SHIFT 0 72 #define ACCC_CHROMA_CB_MASK (7 << 0) 73 74 /* ACC Reference level control register bits */ 75 #define ACCRC_CHROMA_MASK 0xfc 76 #define ACCRC_CHROMA_SHIFT 2 77 78 /* ADC Register 2 register bits */ 79 #define ADC2_CLAMP_VOLTAGE_MASK (7 << 1) 80 #define ADC2_CLAMP_VOLTAGE(n) ((n & 7) << 1) 81 82 /* PLL Register 1 register bits */ 83 #define PLLR1_FIXED_CLOCK (1 << 7) 84 85 /* STATUS Register register bits */ 86 #define STATUS_HLOCK_DETECT (1 << 3) 87 #define STATUS_NTSCPAL (1 << 2) 88 89 struct ml86v7667_priv { 90 struct v4l2_subdev sd; 91 struct v4l2_ctrl_handler hdl; 92 v4l2_std_id std; 93 }; 94 95 static inline struct ml86v7667_priv *to_ml86v7667(struct v4l2_subdev *subdev) 96 { 97 return container_of(subdev, struct ml86v7667_priv, sd); 98 } 99 100 static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl) 101 { 102 return &container_of(ctrl->handler, struct ml86v7667_priv, hdl)->sd; 103 } 104 105 static int ml86v7667_mask_set(struct i2c_client *client, const u8 reg, 106 const u8 mask, const u8 data) 107 { 108 int val = i2c_smbus_read_byte_data(client, reg); 109 if (val < 0) 110 return val; 111 112 val = (val & ~mask) | (data & mask); 113 return i2c_smbus_write_byte_data(client, reg, val); 114 } 115 116 static int ml86v7667_s_ctrl(struct v4l2_ctrl *ctrl) 117 { 118 struct v4l2_subdev *sd = to_sd(ctrl); 119 struct i2c_client *client = v4l2_get_subdevdata(sd); 120 int ret = -EINVAL; 121 122 switch (ctrl->id) { 123 case V4L2_CID_BRIGHTNESS: 124 ret = ml86v7667_mask_set(client, SSEPL_REG, 125 SSEPL_LUMINANCE_MASK, ctrl->val); 126 break; 127 case V4L2_CID_CONTRAST: 128 ret = ml86v7667_mask_set(client, CLC_REG, 129 CLC_CONTRAST_MASK, ctrl->val); 130 break; 131 case V4L2_CID_CHROMA_GAIN: 132 ret = ml86v7667_mask_set(client, ACCRC_REG, ACCRC_CHROMA_MASK, 133 ctrl->val << ACCRC_CHROMA_SHIFT); 134 break; 135 case V4L2_CID_HUE: 136 ret = ml86v7667_mask_set(client, HUE_REG, ~0, ctrl->val); 137 break; 138 case V4L2_CID_RED_BALANCE: 139 ret = ml86v7667_mask_set(client, ACCC_REG, 140 ACCC_CHROMA_CR_MASK, 141 ctrl->val << ACCC_CHROMA_CR_SHIFT); 142 break; 143 case V4L2_CID_BLUE_BALANCE: 144 ret = ml86v7667_mask_set(client, ACCC_REG, 145 ACCC_CHROMA_CB_MASK, 146 ctrl->val << ACCC_CHROMA_CB_SHIFT); 147 break; 148 case V4L2_CID_SHARPNESS: 149 ret = ml86v7667_mask_set(client, LUMC_REG, 150 LUMC_ONOFF_MASK, 151 ctrl->val << LUMC_ONOFF_SHIFT); 152 break; 153 case V4L2_CID_COLOR_KILLER: 154 ret = ml86v7667_mask_set(client, CHRCA_REG, 155 CHRCA_MODE_MASK, 156 ctrl->val << CHRCA_MODE_SHIFT); 157 break; 158 } 159 160 return ret; 161 } 162 163 static int ml86v7667_querystd(struct v4l2_subdev *sd, v4l2_std_id *std) 164 { 165 struct i2c_client *client = v4l2_get_subdevdata(sd); 166 int status; 167 168 status = i2c_smbus_read_byte_data(client, STATUS_REG); 169 if (status < 0) 170 return status; 171 172 if (status & STATUS_HLOCK_DETECT) 173 *std &= status & STATUS_NTSCPAL ? V4L2_STD_625_50 : V4L2_STD_525_60; 174 else 175 *std = V4L2_STD_UNKNOWN; 176 177 return 0; 178 } 179 180 static int ml86v7667_g_input_status(struct v4l2_subdev *sd, u32 *status) 181 { 182 struct i2c_client *client = v4l2_get_subdevdata(sd); 183 int status_reg; 184 185 status_reg = i2c_smbus_read_byte_data(client, STATUS_REG); 186 if (status_reg < 0) 187 return status_reg; 188 189 *status = status_reg & STATUS_HLOCK_DETECT ? 0 : V4L2_IN_ST_NO_SIGNAL; 190 191 return 0; 192 } 193 194 static int ml86v7667_enum_mbus_code(struct v4l2_subdev *sd, 195 struct v4l2_subdev_pad_config *cfg, 196 struct v4l2_subdev_mbus_code_enum *code) 197 { 198 if (code->pad || code->index > 0) 199 return -EINVAL; 200 201 code->code = MEDIA_BUS_FMT_YUYV8_2X8; 202 203 return 0; 204 } 205 206 static int ml86v7667_mbus_fmt(struct v4l2_subdev *sd, 207 struct v4l2_mbus_framefmt *fmt) 208 { 209 struct ml86v7667_priv *priv = to_ml86v7667(sd); 210 211 fmt->code = MEDIA_BUS_FMT_YUYV8_2X8; 212 fmt->colorspace = V4L2_COLORSPACE_SMPTE170M; 213 /* The top field is always transferred first by the chip */ 214 fmt->field = V4L2_FIELD_INTERLACED_TB; 215 fmt->width = 720; 216 fmt->height = priv->std & V4L2_STD_525_60 ? 480 : 576; 217 218 return 0; 219 } 220 221 static int ml86v7667_g_mbus_config(struct v4l2_subdev *sd, 222 struct v4l2_mbus_config *cfg) 223 { 224 cfg->flags = V4L2_MBUS_MASTER | V4L2_MBUS_PCLK_SAMPLE_RISING | 225 V4L2_MBUS_DATA_ACTIVE_HIGH; 226 cfg->type = V4L2_MBUS_BT656; 227 228 return 0; 229 } 230 231 static int ml86v7667_s_std(struct v4l2_subdev *sd, v4l2_std_id std) 232 { 233 struct ml86v7667_priv *priv = to_ml86v7667(sd); 234 struct i2c_client *client = v4l2_get_subdevdata(&priv->sd); 235 int ret; 236 u8 mode; 237 238 /* PAL/NTSC ITU-R BT.601 input mode */ 239 mode = std & V4L2_STD_525_60 ? MRA_NTSC_BT601 : MRA_PAL_BT601; 240 ret = ml86v7667_mask_set(client, MRA_REG, MRA_INPUT_MODE_MASK, mode); 241 if (ret < 0) 242 return ret; 243 244 priv->std = std; 245 246 return 0; 247 } 248 249 #ifdef CONFIG_VIDEO_ADV_DEBUG 250 static int ml86v7667_g_register(struct v4l2_subdev *sd, 251 struct v4l2_dbg_register *reg) 252 { 253 struct i2c_client *client = v4l2_get_subdevdata(sd); 254 int ret; 255 256 ret = i2c_smbus_read_byte_data(client, (u8)reg->reg); 257 if (ret < 0) 258 return ret; 259 260 reg->val = ret; 261 reg->size = sizeof(u8); 262 263 return 0; 264 } 265 266 static int ml86v7667_s_register(struct v4l2_subdev *sd, 267 const struct v4l2_dbg_register *reg) 268 { 269 struct i2c_client *client = v4l2_get_subdevdata(sd); 270 271 return i2c_smbus_write_byte_data(client, (u8)reg->reg, (u8)reg->val); 272 } 273 #endif 274 275 static const struct v4l2_ctrl_ops ml86v7667_ctrl_ops = { 276 .s_ctrl = ml86v7667_s_ctrl, 277 }; 278 279 static struct v4l2_subdev_video_ops ml86v7667_subdev_video_ops = { 280 .s_std = ml86v7667_s_std, 281 .querystd = ml86v7667_querystd, 282 .g_input_status = ml86v7667_g_input_status, 283 .try_mbus_fmt = ml86v7667_mbus_fmt, 284 .g_mbus_fmt = ml86v7667_mbus_fmt, 285 .s_mbus_fmt = ml86v7667_mbus_fmt, 286 .g_mbus_config = ml86v7667_g_mbus_config, 287 }; 288 289 static const struct v4l2_subdev_pad_ops ml86v7667_subdev_pad_ops = { 290 .enum_mbus_code = ml86v7667_enum_mbus_code, 291 }; 292 293 static struct v4l2_subdev_core_ops ml86v7667_subdev_core_ops = { 294 #ifdef CONFIG_VIDEO_ADV_DEBUG 295 .g_register = ml86v7667_g_register, 296 .s_register = ml86v7667_s_register, 297 #endif 298 }; 299 300 static struct v4l2_subdev_ops ml86v7667_subdev_ops = { 301 .core = &ml86v7667_subdev_core_ops, 302 .video = &ml86v7667_subdev_video_ops, 303 .pad = &ml86v7667_subdev_pad_ops, 304 }; 305 306 static int ml86v7667_init(struct ml86v7667_priv *priv) 307 { 308 struct i2c_client *client = v4l2_get_subdevdata(&priv->sd); 309 int val; 310 int ret; 311 312 /* BT.656-4 output mode, register mode */ 313 ret = ml86v7667_mask_set(client, MRA_REG, 314 MRA_OUTPUT_MODE_MASK | MRA_REGISTER_MODE, 315 MRA_ITUR_BT656 | MRA_REGISTER_MODE); 316 317 /* PLL circuit fixed clock, 32MHz */ 318 ret |= ml86v7667_mask_set(client, PLLR1_REG, PLLR1_FIXED_CLOCK, 319 PLLR1_FIXED_CLOCK); 320 321 /* ADC2 clamping voltage maximum */ 322 ret |= ml86v7667_mask_set(client, ADC2_REG, ADC2_CLAMP_VOLTAGE_MASK, 323 ADC2_CLAMP_VOLTAGE(7)); 324 325 /* enable luminance function */ 326 ret |= ml86v7667_mask_set(client, SSEPL_REG, SSEPL_LUMINANCE_ONOFF, 327 SSEPL_LUMINANCE_ONOFF); 328 329 /* enable contrast function */ 330 ret |= ml86v7667_mask_set(client, CLC_REG, CLC_CONTRAST_ONOFF, 0); 331 332 /* 333 * PAL/NTSC autodetection is enabled after reset, 334 * set the autodetected std in manual std mode and 335 * disable autodetection 336 */ 337 val = i2c_smbus_read_byte_data(client, STATUS_REG); 338 if (val < 0) 339 return val; 340 341 priv->std = val & STATUS_NTSCPAL ? V4L2_STD_625_50 : V4L2_STD_525_60; 342 ret |= ml86v7667_mask_set(client, MRC_REG, MRC_AUTOSELECT, 0); 343 344 val = priv->std & V4L2_STD_525_60 ? MRA_NTSC_BT601 : MRA_PAL_BT601; 345 ret |= ml86v7667_mask_set(client, MRA_REG, MRA_INPUT_MODE_MASK, val); 346 347 return ret; 348 } 349 350 static int ml86v7667_probe(struct i2c_client *client, 351 const struct i2c_device_id *did) 352 { 353 struct ml86v7667_priv *priv; 354 int ret; 355 356 if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA)) 357 return -EIO; 358 359 priv = devm_kzalloc(&client->dev, sizeof(*priv), GFP_KERNEL); 360 if (!priv) 361 return -ENOMEM; 362 363 v4l2_i2c_subdev_init(&priv->sd, client, &ml86v7667_subdev_ops); 364 365 v4l2_ctrl_handler_init(&priv->hdl, 8); 366 v4l2_ctrl_new_std(&priv->hdl, &ml86v7667_ctrl_ops, 367 V4L2_CID_BRIGHTNESS, -64, 63, 1, 0); 368 v4l2_ctrl_new_std(&priv->hdl, &ml86v7667_ctrl_ops, 369 V4L2_CID_CONTRAST, -8, 7, 1, 0); 370 v4l2_ctrl_new_std(&priv->hdl, &ml86v7667_ctrl_ops, 371 V4L2_CID_CHROMA_GAIN, -32, 31, 1, 0); 372 v4l2_ctrl_new_std(&priv->hdl, &ml86v7667_ctrl_ops, 373 V4L2_CID_HUE, -128, 127, 1, 0); 374 v4l2_ctrl_new_std(&priv->hdl, &ml86v7667_ctrl_ops, 375 V4L2_CID_RED_BALANCE, -4, 3, 1, 0); 376 v4l2_ctrl_new_std(&priv->hdl, &ml86v7667_ctrl_ops, 377 V4L2_CID_BLUE_BALANCE, -4, 3, 1, 0); 378 v4l2_ctrl_new_std(&priv->hdl, &ml86v7667_ctrl_ops, 379 V4L2_CID_SHARPNESS, 0, 1, 1, 0); 380 v4l2_ctrl_new_std(&priv->hdl, &ml86v7667_ctrl_ops, 381 V4L2_CID_COLOR_KILLER, 0, 1, 1, 0); 382 priv->sd.ctrl_handler = &priv->hdl; 383 384 ret = priv->hdl.error; 385 if (ret) 386 goto cleanup; 387 388 v4l2_ctrl_handler_setup(&priv->hdl); 389 390 ret = ml86v7667_init(priv); 391 if (ret) 392 goto cleanup; 393 394 v4l_info(client, "chip found @ 0x%02x (%s)\n", 395 client->addr, client->adapter->name); 396 return 0; 397 398 cleanup: 399 v4l2_ctrl_handler_free(&priv->hdl); 400 v4l2_device_unregister_subdev(&priv->sd); 401 v4l_err(client, "failed to probe @ 0x%02x (%s)\n", 402 client->addr, client->adapter->name); 403 return ret; 404 } 405 406 static int ml86v7667_remove(struct i2c_client *client) 407 { 408 struct v4l2_subdev *sd = i2c_get_clientdata(client); 409 struct ml86v7667_priv *priv = to_ml86v7667(sd); 410 411 v4l2_ctrl_handler_free(&priv->hdl); 412 v4l2_device_unregister_subdev(&priv->sd); 413 414 return 0; 415 } 416 417 static const struct i2c_device_id ml86v7667_id[] = { 418 {DRV_NAME, 0}, 419 {}, 420 }; 421 MODULE_DEVICE_TABLE(i2c, ml86v7667_id); 422 423 static struct i2c_driver ml86v7667_i2c_driver = { 424 .driver = { 425 .name = DRV_NAME, 426 .owner = THIS_MODULE, 427 }, 428 .probe = ml86v7667_probe, 429 .remove = ml86v7667_remove, 430 .id_table = ml86v7667_id, 431 }; 432 433 module_i2c_driver(ml86v7667_i2c_driver); 434 435 MODULE_DESCRIPTION("OKI Semiconductor ML86V7667 video decoder driver"); 436 MODULE_AUTHOR("Vladimir Barinov"); 437 MODULE_LICENSE("GPL"); 438