1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Maxim MAX9286 GMSL Deserializer Driver 4 * 5 * Copyright (C) 2017-2019 Jacopo Mondi 6 * Copyright (C) 2017-2019 Kieran Bingham 7 * Copyright (C) 2017-2019 Laurent Pinchart 8 * Copyright (C) 2017-2019 Niklas Söderlund 9 * Copyright (C) 2016 Renesas Electronics Corporation 10 * Copyright (C) 2015 Cogent Embedded, Inc. 11 */ 12 13 #include <linux/delay.h> 14 #include <linux/device.h> 15 #include <linux/fwnode.h> 16 #include <linux/gpio/consumer.h> 17 #include <linux/gpio/driver.h> 18 #include <linux/gpio/machine.h> 19 #include <linux/i2c.h> 20 #include <linux/i2c-mux.h> 21 #include <linux/module.h> 22 #include <linux/mutex.h> 23 #include <linux/of_graph.h> 24 #include <linux/regulator/consumer.h> 25 #include <linux/slab.h> 26 27 #include <media/v4l2-async.h> 28 #include <media/v4l2-ctrls.h> 29 #include <media/v4l2-device.h> 30 #include <media/v4l2-fwnode.h> 31 #include <media/v4l2-subdev.h> 32 33 /* Register 0x00 */ 34 #define MAX9286_MSTLINKSEL_AUTO (7 << 5) 35 #define MAX9286_MSTLINKSEL(n) ((n) << 5) 36 #define MAX9286_EN_VS_GEN BIT(4) 37 #define MAX9286_LINKEN(n) (1 << (n)) 38 /* Register 0x01 */ 39 #define MAX9286_FSYNCMODE_ECU (3 << 6) 40 #define MAX9286_FSYNCMODE_EXT (2 << 6) 41 #define MAX9286_FSYNCMODE_INT_OUT (1 << 6) 42 #define MAX9286_FSYNCMODE_INT_HIZ (0 << 6) 43 #define MAX9286_GPIEN BIT(5) 44 #define MAX9286_ENLMO_RSTFSYNC BIT(2) 45 #define MAX9286_FSYNCMETH_AUTO (2 << 0) 46 #define MAX9286_FSYNCMETH_SEMI_AUTO (1 << 0) 47 #define MAX9286_FSYNCMETH_MANUAL (0 << 0) 48 #define MAX9286_REG_FSYNC_PERIOD_L 0x06 49 #define MAX9286_REG_FSYNC_PERIOD_M 0x07 50 #define MAX9286_REG_FSYNC_PERIOD_H 0x08 51 /* Register 0x0a */ 52 #define MAX9286_FWDCCEN(n) (1 << ((n) + 4)) 53 #define MAX9286_REVCCEN(n) (1 << (n)) 54 /* Register 0x0c */ 55 #define MAX9286_HVEN BIT(7) 56 #define MAX9286_EDC_6BIT_HAMMING (2 << 5) 57 #define MAX9286_EDC_6BIT_CRC (1 << 5) 58 #define MAX9286_EDC_1BIT_PARITY (0 << 5) 59 #define MAX9286_DESEL BIT(4) 60 #define MAX9286_INVVS BIT(3) 61 #define MAX9286_INVHS BIT(2) 62 #define MAX9286_HVSRC_D0 (2 << 0) 63 #define MAX9286_HVSRC_D14 (1 << 0) 64 #define MAX9286_HVSRC_D18 (0 << 0) 65 /* Register 0x0f */ 66 #define MAX9286_0X0F_RESERVED BIT(3) 67 /* Register 0x12 */ 68 #define MAX9286_CSILANECNT(n) (((n) - 1) << 6) 69 #define MAX9286_CSIDBL BIT(5) 70 #define MAX9286_DBL BIT(4) 71 #define MAX9286_DATATYPE_USER_8BIT (11 << 0) 72 #define MAX9286_DATATYPE_USER_YUV_12BIT (10 << 0) 73 #define MAX9286_DATATYPE_USER_24BIT (9 << 0) 74 #define MAX9286_DATATYPE_RAW14 (8 << 0) 75 #define MAX9286_DATATYPE_RAW12 (7 << 0) 76 #define MAX9286_DATATYPE_RAW10 (6 << 0) 77 #define MAX9286_DATATYPE_RAW8 (5 << 0) 78 #define MAX9286_DATATYPE_YUV422_10BIT (4 << 0) 79 #define MAX9286_DATATYPE_YUV422_8BIT (3 << 0) 80 #define MAX9286_DATATYPE_RGB555 (2 << 0) 81 #define MAX9286_DATATYPE_RGB565 (1 << 0) 82 #define MAX9286_DATATYPE_RGB888 (0 << 0) 83 /* Register 0x15 */ 84 #define MAX9286_CSI_IMAGE_TYP BIT(7) 85 #define MAX9286_VC(n) ((n) << 5) 86 #define MAX9286_VCTYPE BIT(4) 87 #define MAX9286_CSIOUTEN BIT(3) 88 #define MAX9286_SWP_ENDIAN BIT(2) 89 #define MAX9286_EN_CCBSYB_CLK_STR BIT(1) 90 #define MAX9286_EN_GPI_CCBSYB BIT(0) 91 /* Register 0x1b */ 92 #define MAX9286_SWITCHIN(n) (1 << ((n) + 4)) 93 #define MAX9286_ENEQ(n) (1 << (n)) 94 /* Register 0x1c */ 95 #define MAX9286_HIGHIMM(n) BIT((n) + 4) 96 #define MAX9286_I2CSEL BIT(2) 97 #define MAX9286_HIBW BIT(1) 98 #define MAX9286_BWS BIT(0) 99 /* Register 0x27 */ 100 #define MAX9286_LOCKED BIT(7) 101 /* Register 0x31 */ 102 #define MAX9286_FSYNC_LOCKED BIT(6) 103 /* Register 0x34 */ 104 #define MAX9286_I2CLOCACK BIT(7) 105 #define MAX9286_I2CSLVSH_1046NS_469NS (3 << 5) 106 #define MAX9286_I2CSLVSH_938NS_352NS (2 << 5) 107 #define MAX9286_I2CSLVSH_469NS_234NS (1 << 5) 108 #define MAX9286_I2CSLVSH_352NS_117NS (0 << 5) 109 #define MAX9286_I2CMSTBT_837KBPS (7 << 2) 110 #define MAX9286_I2CMSTBT_533KBPS (6 << 2) 111 #define MAX9286_I2CMSTBT_339KBPS (5 << 2) 112 #define MAX9286_I2CMSTBT_173KBPS (4 << 2) 113 #define MAX9286_I2CMSTBT_105KBPS (3 << 2) 114 #define MAX9286_I2CMSTBT_84KBPS (2 << 2) 115 #define MAX9286_I2CMSTBT_28KBPS (1 << 2) 116 #define MAX9286_I2CMSTBT_8KBPS (0 << 2) 117 #define MAX9286_I2CSLVTO_NONE (3 << 0) 118 #define MAX9286_I2CSLVTO_1024US (2 << 0) 119 #define MAX9286_I2CSLVTO_256US (1 << 0) 120 #define MAX9286_I2CSLVTO_64US (0 << 0) 121 /* Register 0x3b */ 122 #define MAX9286_REV_TRF(n) ((n) << 4) 123 #define MAX9286_REV_AMP(n) ((((n) - 30) / 10) << 1) /* in mV */ 124 #define MAX9286_REV_AMP_X BIT(0) 125 #define MAX9286_REV_AMP_HIGH 170 126 /* Register 0x3f */ 127 #define MAX9286_EN_REV_CFG BIT(6) 128 #define MAX9286_REV_FLEN(n) ((n) - 20) 129 /* Register 0x49 */ 130 #define MAX9286_VIDEO_DETECT_MASK 0x0f 131 /* Register 0x69 */ 132 #define MAX9286_LFLTBMONMASKED BIT(7) 133 #define MAX9286_LOCKMONMASKED BIT(6) 134 #define MAX9286_AUTOCOMBACKEN BIT(5) 135 #define MAX9286_AUTOMASKEN BIT(4) 136 #define MAX9286_MASKLINK(n) ((n) << 0) 137 138 /* 139 * The sink and source pads are created to match the OF graph port numbers so 140 * that their indexes can be used interchangeably. 141 */ 142 #define MAX9286_NUM_GMSL 4 143 #define MAX9286_N_SINKS 4 144 #define MAX9286_N_PADS 5 145 #define MAX9286_SRC_PAD 4 146 147 struct max9286_format_info { 148 u32 code; 149 u8 datatype; 150 }; 151 152 struct max9286_i2c_speed { 153 u32 rate; 154 u8 mstbt; 155 }; 156 157 struct max9286_source { 158 struct v4l2_subdev *sd; 159 struct fwnode_handle *fwnode; 160 struct regulator *regulator; 161 }; 162 163 struct max9286_asd { 164 struct v4l2_async_subdev base; 165 struct max9286_source *source; 166 }; 167 168 static inline struct max9286_asd *to_max9286_asd(struct v4l2_async_subdev *asd) 169 { 170 return container_of(asd, struct max9286_asd, base); 171 } 172 173 struct max9286_priv { 174 struct i2c_client *client; 175 struct gpio_desc *gpiod_pwdn; 176 struct v4l2_subdev sd; 177 struct media_pad pads[MAX9286_N_PADS]; 178 struct regulator *regulator; 179 180 struct gpio_chip gpio; 181 u8 gpio_state; 182 183 struct i2c_mux_core *mux; 184 unsigned int mux_channel; 185 bool mux_open; 186 187 /* The initial reverse control channel amplitude. */ 188 u32 init_rev_chan_mv; 189 u32 rev_chan_mv; 190 u8 i2c_mstbt; 191 u32 bus_width; 192 193 bool use_gpio_poc; 194 u32 gpio_poc[2]; 195 196 struct v4l2_ctrl_handler ctrls; 197 struct v4l2_ctrl *pixelrate_ctrl; 198 unsigned int pixelrate; 199 200 struct v4l2_mbus_framefmt fmt[MAX9286_N_SINKS]; 201 struct v4l2_fract interval; 202 203 /* Protects controls and fmt structures */ 204 struct mutex mutex; 205 206 unsigned int nsources; 207 unsigned int source_mask; 208 unsigned int route_mask; 209 unsigned int bound_sources; 210 unsigned int csi2_data_lanes; 211 struct max9286_source sources[MAX9286_NUM_GMSL]; 212 struct v4l2_async_notifier notifier; 213 }; 214 215 static struct max9286_source *next_source(struct max9286_priv *priv, 216 struct max9286_source *source) 217 { 218 if (!source) 219 source = &priv->sources[0]; 220 else 221 source++; 222 223 for (; source < &priv->sources[MAX9286_NUM_GMSL]; source++) { 224 if (source->fwnode) 225 return source; 226 } 227 228 return NULL; 229 } 230 231 #define for_each_source(priv, source) \ 232 for ((source) = NULL; ((source) = next_source((priv), (source))); ) 233 234 #define to_index(priv, source) ((source) - &(priv)->sources[0]) 235 236 static inline struct max9286_priv *sd_to_max9286(struct v4l2_subdev *sd) 237 { 238 return container_of(sd, struct max9286_priv, sd); 239 } 240 241 static const struct max9286_format_info max9286_formats[] = { 242 { 243 .code = MEDIA_BUS_FMT_UYVY8_1X16, 244 .datatype = MAX9286_DATATYPE_YUV422_8BIT, 245 }, { 246 .code = MEDIA_BUS_FMT_VYUY8_1X16, 247 .datatype = MAX9286_DATATYPE_YUV422_8BIT, 248 }, { 249 .code = MEDIA_BUS_FMT_YUYV8_1X16, 250 .datatype = MAX9286_DATATYPE_YUV422_8BIT, 251 }, { 252 .code = MEDIA_BUS_FMT_YVYU8_1X16, 253 .datatype = MAX9286_DATATYPE_YUV422_8BIT, 254 }, { 255 .code = MEDIA_BUS_FMT_SBGGR12_1X12, 256 .datatype = MAX9286_DATATYPE_RAW12, 257 }, { 258 .code = MEDIA_BUS_FMT_SGBRG12_1X12, 259 .datatype = MAX9286_DATATYPE_RAW12, 260 }, { 261 .code = MEDIA_BUS_FMT_SGRBG12_1X12, 262 .datatype = MAX9286_DATATYPE_RAW12, 263 }, { 264 .code = MEDIA_BUS_FMT_SRGGB12_1X12, 265 .datatype = MAX9286_DATATYPE_RAW12, 266 }, 267 }; 268 269 static const struct max9286_i2c_speed max9286_i2c_speeds[] = { 270 { .rate = 8470, .mstbt = MAX9286_I2CMSTBT_8KBPS }, 271 { .rate = 28300, .mstbt = MAX9286_I2CMSTBT_28KBPS }, 272 { .rate = 84700, .mstbt = MAX9286_I2CMSTBT_84KBPS }, 273 { .rate = 105000, .mstbt = MAX9286_I2CMSTBT_105KBPS }, 274 { .rate = 173000, .mstbt = MAX9286_I2CMSTBT_173KBPS }, 275 { .rate = 339000, .mstbt = MAX9286_I2CMSTBT_339KBPS }, 276 { .rate = 533000, .mstbt = MAX9286_I2CMSTBT_533KBPS }, 277 { .rate = 837000, .mstbt = MAX9286_I2CMSTBT_837KBPS }, 278 }; 279 280 /* ----------------------------------------------------------------------------- 281 * I2C IO 282 */ 283 284 static int max9286_read(struct max9286_priv *priv, u8 reg) 285 { 286 int ret; 287 288 ret = i2c_smbus_read_byte_data(priv->client, reg); 289 if (ret < 0) 290 dev_err(&priv->client->dev, 291 "%s: register 0x%02x read failed (%d)\n", 292 __func__, reg, ret); 293 294 return ret; 295 } 296 297 static int max9286_write(struct max9286_priv *priv, u8 reg, u8 val) 298 { 299 int ret; 300 301 ret = i2c_smbus_write_byte_data(priv->client, reg, val); 302 if (ret < 0) 303 dev_err(&priv->client->dev, 304 "%s: register 0x%02x write failed (%d)\n", 305 __func__, reg, ret); 306 307 return ret; 308 } 309 310 /* ----------------------------------------------------------------------------- 311 * I2C Multiplexer 312 */ 313 314 static void max9286_i2c_mux_configure(struct max9286_priv *priv, u8 conf) 315 { 316 max9286_write(priv, 0x0a, conf); 317 318 /* 319 * We must sleep after any change to the forward or reverse channel 320 * configuration. 321 */ 322 usleep_range(3000, 5000); 323 } 324 325 static void max9286_i2c_mux_open(struct max9286_priv *priv) 326 { 327 /* Open all channels on the MAX9286 */ 328 max9286_i2c_mux_configure(priv, 0xff); 329 330 priv->mux_open = true; 331 } 332 333 static void max9286_i2c_mux_close(struct max9286_priv *priv) 334 { 335 /* 336 * Ensure that both the forward and reverse channel are disabled on the 337 * mux, and that the channel ID is invalidated to ensure we reconfigure 338 * on the next max9286_i2c_mux_select() call. 339 */ 340 max9286_i2c_mux_configure(priv, 0x00); 341 342 priv->mux_open = false; 343 priv->mux_channel = -1; 344 } 345 346 static int max9286_i2c_mux_select(struct i2c_mux_core *muxc, u32 chan) 347 { 348 struct max9286_priv *priv = i2c_mux_priv(muxc); 349 350 /* Channel select is disabled when configured in the opened state. */ 351 if (priv->mux_open) 352 return 0; 353 354 if (priv->mux_channel == chan) 355 return 0; 356 357 priv->mux_channel = chan; 358 359 max9286_i2c_mux_configure(priv, MAX9286_FWDCCEN(chan) | 360 MAX9286_REVCCEN(chan)); 361 362 return 0; 363 } 364 365 static int max9286_i2c_mux_init(struct max9286_priv *priv) 366 { 367 struct max9286_source *source; 368 int ret; 369 370 if (!i2c_check_functionality(priv->client->adapter, 371 I2C_FUNC_SMBUS_WRITE_BYTE_DATA)) 372 return -ENODEV; 373 374 priv->mux = i2c_mux_alloc(priv->client->adapter, &priv->client->dev, 375 priv->nsources, 0, I2C_MUX_LOCKED, 376 max9286_i2c_mux_select, NULL); 377 if (!priv->mux) 378 return -ENOMEM; 379 380 priv->mux->priv = priv; 381 382 for_each_source(priv, source) { 383 unsigned int index = to_index(priv, source); 384 385 ret = i2c_mux_add_adapter(priv->mux, 0, index, 0); 386 if (ret < 0) 387 goto error; 388 } 389 390 return 0; 391 392 error: 393 i2c_mux_del_adapters(priv->mux); 394 return ret; 395 } 396 397 static void max9286_configure_i2c(struct max9286_priv *priv, bool localack) 398 { 399 u8 config = MAX9286_I2CSLVSH_469NS_234NS | MAX9286_I2CSLVTO_1024US | 400 priv->i2c_mstbt; 401 402 if (localack) 403 config |= MAX9286_I2CLOCACK; 404 405 max9286_write(priv, 0x34, config); 406 usleep_range(3000, 5000); 407 } 408 409 static void max9286_reverse_channel_setup(struct max9286_priv *priv, 410 unsigned int chan_amplitude) 411 { 412 u8 chan_config; 413 414 if (priv->rev_chan_mv == chan_amplitude) 415 return; 416 417 priv->rev_chan_mv = chan_amplitude; 418 419 /* Reverse channel transmission time: default to 1. */ 420 chan_config = MAX9286_REV_TRF(1); 421 422 /* 423 * Reverse channel setup. 424 * 425 * - Enable custom reverse channel configuration (through register 0x3f) 426 * and set the first pulse length to 35 clock cycles. 427 * - Adjust reverse channel amplitude: values > 130 are programmed 428 * using the additional +100mV REV_AMP_X boost flag 429 */ 430 max9286_write(priv, 0x3f, MAX9286_EN_REV_CFG | MAX9286_REV_FLEN(35)); 431 432 if (chan_amplitude > 100) { 433 /* It is not possible to express values (100 < x < 130) */ 434 chan_amplitude = max(30U, chan_amplitude - 100); 435 chan_config |= MAX9286_REV_AMP_X; 436 } 437 max9286_write(priv, 0x3b, chan_config | MAX9286_REV_AMP(chan_amplitude)); 438 usleep_range(2000, 2500); 439 } 440 441 /* 442 * max9286_check_video_links() - Make sure video links are detected and locked 443 * 444 * Performs safety checks on video link status. Make sure they are detected 445 * and all enabled links are locked. 446 * 447 * Returns 0 for success, -EIO for errors. 448 */ 449 static int max9286_check_video_links(struct max9286_priv *priv) 450 { 451 unsigned int i; 452 int ret; 453 454 /* 455 * Make sure valid video links are detected. 456 * The delay is not characterized in de-serializer manual, wait up 457 * to 5 ms. 458 */ 459 for (i = 0; i < 10; i++) { 460 ret = max9286_read(priv, 0x49); 461 if (ret < 0) 462 return -EIO; 463 464 if ((ret & MAX9286_VIDEO_DETECT_MASK) == priv->source_mask) 465 break; 466 467 usleep_range(350, 500); 468 } 469 470 if (i == 10) { 471 dev_err(&priv->client->dev, 472 "Unable to detect video links: 0x%02x\n", ret); 473 return -EIO; 474 } 475 476 /* Make sure all enabled links are locked (4ms max). */ 477 for (i = 0; i < 10; i++) { 478 ret = max9286_read(priv, 0x27); 479 if (ret < 0) 480 return -EIO; 481 482 if (ret & MAX9286_LOCKED) 483 break; 484 485 usleep_range(350, 450); 486 } 487 488 if (i == 10) { 489 dev_err(&priv->client->dev, "Not all enabled links locked\n"); 490 return -EIO; 491 } 492 493 return 0; 494 } 495 496 /* 497 * max9286_check_config_link() - Detect and wait for configuration links 498 * 499 * Determine if the configuration channel is up and settled for a link. 500 * 501 * Returns 0 for success, -EIO for errors. 502 */ 503 static int max9286_check_config_link(struct max9286_priv *priv, 504 unsigned int source_mask) 505 { 506 unsigned int conflink_mask = (source_mask & 0x0f) << 4; 507 unsigned int i; 508 int ret; 509 510 /* 511 * Make sure requested configuration links are detected. 512 * The delay is not characterized in the chip manual: wait up 513 * to 5 milliseconds. 514 */ 515 for (i = 0; i < 10; i++) { 516 ret = max9286_read(priv, 0x49); 517 if (ret < 0) 518 return -EIO; 519 520 ret &= 0xf0; 521 if (ret == conflink_mask) 522 break; 523 524 usleep_range(350, 500); 525 } 526 527 if (ret != conflink_mask) { 528 dev_err(&priv->client->dev, 529 "Unable to detect configuration links: 0x%02x expected 0x%02x\n", 530 ret, conflink_mask); 531 return -EIO; 532 } 533 534 dev_info(&priv->client->dev, 535 "Successfully detected configuration links after %u loops: 0x%02x\n", 536 i, conflink_mask); 537 538 return 0; 539 } 540 541 static void max9286_set_video_format(struct max9286_priv *priv, 542 const struct v4l2_mbus_framefmt *format) 543 { 544 const struct max9286_format_info *info = NULL; 545 unsigned int i; 546 547 for (i = 0; i < ARRAY_SIZE(max9286_formats); ++i) { 548 if (max9286_formats[i].code == format->code) { 549 info = &max9286_formats[i]; 550 break; 551 } 552 } 553 554 if (WARN_ON(!info)) 555 return; 556 557 /* 558 * Video format setup: disable CSI output, set VC according to Link 559 * number, enable I2C clock stretching when CCBSY is low, enable CCBSY 560 * in external GPI-to-GPO mode. 561 */ 562 max9286_write(priv, 0x15, MAX9286_VCTYPE | MAX9286_EN_CCBSYB_CLK_STR | 563 MAX9286_EN_GPI_CCBSYB); 564 565 /* Enable CSI-2 Lane D0-D3 only, DBL mode. */ 566 max9286_write(priv, 0x12, MAX9286_CSIDBL | MAX9286_DBL | 567 MAX9286_CSILANECNT(priv->csi2_data_lanes) | 568 info->datatype); 569 570 /* 571 * Enable HS/VS encoding, use HS as line valid source, use D14/15 for 572 * HS/VS, invert VS. 573 */ 574 max9286_write(priv, 0x0c, MAX9286_HVEN | MAX9286_DESEL | 575 MAX9286_INVVS | MAX9286_HVSRC_D14); 576 } 577 578 static void max9286_set_fsync_period(struct max9286_priv *priv) 579 { 580 u32 fsync; 581 582 if (!priv->interval.numerator || !priv->interval.denominator) { 583 /* 584 * Special case, a null interval enables automatic FRAMESYNC 585 * mode. FRAMESYNC is taken from the slowest link. 586 */ 587 max9286_write(priv, 0x01, MAX9286_FSYNCMODE_INT_HIZ | 588 MAX9286_FSYNCMETH_AUTO); 589 return; 590 } 591 592 /* 593 * Manual FRAMESYNC 594 * 595 * The FRAMESYNC generator is configured with a period expressed as a 596 * number of PCLK periods. 597 */ 598 fsync = div_u64((u64)priv->pixelrate * priv->interval.numerator, 599 priv->interval.denominator); 600 601 dev_dbg(&priv->client->dev, "fsync period %u (pclk %u)\n", fsync, 602 priv->pixelrate); 603 604 max9286_write(priv, 0x01, MAX9286_FSYNCMODE_INT_OUT | 605 MAX9286_FSYNCMETH_MANUAL); 606 607 max9286_write(priv, 0x06, (fsync >> 0) & 0xff); 608 max9286_write(priv, 0x07, (fsync >> 8) & 0xff); 609 max9286_write(priv, 0x08, (fsync >> 16) & 0xff); 610 } 611 612 /* ----------------------------------------------------------------------------- 613 * V4L2 Subdev 614 */ 615 616 static int max9286_set_pixelrate(struct max9286_priv *priv) 617 { 618 struct max9286_source *source = NULL; 619 u64 pixelrate = 0; 620 621 for_each_source(priv, source) { 622 struct v4l2_ctrl *ctrl; 623 u64 source_rate = 0; 624 625 /* Pixel rate is mandatory to be reported by sources. */ 626 ctrl = v4l2_ctrl_find(source->sd->ctrl_handler, 627 V4L2_CID_PIXEL_RATE); 628 if (!ctrl) { 629 pixelrate = 0; 630 break; 631 } 632 633 /* All source must report the same pixel rate. */ 634 source_rate = v4l2_ctrl_g_ctrl_int64(ctrl); 635 if (!pixelrate) { 636 pixelrate = source_rate; 637 } else if (pixelrate != source_rate) { 638 dev_err(&priv->client->dev, 639 "Unable to calculate pixel rate\n"); 640 return -EINVAL; 641 } 642 } 643 644 if (!pixelrate) { 645 dev_err(&priv->client->dev, 646 "No pixel rate control available in sources\n"); 647 return -EINVAL; 648 } 649 650 priv->pixelrate = pixelrate; 651 652 /* 653 * The CSI-2 transmitter pixel rate is the single source rate multiplied 654 * by the number of available sources. 655 */ 656 return v4l2_ctrl_s_ctrl_int64(priv->pixelrate_ctrl, 657 pixelrate * priv->nsources); 658 } 659 660 static int max9286_notify_bound(struct v4l2_async_notifier *notifier, 661 struct v4l2_subdev *subdev, 662 struct v4l2_async_subdev *asd) 663 { 664 struct max9286_priv *priv = sd_to_max9286(notifier->sd); 665 struct max9286_source *source = to_max9286_asd(asd)->source; 666 unsigned int index = to_index(priv, source); 667 unsigned int src_pad; 668 int ret; 669 670 ret = media_entity_get_fwnode_pad(&subdev->entity, 671 source->fwnode, 672 MEDIA_PAD_FL_SOURCE); 673 if (ret < 0) { 674 dev_err(&priv->client->dev, 675 "Failed to find pad for %s\n", subdev->name); 676 return ret; 677 } 678 679 priv->bound_sources |= BIT(index); 680 source->sd = subdev; 681 src_pad = ret; 682 683 ret = media_create_pad_link(&source->sd->entity, src_pad, 684 &priv->sd.entity, index, 685 MEDIA_LNK_FL_ENABLED | 686 MEDIA_LNK_FL_IMMUTABLE); 687 if (ret) { 688 dev_err(&priv->client->dev, 689 "Unable to link %s:%u -> %s:%u\n", 690 source->sd->name, src_pad, priv->sd.name, index); 691 return ret; 692 } 693 694 dev_dbg(&priv->client->dev, "Bound %s pad: %u on index %u\n", 695 subdev->name, src_pad, index); 696 697 /* 698 * As we register a subdev notifiers we won't get a .complete() callback 699 * here, so we have to use bound_sources to identify when all remote 700 * serializers have probed. 701 */ 702 if (priv->bound_sources != priv->source_mask) 703 return 0; 704 705 /* 706 * All enabled sources have probed and enabled their reverse control 707 * channels: 708 * 709 * - Increase the reverse channel amplitude to compensate for the 710 * remote ends high threshold 711 * - Verify all configuration links are properly detected 712 * - Disable auto-ack as communication on the control channel are now 713 * stable. 714 */ 715 max9286_reverse_channel_setup(priv, MAX9286_REV_AMP_HIGH); 716 max9286_check_config_link(priv, priv->source_mask); 717 max9286_configure_i2c(priv, false); 718 719 return max9286_set_pixelrate(priv); 720 } 721 722 static void max9286_notify_unbind(struct v4l2_async_notifier *notifier, 723 struct v4l2_subdev *subdev, 724 struct v4l2_async_subdev *asd) 725 { 726 struct max9286_priv *priv = sd_to_max9286(notifier->sd); 727 struct max9286_source *source = to_max9286_asd(asd)->source; 728 unsigned int index = to_index(priv, source); 729 730 source->sd = NULL; 731 priv->bound_sources &= ~BIT(index); 732 } 733 734 static const struct v4l2_async_notifier_operations max9286_notify_ops = { 735 .bound = max9286_notify_bound, 736 .unbind = max9286_notify_unbind, 737 }; 738 739 static int max9286_v4l2_notifier_register(struct max9286_priv *priv) 740 { 741 struct device *dev = &priv->client->dev; 742 struct max9286_source *source = NULL; 743 int ret; 744 745 if (!priv->nsources) 746 return 0; 747 748 v4l2_async_nf_init(&priv->notifier); 749 750 for_each_source(priv, source) { 751 unsigned int i = to_index(priv, source); 752 struct max9286_asd *mas; 753 754 mas = v4l2_async_nf_add_fwnode(&priv->notifier, source->fwnode, 755 struct max9286_asd); 756 if (IS_ERR(mas)) { 757 dev_err(dev, "Failed to add subdev for source %u: %ld", 758 i, PTR_ERR(mas)); 759 v4l2_async_nf_cleanup(&priv->notifier); 760 return PTR_ERR(mas); 761 } 762 763 mas->source = source; 764 } 765 766 priv->notifier.ops = &max9286_notify_ops; 767 768 ret = v4l2_async_subdev_nf_register(&priv->sd, &priv->notifier); 769 if (ret) { 770 dev_err(dev, "Failed to register subdev_notifier"); 771 v4l2_async_nf_cleanup(&priv->notifier); 772 return ret; 773 } 774 775 return 0; 776 } 777 778 static void max9286_v4l2_notifier_unregister(struct max9286_priv *priv) 779 { 780 if (!priv->nsources) 781 return; 782 783 v4l2_async_nf_unregister(&priv->notifier); 784 v4l2_async_nf_cleanup(&priv->notifier); 785 } 786 787 static int max9286_s_stream(struct v4l2_subdev *sd, int enable) 788 { 789 struct max9286_priv *priv = sd_to_max9286(sd); 790 struct max9286_source *source; 791 unsigned int i; 792 bool sync = false; 793 int ret; 794 795 if (enable) { 796 const struct v4l2_mbus_framefmt *format; 797 798 /* 799 * Get the format from the first used sink pad, as all sink 800 * formats must be identical. 801 */ 802 format = &priv->fmt[__ffs(priv->bound_sources)]; 803 804 max9286_set_video_format(priv, format); 805 max9286_set_fsync_period(priv); 806 807 /* 808 * The frame sync between cameras is transmitted across the 809 * reverse channel as GPIO. We must open all channels while 810 * streaming to allow this synchronisation signal to be shared. 811 */ 812 max9286_i2c_mux_open(priv); 813 814 /* Start all cameras. */ 815 for_each_source(priv, source) { 816 ret = v4l2_subdev_call(source->sd, video, s_stream, 1); 817 if (ret) 818 return ret; 819 } 820 821 ret = max9286_check_video_links(priv); 822 if (ret) 823 return ret; 824 825 /* 826 * Wait until frame synchronization is locked. 827 * 828 * Manual says frame sync locking should take ~6 VTS. 829 * From practical experience at least 8 are required. Give 830 * 12 complete frames time (~400ms at 30 fps) to achieve frame 831 * locking before returning error. 832 */ 833 for (i = 0; i < 40; i++) { 834 if (max9286_read(priv, 0x31) & MAX9286_FSYNC_LOCKED) { 835 sync = true; 836 break; 837 } 838 usleep_range(9000, 11000); 839 } 840 841 if (!sync) { 842 dev_err(&priv->client->dev, 843 "Failed to get frame synchronization\n"); 844 return -EXDEV; /* Invalid cross-device link */ 845 } 846 847 /* 848 * Configure the CSI-2 output to line interleaved mode (W x (N 849 * x H), as opposed to the (N x W) x H mode that outputs the 850 * images stitched side-by-side) and enable it. 851 */ 852 max9286_write(priv, 0x15, MAX9286_CSI_IMAGE_TYP | MAX9286_VCTYPE | 853 MAX9286_CSIOUTEN | MAX9286_EN_CCBSYB_CLK_STR | 854 MAX9286_EN_GPI_CCBSYB); 855 } else { 856 max9286_write(priv, 0x15, MAX9286_VCTYPE | 857 MAX9286_EN_CCBSYB_CLK_STR | 858 MAX9286_EN_GPI_CCBSYB); 859 860 /* Stop all cameras. */ 861 for_each_source(priv, source) 862 v4l2_subdev_call(source->sd, video, s_stream, 0); 863 864 max9286_i2c_mux_close(priv); 865 } 866 867 return 0; 868 } 869 870 static int max9286_g_frame_interval(struct v4l2_subdev *sd, 871 struct v4l2_subdev_frame_interval *interval) 872 { 873 struct max9286_priv *priv = sd_to_max9286(sd); 874 875 if (interval->pad != MAX9286_SRC_PAD) 876 return -EINVAL; 877 878 interval->interval = priv->interval; 879 880 return 0; 881 } 882 883 static int max9286_s_frame_interval(struct v4l2_subdev *sd, 884 struct v4l2_subdev_frame_interval *interval) 885 { 886 struct max9286_priv *priv = sd_to_max9286(sd); 887 888 if (interval->pad != MAX9286_SRC_PAD) 889 return -EINVAL; 890 891 priv->interval = interval->interval; 892 893 return 0; 894 } 895 896 static int max9286_enum_mbus_code(struct v4l2_subdev *sd, 897 struct v4l2_subdev_state *sd_state, 898 struct v4l2_subdev_mbus_code_enum *code) 899 { 900 if (code->pad || code->index > 0) 901 return -EINVAL; 902 903 code->code = MEDIA_BUS_FMT_UYVY8_1X16; 904 905 return 0; 906 } 907 908 static struct v4l2_mbus_framefmt * 909 max9286_get_pad_format(struct max9286_priv *priv, 910 struct v4l2_subdev_state *sd_state, 911 unsigned int pad, u32 which) 912 { 913 switch (which) { 914 case V4L2_SUBDEV_FORMAT_TRY: 915 return v4l2_subdev_get_try_format(&priv->sd, sd_state, pad); 916 case V4L2_SUBDEV_FORMAT_ACTIVE: 917 return &priv->fmt[pad]; 918 default: 919 return NULL; 920 } 921 } 922 923 static int max9286_set_fmt(struct v4l2_subdev *sd, 924 struct v4l2_subdev_state *sd_state, 925 struct v4l2_subdev_format *format) 926 { 927 struct max9286_priv *priv = sd_to_max9286(sd); 928 struct v4l2_mbus_framefmt *cfg_fmt; 929 unsigned int i; 930 931 if (format->pad == MAX9286_SRC_PAD) 932 return -EINVAL; 933 934 /* Validate the format. */ 935 for (i = 0; i < ARRAY_SIZE(max9286_formats); ++i) { 936 if (max9286_formats[i].code == format->format.code) 937 break; 938 } 939 940 if (i == ARRAY_SIZE(max9286_formats)) 941 format->format.code = max9286_formats[0].code; 942 943 cfg_fmt = max9286_get_pad_format(priv, sd_state, format->pad, 944 format->which); 945 if (!cfg_fmt) 946 return -EINVAL; 947 948 mutex_lock(&priv->mutex); 949 *cfg_fmt = format->format; 950 mutex_unlock(&priv->mutex); 951 952 return 0; 953 } 954 955 static int max9286_get_fmt(struct v4l2_subdev *sd, 956 struct v4l2_subdev_state *sd_state, 957 struct v4l2_subdev_format *format) 958 { 959 struct max9286_priv *priv = sd_to_max9286(sd); 960 struct v4l2_mbus_framefmt *cfg_fmt; 961 unsigned int pad = format->pad; 962 963 /* 964 * Multiplexed Stream Support: Support link validation by returning the 965 * format of the first bound link. All links must have the same format, 966 * as we do not support mixing and matching of cameras connected to the 967 * max9286. 968 */ 969 if (pad == MAX9286_SRC_PAD) 970 pad = __ffs(priv->bound_sources); 971 972 cfg_fmt = max9286_get_pad_format(priv, sd_state, pad, format->which); 973 if (!cfg_fmt) 974 return -EINVAL; 975 976 mutex_lock(&priv->mutex); 977 format->format = *cfg_fmt; 978 mutex_unlock(&priv->mutex); 979 980 return 0; 981 } 982 983 static const struct v4l2_subdev_video_ops max9286_video_ops = { 984 .s_stream = max9286_s_stream, 985 .g_frame_interval = max9286_g_frame_interval, 986 .s_frame_interval = max9286_s_frame_interval, 987 }; 988 989 static const struct v4l2_subdev_pad_ops max9286_pad_ops = { 990 .enum_mbus_code = max9286_enum_mbus_code, 991 .get_fmt = max9286_get_fmt, 992 .set_fmt = max9286_set_fmt, 993 }; 994 995 static const struct v4l2_subdev_ops max9286_subdev_ops = { 996 .video = &max9286_video_ops, 997 .pad = &max9286_pad_ops, 998 }; 999 1000 static const struct v4l2_mbus_framefmt max9286_default_format = { 1001 .width = 1280, 1002 .height = 800, 1003 .code = MEDIA_BUS_FMT_UYVY8_1X16, 1004 .colorspace = V4L2_COLORSPACE_SRGB, 1005 .field = V4L2_FIELD_NONE, 1006 .ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT, 1007 .quantization = V4L2_QUANTIZATION_DEFAULT, 1008 .xfer_func = V4L2_XFER_FUNC_DEFAULT, 1009 }; 1010 1011 static void max9286_init_format(struct v4l2_mbus_framefmt *fmt) 1012 { 1013 *fmt = max9286_default_format; 1014 } 1015 1016 static int max9286_open(struct v4l2_subdev *subdev, struct v4l2_subdev_fh *fh) 1017 { 1018 struct v4l2_mbus_framefmt *format; 1019 unsigned int i; 1020 1021 for (i = 0; i < MAX9286_N_SINKS; i++) { 1022 format = v4l2_subdev_get_try_format(subdev, fh->state, i); 1023 max9286_init_format(format); 1024 } 1025 1026 return 0; 1027 } 1028 1029 static const struct v4l2_subdev_internal_ops max9286_subdev_internal_ops = { 1030 .open = max9286_open, 1031 }; 1032 1033 static const struct media_entity_operations max9286_media_ops = { 1034 .link_validate = v4l2_subdev_link_validate 1035 }; 1036 1037 static int max9286_s_ctrl(struct v4l2_ctrl *ctrl) 1038 { 1039 switch (ctrl->id) { 1040 case V4L2_CID_PIXEL_RATE: 1041 return 0; 1042 default: 1043 return -EINVAL; 1044 } 1045 } 1046 1047 static const struct v4l2_ctrl_ops max9286_ctrl_ops = { 1048 .s_ctrl = max9286_s_ctrl, 1049 }; 1050 1051 static int max9286_v4l2_register(struct max9286_priv *priv) 1052 { 1053 struct device *dev = &priv->client->dev; 1054 struct fwnode_handle *ep; 1055 int ret; 1056 int i; 1057 1058 /* Register v4l2 async notifiers for connected Camera subdevices */ 1059 ret = max9286_v4l2_notifier_register(priv); 1060 if (ret) { 1061 dev_err(dev, "Unable to register V4L2 async notifiers\n"); 1062 return ret; 1063 } 1064 1065 /* Configure V4L2 for the MAX9286 itself */ 1066 1067 for (i = 0; i < MAX9286_N_SINKS; i++) 1068 max9286_init_format(&priv->fmt[i]); 1069 1070 v4l2_i2c_subdev_init(&priv->sd, priv->client, &max9286_subdev_ops); 1071 priv->sd.internal_ops = &max9286_subdev_internal_ops; 1072 priv->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; 1073 1074 v4l2_ctrl_handler_init(&priv->ctrls, 1); 1075 priv->pixelrate_ctrl = v4l2_ctrl_new_std(&priv->ctrls, 1076 &max9286_ctrl_ops, 1077 V4L2_CID_PIXEL_RATE, 1078 1, INT_MAX, 1, 50000000); 1079 1080 priv->sd.ctrl_handler = &priv->ctrls; 1081 ret = priv->ctrls.error; 1082 if (ret) 1083 goto err_async; 1084 1085 priv->sd.entity.function = MEDIA_ENT_F_VID_IF_BRIDGE; 1086 priv->sd.entity.ops = &max9286_media_ops; 1087 1088 priv->pads[MAX9286_SRC_PAD].flags = MEDIA_PAD_FL_SOURCE; 1089 for (i = 0; i < MAX9286_SRC_PAD; i++) 1090 priv->pads[i].flags = MEDIA_PAD_FL_SINK; 1091 ret = media_entity_pads_init(&priv->sd.entity, MAX9286_N_PADS, 1092 priv->pads); 1093 if (ret) 1094 goto err_async; 1095 1096 ep = fwnode_graph_get_endpoint_by_id(dev_fwnode(dev), MAX9286_SRC_PAD, 1097 0, 0); 1098 if (!ep) { 1099 dev_err(dev, "Unable to retrieve endpoint on \"port@4\"\n"); 1100 ret = -ENOENT; 1101 goto err_async; 1102 } 1103 priv->sd.fwnode = ep; 1104 1105 ret = v4l2_async_register_subdev(&priv->sd); 1106 if (ret < 0) { 1107 dev_err(dev, "Unable to register subdevice\n"); 1108 goto err_put_node; 1109 } 1110 1111 return 0; 1112 1113 err_put_node: 1114 fwnode_handle_put(ep); 1115 err_async: 1116 v4l2_ctrl_handler_free(&priv->ctrls); 1117 max9286_v4l2_notifier_unregister(priv); 1118 1119 return ret; 1120 } 1121 1122 static void max9286_v4l2_unregister(struct max9286_priv *priv) 1123 { 1124 fwnode_handle_put(priv->sd.fwnode); 1125 v4l2_async_unregister_subdev(&priv->sd); 1126 max9286_v4l2_notifier_unregister(priv); 1127 } 1128 1129 /* ----------------------------------------------------------------------------- 1130 * Probe/Remove 1131 */ 1132 1133 static int max9286_setup(struct max9286_priv *priv) 1134 { 1135 /* 1136 * Link ordering values for all enabled links combinations. Orders must 1137 * be assigned sequentially from 0 to the number of enabled links 1138 * without leaving any hole for disabled links. We thus assign orders to 1139 * enabled links first, and use the remaining order values for disabled 1140 * links are all links must have a different order value; 1141 */ 1142 static const u8 link_order[] = { 1143 (3 << 6) | (2 << 4) | (1 << 2) | (0 << 0), /* xxxx */ 1144 (3 << 6) | (2 << 4) | (1 << 2) | (0 << 0), /* xxx0 */ 1145 (3 << 6) | (2 << 4) | (0 << 2) | (1 << 0), /* xx0x */ 1146 (3 << 6) | (2 << 4) | (1 << 2) | (0 << 0), /* xx10 */ 1147 (3 << 6) | (0 << 4) | (2 << 2) | (1 << 0), /* x0xx */ 1148 (3 << 6) | (1 << 4) | (2 << 2) | (0 << 0), /* x1x0 */ 1149 (3 << 6) | (1 << 4) | (0 << 2) | (2 << 0), /* x10x */ 1150 (3 << 6) | (1 << 4) | (1 << 2) | (0 << 0), /* x210 */ 1151 (0 << 6) | (3 << 4) | (2 << 2) | (1 << 0), /* 0xxx */ 1152 (1 << 6) | (3 << 4) | (2 << 2) | (0 << 0), /* 1xx0 */ 1153 (1 << 6) | (3 << 4) | (0 << 2) | (2 << 0), /* 1x0x */ 1154 (2 << 6) | (3 << 4) | (1 << 2) | (0 << 0), /* 2x10 */ 1155 (1 << 6) | (0 << 4) | (3 << 2) | (2 << 0), /* 10xx */ 1156 (2 << 6) | (1 << 4) | (3 << 2) | (0 << 0), /* 21x0 */ 1157 (2 << 6) | (1 << 4) | (0 << 2) | (3 << 0), /* 210x */ 1158 (3 << 6) | (2 << 4) | (1 << 2) | (0 << 0), /* 3210 */ 1159 }; 1160 int cfg; 1161 1162 /* 1163 * Set the I2C bus speed. 1164 * 1165 * Enable I2C Local Acknowledge during the probe sequences of the camera 1166 * only. This should be disabled after the mux is initialised. 1167 */ 1168 max9286_configure_i2c(priv, true); 1169 max9286_reverse_channel_setup(priv, priv->init_rev_chan_mv); 1170 1171 /* 1172 * Enable GMSL links, mask unused ones and autodetect link 1173 * used as CSI clock source. 1174 */ 1175 max9286_write(priv, 0x00, MAX9286_MSTLINKSEL_AUTO | priv->route_mask); 1176 max9286_write(priv, 0x0b, link_order[priv->route_mask]); 1177 max9286_write(priv, 0x69, (0xf & ~priv->route_mask)); 1178 1179 max9286_set_video_format(priv, &max9286_default_format); 1180 max9286_set_fsync_period(priv); 1181 1182 cfg = max9286_read(priv, 0x1c); 1183 if (cfg < 0) 1184 return cfg; 1185 1186 dev_dbg(&priv->client->dev, "power-up config: %s immunity, %u-bit bus\n", 1187 cfg & MAX9286_HIGHIMM(0) ? "high" : "legacy", 1188 cfg & MAX9286_BWS ? 32 : cfg & MAX9286_HIBW ? 27 : 24); 1189 1190 if (priv->bus_width) { 1191 cfg &= ~(MAX9286_HIBW | MAX9286_BWS); 1192 1193 if (priv->bus_width == 27) 1194 cfg |= MAX9286_HIBW; 1195 else if (priv->bus_width == 32) 1196 cfg |= MAX9286_BWS; 1197 1198 max9286_write(priv, 0x1c, cfg); 1199 } 1200 1201 /* 1202 * The overlap window seems to provide additional validation by tracking 1203 * the delay between vsync and frame sync, generating an error if the 1204 * delay is bigger than the programmed window, though it's not yet clear 1205 * what value should be set. 1206 * 1207 * As it's an optional value and can be disabled, we do so by setting 1208 * a 0 overlap value. 1209 */ 1210 max9286_write(priv, 0x63, 0); 1211 max9286_write(priv, 0x64, 0); 1212 1213 /* 1214 * Wait for 2ms to allow the link to resynchronize after the 1215 * configuration change. 1216 */ 1217 usleep_range(2000, 5000); 1218 1219 return 0; 1220 } 1221 1222 static int max9286_gpio_set(struct max9286_priv *priv, unsigned int offset, 1223 int value) 1224 { 1225 if (value) 1226 priv->gpio_state |= BIT(offset); 1227 else 1228 priv->gpio_state &= ~BIT(offset); 1229 1230 return max9286_write(priv, 0x0f, 1231 MAX9286_0X0F_RESERVED | priv->gpio_state); 1232 } 1233 1234 static void max9286_gpiochip_set(struct gpio_chip *chip, 1235 unsigned int offset, int value) 1236 { 1237 struct max9286_priv *priv = gpiochip_get_data(chip); 1238 1239 max9286_gpio_set(priv, offset, value); 1240 } 1241 1242 static int max9286_gpiochip_get(struct gpio_chip *chip, unsigned int offset) 1243 { 1244 struct max9286_priv *priv = gpiochip_get_data(chip); 1245 1246 return priv->gpio_state & BIT(offset); 1247 } 1248 1249 static int max9286_register_gpio(struct max9286_priv *priv) 1250 { 1251 struct device *dev = &priv->client->dev; 1252 struct gpio_chip *gpio = &priv->gpio; 1253 int ret; 1254 1255 /* Configure the GPIO */ 1256 gpio->label = dev_name(dev); 1257 gpio->parent = dev; 1258 gpio->owner = THIS_MODULE; 1259 gpio->ngpio = 2; 1260 gpio->base = -1; 1261 gpio->set = max9286_gpiochip_set; 1262 gpio->get = max9286_gpiochip_get; 1263 gpio->can_sleep = true; 1264 1265 ret = devm_gpiochip_add_data(dev, gpio, priv); 1266 if (ret) 1267 dev_err(dev, "Unable to create gpio_chip\n"); 1268 1269 return ret; 1270 } 1271 1272 static int max9286_parse_gpios(struct max9286_priv *priv) 1273 { 1274 struct device *dev = &priv->client->dev; 1275 int ret; 1276 1277 /* 1278 * Parse the "gpio-poc" vendor property. If the property is not 1279 * specified the camera power is controlled by a regulator. 1280 */ 1281 ret = of_property_read_u32_array(dev->of_node, "maxim,gpio-poc", 1282 priv->gpio_poc, 2); 1283 if (ret == -EINVAL) { 1284 /* 1285 * If gpio lines are not used for the camera power, register 1286 * a gpio controller for consumers. 1287 */ 1288 return max9286_register_gpio(priv); 1289 } 1290 1291 /* If the property is specified make sure it is well formed. */ 1292 if (ret || priv->gpio_poc[0] > 1 || 1293 (priv->gpio_poc[1] != GPIO_ACTIVE_HIGH && 1294 priv->gpio_poc[1] != GPIO_ACTIVE_LOW)) { 1295 dev_err(dev, "Invalid 'gpio-poc' property\n"); 1296 return -EINVAL; 1297 } 1298 1299 priv->use_gpio_poc = true; 1300 return 0; 1301 } 1302 1303 static int max9286_poc_power_on(struct max9286_priv *priv) 1304 { 1305 struct max9286_source *source; 1306 unsigned int enabled = 0; 1307 int ret; 1308 1309 /* Enable the global regulator if available. */ 1310 if (priv->regulator) 1311 return regulator_enable(priv->regulator); 1312 1313 if (priv->use_gpio_poc) 1314 return max9286_gpio_set(priv, priv->gpio_poc[0], 1315 !priv->gpio_poc[1]); 1316 1317 /* Otherwise use the per-port regulators. */ 1318 for_each_source(priv, source) { 1319 ret = regulator_enable(source->regulator); 1320 if (ret < 0) 1321 goto error; 1322 1323 enabled |= BIT(to_index(priv, source)); 1324 } 1325 1326 return 0; 1327 1328 error: 1329 for_each_source(priv, source) { 1330 if (enabled & BIT(to_index(priv, source))) 1331 regulator_disable(source->regulator); 1332 } 1333 1334 return ret; 1335 } 1336 1337 static int max9286_poc_power_off(struct max9286_priv *priv) 1338 { 1339 struct max9286_source *source; 1340 int ret = 0; 1341 1342 if (priv->regulator) 1343 return regulator_disable(priv->regulator); 1344 1345 if (priv->use_gpio_poc) 1346 return max9286_gpio_set(priv, priv->gpio_poc[0], 1347 priv->gpio_poc[1]); 1348 1349 for_each_source(priv, source) { 1350 int err; 1351 1352 err = regulator_disable(source->regulator); 1353 if (!ret) 1354 ret = err; 1355 } 1356 1357 return ret; 1358 } 1359 1360 static int max9286_poc_enable(struct max9286_priv *priv, bool enable) 1361 { 1362 int ret; 1363 1364 if (enable) 1365 ret = max9286_poc_power_on(priv); 1366 else 1367 ret = max9286_poc_power_off(priv); 1368 1369 if (ret < 0) 1370 dev_err(&priv->client->dev, "Unable to turn power %s\n", 1371 enable ? "on" : "off"); 1372 1373 return ret; 1374 } 1375 1376 static int max9286_init(struct max9286_priv *priv) 1377 { 1378 struct i2c_client *client = priv->client; 1379 int ret; 1380 1381 ret = max9286_poc_enable(priv, true); 1382 if (ret) 1383 return ret; 1384 1385 ret = max9286_setup(priv); 1386 if (ret) { 1387 dev_err(&client->dev, "Unable to setup max9286\n"); 1388 goto err_poc_disable; 1389 } 1390 1391 /* 1392 * Register all V4L2 interactions for the MAX9286 and notifiers for 1393 * any subdevices connected. 1394 */ 1395 ret = max9286_v4l2_register(priv); 1396 if (ret) { 1397 dev_err(&client->dev, "Failed to register with V4L2\n"); 1398 goto err_poc_disable; 1399 } 1400 1401 ret = max9286_i2c_mux_init(priv); 1402 if (ret) { 1403 dev_err(&client->dev, "Unable to initialize I2C multiplexer\n"); 1404 goto err_v4l2_register; 1405 } 1406 1407 /* Leave the mux channels disabled until they are selected. */ 1408 max9286_i2c_mux_close(priv); 1409 1410 return 0; 1411 1412 err_v4l2_register: 1413 max9286_v4l2_unregister(priv); 1414 err_poc_disable: 1415 max9286_poc_enable(priv, false); 1416 1417 return ret; 1418 } 1419 1420 static void max9286_cleanup_dt(struct max9286_priv *priv) 1421 { 1422 struct max9286_source *source; 1423 1424 for_each_source(priv, source) { 1425 fwnode_handle_put(source->fwnode); 1426 source->fwnode = NULL; 1427 } 1428 } 1429 1430 static int max9286_parse_dt(struct max9286_priv *priv) 1431 { 1432 struct device *dev = &priv->client->dev; 1433 struct device_node *i2c_mux; 1434 struct device_node *node = NULL; 1435 unsigned int i2c_mux_mask = 0; 1436 u32 reverse_channel_microvolt; 1437 u32 i2c_clk_freq = 105000; 1438 unsigned int i; 1439 1440 /* Balance the of_node_put() performed by of_find_node_by_name(). */ 1441 of_node_get(dev->of_node); 1442 i2c_mux = of_find_node_by_name(dev->of_node, "i2c-mux"); 1443 if (!i2c_mux) { 1444 dev_err(dev, "Failed to find i2c-mux node\n"); 1445 return -EINVAL; 1446 } 1447 1448 /* Identify which i2c-mux channels are enabled */ 1449 for_each_child_of_node(i2c_mux, node) { 1450 u32 id = 0; 1451 1452 of_property_read_u32(node, "reg", &id); 1453 if (id >= MAX9286_NUM_GMSL) 1454 continue; 1455 1456 if (!of_device_is_available(node)) { 1457 dev_dbg(dev, "Skipping disabled I2C bus port %u\n", id); 1458 continue; 1459 } 1460 1461 i2c_mux_mask |= BIT(id); 1462 } 1463 of_node_put(node); 1464 of_node_put(i2c_mux); 1465 1466 /* Parse the endpoints */ 1467 for_each_endpoint_of_node(dev->of_node, node) { 1468 struct max9286_source *source; 1469 struct of_endpoint ep; 1470 1471 of_graph_parse_endpoint(node, &ep); 1472 dev_dbg(dev, "Endpoint %pOF on port %d", 1473 ep.local_node, ep.port); 1474 1475 if (ep.port > MAX9286_NUM_GMSL) { 1476 dev_err(dev, "Invalid endpoint %s on port %d", 1477 of_node_full_name(ep.local_node), ep.port); 1478 continue; 1479 } 1480 1481 /* For the source endpoint just parse the bus configuration. */ 1482 if (ep.port == MAX9286_SRC_PAD) { 1483 struct v4l2_fwnode_endpoint vep = { 1484 .bus_type = V4L2_MBUS_CSI2_DPHY 1485 }; 1486 int ret; 1487 1488 ret = v4l2_fwnode_endpoint_parse( 1489 of_fwnode_handle(node), &vep); 1490 if (ret) { 1491 of_node_put(node); 1492 return ret; 1493 } 1494 1495 priv->csi2_data_lanes = 1496 vep.bus.mipi_csi2.num_data_lanes; 1497 1498 continue; 1499 } 1500 1501 /* Skip if the corresponding GMSL link is unavailable. */ 1502 if (!(i2c_mux_mask & BIT(ep.port))) 1503 continue; 1504 1505 if (priv->sources[ep.port].fwnode) { 1506 dev_err(dev, 1507 "Multiple port endpoints are not supported: %d", 1508 ep.port); 1509 1510 continue; 1511 } 1512 1513 source = &priv->sources[ep.port]; 1514 source->fwnode = fwnode_graph_get_remote_endpoint( 1515 of_fwnode_handle(node)); 1516 if (!source->fwnode) { 1517 dev_err(dev, 1518 "Endpoint %pOF has no remote endpoint connection\n", 1519 ep.local_node); 1520 1521 continue; 1522 } 1523 1524 priv->source_mask |= BIT(ep.port); 1525 priv->nsources++; 1526 } 1527 of_node_put(node); 1528 1529 of_property_read_u32(dev->of_node, "maxim,bus-width", &priv->bus_width); 1530 switch (priv->bus_width) { 1531 case 0: 1532 /* 1533 * The property isn't specified in the device tree, the driver 1534 * will keep the default value selected by the BWS pin. 1535 */ 1536 case 24: 1537 case 27: 1538 case 32: 1539 break; 1540 default: 1541 dev_err(dev, "Invalid %s value %u\n", "maxim,bus-width", 1542 priv->bus_width); 1543 return -EINVAL; 1544 } 1545 1546 of_property_read_u32(dev->of_node, "maxim,i2c-remote-bus-hz", 1547 &i2c_clk_freq); 1548 for (i = 0; i < ARRAY_SIZE(max9286_i2c_speeds); ++i) { 1549 const struct max9286_i2c_speed *speed = &max9286_i2c_speeds[i]; 1550 1551 if (speed->rate == i2c_clk_freq) { 1552 priv->i2c_mstbt = speed->mstbt; 1553 break; 1554 } 1555 } 1556 1557 if (i == ARRAY_SIZE(max9286_i2c_speeds)) { 1558 dev_err(dev, "Invalid %s value %u\n", "maxim,i2c-remote-bus-hz", 1559 i2c_clk_freq); 1560 return -EINVAL; 1561 } 1562 1563 /* 1564 * Parse the initial value of the reverse channel amplitude from 1565 * the firmware interface and convert it to millivolts. 1566 * 1567 * Default it to 170mV for backward compatibility with DTBs that do not 1568 * provide the property. 1569 */ 1570 if (of_property_read_u32(dev->of_node, 1571 "maxim,reverse-channel-microvolt", 1572 &reverse_channel_microvolt)) 1573 priv->init_rev_chan_mv = 170; 1574 else 1575 priv->init_rev_chan_mv = reverse_channel_microvolt / 1000U; 1576 1577 priv->route_mask = priv->source_mask; 1578 1579 return 0; 1580 } 1581 1582 static int max9286_get_poc_supplies(struct max9286_priv *priv) 1583 { 1584 struct device *dev = &priv->client->dev; 1585 struct max9286_source *source; 1586 int ret; 1587 1588 /* Start by getting the global regulator. */ 1589 priv->regulator = devm_regulator_get_optional(dev, "poc"); 1590 if (!IS_ERR(priv->regulator)) 1591 return 0; 1592 1593 if (PTR_ERR(priv->regulator) != -ENODEV) 1594 return dev_err_probe(dev, PTR_ERR(priv->regulator), 1595 "Unable to get PoC regulator\n"); 1596 1597 /* If there's no global regulator, get per-port regulators. */ 1598 dev_dbg(dev, 1599 "No global PoC regulator, looking for per-port regulators\n"); 1600 priv->regulator = NULL; 1601 1602 for_each_source(priv, source) { 1603 unsigned int index = to_index(priv, source); 1604 char name[10]; 1605 1606 snprintf(name, sizeof(name), "port%u-poc", index); 1607 source->regulator = devm_regulator_get(dev, name); 1608 if (IS_ERR(source->regulator)) { 1609 ret = PTR_ERR(source->regulator); 1610 dev_err_probe(dev, ret, 1611 "Unable to get port %u PoC regulator\n", 1612 index); 1613 return ret; 1614 } 1615 } 1616 1617 return 0; 1618 } 1619 1620 static int max9286_probe(struct i2c_client *client) 1621 { 1622 struct max9286_priv *priv; 1623 int ret; 1624 1625 priv = devm_kzalloc(&client->dev, sizeof(*priv), GFP_KERNEL); 1626 if (!priv) 1627 return -ENOMEM; 1628 1629 mutex_init(&priv->mutex); 1630 1631 priv->client = client; 1632 1633 /* GPIO values default to high */ 1634 priv->gpio_state = BIT(0) | BIT(1); 1635 1636 ret = max9286_parse_dt(priv); 1637 if (ret) 1638 goto err_cleanup_dt; 1639 1640 priv->gpiod_pwdn = devm_gpiod_get_optional(&client->dev, "enable", 1641 GPIOD_OUT_HIGH); 1642 if (IS_ERR(priv->gpiod_pwdn)) { 1643 ret = PTR_ERR(priv->gpiod_pwdn); 1644 goto err_cleanup_dt; 1645 } 1646 1647 gpiod_set_consumer_name(priv->gpiod_pwdn, "max9286-pwdn"); 1648 gpiod_set_value_cansleep(priv->gpiod_pwdn, 1); 1649 1650 /* Wait at least 4ms before the I2C lines latch to the address */ 1651 if (priv->gpiod_pwdn) 1652 usleep_range(4000, 5000); 1653 1654 /* 1655 * The MAX9286 starts by default with all ports enabled, we disable all 1656 * ports early to ensure that all channels are disabled if we error out 1657 * and keep the bus consistent. 1658 */ 1659 max9286_i2c_mux_close(priv); 1660 1661 /* 1662 * The MAX9286 initialises with auto-acknowledge enabled by default. 1663 * This can be invasive to other transactions on the same bus, so 1664 * disable it early. It will be enabled only as and when needed. 1665 */ 1666 max9286_configure_i2c(priv, false); 1667 1668 ret = max9286_parse_gpios(priv); 1669 if (ret) 1670 goto err_powerdown; 1671 1672 if (!priv->use_gpio_poc) { 1673 ret = max9286_get_poc_supplies(priv); 1674 if (ret) 1675 goto err_cleanup_dt; 1676 } 1677 1678 ret = max9286_init(priv); 1679 if (ret < 0) 1680 goto err_cleanup_dt; 1681 1682 return 0; 1683 1684 err_powerdown: 1685 gpiod_set_value_cansleep(priv->gpiod_pwdn, 0); 1686 err_cleanup_dt: 1687 max9286_cleanup_dt(priv); 1688 1689 return ret; 1690 } 1691 1692 static void max9286_remove(struct i2c_client *client) 1693 { 1694 struct max9286_priv *priv = sd_to_max9286(i2c_get_clientdata(client)); 1695 1696 i2c_mux_del_adapters(priv->mux); 1697 1698 max9286_v4l2_unregister(priv); 1699 1700 max9286_poc_enable(priv, false); 1701 1702 gpiod_set_value_cansleep(priv->gpiod_pwdn, 0); 1703 1704 max9286_cleanup_dt(priv); 1705 } 1706 1707 static const struct of_device_id max9286_dt_ids[] = { 1708 { .compatible = "maxim,max9286" }, 1709 {}, 1710 }; 1711 MODULE_DEVICE_TABLE(of, max9286_dt_ids); 1712 1713 static struct i2c_driver max9286_i2c_driver = { 1714 .driver = { 1715 .name = "max9286", 1716 .of_match_table = of_match_ptr(max9286_dt_ids), 1717 }, 1718 .probe_new = max9286_probe, 1719 .remove = max9286_remove, 1720 }; 1721 1722 module_i2c_driver(max9286_i2c_driver); 1723 1724 MODULE_DESCRIPTION("Maxim MAX9286 GMSL Deserializer Driver"); 1725 MODULE_AUTHOR("Jacopo Mondi, Kieran Bingham, Laurent Pinchart, Niklas Söderlund, Vladimir Barinov"); 1726 MODULE_LICENSE("GPL"); 1727