1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Maxim MAX9286 GMSL Deserializer Driver 4 * 5 * Copyright (C) 2017-2019 Jacopo Mondi 6 * Copyright (C) 2017-2019 Kieran Bingham 7 * Copyright (C) 2017-2019 Laurent Pinchart 8 * Copyright (C) 2017-2019 Niklas Söderlund 9 * Copyright (C) 2016 Renesas Electronics Corporation 10 * Copyright (C) 2015 Cogent Embedded, Inc. 11 */ 12 13 #include <linux/delay.h> 14 #include <linux/device.h> 15 #include <linux/fwnode.h> 16 #include <linux/gpio/consumer.h> 17 #include <linux/gpio/driver.h> 18 #include <linux/gpio/machine.h> 19 #include <linux/i2c.h> 20 #include <linux/i2c-mux.h> 21 #include <linux/module.h> 22 #include <linux/mutex.h> 23 #include <linux/of_graph.h> 24 #include <linux/regulator/consumer.h> 25 #include <linux/slab.h> 26 27 #include <media/v4l2-async.h> 28 #include <media/v4l2-ctrls.h> 29 #include <media/v4l2-device.h> 30 #include <media/v4l2-fwnode.h> 31 #include <media/v4l2-subdev.h> 32 33 /* Register 0x00 */ 34 #define MAX9286_MSTLINKSEL_AUTO (7 << 5) 35 #define MAX9286_MSTLINKSEL(n) ((n) << 5) 36 #define MAX9286_EN_VS_GEN BIT(4) 37 #define MAX9286_LINKEN(n) (1 << (n)) 38 /* Register 0x01 */ 39 #define MAX9286_FSYNCMODE_ECU (3 << 6) 40 #define MAX9286_FSYNCMODE_EXT (2 << 6) 41 #define MAX9286_FSYNCMODE_INT_OUT (1 << 6) 42 #define MAX9286_FSYNCMODE_INT_HIZ (0 << 6) 43 #define MAX9286_GPIEN BIT(5) 44 #define MAX9286_ENLMO_RSTFSYNC BIT(2) 45 #define MAX9286_FSYNCMETH_AUTO (2 << 0) 46 #define MAX9286_FSYNCMETH_SEMI_AUTO (1 << 0) 47 #define MAX9286_FSYNCMETH_MANUAL (0 << 0) 48 #define MAX9286_REG_FSYNC_PERIOD_L 0x06 49 #define MAX9286_REG_FSYNC_PERIOD_M 0x07 50 #define MAX9286_REG_FSYNC_PERIOD_H 0x08 51 /* Register 0x0a */ 52 #define MAX9286_FWDCCEN(n) (1 << ((n) + 4)) 53 #define MAX9286_REVCCEN(n) (1 << (n)) 54 /* Register 0x0c */ 55 #define MAX9286_HVEN BIT(7) 56 #define MAX9286_EDC_6BIT_HAMMING (2 << 5) 57 #define MAX9286_EDC_6BIT_CRC (1 << 5) 58 #define MAX9286_EDC_1BIT_PARITY (0 << 5) 59 #define MAX9286_DESEL BIT(4) 60 #define MAX9286_INVVS BIT(3) 61 #define MAX9286_INVHS BIT(2) 62 #define MAX9286_HVSRC_D0 (2 << 0) 63 #define MAX9286_HVSRC_D14 (1 << 0) 64 #define MAX9286_HVSRC_D18 (0 << 0) 65 /* Register 0x0f */ 66 #define MAX9286_0X0F_RESERVED BIT(3) 67 /* Register 0x12 */ 68 #define MAX9286_CSILANECNT(n) (((n) - 1) << 6) 69 #define MAX9286_CSIDBL BIT(5) 70 #define MAX9286_DBL BIT(4) 71 #define MAX9286_DATATYPE_USER_8BIT (11 << 0) 72 #define MAX9286_DATATYPE_USER_YUV_12BIT (10 << 0) 73 #define MAX9286_DATATYPE_USER_24BIT (9 << 0) 74 #define MAX9286_DATATYPE_RAW14 (8 << 0) 75 #define MAX9286_DATATYPE_RAW12 (7 << 0) 76 #define MAX9286_DATATYPE_RAW10 (6 << 0) 77 #define MAX9286_DATATYPE_RAW8 (5 << 0) 78 #define MAX9286_DATATYPE_YUV422_10BIT (4 << 0) 79 #define MAX9286_DATATYPE_YUV422_8BIT (3 << 0) 80 #define MAX9286_DATATYPE_RGB555 (2 << 0) 81 #define MAX9286_DATATYPE_RGB565 (1 << 0) 82 #define MAX9286_DATATYPE_RGB888 (0 << 0) 83 /* Register 0x15 */ 84 #define MAX9286_CSI_IMAGE_TYP BIT(7) 85 #define MAX9286_VC(n) ((n) << 5) 86 #define MAX9286_VCTYPE BIT(4) 87 #define MAX9286_CSIOUTEN BIT(3) 88 #define MAX9286_SWP_ENDIAN BIT(2) 89 #define MAX9286_EN_CCBSYB_CLK_STR BIT(1) 90 #define MAX9286_EN_GPI_CCBSYB BIT(0) 91 /* Register 0x1b */ 92 #define MAX9286_SWITCHIN(n) (1 << ((n) + 4)) 93 #define MAX9286_ENEQ(n) (1 << (n)) 94 /* Register 0x27 */ 95 #define MAX9286_LOCKED BIT(7) 96 /* Register 0x31 */ 97 #define MAX9286_FSYNC_LOCKED BIT(6) 98 /* Register 0x34 */ 99 #define MAX9286_I2CLOCACK BIT(7) 100 #define MAX9286_I2CSLVSH_1046NS_469NS (3 << 5) 101 #define MAX9286_I2CSLVSH_938NS_352NS (2 << 5) 102 #define MAX9286_I2CSLVSH_469NS_234NS (1 << 5) 103 #define MAX9286_I2CSLVSH_352NS_117NS (0 << 5) 104 #define MAX9286_I2CMSTBT_837KBPS (7 << 2) 105 #define MAX9286_I2CMSTBT_533KBPS (6 << 2) 106 #define MAX9286_I2CMSTBT_339KBPS (5 << 2) 107 #define MAX9286_I2CMSTBT_173KBPS (4 << 2) 108 #define MAX9286_I2CMSTBT_105KBPS (3 << 2) 109 #define MAX9286_I2CMSTBT_84KBPS (2 << 2) 110 #define MAX9286_I2CMSTBT_28KBPS (1 << 2) 111 #define MAX9286_I2CMSTBT_8KBPS (0 << 2) 112 #define MAX9286_I2CSLVTO_NONE (3 << 0) 113 #define MAX9286_I2CSLVTO_1024US (2 << 0) 114 #define MAX9286_I2CSLVTO_256US (1 << 0) 115 #define MAX9286_I2CSLVTO_64US (0 << 0) 116 /* Register 0x3b */ 117 #define MAX9286_REV_TRF(n) ((n) << 4) 118 #define MAX9286_REV_AMP(n) ((((n) - 30) / 10) << 1) /* in mV */ 119 #define MAX9286_REV_AMP_X BIT(0) 120 #define MAX9286_REV_AMP_HIGH 170 121 /* Register 0x3f */ 122 #define MAX9286_EN_REV_CFG BIT(6) 123 #define MAX9286_REV_FLEN(n) ((n) - 20) 124 /* Register 0x49 */ 125 #define MAX9286_VIDEO_DETECT_MASK 0x0f 126 /* Register 0x69 */ 127 #define MAX9286_LFLTBMONMASKED BIT(7) 128 #define MAX9286_LOCKMONMASKED BIT(6) 129 #define MAX9286_AUTOCOMBACKEN BIT(5) 130 #define MAX9286_AUTOMASKEN BIT(4) 131 #define MAX9286_MASKLINK(n) ((n) << 0) 132 133 /* 134 * The sink and source pads are created to match the OF graph port numbers so 135 * that their indexes can be used interchangeably. 136 */ 137 #define MAX9286_NUM_GMSL 4 138 #define MAX9286_N_SINKS 4 139 #define MAX9286_N_PADS 5 140 #define MAX9286_SRC_PAD 4 141 142 struct max9286_format_info { 143 u32 code; 144 u8 datatype; 145 }; 146 147 struct max9286_source { 148 struct v4l2_subdev *sd; 149 struct fwnode_handle *fwnode; 150 struct regulator *regulator; 151 }; 152 153 struct max9286_asd { 154 struct v4l2_async_subdev base; 155 struct max9286_source *source; 156 }; 157 158 static inline struct max9286_asd *to_max9286_asd(struct v4l2_async_subdev *asd) 159 { 160 return container_of(asd, struct max9286_asd, base); 161 } 162 163 struct max9286_priv { 164 struct i2c_client *client; 165 struct gpio_desc *gpiod_pwdn; 166 struct v4l2_subdev sd; 167 struct media_pad pads[MAX9286_N_PADS]; 168 struct regulator *regulator; 169 170 struct gpio_chip gpio; 171 u8 gpio_state; 172 173 struct i2c_mux_core *mux; 174 unsigned int mux_channel; 175 bool mux_open; 176 177 /* The initial reverse control channel amplitude. */ 178 u32 init_rev_chan_mv; 179 u32 rev_chan_mv; 180 181 bool use_gpio_poc; 182 u32 gpio_poc[2]; 183 184 struct v4l2_ctrl_handler ctrls; 185 struct v4l2_ctrl *pixelrate_ctrl; 186 unsigned int pixelrate; 187 188 struct v4l2_mbus_framefmt fmt[MAX9286_N_SINKS]; 189 struct v4l2_fract interval; 190 191 /* Protects controls and fmt structures */ 192 struct mutex mutex; 193 194 unsigned int nsources; 195 unsigned int source_mask; 196 unsigned int route_mask; 197 unsigned int bound_sources; 198 unsigned int csi2_data_lanes; 199 struct max9286_source sources[MAX9286_NUM_GMSL]; 200 struct v4l2_async_notifier notifier; 201 }; 202 203 static struct max9286_source *next_source(struct max9286_priv *priv, 204 struct max9286_source *source) 205 { 206 if (!source) 207 source = &priv->sources[0]; 208 else 209 source++; 210 211 for (; source < &priv->sources[MAX9286_NUM_GMSL]; source++) { 212 if (source->fwnode) 213 return source; 214 } 215 216 return NULL; 217 } 218 219 #define for_each_source(priv, source) \ 220 for ((source) = NULL; ((source) = next_source((priv), (source))); ) 221 222 #define to_index(priv, source) ((source) - &(priv)->sources[0]) 223 224 static inline struct max9286_priv *sd_to_max9286(struct v4l2_subdev *sd) 225 { 226 return container_of(sd, struct max9286_priv, sd); 227 } 228 229 static const struct max9286_format_info max9286_formats[] = { 230 { 231 .code = MEDIA_BUS_FMT_UYVY8_1X16, 232 .datatype = MAX9286_DATATYPE_YUV422_8BIT, 233 }, { 234 .code = MEDIA_BUS_FMT_VYUY8_1X16, 235 .datatype = MAX9286_DATATYPE_YUV422_8BIT, 236 }, { 237 .code = MEDIA_BUS_FMT_YUYV8_1X16, 238 .datatype = MAX9286_DATATYPE_YUV422_8BIT, 239 }, { 240 .code = MEDIA_BUS_FMT_YVYU8_1X16, 241 .datatype = MAX9286_DATATYPE_YUV422_8BIT, 242 }, { 243 .code = MEDIA_BUS_FMT_SBGGR12_1X12, 244 .datatype = MAX9286_DATATYPE_RAW12, 245 }, { 246 .code = MEDIA_BUS_FMT_SGBRG12_1X12, 247 .datatype = MAX9286_DATATYPE_RAW12, 248 }, { 249 .code = MEDIA_BUS_FMT_SGRBG12_1X12, 250 .datatype = MAX9286_DATATYPE_RAW12, 251 }, { 252 .code = MEDIA_BUS_FMT_SRGGB12_1X12, 253 .datatype = MAX9286_DATATYPE_RAW12, 254 }, 255 }; 256 257 /* ----------------------------------------------------------------------------- 258 * I2C IO 259 */ 260 261 static int max9286_read(struct max9286_priv *priv, u8 reg) 262 { 263 int ret; 264 265 ret = i2c_smbus_read_byte_data(priv->client, reg); 266 if (ret < 0) 267 dev_err(&priv->client->dev, 268 "%s: register 0x%02x read failed (%d)\n", 269 __func__, reg, ret); 270 271 return ret; 272 } 273 274 static int max9286_write(struct max9286_priv *priv, u8 reg, u8 val) 275 { 276 int ret; 277 278 ret = i2c_smbus_write_byte_data(priv->client, reg, val); 279 if (ret < 0) 280 dev_err(&priv->client->dev, 281 "%s: register 0x%02x write failed (%d)\n", 282 __func__, reg, ret); 283 284 return ret; 285 } 286 287 /* ----------------------------------------------------------------------------- 288 * I2C Multiplexer 289 */ 290 291 static void max9286_i2c_mux_configure(struct max9286_priv *priv, u8 conf) 292 { 293 max9286_write(priv, 0x0a, conf); 294 295 /* 296 * We must sleep after any change to the forward or reverse channel 297 * configuration. 298 */ 299 usleep_range(3000, 5000); 300 } 301 302 static void max9286_i2c_mux_open(struct max9286_priv *priv) 303 { 304 /* Open all channels on the MAX9286 */ 305 max9286_i2c_mux_configure(priv, 0xff); 306 307 priv->mux_open = true; 308 } 309 310 static void max9286_i2c_mux_close(struct max9286_priv *priv) 311 { 312 /* 313 * Ensure that both the forward and reverse channel are disabled on the 314 * mux, and that the channel ID is invalidated to ensure we reconfigure 315 * on the next max9286_i2c_mux_select() call. 316 */ 317 max9286_i2c_mux_configure(priv, 0x00); 318 319 priv->mux_open = false; 320 priv->mux_channel = -1; 321 } 322 323 static int max9286_i2c_mux_select(struct i2c_mux_core *muxc, u32 chan) 324 { 325 struct max9286_priv *priv = i2c_mux_priv(muxc); 326 327 /* Channel select is disabled when configured in the opened state. */ 328 if (priv->mux_open) 329 return 0; 330 331 if (priv->mux_channel == chan) 332 return 0; 333 334 priv->mux_channel = chan; 335 336 max9286_i2c_mux_configure(priv, MAX9286_FWDCCEN(chan) | 337 MAX9286_REVCCEN(chan)); 338 339 return 0; 340 } 341 342 static int max9286_i2c_mux_init(struct max9286_priv *priv) 343 { 344 struct max9286_source *source; 345 int ret; 346 347 if (!i2c_check_functionality(priv->client->adapter, 348 I2C_FUNC_SMBUS_WRITE_BYTE_DATA)) 349 return -ENODEV; 350 351 priv->mux = i2c_mux_alloc(priv->client->adapter, &priv->client->dev, 352 priv->nsources, 0, I2C_MUX_LOCKED, 353 max9286_i2c_mux_select, NULL); 354 if (!priv->mux) 355 return -ENOMEM; 356 357 priv->mux->priv = priv; 358 359 for_each_source(priv, source) { 360 unsigned int index = to_index(priv, source); 361 362 ret = i2c_mux_add_adapter(priv->mux, 0, index, 0); 363 if (ret < 0) 364 goto error; 365 } 366 367 return 0; 368 369 error: 370 i2c_mux_del_adapters(priv->mux); 371 return ret; 372 } 373 374 static void max9286_configure_i2c(struct max9286_priv *priv, bool localack) 375 { 376 u8 config = MAX9286_I2CSLVSH_469NS_234NS | MAX9286_I2CSLVTO_1024US | 377 MAX9286_I2CMSTBT_105KBPS; 378 379 if (localack) 380 config |= MAX9286_I2CLOCACK; 381 382 max9286_write(priv, 0x34, config); 383 usleep_range(3000, 5000); 384 } 385 386 static void max9286_reverse_channel_setup(struct max9286_priv *priv, 387 unsigned int chan_amplitude) 388 { 389 u8 chan_config; 390 391 if (priv->rev_chan_mv == chan_amplitude) 392 return; 393 394 priv->rev_chan_mv = chan_amplitude; 395 396 /* Reverse channel transmission time: default to 1. */ 397 chan_config = MAX9286_REV_TRF(1); 398 399 /* 400 * Reverse channel setup. 401 * 402 * - Enable custom reverse channel configuration (through register 0x3f) 403 * and set the first pulse length to 35 clock cycles. 404 * - Adjust reverse channel amplitude: values > 130 are programmed 405 * using the additional +100mV REV_AMP_X boost flag 406 */ 407 max9286_write(priv, 0x3f, MAX9286_EN_REV_CFG | MAX9286_REV_FLEN(35)); 408 409 if (chan_amplitude > 100) { 410 /* It is not possible to express values (100 < x < 130) */ 411 chan_amplitude = max(30U, chan_amplitude - 100); 412 chan_config |= MAX9286_REV_AMP_X; 413 } 414 max9286_write(priv, 0x3b, chan_config | MAX9286_REV_AMP(chan_amplitude)); 415 usleep_range(2000, 2500); 416 } 417 418 /* 419 * max9286_check_video_links() - Make sure video links are detected and locked 420 * 421 * Performs safety checks on video link status. Make sure they are detected 422 * and all enabled links are locked. 423 * 424 * Returns 0 for success, -EIO for errors. 425 */ 426 static int max9286_check_video_links(struct max9286_priv *priv) 427 { 428 unsigned int i; 429 int ret; 430 431 /* 432 * Make sure valid video links are detected. 433 * The delay is not characterized in de-serializer manual, wait up 434 * to 5 ms. 435 */ 436 for (i = 0; i < 10; i++) { 437 ret = max9286_read(priv, 0x49); 438 if (ret < 0) 439 return -EIO; 440 441 if ((ret & MAX9286_VIDEO_DETECT_MASK) == priv->source_mask) 442 break; 443 444 usleep_range(350, 500); 445 } 446 447 if (i == 10) { 448 dev_err(&priv->client->dev, 449 "Unable to detect video links: 0x%02x\n", ret); 450 return -EIO; 451 } 452 453 /* Make sure all enabled links are locked (4ms max). */ 454 for (i = 0; i < 10; i++) { 455 ret = max9286_read(priv, 0x27); 456 if (ret < 0) 457 return -EIO; 458 459 if (ret & MAX9286_LOCKED) 460 break; 461 462 usleep_range(350, 450); 463 } 464 465 if (i == 10) { 466 dev_err(&priv->client->dev, "Not all enabled links locked\n"); 467 return -EIO; 468 } 469 470 return 0; 471 } 472 473 /* 474 * max9286_check_config_link() - Detect and wait for configuration links 475 * 476 * Determine if the configuration channel is up and settled for a link. 477 * 478 * Returns 0 for success, -EIO for errors. 479 */ 480 static int max9286_check_config_link(struct max9286_priv *priv, 481 unsigned int source_mask) 482 { 483 unsigned int conflink_mask = (source_mask & 0x0f) << 4; 484 unsigned int i; 485 int ret; 486 487 /* 488 * Make sure requested configuration links are detected. 489 * The delay is not characterized in the chip manual: wait up 490 * to 5 milliseconds. 491 */ 492 for (i = 0; i < 10; i++) { 493 ret = max9286_read(priv, 0x49); 494 if (ret < 0) 495 return -EIO; 496 497 ret &= 0xf0; 498 if (ret == conflink_mask) 499 break; 500 501 usleep_range(350, 500); 502 } 503 504 if (ret != conflink_mask) { 505 dev_err(&priv->client->dev, 506 "Unable to detect configuration links: 0x%02x expected 0x%02x\n", 507 ret, conflink_mask); 508 return -EIO; 509 } 510 511 dev_info(&priv->client->dev, 512 "Successfully detected configuration links after %u loops: 0x%02x\n", 513 i, conflink_mask); 514 515 return 0; 516 } 517 518 static void max9286_set_video_format(struct max9286_priv *priv, 519 const struct v4l2_mbus_framefmt *format) 520 { 521 const struct max9286_format_info *info = NULL; 522 unsigned int i; 523 524 for (i = 0; i < ARRAY_SIZE(max9286_formats); ++i) { 525 if (max9286_formats[i].code == format->code) { 526 info = &max9286_formats[i]; 527 break; 528 } 529 } 530 531 if (WARN_ON(!info)) 532 return; 533 534 /* 535 * Video format setup: disable CSI output, set VC according to Link 536 * number, enable I2C clock stretching when CCBSY is low, enable CCBSY 537 * in external GPI-to-GPO mode. 538 */ 539 max9286_write(priv, 0x15, MAX9286_VCTYPE | MAX9286_EN_CCBSYB_CLK_STR | 540 MAX9286_EN_GPI_CCBSYB); 541 542 /* Enable CSI-2 Lane D0-D3 only, DBL mode. */ 543 max9286_write(priv, 0x12, MAX9286_CSIDBL | MAX9286_DBL | 544 MAX9286_CSILANECNT(priv->csi2_data_lanes) | 545 info->datatype); 546 547 /* Enable HS/VS encoding, use D14/15 for HS/VS, invert VS. */ 548 max9286_write(priv, 0x0c, MAX9286_HVEN | MAX9286_INVVS | 549 MAX9286_HVSRC_D14); 550 } 551 552 static void max9286_set_fsync_period(struct max9286_priv *priv) 553 { 554 u32 fsync; 555 556 if (!priv->interval.numerator || !priv->interval.denominator) { 557 /* 558 * Special case, a null interval enables automatic FRAMESYNC 559 * mode. FRAMESYNC is taken from the slowest link. 560 */ 561 max9286_write(priv, 0x01, MAX9286_FSYNCMODE_INT_HIZ | 562 MAX9286_FSYNCMETH_AUTO); 563 return; 564 } 565 566 /* 567 * Manual FRAMESYNC 568 * 569 * The FRAMESYNC generator is configured with a period expressed as a 570 * number of PCLK periods. 571 */ 572 fsync = div_u64((u64)priv->pixelrate * priv->interval.numerator, 573 priv->interval.denominator); 574 575 dev_dbg(&priv->client->dev, "fsync period %u (pclk %u)\n", fsync, 576 priv->pixelrate); 577 578 max9286_write(priv, 0x01, MAX9286_FSYNCMODE_INT_OUT | 579 MAX9286_FSYNCMETH_MANUAL); 580 581 max9286_write(priv, 0x06, (fsync >> 0) & 0xff); 582 max9286_write(priv, 0x07, (fsync >> 8) & 0xff); 583 max9286_write(priv, 0x08, (fsync >> 16) & 0xff); 584 } 585 586 /* ----------------------------------------------------------------------------- 587 * V4L2 Subdev 588 */ 589 590 static int max9286_set_pixelrate(struct max9286_priv *priv) 591 { 592 struct max9286_source *source = NULL; 593 u64 pixelrate = 0; 594 595 for_each_source(priv, source) { 596 struct v4l2_ctrl *ctrl; 597 u64 source_rate = 0; 598 599 /* Pixel rate is mandatory to be reported by sources. */ 600 ctrl = v4l2_ctrl_find(source->sd->ctrl_handler, 601 V4L2_CID_PIXEL_RATE); 602 if (!ctrl) { 603 pixelrate = 0; 604 break; 605 } 606 607 /* All source must report the same pixel rate. */ 608 source_rate = v4l2_ctrl_g_ctrl_int64(ctrl); 609 if (!pixelrate) { 610 pixelrate = source_rate; 611 } else if (pixelrate != source_rate) { 612 dev_err(&priv->client->dev, 613 "Unable to calculate pixel rate\n"); 614 return -EINVAL; 615 } 616 } 617 618 if (!pixelrate) { 619 dev_err(&priv->client->dev, 620 "No pixel rate control available in sources\n"); 621 return -EINVAL; 622 } 623 624 priv->pixelrate = pixelrate; 625 626 /* 627 * The CSI-2 transmitter pixel rate is the single source rate multiplied 628 * by the number of available sources. 629 */ 630 return v4l2_ctrl_s_ctrl_int64(priv->pixelrate_ctrl, 631 pixelrate * priv->nsources); 632 } 633 634 static int max9286_notify_bound(struct v4l2_async_notifier *notifier, 635 struct v4l2_subdev *subdev, 636 struct v4l2_async_subdev *asd) 637 { 638 struct max9286_priv *priv = sd_to_max9286(notifier->sd); 639 struct max9286_source *source = to_max9286_asd(asd)->source; 640 unsigned int index = to_index(priv, source); 641 unsigned int src_pad; 642 int ret; 643 644 ret = media_entity_get_fwnode_pad(&subdev->entity, 645 source->fwnode, 646 MEDIA_PAD_FL_SOURCE); 647 if (ret < 0) { 648 dev_err(&priv->client->dev, 649 "Failed to find pad for %s\n", subdev->name); 650 return ret; 651 } 652 653 priv->bound_sources |= BIT(index); 654 source->sd = subdev; 655 src_pad = ret; 656 657 ret = media_create_pad_link(&source->sd->entity, src_pad, 658 &priv->sd.entity, index, 659 MEDIA_LNK_FL_ENABLED | 660 MEDIA_LNK_FL_IMMUTABLE); 661 if (ret) { 662 dev_err(&priv->client->dev, 663 "Unable to link %s:%u -> %s:%u\n", 664 source->sd->name, src_pad, priv->sd.name, index); 665 return ret; 666 } 667 668 dev_dbg(&priv->client->dev, "Bound %s pad: %u on index %u\n", 669 subdev->name, src_pad, index); 670 671 /* 672 * As we register a subdev notifiers we won't get a .complete() callback 673 * here, so we have to use bound_sources to identify when all remote 674 * serializers have probed. 675 */ 676 if (priv->bound_sources != priv->source_mask) 677 return 0; 678 679 /* 680 * All enabled sources have probed and enabled their reverse control 681 * channels: 682 * 683 * - Increase the reverse channel amplitude to compensate for the 684 * remote ends high threshold 685 * - Verify all configuration links are properly detected 686 * - Disable auto-ack as communication on the control channel are now 687 * stable. 688 */ 689 max9286_reverse_channel_setup(priv, MAX9286_REV_AMP_HIGH); 690 max9286_check_config_link(priv, priv->source_mask); 691 max9286_configure_i2c(priv, false); 692 693 return max9286_set_pixelrate(priv); 694 } 695 696 static void max9286_notify_unbind(struct v4l2_async_notifier *notifier, 697 struct v4l2_subdev *subdev, 698 struct v4l2_async_subdev *asd) 699 { 700 struct max9286_priv *priv = sd_to_max9286(notifier->sd); 701 struct max9286_source *source = to_max9286_asd(asd)->source; 702 unsigned int index = to_index(priv, source); 703 704 source->sd = NULL; 705 priv->bound_sources &= ~BIT(index); 706 } 707 708 static const struct v4l2_async_notifier_operations max9286_notify_ops = { 709 .bound = max9286_notify_bound, 710 .unbind = max9286_notify_unbind, 711 }; 712 713 static int max9286_v4l2_notifier_register(struct max9286_priv *priv) 714 { 715 struct device *dev = &priv->client->dev; 716 struct max9286_source *source = NULL; 717 int ret; 718 719 if (!priv->nsources) 720 return 0; 721 722 v4l2_async_nf_init(&priv->notifier); 723 724 for_each_source(priv, source) { 725 unsigned int i = to_index(priv, source); 726 struct max9286_asd *mas; 727 728 mas = v4l2_async_nf_add_fwnode(&priv->notifier, source->fwnode, 729 struct max9286_asd); 730 if (IS_ERR(mas)) { 731 dev_err(dev, "Failed to add subdev for source %u: %ld", 732 i, PTR_ERR(mas)); 733 v4l2_async_nf_cleanup(&priv->notifier); 734 return PTR_ERR(mas); 735 } 736 737 mas->source = source; 738 } 739 740 priv->notifier.ops = &max9286_notify_ops; 741 742 ret = v4l2_async_subdev_nf_register(&priv->sd, &priv->notifier); 743 if (ret) { 744 dev_err(dev, "Failed to register subdev_notifier"); 745 v4l2_async_nf_cleanup(&priv->notifier); 746 return ret; 747 } 748 749 return 0; 750 } 751 752 static void max9286_v4l2_notifier_unregister(struct max9286_priv *priv) 753 { 754 if (!priv->nsources) 755 return; 756 757 v4l2_async_nf_unregister(&priv->notifier); 758 v4l2_async_nf_cleanup(&priv->notifier); 759 } 760 761 static int max9286_s_stream(struct v4l2_subdev *sd, int enable) 762 { 763 struct max9286_priv *priv = sd_to_max9286(sd); 764 struct max9286_source *source; 765 unsigned int i; 766 bool sync = false; 767 int ret; 768 769 if (enable) { 770 const struct v4l2_mbus_framefmt *format; 771 772 /* 773 * Get the format from the first used sink pad, as all sink 774 * formats must be identical. 775 */ 776 format = &priv->fmt[__ffs(priv->bound_sources)]; 777 778 max9286_set_video_format(priv, format); 779 max9286_set_fsync_period(priv); 780 781 /* 782 * The frame sync between cameras is transmitted across the 783 * reverse channel as GPIO. We must open all channels while 784 * streaming to allow this synchronisation signal to be shared. 785 */ 786 max9286_i2c_mux_open(priv); 787 788 /* Start all cameras. */ 789 for_each_source(priv, source) { 790 ret = v4l2_subdev_call(source->sd, video, s_stream, 1); 791 if (ret) 792 return ret; 793 } 794 795 ret = max9286_check_video_links(priv); 796 if (ret) 797 return ret; 798 799 /* 800 * Wait until frame synchronization is locked. 801 * 802 * Manual says frame sync locking should take ~6 VTS. 803 * From practical experience at least 8 are required. Give 804 * 12 complete frames time (~400ms at 30 fps) to achieve frame 805 * locking before returning error. 806 */ 807 for (i = 0; i < 40; i++) { 808 if (max9286_read(priv, 0x31) & MAX9286_FSYNC_LOCKED) { 809 sync = true; 810 break; 811 } 812 usleep_range(9000, 11000); 813 } 814 815 if (!sync) { 816 dev_err(&priv->client->dev, 817 "Failed to get frame synchronization\n"); 818 return -EXDEV; /* Invalid cross-device link */ 819 } 820 821 /* 822 * Configure the CSI-2 output to line interleaved mode (W x (N 823 * x H), as opposed to the (N x W) x H mode that outputs the 824 * images stitched side-by-side) and enable it. 825 */ 826 max9286_write(priv, 0x15, MAX9286_CSI_IMAGE_TYP | MAX9286_VCTYPE | 827 MAX9286_CSIOUTEN | MAX9286_EN_CCBSYB_CLK_STR | 828 MAX9286_EN_GPI_CCBSYB); 829 } else { 830 max9286_write(priv, 0x15, MAX9286_VCTYPE | 831 MAX9286_EN_CCBSYB_CLK_STR | 832 MAX9286_EN_GPI_CCBSYB); 833 834 /* Stop all cameras. */ 835 for_each_source(priv, source) 836 v4l2_subdev_call(source->sd, video, s_stream, 0); 837 838 max9286_i2c_mux_close(priv); 839 } 840 841 return 0; 842 } 843 844 static int max9286_g_frame_interval(struct v4l2_subdev *sd, 845 struct v4l2_subdev_frame_interval *interval) 846 { 847 struct max9286_priv *priv = sd_to_max9286(sd); 848 849 if (interval->pad != MAX9286_SRC_PAD) 850 return -EINVAL; 851 852 interval->interval = priv->interval; 853 854 return 0; 855 } 856 857 static int max9286_s_frame_interval(struct v4l2_subdev *sd, 858 struct v4l2_subdev_frame_interval *interval) 859 { 860 struct max9286_priv *priv = sd_to_max9286(sd); 861 862 if (interval->pad != MAX9286_SRC_PAD) 863 return -EINVAL; 864 865 priv->interval = interval->interval; 866 867 return 0; 868 } 869 870 static int max9286_enum_mbus_code(struct v4l2_subdev *sd, 871 struct v4l2_subdev_state *sd_state, 872 struct v4l2_subdev_mbus_code_enum *code) 873 { 874 if (code->pad || code->index > 0) 875 return -EINVAL; 876 877 code->code = MEDIA_BUS_FMT_UYVY8_1X16; 878 879 return 0; 880 } 881 882 static struct v4l2_mbus_framefmt * 883 max9286_get_pad_format(struct max9286_priv *priv, 884 struct v4l2_subdev_state *sd_state, 885 unsigned int pad, u32 which) 886 { 887 switch (which) { 888 case V4L2_SUBDEV_FORMAT_TRY: 889 return v4l2_subdev_get_try_format(&priv->sd, sd_state, pad); 890 case V4L2_SUBDEV_FORMAT_ACTIVE: 891 return &priv->fmt[pad]; 892 default: 893 return NULL; 894 } 895 } 896 897 static int max9286_set_fmt(struct v4l2_subdev *sd, 898 struct v4l2_subdev_state *sd_state, 899 struct v4l2_subdev_format *format) 900 { 901 struct max9286_priv *priv = sd_to_max9286(sd); 902 struct v4l2_mbus_framefmt *cfg_fmt; 903 unsigned int i; 904 905 if (format->pad == MAX9286_SRC_PAD) 906 return -EINVAL; 907 908 /* Validate the format. */ 909 for (i = 0; i < ARRAY_SIZE(max9286_formats); ++i) { 910 if (max9286_formats[i].code == format->format.code) 911 break; 912 } 913 914 if (i == ARRAY_SIZE(max9286_formats)) 915 format->format.code = max9286_formats[0].code; 916 917 cfg_fmt = max9286_get_pad_format(priv, sd_state, format->pad, 918 format->which); 919 if (!cfg_fmt) 920 return -EINVAL; 921 922 mutex_lock(&priv->mutex); 923 *cfg_fmt = format->format; 924 mutex_unlock(&priv->mutex); 925 926 return 0; 927 } 928 929 static int max9286_get_fmt(struct v4l2_subdev *sd, 930 struct v4l2_subdev_state *sd_state, 931 struct v4l2_subdev_format *format) 932 { 933 struct max9286_priv *priv = sd_to_max9286(sd); 934 struct v4l2_mbus_framefmt *cfg_fmt; 935 unsigned int pad = format->pad; 936 937 /* 938 * Multiplexed Stream Support: Support link validation by returning the 939 * format of the first bound link. All links must have the same format, 940 * as we do not support mixing and matching of cameras connected to the 941 * max9286. 942 */ 943 if (pad == MAX9286_SRC_PAD) 944 pad = __ffs(priv->bound_sources); 945 946 cfg_fmt = max9286_get_pad_format(priv, sd_state, pad, format->which); 947 if (!cfg_fmt) 948 return -EINVAL; 949 950 mutex_lock(&priv->mutex); 951 format->format = *cfg_fmt; 952 mutex_unlock(&priv->mutex); 953 954 return 0; 955 } 956 957 static const struct v4l2_subdev_video_ops max9286_video_ops = { 958 .s_stream = max9286_s_stream, 959 .g_frame_interval = max9286_g_frame_interval, 960 .s_frame_interval = max9286_s_frame_interval, 961 }; 962 963 static const struct v4l2_subdev_pad_ops max9286_pad_ops = { 964 .enum_mbus_code = max9286_enum_mbus_code, 965 .get_fmt = max9286_get_fmt, 966 .set_fmt = max9286_set_fmt, 967 }; 968 969 static const struct v4l2_subdev_ops max9286_subdev_ops = { 970 .video = &max9286_video_ops, 971 .pad = &max9286_pad_ops, 972 }; 973 974 static const struct v4l2_mbus_framefmt max9286_default_format = { 975 .width = 1280, 976 .height = 800, 977 .code = MEDIA_BUS_FMT_UYVY8_1X16, 978 .colorspace = V4L2_COLORSPACE_SRGB, 979 .field = V4L2_FIELD_NONE, 980 .ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT, 981 .quantization = V4L2_QUANTIZATION_DEFAULT, 982 .xfer_func = V4L2_XFER_FUNC_DEFAULT, 983 }; 984 985 static void max9286_init_format(struct v4l2_mbus_framefmt *fmt) 986 { 987 *fmt = max9286_default_format; 988 } 989 990 static int max9286_open(struct v4l2_subdev *subdev, struct v4l2_subdev_fh *fh) 991 { 992 struct v4l2_mbus_framefmt *format; 993 unsigned int i; 994 995 for (i = 0; i < MAX9286_N_SINKS; i++) { 996 format = v4l2_subdev_get_try_format(subdev, fh->state, i); 997 max9286_init_format(format); 998 } 999 1000 return 0; 1001 } 1002 1003 static const struct v4l2_subdev_internal_ops max9286_subdev_internal_ops = { 1004 .open = max9286_open, 1005 }; 1006 1007 static const struct media_entity_operations max9286_media_ops = { 1008 .link_validate = v4l2_subdev_link_validate 1009 }; 1010 1011 static int max9286_s_ctrl(struct v4l2_ctrl *ctrl) 1012 { 1013 switch (ctrl->id) { 1014 case V4L2_CID_PIXEL_RATE: 1015 return 0; 1016 default: 1017 return -EINVAL; 1018 } 1019 } 1020 1021 static const struct v4l2_ctrl_ops max9286_ctrl_ops = { 1022 .s_ctrl = max9286_s_ctrl, 1023 }; 1024 1025 static int max9286_v4l2_register(struct max9286_priv *priv) 1026 { 1027 struct device *dev = &priv->client->dev; 1028 struct fwnode_handle *ep; 1029 int ret; 1030 int i; 1031 1032 /* Register v4l2 async notifiers for connected Camera subdevices */ 1033 ret = max9286_v4l2_notifier_register(priv); 1034 if (ret) { 1035 dev_err(dev, "Unable to register V4L2 async notifiers\n"); 1036 return ret; 1037 } 1038 1039 /* Configure V4L2 for the MAX9286 itself */ 1040 1041 for (i = 0; i < MAX9286_N_SINKS; i++) 1042 max9286_init_format(&priv->fmt[i]); 1043 1044 v4l2_i2c_subdev_init(&priv->sd, priv->client, &max9286_subdev_ops); 1045 priv->sd.internal_ops = &max9286_subdev_internal_ops; 1046 priv->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; 1047 1048 v4l2_ctrl_handler_init(&priv->ctrls, 1); 1049 priv->pixelrate_ctrl = v4l2_ctrl_new_std(&priv->ctrls, 1050 &max9286_ctrl_ops, 1051 V4L2_CID_PIXEL_RATE, 1052 1, INT_MAX, 1, 50000000); 1053 1054 priv->sd.ctrl_handler = &priv->ctrls; 1055 ret = priv->ctrls.error; 1056 if (ret) 1057 goto err_async; 1058 1059 priv->sd.entity.function = MEDIA_ENT_F_VID_IF_BRIDGE; 1060 priv->sd.entity.ops = &max9286_media_ops; 1061 1062 priv->pads[MAX9286_SRC_PAD].flags = MEDIA_PAD_FL_SOURCE; 1063 for (i = 0; i < MAX9286_SRC_PAD; i++) 1064 priv->pads[i].flags = MEDIA_PAD_FL_SINK; 1065 ret = media_entity_pads_init(&priv->sd.entity, MAX9286_N_PADS, 1066 priv->pads); 1067 if (ret) 1068 goto err_async; 1069 1070 ep = fwnode_graph_get_endpoint_by_id(dev_fwnode(dev), MAX9286_SRC_PAD, 1071 0, 0); 1072 if (!ep) { 1073 dev_err(dev, "Unable to retrieve endpoint on \"port@4\"\n"); 1074 ret = -ENOENT; 1075 goto err_async; 1076 } 1077 priv->sd.fwnode = ep; 1078 1079 ret = v4l2_async_register_subdev(&priv->sd); 1080 if (ret < 0) { 1081 dev_err(dev, "Unable to register subdevice\n"); 1082 goto err_put_node; 1083 } 1084 1085 return 0; 1086 1087 err_put_node: 1088 fwnode_handle_put(ep); 1089 err_async: 1090 max9286_v4l2_notifier_unregister(priv); 1091 1092 return ret; 1093 } 1094 1095 static void max9286_v4l2_unregister(struct max9286_priv *priv) 1096 { 1097 fwnode_handle_put(priv->sd.fwnode); 1098 v4l2_async_unregister_subdev(&priv->sd); 1099 max9286_v4l2_notifier_unregister(priv); 1100 } 1101 1102 /* ----------------------------------------------------------------------------- 1103 * Probe/Remove 1104 */ 1105 1106 static int max9286_setup(struct max9286_priv *priv) 1107 { 1108 /* 1109 * Link ordering values for all enabled links combinations. Orders must 1110 * be assigned sequentially from 0 to the number of enabled links 1111 * without leaving any hole for disabled links. We thus assign orders to 1112 * enabled links first, and use the remaining order values for disabled 1113 * links are all links must have a different order value; 1114 */ 1115 static const u8 link_order[] = { 1116 (3 << 6) | (2 << 4) | (1 << 2) | (0 << 0), /* xxxx */ 1117 (3 << 6) | (2 << 4) | (1 << 2) | (0 << 0), /* xxx0 */ 1118 (3 << 6) | (2 << 4) | (0 << 2) | (1 << 0), /* xx0x */ 1119 (3 << 6) | (2 << 4) | (1 << 2) | (0 << 0), /* xx10 */ 1120 (3 << 6) | (0 << 4) | (2 << 2) | (1 << 0), /* x0xx */ 1121 (3 << 6) | (1 << 4) | (2 << 2) | (0 << 0), /* x1x0 */ 1122 (3 << 6) | (1 << 4) | (0 << 2) | (2 << 0), /* x10x */ 1123 (3 << 6) | (1 << 4) | (1 << 2) | (0 << 0), /* x210 */ 1124 (0 << 6) | (3 << 4) | (2 << 2) | (1 << 0), /* 0xxx */ 1125 (1 << 6) | (3 << 4) | (2 << 2) | (0 << 0), /* 1xx0 */ 1126 (1 << 6) | (3 << 4) | (0 << 2) | (2 << 0), /* 1x0x */ 1127 (2 << 6) | (3 << 4) | (1 << 2) | (0 << 0), /* 2x10 */ 1128 (1 << 6) | (0 << 4) | (3 << 2) | (2 << 0), /* 10xx */ 1129 (2 << 6) | (1 << 4) | (3 << 2) | (0 << 0), /* 21x0 */ 1130 (2 << 6) | (1 << 4) | (0 << 2) | (3 << 0), /* 210x */ 1131 (3 << 6) | (2 << 4) | (1 << 2) | (0 << 0), /* 3210 */ 1132 }; 1133 1134 /* 1135 * Set the I2C bus speed. 1136 * 1137 * Enable I2C Local Acknowledge during the probe sequences of the camera 1138 * only. This should be disabled after the mux is initialised. 1139 */ 1140 max9286_configure_i2c(priv, true); 1141 max9286_reverse_channel_setup(priv, priv->init_rev_chan_mv); 1142 1143 /* 1144 * Enable GMSL links, mask unused ones and autodetect link 1145 * used as CSI clock source. 1146 */ 1147 max9286_write(priv, 0x00, MAX9286_MSTLINKSEL_AUTO | priv->route_mask); 1148 max9286_write(priv, 0x0b, link_order[priv->route_mask]); 1149 max9286_write(priv, 0x69, (0xf & ~priv->route_mask)); 1150 1151 max9286_set_video_format(priv, &max9286_default_format); 1152 max9286_set_fsync_period(priv); 1153 1154 /* 1155 * The overlap window seems to provide additional validation by tracking 1156 * the delay between vsync and frame sync, generating an error if the 1157 * delay is bigger than the programmed window, though it's not yet clear 1158 * what value should be set. 1159 * 1160 * As it's an optional value and can be disabled, we do so by setting 1161 * a 0 overlap value. 1162 */ 1163 max9286_write(priv, 0x63, 0); 1164 max9286_write(priv, 0x64, 0); 1165 1166 /* 1167 * Wait for 2ms to allow the link to resynchronize after the 1168 * configuration change. 1169 */ 1170 usleep_range(2000, 5000); 1171 1172 return 0; 1173 } 1174 1175 static int max9286_gpio_set(struct max9286_priv *priv, unsigned int offset, 1176 int value) 1177 { 1178 if (value) 1179 priv->gpio_state |= BIT(offset); 1180 else 1181 priv->gpio_state &= ~BIT(offset); 1182 1183 return max9286_write(priv, 0x0f, 1184 MAX9286_0X0F_RESERVED | priv->gpio_state); 1185 } 1186 1187 static void max9286_gpiochip_set(struct gpio_chip *chip, 1188 unsigned int offset, int value) 1189 { 1190 struct max9286_priv *priv = gpiochip_get_data(chip); 1191 1192 max9286_gpio_set(priv, offset, value); 1193 } 1194 1195 static int max9286_gpiochip_get(struct gpio_chip *chip, unsigned int offset) 1196 { 1197 struct max9286_priv *priv = gpiochip_get_data(chip); 1198 1199 return priv->gpio_state & BIT(offset); 1200 } 1201 1202 static int max9286_register_gpio(struct max9286_priv *priv) 1203 { 1204 struct device *dev = &priv->client->dev; 1205 struct gpio_chip *gpio = &priv->gpio; 1206 int ret; 1207 1208 /* Configure the GPIO */ 1209 gpio->label = dev_name(dev); 1210 gpio->parent = dev; 1211 gpio->owner = THIS_MODULE; 1212 gpio->ngpio = 2; 1213 gpio->base = -1; 1214 gpio->set = max9286_gpiochip_set; 1215 gpio->get = max9286_gpiochip_get; 1216 gpio->can_sleep = true; 1217 1218 ret = devm_gpiochip_add_data(dev, gpio, priv); 1219 if (ret) 1220 dev_err(dev, "Unable to create gpio_chip\n"); 1221 1222 return ret; 1223 } 1224 1225 static int max9286_parse_gpios(struct max9286_priv *priv) 1226 { 1227 struct device *dev = &priv->client->dev; 1228 int ret; 1229 1230 /* 1231 * Parse the "gpio-poc" vendor property. If the property is not 1232 * specified the camera power is controlled by a regulator. 1233 */ 1234 ret = of_property_read_u32_array(dev->of_node, "maxim,gpio-poc", 1235 priv->gpio_poc, 2); 1236 if (ret == -EINVAL) { 1237 /* 1238 * If gpio lines are not used for the camera power, register 1239 * a gpio controller for consumers. 1240 */ 1241 return max9286_register_gpio(priv); 1242 } 1243 1244 /* If the property is specified make sure it is well formed. */ 1245 if (ret || priv->gpio_poc[0] > 1 || 1246 (priv->gpio_poc[1] != GPIO_ACTIVE_HIGH && 1247 priv->gpio_poc[1] != GPIO_ACTIVE_LOW)) { 1248 dev_err(dev, "Invalid 'gpio-poc' property\n"); 1249 return -EINVAL; 1250 } 1251 1252 priv->use_gpio_poc = true; 1253 return 0; 1254 } 1255 1256 static int max9286_poc_power_on(struct max9286_priv *priv) 1257 { 1258 struct max9286_source *source; 1259 unsigned int enabled = 0; 1260 int ret; 1261 1262 /* Enable the global regulator if available. */ 1263 if (priv->regulator) 1264 return regulator_enable(priv->regulator); 1265 1266 if (priv->use_gpio_poc) 1267 return max9286_gpio_set(priv, priv->gpio_poc[0], 1268 !priv->gpio_poc[1]); 1269 1270 /* Otherwise use the per-port regulators. */ 1271 for_each_source(priv, source) { 1272 ret = regulator_enable(source->regulator); 1273 if (ret < 0) 1274 goto error; 1275 1276 enabled |= BIT(to_index(priv, source)); 1277 } 1278 1279 return 0; 1280 1281 error: 1282 for_each_source(priv, source) { 1283 if (enabled & BIT(to_index(priv, source))) 1284 regulator_disable(source->regulator); 1285 } 1286 1287 return ret; 1288 } 1289 1290 static int max9286_poc_power_off(struct max9286_priv *priv) 1291 { 1292 struct max9286_source *source; 1293 int ret = 0; 1294 1295 if (priv->regulator) 1296 return regulator_disable(priv->regulator); 1297 1298 if (priv->use_gpio_poc) 1299 return max9286_gpio_set(priv, priv->gpio_poc[0], 1300 priv->gpio_poc[1]); 1301 1302 for_each_source(priv, source) { 1303 int err; 1304 1305 err = regulator_disable(source->regulator); 1306 if (!ret) 1307 ret = err; 1308 } 1309 1310 return ret; 1311 } 1312 1313 static int max9286_poc_enable(struct max9286_priv *priv, bool enable) 1314 { 1315 int ret; 1316 1317 if (enable) 1318 ret = max9286_poc_power_on(priv); 1319 else 1320 ret = max9286_poc_power_off(priv); 1321 1322 if (ret < 0) 1323 dev_err(&priv->client->dev, "Unable to turn power %s\n", 1324 enable ? "on" : "off"); 1325 1326 return ret; 1327 } 1328 1329 static int max9286_init(struct max9286_priv *priv) 1330 { 1331 struct i2c_client *client = priv->client; 1332 int ret; 1333 1334 ret = max9286_poc_enable(priv, true); 1335 if (ret) 1336 return ret; 1337 1338 ret = max9286_setup(priv); 1339 if (ret) { 1340 dev_err(&client->dev, "Unable to setup max9286\n"); 1341 goto err_poc_disable; 1342 } 1343 1344 /* 1345 * Register all V4L2 interactions for the MAX9286 and notifiers for 1346 * any subdevices connected. 1347 */ 1348 ret = max9286_v4l2_register(priv); 1349 if (ret) { 1350 dev_err(&client->dev, "Failed to register with V4L2\n"); 1351 goto err_poc_disable; 1352 } 1353 1354 ret = max9286_i2c_mux_init(priv); 1355 if (ret) { 1356 dev_err(&client->dev, "Unable to initialize I2C multiplexer\n"); 1357 goto err_v4l2_register; 1358 } 1359 1360 /* Leave the mux channels disabled until they are selected. */ 1361 max9286_i2c_mux_close(priv); 1362 1363 return 0; 1364 1365 err_v4l2_register: 1366 max9286_v4l2_unregister(priv); 1367 err_poc_disable: 1368 max9286_poc_enable(priv, false); 1369 1370 return ret; 1371 } 1372 1373 static void max9286_cleanup_dt(struct max9286_priv *priv) 1374 { 1375 struct max9286_source *source; 1376 1377 for_each_source(priv, source) { 1378 fwnode_handle_put(source->fwnode); 1379 source->fwnode = NULL; 1380 } 1381 } 1382 1383 static int max9286_parse_dt(struct max9286_priv *priv) 1384 { 1385 struct device *dev = &priv->client->dev; 1386 struct device_node *i2c_mux; 1387 struct device_node *node = NULL; 1388 unsigned int i2c_mux_mask = 0; 1389 u32 reverse_channel_microvolt; 1390 1391 /* Balance the of_node_put() performed by of_find_node_by_name(). */ 1392 of_node_get(dev->of_node); 1393 i2c_mux = of_find_node_by_name(dev->of_node, "i2c-mux"); 1394 if (!i2c_mux) { 1395 dev_err(dev, "Failed to find i2c-mux node\n"); 1396 return -EINVAL; 1397 } 1398 1399 /* Identify which i2c-mux channels are enabled */ 1400 for_each_child_of_node(i2c_mux, node) { 1401 u32 id = 0; 1402 1403 of_property_read_u32(node, "reg", &id); 1404 if (id >= MAX9286_NUM_GMSL) 1405 continue; 1406 1407 if (!of_device_is_available(node)) { 1408 dev_dbg(dev, "Skipping disabled I2C bus port %u\n", id); 1409 continue; 1410 } 1411 1412 i2c_mux_mask |= BIT(id); 1413 } 1414 of_node_put(node); 1415 of_node_put(i2c_mux); 1416 1417 /* Parse the endpoints */ 1418 for_each_endpoint_of_node(dev->of_node, node) { 1419 struct max9286_source *source; 1420 struct of_endpoint ep; 1421 1422 of_graph_parse_endpoint(node, &ep); 1423 dev_dbg(dev, "Endpoint %pOF on port %d", 1424 ep.local_node, ep.port); 1425 1426 if (ep.port > MAX9286_NUM_GMSL) { 1427 dev_err(dev, "Invalid endpoint %s on port %d", 1428 of_node_full_name(ep.local_node), ep.port); 1429 continue; 1430 } 1431 1432 /* For the source endpoint just parse the bus configuration. */ 1433 if (ep.port == MAX9286_SRC_PAD) { 1434 struct v4l2_fwnode_endpoint vep = { 1435 .bus_type = V4L2_MBUS_CSI2_DPHY 1436 }; 1437 int ret; 1438 1439 ret = v4l2_fwnode_endpoint_parse( 1440 of_fwnode_handle(node), &vep); 1441 if (ret) { 1442 of_node_put(node); 1443 return ret; 1444 } 1445 1446 priv->csi2_data_lanes = 1447 vep.bus.mipi_csi2.num_data_lanes; 1448 1449 continue; 1450 } 1451 1452 /* Skip if the corresponding GMSL link is unavailable. */ 1453 if (!(i2c_mux_mask & BIT(ep.port))) 1454 continue; 1455 1456 if (priv->sources[ep.port].fwnode) { 1457 dev_err(dev, 1458 "Multiple port endpoints are not supported: %d", 1459 ep.port); 1460 1461 continue; 1462 } 1463 1464 source = &priv->sources[ep.port]; 1465 source->fwnode = fwnode_graph_get_remote_endpoint( 1466 of_fwnode_handle(node)); 1467 if (!source->fwnode) { 1468 dev_err(dev, 1469 "Endpoint %pOF has no remote endpoint connection\n", 1470 ep.local_node); 1471 1472 continue; 1473 } 1474 1475 priv->source_mask |= BIT(ep.port); 1476 priv->nsources++; 1477 } 1478 of_node_put(node); 1479 1480 /* 1481 * Parse the initial value of the reverse channel amplitude from 1482 * the firmware interface and convert it to millivolts. 1483 * 1484 * Default it to 170mV for backward compatibility with DTBs that do not 1485 * provide the property. 1486 */ 1487 if (of_property_read_u32(dev->of_node, 1488 "maxim,reverse-channel-microvolt", 1489 &reverse_channel_microvolt)) 1490 priv->init_rev_chan_mv = 170; 1491 else 1492 priv->init_rev_chan_mv = reverse_channel_microvolt / 1000U; 1493 1494 priv->route_mask = priv->source_mask; 1495 1496 return 0; 1497 } 1498 1499 static int max9286_get_poc_supplies(struct max9286_priv *priv) 1500 { 1501 struct device *dev = &priv->client->dev; 1502 struct max9286_source *source; 1503 int ret; 1504 1505 /* Start by getting the global regulator. */ 1506 priv->regulator = devm_regulator_get_optional(dev, "poc"); 1507 if (!IS_ERR(priv->regulator)) 1508 return 0; 1509 1510 if (PTR_ERR(priv->regulator) != -ENODEV) 1511 return dev_err_probe(dev, PTR_ERR(priv->regulator), 1512 "Unable to get PoC regulator\n"); 1513 1514 /* If there's no global regulator, get per-port regulators. */ 1515 dev_dbg(dev, 1516 "No global PoC regulator, looking for per-port regulators\n"); 1517 priv->regulator = NULL; 1518 1519 for_each_source(priv, source) { 1520 unsigned int index = to_index(priv, source); 1521 char name[10]; 1522 1523 snprintf(name, sizeof(name), "port%u-poc", index); 1524 source->regulator = devm_regulator_get(dev, name); 1525 if (IS_ERR(source->regulator)) { 1526 ret = PTR_ERR(source->regulator); 1527 dev_err_probe(dev, ret, 1528 "Unable to get port %u PoC regulator\n", 1529 index); 1530 return ret; 1531 } 1532 } 1533 1534 return 0; 1535 } 1536 1537 static int max9286_probe(struct i2c_client *client) 1538 { 1539 struct max9286_priv *priv; 1540 int ret; 1541 1542 priv = devm_kzalloc(&client->dev, sizeof(*priv), GFP_KERNEL); 1543 if (!priv) 1544 return -ENOMEM; 1545 1546 mutex_init(&priv->mutex); 1547 1548 priv->client = client; 1549 1550 /* GPIO values default to high */ 1551 priv->gpio_state = BIT(0) | BIT(1); 1552 1553 priv->gpiod_pwdn = devm_gpiod_get_optional(&client->dev, "enable", 1554 GPIOD_OUT_HIGH); 1555 if (IS_ERR(priv->gpiod_pwdn)) 1556 return PTR_ERR(priv->gpiod_pwdn); 1557 1558 gpiod_set_consumer_name(priv->gpiod_pwdn, "max9286-pwdn"); 1559 gpiod_set_value_cansleep(priv->gpiod_pwdn, 1); 1560 1561 /* Wait at least 4ms before the I2C lines latch to the address */ 1562 if (priv->gpiod_pwdn) 1563 usleep_range(4000, 5000); 1564 1565 /* 1566 * The MAX9286 starts by default with all ports enabled, we disable all 1567 * ports early to ensure that all channels are disabled if we error out 1568 * and keep the bus consistent. 1569 */ 1570 max9286_i2c_mux_close(priv); 1571 1572 /* 1573 * The MAX9286 initialises with auto-acknowledge enabled by default. 1574 * This can be invasive to other transactions on the same bus, so 1575 * disable it early. It will be enabled only as and when needed. 1576 */ 1577 max9286_configure_i2c(priv, false); 1578 1579 ret = max9286_parse_gpios(priv); 1580 if (ret) 1581 goto err_powerdown; 1582 1583 ret = max9286_parse_dt(priv); 1584 if (ret) 1585 goto err_cleanup_dt; 1586 1587 if (!priv->use_gpio_poc) { 1588 ret = max9286_get_poc_supplies(priv); 1589 if (ret) 1590 goto err_cleanup_dt; 1591 } 1592 1593 ret = max9286_init(priv); 1594 if (ret < 0) 1595 goto err_cleanup_dt; 1596 1597 return 0; 1598 1599 err_cleanup_dt: 1600 max9286_cleanup_dt(priv); 1601 err_powerdown: 1602 gpiod_set_value_cansleep(priv->gpiod_pwdn, 0); 1603 1604 return ret; 1605 } 1606 1607 static void max9286_remove(struct i2c_client *client) 1608 { 1609 struct max9286_priv *priv = sd_to_max9286(i2c_get_clientdata(client)); 1610 1611 i2c_mux_del_adapters(priv->mux); 1612 1613 max9286_v4l2_unregister(priv); 1614 1615 max9286_poc_enable(priv, false); 1616 1617 gpiod_set_value_cansleep(priv->gpiod_pwdn, 0); 1618 1619 max9286_cleanup_dt(priv); 1620 } 1621 1622 static const struct of_device_id max9286_dt_ids[] = { 1623 { .compatible = "maxim,max9286" }, 1624 {}, 1625 }; 1626 MODULE_DEVICE_TABLE(of, max9286_dt_ids); 1627 1628 static struct i2c_driver max9286_i2c_driver = { 1629 .driver = { 1630 .name = "max9286", 1631 .of_match_table = of_match_ptr(max9286_dt_ids), 1632 }, 1633 .probe_new = max9286_probe, 1634 .remove = max9286_remove, 1635 }; 1636 1637 module_i2c_driver(max9286_i2c_driver); 1638 1639 MODULE_DESCRIPTION("Maxim MAX9286 GMSL Deserializer Driver"); 1640 MODULE_AUTHOR("Jacopo Mondi, Kieran Bingham, Laurent Pinchart, Niklas Söderlund, Vladimir Barinov"); 1641 MODULE_LICENSE("GPL"); 1642