1 /* 2 * Video Capture Driver (Video for Linux 1/2) 3 * for the Matrox Marvel G200,G400 and Rainbow Runner-G series 4 * 5 * This module is an interface to the KS0127 video decoder chip. 6 * 7 * Copyright (C) 1999 Ryan Drake <stiletto@mediaone.net> 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License 11 * as published by the Free Software Foundation; either version 2 12 * of the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 22 * 23 ***************************************************************************** 24 * 25 * Modified and extended by 26 * Mike Bernson <mike@mlb.org> 27 * Gerard v.d. Horst 28 * Leon van Stuivenberg <l.vanstuivenberg@chello.nl> 29 * Gernot Ziegler <gz@lysator.liu.se> 30 * 31 * Version History: 32 * V1.0 Ryan Drake Initial version by Ryan Drake 33 * V1.1 Gerard v.d. Horst Added some debugoutput, reset the video-standard 34 */ 35 36 #include <linux/init.h> 37 #include <linux/module.h> 38 #include <linux/delay.h> 39 #include <linux/errno.h> 40 #include <linux/kernel.h> 41 #include <linux/i2c.h> 42 #include <linux/videodev2.h> 43 #include <linux/slab.h> 44 #include <media/v4l2-device.h> 45 #include "ks0127.h" 46 47 MODULE_DESCRIPTION("KS0127 video decoder driver"); 48 MODULE_AUTHOR("Ryan Drake"); 49 MODULE_LICENSE("GPL"); 50 51 /* Addresses */ 52 #define I2C_KS0127_ADDON 0xD8 53 #define I2C_KS0127_ONBOARD 0xDA 54 55 56 /* ks0127 control registers */ 57 #define KS_STAT 0x00 58 #define KS_CMDA 0x01 59 #define KS_CMDB 0x02 60 #define KS_CMDC 0x03 61 #define KS_CMDD 0x04 62 #define KS_HAVB 0x05 63 #define KS_HAVE 0x06 64 #define KS_HS1B 0x07 65 #define KS_HS1E 0x08 66 #define KS_HS2B 0x09 67 #define KS_HS2E 0x0a 68 #define KS_AGC 0x0b 69 #define KS_HXTRA 0x0c 70 #define KS_CDEM 0x0d 71 #define KS_PORTAB 0x0e 72 #define KS_LUMA 0x0f 73 #define KS_CON 0x10 74 #define KS_BRT 0x11 75 #define KS_CHROMA 0x12 76 #define KS_CHROMB 0x13 77 #define KS_DEMOD 0x14 78 #define KS_SAT 0x15 79 #define KS_HUE 0x16 80 #define KS_VERTIA 0x17 81 #define KS_VERTIB 0x18 82 #define KS_VERTIC 0x19 83 #define KS_HSCLL 0x1a 84 #define KS_HSCLH 0x1b 85 #define KS_VSCLL 0x1c 86 #define KS_VSCLH 0x1d 87 #define KS_OFMTA 0x1e 88 #define KS_OFMTB 0x1f 89 #define KS_VBICTL 0x20 90 #define KS_CCDAT2 0x21 91 #define KS_CCDAT1 0x22 92 #define KS_VBIL30 0x23 93 #define KS_VBIL74 0x24 94 #define KS_VBIL118 0x25 95 #define KS_VBIL1512 0x26 96 #define KS_TTFRAM 0x27 97 #define KS_TESTA 0x28 98 #define KS_UVOFFH 0x29 99 #define KS_UVOFFL 0x2a 100 #define KS_UGAIN 0x2b 101 #define KS_VGAIN 0x2c 102 #define KS_VAVB 0x2d 103 #define KS_VAVE 0x2e 104 #define KS_CTRACK 0x2f 105 #define KS_POLCTL 0x30 106 #define KS_REFCOD 0x31 107 #define KS_INVALY 0x32 108 #define KS_INVALU 0x33 109 #define KS_INVALV 0x34 110 #define KS_UNUSEY 0x35 111 #define KS_UNUSEU 0x36 112 #define KS_UNUSEV 0x37 113 #define KS_USRSAV 0x38 114 #define KS_USREAV 0x39 115 #define KS_SHS1A 0x3a 116 #define KS_SHS1B 0x3b 117 #define KS_SHS1C 0x3c 118 #define KS_CMDE 0x3d 119 #define KS_VSDEL 0x3e 120 #define KS_CMDF 0x3f 121 #define KS_GAMMA0 0x40 122 #define KS_GAMMA1 0x41 123 #define KS_GAMMA2 0x42 124 #define KS_GAMMA3 0x43 125 #define KS_GAMMA4 0x44 126 #define KS_GAMMA5 0x45 127 #define KS_GAMMA6 0x46 128 #define KS_GAMMA7 0x47 129 #define KS_GAMMA8 0x48 130 #define KS_GAMMA9 0x49 131 #define KS_GAMMA10 0x4a 132 #define KS_GAMMA11 0x4b 133 #define KS_GAMMA12 0x4c 134 #define KS_GAMMA13 0x4d 135 #define KS_GAMMA14 0x4e 136 #define KS_GAMMA15 0x4f 137 #define KS_GAMMA16 0x50 138 #define KS_GAMMA17 0x51 139 #define KS_GAMMA18 0x52 140 #define KS_GAMMA19 0x53 141 #define KS_GAMMA20 0x54 142 #define KS_GAMMA21 0x55 143 #define KS_GAMMA22 0x56 144 #define KS_GAMMA23 0x57 145 #define KS_GAMMA24 0x58 146 #define KS_GAMMA25 0x59 147 #define KS_GAMMA26 0x5a 148 #define KS_GAMMA27 0x5b 149 #define KS_GAMMA28 0x5c 150 #define KS_GAMMA29 0x5d 151 #define KS_GAMMA30 0x5e 152 #define KS_GAMMA31 0x5f 153 #define KS_GAMMAD0 0x60 154 #define KS_GAMMAD1 0x61 155 #define KS_GAMMAD2 0x62 156 #define KS_GAMMAD3 0x63 157 #define KS_GAMMAD4 0x64 158 #define KS_GAMMAD5 0x65 159 #define KS_GAMMAD6 0x66 160 #define KS_GAMMAD7 0x67 161 #define KS_GAMMAD8 0x68 162 #define KS_GAMMAD9 0x69 163 #define KS_GAMMAD10 0x6a 164 #define KS_GAMMAD11 0x6b 165 #define KS_GAMMAD12 0x6c 166 #define KS_GAMMAD13 0x6d 167 #define KS_GAMMAD14 0x6e 168 #define KS_GAMMAD15 0x6f 169 #define KS_GAMMAD16 0x70 170 #define KS_GAMMAD17 0x71 171 #define KS_GAMMAD18 0x72 172 #define KS_GAMMAD19 0x73 173 #define KS_GAMMAD20 0x74 174 #define KS_GAMMAD21 0x75 175 #define KS_GAMMAD22 0x76 176 #define KS_GAMMAD23 0x77 177 #define KS_GAMMAD24 0x78 178 #define KS_GAMMAD25 0x79 179 #define KS_GAMMAD26 0x7a 180 #define KS_GAMMAD27 0x7b 181 #define KS_GAMMAD28 0x7c 182 #define KS_GAMMAD29 0x7d 183 #define KS_GAMMAD30 0x7e 184 #define KS_GAMMAD31 0x7f 185 186 187 /**************************************************************************** 188 * mga_dev : represents one ks0127 chip. 189 ****************************************************************************/ 190 191 struct adjust { 192 int contrast; 193 int bright; 194 int hue; 195 int ugain; 196 int vgain; 197 }; 198 199 struct ks0127 { 200 struct v4l2_subdev sd; 201 v4l2_std_id norm; 202 u8 regs[256]; 203 }; 204 205 static inline struct ks0127 *to_ks0127(struct v4l2_subdev *sd) 206 { 207 return container_of(sd, struct ks0127, sd); 208 } 209 210 211 static int debug; /* insmod parameter */ 212 213 module_param(debug, int, 0); 214 MODULE_PARM_DESC(debug, "Debug output"); 215 216 static u8 reg_defaults[64]; 217 218 static void init_reg_defaults(void) 219 { 220 static int initialized; 221 u8 *table = reg_defaults; 222 223 if (initialized) 224 return; 225 initialized = 1; 226 227 table[KS_CMDA] = 0x2c; /* VSE=0, CCIR 601, autodetect standard */ 228 table[KS_CMDB] = 0x12; /* VALIGN=0, AGC control and input */ 229 table[KS_CMDC] = 0x00; /* Test options */ 230 /* clock & input select, write 1 to PORTA */ 231 table[KS_CMDD] = 0x01; 232 table[KS_HAVB] = 0x00; /* HAV Start Control */ 233 table[KS_HAVE] = 0x00; /* HAV End Control */ 234 table[KS_HS1B] = 0x10; /* HS1 Start Control */ 235 table[KS_HS1E] = 0x00; /* HS1 End Control */ 236 table[KS_HS2B] = 0x00; /* HS2 Start Control */ 237 table[KS_HS2E] = 0x00; /* HS2 End Control */ 238 table[KS_AGC] = 0x53; /* Manual setting for AGC */ 239 table[KS_HXTRA] = 0x00; /* Extra Bits for HAV and HS1/2 */ 240 table[KS_CDEM] = 0x00; /* Chroma Demodulation Control */ 241 table[KS_PORTAB] = 0x0f; /* port B is input, port A output GPPORT */ 242 table[KS_LUMA] = 0x01; /* Luma control */ 243 table[KS_CON] = 0x00; /* Contrast Control */ 244 table[KS_BRT] = 0x00; /* Brightness Control */ 245 table[KS_CHROMA] = 0x2a; /* Chroma control A */ 246 table[KS_CHROMB] = 0x90; /* Chroma control B */ 247 table[KS_DEMOD] = 0x00; /* Chroma Demodulation Control & Status */ 248 table[KS_SAT] = 0x00; /* Color Saturation Control*/ 249 table[KS_HUE] = 0x00; /* Hue Control */ 250 table[KS_VERTIA] = 0x00; /* Vertical Processing Control A */ 251 /* Vertical Processing Control B, luma 1 line delayed */ 252 table[KS_VERTIB] = 0x12; 253 table[KS_VERTIC] = 0x0b; /* Vertical Processing Control C */ 254 table[KS_HSCLL] = 0x00; /* Horizontal Scaling Ratio Low */ 255 table[KS_HSCLH] = 0x00; /* Horizontal Scaling Ratio High */ 256 table[KS_VSCLL] = 0x00; /* Vertical Scaling Ratio Low */ 257 table[KS_VSCLH] = 0x00; /* Vertical Scaling Ratio High */ 258 /* 16 bit YCbCr 4:2:2 output; I can't make the bt866 like 8 bit /Sam */ 259 table[KS_OFMTA] = 0x30; 260 table[KS_OFMTB] = 0x00; /* Output Control B */ 261 /* VBI Decoder Control; 4bit fmt: avoid Y overflow */ 262 table[KS_VBICTL] = 0x5d; 263 table[KS_CCDAT2] = 0x00; /* Read Only register */ 264 table[KS_CCDAT1] = 0x00; /* Read Only register */ 265 table[KS_VBIL30] = 0xa8; /* VBI data decoding options */ 266 table[KS_VBIL74] = 0xaa; /* VBI data decoding options */ 267 table[KS_VBIL118] = 0x2a; /* VBI data decoding options */ 268 table[KS_VBIL1512] = 0x00; /* VBI data decoding options */ 269 table[KS_TTFRAM] = 0x00; /* Teletext frame alignment pattern */ 270 table[KS_TESTA] = 0x00; /* test register, shouldn't be written */ 271 table[KS_UVOFFH] = 0x00; /* UV Offset Adjustment High */ 272 table[KS_UVOFFL] = 0x00; /* UV Offset Adjustment Low */ 273 table[KS_UGAIN] = 0x00; /* U Component Gain Adjustment */ 274 table[KS_VGAIN] = 0x00; /* V Component Gain Adjustment */ 275 table[KS_VAVB] = 0x07; /* VAV Begin */ 276 table[KS_VAVE] = 0x00; /* VAV End */ 277 table[KS_CTRACK] = 0x00; /* Chroma Tracking Control */ 278 table[KS_POLCTL] = 0x41; /* Timing Signal Polarity Control */ 279 table[KS_REFCOD] = 0x80; /* Reference Code Insertion Control */ 280 table[KS_INVALY] = 0x10; /* Invalid Y Code */ 281 table[KS_INVALU] = 0x80; /* Invalid U Code */ 282 table[KS_INVALV] = 0x80; /* Invalid V Code */ 283 table[KS_UNUSEY] = 0x10; /* Unused Y Code */ 284 table[KS_UNUSEU] = 0x80; /* Unused U Code */ 285 table[KS_UNUSEV] = 0x80; /* Unused V Code */ 286 table[KS_USRSAV] = 0x00; /* reserved */ 287 table[KS_USREAV] = 0x00; /* reserved */ 288 table[KS_SHS1A] = 0x00; /* User Defined SHS1 A */ 289 /* User Defined SHS1 B, ALT656=1 on 0127B */ 290 table[KS_SHS1B] = 0x80; 291 table[KS_SHS1C] = 0x00; /* User Defined SHS1 C */ 292 table[KS_CMDE] = 0x00; /* Command Register E */ 293 table[KS_VSDEL] = 0x00; /* VS Delay Control */ 294 /* Command Register F, update -immediately- */ 295 /* (there might come no vsync)*/ 296 table[KS_CMDF] = 0x02; 297 } 298 299 300 /* We need to manually read because of a bug in the KS0127 chip. 301 * 302 * An explanation from kayork@mail.utexas.edu: 303 * 304 * During I2C reads, the KS0127 only samples for a stop condition 305 * during the place where the acknowledge bit should be. Any standard 306 * I2C implementation (correctly) throws in another clock transition 307 * at the 9th bit, and the KS0127 will not recognize the stop condition 308 * and will continue to clock out data. 309 * 310 * So we have to do the read ourself. Big deal. 311 * workaround in i2c-algo-bit 312 */ 313 314 315 static u8 ks0127_read(struct v4l2_subdev *sd, u8 reg) 316 { 317 struct i2c_client *client = v4l2_get_subdevdata(sd); 318 char val = 0; 319 struct i2c_msg msgs[] = { 320 { 321 .addr = client->addr, 322 .len = sizeof(reg), 323 .buf = ® 324 }, 325 { 326 .addr = client->addr, 327 .flags = I2C_M_RD | I2C_M_NO_RD_ACK, 328 .len = sizeof(val), 329 .buf = &val 330 } 331 }; 332 int ret; 333 334 ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs)); 335 if (ret != ARRAY_SIZE(msgs)) 336 v4l2_dbg(1, debug, sd, "read error\n"); 337 338 return val; 339 } 340 341 342 static void ks0127_write(struct v4l2_subdev *sd, u8 reg, u8 val) 343 { 344 struct i2c_client *client = v4l2_get_subdevdata(sd); 345 struct ks0127 *ks = to_ks0127(sd); 346 char msg[] = { reg, val }; 347 348 if (i2c_master_send(client, msg, sizeof(msg)) != sizeof(msg)) 349 v4l2_dbg(1, debug, sd, "write error\n"); 350 351 ks->regs[reg] = val; 352 } 353 354 355 /* generic bit-twiddling */ 356 static void ks0127_and_or(struct v4l2_subdev *sd, u8 reg, u8 and_v, u8 or_v) 357 { 358 struct ks0127 *ks = to_ks0127(sd); 359 360 u8 val = ks->regs[reg]; 361 val = (val & and_v) | or_v; 362 ks0127_write(sd, reg, val); 363 } 364 365 366 367 /**************************************************************************** 368 * ks0127 private api 369 ****************************************************************************/ 370 static void ks0127_init(struct v4l2_subdev *sd) 371 { 372 u8 *table = reg_defaults; 373 int i; 374 375 v4l2_dbg(1, debug, sd, "reset\n"); 376 msleep(1); 377 378 /* initialize all registers to known values */ 379 /* (except STAT, 0x21, 0x22, TEST and 0x38,0x39) */ 380 381 for (i = 1; i < 33; i++) 382 ks0127_write(sd, i, table[i]); 383 384 for (i = 35; i < 40; i++) 385 ks0127_write(sd, i, table[i]); 386 387 for (i = 41; i < 56; i++) 388 ks0127_write(sd, i, table[i]); 389 390 for (i = 58; i < 64; i++) 391 ks0127_write(sd, i, table[i]); 392 393 394 if ((ks0127_read(sd, KS_STAT) & 0x80) == 0) { 395 v4l2_dbg(1, debug, sd, "ks0122s found\n"); 396 return; 397 } 398 399 switch (ks0127_read(sd, KS_CMDE) & 0x0f) { 400 case 0: 401 v4l2_dbg(1, debug, sd, "ks0127 found\n"); 402 break; 403 404 case 9: 405 v4l2_dbg(1, debug, sd, "ks0127B Revision A found\n"); 406 break; 407 408 default: 409 v4l2_dbg(1, debug, sd, "unknown revision\n"); 410 break; 411 } 412 } 413 414 static int ks0127_s_routing(struct v4l2_subdev *sd, 415 u32 input, u32 output, u32 config) 416 { 417 struct ks0127 *ks = to_ks0127(sd); 418 419 switch (input) { 420 case KS_INPUT_COMPOSITE_1: 421 case KS_INPUT_COMPOSITE_2: 422 case KS_INPUT_COMPOSITE_3: 423 case KS_INPUT_COMPOSITE_4: 424 case KS_INPUT_COMPOSITE_5: 425 case KS_INPUT_COMPOSITE_6: 426 v4l2_dbg(1, debug, sd, 427 "s_routing %d: Composite\n", input); 428 /* autodetect 50/60 Hz */ 429 ks0127_and_or(sd, KS_CMDA, 0xfc, 0x00); 430 /* VSE=0 */ 431 ks0127_and_or(sd, KS_CMDA, ~0x40, 0x00); 432 /* set input line */ 433 ks0127_and_or(sd, KS_CMDB, 0xb0, input); 434 /* non-freerunning mode */ 435 ks0127_and_or(sd, KS_CMDC, 0x70, 0x0a); 436 /* analog input */ 437 ks0127_and_or(sd, KS_CMDD, 0x03, 0x00); 438 /* enable chroma demodulation */ 439 ks0127_and_or(sd, KS_CTRACK, 0xcf, 0x00); 440 /* chroma trap, HYBWR=1 */ 441 ks0127_and_or(sd, KS_LUMA, 0x00, 442 (reg_defaults[KS_LUMA])|0x0c); 443 /* scaler fullbw, luma comb off */ 444 ks0127_and_or(sd, KS_VERTIA, 0x08, 0x81); 445 /* manual chroma comb .25 .5 .25 */ 446 ks0127_and_or(sd, KS_VERTIC, 0x0f, 0x90); 447 448 /* chroma path delay */ 449 ks0127_and_or(sd, KS_CHROMB, 0x0f, 0x90); 450 451 ks0127_write(sd, KS_UGAIN, reg_defaults[KS_UGAIN]); 452 ks0127_write(sd, KS_VGAIN, reg_defaults[KS_VGAIN]); 453 ks0127_write(sd, KS_UVOFFH, reg_defaults[KS_UVOFFH]); 454 ks0127_write(sd, KS_UVOFFL, reg_defaults[KS_UVOFFL]); 455 break; 456 457 case KS_INPUT_SVIDEO_1: 458 case KS_INPUT_SVIDEO_2: 459 case KS_INPUT_SVIDEO_3: 460 v4l2_dbg(1, debug, sd, 461 "s_routing %d: S-Video\n", input); 462 /* autodetect 50/60 Hz */ 463 ks0127_and_or(sd, KS_CMDA, 0xfc, 0x00); 464 /* VSE=0 */ 465 ks0127_and_or(sd, KS_CMDA, ~0x40, 0x00); 466 /* set input line */ 467 ks0127_and_or(sd, KS_CMDB, 0xb0, input); 468 /* non-freerunning mode */ 469 ks0127_and_or(sd, KS_CMDC, 0x70, 0x0a); 470 /* analog input */ 471 ks0127_and_or(sd, KS_CMDD, 0x03, 0x00); 472 /* enable chroma demodulation */ 473 ks0127_and_or(sd, KS_CTRACK, 0xcf, 0x00); 474 ks0127_and_or(sd, KS_LUMA, 0x00, 475 reg_defaults[KS_LUMA]); 476 /* disable luma comb */ 477 ks0127_and_or(sd, KS_VERTIA, 0x08, 478 (reg_defaults[KS_VERTIA]&0xf0)|0x01); 479 ks0127_and_or(sd, KS_VERTIC, 0x0f, 480 reg_defaults[KS_VERTIC]&0xf0); 481 482 ks0127_and_or(sd, KS_CHROMB, 0x0f, 483 reg_defaults[KS_CHROMB]&0xf0); 484 485 ks0127_write(sd, KS_UGAIN, reg_defaults[KS_UGAIN]); 486 ks0127_write(sd, KS_VGAIN, reg_defaults[KS_VGAIN]); 487 ks0127_write(sd, KS_UVOFFH, reg_defaults[KS_UVOFFH]); 488 ks0127_write(sd, KS_UVOFFL, reg_defaults[KS_UVOFFL]); 489 break; 490 491 case KS_INPUT_YUV656: 492 v4l2_dbg(1, debug, sd, "s_routing 15: YUV656\n"); 493 if (ks->norm & V4L2_STD_525_60) 494 /* force 60 Hz */ 495 ks0127_and_or(sd, KS_CMDA, 0xfc, 0x03); 496 else 497 /* force 50 Hz */ 498 ks0127_and_or(sd, KS_CMDA, 0xfc, 0x02); 499 500 ks0127_and_or(sd, KS_CMDA, 0xff, 0x40); /* VSE=1 */ 501 /* set input line and VALIGN */ 502 ks0127_and_or(sd, KS_CMDB, 0xb0, (input | 0x40)); 503 /* freerunning mode, */ 504 /* TSTGEN = 1 TSTGFR=11 TSTGPH=0 TSTGPK=0 VMEM=1*/ 505 ks0127_and_or(sd, KS_CMDC, 0x70, 0x87); 506 /* digital input, SYNDIR = 0 INPSL=01 CLKDIR=0 EAV=0 */ 507 ks0127_and_or(sd, KS_CMDD, 0x03, 0x08); 508 /* disable chroma demodulation */ 509 ks0127_and_or(sd, KS_CTRACK, 0xcf, 0x30); 510 /* HYPK =01 CTRAP = 0 HYBWR=0 PED=1 RGBH=1 UNIT=1 */ 511 ks0127_and_or(sd, KS_LUMA, 0x00, 0x71); 512 ks0127_and_or(sd, KS_VERTIC, 0x0f, 513 reg_defaults[KS_VERTIC]&0xf0); 514 515 /* scaler fullbw, luma comb off */ 516 ks0127_and_or(sd, KS_VERTIA, 0x08, 0x81); 517 518 ks0127_and_or(sd, KS_CHROMB, 0x0f, 519 reg_defaults[KS_CHROMB]&0xf0); 520 521 ks0127_and_or(sd, KS_CON, 0x00, 0x00); 522 ks0127_and_or(sd, KS_BRT, 0x00, 32); /* spec: 34 */ 523 /* spec: 229 (e5) */ 524 ks0127_and_or(sd, KS_SAT, 0x00, 0xe8); 525 ks0127_and_or(sd, KS_HUE, 0x00, 0); 526 527 ks0127_and_or(sd, KS_UGAIN, 0x00, 238); 528 ks0127_and_or(sd, KS_VGAIN, 0x00, 0x00); 529 530 /*UOFF:0x30, VOFF:0x30, TSTCGN=1 */ 531 ks0127_and_or(sd, KS_UVOFFH, 0x00, 0x4f); 532 ks0127_and_or(sd, KS_UVOFFL, 0x00, 0x00); 533 break; 534 535 default: 536 v4l2_dbg(1, debug, sd, 537 "s_routing: Unknown input %d\n", input); 538 break; 539 } 540 541 /* hack: CDMLPF sometimes spontaneously switches on; */ 542 /* force back off */ 543 ks0127_write(sd, KS_DEMOD, reg_defaults[KS_DEMOD]); 544 return 0; 545 } 546 547 static int ks0127_s_std(struct v4l2_subdev *sd, v4l2_std_id std) 548 { 549 struct ks0127 *ks = to_ks0127(sd); 550 551 /* Set to automatic SECAM/Fsc mode */ 552 ks0127_and_or(sd, KS_DEMOD, 0xf0, 0x00); 553 554 ks->norm = std; 555 if (std & V4L2_STD_NTSC) { 556 v4l2_dbg(1, debug, sd, 557 "s_std: NTSC_M\n"); 558 ks0127_and_or(sd, KS_CHROMA, 0x9f, 0x20); 559 } else if (std & V4L2_STD_PAL_N) { 560 v4l2_dbg(1, debug, sd, 561 "s_std: NTSC_N (fixme)\n"); 562 ks0127_and_or(sd, KS_CHROMA, 0x9f, 0x40); 563 } else if (std & V4L2_STD_PAL) { 564 v4l2_dbg(1, debug, sd, 565 "s_std: PAL_N\n"); 566 ks0127_and_or(sd, KS_CHROMA, 0x9f, 0x20); 567 } else if (std & V4L2_STD_PAL_M) { 568 v4l2_dbg(1, debug, sd, 569 "s_std: PAL_M (fixme)\n"); 570 ks0127_and_or(sd, KS_CHROMA, 0x9f, 0x40); 571 } else if (std & V4L2_STD_SECAM) { 572 v4l2_dbg(1, debug, sd, 573 "s_std: SECAM\n"); 574 575 /* set to secam autodetection */ 576 ks0127_and_or(sd, KS_CHROMA, 0xdf, 0x20); 577 ks0127_and_or(sd, KS_DEMOD, 0xf0, 0x00); 578 schedule_timeout_interruptible(HZ/10+1); 579 580 /* did it autodetect? */ 581 if (!(ks0127_read(sd, KS_DEMOD) & 0x40)) 582 /* force to secam mode */ 583 ks0127_and_or(sd, KS_DEMOD, 0xf0, 0x0f); 584 } else { 585 v4l2_dbg(1, debug, sd, "s_std: Unknown norm %llx\n", 586 (unsigned long long)std); 587 } 588 return 0; 589 } 590 591 static int ks0127_s_stream(struct v4l2_subdev *sd, int enable) 592 { 593 v4l2_dbg(1, debug, sd, "s_stream(%d)\n", enable); 594 if (enable) { 595 /* All output pins on */ 596 ks0127_and_or(sd, KS_OFMTA, 0xcf, 0x30); 597 /* Obey the OEN pin */ 598 ks0127_and_or(sd, KS_CDEM, 0x7f, 0x00); 599 } else { 600 /* Video output pins off */ 601 ks0127_and_or(sd, KS_OFMTA, 0xcf, 0x00); 602 /* Ignore the OEN pin */ 603 ks0127_and_or(sd, KS_CDEM, 0x7f, 0x80); 604 } 605 return 0; 606 } 607 608 static int ks0127_status(struct v4l2_subdev *sd, u32 *pstatus, v4l2_std_id *pstd) 609 { 610 int stat = V4L2_IN_ST_NO_SIGNAL; 611 u8 status; 612 v4l2_std_id std = pstd ? *pstd : V4L2_STD_ALL; 613 614 status = ks0127_read(sd, KS_STAT); 615 if (!(status & 0x20)) /* NOVID not set */ 616 stat = 0; 617 if (!(status & 0x01)) { /* CLOCK set */ 618 stat |= V4L2_IN_ST_NO_COLOR; 619 std = V4L2_STD_UNKNOWN; 620 } else { 621 if ((status & 0x08)) /* PALDET set */ 622 std &= V4L2_STD_PAL; 623 else 624 std &= V4L2_STD_NTSC; 625 } 626 if ((status & 0x10)) /* PALDET set */ 627 std &= V4L2_STD_525_60; 628 else 629 std &= V4L2_STD_625_50; 630 if (pstd) 631 *pstd = std; 632 if (pstatus) 633 *pstatus = stat; 634 return 0; 635 } 636 637 static int ks0127_querystd(struct v4l2_subdev *sd, v4l2_std_id *std) 638 { 639 v4l2_dbg(1, debug, sd, "querystd\n"); 640 return ks0127_status(sd, NULL, std); 641 } 642 643 static int ks0127_g_input_status(struct v4l2_subdev *sd, u32 *status) 644 { 645 v4l2_dbg(1, debug, sd, "g_input_status\n"); 646 return ks0127_status(sd, status, NULL); 647 } 648 649 /* ----------------------------------------------------------------------- */ 650 651 static const struct v4l2_subdev_core_ops ks0127_core_ops = { 652 .s_std = ks0127_s_std, 653 }; 654 655 static const struct v4l2_subdev_video_ops ks0127_video_ops = { 656 .s_routing = ks0127_s_routing, 657 .s_stream = ks0127_s_stream, 658 .querystd = ks0127_querystd, 659 .g_input_status = ks0127_g_input_status, 660 }; 661 662 static const struct v4l2_subdev_ops ks0127_ops = { 663 .core = &ks0127_core_ops, 664 .video = &ks0127_video_ops, 665 }; 666 667 /* ----------------------------------------------------------------------- */ 668 669 670 static int ks0127_probe(struct i2c_client *client, const struct i2c_device_id *id) 671 { 672 struct ks0127 *ks; 673 struct v4l2_subdev *sd; 674 675 v4l_info(client, "%s chip found @ 0x%x (%s)\n", 676 client->addr == (I2C_KS0127_ADDON >> 1) ? "addon" : "on-board", 677 client->addr << 1, client->adapter->name); 678 679 ks = devm_kzalloc(&client->dev, sizeof(*ks), GFP_KERNEL); 680 if (ks == NULL) 681 return -ENOMEM; 682 sd = &ks->sd; 683 v4l2_i2c_subdev_init(sd, client, &ks0127_ops); 684 685 /* power up */ 686 init_reg_defaults(); 687 ks0127_write(sd, KS_CMDA, 0x2c); 688 mdelay(10); 689 690 /* reset the device */ 691 ks0127_init(sd); 692 return 0; 693 } 694 695 static int ks0127_remove(struct i2c_client *client) 696 { 697 struct v4l2_subdev *sd = i2c_get_clientdata(client); 698 699 v4l2_device_unregister_subdev(sd); 700 ks0127_write(sd, KS_OFMTA, 0x20); /* tristate */ 701 ks0127_write(sd, KS_CMDA, 0x2c | 0x80); /* power down */ 702 return 0; 703 } 704 705 static const struct i2c_device_id ks0127_id[] = { 706 { "ks0127", 0 }, 707 { "ks0127b", 0 }, 708 { "ks0122s", 0 }, 709 { } 710 }; 711 MODULE_DEVICE_TABLE(i2c, ks0127_id); 712 713 static struct i2c_driver ks0127_driver = { 714 .driver = { 715 .owner = THIS_MODULE, 716 .name = "ks0127", 717 }, 718 .probe = ks0127_probe, 719 .remove = ks0127_remove, 720 .id_table = ks0127_id, 721 }; 722 723 module_i2c_driver(ks0127_driver); 724