1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Driver for IMX296 CMOS Image Sensor from Sony 4 * 5 * Copyright 2019 Laurent Pinchart <laurent.pinchart@ideasonboard.com> 6 */ 7 8 #include <linux/clk.h> 9 #include <linux/gpio/consumer.h> 10 #include <linux/i2c.h> 11 #include <linux/module.h> 12 #include <linux/of.h> 13 #include <linux/pm_runtime.h> 14 #include <linux/regmap.h> 15 #include <linux/regulator/consumer.h> 16 #include <linux/slab.h> 17 #include <linux/videodev2.h> 18 19 #include <media/v4l2-ctrls.h> 20 #include <media/v4l2-fwnode.h> 21 #include <media/v4l2-subdev.h> 22 23 #define IMX296_PIXEL_ARRAY_WIDTH 1456 24 #define IMX296_PIXEL_ARRAY_HEIGHT 1088 25 26 #define IMX296_REG_8BIT(n) ((1 << 16) | (n)) 27 #define IMX296_REG_16BIT(n) ((2 << 16) | (n)) 28 #define IMX296_REG_24BIT(n) ((3 << 16) | (n)) 29 #define IMX296_REG_SIZE_SHIFT 16 30 #define IMX296_REG_ADDR_MASK 0xffff 31 32 #define IMX296_CTRL00 IMX296_REG_8BIT(0x3000) 33 #define IMX296_CTRL00_STANDBY BIT(0) 34 #define IMX296_CTRL08 IMX296_REG_8BIT(0x3008) 35 #define IMX296_CTRL08_REGHOLD BIT(0) 36 #define IMX296_CTRL0A IMX296_REG_8BIT(0x300a) 37 #define IMX296_CTRL0A_XMSTA BIT(0) 38 #define IMX296_CTRL0B IMX296_REG_8BIT(0x300b) 39 #define IMX296_CTRL0B_TRIGEN BIT(0) 40 #define IMX296_CTRL0D IMX296_REG_8BIT(0x300d) 41 #define IMX296_CTRL0D_WINMODE_ALL (0 << 0) 42 #define IMX296_CTRL0D_WINMODE_FD_BINNING (2 << 0) 43 #define IMX296_CTRL0D_HADD_ON_BINNING BIT(5) 44 #define IMX296_CTRL0D_SAT_CNT BIT(6) 45 #define IMX296_CTRL0E IMX296_REG_8BIT(0x300e) 46 #define IMX296_CTRL0E_VREVERSE BIT(0) 47 #define IMX296_CTRL0E_HREVERSE BIT(1) 48 #define IMX296_VMAX IMX296_REG_24BIT(0x3010) 49 #define IMX296_HMAX IMX296_REG_16BIT(0x3014) 50 #define IMX296_TMDCTRL IMX296_REG_8BIT(0x301d) 51 #define IMX296_TMDCTRL_LATCH BIT(0) 52 #define IMX296_TMDOUT IMX296_REG_16BIT(0x301e) 53 #define IMX296_TMDOUT_MASK 0x3ff 54 #define IMX296_WDSEL IMX296_REG_8BIT(0x3021) 55 #define IMX296_WDSEL_NORMAL (0 << 0) 56 #define IMX296_WDSEL_MULTI_2 (1 << 0) 57 #define IMX296_WDSEL_MULTI_4 (3 << 0) 58 #define IMX296_BLKLEVELAUTO IMX296_REG_8BIT(0x3022) 59 #define IMX296_BLKLEVELAUTO_ON 0x01 60 #define IMX296_BLKLEVELAUTO_OFF 0xf0 61 #define IMX296_SST IMX296_REG_8BIT(0x3024) 62 #define IMX296_SST_EN BIT(0) 63 #define IMX296_CTRLTOUT IMX296_REG_8BIT(0x3026) 64 #define IMX296_CTRLTOUT_TOUT1SEL_LOW (0 << 0) 65 #define IMX296_CTRLTOUT_TOUT1SEL_PULSE (3 << 0) 66 #define IMX296_CTRLTOUT_TOUT2SEL_LOW (0 << 2) 67 #define IMX296_CTRLTOUT_TOUT2SEL_PULSE (3 << 2) 68 #define IMX296_CTRLTRIG IMX296_REG_8BIT(0x3029) 69 #define IMX296_CTRLTRIG_TOUT1_SEL_LOW (0 << 0) 70 #define IMX296_CTRLTRIG_TOUT1_SEL_PULSE1 (1 << 0) 71 #define IMX296_CTRLTRIG_TOUT2_SEL_LOW (0 << 4) 72 #define IMX296_CTRLTRIG_TOUT2_SEL_PULSE2 (2 << 4) 73 #define IMX296_SYNCSEL IMX296_REG_8BIT(0x3036) 74 #define IMX296_SYNCSEL_NORMAL 0xc0 75 #define IMX296_SYNCSEL_HIZ 0xf0 76 #define IMX296_PULSE1 IMX296_REG_8BIT(0x306d) 77 #define IMX296_PULSE1_EN_NOR BIT(0) 78 #define IMX296_PULSE1_EN_TRIG BIT(1) 79 #define IMX296_PULSE1_POL_HIGH (0 << 2) 80 #define IMX296_PULSE1_POL_LOW (1 << 2) 81 #define IMX296_PULSE1_UP IMX296_REG_24BIT(0x3070) 82 #define IMX296_PULSE1_DN IMX296_REG_24BIT(0x3074) 83 #define IMX296_PULSE2 IMX296_REG_8BIT(0x3079) 84 #define IMX296_PULSE2_EN_NOR BIT(0) 85 #define IMX296_PULSE2_EN_TRIG BIT(1) 86 #define IMX296_PULSE2_POL_HIGH (0 << 2) 87 #define IMX296_PULSE2_POL_LOW (1 << 2) 88 #define IMX296_PULSE2_UP IMX296_REG_24BIT(0x307c) 89 #define IMX296_PULSE2_DN IMX296_REG_24BIT(0x3080) 90 #define IMX296_INCKSEL(n) IMX296_REG_8BIT(0x3089 + (n)) 91 #define IMX296_SHS1 IMX296_REG_24BIT(0x308d) 92 #define IMX296_SHS2 IMX296_REG_24BIT(0x3090) 93 #define IMX296_SHS3 IMX296_REG_24BIT(0x3094) 94 #define IMX296_SHS4 IMX296_REG_24BIT(0x3098) 95 #define IMX296_VBLANKLP IMX296_REG_8BIT(0x309c) 96 #define IMX296_VBLANKLP_NORMAL 0x04 97 #define IMX296_VBLANKLP_LOW_POWER 0x2c 98 #define IMX296_EXP_CNT IMX296_REG_8BIT(0x30a3) 99 #define IMX296_EXP_CNT_RESET BIT(0) 100 #define IMX296_EXP_MAX IMX296_REG_16BIT(0x30a6) 101 #define IMX296_VINT IMX296_REG_8BIT(0x30aa) 102 #define IMX296_VINT_EN BIT(0) 103 #define IMX296_LOWLAGTRG IMX296_REG_8BIT(0x30ae) 104 #define IMX296_LOWLAGTRG_FAST BIT(0) 105 #define IMX296_I2CCTRL IMX296_REG_8BIT(0x30ef) 106 #define IMX296_I2CCTRL_I2CACKEN BIT(0) 107 108 #define IMX296_SENSOR_INFO IMX296_REG_16BIT(0x3148) 109 #define IMX296_SENSOR_INFO_MONO BIT(15) 110 #define IMX296_SENSOR_INFO_IMX296LQ 0x4a00 111 #define IMX296_SENSOR_INFO_IMX296LL 0xca00 112 #define IMX296_S_SHSA IMX296_REG_16BIT(0x31ca) 113 #define IMX296_S_SHSB IMX296_REG_16BIT(0x31d2) 114 /* 115 * Registers 0x31c8 to 0x31cd, 0x31d0 to 0x31d5, 0x31e2, 0x31e3, 0x31ea and 116 * 0x31eb are related to exposure mode but otherwise not documented. 117 */ 118 119 #define IMX296_GAINCTRL IMX296_REG_8BIT(0x3200) 120 #define IMX296_GAINCTRL_WD_GAIN_MODE_NORMAL 0x01 121 #define IMX296_GAINCTRL_WD_GAIN_MODE_MULTI 0x41 122 #define IMX296_GAIN IMX296_REG_16BIT(0x3204) 123 #define IMX296_GAIN_MIN 0 124 #define IMX296_GAIN_MAX 480 125 #define IMX296_GAIN1 IMX296_REG_16BIT(0x3208) 126 #define IMX296_GAIN2 IMX296_REG_16BIT(0x320c) 127 #define IMX296_GAIN3 IMX296_REG_16BIT(0x3210) 128 #define IMX296_GAINDLY IMX296_REG_8BIT(0x3212) 129 #define IMX296_GAINDLY_NONE 0x08 130 #define IMX296_GAINDLY_1FRAME 0x09 131 #define IMX296_PGCTRL IMX296_REG_8BIT(0x3238) 132 #define IMX296_PGCTRL_REGEN BIT(0) 133 #define IMX296_PGCTRL_THRU BIT(1) 134 #define IMX296_PGCTRL_CLKEN BIT(2) 135 #define IMX296_PGCTRL_MODE(n) ((n) << 3) 136 #define IMX296_PGHPOS IMX296_REG_16BIT(0x3239) 137 #define IMX296_PGVPOS IMX296_REG_16BIT(0x323c) 138 #define IMX296_PGHPSTEP IMX296_REG_8BIT(0x323e) 139 #define IMX296_PGVPSTEP IMX296_REG_8BIT(0x323f) 140 #define IMX296_PGHPNUM IMX296_REG_8BIT(0x3240) 141 #define IMX296_PGVPNUM IMX296_REG_8BIT(0x3241) 142 #define IMX296_PGDATA1 IMX296_REG_16BIT(0x3244) 143 #define IMX296_PGDATA2 IMX296_REG_16BIT(0x3246) 144 #define IMX296_PGHGSTEP IMX296_REG_8BIT(0x3249) 145 #define IMX296_BLKLEVEL IMX296_REG_16BIT(0x3254) 146 147 #define IMX296_FID0_ROI IMX296_REG_8BIT(0x3300) 148 #define IMX296_FID0_ROIH1ON BIT(0) 149 #define IMX296_FID0_ROIV1ON BIT(1) 150 #define IMX296_FID0_ROIPH1 IMX296_REG_16BIT(0x3310) 151 #define IMX296_FID0_ROIPV1 IMX296_REG_16BIT(0x3312) 152 #define IMX296_FID0_ROIWH1 IMX296_REG_16BIT(0x3314) 153 #define IMX296_FID0_ROIWH1_MIN 80 154 #define IMX296_FID0_ROIWV1 IMX296_REG_16BIT(0x3316) 155 #define IMX296_FID0_ROIWV1_MIN 4 156 157 #define IMX296_CM_HSST_STARTTMG IMX296_REG_16BIT(0x4018) 158 #define IMX296_CM_HSST_ENDTMG IMX296_REG_16BIT(0x401a) 159 #define IMX296_DA_HSST_STARTTMG IMX296_REG_16BIT(0x404d) 160 #define IMX296_DA_HSST_ENDTMG IMX296_REG_16BIT(0x4050) 161 #define IMX296_LM_HSST_STARTTMG IMX296_REG_16BIT(0x4094) 162 #define IMX296_LM_HSST_ENDTMG IMX296_REG_16BIT(0x4096) 163 #define IMX296_SST_SIEASTA1_SET IMX296_REG_8BIT(0x40c9) 164 #define IMX296_SST_SIEASTA1PRE_1U IMX296_REG_16BIT(0x40cc) 165 #define IMX296_SST_SIEASTA1PRE_1D IMX296_REG_16BIT(0x40ce) 166 #define IMX296_SST_SIEASTA1PRE_2U IMX296_REG_16BIT(0x40d0) 167 #define IMX296_SST_SIEASTA1PRE_2D IMX296_REG_16BIT(0x40d2) 168 #define IMX296_HSST IMX296_REG_8BIT(0x40dc) 169 #define IMX296_HSST_EN BIT(2) 170 171 #define IMX296_CKREQSEL IMX296_REG_8BIT(0x4101) 172 #define IMX296_CKREQSEL_HS BIT(2) 173 #define IMX296_GTTABLENUM IMX296_REG_8BIT(0x4114) 174 #define IMX296_CTRL418C IMX296_REG_8BIT(0x418c) 175 176 struct imx296_clk_params { 177 unsigned int freq; 178 u8 incksel[4]; 179 u8 ctrl418c; 180 }; 181 182 static const struct imx296_clk_params imx296_clk_params[] = { 183 { 37125000, { 0x80, 0x0b, 0x80, 0x08 }, 116 }, 184 { 54000000, { 0xb0, 0x0f, 0xb0, 0x0c }, 168 }, 185 { 74250000, { 0x80, 0x0f, 0x80, 0x0c }, 232 }, 186 }; 187 188 static const char * const imx296_supply_names[] = { 189 "dvdd", 190 "ovdd", 191 "avdd", 192 }; 193 194 struct imx296 { 195 struct device *dev; 196 struct clk *clk; 197 struct regulator_bulk_data supplies[ARRAY_SIZE(imx296_supply_names)]; 198 struct gpio_desc *reset; 199 struct regmap *regmap; 200 201 const struct imx296_clk_params *clk_params; 202 bool mono; 203 204 bool streaming; 205 206 struct v4l2_subdev subdev; 207 struct media_pad pad; 208 209 struct v4l2_ctrl_handler ctrls; 210 struct v4l2_ctrl *hblank; 211 struct v4l2_ctrl *vblank; 212 }; 213 214 static inline struct imx296 *to_imx296(struct v4l2_subdev *sd) 215 { 216 return container_of(sd, struct imx296, subdev); 217 } 218 219 static int imx296_read(struct imx296 *sensor, u32 addr) 220 { 221 u8 data[3] = { 0, 0, 0 }; 222 int ret; 223 224 ret = regmap_raw_read(sensor->regmap, addr & IMX296_REG_ADDR_MASK, data, 225 (addr >> IMX296_REG_SIZE_SHIFT) & 3); 226 if (ret < 0) 227 return ret; 228 229 return (data[2] << 16) | (data[1] << 8) | data[0]; 230 } 231 232 static int imx296_write(struct imx296 *sensor, u32 addr, u32 value, int *err) 233 { 234 u8 data[3] = { value & 0xff, (value >> 8) & 0xff, value >> 16 }; 235 int ret; 236 237 if (err && *err) 238 return *err; 239 240 ret = regmap_raw_write(sensor->regmap, addr & IMX296_REG_ADDR_MASK, 241 data, (addr >> IMX296_REG_SIZE_SHIFT) & 3); 242 if (ret < 0) { 243 dev_err(sensor->dev, "%u-bit write to 0x%04x failed: %d\n", 244 ((addr >> IMX296_REG_SIZE_SHIFT) & 3) * 8, 245 addr & IMX296_REG_ADDR_MASK, ret); 246 if (err) 247 *err = ret; 248 } 249 250 return ret; 251 } 252 253 static int imx296_power_on(struct imx296 *sensor) 254 { 255 int ret; 256 257 ret = regulator_bulk_enable(ARRAY_SIZE(sensor->supplies), 258 sensor->supplies); 259 if (ret < 0) 260 return ret; 261 262 udelay(1); 263 264 ret = gpiod_direction_output(sensor->reset, 0); 265 if (ret < 0) 266 goto err_supply; 267 268 udelay(1); 269 270 ret = clk_prepare_enable(sensor->clk); 271 if (ret < 0) 272 goto err_reset; 273 274 /* 275 * The documentation doesn't explicitly say how much time is required 276 * after providing a clock and before starting I2C communication. It 277 * mentions a delay of 20µs in 4-wire mode, but tests showed that a 278 * delay of 100µs resulted in I2C communication failures, while 500µs 279 * seems to be enough. Be conservative. 280 */ 281 usleep_range(1000, 2000); 282 283 return 0; 284 285 err_reset: 286 gpiod_direction_output(sensor->reset, 1); 287 err_supply: 288 regulator_bulk_disable(ARRAY_SIZE(sensor->supplies), sensor->supplies); 289 return ret; 290 } 291 292 static void imx296_power_off(struct imx296 *sensor) 293 { 294 clk_disable_unprepare(sensor->clk); 295 gpiod_direction_output(sensor->reset, 1); 296 regulator_bulk_disable(ARRAY_SIZE(sensor->supplies), sensor->supplies); 297 } 298 299 /* ----------------------------------------------------------------------------- 300 * Controls 301 */ 302 303 static const char * const imx296_test_pattern_menu[] = { 304 "Disabled", 305 "Multiple Pixels", 306 "Sequence 1", 307 "Sequence 2", 308 "Gradient", 309 "Row", 310 "Column", 311 "Cross", 312 "Stripe", 313 "Checks", 314 }; 315 316 static int imx296_s_ctrl(struct v4l2_ctrl *ctrl) 317 { 318 struct imx296 *sensor = container_of(ctrl->handler, struct imx296, ctrls); 319 const struct v4l2_mbus_framefmt *format; 320 struct v4l2_subdev_state *state; 321 unsigned int vmax; 322 int ret = 0; 323 324 if (!sensor->streaming) 325 return 0; 326 327 state = v4l2_subdev_get_locked_active_state(&sensor->subdev); 328 format = v4l2_subdev_get_pad_format(&sensor->subdev, state, 0); 329 330 switch (ctrl->id) { 331 case V4L2_CID_EXPOSURE: 332 /* Clamp the exposure value to VMAX. */ 333 vmax = format->height + sensor->vblank->cur.val; 334 ctrl->val = min_t(int, ctrl->val, vmax); 335 imx296_write(sensor, IMX296_SHS1, vmax - ctrl->val, &ret); 336 break; 337 338 case V4L2_CID_ANALOGUE_GAIN: 339 imx296_write(sensor, IMX296_GAIN, ctrl->val, &ret); 340 break; 341 342 case V4L2_CID_VBLANK: 343 imx296_write(sensor, IMX296_VMAX, format->height + ctrl->val, 344 &ret); 345 break; 346 347 case V4L2_CID_TEST_PATTERN: 348 if (ctrl->val) { 349 imx296_write(sensor, IMX296_PGHPOS, 8, &ret); 350 imx296_write(sensor, IMX296_PGVPOS, 8, &ret); 351 imx296_write(sensor, IMX296_PGHPSTEP, 8, &ret); 352 imx296_write(sensor, IMX296_PGVPSTEP, 8, &ret); 353 imx296_write(sensor, IMX296_PGHPNUM, 100, &ret); 354 imx296_write(sensor, IMX296_PGVPNUM, 100, &ret); 355 imx296_write(sensor, IMX296_PGDATA1, 0x300, &ret); 356 imx296_write(sensor, IMX296_PGDATA2, 0x100, &ret); 357 imx296_write(sensor, IMX296_PGHGSTEP, 0, &ret); 358 imx296_write(sensor, IMX296_BLKLEVEL, 0, &ret); 359 imx296_write(sensor, IMX296_BLKLEVELAUTO, 360 IMX296_BLKLEVELAUTO_OFF, &ret); 361 imx296_write(sensor, IMX296_PGCTRL, 362 IMX296_PGCTRL_REGEN | 363 IMX296_PGCTRL_CLKEN | 364 IMX296_PGCTRL_MODE(ctrl->val - 1), &ret); 365 } else { 366 imx296_write(sensor, IMX296_PGCTRL, 367 IMX296_PGCTRL_CLKEN, &ret); 368 imx296_write(sensor, IMX296_BLKLEVEL, 0x3c, &ret); 369 imx296_write(sensor, IMX296_BLKLEVELAUTO, 370 IMX296_BLKLEVELAUTO_ON, &ret); 371 } 372 break; 373 374 default: 375 ret = -EINVAL; 376 break; 377 } 378 379 return ret; 380 } 381 382 static const struct v4l2_ctrl_ops imx296_ctrl_ops = { 383 .s_ctrl = imx296_s_ctrl, 384 }; 385 386 static int imx296_ctrls_init(struct imx296 *sensor) 387 { 388 struct v4l2_fwnode_device_properties props; 389 unsigned int hblank; 390 int ret; 391 392 ret = v4l2_fwnode_device_parse(sensor->dev, &props); 393 if (ret < 0) 394 return ret; 395 396 v4l2_ctrl_handler_init(&sensor->ctrls, 9); 397 398 v4l2_ctrl_new_std(&sensor->ctrls, &imx296_ctrl_ops, 399 V4L2_CID_EXPOSURE, 1, 1048575, 1, 1104); 400 v4l2_ctrl_new_std(&sensor->ctrls, &imx296_ctrl_ops, 401 V4L2_CID_ANALOGUE_GAIN, IMX296_GAIN_MIN, 402 IMX296_GAIN_MAX, 1, IMX296_GAIN_MIN); 403 404 /* 405 * Horizontal blanking is controlled through the HMAX register, which 406 * contains a line length in INCK clock units. The INCK frequency is 407 * fixed to 74.25 MHz. The HMAX value is currently fixed to 1100, 408 * convert it to a number of pixels based on the nominal pixel rate. 409 */ 410 hblank = 1100 * 1188000000ULL / 10 / 74250000 411 - IMX296_PIXEL_ARRAY_WIDTH; 412 sensor->hblank = v4l2_ctrl_new_std(&sensor->ctrls, &imx296_ctrl_ops, 413 V4L2_CID_HBLANK, hblank, hblank, 1, 414 hblank); 415 if (sensor->hblank) 416 sensor->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY; 417 418 sensor->vblank = v4l2_ctrl_new_std(&sensor->ctrls, &imx296_ctrl_ops, 419 V4L2_CID_VBLANK, 30, 420 1048575 - IMX296_PIXEL_ARRAY_HEIGHT, 421 1, 30); 422 /* 423 * The sensor calculates the MIPI timings internally to achieve a bit 424 * rate between 1122 and 1198 Mbps. The exact value is unfortunately not 425 * reported, at least according to the documentation. Report a nominal 426 * rate of 1188 Mbps as that is used by the datasheet in multiple 427 * examples. 428 */ 429 v4l2_ctrl_new_std(&sensor->ctrls, NULL, V4L2_CID_PIXEL_RATE, 430 1122000000 / 10, 1198000000 / 10, 1, 1188000000 / 10); 431 v4l2_ctrl_new_std_menu_items(&sensor->ctrls, &imx296_ctrl_ops, 432 V4L2_CID_TEST_PATTERN, 433 ARRAY_SIZE(imx296_test_pattern_menu) - 1, 434 0, 0, imx296_test_pattern_menu); 435 436 v4l2_ctrl_new_fwnode_properties(&sensor->ctrls, &imx296_ctrl_ops, 437 &props); 438 439 if (sensor->ctrls.error) { 440 dev_err(sensor->dev, "failed to add controls (%d)\n", 441 sensor->ctrls.error); 442 v4l2_ctrl_handler_free(&sensor->ctrls); 443 return sensor->ctrls.error; 444 } 445 446 sensor->subdev.ctrl_handler = &sensor->ctrls; 447 448 return 0; 449 } 450 451 /* ----------------------------------------------------------------------------- 452 * V4L2 Subdev Operations 453 */ 454 455 /* 456 * This table is extracted from vendor data that is entirely undocumented. The 457 * first register write is required to activate the CSI-2 output. The other 458 * entries may or may not be optional? 459 */ 460 static const struct { 461 unsigned int reg; 462 unsigned int value; 463 } imx296_init_table[] = { 464 { IMX296_REG_8BIT(0x3005), 0xf0 }, 465 { IMX296_REG_8BIT(0x309e), 0x04 }, 466 { IMX296_REG_8BIT(0x30a0), 0x04 }, 467 { IMX296_REG_8BIT(0x30a1), 0x3c }, 468 { IMX296_REG_8BIT(0x30a4), 0x5f }, 469 { IMX296_REG_8BIT(0x30a8), 0x91 }, 470 { IMX296_REG_8BIT(0x30ac), 0x28 }, 471 { IMX296_REG_8BIT(0x30af), 0x09 }, 472 { IMX296_REG_8BIT(0x30df), 0x00 }, 473 { IMX296_REG_8BIT(0x3165), 0x00 }, 474 { IMX296_REG_8BIT(0x3169), 0x10 }, 475 { IMX296_REG_8BIT(0x316a), 0x02 }, 476 { IMX296_REG_8BIT(0x31c8), 0xf3 }, /* Exposure-related */ 477 { IMX296_REG_8BIT(0x31d0), 0xf4 }, /* Exposure-related */ 478 { IMX296_REG_8BIT(0x321a), 0x00 }, 479 { IMX296_REG_8BIT(0x3226), 0x02 }, 480 { IMX296_REG_8BIT(0x3256), 0x01 }, 481 { IMX296_REG_8BIT(0x3541), 0x72 }, 482 { IMX296_REG_8BIT(0x3516), 0x77 }, 483 { IMX296_REG_8BIT(0x350b), 0x7f }, 484 { IMX296_REG_8BIT(0x3758), 0xa3 }, 485 { IMX296_REG_8BIT(0x3759), 0x00 }, 486 { IMX296_REG_8BIT(0x375a), 0x85 }, 487 { IMX296_REG_8BIT(0x375b), 0x00 }, 488 { IMX296_REG_8BIT(0x3832), 0xf5 }, 489 { IMX296_REG_8BIT(0x3833), 0x00 }, 490 { IMX296_REG_8BIT(0x38a2), 0xf6 }, 491 { IMX296_REG_8BIT(0x38a3), 0x00 }, 492 { IMX296_REG_8BIT(0x3a00), 0x80 }, 493 { IMX296_REG_8BIT(0x3d48), 0xa3 }, 494 { IMX296_REG_8BIT(0x3d49), 0x00 }, 495 { IMX296_REG_8BIT(0x3d4a), 0x85 }, 496 { IMX296_REG_8BIT(0x3d4b), 0x00 }, 497 { IMX296_REG_8BIT(0x400e), 0x58 }, 498 { IMX296_REG_8BIT(0x4014), 0x1c }, 499 { IMX296_REG_8BIT(0x4041), 0x2a }, 500 { IMX296_REG_8BIT(0x40a2), 0x06 }, 501 { IMX296_REG_8BIT(0x40c1), 0xf6 }, 502 { IMX296_REG_8BIT(0x40c7), 0x0f }, 503 { IMX296_REG_8BIT(0x40c8), 0x00 }, 504 { IMX296_REG_8BIT(0x4174), 0x00 }, 505 }; 506 507 static int imx296_setup(struct imx296 *sensor, struct v4l2_subdev_state *state) 508 { 509 const struct v4l2_mbus_framefmt *format; 510 const struct v4l2_rect *crop; 511 unsigned int i; 512 int ret = 0; 513 514 format = v4l2_subdev_get_pad_format(&sensor->subdev, state, 0); 515 crop = v4l2_subdev_get_pad_crop(&sensor->subdev, state, 0); 516 517 for (i = 0; i < ARRAY_SIZE(imx296_init_table); ++i) 518 imx296_write(sensor, imx296_init_table[i].reg, 519 imx296_init_table[i].value, &ret); 520 521 if (crop->width != IMX296_PIXEL_ARRAY_WIDTH || 522 crop->height != IMX296_PIXEL_ARRAY_HEIGHT) { 523 imx296_write(sensor, IMX296_FID0_ROI, 524 IMX296_FID0_ROIH1ON | IMX296_FID0_ROIV1ON, &ret); 525 imx296_write(sensor, IMX296_FID0_ROIPH1, crop->left, &ret); 526 imx296_write(sensor, IMX296_FID0_ROIPV1, crop->top, &ret); 527 imx296_write(sensor, IMX296_FID0_ROIWH1, crop->width, &ret); 528 imx296_write(sensor, IMX296_FID0_ROIWV1, crop->height, &ret); 529 } else { 530 imx296_write(sensor, IMX296_FID0_ROI, 0, &ret); 531 } 532 533 imx296_write(sensor, IMX296_CTRL0D, 534 (crop->width != format->width ? 535 IMX296_CTRL0D_HADD_ON_BINNING : 0) | 536 (crop->height != format->height ? 537 IMX296_CTRL0D_WINMODE_FD_BINNING : 0), 538 &ret); 539 540 /* 541 * HMAX and VMAX configure horizontal and vertical blanking by 542 * specifying the total line time and frame time respectively. The line 543 * time is specified in operational clock units (which appears to be the 544 * output of an internal PLL, fixed at 74.25 MHz regardless of the 545 * exernal clock frequency), while the frame time is specified as a 546 * number of lines. 547 * 548 * In the vertical direction the sensor outputs the following: 549 * 550 * - one line for the FS packet 551 * - two lines of embedded data (DT 0x12) 552 * - six null lines (DT 0x10) 553 * - four lines of vertical effective optical black (DT 0x37) 554 * - 8 to 1088 lines of active image data (RAW10, DT 0x2b) 555 * - one line for the FE packet 556 * - 16 or more lines of vertical blanking 557 */ 558 imx296_write(sensor, IMX296_HMAX, 1100, &ret); 559 imx296_write(sensor, IMX296_VMAX, 560 format->height + sensor->vblank->cur.val, &ret); 561 562 for (i = 0; i < ARRAY_SIZE(sensor->clk_params->incksel); ++i) 563 imx296_write(sensor, IMX296_INCKSEL(i), 564 sensor->clk_params->incksel[i], &ret); 565 imx296_write(sensor, IMX296_GTTABLENUM, 0xc5, &ret); 566 imx296_write(sensor, IMX296_CTRL418C, sensor->clk_params->ctrl418c, 567 &ret); 568 569 imx296_write(sensor, IMX296_GAINDLY, IMX296_GAINDLY_NONE, &ret); 570 imx296_write(sensor, IMX296_BLKLEVEL, 0x03c, &ret); 571 572 return ret; 573 } 574 575 static int imx296_stream_on(struct imx296 *sensor) 576 { 577 int ret = 0; 578 579 imx296_write(sensor, IMX296_CTRL00, 0, &ret); 580 usleep_range(2000, 5000); 581 imx296_write(sensor, IMX296_CTRL0A, 0, &ret); 582 583 return ret; 584 } 585 586 static int imx296_stream_off(struct imx296 *sensor) 587 { 588 int ret = 0; 589 590 imx296_write(sensor, IMX296_CTRL0A, IMX296_CTRL0A_XMSTA, &ret); 591 imx296_write(sensor, IMX296_CTRL00, IMX296_CTRL00_STANDBY, &ret); 592 593 return ret; 594 } 595 596 static int imx296_s_stream(struct v4l2_subdev *sd, int enable) 597 { 598 struct imx296 *sensor = to_imx296(sd); 599 struct v4l2_subdev_state *state; 600 int ret; 601 602 state = v4l2_subdev_lock_and_get_active_state(sd); 603 604 if (!enable) { 605 ret = imx296_stream_off(sensor); 606 607 pm_runtime_mark_last_busy(sensor->dev); 608 pm_runtime_put_autosuspend(sensor->dev); 609 610 sensor->streaming = false; 611 612 goto unlock; 613 } 614 615 ret = pm_runtime_resume_and_get(sensor->dev); 616 if (ret < 0) 617 goto unlock; 618 619 ret = imx296_setup(sensor, state); 620 if (ret < 0) 621 goto err_pm; 622 623 /* 624 * Set streaming to true to ensure __v4l2_ctrl_handler_setup() will set 625 * the controls. The flag is reset to false further down if an error 626 * occurs. 627 */ 628 sensor->streaming = true; 629 630 ret = __v4l2_ctrl_handler_setup(&sensor->ctrls); 631 if (ret < 0) 632 goto err_pm; 633 634 ret = imx296_stream_on(sensor); 635 if (ret) 636 goto err_pm; 637 638 unlock: 639 v4l2_subdev_unlock_state(state); 640 641 return ret; 642 643 err_pm: 644 /* 645 * In case of error, turn the power off synchronously as the device 646 * likely has no other chance to recover. 647 */ 648 pm_runtime_put_sync(sensor->dev); 649 sensor->streaming = false; 650 651 goto unlock; 652 } 653 654 static int imx296_enum_mbus_code(struct v4l2_subdev *sd, 655 struct v4l2_subdev_state *state, 656 struct v4l2_subdev_mbus_code_enum *code) 657 { 658 struct imx296 *sensor = to_imx296(sd); 659 660 if (code->index != 0) 661 return -EINVAL; 662 663 code->code = sensor->mono ? MEDIA_BUS_FMT_Y10_1X10 664 : MEDIA_BUS_FMT_SBGGR10_1X10; 665 666 return 0; 667 } 668 669 static int imx296_enum_frame_size(struct v4l2_subdev *sd, 670 struct v4l2_subdev_state *state, 671 struct v4l2_subdev_frame_size_enum *fse) 672 { 673 const struct v4l2_mbus_framefmt *format; 674 675 format = v4l2_subdev_get_pad_format(sd, state, fse->pad); 676 677 if (fse->index >= 2 || fse->code != format->code) 678 return -EINVAL; 679 680 fse->min_width = IMX296_PIXEL_ARRAY_WIDTH / (fse->index + 1); 681 fse->max_width = fse->min_width; 682 fse->min_height = IMX296_PIXEL_ARRAY_HEIGHT / (fse->index + 1); 683 fse->max_height = fse->min_height; 684 685 return 0; 686 } 687 688 static int imx296_set_format(struct v4l2_subdev *sd, 689 struct v4l2_subdev_state *state, 690 struct v4l2_subdev_format *fmt) 691 { 692 struct imx296 *sensor = to_imx296(sd); 693 struct v4l2_mbus_framefmt *format; 694 struct v4l2_rect *crop; 695 696 crop = v4l2_subdev_get_pad_crop(sd, state, fmt->pad); 697 format = v4l2_subdev_get_pad_format(sd, state, fmt->pad); 698 699 /* 700 * Binning is only allowed when cropping is disabled according to the 701 * documentation. This should be double-checked. 702 */ 703 if (crop->width == IMX296_PIXEL_ARRAY_WIDTH && 704 crop->height == IMX296_PIXEL_ARRAY_HEIGHT) { 705 unsigned int width; 706 unsigned int height; 707 unsigned int hratio; 708 unsigned int vratio; 709 710 /* Clamp the width and height to avoid dividing by zero. */ 711 width = clamp_t(unsigned int, fmt->format.width, 712 crop->width / 2, crop->width); 713 height = clamp_t(unsigned int, fmt->format.height, 714 crop->height / 2, crop->height); 715 716 hratio = DIV_ROUND_CLOSEST(crop->width, width); 717 vratio = DIV_ROUND_CLOSEST(crop->height, height); 718 719 format->width = crop->width / hratio; 720 format->height = crop->height / vratio; 721 } else { 722 format->width = crop->width; 723 format->height = crop->height; 724 } 725 726 format->code = sensor->mono ? MEDIA_BUS_FMT_Y10_1X10 727 : MEDIA_BUS_FMT_SBGGR10_1X10; 728 format->field = V4L2_FIELD_NONE; 729 format->colorspace = V4L2_COLORSPACE_RAW; 730 format->ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT; 731 format->quantization = V4L2_QUANTIZATION_FULL_RANGE; 732 format->xfer_func = V4L2_XFER_FUNC_NONE; 733 734 fmt->format = *format; 735 736 return 0; 737 } 738 739 static int imx296_get_selection(struct v4l2_subdev *sd, 740 struct v4l2_subdev_state *state, 741 struct v4l2_subdev_selection *sel) 742 { 743 switch (sel->target) { 744 case V4L2_SEL_TGT_CROP: 745 sel->r = *v4l2_subdev_get_pad_crop(sd, state, sel->pad); 746 break; 747 748 case V4L2_SEL_TGT_CROP_DEFAULT: 749 case V4L2_SEL_TGT_CROP_BOUNDS: 750 case V4L2_SEL_TGT_NATIVE_SIZE: 751 sel->r.left = 0; 752 sel->r.top = 0; 753 sel->r.width = IMX296_PIXEL_ARRAY_WIDTH; 754 sel->r.height = IMX296_PIXEL_ARRAY_HEIGHT; 755 break; 756 757 default: 758 return -EINVAL; 759 } 760 761 return 0; 762 } 763 764 static int imx296_set_selection(struct v4l2_subdev *sd, 765 struct v4l2_subdev_state *state, 766 struct v4l2_subdev_selection *sel) 767 { 768 struct v4l2_mbus_framefmt *format; 769 struct v4l2_rect *crop; 770 struct v4l2_rect rect; 771 772 if (sel->target != V4L2_SEL_TGT_CROP) 773 return -EINVAL; 774 775 /* 776 * Clamp the crop rectangle boundaries and align them to a multiple of 4 777 * pixels to satisfy hardware requirements. 778 */ 779 rect.left = clamp(ALIGN(sel->r.left, 4), 0, 780 IMX296_PIXEL_ARRAY_WIDTH - IMX296_FID0_ROIWH1_MIN); 781 rect.top = clamp(ALIGN(sel->r.top, 4), 0, 782 IMX296_PIXEL_ARRAY_HEIGHT - IMX296_FID0_ROIWV1_MIN); 783 rect.width = clamp_t(unsigned int, ALIGN(sel->r.width, 4), 784 IMX296_FID0_ROIWH1_MIN, IMX296_PIXEL_ARRAY_WIDTH); 785 rect.height = clamp_t(unsigned int, ALIGN(sel->r.height, 4), 786 IMX296_FID0_ROIWV1_MIN, IMX296_PIXEL_ARRAY_HEIGHT); 787 788 rect.width = min_t(unsigned int, rect.width, 789 IMX296_PIXEL_ARRAY_WIDTH - rect.left); 790 rect.height = min_t(unsigned int, rect.height, 791 IMX296_PIXEL_ARRAY_HEIGHT - rect.top); 792 793 crop = v4l2_subdev_get_pad_crop(sd, state, sel->pad); 794 795 if (rect.width != crop->width || rect.height != crop->height) { 796 /* 797 * Reset the output image size if the crop rectangle size has 798 * been modified. 799 */ 800 format = v4l2_subdev_get_pad_format(sd, state, sel->pad); 801 format->width = rect.width; 802 format->height = rect.height; 803 } 804 805 *crop = rect; 806 sel->r = rect; 807 808 return 0; 809 } 810 811 static int imx296_init_cfg(struct v4l2_subdev *sd, 812 struct v4l2_subdev_state *state) 813 { 814 struct v4l2_subdev_selection sel = { 815 .target = V4L2_SEL_TGT_CROP, 816 .r.width = IMX296_PIXEL_ARRAY_WIDTH, 817 .r.height = IMX296_PIXEL_ARRAY_HEIGHT, 818 }; 819 struct v4l2_subdev_format format = { 820 .format = { 821 .width = IMX296_PIXEL_ARRAY_WIDTH, 822 .height = IMX296_PIXEL_ARRAY_HEIGHT, 823 }, 824 }; 825 826 imx296_set_selection(sd, state, &sel); 827 imx296_set_format(sd, state, &format); 828 829 return 0; 830 } 831 832 static const struct v4l2_subdev_video_ops imx296_subdev_video_ops = { 833 .s_stream = imx296_s_stream, 834 }; 835 836 static const struct v4l2_subdev_pad_ops imx296_subdev_pad_ops = { 837 .enum_mbus_code = imx296_enum_mbus_code, 838 .enum_frame_size = imx296_enum_frame_size, 839 .get_fmt = v4l2_subdev_get_fmt, 840 .set_fmt = imx296_set_format, 841 .get_selection = imx296_get_selection, 842 .set_selection = imx296_set_selection, 843 .init_cfg = imx296_init_cfg, 844 }; 845 846 static const struct v4l2_subdev_ops imx296_subdev_ops = { 847 .video = &imx296_subdev_video_ops, 848 .pad = &imx296_subdev_pad_ops, 849 }; 850 851 static int imx296_subdev_init(struct imx296 *sensor) 852 { 853 struct i2c_client *client = to_i2c_client(sensor->dev); 854 int ret; 855 856 v4l2_i2c_subdev_init(&sensor->subdev, client, &imx296_subdev_ops); 857 858 ret = imx296_ctrls_init(sensor); 859 if (ret < 0) 860 return ret; 861 862 sensor->subdev.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; 863 sensor->pad.flags = MEDIA_PAD_FL_SOURCE; 864 sensor->subdev.entity.function = MEDIA_ENT_F_CAM_SENSOR; 865 ret = media_entity_pads_init(&sensor->subdev.entity, 1, &sensor->pad); 866 if (ret < 0) { 867 v4l2_ctrl_handler_free(&sensor->ctrls); 868 return ret; 869 } 870 871 sensor->subdev.state_lock = sensor->subdev.ctrl_handler->lock; 872 873 v4l2_subdev_init_finalize(&sensor->subdev); 874 875 return ret; 876 } 877 878 static void imx296_subdev_cleanup(struct imx296 *sensor) 879 { 880 media_entity_cleanup(&sensor->subdev.entity); 881 v4l2_ctrl_handler_free(&sensor->ctrls); 882 } 883 884 /* ----------------------------------------------------------------------------- 885 * Power management 886 */ 887 888 static int __maybe_unused imx296_runtime_resume(struct device *dev) 889 { 890 struct i2c_client *client = to_i2c_client(dev); 891 struct v4l2_subdev *subdev = i2c_get_clientdata(client); 892 struct imx296 *sensor = to_imx296(subdev); 893 894 return imx296_power_on(sensor); 895 } 896 897 static int __maybe_unused imx296_runtime_suspend(struct device *dev) 898 { 899 struct i2c_client *client = to_i2c_client(dev); 900 struct v4l2_subdev *subdev = i2c_get_clientdata(client); 901 struct imx296 *sensor = to_imx296(subdev); 902 903 imx296_power_off(sensor); 904 905 return 0; 906 } 907 908 static const struct dev_pm_ops imx296_pm_ops = { 909 SET_RUNTIME_PM_OPS(imx296_runtime_suspend, imx296_runtime_resume, NULL) 910 }; 911 912 /* ----------------------------------------------------------------------------- 913 * Probe & Remove 914 */ 915 916 static int imx296_read_temperature(struct imx296 *sensor, int *temp) 917 { 918 int tmdout; 919 int ret; 920 921 ret = imx296_write(sensor, IMX296_TMDCTRL, IMX296_TMDCTRL_LATCH, NULL); 922 if (ret < 0) 923 return ret; 924 925 tmdout = imx296_read(sensor, IMX296_TMDOUT); 926 if (tmdout < 0) 927 return tmdout; 928 929 tmdout &= IMX296_TMDOUT_MASK; 930 931 /* T(°C) = 246.312 - 0.304 * TMDOUT */; 932 *temp = 246312 - 304 * tmdout; 933 934 return imx296_write(sensor, IMX296_TMDCTRL, 0, NULL); 935 } 936 937 static int imx296_identify_model(struct imx296 *sensor) 938 { 939 unsigned int model; 940 int temp = 0; 941 int ret; 942 943 model = (uintptr_t)of_device_get_match_data(sensor->dev); 944 if (model) { 945 dev_dbg(sensor->dev, 946 "sensor model auto-detection disabled, forcing 0x%04x\n", 947 model); 948 sensor->mono = model & IMX296_SENSOR_INFO_MONO; 949 return 0; 950 } 951 952 /* 953 * While most registers can be read when the sensor is in standby, this 954 * is not the case of the sensor info register :-( 955 */ 956 ret = imx296_write(sensor, IMX296_CTRL00, 0, NULL); 957 if (ret < 0) { 958 dev_err(sensor->dev, 959 "failed to get sensor out of standby (%d)\n", ret); 960 return ret; 961 } 962 963 ret = imx296_read(sensor, IMX296_SENSOR_INFO); 964 if (ret < 0) { 965 dev_err(sensor->dev, "failed to read sensor information (%d)\n", 966 ret); 967 goto done; 968 } 969 970 model = (ret >> 6) & 0x1ff; 971 972 switch (model) { 973 case 296: 974 sensor->mono = ret & IMX296_SENSOR_INFO_MONO; 975 break; 976 /* 977 * The IMX297 seems to share features with the IMX296, it may be 978 * possible to support it in the same driver. 979 */ 980 case 297: 981 default: 982 dev_err(sensor->dev, "invalid device model 0x%04x\n", ret); 983 ret = -ENODEV; 984 goto done; 985 } 986 987 ret = imx296_read_temperature(sensor, &temp); 988 if (ret < 0) 989 goto done; 990 991 dev_info(sensor->dev, "found IMX%u%s (%u.%uC)\n", model, 992 sensor->mono ? "LL" : "LQ", temp / 1000, (temp / 100) % 10); 993 994 done: 995 imx296_write(sensor, IMX296_CTRL00, IMX296_CTRL00_STANDBY, NULL); 996 return ret; 997 } 998 999 static const struct regmap_config imx296_regmap_config = { 1000 .reg_bits = 16, 1001 .val_bits = 8, 1002 1003 .wr_table = &(const struct regmap_access_table) { 1004 .no_ranges = (const struct regmap_range[]) { 1005 { 1006 .range_min = IMX296_SENSOR_INFO & 0xffff, 1007 .range_max = (IMX296_SENSOR_INFO & 0xffff) + 1, 1008 }, 1009 }, 1010 .n_no_ranges = 1, 1011 }, 1012 }; 1013 1014 static int imx296_probe(struct i2c_client *client) 1015 { 1016 struct i2c_adapter *adapter = to_i2c_adapter(client->dev.parent); 1017 unsigned long clk_rate; 1018 struct imx296 *sensor; 1019 unsigned int i; 1020 int ret; 1021 1022 if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA)) { 1023 dev_warn(&adapter->dev, 1024 "I2C-Adapter doesn't support I2C_FUNC_SMBUS_BYTE\n"); 1025 return -EIO; 1026 } 1027 1028 sensor = devm_kzalloc(&client->dev, sizeof(*sensor), GFP_KERNEL); 1029 if (!sensor) 1030 return -ENOMEM; 1031 1032 sensor->dev = &client->dev; 1033 1034 /* Acquire resources. */ 1035 for (i = 0; i < ARRAY_SIZE(sensor->supplies); ++i) 1036 sensor->supplies[i].supply = imx296_supply_names[i]; 1037 1038 ret = devm_regulator_bulk_get(sensor->dev, ARRAY_SIZE(sensor->supplies), 1039 sensor->supplies); 1040 if (ret) { 1041 dev_err_probe(sensor->dev, ret, "failed to get supplies\n"); 1042 return ret; 1043 } 1044 1045 sensor->reset = devm_gpiod_get_optional(sensor->dev, "reset", 1046 GPIOD_OUT_HIGH); 1047 if (IS_ERR(sensor->reset)) 1048 return dev_err_probe(sensor->dev, PTR_ERR(sensor->reset), 1049 "failed to get reset GPIO\n"); 1050 1051 sensor->clk = devm_clk_get(sensor->dev, "inck"); 1052 if (IS_ERR(sensor->clk)) 1053 return dev_err_probe(sensor->dev, PTR_ERR(sensor->clk), 1054 "failed to get clock\n"); 1055 1056 clk_rate = clk_get_rate(sensor->clk); 1057 for (i = 0; i < ARRAY_SIZE(imx296_clk_params); ++i) { 1058 if (clk_rate == imx296_clk_params[i].freq) { 1059 sensor->clk_params = &imx296_clk_params[i]; 1060 break; 1061 } 1062 } 1063 1064 if (!sensor->clk_params) { 1065 dev_err(sensor->dev, "unsupported clock rate %lu\n", clk_rate); 1066 return -EINVAL; 1067 } 1068 1069 sensor->regmap = devm_regmap_init_i2c(client, &imx296_regmap_config); 1070 if (IS_ERR(sensor->regmap)) 1071 return PTR_ERR(sensor->regmap); 1072 1073 /* 1074 * Enable power management. The driver supports runtime PM, but needs to 1075 * work when runtime PM is disabled in the kernel. To that end, power 1076 * the sensor on manually here, identify it, and fully initialize it. 1077 */ 1078 ret = imx296_power_on(sensor); 1079 if (ret < 0) 1080 return ret; 1081 1082 ret = imx296_identify_model(sensor); 1083 if (ret < 0) 1084 goto err_power; 1085 1086 /* Initialize the V4L2 subdev. */ 1087 ret = imx296_subdev_init(sensor); 1088 if (ret < 0) 1089 goto err_power; 1090 1091 /* 1092 * Enable runtime PM. As the device has been powered manually, mark it 1093 * as active, and increase the usage count without resuming the device. 1094 */ 1095 pm_runtime_set_active(sensor->dev); 1096 pm_runtime_get_noresume(sensor->dev); 1097 pm_runtime_enable(sensor->dev); 1098 1099 /* Register the V4L2 subdev. */ 1100 ret = v4l2_async_register_subdev(&sensor->subdev); 1101 if (ret < 0) 1102 goto err_pm; 1103 1104 /* 1105 * Finally, enable autosuspend and decrease the usage count. The device 1106 * will get suspended after the autosuspend delay, turning the power 1107 * off. 1108 */ 1109 pm_runtime_set_autosuspend_delay(sensor->dev, 1000); 1110 pm_runtime_use_autosuspend(sensor->dev); 1111 pm_runtime_put_autosuspend(sensor->dev); 1112 1113 return 0; 1114 1115 err_pm: 1116 pm_runtime_disable(sensor->dev); 1117 pm_runtime_put_noidle(sensor->dev); 1118 imx296_subdev_cleanup(sensor); 1119 err_power: 1120 imx296_power_off(sensor); 1121 return ret; 1122 } 1123 1124 static void imx296_remove(struct i2c_client *client) 1125 { 1126 struct v4l2_subdev *subdev = i2c_get_clientdata(client); 1127 struct imx296 *sensor = to_imx296(subdev); 1128 1129 v4l2_async_unregister_subdev(subdev); 1130 1131 imx296_subdev_cleanup(sensor); 1132 1133 /* 1134 * Disable runtime PM. In case runtime PM is disabled in the kernel, 1135 * make sure to turn power off manually. 1136 */ 1137 pm_runtime_disable(sensor->dev); 1138 if (!pm_runtime_status_suspended(sensor->dev)) 1139 imx296_power_off(sensor); 1140 pm_runtime_set_suspended(sensor->dev); 1141 } 1142 1143 static const struct of_device_id imx296_of_match[] = { 1144 { .compatible = "sony,imx296", .data = NULL }, 1145 { .compatible = "sony,imx296ll", .data = (void *)IMX296_SENSOR_INFO_IMX296LL }, 1146 { .compatible = "sony,imx296lq", .data = (void *)IMX296_SENSOR_INFO_IMX296LQ }, 1147 { /* sentinel */ }, 1148 }; 1149 MODULE_DEVICE_TABLE(of, imx296_of_match); 1150 1151 static struct i2c_driver imx296_i2c_driver = { 1152 .driver = { 1153 .of_match_table = imx296_of_match, 1154 .name = "imx296", 1155 .pm = &imx296_pm_ops 1156 }, 1157 .probe = imx296_probe, 1158 .remove = imx296_remove, 1159 }; 1160 1161 module_i2c_driver(imx296_i2c_driver); 1162 1163 MODULE_DESCRIPTION("Sony IMX296 Camera driver"); 1164 MODULE_AUTHOR("Laurent Pinchart <laurent.pinchart@ideasonboard.com>"); 1165 MODULE_LICENSE("GPL"); 1166