1e6002df8SLuca Ceresoli // SPDX-License-Identifier: GPL-2.0 20985dd30SLeon Luo /* 30985dd30SLeon Luo * imx274.c - IMX274 CMOS Image Sensor driver 40985dd30SLeon Luo * 50985dd30SLeon Luo * Copyright (C) 2017, Leopard Imaging, Inc. 60985dd30SLeon Luo * 70985dd30SLeon Luo * Leon Luo <leonl@leopardimaging.com> 80985dd30SLeon Luo * Edwin Zou <edwinz@leopardimaging.com> 939dd23dcSLuca Ceresoli * Luca Ceresoli <luca@lucaceresoli.net> 100985dd30SLeon Luo */ 110985dd30SLeon Luo 120985dd30SLeon Luo #include <linux/clk.h> 130985dd30SLeon Luo #include <linux/delay.h> 140985dd30SLeon Luo #include <linux/gpio.h> 150985dd30SLeon Luo #include <linux/gpio/consumer.h> 160985dd30SLeon Luo #include <linux/i2c.h> 170985dd30SLeon Luo #include <linux/init.h> 1839dd23dcSLuca Ceresoli #include <linux/kernel.h> 190985dd30SLeon Luo #include <linux/module.h> 200985dd30SLeon Luo #include <linux/of_gpio.h> 210985dd30SLeon Luo #include <linux/regmap.h> 220985dd30SLeon Luo #include <linux/slab.h> 230985dd30SLeon Luo #include <linux/v4l2-mediabus.h> 240985dd30SLeon Luo #include <linux/videodev2.h> 250985dd30SLeon Luo 260985dd30SLeon Luo #include <media/v4l2-ctrls.h> 270985dd30SLeon Luo #include <media/v4l2-device.h> 280985dd30SLeon Luo #include <media/v4l2-subdev.h> 290985dd30SLeon Luo 300985dd30SLeon Luo /* 310985dd30SLeon Luo * See "SHR, SVR Setting" in datasheet 320985dd30SLeon Luo */ 330985dd30SLeon Luo #define IMX274_DEFAULT_FRAME_LENGTH (4550) 340985dd30SLeon Luo #define IMX274_MAX_FRAME_LENGTH (0x000fffff) 350985dd30SLeon Luo 360985dd30SLeon Luo /* 370985dd30SLeon Luo * See "Frame Rate Adjustment" in datasheet 380985dd30SLeon Luo */ 390985dd30SLeon Luo #define IMX274_PIXCLK_CONST1 (72000000) 400985dd30SLeon Luo #define IMX274_PIXCLK_CONST2 (1000000) 410985dd30SLeon Luo 420985dd30SLeon Luo /* 430985dd30SLeon Luo * The input gain is shifted by IMX274_GAIN_SHIFT to get 440985dd30SLeon Luo * decimal number. The real gain is 450985dd30SLeon Luo * (float)input_gain_value / (1 << IMX274_GAIN_SHIFT) 460985dd30SLeon Luo */ 470985dd30SLeon Luo #define IMX274_GAIN_SHIFT (8) 480985dd30SLeon Luo #define IMX274_GAIN_SHIFT_MASK ((1 << IMX274_GAIN_SHIFT) - 1) 490985dd30SLeon Luo 500985dd30SLeon Luo /* 510985dd30SLeon Luo * See "Analog Gain" and "Digital Gain" in datasheet 520985dd30SLeon Luo * min gain is 1X 530985dd30SLeon Luo * max gain is calculated based on IMX274_GAIN_REG_MAX 540985dd30SLeon Luo */ 550985dd30SLeon Luo #define IMX274_GAIN_REG_MAX (1957) 560985dd30SLeon Luo #define IMX274_MIN_GAIN (0x01 << IMX274_GAIN_SHIFT) 570985dd30SLeon Luo #define IMX274_MAX_ANALOG_GAIN ((2048 << IMX274_GAIN_SHIFT)\ 580985dd30SLeon Luo / (2048 - IMX274_GAIN_REG_MAX)) 590985dd30SLeon Luo #define IMX274_MAX_DIGITAL_GAIN (8) 600985dd30SLeon Luo #define IMX274_DEF_GAIN (20 << IMX274_GAIN_SHIFT) 610985dd30SLeon Luo #define IMX274_GAIN_CONST (2048) /* for gain formula */ 620985dd30SLeon Luo 630985dd30SLeon Luo /* 640985dd30SLeon Luo * 1 line time in us = (HMAX / 72), minimal is 4 lines 650985dd30SLeon Luo */ 660985dd30SLeon Luo #define IMX274_MIN_EXPOSURE_TIME (4 * 260 / 72) 670985dd30SLeon Luo 683df8adb7SLuca Ceresoli #define IMX274_DEFAULT_BINNING IMX274_BINNING_OFF 690985dd30SLeon Luo #define IMX274_MAX_WIDTH (3840) 700985dd30SLeon Luo #define IMX274_MAX_HEIGHT (2160) 710985dd30SLeon Luo #define IMX274_MAX_FRAME_RATE (120) 720985dd30SLeon Luo #define IMX274_MIN_FRAME_RATE (5) 730985dd30SLeon Luo #define IMX274_DEF_FRAME_RATE (60) 740985dd30SLeon Luo 750985dd30SLeon Luo /* 760985dd30SLeon Luo * register SHR is limited to (SVR value + 1) x VMAX value - 4 770985dd30SLeon Luo */ 780985dd30SLeon Luo #define IMX274_SHR_LIMIT_CONST (4) 790985dd30SLeon Luo 800985dd30SLeon Luo /* 814c858e96SLuca Ceresoli * Min and max sensor reset delay (microseconds) 820985dd30SLeon Luo */ 830985dd30SLeon Luo #define IMX274_RESET_DELAY1 (2000) 840985dd30SLeon Luo #define IMX274_RESET_DELAY2 (2200) 850985dd30SLeon Luo 860985dd30SLeon Luo /* 870985dd30SLeon Luo * shift and mask constants 880985dd30SLeon Luo */ 890985dd30SLeon Luo #define IMX274_SHIFT_8_BITS (8) 900985dd30SLeon Luo #define IMX274_SHIFT_16_BITS (16) 910985dd30SLeon Luo #define IMX274_MASK_LSB_2_BITS (0x03) 920985dd30SLeon Luo #define IMX274_MASK_LSB_3_BITS (0x07) 930985dd30SLeon Luo #define IMX274_MASK_LSB_4_BITS (0x0f) 940985dd30SLeon Luo #define IMX274_MASK_LSB_8_BITS (0x00ff) 950985dd30SLeon Luo 960985dd30SLeon Luo #define DRIVER_NAME "IMX274" 970985dd30SLeon Luo 980985dd30SLeon Luo /* 990985dd30SLeon Luo * IMX274 register definitions 1000985dd30SLeon Luo */ 1014eb7846dSLuca Ceresoli #define IMX274_SHR_REG_MSB 0x300D /* SHR */ 1024eb7846dSLuca Ceresoli #define IMX274_SHR_REG_LSB 0x300C /* SHR */ 1030985dd30SLeon Luo #define IMX274_SVR_REG_MSB 0x300F /* SVR */ 1040985dd30SLeon Luo #define IMX274_SVR_REG_LSB 0x300E /* SVR */ 10539dd23dcSLuca Ceresoli #define IMX274_HTRIM_EN_REG 0x3037 10639dd23dcSLuca Ceresoli #define IMX274_HTRIM_START_REG_LSB 0x3038 10739dd23dcSLuca Ceresoli #define IMX274_HTRIM_START_REG_MSB 0x3039 10839dd23dcSLuca Ceresoli #define IMX274_HTRIM_END_REG_LSB 0x303A 10939dd23dcSLuca Ceresoli #define IMX274_HTRIM_END_REG_MSB 0x303B 11039dd23dcSLuca Ceresoli #define IMX274_VWIDCUTEN_REG 0x30DD 11139dd23dcSLuca Ceresoli #define IMX274_VWIDCUT_REG_LSB 0x30DE 11239dd23dcSLuca Ceresoli #define IMX274_VWIDCUT_REG_MSB 0x30DF 11339dd23dcSLuca Ceresoli #define IMX274_VWINPOS_REG_LSB 0x30E0 11439dd23dcSLuca Ceresoli #define IMX274_VWINPOS_REG_MSB 0x30E1 11539dd23dcSLuca Ceresoli #define IMX274_WRITE_VSIZE_REG_LSB 0x3130 11639dd23dcSLuca Ceresoli #define IMX274_WRITE_VSIZE_REG_MSB 0x3131 11739dd23dcSLuca Ceresoli #define IMX274_Y_OUT_SIZE_REG_LSB 0x3132 11839dd23dcSLuca Ceresoli #define IMX274_Y_OUT_SIZE_REG_MSB 0x3133 1194eb7846dSLuca Ceresoli #define IMX274_VMAX_REG_1 0x30FA /* VMAX, MSB */ 1204eb7846dSLuca Ceresoli #define IMX274_VMAX_REG_2 0x30F9 /* VMAX */ 1214eb7846dSLuca Ceresoli #define IMX274_VMAX_REG_3 0x30F8 /* VMAX, LSB */ 1220985dd30SLeon Luo #define IMX274_HMAX_REG_MSB 0x30F7 /* HMAX */ 1230985dd30SLeon Luo #define IMX274_HMAX_REG_LSB 0x30F6 /* HMAX */ 1240985dd30SLeon Luo #define IMX274_ANALOG_GAIN_ADDR_LSB 0x300A /* ANALOG GAIN LSB */ 1250985dd30SLeon Luo #define IMX274_ANALOG_GAIN_ADDR_MSB 0x300B /* ANALOG GAIN MSB */ 1260985dd30SLeon Luo #define IMX274_DIGITAL_GAIN_REG 0x3012 /* Digital Gain */ 1270985dd30SLeon Luo #define IMX274_VFLIP_REG 0x301A /* VERTICAL FLIP */ 1280985dd30SLeon Luo #define IMX274_TEST_PATTERN_REG 0x303D /* TEST PATTERN */ 1290985dd30SLeon Luo #define IMX274_STANDBY_REG 0x3000 /* STANDBY */ 1300985dd30SLeon Luo 1310985dd30SLeon Luo #define IMX274_TABLE_WAIT_MS 0 1320985dd30SLeon Luo #define IMX274_TABLE_END 1 1330985dd30SLeon Luo 1340985dd30SLeon Luo /* 1350985dd30SLeon Luo * imx274 I2C operation related structure 1360985dd30SLeon Luo */ 1370985dd30SLeon Luo struct reg_8 { 1380985dd30SLeon Luo u16 addr; 1390985dd30SLeon Luo u8 val; 1400985dd30SLeon Luo }; 1410985dd30SLeon Luo 1420985dd30SLeon Luo static const struct regmap_config imx274_regmap_config = { 1430985dd30SLeon Luo .reg_bits = 16, 1440985dd30SLeon Luo .val_bits = 8, 1450985dd30SLeon Luo .cache_type = REGCACHE_RBTREE, 1460985dd30SLeon Luo }; 1470985dd30SLeon Luo 14839dd23dcSLuca Ceresoli enum imx274_binning { 14939dd23dcSLuca Ceresoli IMX274_BINNING_OFF, 15039dd23dcSLuca Ceresoli IMX274_BINNING_2_1, 15139dd23dcSLuca Ceresoli IMX274_BINNING_3_1, 1520985dd30SLeon Luo }; 1530985dd30SLeon Luo 1540985dd30SLeon Luo /* 15596a2c731SLuca Ceresoli * Parameters for each imx274 readout mode. 15696a2c731SLuca Ceresoli * 15796a2c731SLuca Ceresoli * These are the values to configure the sensor in one of the 15896a2c731SLuca Ceresoli * implemented modes. 15996a2c731SLuca Ceresoli * 16096a2c731SLuca Ceresoli * @init_regs: registers to initialize the mode 16139dd23dcSLuca Ceresoli * @bin_ratio: downscale factor (e.g. 3 for 3:1 binning) 16296a2c731SLuca Ceresoli * @min_frame_len: Minimum frame length for each mode (see "Frame Rate 16396a2c731SLuca Ceresoli * Adjustment (CSI-2)" in the datasheet) 16496a2c731SLuca Ceresoli * @min_SHR: Minimum SHR register value (see "Shutter Setting (CSI-2)" in the 16596a2c731SLuca Ceresoli * datasheet) 16696a2c731SLuca Ceresoli * @max_fps: Maximum frames per second 16796a2c731SLuca Ceresoli * @nocpiop: Number of clocks per internal offset period (see "Integration Time 16896a2c731SLuca Ceresoli * in Each Readout Drive Mode (CSI-2)" in the datasheet) 1690985dd30SLeon Luo */ 1709648cb57SLuca Ceresoli struct imx274_mode { 17196a2c731SLuca Ceresoli const struct reg_8 *init_regs; 17239dd23dcSLuca Ceresoli unsigned int bin_ratio; 17396a2c731SLuca Ceresoli int min_frame_len; 17496a2c731SLuca Ceresoli int min_SHR; 17596a2c731SLuca Ceresoli int max_fps; 17696a2c731SLuca Ceresoli int nocpiop; 1770985dd30SLeon Luo }; 1780985dd30SLeon Luo 1790985dd30SLeon Luo /* 1800985dd30SLeon Luo * imx274 test pattern related structure 1810985dd30SLeon Luo */ 1820985dd30SLeon Luo enum { 1830985dd30SLeon Luo TEST_PATTERN_DISABLED = 0, 1840985dd30SLeon Luo TEST_PATTERN_ALL_000H, 1850985dd30SLeon Luo TEST_PATTERN_ALL_FFFH, 1860985dd30SLeon Luo TEST_PATTERN_ALL_555H, 1870985dd30SLeon Luo TEST_PATTERN_ALL_AAAH, 1880985dd30SLeon Luo TEST_PATTERN_VSP_5AH, /* VERTICAL STRIPE PATTERN 555H/AAAH */ 1890985dd30SLeon Luo TEST_PATTERN_VSP_A5H, /* VERTICAL STRIPE PATTERN AAAH/555H */ 1900985dd30SLeon Luo TEST_PATTERN_VSP_05H, /* VERTICAL STRIPE PATTERN 000H/555H */ 1910985dd30SLeon Luo TEST_PATTERN_VSP_50H, /* VERTICAL STRIPE PATTERN 555H/000H */ 1920985dd30SLeon Luo TEST_PATTERN_VSP_0FH, /* VERTICAL STRIPE PATTERN 000H/FFFH */ 1930985dd30SLeon Luo TEST_PATTERN_VSP_F0H, /* VERTICAL STRIPE PATTERN FFFH/000H */ 1940985dd30SLeon Luo TEST_PATTERN_H_COLOR_BARS, 1950985dd30SLeon Luo TEST_PATTERN_V_COLOR_BARS, 1960985dd30SLeon Luo }; 1970985dd30SLeon Luo 1980985dd30SLeon Luo static const char * const tp_qmenu[] = { 1990985dd30SLeon Luo "Disabled", 2000985dd30SLeon Luo "All 000h Pattern", 2010985dd30SLeon Luo "All FFFh Pattern", 2020985dd30SLeon Luo "All 555h Pattern", 2030985dd30SLeon Luo "All AAAh Pattern", 2040985dd30SLeon Luo "Vertical Stripe (555h / AAAh)", 2050985dd30SLeon Luo "Vertical Stripe (AAAh / 555h)", 2060985dd30SLeon Luo "Vertical Stripe (000h / 555h)", 2070985dd30SLeon Luo "Vertical Stripe (555h / 000h)", 2080985dd30SLeon Luo "Vertical Stripe (000h / FFFh)", 2090985dd30SLeon Luo "Vertical Stripe (FFFh / 000h)", 2100985dd30SLeon Luo "Vertical Color Bars", 21147ee7bdeSLuca Ceresoli "Horizontal Color Bars", 2120985dd30SLeon Luo }; 2130985dd30SLeon Luo 2140985dd30SLeon Luo /* 2150985dd30SLeon Luo * All-pixel scan mode (10-bit) 2160985dd30SLeon Luo * imx274 mode1(refer to datasheet) register configuration with 2170985dd30SLeon Luo * 3840x2160 resolution, raw10 data and mipi four lane output 2180985dd30SLeon Luo */ 2190985dd30SLeon Luo static const struct reg_8 imx274_mode1_3840x2160_raw10[] = { 2200985dd30SLeon Luo {0x3004, 0x01}, 2210985dd30SLeon Luo {0x3005, 0x01}, 2220985dd30SLeon Luo {0x3006, 0x00}, 22339dd23dcSLuca Ceresoli {0x3007, 0xa2}, 2240985dd30SLeon Luo 2250985dd30SLeon Luo {0x3018, 0xA2}, /* output XVS, HVS */ 2260985dd30SLeon Luo 2270985dd30SLeon Luo {0x306B, 0x05}, 2280985dd30SLeon Luo {0x30E2, 0x01}, 2290985dd30SLeon Luo 2300985dd30SLeon Luo {0x30EE, 0x01}, 2310985dd30SLeon Luo {0x3342, 0x0A}, 2320985dd30SLeon Luo {0x3343, 0x00}, 2330985dd30SLeon Luo {0x3344, 0x16}, 2340985dd30SLeon Luo {0x3345, 0x00}, 2350985dd30SLeon Luo {0x33A6, 0x01}, 2360985dd30SLeon Luo {0x3528, 0x0E}, 2370985dd30SLeon Luo {0x3554, 0x1F}, 2380985dd30SLeon Luo {0x3555, 0x01}, 2390985dd30SLeon Luo {0x3556, 0x01}, 2400985dd30SLeon Luo {0x3557, 0x01}, 2410985dd30SLeon Luo {0x3558, 0x01}, 2420985dd30SLeon Luo {0x3559, 0x00}, 2430985dd30SLeon Luo {0x355A, 0x00}, 2440985dd30SLeon Luo {0x35BA, 0x0E}, 2450985dd30SLeon Luo {0x366A, 0x1B}, 2460985dd30SLeon Luo {0x366B, 0x1A}, 2470985dd30SLeon Luo {0x366C, 0x19}, 2480985dd30SLeon Luo {0x366D, 0x17}, 2490985dd30SLeon Luo {0x3A41, 0x08}, 2500985dd30SLeon Luo 2510985dd30SLeon Luo {IMX274_TABLE_END, 0x00} 2520985dd30SLeon Luo }; 2530985dd30SLeon Luo 2540985dd30SLeon Luo /* 2550985dd30SLeon Luo * Horizontal/vertical 2/2-line binning 2560985dd30SLeon Luo * (Horizontal and vertical weightedbinning, 10-bit) 2570985dd30SLeon Luo * imx274 mode3(refer to datasheet) register configuration with 2580985dd30SLeon Luo * 1920x1080 resolution, raw10 data and mipi four lane output 2590985dd30SLeon Luo */ 2600985dd30SLeon Luo static const struct reg_8 imx274_mode3_1920x1080_raw10[] = { 2610985dd30SLeon Luo {0x3004, 0x02}, 2620985dd30SLeon Luo {0x3005, 0x21}, 2630985dd30SLeon Luo {0x3006, 0x00}, 26439dd23dcSLuca Ceresoli {0x3007, 0xb1}, 2650985dd30SLeon Luo 2660985dd30SLeon Luo {0x3018, 0xA2}, /* output XVS, HVS */ 2670985dd30SLeon Luo 2680985dd30SLeon Luo {0x306B, 0x05}, 2690985dd30SLeon Luo {0x30E2, 0x02}, 2700985dd30SLeon Luo 2710985dd30SLeon Luo {0x30EE, 0x01}, 2720985dd30SLeon Luo {0x3342, 0x0A}, 2730985dd30SLeon Luo {0x3343, 0x00}, 2740985dd30SLeon Luo {0x3344, 0x1A}, 2750985dd30SLeon Luo {0x3345, 0x00}, 2760985dd30SLeon Luo {0x33A6, 0x01}, 2770985dd30SLeon Luo {0x3528, 0x0E}, 2780985dd30SLeon Luo {0x3554, 0x00}, 2790985dd30SLeon Luo {0x3555, 0x01}, 2800985dd30SLeon Luo {0x3556, 0x01}, 2810985dd30SLeon Luo {0x3557, 0x01}, 2820985dd30SLeon Luo {0x3558, 0x01}, 2830985dd30SLeon Luo {0x3559, 0x00}, 2840985dd30SLeon Luo {0x355A, 0x00}, 2850985dd30SLeon Luo {0x35BA, 0x0E}, 2860985dd30SLeon Luo {0x366A, 0x1B}, 2870985dd30SLeon Luo {0x366B, 0x1A}, 2880985dd30SLeon Luo {0x366C, 0x19}, 2890985dd30SLeon Luo {0x366D, 0x17}, 2900985dd30SLeon Luo {0x3A41, 0x08}, 2910985dd30SLeon Luo 2920985dd30SLeon Luo {IMX274_TABLE_END, 0x00} 2930985dd30SLeon Luo }; 2940985dd30SLeon Luo 2950985dd30SLeon Luo /* 2960985dd30SLeon Luo * Vertical 2/3 subsampling binning horizontal 3 binning 2970985dd30SLeon Luo * imx274 mode5(refer to datasheet) register configuration with 2980985dd30SLeon Luo * 1280x720 resolution, raw10 data and mipi four lane output 2990985dd30SLeon Luo */ 3000985dd30SLeon Luo static const struct reg_8 imx274_mode5_1280x720_raw10[] = { 3010985dd30SLeon Luo {0x3004, 0x03}, 3020985dd30SLeon Luo {0x3005, 0x31}, 3030985dd30SLeon Luo {0x3006, 0x00}, 30439dd23dcSLuca Ceresoli {0x3007, 0xa9}, 3050985dd30SLeon Luo 3060985dd30SLeon Luo {0x3018, 0xA2}, /* output XVS, HVS */ 3070985dd30SLeon Luo 3080985dd30SLeon Luo {0x306B, 0x05}, 3090985dd30SLeon Luo {0x30E2, 0x03}, 3100985dd30SLeon Luo 3110985dd30SLeon Luo {0x30EE, 0x01}, 3120985dd30SLeon Luo {0x3342, 0x0A}, 3130985dd30SLeon Luo {0x3343, 0x00}, 3140985dd30SLeon Luo {0x3344, 0x1B}, 3150985dd30SLeon Luo {0x3345, 0x00}, 3160985dd30SLeon Luo {0x33A6, 0x01}, 3170985dd30SLeon Luo {0x3528, 0x0E}, 3180985dd30SLeon Luo {0x3554, 0x00}, 3190985dd30SLeon Luo {0x3555, 0x01}, 3200985dd30SLeon Luo {0x3556, 0x01}, 3210985dd30SLeon Luo {0x3557, 0x01}, 3220985dd30SLeon Luo {0x3558, 0x01}, 3230985dd30SLeon Luo {0x3559, 0x00}, 3240985dd30SLeon Luo {0x355A, 0x00}, 3250985dd30SLeon Luo {0x35BA, 0x0E}, 3260985dd30SLeon Luo {0x366A, 0x1B}, 3270985dd30SLeon Luo {0x366B, 0x19}, 3280985dd30SLeon Luo {0x366C, 0x17}, 3290985dd30SLeon Luo {0x366D, 0x17}, 3300985dd30SLeon Luo {0x3A41, 0x04}, 3310985dd30SLeon Luo 3320985dd30SLeon Luo {IMX274_TABLE_END, 0x00} 3330985dd30SLeon Luo }; 3340985dd30SLeon Luo 3350985dd30SLeon Luo /* 3360985dd30SLeon Luo * imx274 first step register configuration for 3370985dd30SLeon Luo * starting stream 3380985dd30SLeon Luo */ 3390985dd30SLeon Luo static const struct reg_8 imx274_start_1[] = { 3400985dd30SLeon Luo {IMX274_STANDBY_REG, 0x12}, 3410985dd30SLeon Luo 3427d2332c7SLuca Ceresoli /* PLRD: clock settings */ 3437d2332c7SLuca Ceresoli {0x3120, 0xF0}, 3447d2332c7SLuca Ceresoli {0x3121, 0x00}, 3457d2332c7SLuca Ceresoli {0x3122, 0x02}, 3467d2332c7SLuca Ceresoli {0x3129, 0x9C}, 3477d2332c7SLuca Ceresoli {0x312A, 0x02}, 3487d2332c7SLuca Ceresoli {0x312D, 0x02}, 3490985dd30SLeon Luo 3500985dd30SLeon Luo {0x310B, 0x00}, 3510985dd30SLeon Luo 3520985dd30SLeon Luo /* PLSTMG */ 3530985dd30SLeon Luo {0x304C, 0x00}, /* PLSTMG01 */ 3540985dd30SLeon Luo {0x304D, 0x03}, 3550985dd30SLeon Luo {0x331C, 0x1A}, 3560985dd30SLeon Luo {0x331D, 0x00}, 3570985dd30SLeon Luo {0x3502, 0x02}, 3580985dd30SLeon Luo {0x3529, 0x0E}, 3590985dd30SLeon Luo {0x352A, 0x0E}, 3600985dd30SLeon Luo {0x352B, 0x0E}, 3610985dd30SLeon Luo {0x3538, 0x0E}, 3620985dd30SLeon Luo {0x3539, 0x0E}, 3630985dd30SLeon Luo {0x3553, 0x00}, 3640985dd30SLeon Luo {0x357D, 0x05}, 3650985dd30SLeon Luo {0x357F, 0x05}, 3660985dd30SLeon Luo {0x3581, 0x04}, 3670985dd30SLeon Luo {0x3583, 0x76}, 3680985dd30SLeon Luo {0x3587, 0x01}, 3690985dd30SLeon Luo {0x35BB, 0x0E}, 3700985dd30SLeon Luo {0x35BC, 0x0E}, 3710985dd30SLeon Luo {0x35BD, 0x0E}, 3720985dd30SLeon Luo {0x35BE, 0x0E}, 3730985dd30SLeon Luo {0x35BF, 0x0E}, 3740985dd30SLeon Luo {0x366E, 0x00}, 3750985dd30SLeon Luo {0x366F, 0x00}, 3760985dd30SLeon Luo {0x3670, 0x00}, 3770985dd30SLeon Luo {0x3671, 0x00}, 3780985dd30SLeon Luo 3790985dd30SLeon Luo /* PSMIPI */ 3800985dd30SLeon Luo {0x3304, 0x32}, /* PSMIPI1 */ 3810985dd30SLeon Luo {0x3305, 0x00}, 3820985dd30SLeon Luo {0x3306, 0x32}, 3830985dd30SLeon Luo {0x3307, 0x00}, 3840985dd30SLeon Luo {0x3590, 0x32}, 3850985dd30SLeon Luo {0x3591, 0x00}, 3860985dd30SLeon Luo {0x3686, 0x32}, 3870985dd30SLeon Luo {0x3687, 0x00}, 3880985dd30SLeon Luo 3890985dd30SLeon Luo {IMX274_TABLE_END, 0x00} 3900985dd30SLeon Luo }; 3910985dd30SLeon Luo 3920985dd30SLeon Luo /* 3937d2332c7SLuca Ceresoli * imx274 second step register configuration for 3940985dd30SLeon Luo * starting stream 3950985dd30SLeon Luo */ 3967d2332c7SLuca Ceresoli static const struct reg_8 imx274_start_2[] = { 3970985dd30SLeon Luo {IMX274_STANDBY_REG, 0x00}, 3980985dd30SLeon Luo {0x303E, 0x02}, /* SYS_MODE = 2 */ 3990985dd30SLeon Luo {IMX274_TABLE_END, 0x00} 4000985dd30SLeon Luo }; 4010985dd30SLeon Luo 4020985dd30SLeon Luo /* 4037d2332c7SLuca Ceresoli * imx274 third step register configuration for 4040985dd30SLeon Luo * starting stream 4050985dd30SLeon Luo */ 4067d2332c7SLuca Ceresoli static const struct reg_8 imx274_start_3[] = { 4070985dd30SLeon Luo {0x30F4, 0x00}, 4080985dd30SLeon Luo {0x3018, 0xA2}, /* XHS VHS OUTUPT */ 4090985dd30SLeon Luo {IMX274_TABLE_END, 0x00} 4100985dd30SLeon Luo }; 4110985dd30SLeon Luo 4120985dd30SLeon Luo /* 4130985dd30SLeon Luo * imx274 register configuration for stoping stream 4140985dd30SLeon Luo */ 4150985dd30SLeon Luo static const struct reg_8 imx274_stop[] = { 4160985dd30SLeon Luo {IMX274_STANDBY_REG, 0x01}, 4170985dd30SLeon Luo {IMX274_TABLE_END, 0x00} 4180985dd30SLeon Luo }; 4190985dd30SLeon Luo 4200985dd30SLeon Luo /* 4210985dd30SLeon Luo * imx274 disable test pattern register configuration 4220985dd30SLeon Luo */ 4230985dd30SLeon Luo static const struct reg_8 imx274_tp_disabled[] = { 4240985dd30SLeon Luo {0x303C, 0x00}, 4250985dd30SLeon Luo {0x377F, 0x00}, 4260985dd30SLeon Luo {0x3781, 0x00}, 4270985dd30SLeon Luo {0x370B, 0x00}, 4280985dd30SLeon Luo {IMX274_TABLE_END, 0x00} 4290985dd30SLeon Luo }; 4300985dd30SLeon Luo 4310985dd30SLeon Luo /* 4320985dd30SLeon Luo * imx274 test pattern register configuration 4330985dd30SLeon Luo * reg 0x303D defines the test pattern modes 4340985dd30SLeon Luo */ 4350985dd30SLeon Luo static const struct reg_8 imx274_tp_regs[] = { 4360985dd30SLeon Luo {0x303C, 0x11}, 4370985dd30SLeon Luo {0x370E, 0x01}, 4380985dd30SLeon Luo {0x377F, 0x01}, 4390985dd30SLeon Luo {0x3781, 0x01}, 4400985dd30SLeon Luo {0x370B, 0x11}, 4410985dd30SLeon Luo {IMX274_TABLE_END, 0x00} 4420985dd30SLeon Luo }; 4430985dd30SLeon Luo 44496a2c731SLuca Ceresoli /* nocpiop happens to be the same number for the implemented modes */ 4459648cb57SLuca Ceresoli static const struct imx274_mode imx274_modes[] = { 44696a2c731SLuca Ceresoli { 44796a2c731SLuca Ceresoli /* mode 1, 4K */ 44839dd23dcSLuca Ceresoli .bin_ratio = 1, 44996a2c731SLuca Ceresoli .init_regs = imx274_mode1_3840x2160_raw10, 45096a2c731SLuca Ceresoli .min_frame_len = 4550, 45196a2c731SLuca Ceresoli .min_SHR = 12, 45296a2c731SLuca Ceresoli .max_fps = 60, 45396a2c731SLuca Ceresoli .nocpiop = 112, 45496a2c731SLuca Ceresoli }, 45596a2c731SLuca Ceresoli { 45696a2c731SLuca Ceresoli /* mode 3, 1080p */ 45739dd23dcSLuca Ceresoli .bin_ratio = 2, 45896a2c731SLuca Ceresoli .init_regs = imx274_mode3_1920x1080_raw10, 45996a2c731SLuca Ceresoli .min_frame_len = 2310, 46096a2c731SLuca Ceresoli .min_SHR = 8, 46196a2c731SLuca Ceresoli .max_fps = 120, 46296a2c731SLuca Ceresoli .nocpiop = 112, 46396a2c731SLuca Ceresoli }, 46496a2c731SLuca Ceresoli { 46596a2c731SLuca Ceresoli /* mode 5, 720p */ 46639dd23dcSLuca Ceresoli .bin_ratio = 3, 46796a2c731SLuca Ceresoli .init_regs = imx274_mode5_1280x720_raw10, 46896a2c731SLuca Ceresoli .min_frame_len = 2310, 46996a2c731SLuca Ceresoli .min_SHR = 8, 47096a2c731SLuca Ceresoli .max_fps = 120, 47196a2c731SLuca Ceresoli .nocpiop = 112, 47296a2c731SLuca Ceresoli }, 4730985dd30SLeon Luo }; 4740985dd30SLeon Luo 4750985dd30SLeon Luo /* 4760985dd30SLeon Luo * struct imx274_ctrls - imx274 ctrl structure 4770985dd30SLeon Luo * @handler: V4L2 ctrl handler structure 4780985dd30SLeon Luo * @exposure: Pointer to expsure ctrl structure 4790985dd30SLeon Luo * @gain: Pointer to gain ctrl structure 4800985dd30SLeon Luo * @vflip: Pointer to vflip ctrl structure 4810985dd30SLeon Luo * @test_pattern: Pointer to test pattern ctrl structure 4820985dd30SLeon Luo */ 4830985dd30SLeon Luo struct imx274_ctrls { 4840985dd30SLeon Luo struct v4l2_ctrl_handler handler; 4850985dd30SLeon Luo struct v4l2_ctrl *exposure; 4860985dd30SLeon Luo struct v4l2_ctrl *gain; 4870985dd30SLeon Luo struct v4l2_ctrl *vflip; 4880985dd30SLeon Luo struct v4l2_ctrl *test_pattern; 4890985dd30SLeon Luo }; 4900985dd30SLeon Luo 4910985dd30SLeon Luo /* 4920985dd30SLeon Luo * struct stim274 - imx274 device structure 4930985dd30SLeon Luo * @sd: V4L2 subdevice structure 49419d38b23SLuca Ceresoli * @pad: Media pad structure 4950985dd30SLeon Luo * @client: Pointer to I2C client 4960985dd30SLeon Luo * @ctrls: imx274 control structure 49739dd23dcSLuca Ceresoli * @crop: rect to be captured 49839dd23dcSLuca Ceresoli * @compose: compose rect, i.e. output resolution 4990985dd30SLeon Luo * @format: V4L2 media bus frame format structure 50039dd23dcSLuca Ceresoli * (width and height are in sync with the compose rect) 5010985dd30SLeon Luo * @frame_rate: V4L2 frame rate structure 5020985dd30SLeon Luo * @regmap: Pointer to regmap structure 5030985dd30SLeon Luo * @reset_gpio: Pointer to reset gpio 5040985dd30SLeon Luo * @lock: Mutex structure 50596a2c731SLuca Ceresoli * @mode: Parameters for the selected readout mode 5060985dd30SLeon Luo */ 5070985dd30SLeon Luo struct stimx274 { 5080985dd30SLeon Luo struct v4l2_subdev sd; 5090985dd30SLeon Luo struct media_pad pad; 5100985dd30SLeon Luo struct i2c_client *client; 5110985dd30SLeon Luo struct imx274_ctrls ctrls; 51239dd23dcSLuca Ceresoli struct v4l2_rect crop; 5130985dd30SLeon Luo struct v4l2_mbus_framefmt format; 5140985dd30SLeon Luo struct v4l2_fract frame_interval; 5150985dd30SLeon Luo struct regmap *regmap; 5160985dd30SLeon Luo struct gpio_desc *reset_gpio; 5170985dd30SLeon Luo struct mutex lock; /* mutex lock for operations */ 5189648cb57SLuca Ceresoli const struct imx274_mode *mode; 5190985dd30SLeon Luo }; 5200985dd30SLeon Luo 52139dd23dcSLuca Ceresoli #define IMX274_ROUND(dim, step, flags) \ 52239dd23dcSLuca Ceresoli ((flags) & V4L2_SEL_FLAG_GE \ 52339dd23dcSLuca Ceresoli ? roundup((dim), (step)) \ 52439dd23dcSLuca Ceresoli : ((flags) & V4L2_SEL_FLAG_LE \ 52539dd23dcSLuca Ceresoli ? rounddown((dim), (step)) \ 52639dd23dcSLuca Ceresoli : rounddown((dim) + (step) / 2, (step)))) 52739dd23dcSLuca Ceresoli 5280985dd30SLeon Luo /* 5290985dd30SLeon Luo * Function declaration 5300985dd30SLeon Luo */ 5310985dd30SLeon Luo static int imx274_set_gain(struct stimx274 *priv, struct v4l2_ctrl *ctrl); 5320985dd30SLeon Luo static int imx274_set_exposure(struct stimx274 *priv, int val); 5330985dd30SLeon Luo static int imx274_set_vflip(struct stimx274 *priv, int val); 5340985dd30SLeon Luo static int imx274_set_test_pattern(struct stimx274 *priv, int val); 5350985dd30SLeon Luo static int imx274_set_frame_interval(struct stimx274 *priv, 5360985dd30SLeon Luo struct v4l2_fract frame_interval); 5370985dd30SLeon Luo 5380985dd30SLeon Luo static inline void msleep_range(unsigned int delay_base) 5390985dd30SLeon Luo { 5400985dd30SLeon Luo usleep_range(delay_base * 1000, delay_base * 1000 + 500); 5410985dd30SLeon Luo } 5420985dd30SLeon Luo 5430985dd30SLeon Luo /* 5440985dd30SLeon Luo * v4l2_ctrl and v4l2_subdev related operations 5450985dd30SLeon Luo */ 5460985dd30SLeon Luo static inline struct v4l2_subdev *ctrl_to_sd(struct v4l2_ctrl *ctrl) 5470985dd30SLeon Luo { 5480985dd30SLeon Luo return &container_of(ctrl->handler, 5490985dd30SLeon Luo struct stimx274, ctrls.handler)->sd; 5500985dd30SLeon Luo } 5510985dd30SLeon Luo 5520985dd30SLeon Luo static inline struct stimx274 *to_imx274(struct v4l2_subdev *sd) 5530985dd30SLeon Luo { 5540985dd30SLeon Luo return container_of(sd, struct stimx274, sd); 5550985dd30SLeon Luo } 5560985dd30SLeon Luo 5570985dd30SLeon Luo /* 5587ff67863SLuca Ceresoli * Writing a register table 5597ff67863SLuca Ceresoli * 5607ff67863SLuca Ceresoli * @priv: Pointer to device 5617ff67863SLuca Ceresoli * @table: Table containing register values (with optional delays) 5620985dd30SLeon Luo * 5630985dd30SLeon Luo * This is used to write register table into sensor's reg map. 5640985dd30SLeon Luo * 5650985dd30SLeon Luo * Return: 0 on success, errors otherwise 5660985dd30SLeon Luo */ 5677ff67863SLuca Ceresoli static int imx274_write_table(struct stimx274 *priv, const struct reg_8 table[]) 5680985dd30SLeon Luo { 5697ff67863SLuca Ceresoli struct regmap *regmap = priv->regmap; 570021741adSDan Carpenter int err = 0; 5710985dd30SLeon Luo const struct reg_8 *next; 5720985dd30SLeon Luo u8 val; 5730985dd30SLeon Luo 5740985dd30SLeon Luo int range_start = -1; 5750985dd30SLeon Luo int range_count = 0; 5760985dd30SLeon Luo u8 range_vals[16]; 5770985dd30SLeon Luo int max_range_vals = ARRAY_SIZE(range_vals); 5780985dd30SLeon Luo 5790985dd30SLeon Luo for (next = table;; next++) { 5800985dd30SLeon Luo if ((next->addr != range_start + range_count) || 5817ff67863SLuca Ceresoli (next->addr == IMX274_TABLE_END) || 5827ff67863SLuca Ceresoli (next->addr == IMX274_TABLE_WAIT_MS) || 5830985dd30SLeon Luo (range_count == max_range_vals)) { 5840985dd30SLeon Luo if (range_count == 1) 5850985dd30SLeon Luo err = regmap_write(regmap, 5860985dd30SLeon Luo range_start, range_vals[0]); 5870985dd30SLeon Luo else if (range_count > 1) 5880985dd30SLeon Luo err = regmap_bulk_write(regmap, range_start, 5890985dd30SLeon Luo &range_vals[0], 5900985dd30SLeon Luo range_count); 59100b4bac7SMauro Carvalho Chehab else 59200b4bac7SMauro Carvalho Chehab err = 0; 5930985dd30SLeon Luo 5940985dd30SLeon Luo if (err) 5950985dd30SLeon Luo return err; 5960985dd30SLeon Luo 5970985dd30SLeon Luo range_start = -1; 5980985dd30SLeon Luo range_count = 0; 5990985dd30SLeon Luo 6000985dd30SLeon Luo /* Handle special address values */ 6017ff67863SLuca Ceresoli if (next->addr == IMX274_TABLE_END) 6020985dd30SLeon Luo break; 6030985dd30SLeon Luo 6047ff67863SLuca Ceresoli if (next->addr == IMX274_TABLE_WAIT_MS) { 6050985dd30SLeon Luo msleep_range(next->val); 6060985dd30SLeon Luo continue; 6070985dd30SLeon Luo } 6080985dd30SLeon Luo } 6090985dd30SLeon Luo 6100985dd30SLeon Luo val = next->val; 6110985dd30SLeon Luo 6120985dd30SLeon Luo if (range_start == -1) 6130985dd30SLeon Luo range_start = next->addr; 6140985dd30SLeon Luo 6150985dd30SLeon Luo range_vals[range_count++] = val; 6160985dd30SLeon Luo } 6170985dd30SLeon Luo return 0; 6180985dd30SLeon Luo } 6190985dd30SLeon Luo 6200985dd30SLeon Luo static inline int imx274_read_reg(struct stimx274 *priv, u16 addr, u8 *val) 6210985dd30SLeon Luo { 622cea8c007SLuca Ceresoli unsigned int uint_val; 6230985dd30SLeon Luo int err; 6240985dd30SLeon Luo 625cea8c007SLuca Ceresoli err = regmap_read(priv->regmap, addr, &uint_val); 6260985dd30SLeon Luo if (err) 6270985dd30SLeon Luo dev_err(&priv->client->dev, 6280985dd30SLeon Luo "%s : i2c read failed, addr = %x\n", __func__, addr); 6290985dd30SLeon Luo else 6300985dd30SLeon Luo dev_dbg(&priv->client->dev, 6310985dd30SLeon Luo "%s : addr 0x%x, val=0x%x\n", __func__, 632cea8c007SLuca Ceresoli addr, uint_val); 633cea8c007SLuca Ceresoli 634cea8c007SLuca Ceresoli *val = uint_val; 6350985dd30SLeon Luo return err; 6360985dd30SLeon Luo } 6370985dd30SLeon Luo 6380985dd30SLeon Luo static inline int imx274_write_reg(struct stimx274 *priv, u16 addr, u8 val) 6390985dd30SLeon Luo { 6400985dd30SLeon Luo int err; 6410985dd30SLeon Luo 6420985dd30SLeon Luo err = regmap_write(priv->regmap, addr, val); 6430985dd30SLeon Luo if (err) 6440985dd30SLeon Luo dev_err(&priv->client->dev, 6450985dd30SLeon Luo "%s : i2c write failed, %x = %x\n", __func__, 6460985dd30SLeon Luo addr, val); 6470985dd30SLeon Luo else 6480985dd30SLeon Luo dev_dbg(&priv->client->dev, 6490985dd30SLeon Luo "%s : addr 0x%x, val=0x%x\n", __func__, 6500985dd30SLeon Luo addr, val); 6510985dd30SLeon Luo return err; 6520985dd30SLeon Luo } 6530985dd30SLeon Luo 654279b4b9aSLuca Ceresoli /** 655ca017467SLuca Ceresoli * Read a multibyte register. 656ca017467SLuca Ceresoli * 657ca017467SLuca Ceresoli * Uses a bulk read where possible. 658ca017467SLuca Ceresoli * 659ca017467SLuca Ceresoli * @priv: Pointer to device structure 660ca017467SLuca Ceresoli * @addr: Address of the LSB register. Other registers must be 661ca017467SLuca Ceresoli * consecutive, least-to-most significant. 662ca017467SLuca Ceresoli * @val: Pointer to store the register value (cpu endianness) 663ca017467SLuca Ceresoli * @nbytes: Number of bytes to read (range: [1..3]). 664ca017467SLuca Ceresoli * Other bytes are zet to 0. 665ca017467SLuca Ceresoli * 666ca017467SLuca Ceresoli * Return: 0 on success, errors otherwise 667ca017467SLuca Ceresoli */ 668ca017467SLuca Ceresoli static int imx274_read_mbreg(struct stimx274 *priv, u16 addr, u32 *val, 669ca017467SLuca Ceresoli size_t nbytes) 670ca017467SLuca Ceresoli { 671ca017467SLuca Ceresoli __le32 val_le = 0; 672ca017467SLuca Ceresoli int err; 673ca017467SLuca Ceresoli 674ca017467SLuca Ceresoli err = regmap_bulk_read(priv->regmap, addr, &val_le, nbytes); 675ca017467SLuca Ceresoli if (err) { 676ca017467SLuca Ceresoli dev_err(&priv->client->dev, 677ca017467SLuca Ceresoli "%s : i2c bulk read failed, %x (%zu bytes)\n", 678ca017467SLuca Ceresoli __func__, addr, nbytes); 679ca017467SLuca Ceresoli } else { 680ca017467SLuca Ceresoli *val = le32_to_cpu(val_le); 681ca017467SLuca Ceresoli dev_dbg(&priv->client->dev, 682ca017467SLuca Ceresoli "%s : addr 0x%x, val=0x%x (%zu bytes)\n", 683ca017467SLuca Ceresoli __func__, addr, *val, nbytes); 684ca017467SLuca Ceresoli } 685ca017467SLuca Ceresoli 686ca017467SLuca Ceresoli return err; 687ca017467SLuca Ceresoli } 688ca017467SLuca Ceresoli 689ca017467SLuca Ceresoli /** 690279b4b9aSLuca Ceresoli * Write a multibyte register. 691279b4b9aSLuca Ceresoli * 692279b4b9aSLuca Ceresoli * Uses a bulk write where possible. 693279b4b9aSLuca Ceresoli * 694279b4b9aSLuca Ceresoli * @priv: Pointer to device structure 695279b4b9aSLuca Ceresoli * @addr: Address of the LSB register. Other registers must be 696279b4b9aSLuca Ceresoli * consecutive, least-to-most significant. 697279b4b9aSLuca Ceresoli * @val: Value to be written to the register (cpu endianness) 6981657c28dSLuca Ceresoli * @nbytes: Number of bytes to write (range: [1..3]) 699279b4b9aSLuca Ceresoli */ 700279b4b9aSLuca Ceresoli static int imx274_write_mbreg(struct stimx274 *priv, u16 addr, u32 val, 701279b4b9aSLuca Ceresoli size_t nbytes) 702279b4b9aSLuca Ceresoli { 703279b4b9aSLuca Ceresoli __le32 val_le = cpu_to_le32(val); 704279b4b9aSLuca Ceresoli int err; 705279b4b9aSLuca Ceresoli 706279b4b9aSLuca Ceresoli err = regmap_bulk_write(priv->regmap, addr, &val_le, nbytes); 707279b4b9aSLuca Ceresoli if (err) 708279b4b9aSLuca Ceresoli dev_err(&priv->client->dev, 709279b4b9aSLuca Ceresoli "%s : i2c bulk write failed, %x = %x (%zu bytes)\n", 710279b4b9aSLuca Ceresoli __func__, addr, val, nbytes); 711279b4b9aSLuca Ceresoli else 712279b4b9aSLuca Ceresoli dev_dbg(&priv->client->dev, 713279b4b9aSLuca Ceresoli "%s : addr 0x%x, val=0x%x (%zu bytes)\n", 714279b4b9aSLuca Ceresoli __func__, addr, val, nbytes); 715279b4b9aSLuca Ceresoli return err; 716279b4b9aSLuca Ceresoli } 717279b4b9aSLuca Ceresoli 7180985dd30SLeon Luo /* 71996a2c731SLuca Ceresoli * Set mode registers to start stream. 7200985dd30SLeon Luo * @priv: Pointer to device structure 7210985dd30SLeon Luo * 7220985dd30SLeon Luo * Return: 0 on success, errors otherwise 7230985dd30SLeon Luo */ 72496a2c731SLuca Ceresoli static int imx274_mode_regs(struct stimx274 *priv) 7250985dd30SLeon Luo { 7260985dd30SLeon Luo int err = 0; 7270985dd30SLeon Luo 7288ed8bba7SLuca Ceresoli err = imx274_write_table(priv, imx274_start_1); 7290985dd30SLeon Luo if (err) 7300985dd30SLeon Luo return err; 7310985dd30SLeon Luo 73296a2c731SLuca Ceresoli err = imx274_write_table(priv, priv->mode->init_regs); 7330985dd30SLeon Luo 7340985dd30SLeon Luo return err; 7350985dd30SLeon Luo } 7360985dd30SLeon Luo 7370985dd30SLeon Luo /* 7380985dd30SLeon Luo * imx274_start_stream - Function for starting stream per mode index 7390985dd30SLeon Luo * @priv: Pointer to device structure 7400985dd30SLeon Luo * 7410985dd30SLeon Luo * Return: 0 on success, errors otherwise 7420985dd30SLeon Luo */ 7430985dd30SLeon Luo static int imx274_start_stream(struct stimx274 *priv) 7440985dd30SLeon Luo { 7450985dd30SLeon Luo int err = 0; 7460985dd30SLeon Luo 7470985dd30SLeon Luo /* 7480985dd30SLeon Luo * Refer to "Standby Cancel Sequence when using CSI-2" in 7490985dd30SLeon Luo * imx274 datasheet, it should wait 10ms or more here. 7500985dd30SLeon Luo * give it 1 extra ms for margin 7510985dd30SLeon Luo */ 7520985dd30SLeon Luo msleep_range(11); 7537d2332c7SLuca Ceresoli err = imx274_write_table(priv, imx274_start_2); 7540985dd30SLeon Luo if (err) 7550985dd30SLeon Luo return err; 7560985dd30SLeon Luo 7570985dd30SLeon Luo /* 7580985dd30SLeon Luo * Refer to "Standby Cancel Sequence when using CSI-2" in 7590985dd30SLeon Luo * imx274 datasheet, it should wait 7ms or more here. 7600985dd30SLeon Luo * give it 1 extra ms for margin 7610985dd30SLeon Luo */ 7620985dd30SLeon Luo msleep_range(8); 7637d2332c7SLuca Ceresoli err = imx274_write_table(priv, imx274_start_3); 7640985dd30SLeon Luo if (err) 7650985dd30SLeon Luo return err; 7660985dd30SLeon Luo 7670985dd30SLeon Luo return 0; 7680985dd30SLeon Luo } 7690985dd30SLeon Luo 7700985dd30SLeon Luo /* 7710985dd30SLeon Luo * imx274_reset - Function called to reset the sensor 7720985dd30SLeon Luo * @priv: Pointer to device structure 7730985dd30SLeon Luo * @rst: Input value for determining the sensor's end state after reset 7740985dd30SLeon Luo * 7750985dd30SLeon Luo * Set the senor in reset and then 7760985dd30SLeon Luo * if rst = 0, keep it in reset; 7770985dd30SLeon Luo * if rst = 1, bring it out of reset. 7780985dd30SLeon Luo * 7790985dd30SLeon Luo */ 7800985dd30SLeon Luo static void imx274_reset(struct stimx274 *priv, int rst) 7810985dd30SLeon Luo { 7820985dd30SLeon Luo gpiod_set_value_cansleep(priv->reset_gpio, 0); 7830985dd30SLeon Luo usleep_range(IMX274_RESET_DELAY1, IMX274_RESET_DELAY2); 7840985dd30SLeon Luo gpiod_set_value_cansleep(priv->reset_gpio, !!rst); 7850985dd30SLeon Luo usleep_range(IMX274_RESET_DELAY1, IMX274_RESET_DELAY2); 7860985dd30SLeon Luo } 7870985dd30SLeon Luo 7880985dd30SLeon Luo /** 7890985dd30SLeon Luo * imx274_s_ctrl - This is used to set the imx274 V4L2 controls 7900985dd30SLeon Luo * @ctrl: V4L2 control to be set 7910985dd30SLeon Luo * 7920985dd30SLeon Luo * This function is used to set the V4L2 controls for the imx274 sensor. 7930985dd30SLeon Luo * 7940985dd30SLeon Luo * Return: 0 on success, errors otherwise 7950985dd30SLeon Luo */ 7960985dd30SLeon Luo static int imx274_s_ctrl(struct v4l2_ctrl *ctrl) 7970985dd30SLeon Luo { 7980985dd30SLeon Luo struct v4l2_subdev *sd = ctrl_to_sd(ctrl); 7990985dd30SLeon Luo struct stimx274 *imx274 = to_imx274(sd); 8000985dd30SLeon Luo int ret = -EINVAL; 8010985dd30SLeon Luo 8020985dd30SLeon Luo dev_dbg(&imx274->client->dev, 8030985dd30SLeon Luo "%s : s_ctrl: %s, value: %d\n", __func__, 8040985dd30SLeon Luo ctrl->name, ctrl->val); 8050985dd30SLeon Luo 8060985dd30SLeon Luo switch (ctrl->id) { 8070985dd30SLeon Luo case V4L2_CID_EXPOSURE: 8080985dd30SLeon Luo dev_dbg(&imx274->client->dev, 8090985dd30SLeon Luo "%s : set V4L2_CID_EXPOSURE\n", __func__); 8100985dd30SLeon Luo ret = imx274_set_exposure(imx274, ctrl->val); 8110985dd30SLeon Luo break; 8120985dd30SLeon Luo 8130985dd30SLeon Luo case V4L2_CID_GAIN: 8140985dd30SLeon Luo dev_dbg(&imx274->client->dev, 8150985dd30SLeon Luo "%s : set V4L2_CID_GAIN\n", __func__); 8160985dd30SLeon Luo ret = imx274_set_gain(imx274, ctrl); 8170985dd30SLeon Luo break; 8180985dd30SLeon Luo 8190985dd30SLeon Luo case V4L2_CID_VFLIP: 8200985dd30SLeon Luo dev_dbg(&imx274->client->dev, 8210985dd30SLeon Luo "%s : set V4L2_CID_VFLIP\n", __func__); 8220985dd30SLeon Luo ret = imx274_set_vflip(imx274, ctrl->val); 8230985dd30SLeon Luo break; 8240985dd30SLeon Luo 8250985dd30SLeon Luo case V4L2_CID_TEST_PATTERN: 8260985dd30SLeon Luo dev_dbg(&imx274->client->dev, 8270985dd30SLeon Luo "%s : set V4L2_CID_TEST_PATTERN\n", __func__); 8280985dd30SLeon Luo ret = imx274_set_test_pattern(imx274, ctrl->val); 8290985dd30SLeon Luo break; 8300985dd30SLeon Luo } 8310985dd30SLeon Luo 8320985dd30SLeon Luo return ret; 8330985dd30SLeon Luo } 8340985dd30SLeon Luo 83539dd23dcSLuca Ceresoli static int imx274_binning_goodness(struct stimx274 *imx274, 83639dd23dcSLuca Ceresoli int w, int ask_w, 83739dd23dcSLuca Ceresoli int h, int ask_h, u32 flags) 83839dd23dcSLuca Ceresoli { 83939dd23dcSLuca Ceresoli struct device *dev = &imx274->client->dev; 84039dd23dcSLuca Ceresoli const int goodness = 100000; 84139dd23dcSLuca Ceresoli int val = 0; 84239dd23dcSLuca Ceresoli 84339dd23dcSLuca Ceresoli if (flags & V4L2_SEL_FLAG_GE) { 84439dd23dcSLuca Ceresoli if (w < ask_w) 84539dd23dcSLuca Ceresoli val -= goodness; 84639dd23dcSLuca Ceresoli if (h < ask_h) 84739dd23dcSLuca Ceresoli val -= goodness; 84839dd23dcSLuca Ceresoli } 84939dd23dcSLuca Ceresoli 85039dd23dcSLuca Ceresoli if (flags & V4L2_SEL_FLAG_LE) { 85139dd23dcSLuca Ceresoli if (w > ask_w) 85239dd23dcSLuca Ceresoli val -= goodness; 85339dd23dcSLuca Ceresoli if (h > ask_h) 85439dd23dcSLuca Ceresoli val -= goodness; 85539dd23dcSLuca Ceresoli } 85639dd23dcSLuca Ceresoli 85739dd23dcSLuca Ceresoli val -= abs(w - ask_w); 85839dd23dcSLuca Ceresoli val -= abs(h - ask_h); 85939dd23dcSLuca Ceresoli 86039dd23dcSLuca Ceresoli dev_dbg(dev, "%s: ask %dx%d, size %dx%d, goodness %d\n", 86139dd23dcSLuca Ceresoli __func__, ask_w, ask_h, w, h, val); 86239dd23dcSLuca Ceresoli 86339dd23dcSLuca Ceresoli return val; 86439dd23dcSLuca Ceresoli } 86539dd23dcSLuca Ceresoli 86639dd23dcSLuca Ceresoli /** 86739dd23dcSLuca Ceresoli * Helper function to change binning and set both compose and format. 86839dd23dcSLuca Ceresoli * 86939dd23dcSLuca Ceresoli * We have two entry points to change binning: set_fmt and 87039dd23dcSLuca Ceresoli * set_selection(COMPOSE). Both have to compute the new output size 87139dd23dcSLuca Ceresoli * and set it in both the compose rect and the frame format size. We 87239dd23dcSLuca Ceresoli * also need to do the same things after setting cropping to restore 87339dd23dcSLuca Ceresoli * 1:1 binning. 87439dd23dcSLuca Ceresoli * 87539dd23dcSLuca Ceresoli * This function contains the common code for these three cases, it 87639dd23dcSLuca Ceresoli * has many arguments in order to accommodate the needs of all of 87739dd23dcSLuca Ceresoli * them. 87839dd23dcSLuca Ceresoli * 87939dd23dcSLuca Ceresoli * Must be called with imx274->lock locked. 88039dd23dcSLuca Ceresoli * 88139dd23dcSLuca Ceresoli * @imx274: The device object 88239dd23dcSLuca Ceresoli * @cfg: The pad config we are editing for TRY requests 88339dd23dcSLuca Ceresoli * @which: V4L2_SUBDEV_FORMAT_ACTIVE or V4L2_SUBDEV_FORMAT_TRY from the caller 88439dd23dcSLuca Ceresoli * @width: Input-output parameter: set to the desired width before 88539dd23dcSLuca Ceresoli * the call, contains the chosen value after returning successfully 88639dd23dcSLuca Ceresoli * @height: Input-output parameter for height (see @width) 88739dd23dcSLuca Ceresoli * @flags: Selection flags from struct v4l2_subdev_selection, or 0 if not 88839dd23dcSLuca Ceresoli * available (when called from set_fmt) 88939dd23dcSLuca Ceresoli */ 89039dd23dcSLuca Ceresoli static int __imx274_change_compose(struct stimx274 *imx274, 89139dd23dcSLuca Ceresoli struct v4l2_subdev_pad_config *cfg, 89239dd23dcSLuca Ceresoli u32 which, 89339dd23dcSLuca Ceresoli u32 *width, 89439dd23dcSLuca Ceresoli u32 *height, 89539dd23dcSLuca Ceresoli u32 flags) 89639dd23dcSLuca Ceresoli { 89739dd23dcSLuca Ceresoli struct device *dev = &imx274->client->dev; 89839dd23dcSLuca Ceresoli const struct v4l2_rect *cur_crop; 89939dd23dcSLuca Ceresoli struct v4l2_mbus_framefmt *tgt_fmt; 90039dd23dcSLuca Ceresoli unsigned int i; 9019648cb57SLuca Ceresoli const struct imx274_mode *best_mode = &imx274_modes[0]; 90239dd23dcSLuca Ceresoli int best_goodness = INT_MIN; 90339dd23dcSLuca Ceresoli 90439dd23dcSLuca Ceresoli if (which == V4L2_SUBDEV_FORMAT_TRY) { 90539dd23dcSLuca Ceresoli cur_crop = &cfg->try_crop; 90639dd23dcSLuca Ceresoli tgt_fmt = &cfg->try_fmt; 90739dd23dcSLuca Ceresoli } else { 90839dd23dcSLuca Ceresoli cur_crop = &imx274->crop; 90939dd23dcSLuca Ceresoli tgt_fmt = &imx274->format; 91039dd23dcSLuca Ceresoli } 91139dd23dcSLuca Ceresoli 9129648cb57SLuca Ceresoli for (i = 0; i < ARRAY_SIZE(imx274_modes); i++) { 9139648cb57SLuca Ceresoli unsigned int ratio = imx274_modes[i].bin_ratio; 91439dd23dcSLuca Ceresoli 91539dd23dcSLuca Ceresoli int goodness = imx274_binning_goodness( 91639dd23dcSLuca Ceresoli imx274, 91739dd23dcSLuca Ceresoli cur_crop->width / ratio, *width, 91839dd23dcSLuca Ceresoli cur_crop->height / ratio, *height, 91939dd23dcSLuca Ceresoli flags); 92039dd23dcSLuca Ceresoli 92139dd23dcSLuca Ceresoli if (goodness >= best_goodness) { 92239dd23dcSLuca Ceresoli best_goodness = goodness; 9239648cb57SLuca Ceresoli best_mode = &imx274_modes[i]; 92439dd23dcSLuca Ceresoli } 92539dd23dcSLuca Ceresoli } 92639dd23dcSLuca Ceresoli 92739dd23dcSLuca Ceresoli *width = cur_crop->width / best_mode->bin_ratio; 92839dd23dcSLuca Ceresoli *height = cur_crop->height / best_mode->bin_ratio; 92939dd23dcSLuca Ceresoli 93039dd23dcSLuca Ceresoli if (which == V4L2_SUBDEV_FORMAT_ACTIVE) 93139dd23dcSLuca Ceresoli imx274->mode = best_mode; 93239dd23dcSLuca Ceresoli 93339dd23dcSLuca Ceresoli dev_dbg(dev, "%s: selected %u:1 binning\n", 93439dd23dcSLuca Ceresoli __func__, best_mode->bin_ratio); 93539dd23dcSLuca Ceresoli 93639dd23dcSLuca Ceresoli tgt_fmt->width = *width; 93739dd23dcSLuca Ceresoli tgt_fmt->height = *height; 93839dd23dcSLuca Ceresoli tgt_fmt->field = V4L2_FIELD_NONE; 93939dd23dcSLuca Ceresoli 94039dd23dcSLuca Ceresoli return 0; 94139dd23dcSLuca Ceresoli } 94239dd23dcSLuca Ceresoli 9430985dd30SLeon Luo /** 9440985dd30SLeon Luo * imx274_get_fmt - Get the pad format 9450985dd30SLeon Luo * @sd: Pointer to V4L2 Sub device structure 9460985dd30SLeon Luo * @cfg: Pointer to sub device pad information structure 9470985dd30SLeon Luo * @fmt: Pointer to pad level media bus format 9480985dd30SLeon Luo * 9490985dd30SLeon Luo * This function is used to get the pad format information. 9500985dd30SLeon Luo * 9510985dd30SLeon Luo * Return: 0 on success 9520985dd30SLeon Luo */ 9530985dd30SLeon Luo static int imx274_get_fmt(struct v4l2_subdev *sd, 9540985dd30SLeon Luo struct v4l2_subdev_pad_config *cfg, 9550985dd30SLeon Luo struct v4l2_subdev_format *fmt) 9560985dd30SLeon Luo { 9570985dd30SLeon Luo struct stimx274 *imx274 = to_imx274(sd); 9580985dd30SLeon Luo 9590985dd30SLeon Luo mutex_lock(&imx274->lock); 9600985dd30SLeon Luo fmt->format = imx274->format; 9610985dd30SLeon Luo mutex_unlock(&imx274->lock); 9620985dd30SLeon Luo return 0; 9630985dd30SLeon Luo } 9640985dd30SLeon Luo 9650985dd30SLeon Luo /** 9660985dd30SLeon Luo * imx274_set_fmt - This is used to set the pad format 9670985dd30SLeon Luo * @sd: Pointer to V4L2 Sub device structure 9680985dd30SLeon Luo * @cfg: Pointer to sub device pad information structure 9690985dd30SLeon Luo * @format: Pointer to pad level media bus format 9700985dd30SLeon Luo * 9710985dd30SLeon Luo * This function is used to set the pad format. 9720985dd30SLeon Luo * 9730985dd30SLeon Luo * Return: 0 on success 9740985dd30SLeon Luo */ 9750985dd30SLeon Luo static int imx274_set_fmt(struct v4l2_subdev *sd, 9760985dd30SLeon Luo struct v4l2_subdev_pad_config *cfg, 9770985dd30SLeon Luo struct v4l2_subdev_format *format) 9780985dd30SLeon Luo { 9790985dd30SLeon Luo struct v4l2_mbus_framefmt *fmt = &format->format; 9800985dd30SLeon Luo struct stimx274 *imx274 = to_imx274(sd); 98139dd23dcSLuca Ceresoli int err = 0; 9820985dd30SLeon Luo 9830985dd30SLeon Luo mutex_lock(&imx274->lock); 9840985dd30SLeon Luo 98539dd23dcSLuca Ceresoli err = __imx274_change_compose(imx274, cfg, format->which, 98639dd23dcSLuca Ceresoli &fmt->width, &fmt->height, 0); 9870985dd30SLeon Luo 98839dd23dcSLuca Ceresoli if (err) 98939dd23dcSLuca Ceresoli goto out; 9900985dd30SLeon Luo 99139dd23dcSLuca Ceresoli /* 99239dd23dcSLuca Ceresoli * __imx274_change_compose already set width and height in the 99339dd23dcSLuca Ceresoli * applicable format, but we need to keep all other format 99439dd23dcSLuca Ceresoli * values, so do a full copy here 99539dd23dcSLuca Ceresoli */ 9960985dd30SLeon Luo fmt->field = V4L2_FIELD_NONE; 9970985dd30SLeon Luo if (format->which == V4L2_SUBDEV_FORMAT_TRY) 9980985dd30SLeon Luo cfg->try_fmt = *fmt; 9990985dd30SLeon Luo else 10000985dd30SLeon Luo imx274->format = *fmt; 10010985dd30SLeon Luo 100239dd23dcSLuca Ceresoli out: 10030985dd30SLeon Luo mutex_unlock(&imx274->lock); 100439dd23dcSLuca Ceresoli 100539dd23dcSLuca Ceresoli return err; 100639dd23dcSLuca Ceresoli } 100739dd23dcSLuca Ceresoli 100839dd23dcSLuca Ceresoli static int imx274_get_selection(struct v4l2_subdev *sd, 100939dd23dcSLuca Ceresoli struct v4l2_subdev_pad_config *cfg, 101039dd23dcSLuca Ceresoli struct v4l2_subdev_selection *sel) 101139dd23dcSLuca Ceresoli { 101239dd23dcSLuca Ceresoli struct stimx274 *imx274 = to_imx274(sd); 101339dd23dcSLuca Ceresoli const struct v4l2_rect *src_crop; 101439dd23dcSLuca Ceresoli const struct v4l2_mbus_framefmt *src_fmt; 101539dd23dcSLuca Ceresoli int ret = 0; 101639dd23dcSLuca Ceresoli 101739dd23dcSLuca Ceresoli if (sel->pad != 0) 101839dd23dcSLuca Ceresoli return -EINVAL; 101939dd23dcSLuca Ceresoli 102039dd23dcSLuca Ceresoli if (sel->target == V4L2_SEL_TGT_CROP_BOUNDS) { 102139dd23dcSLuca Ceresoli sel->r.left = 0; 102239dd23dcSLuca Ceresoli sel->r.top = 0; 102339dd23dcSLuca Ceresoli sel->r.width = IMX274_MAX_WIDTH; 102439dd23dcSLuca Ceresoli sel->r.height = IMX274_MAX_HEIGHT; 10250985dd30SLeon Luo return 0; 10260985dd30SLeon Luo } 10270985dd30SLeon Luo 102839dd23dcSLuca Ceresoli if (sel->which == V4L2_SUBDEV_FORMAT_TRY) { 102939dd23dcSLuca Ceresoli src_crop = &cfg->try_crop; 103039dd23dcSLuca Ceresoli src_fmt = &cfg->try_fmt; 103139dd23dcSLuca Ceresoli } else { 103239dd23dcSLuca Ceresoli src_crop = &imx274->crop; 103339dd23dcSLuca Ceresoli src_fmt = &imx274->format; 103439dd23dcSLuca Ceresoli } 103539dd23dcSLuca Ceresoli 103639dd23dcSLuca Ceresoli mutex_lock(&imx274->lock); 103739dd23dcSLuca Ceresoli 103839dd23dcSLuca Ceresoli switch (sel->target) { 103939dd23dcSLuca Ceresoli case V4L2_SEL_TGT_CROP: 104039dd23dcSLuca Ceresoli sel->r = *src_crop; 104139dd23dcSLuca Ceresoli break; 104239dd23dcSLuca Ceresoli case V4L2_SEL_TGT_COMPOSE_BOUNDS: 104339dd23dcSLuca Ceresoli sel->r.top = 0; 104439dd23dcSLuca Ceresoli sel->r.left = 0; 104539dd23dcSLuca Ceresoli sel->r.width = src_crop->width; 104639dd23dcSLuca Ceresoli sel->r.height = src_crop->height; 104739dd23dcSLuca Ceresoli break; 104839dd23dcSLuca Ceresoli case V4L2_SEL_TGT_COMPOSE: 104939dd23dcSLuca Ceresoli sel->r.top = 0; 105039dd23dcSLuca Ceresoli sel->r.left = 0; 105139dd23dcSLuca Ceresoli sel->r.width = src_fmt->width; 105239dd23dcSLuca Ceresoli sel->r.height = src_fmt->height; 105339dd23dcSLuca Ceresoli break; 105439dd23dcSLuca Ceresoli default: 105539dd23dcSLuca Ceresoli ret = -EINVAL; 105639dd23dcSLuca Ceresoli } 105739dd23dcSLuca Ceresoli 105839dd23dcSLuca Ceresoli mutex_unlock(&imx274->lock); 105939dd23dcSLuca Ceresoli 106039dd23dcSLuca Ceresoli return ret; 106139dd23dcSLuca Ceresoli } 106239dd23dcSLuca Ceresoli 106339dd23dcSLuca Ceresoli static int imx274_set_selection_crop(struct stimx274 *imx274, 106439dd23dcSLuca Ceresoli struct v4l2_subdev_pad_config *cfg, 106539dd23dcSLuca Ceresoli struct v4l2_subdev_selection *sel) 106639dd23dcSLuca Ceresoli { 106739dd23dcSLuca Ceresoli struct v4l2_rect *tgt_crop; 106839dd23dcSLuca Ceresoli struct v4l2_rect new_crop; 106939dd23dcSLuca Ceresoli bool size_changed; 107039dd23dcSLuca Ceresoli 107139dd23dcSLuca Ceresoli /* 107239dd23dcSLuca Ceresoli * h_step could be 12 or 24 depending on the binning. But we 107339dd23dcSLuca Ceresoli * won't know the binning until we choose the mode later in 107439dd23dcSLuca Ceresoli * __imx274_change_compose(). Thus let's be safe and use the 107539dd23dcSLuca Ceresoli * most conservative value in all cases. 107639dd23dcSLuca Ceresoli */ 107739dd23dcSLuca Ceresoli const u32 h_step = 24; 107839dd23dcSLuca Ceresoli 107939dd23dcSLuca Ceresoli new_crop.width = min_t(u32, 108039dd23dcSLuca Ceresoli IMX274_ROUND(sel->r.width, h_step, sel->flags), 108139dd23dcSLuca Ceresoli IMX274_MAX_WIDTH); 108239dd23dcSLuca Ceresoli 108339dd23dcSLuca Ceresoli /* Constraint: HTRIMMING_END - HTRIMMING_START >= 144 */ 108439dd23dcSLuca Ceresoli if (new_crop.width < 144) 108539dd23dcSLuca Ceresoli new_crop.width = 144; 108639dd23dcSLuca Ceresoli 108739dd23dcSLuca Ceresoli new_crop.left = min_t(u32, 108839dd23dcSLuca Ceresoli IMX274_ROUND(sel->r.left, h_step, 0), 108939dd23dcSLuca Ceresoli IMX274_MAX_WIDTH - new_crop.width); 109039dd23dcSLuca Ceresoli 109139dd23dcSLuca Ceresoli new_crop.height = min_t(u32, 109239dd23dcSLuca Ceresoli IMX274_ROUND(sel->r.height, 2, sel->flags), 109339dd23dcSLuca Ceresoli IMX274_MAX_HEIGHT); 109439dd23dcSLuca Ceresoli 109539dd23dcSLuca Ceresoli new_crop.top = min_t(u32, IMX274_ROUND(sel->r.top, 2, 0), 109639dd23dcSLuca Ceresoli IMX274_MAX_HEIGHT - new_crop.height); 109739dd23dcSLuca Ceresoli 109839dd23dcSLuca Ceresoli sel->r = new_crop; 109939dd23dcSLuca Ceresoli 110039dd23dcSLuca Ceresoli if (sel->which == V4L2_SUBDEV_FORMAT_TRY) 110139dd23dcSLuca Ceresoli tgt_crop = &cfg->try_crop; 110239dd23dcSLuca Ceresoli else 110339dd23dcSLuca Ceresoli tgt_crop = &imx274->crop; 110439dd23dcSLuca Ceresoli 110539dd23dcSLuca Ceresoli mutex_lock(&imx274->lock); 110639dd23dcSLuca Ceresoli 110739dd23dcSLuca Ceresoli size_changed = (new_crop.width != tgt_crop->width || 110839dd23dcSLuca Ceresoli new_crop.height != tgt_crop->height); 110939dd23dcSLuca Ceresoli 111039dd23dcSLuca Ceresoli /* __imx274_change_compose needs the new size in *tgt_crop */ 111139dd23dcSLuca Ceresoli *tgt_crop = new_crop; 111239dd23dcSLuca Ceresoli 111339dd23dcSLuca Ceresoli /* if crop size changed then reset the output image size */ 111439dd23dcSLuca Ceresoli if (size_changed) 111539dd23dcSLuca Ceresoli __imx274_change_compose(imx274, cfg, sel->which, 111639dd23dcSLuca Ceresoli &new_crop.width, &new_crop.height, 111739dd23dcSLuca Ceresoli sel->flags); 111839dd23dcSLuca Ceresoli 111939dd23dcSLuca Ceresoli mutex_unlock(&imx274->lock); 112039dd23dcSLuca Ceresoli 112139dd23dcSLuca Ceresoli return 0; 112239dd23dcSLuca Ceresoli } 112339dd23dcSLuca Ceresoli 112439dd23dcSLuca Ceresoli static int imx274_set_selection(struct v4l2_subdev *sd, 112539dd23dcSLuca Ceresoli struct v4l2_subdev_pad_config *cfg, 112639dd23dcSLuca Ceresoli struct v4l2_subdev_selection *sel) 112739dd23dcSLuca Ceresoli { 112839dd23dcSLuca Ceresoli struct stimx274 *imx274 = to_imx274(sd); 112939dd23dcSLuca Ceresoli 113039dd23dcSLuca Ceresoli if (sel->pad != 0) 113139dd23dcSLuca Ceresoli return -EINVAL; 113239dd23dcSLuca Ceresoli 113339dd23dcSLuca Ceresoli if (sel->target == V4L2_SEL_TGT_CROP) 113439dd23dcSLuca Ceresoli return imx274_set_selection_crop(imx274, cfg, sel); 113539dd23dcSLuca Ceresoli 113639dd23dcSLuca Ceresoli if (sel->target == V4L2_SEL_TGT_COMPOSE) { 113739dd23dcSLuca Ceresoli int err; 113839dd23dcSLuca Ceresoli 113939dd23dcSLuca Ceresoli mutex_lock(&imx274->lock); 114039dd23dcSLuca Ceresoli err = __imx274_change_compose(imx274, cfg, sel->which, 114139dd23dcSLuca Ceresoli &sel->r.width, &sel->r.height, 114239dd23dcSLuca Ceresoli sel->flags); 114339dd23dcSLuca Ceresoli mutex_unlock(&imx274->lock); 114439dd23dcSLuca Ceresoli 114539dd23dcSLuca Ceresoli /* 114639dd23dcSLuca Ceresoli * __imx274_change_compose already set width and 114739dd23dcSLuca Ceresoli * height in set->r, we still need to set top-left 114839dd23dcSLuca Ceresoli */ 114939dd23dcSLuca Ceresoli if (!err) { 115039dd23dcSLuca Ceresoli sel->r.top = 0; 115139dd23dcSLuca Ceresoli sel->r.left = 0; 115239dd23dcSLuca Ceresoli } 115339dd23dcSLuca Ceresoli 115439dd23dcSLuca Ceresoli return err; 115539dd23dcSLuca Ceresoli } 115639dd23dcSLuca Ceresoli 115739dd23dcSLuca Ceresoli return -EINVAL; 115839dd23dcSLuca Ceresoli } 115939dd23dcSLuca Ceresoli 116039dd23dcSLuca Ceresoli static int imx274_apply_trimming(struct stimx274 *imx274) 116139dd23dcSLuca Ceresoli { 116239dd23dcSLuca Ceresoli u32 h_start; 116339dd23dcSLuca Ceresoli u32 h_end; 116439dd23dcSLuca Ceresoli u32 hmax; 116539dd23dcSLuca Ceresoli u32 v_cut; 116639dd23dcSLuca Ceresoli s32 v_pos; 116739dd23dcSLuca Ceresoli u32 write_v_size; 116839dd23dcSLuca Ceresoli u32 y_out_size; 116939dd23dcSLuca Ceresoli int err; 117039dd23dcSLuca Ceresoli 117139dd23dcSLuca Ceresoli h_start = imx274->crop.left + 12; 117239dd23dcSLuca Ceresoli h_end = h_start + imx274->crop.width; 117339dd23dcSLuca Ceresoli 117439dd23dcSLuca Ceresoli /* Use the minimum allowed value of HMAX */ 117539dd23dcSLuca Ceresoli /* Note: except in mode 1, (width / 16 + 23) is always < hmax_min */ 117639dd23dcSLuca Ceresoli /* Note: 260 is the minimum HMAX in all implemented modes */ 117739dd23dcSLuca Ceresoli hmax = max_t(u32, 260, (imx274->crop.width) / 16 + 23); 117839dd23dcSLuca Ceresoli 117939dd23dcSLuca Ceresoli /* invert v_pos if VFLIP */ 118039dd23dcSLuca Ceresoli v_pos = imx274->ctrls.vflip->cur.val ? 118139dd23dcSLuca Ceresoli (-imx274->crop.top / 2) : (imx274->crop.top / 2); 118239dd23dcSLuca Ceresoli v_cut = (IMX274_MAX_HEIGHT - imx274->crop.height) / 2; 118339dd23dcSLuca Ceresoli write_v_size = imx274->crop.height + 22; 118439dd23dcSLuca Ceresoli y_out_size = imx274->crop.height + 14; 118539dd23dcSLuca Ceresoli 118639dd23dcSLuca Ceresoli err = imx274_write_mbreg(imx274, IMX274_HMAX_REG_LSB, hmax, 2); 118739dd23dcSLuca Ceresoli if (!err) 118839dd23dcSLuca Ceresoli err = imx274_write_mbreg(imx274, IMX274_HTRIM_EN_REG, 1, 1); 118939dd23dcSLuca Ceresoli if (!err) 119039dd23dcSLuca Ceresoli err = imx274_write_mbreg(imx274, IMX274_HTRIM_START_REG_LSB, 119139dd23dcSLuca Ceresoli h_start, 2); 119239dd23dcSLuca Ceresoli if (!err) 119339dd23dcSLuca Ceresoli err = imx274_write_mbreg(imx274, IMX274_HTRIM_END_REG_LSB, 119439dd23dcSLuca Ceresoli h_end, 2); 119539dd23dcSLuca Ceresoli if (!err) 119639dd23dcSLuca Ceresoli err = imx274_write_mbreg(imx274, IMX274_VWIDCUTEN_REG, 1, 1); 119739dd23dcSLuca Ceresoli if (!err) 119839dd23dcSLuca Ceresoli err = imx274_write_mbreg(imx274, IMX274_VWIDCUT_REG_LSB, 119939dd23dcSLuca Ceresoli v_cut, 2); 120039dd23dcSLuca Ceresoli if (!err) 120139dd23dcSLuca Ceresoli err = imx274_write_mbreg(imx274, IMX274_VWINPOS_REG_LSB, 120239dd23dcSLuca Ceresoli v_pos, 2); 120339dd23dcSLuca Ceresoli if (!err) 120439dd23dcSLuca Ceresoli err = imx274_write_mbreg(imx274, IMX274_WRITE_VSIZE_REG_LSB, 120539dd23dcSLuca Ceresoli write_v_size, 2); 120639dd23dcSLuca Ceresoli if (!err) 120739dd23dcSLuca Ceresoli err = imx274_write_mbreg(imx274, IMX274_Y_OUT_SIZE_REG_LSB, 120839dd23dcSLuca Ceresoli y_out_size, 2); 120939dd23dcSLuca Ceresoli 121039dd23dcSLuca Ceresoli return err; 121139dd23dcSLuca Ceresoli } 121239dd23dcSLuca Ceresoli 12130985dd30SLeon Luo /** 12140985dd30SLeon Luo * imx274_g_frame_interval - Get the frame interval 12150985dd30SLeon Luo * @sd: Pointer to V4L2 Sub device structure 12160985dd30SLeon Luo * @fi: Pointer to V4l2 Sub device frame interval structure 12170985dd30SLeon Luo * 12180985dd30SLeon Luo * This function is used to get the frame interval. 12190985dd30SLeon Luo * 12200985dd30SLeon Luo * Return: 0 on success 12210985dd30SLeon Luo */ 12220985dd30SLeon Luo static int imx274_g_frame_interval(struct v4l2_subdev *sd, 12230985dd30SLeon Luo struct v4l2_subdev_frame_interval *fi) 12240985dd30SLeon Luo { 12250985dd30SLeon Luo struct stimx274 *imx274 = to_imx274(sd); 12260985dd30SLeon Luo 12270985dd30SLeon Luo fi->interval = imx274->frame_interval; 12280985dd30SLeon Luo dev_dbg(&imx274->client->dev, "%s frame rate = %d / %d\n", 12290985dd30SLeon Luo __func__, imx274->frame_interval.numerator, 12300985dd30SLeon Luo imx274->frame_interval.denominator); 12310985dd30SLeon Luo 12320985dd30SLeon Luo return 0; 12330985dd30SLeon Luo } 12340985dd30SLeon Luo 12350985dd30SLeon Luo /** 12360985dd30SLeon Luo * imx274_s_frame_interval - Set the frame interval 12370985dd30SLeon Luo * @sd: Pointer to V4L2 Sub device structure 12380985dd30SLeon Luo * @fi: Pointer to V4l2 Sub device frame interval structure 12390985dd30SLeon Luo * 12400985dd30SLeon Luo * This function is used to set the frame intervavl. 12410985dd30SLeon Luo * 12420985dd30SLeon Luo * Return: 0 on success 12430985dd30SLeon Luo */ 12440985dd30SLeon Luo static int imx274_s_frame_interval(struct v4l2_subdev *sd, 12450985dd30SLeon Luo struct v4l2_subdev_frame_interval *fi) 12460985dd30SLeon Luo { 12470985dd30SLeon Luo struct stimx274 *imx274 = to_imx274(sd); 12480985dd30SLeon Luo struct v4l2_ctrl *ctrl = imx274->ctrls.exposure; 12490985dd30SLeon Luo int min, max, def; 12500985dd30SLeon Luo int ret; 12510985dd30SLeon Luo 12520985dd30SLeon Luo mutex_lock(&imx274->lock); 12530985dd30SLeon Luo ret = imx274_set_frame_interval(imx274, fi->interval); 12540985dd30SLeon Luo 12550985dd30SLeon Luo if (!ret) { 12560985dd30SLeon Luo /* 12570985dd30SLeon Luo * exposure time range is decided by frame interval 125801343391SLuca Ceresoli * need to update it after frame interval changes 12590985dd30SLeon Luo */ 12600985dd30SLeon Luo min = IMX274_MIN_EXPOSURE_TIME; 12610985dd30SLeon Luo max = fi->interval.numerator * 1000000 12620985dd30SLeon Luo / fi->interval.denominator; 12630985dd30SLeon Luo def = max; 12640985dd30SLeon Luo if (__v4l2_ctrl_modify_range(ctrl, min, max, 1, def)) { 12650985dd30SLeon Luo dev_err(&imx274->client->dev, 12660985dd30SLeon Luo "Exposure ctrl range update failed\n"); 12670985dd30SLeon Luo goto unlock; 12680985dd30SLeon Luo } 12690985dd30SLeon Luo 12700985dd30SLeon Luo /* update exposure time accordingly */ 1271cf908704SLuca Ceresoli imx274_set_exposure(imx274, ctrl->val); 12720985dd30SLeon Luo 12730985dd30SLeon Luo dev_dbg(&imx274->client->dev, "set frame interval to %uus\n", 12740985dd30SLeon Luo fi->interval.numerator * 1000000 12750985dd30SLeon Luo / fi->interval.denominator); 12760985dd30SLeon Luo } 12770985dd30SLeon Luo 12780985dd30SLeon Luo unlock: 12790985dd30SLeon Luo mutex_unlock(&imx274->lock); 12800985dd30SLeon Luo 12810985dd30SLeon Luo return ret; 12820985dd30SLeon Luo } 12830985dd30SLeon Luo 12840985dd30SLeon Luo /** 12850985dd30SLeon Luo * imx274_load_default - load default control values 12860985dd30SLeon Luo * @priv: Pointer to device structure 12870985dd30SLeon Luo * 12880985dd30SLeon Luo * Return: 0 on success, errors otherwise 12890985dd30SLeon Luo */ 12900985dd30SLeon Luo static int imx274_load_default(struct stimx274 *priv) 12910985dd30SLeon Luo { 12920985dd30SLeon Luo int ret; 12930985dd30SLeon Luo 12940985dd30SLeon Luo /* load default control values */ 12950985dd30SLeon Luo priv->frame_interval.numerator = 1; 12960985dd30SLeon Luo priv->frame_interval.denominator = IMX274_DEF_FRAME_RATE; 12970985dd30SLeon Luo priv->ctrls.exposure->val = 1000000 / IMX274_DEF_FRAME_RATE; 12980985dd30SLeon Luo priv->ctrls.gain->val = IMX274_DEF_GAIN; 12990985dd30SLeon Luo priv->ctrls.vflip->val = 0; 13000985dd30SLeon Luo priv->ctrls.test_pattern->val = TEST_PATTERN_DISABLED; 13010985dd30SLeon Luo 13020985dd30SLeon Luo /* update frame rate */ 13030985dd30SLeon Luo ret = imx274_set_frame_interval(priv, 13040985dd30SLeon Luo priv->frame_interval); 13050985dd30SLeon Luo if (ret) 13060985dd30SLeon Luo return ret; 13070985dd30SLeon Luo 13080985dd30SLeon Luo /* update exposure time */ 13090985dd30SLeon Luo ret = v4l2_ctrl_s_ctrl(priv->ctrls.exposure, priv->ctrls.exposure->val); 13100985dd30SLeon Luo if (ret) 13110985dd30SLeon Luo return ret; 13120985dd30SLeon Luo 13130985dd30SLeon Luo /* update gain */ 13140985dd30SLeon Luo ret = v4l2_ctrl_s_ctrl(priv->ctrls.gain, priv->ctrls.gain->val); 13150985dd30SLeon Luo if (ret) 13160985dd30SLeon Luo return ret; 13170985dd30SLeon Luo 13180985dd30SLeon Luo /* update vflip */ 13190985dd30SLeon Luo ret = v4l2_ctrl_s_ctrl(priv->ctrls.vflip, priv->ctrls.vflip->val); 13200985dd30SLeon Luo if (ret) 13210985dd30SLeon Luo return ret; 13220985dd30SLeon Luo 13230985dd30SLeon Luo return 0; 13240985dd30SLeon Luo } 13250985dd30SLeon Luo 13260985dd30SLeon Luo /** 13270985dd30SLeon Luo * imx274_s_stream - It is used to start/stop the streaming. 13280985dd30SLeon Luo * @sd: V4L2 Sub device 13290985dd30SLeon Luo * @on: Flag (True / False) 13300985dd30SLeon Luo * 13310985dd30SLeon Luo * This function controls the start or stop of streaming for the 13320985dd30SLeon Luo * imx274 sensor. 13330985dd30SLeon Luo * 13340985dd30SLeon Luo * Return: 0 on success, errors otherwise 13350985dd30SLeon Luo */ 13360985dd30SLeon Luo static int imx274_s_stream(struct v4l2_subdev *sd, int on) 13370985dd30SLeon Luo { 13380985dd30SLeon Luo struct stimx274 *imx274 = to_imx274(sd); 13390985dd30SLeon Luo int ret = 0; 13400985dd30SLeon Luo 13414317322dSLuca Ceresoli dev_dbg(&imx274->client->dev, "%s : %s, mode index = %td\n", __func__, 13424317322dSLuca Ceresoli on ? "Stream Start" : "Stream Stop", 13439648cb57SLuca Ceresoli imx274->mode - &imx274_modes[0]); 13440985dd30SLeon Luo 13450985dd30SLeon Luo mutex_lock(&imx274->lock); 13460985dd30SLeon Luo 13470985dd30SLeon Luo if (on) { 13480985dd30SLeon Luo /* load mode registers */ 134996a2c731SLuca Ceresoli ret = imx274_mode_regs(imx274); 13500985dd30SLeon Luo if (ret) 13510985dd30SLeon Luo goto fail; 13520985dd30SLeon Luo 135339dd23dcSLuca Ceresoli ret = imx274_apply_trimming(imx274); 135439dd23dcSLuca Ceresoli if (ret) 135539dd23dcSLuca Ceresoli goto fail; 135639dd23dcSLuca Ceresoli 13570985dd30SLeon Luo /* 13580985dd30SLeon Luo * update frame rate & expsoure. if the last mode is different, 13590985dd30SLeon Luo * HMAX could be changed. As the result, frame rate & exposure 13600985dd30SLeon Luo * are changed. 13610985dd30SLeon Luo * gain is not affected. 13620985dd30SLeon Luo */ 13630985dd30SLeon Luo ret = imx274_set_frame_interval(imx274, 13640985dd30SLeon Luo imx274->frame_interval); 13650985dd30SLeon Luo if (ret) 13660985dd30SLeon Luo goto fail; 13670985dd30SLeon Luo 13680985dd30SLeon Luo /* update exposure time */ 13690985dd30SLeon Luo ret = __v4l2_ctrl_s_ctrl(imx274->ctrls.exposure, 13700985dd30SLeon Luo imx274->ctrls.exposure->val); 13710985dd30SLeon Luo if (ret) 13720985dd30SLeon Luo goto fail; 13730985dd30SLeon Luo 13740985dd30SLeon Luo /* start stream */ 13750985dd30SLeon Luo ret = imx274_start_stream(imx274); 13760985dd30SLeon Luo if (ret) 13770985dd30SLeon Luo goto fail; 13780985dd30SLeon Luo } else { 13790985dd30SLeon Luo /* stop stream */ 13808ed8bba7SLuca Ceresoli ret = imx274_write_table(imx274, imx274_stop); 13810985dd30SLeon Luo if (ret) 13820985dd30SLeon Luo goto fail; 13830985dd30SLeon Luo } 13840985dd30SLeon Luo 13850985dd30SLeon Luo mutex_unlock(&imx274->lock); 13864317322dSLuca Ceresoli dev_dbg(&imx274->client->dev, "%s : Done\n", __func__); 13870985dd30SLeon Luo return 0; 13880985dd30SLeon Luo 13890985dd30SLeon Luo fail: 13900985dd30SLeon Luo mutex_unlock(&imx274->lock); 13910985dd30SLeon Luo dev_err(&imx274->client->dev, "s_stream failed\n"); 13920985dd30SLeon Luo return ret; 13930985dd30SLeon Luo } 13940985dd30SLeon Luo 13950985dd30SLeon Luo /* 13960985dd30SLeon Luo * imx274_get_frame_length - Function for obtaining current frame length 13970985dd30SLeon Luo * @priv: Pointer to device structure 13980985dd30SLeon Luo * @val: Pointer to obainted value 13990985dd30SLeon Luo * 14000985dd30SLeon Luo * frame_length = vmax x (svr + 1), in unit of hmax. 14010985dd30SLeon Luo * 14020985dd30SLeon Luo * Return: 0 on success 14030985dd30SLeon Luo */ 14040985dd30SLeon Luo static int imx274_get_frame_length(struct stimx274 *priv, u32 *val) 14050985dd30SLeon Luo { 14060985dd30SLeon Luo int err; 1407ca017467SLuca Ceresoli u32 svr; 14080985dd30SLeon Luo u32 vmax; 14090985dd30SLeon Luo 1410ca017467SLuca Ceresoli err = imx274_read_mbreg(priv, IMX274_SVR_REG_LSB, &svr, 2); 14110985dd30SLeon Luo if (err) 14120985dd30SLeon Luo goto fail; 14130985dd30SLeon Luo 1414ca017467SLuca Ceresoli err = imx274_read_mbreg(priv, IMX274_VMAX_REG_3, &vmax, 3); 14150985dd30SLeon Luo if (err) 14160985dd30SLeon Luo goto fail; 14170985dd30SLeon Luo 14180985dd30SLeon Luo *val = vmax * (svr + 1); 14190985dd30SLeon Luo 14200985dd30SLeon Luo return 0; 14210985dd30SLeon Luo 14220985dd30SLeon Luo fail: 14230985dd30SLeon Luo dev_err(&priv->client->dev, "%s error = %d\n", __func__, err); 14240985dd30SLeon Luo return err; 14250985dd30SLeon Luo } 14260985dd30SLeon Luo 14270985dd30SLeon Luo static int imx274_clamp_coarse_time(struct stimx274 *priv, u32 *val, 14280985dd30SLeon Luo u32 *frame_length) 14290985dd30SLeon Luo { 14300985dd30SLeon Luo int err; 14310985dd30SLeon Luo 14320985dd30SLeon Luo err = imx274_get_frame_length(priv, frame_length); 14330985dd30SLeon Luo if (err) 14340985dd30SLeon Luo return err; 14350985dd30SLeon Luo 143696a2c731SLuca Ceresoli if (*frame_length < priv->mode->min_frame_len) 143796a2c731SLuca Ceresoli *frame_length = priv->mode->min_frame_len; 14380985dd30SLeon Luo 14390985dd30SLeon Luo *val = *frame_length - *val; /* convert to raw shr */ 14400985dd30SLeon Luo if (*val > *frame_length - IMX274_SHR_LIMIT_CONST) 14410985dd30SLeon Luo *val = *frame_length - IMX274_SHR_LIMIT_CONST; 144296a2c731SLuca Ceresoli else if (*val < priv->mode->min_SHR) 144396a2c731SLuca Ceresoli *val = priv->mode->min_SHR; 14440985dd30SLeon Luo 14450985dd30SLeon Luo return 0; 14460985dd30SLeon Luo } 14470985dd30SLeon Luo 14480985dd30SLeon Luo /* 14490985dd30SLeon Luo * imx274_set_digital gain - Function called when setting digital gain 14500985dd30SLeon Luo * @priv: Pointer to device structure 14510985dd30SLeon Luo * @dgain: Value of digital gain. 14520985dd30SLeon Luo * 14530985dd30SLeon Luo * Digital gain has only 4 steps: 1x, 2x, 4x, and 8x 14540985dd30SLeon Luo * 14550985dd30SLeon Luo * Return: 0 on success 14560985dd30SLeon Luo */ 14570985dd30SLeon Luo static int imx274_set_digital_gain(struct stimx274 *priv, u32 dgain) 14580985dd30SLeon Luo { 14590985dd30SLeon Luo u8 reg_val; 14600985dd30SLeon Luo 14610985dd30SLeon Luo reg_val = ffs(dgain); 14620985dd30SLeon Luo 14630985dd30SLeon Luo if (reg_val) 14640985dd30SLeon Luo reg_val--; 14650985dd30SLeon Luo 14660985dd30SLeon Luo reg_val = clamp(reg_val, (u8)0, (u8)3); 14670985dd30SLeon Luo 14680985dd30SLeon Luo return imx274_write_reg(priv, IMX274_DIGITAL_GAIN_REG, 14690985dd30SLeon Luo reg_val & IMX274_MASK_LSB_4_BITS); 14700985dd30SLeon Luo } 14710985dd30SLeon Luo 14720985dd30SLeon Luo /* 14730985dd30SLeon Luo * imx274_set_gain - Function called when setting gain 14740985dd30SLeon Luo * @priv: Pointer to device structure 14750985dd30SLeon Luo * @val: Value of gain. the real value = val << IMX274_GAIN_SHIFT; 14760985dd30SLeon Luo * @ctrl: v4l2 control pointer 14770985dd30SLeon Luo * 14780985dd30SLeon Luo * Set the gain based on input value. 14790985dd30SLeon Luo * The caller should hold the mutex lock imx274->lock if necessary 14800985dd30SLeon Luo * 14810985dd30SLeon Luo * Return: 0 on success 14820985dd30SLeon Luo */ 14830985dd30SLeon Luo static int imx274_set_gain(struct stimx274 *priv, struct v4l2_ctrl *ctrl) 14840985dd30SLeon Luo { 14850985dd30SLeon Luo int err; 14860985dd30SLeon Luo u32 gain, analog_gain, digital_gain, gain_reg; 14870985dd30SLeon Luo 14880985dd30SLeon Luo gain = (u32)(ctrl->val); 14890985dd30SLeon Luo 14900985dd30SLeon Luo dev_dbg(&priv->client->dev, 14910985dd30SLeon Luo "%s : input gain = %d.%d\n", __func__, 14920985dd30SLeon Luo gain >> IMX274_GAIN_SHIFT, 14930985dd30SLeon Luo ((gain & IMX274_GAIN_SHIFT_MASK) * 100) >> IMX274_GAIN_SHIFT); 14940985dd30SLeon Luo 14950985dd30SLeon Luo if (gain > IMX274_MAX_DIGITAL_GAIN * IMX274_MAX_ANALOG_GAIN) 14960985dd30SLeon Luo gain = IMX274_MAX_DIGITAL_GAIN * IMX274_MAX_ANALOG_GAIN; 14970985dd30SLeon Luo else if (gain < IMX274_MIN_GAIN) 14980985dd30SLeon Luo gain = IMX274_MIN_GAIN; 14990985dd30SLeon Luo 15000985dd30SLeon Luo if (gain <= IMX274_MAX_ANALOG_GAIN) 15010985dd30SLeon Luo digital_gain = 1; 15020985dd30SLeon Luo else if (gain <= IMX274_MAX_ANALOG_GAIN * 2) 15030985dd30SLeon Luo digital_gain = 2; 15040985dd30SLeon Luo else if (gain <= IMX274_MAX_ANALOG_GAIN * 4) 15050985dd30SLeon Luo digital_gain = 4; 15060985dd30SLeon Luo else 15070985dd30SLeon Luo digital_gain = IMX274_MAX_DIGITAL_GAIN; 15080985dd30SLeon Luo 15090985dd30SLeon Luo analog_gain = gain / digital_gain; 15100985dd30SLeon Luo 15110985dd30SLeon Luo dev_dbg(&priv->client->dev, 15120985dd30SLeon Luo "%s : digital gain = %d, analog gain = %d.%d\n", 15130985dd30SLeon Luo __func__, digital_gain, analog_gain >> IMX274_GAIN_SHIFT, 15140985dd30SLeon Luo ((analog_gain & IMX274_GAIN_SHIFT_MASK) * 100) 15150985dd30SLeon Luo >> IMX274_GAIN_SHIFT); 15160985dd30SLeon Luo 15170985dd30SLeon Luo err = imx274_set_digital_gain(priv, digital_gain); 15180985dd30SLeon Luo if (err) 15190985dd30SLeon Luo goto fail; 15200985dd30SLeon Luo 15210985dd30SLeon Luo /* convert to register value, refer to imx274 datasheet */ 15220985dd30SLeon Luo gain_reg = (u32)IMX274_GAIN_CONST - 15230985dd30SLeon Luo (IMX274_GAIN_CONST << IMX274_GAIN_SHIFT) / analog_gain; 15240985dd30SLeon Luo if (gain_reg > IMX274_GAIN_REG_MAX) 15250985dd30SLeon Luo gain_reg = IMX274_GAIN_REG_MAX; 15260985dd30SLeon Luo 1527279b4b9aSLuca Ceresoli err = imx274_write_mbreg(priv, IMX274_ANALOG_GAIN_ADDR_LSB, gain_reg, 1528279b4b9aSLuca Ceresoli 2); 15290985dd30SLeon Luo if (err) 15300985dd30SLeon Luo goto fail; 15310985dd30SLeon Luo 15320985dd30SLeon Luo if (IMX274_GAIN_CONST - gain_reg == 0) { 15330985dd30SLeon Luo err = -EINVAL; 15340985dd30SLeon Luo goto fail; 15350985dd30SLeon Luo } 15360985dd30SLeon Luo 15370985dd30SLeon Luo /* convert register value back to gain value */ 15380985dd30SLeon Luo ctrl->val = (IMX274_GAIN_CONST << IMX274_GAIN_SHIFT) 15390985dd30SLeon Luo / (IMX274_GAIN_CONST - gain_reg) * digital_gain; 15400985dd30SLeon Luo 15410985dd30SLeon Luo dev_dbg(&priv->client->dev, 15420985dd30SLeon Luo "%s : GAIN control success, gain_reg = %d, new gain = %d\n", 15430985dd30SLeon Luo __func__, gain_reg, ctrl->val); 15440985dd30SLeon Luo 15450985dd30SLeon Luo return 0; 15460985dd30SLeon Luo 15470985dd30SLeon Luo fail: 15480985dd30SLeon Luo dev_err(&priv->client->dev, "%s error = %d\n", __func__, err); 15490985dd30SLeon Luo return err; 15500985dd30SLeon Luo } 15510985dd30SLeon Luo 15520985dd30SLeon Luo /* 15530985dd30SLeon Luo * imx274_set_coarse_time - Function called when setting SHR value 15540985dd30SLeon Luo * @priv: Pointer to device structure 15550985dd30SLeon Luo * @val: Value for exposure time in number of line_length, or [HMAX] 15560985dd30SLeon Luo * 15570985dd30SLeon Luo * Set SHR value based on input value. 15580985dd30SLeon Luo * 15590985dd30SLeon Luo * Return: 0 on success 15600985dd30SLeon Luo */ 15610985dd30SLeon Luo static int imx274_set_coarse_time(struct stimx274 *priv, u32 *val) 15620985dd30SLeon Luo { 15630985dd30SLeon Luo int err; 15640985dd30SLeon Luo u32 coarse_time, frame_length; 15650985dd30SLeon Luo 15660985dd30SLeon Luo coarse_time = *val; 15670985dd30SLeon Luo 15680985dd30SLeon Luo /* convert exposure_time to appropriate SHR value */ 15690985dd30SLeon Luo err = imx274_clamp_coarse_time(priv, &coarse_time, &frame_length); 15700985dd30SLeon Luo if (err) 15710985dd30SLeon Luo goto fail; 15720985dd30SLeon Luo 1573279b4b9aSLuca Ceresoli err = imx274_write_mbreg(priv, IMX274_SHR_REG_LSB, coarse_time, 2); 15740985dd30SLeon Luo if (err) 15750985dd30SLeon Luo goto fail; 15760985dd30SLeon Luo 15770985dd30SLeon Luo *val = frame_length - coarse_time; 15780985dd30SLeon Luo return 0; 15790985dd30SLeon Luo 15800985dd30SLeon Luo fail: 15810985dd30SLeon Luo dev_err(&priv->client->dev, "%s error = %d\n", __func__, err); 15820985dd30SLeon Luo return err; 15830985dd30SLeon Luo } 15840985dd30SLeon Luo 15850985dd30SLeon Luo /* 15860985dd30SLeon Luo * imx274_set_exposure - Function called when setting exposure time 15870985dd30SLeon Luo * @priv: Pointer to device structure 15880985dd30SLeon Luo * @val: Variable for exposure time, in the unit of micro-second 15890985dd30SLeon Luo * 15900985dd30SLeon Luo * Set exposure time based on input value. 15910985dd30SLeon Luo * The caller should hold the mutex lock imx274->lock if necessary 15920985dd30SLeon Luo * 15930985dd30SLeon Luo * Return: 0 on success 15940985dd30SLeon Luo */ 15950985dd30SLeon Luo static int imx274_set_exposure(struct stimx274 *priv, int val) 15960985dd30SLeon Luo { 15970985dd30SLeon Luo int err; 1598ca017467SLuca Ceresoli u32 hmax; 15990985dd30SLeon Luo u32 coarse_time; /* exposure time in unit of line (HMAX)*/ 16000985dd30SLeon Luo 16010985dd30SLeon Luo dev_dbg(&priv->client->dev, 16020985dd30SLeon Luo "%s : EXPOSURE control input = %d\n", __func__, val); 16030985dd30SLeon Luo 16040985dd30SLeon Luo /* step 1: convert input exposure_time (val) into number of 1[HMAX] */ 16050985dd30SLeon Luo 1606ca017467SLuca Ceresoli err = imx274_read_mbreg(priv, IMX274_HMAX_REG_LSB, &hmax, 2); 16070985dd30SLeon Luo if (err) 16080985dd30SLeon Luo goto fail; 1609ca017467SLuca Ceresoli 16100985dd30SLeon Luo if (hmax == 0) { 16110985dd30SLeon Luo err = -EINVAL; 16120985dd30SLeon Luo goto fail; 16130985dd30SLeon Luo } 16140985dd30SLeon Luo 16150985dd30SLeon Luo coarse_time = (IMX274_PIXCLK_CONST1 / IMX274_PIXCLK_CONST2 * val 161696a2c731SLuca Ceresoli - priv->mode->nocpiop) / hmax; 16170985dd30SLeon Luo 16180985dd30SLeon Luo /* step 2: convert exposure_time into SHR value */ 16190985dd30SLeon Luo 16200985dd30SLeon Luo /* set SHR */ 16210985dd30SLeon Luo err = imx274_set_coarse_time(priv, &coarse_time); 16220985dd30SLeon Luo if (err) 16230985dd30SLeon Luo goto fail; 16240985dd30SLeon Luo 16250985dd30SLeon Luo priv->ctrls.exposure->val = 162696a2c731SLuca Ceresoli (coarse_time * hmax + priv->mode->nocpiop) 16270985dd30SLeon Luo / (IMX274_PIXCLK_CONST1 / IMX274_PIXCLK_CONST2); 16280985dd30SLeon Luo 16290985dd30SLeon Luo dev_dbg(&priv->client->dev, 16300985dd30SLeon Luo "%s : EXPOSURE control success\n", __func__); 16310985dd30SLeon Luo return 0; 16320985dd30SLeon Luo 16330985dd30SLeon Luo fail: 16340985dd30SLeon Luo dev_err(&priv->client->dev, "%s error = %d\n", __func__, err); 16350985dd30SLeon Luo 16360985dd30SLeon Luo return err; 16370985dd30SLeon Luo } 16380985dd30SLeon Luo 16390985dd30SLeon Luo /* 16400985dd30SLeon Luo * imx274_set_vflip - Function called when setting vertical flip 16410985dd30SLeon Luo * @priv: Pointer to device structure 16420985dd30SLeon Luo * @val: Value for vflip setting 16430985dd30SLeon Luo * 16440985dd30SLeon Luo * Set vertical flip based on input value. 16450985dd30SLeon Luo * val = 0: normal, no vertical flip 16460985dd30SLeon Luo * val = 1: vertical flip enabled 16470985dd30SLeon Luo * The caller should hold the mutex lock imx274->lock if necessary 16480985dd30SLeon Luo * 16490985dd30SLeon Luo * Return: 0 on success 16500985dd30SLeon Luo */ 16510985dd30SLeon Luo static int imx274_set_vflip(struct stimx274 *priv, int val) 16520985dd30SLeon Luo { 16530985dd30SLeon Luo int err; 16540985dd30SLeon Luo 16550985dd30SLeon Luo err = imx274_write_reg(priv, IMX274_VFLIP_REG, val); 16560985dd30SLeon Luo if (err) { 16579f67a5e2SLuca Ceresoli dev_err(&priv->client->dev, "VFLIP control error\n"); 16580985dd30SLeon Luo return err; 16590985dd30SLeon Luo } 16600985dd30SLeon Luo 16610985dd30SLeon Luo dev_dbg(&priv->client->dev, 16620985dd30SLeon Luo "%s : VFLIP control success\n", __func__); 16630985dd30SLeon Luo 16640985dd30SLeon Luo return 0; 16650985dd30SLeon Luo } 16660985dd30SLeon Luo 16670985dd30SLeon Luo /* 16680985dd30SLeon Luo * imx274_set_test_pattern - Function called when setting test pattern 16690985dd30SLeon Luo * @priv: Pointer to device structure 16700985dd30SLeon Luo * @val: Variable for test pattern 16710985dd30SLeon Luo * 16720985dd30SLeon Luo * Set to different test patterns based on input value. 16730985dd30SLeon Luo * 16740985dd30SLeon Luo * Return: 0 on success 16750985dd30SLeon Luo */ 16760985dd30SLeon Luo static int imx274_set_test_pattern(struct stimx274 *priv, int val) 16770985dd30SLeon Luo { 16780985dd30SLeon Luo int err = 0; 16790985dd30SLeon Luo 16800985dd30SLeon Luo if (val == TEST_PATTERN_DISABLED) { 16810985dd30SLeon Luo err = imx274_write_table(priv, imx274_tp_disabled); 16820985dd30SLeon Luo } else if (val <= TEST_PATTERN_V_COLOR_BARS) { 16830985dd30SLeon Luo err = imx274_write_reg(priv, IMX274_TEST_PATTERN_REG, val - 1); 16840985dd30SLeon Luo if (!err) 16850985dd30SLeon Luo err = imx274_write_table(priv, imx274_tp_regs); 16860985dd30SLeon Luo } else { 16870985dd30SLeon Luo err = -EINVAL; 16880985dd30SLeon Luo } 16890985dd30SLeon Luo 16900985dd30SLeon Luo if (!err) 16910985dd30SLeon Luo dev_dbg(&priv->client->dev, 16920985dd30SLeon Luo "%s : TEST PATTERN control success\n", __func__); 16930985dd30SLeon Luo else 16940985dd30SLeon Luo dev_err(&priv->client->dev, "%s error = %d\n", __func__, err); 16950985dd30SLeon Luo 16960985dd30SLeon Luo return err; 16970985dd30SLeon Luo } 16980985dd30SLeon Luo 16990985dd30SLeon Luo /* 17000985dd30SLeon Luo * imx274_set_frame_length - Function called when setting frame length 17010985dd30SLeon Luo * @priv: Pointer to device structure 17020985dd30SLeon Luo * @val: Variable for frame length (= VMAX, i.e. vertical drive period length) 17030985dd30SLeon Luo * 17040985dd30SLeon Luo * Set frame length based on input value. 17050985dd30SLeon Luo * 17060985dd30SLeon Luo * Return: 0 on success 17070985dd30SLeon Luo */ 17080985dd30SLeon Luo static int imx274_set_frame_length(struct stimx274 *priv, u32 val) 17090985dd30SLeon Luo { 17100985dd30SLeon Luo int err; 17110985dd30SLeon Luo u32 frame_length; 17120985dd30SLeon Luo 17130985dd30SLeon Luo dev_dbg(&priv->client->dev, "%s : input length = %d\n", 17140985dd30SLeon Luo __func__, val); 17150985dd30SLeon Luo 17160985dd30SLeon Luo frame_length = (u32)val; 17170985dd30SLeon Luo 1718279b4b9aSLuca Ceresoli err = imx274_write_mbreg(priv, IMX274_VMAX_REG_3, frame_length, 3); 17190985dd30SLeon Luo if (err) 17200985dd30SLeon Luo goto fail; 17210985dd30SLeon Luo 17220985dd30SLeon Luo return 0; 17230985dd30SLeon Luo 17240985dd30SLeon Luo fail: 17250985dd30SLeon Luo dev_err(&priv->client->dev, "%s error = %d\n", __func__, err); 17260985dd30SLeon Luo return err; 17270985dd30SLeon Luo } 17280985dd30SLeon Luo 17290985dd30SLeon Luo /* 17300985dd30SLeon Luo * imx274_set_frame_interval - Function called when setting frame interval 17310985dd30SLeon Luo * @priv: Pointer to device structure 17320985dd30SLeon Luo * @frame_interval: Variable for frame interval 17330985dd30SLeon Luo * 17340985dd30SLeon Luo * Change frame interval by updating VMAX value 17350985dd30SLeon Luo * The caller should hold the mutex lock imx274->lock if necessary 17360985dd30SLeon Luo * 17370985dd30SLeon Luo * Return: 0 on success 17380985dd30SLeon Luo */ 17390985dd30SLeon Luo static int imx274_set_frame_interval(struct stimx274 *priv, 17400985dd30SLeon Luo struct v4l2_fract frame_interval) 17410985dd30SLeon Luo { 17420985dd30SLeon Luo int err; 17430985dd30SLeon Luo u32 frame_length, req_frame_rate; 1744ca017467SLuca Ceresoli u32 svr; 1745ca017467SLuca Ceresoli u32 hmax; 17460985dd30SLeon Luo 17470985dd30SLeon Luo dev_dbg(&priv->client->dev, "%s: input frame interval = %d / %d", 17480985dd30SLeon Luo __func__, frame_interval.numerator, 17490985dd30SLeon Luo frame_interval.denominator); 17500985dd30SLeon Luo 17510985dd30SLeon Luo if (frame_interval.numerator == 0) { 17520985dd30SLeon Luo err = -EINVAL; 17530985dd30SLeon Luo goto fail; 17540985dd30SLeon Luo } 17550985dd30SLeon Luo 17560985dd30SLeon Luo req_frame_rate = (u32)(frame_interval.denominator 17570985dd30SLeon Luo / frame_interval.numerator); 17580985dd30SLeon Luo 17590985dd30SLeon Luo /* boundary check */ 176096a2c731SLuca Ceresoli if (req_frame_rate > priv->mode->max_fps) { 17610985dd30SLeon Luo frame_interval.numerator = 1; 176296a2c731SLuca Ceresoli frame_interval.denominator = priv->mode->max_fps; 17630985dd30SLeon Luo } else if (req_frame_rate < IMX274_MIN_FRAME_RATE) { 17640985dd30SLeon Luo frame_interval.numerator = 1; 17650985dd30SLeon Luo frame_interval.denominator = IMX274_MIN_FRAME_RATE; 17660985dd30SLeon Luo } 17670985dd30SLeon Luo 17680985dd30SLeon Luo /* 17690985dd30SLeon Luo * VMAX = 1/frame_rate x 72M / (SVR+1) / HMAX 17700985dd30SLeon Luo * frame_length (i.e. VMAX) = (frame_interval) x 72M /(SVR+1) / HMAX 17710985dd30SLeon Luo */ 17720985dd30SLeon Luo 1773ca017467SLuca Ceresoli err = imx274_read_mbreg(priv, IMX274_SVR_REG_LSB, &svr, 2); 17740985dd30SLeon Luo if (err) 17750985dd30SLeon Luo goto fail; 1776ca017467SLuca Ceresoli 17770985dd30SLeon Luo dev_dbg(&priv->client->dev, 17780985dd30SLeon Luo "%s : register SVR = %d\n", __func__, svr); 17790985dd30SLeon Luo 1780ca017467SLuca Ceresoli err = imx274_read_mbreg(priv, IMX274_HMAX_REG_LSB, &hmax, 2); 17810985dd30SLeon Luo if (err) 17820985dd30SLeon Luo goto fail; 1783ca017467SLuca Ceresoli 17840985dd30SLeon Luo dev_dbg(&priv->client->dev, 17850985dd30SLeon Luo "%s : register HMAX = %d\n", __func__, hmax); 17860985dd30SLeon Luo 17870985dd30SLeon Luo if (hmax == 0 || frame_interval.denominator == 0) { 17880985dd30SLeon Luo err = -EINVAL; 17890985dd30SLeon Luo goto fail; 17900985dd30SLeon Luo } 17910985dd30SLeon Luo 17920985dd30SLeon Luo frame_length = IMX274_PIXCLK_CONST1 / (svr + 1) / hmax 17930985dd30SLeon Luo * frame_interval.numerator 17940985dd30SLeon Luo / frame_interval.denominator; 17950985dd30SLeon Luo 17960985dd30SLeon Luo err = imx274_set_frame_length(priv, frame_length); 17970985dd30SLeon Luo if (err) 17980985dd30SLeon Luo goto fail; 17990985dd30SLeon Luo 18000985dd30SLeon Luo priv->frame_interval = frame_interval; 18010985dd30SLeon Luo return 0; 18020985dd30SLeon Luo 18030985dd30SLeon Luo fail: 18040985dd30SLeon Luo dev_err(&priv->client->dev, "%s error = %d\n", __func__, err); 18050985dd30SLeon Luo return err; 18060985dd30SLeon Luo } 18070985dd30SLeon Luo 18080985dd30SLeon Luo static const struct v4l2_subdev_pad_ops imx274_pad_ops = { 18090985dd30SLeon Luo .get_fmt = imx274_get_fmt, 18100985dd30SLeon Luo .set_fmt = imx274_set_fmt, 181139dd23dcSLuca Ceresoli .get_selection = imx274_get_selection, 181239dd23dcSLuca Ceresoli .set_selection = imx274_set_selection, 18130985dd30SLeon Luo }; 18140985dd30SLeon Luo 18150985dd30SLeon Luo static const struct v4l2_subdev_video_ops imx274_video_ops = { 18160985dd30SLeon Luo .g_frame_interval = imx274_g_frame_interval, 18170985dd30SLeon Luo .s_frame_interval = imx274_s_frame_interval, 18180985dd30SLeon Luo .s_stream = imx274_s_stream, 18190985dd30SLeon Luo }; 18200985dd30SLeon Luo 18210985dd30SLeon Luo static const struct v4l2_subdev_ops imx274_subdev_ops = { 18220985dd30SLeon Luo .pad = &imx274_pad_ops, 18230985dd30SLeon Luo .video = &imx274_video_ops, 18240985dd30SLeon Luo }; 18250985dd30SLeon Luo 18260985dd30SLeon Luo static const struct v4l2_ctrl_ops imx274_ctrl_ops = { 18270985dd30SLeon Luo .s_ctrl = imx274_s_ctrl, 18280985dd30SLeon Luo }; 18290985dd30SLeon Luo 18300985dd30SLeon Luo static const struct of_device_id imx274_of_id_table[] = { 18310985dd30SLeon Luo { .compatible = "sony,imx274" }, 18320985dd30SLeon Luo { } 18330985dd30SLeon Luo }; 18340985dd30SLeon Luo MODULE_DEVICE_TABLE(of, imx274_of_id_table); 18350985dd30SLeon Luo 18360985dd30SLeon Luo static const struct i2c_device_id imx274_id[] = { 18370985dd30SLeon Luo { "IMX274", 0 }, 18380985dd30SLeon Luo { } 18390985dd30SLeon Luo }; 18400985dd30SLeon Luo MODULE_DEVICE_TABLE(i2c, imx274_id); 18410985dd30SLeon Luo 18420985dd30SLeon Luo static int imx274_probe(struct i2c_client *client, 18430985dd30SLeon Luo const struct i2c_device_id *id) 18440985dd30SLeon Luo { 18450985dd30SLeon Luo struct v4l2_subdev *sd; 18460985dd30SLeon Luo struct stimx274 *imx274; 18470985dd30SLeon Luo int ret; 18480985dd30SLeon Luo 18490985dd30SLeon Luo /* initialize imx274 */ 18500985dd30SLeon Luo imx274 = devm_kzalloc(&client->dev, sizeof(*imx274), GFP_KERNEL); 18510985dd30SLeon Luo if (!imx274) 18520985dd30SLeon Luo return -ENOMEM; 18530985dd30SLeon Luo 18540985dd30SLeon Luo mutex_init(&imx274->lock); 18550985dd30SLeon Luo 1856438ac1fdSLuca Ceresoli /* initialize format */ 18579648cb57SLuca Ceresoli imx274->mode = &imx274_modes[IMX274_DEFAULT_BINNING]; 185839dd23dcSLuca Ceresoli imx274->crop.width = IMX274_MAX_WIDTH; 185939dd23dcSLuca Ceresoli imx274->crop.height = IMX274_MAX_HEIGHT; 186039dd23dcSLuca Ceresoli imx274->format.width = imx274->crop.width / imx274->mode->bin_ratio; 186139dd23dcSLuca Ceresoli imx274->format.height = imx274->crop.height / imx274->mode->bin_ratio; 1862438ac1fdSLuca Ceresoli imx274->format.field = V4L2_FIELD_NONE; 1863438ac1fdSLuca Ceresoli imx274->format.code = MEDIA_BUS_FMT_SRGGB10_1X10; 1864438ac1fdSLuca Ceresoli imx274->format.colorspace = V4L2_COLORSPACE_SRGB; 1865438ac1fdSLuca Ceresoli imx274->frame_interval.numerator = 1; 1866438ac1fdSLuca Ceresoli imx274->frame_interval.denominator = IMX274_DEF_FRAME_RATE; 1867438ac1fdSLuca Ceresoli 18680985dd30SLeon Luo /* initialize regmap */ 18690985dd30SLeon Luo imx274->regmap = devm_regmap_init_i2c(client, &imx274_regmap_config); 18700985dd30SLeon Luo if (IS_ERR(imx274->regmap)) { 18710985dd30SLeon Luo dev_err(&client->dev, 18720985dd30SLeon Luo "regmap init failed: %ld\n", PTR_ERR(imx274->regmap)); 18730985dd30SLeon Luo ret = -ENODEV; 18740985dd30SLeon Luo goto err_regmap; 18750985dd30SLeon Luo } 18760985dd30SLeon Luo 18770985dd30SLeon Luo /* initialize subdevice */ 18780985dd30SLeon Luo imx274->client = client; 18790985dd30SLeon Luo sd = &imx274->sd; 18800985dd30SLeon Luo v4l2_i2c_subdev_init(sd, client, &imx274_subdev_ops); 18810985dd30SLeon Luo sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS; 18820985dd30SLeon Luo 18830985dd30SLeon Luo /* initialize subdev media pad */ 18840985dd30SLeon Luo imx274->pad.flags = MEDIA_PAD_FL_SOURCE; 18850985dd30SLeon Luo sd->entity.function = MEDIA_ENT_F_CAM_SENSOR; 18860985dd30SLeon Luo ret = media_entity_pads_init(&sd->entity, 1, &imx274->pad); 18870985dd30SLeon Luo if (ret < 0) { 18880985dd30SLeon Luo dev_err(&client->dev, 18890985dd30SLeon Luo "%s : media entity init Failed %d\n", __func__, ret); 18900985dd30SLeon Luo goto err_regmap; 18910985dd30SLeon Luo } 18920985dd30SLeon Luo 18930985dd30SLeon Luo /* initialize sensor reset gpio */ 18940985dd30SLeon Luo imx274->reset_gpio = devm_gpiod_get_optional(&client->dev, "reset", 18950985dd30SLeon Luo GPIOD_OUT_HIGH); 18960985dd30SLeon Luo if (IS_ERR(imx274->reset_gpio)) { 18970985dd30SLeon Luo if (PTR_ERR(imx274->reset_gpio) != -EPROBE_DEFER) 18980985dd30SLeon Luo dev_err(&client->dev, "Reset GPIO not setup in DT"); 18990985dd30SLeon Luo ret = PTR_ERR(imx274->reset_gpio); 19000985dd30SLeon Luo goto err_me; 19010985dd30SLeon Luo } 19020985dd30SLeon Luo 19030985dd30SLeon Luo /* pull sensor out of reset */ 19040985dd30SLeon Luo imx274_reset(imx274, 1); 19050985dd30SLeon Luo 19060985dd30SLeon Luo /* initialize controls */ 190782f5b507SLuca Ceresoli ret = v4l2_ctrl_handler_init(&imx274->ctrls.handler, 4); 19080985dd30SLeon Luo if (ret < 0) { 19090985dd30SLeon Luo dev_err(&client->dev, 19100985dd30SLeon Luo "%s : ctrl handler init Failed\n", __func__); 19110985dd30SLeon Luo goto err_me; 19120985dd30SLeon Luo } 19130985dd30SLeon Luo 19140985dd30SLeon Luo imx274->ctrls.handler.lock = &imx274->lock; 19150985dd30SLeon Luo 19160985dd30SLeon Luo /* add new controls */ 19170985dd30SLeon Luo imx274->ctrls.test_pattern = v4l2_ctrl_new_std_menu_items( 19180985dd30SLeon Luo &imx274->ctrls.handler, &imx274_ctrl_ops, 19190985dd30SLeon Luo V4L2_CID_TEST_PATTERN, 19200985dd30SLeon Luo ARRAY_SIZE(tp_qmenu) - 1, 0, 0, tp_qmenu); 19210985dd30SLeon Luo 19220985dd30SLeon Luo imx274->ctrls.gain = v4l2_ctrl_new_std( 19230985dd30SLeon Luo &imx274->ctrls.handler, 19240985dd30SLeon Luo &imx274_ctrl_ops, 19250985dd30SLeon Luo V4L2_CID_GAIN, IMX274_MIN_GAIN, 19260985dd30SLeon Luo IMX274_MAX_DIGITAL_GAIN * IMX274_MAX_ANALOG_GAIN, 1, 19270985dd30SLeon Luo IMX274_DEF_GAIN); 19280985dd30SLeon Luo 19290985dd30SLeon Luo imx274->ctrls.exposure = v4l2_ctrl_new_std( 19300985dd30SLeon Luo &imx274->ctrls.handler, 19310985dd30SLeon Luo &imx274_ctrl_ops, 19320985dd30SLeon Luo V4L2_CID_EXPOSURE, IMX274_MIN_EXPOSURE_TIME, 19330985dd30SLeon Luo 1000000 / IMX274_DEF_FRAME_RATE, 1, 19340985dd30SLeon Luo IMX274_MIN_EXPOSURE_TIME); 19350985dd30SLeon Luo 19360985dd30SLeon Luo imx274->ctrls.vflip = v4l2_ctrl_new_std( 19370985dd30SLeon Luo &imx274->ctrls.handler, 19380985dd30SLeon Luo &imx274_ctrl_ops, 19390985dd30SLeon Luo V4L2_CID_VFLIP, 0, 1, 1, 0); 19400985dd30SLeon Luo 19410985dd30SLeon Luo imx274->sd.ctrl_handler = &imx274->ctrls.handler; 19420985dd30SLeon Luo if (imx274->ctrls.handler.error) { 19430985dd30SLeon Luo ret = imx274->ctrls.handler.error; 19440985dd30SLeon Luo goto err_ctrls; 19450985dd30SLeon Luo } 19460985dd30SLeon Luo 19470985dd30SLeon Luo /* setup default controls */ 19480985dd30SLeon Luo ret = v4l2_ctrl_handler_setup(&imx274->ctrls.handler); 19490985dd30SLeon Luo if (ret) { 19500985dd30SLeon Luo dev_err(&client->dev, 19510985dd30SLeon Luo "Error %d setup default controls\n", ret); 19520985dd30SLeon Luo goto err_ctrls; 19530985dd30SLeon Luo } 19540985dd30SLeon Luo 19550985dd30SLeon Luo /* load default control values */ 19560985dd30SLeon Luo ret = imx274_load_default(imx274); 19570985dd30SLeon Luo if (ret) { 19580985dd30SLeon Luo dev_err(&client->dev, 19590985dd30SLeon Luo "%s : imx274_load_default failed %d\n", 19600985dd30SLeon Luo __func__, ret); 19610985dd30SLeon Luo goto err_ctrls; 19620985dd30SLeon Luo } 19630985dd30SLeon Luo 19640985dd30SLeon Luo /* register subdevice */ 19650985dd30SLeon Luo ret = v4l2_async_register_subdev(sd); 19660985dd30SLeon Luo if (ret < 0) { 19670985dd30SLeon Luo dev_err(&client->dev, 19680985dd30SLeon Luo "%s : v4l2_async_register_subdev failed %d\n", 19690985dd30SLeon Luo __func__, ret); 19700985dd30SLeon Luo goto err_ctrls; 19710985dd30SLeon Luo } 19720985dd30SLeon Luo 19730985dd30SLeon Luo dev_info(&client->dev, "imx274 : imx274 probe success !\n"); 19740985dd30SLeon Luo return 0; 19750985dd30SLeon Luo 19760985dd30SLeon Luo err_ctrls: 1977781b045bSSakari Ailus v4l2_ctrl_handler_free(&imx274->ctrls.handler); 19780985dd30SLeon Luo err_me: 19790985dd30SLeon Luo media_entity_cleanup(&sd->entity); 19800985dd30SLeon Luo err_regmap: 19810985dd30SLeon Luo mutex_destroy(&imx274->lock); 19820985dd30SLeon Luo return ret; 19830985dd30SLeon Luo } 19840985dd30SLeon Luo 19850985dd30SLeon Luo static int imx274_remove(struct i2c_client *client) 19860985dd30SLeon Luo { 19870985dd30SLeon Luo struct v4l2_subdev *sd = i2c_get_clientdata(client); 19880985dd30SLeon Luo struct stimx274 *imx274 = to_imx274(sd); 19890985dd30SLeon Luo 19900985dd30SLeon Luo /* stop stream */ 19918ed8bba7SLuca Ceresoli imx274_write_table(imx274, imx274_stop); 19920985dd30SLeon Luo 19930985dd30SLeon Luo v4l2_async_unregister_subdev(sd); 1994781b045bSSakari Ailus v4l2_ctrl_handler_free(&imx274->ctrls.handler); 19950985dd30SLeon Luo media_entity_cleanup(&sd->entity); 19960985dd30SLeon Luo mutex_destroy(&imx274->lock); 19970985dd30SLeon Luo return 0; 19980985dd30SLeon Luo } 19990985dd30SLeon Luo 20000985dd30SLeon Luo static struct i2c_driver imx274_i2c_driver = { 20010985dd30SLeon Luo .driver = { 20020985dd30SLeon Luo .name = DRIVER_NAME, 20030985dd30SLeon Luo .of_match_table = imx274_of_id_table, 20040985dd30SLeon Luo }, 20050985dd30SLeon Luo .probe = imx274_probe, 20060985dd30SLeon Luo .remove = imx274_remove, 20070985dd30SLeon Luo .id_table = imx274_id, 20080985dd30SLeon Luo }; 20090985dd30SLeon Luo 20100985dd30SLeon Luo module_i2c_driver(imx274_i2c_driver); 20110985dd30SLeon Luo 20120985dd30SLeon Luo MODULE_AUTHOR("Leon Luo <leonl@leopardimaging.com>"); 20130985dd30SLeon Luo MODULE_DESCRIPTION("IMX274 CMOS Image Sensor driver"); 20140985dd30SLeon Luo MODULE_LICENSE("GPL v2"); 2015