1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * A V4L2 driver for Sony IMX219 cameras. 4 * Copyright (C) 2019, Raspberry Pi (Trading) Ltd 5 * 6 * Based on Sony imx258 camera driver 7 * Copyright (C) 2018 Intel Corporation 8 * 9 * DT / fwnode changes, and regulator / GPIO control taken from imx214 driver 10 * Copyright 2018 Qtechnology A/S 11 * 12 * Flip handling taken from the Sony IMX319 driver. 13 * Copyright (C) 2018 Intel Corporation 14 * 15 */ 16 17 #include <linux/clk.h> 18 #include <linux/delay.h> 19 #include <linux/gpio/consumer.h> 20 #include <linux/i2c.h> 21 #include <linux/module.h> 22 #include <linux/pm_runtime.h> 23 #include <linux/regulator/consumer.h> 24 25 #include <media/v4l2-cci.h> 26 #include <media/v4l2-ctrls.h> 27 #include <media/v4l2-device.h> 28 #include <media/v4l2-event.h> 29 #include <media/v4l2-fwnode.h> 30 #include <media/v4l2-mediabus.h> 31 32 /* Chip ID */ 33 #define IMX219_REG_CHIP_ID CCI_REG16(0x0000) 34 #define IMX219_CHIP_ID 0x0219 35 36 #define IMX219_REG_MODE_SELECT CCI_REG8(0x0100) 37 #define IMX219_MODE_STANDBY 0x00 38 #define IMX219_MODE_STREAMING 0x01 39 40 #define IMX219_REG_CSI_LANE_MODE CCI_REG8(0x0114) 41 #define IMX219_CSI_2_LANE_MODE 0x01 42 #define IMX219_CSI_4_LANE_MODE 0x03 43 44 #define IMX219_REG_DPHY_CTRL CCI_REG8(0x0128) 45 #define IMX219_DPHY_CTRL_TIMING_AUTO 0 46 #define IMX219_DPHY_CTRL_TIMING_MANUAL 1 47 48 #define IMX219_REG_EXCK_FREQ CCI_REG16(0x012a) 49 #define IMX219_EXCK_FREQ(n) ((n) * 256) /* n expressed in MHz */ 50 51 /* Analog gain control */ 52 #define IMX219_REG_ANALOG_GAIN CCI_REG8(0x0157) 53 #define IMX219_ANA_GAIN_MIN 0 54 #define IMX219_ANA_GAIN_MAX 232 55 #define IMX219_ANA_GAIN_STEP 1 56 #define IMX219_ANA_GAIN_DEFAULT 0x0 57 58 /* Digital gain control */ 59 #define IMX219_REG_DIGITAL_GAIN CCI_REG16(0x0158) 60 #define IMX219_DGTL_GAIN_MIN 0x0100 61 #define IMX219_DGTL_GAIN_MAX 0x0fff 62 #define IMX219_DGTL_GAIN_DEFAULT 0x0100 63 #define IMX219_DGTL_GAIN_STEP 1 64 65 /* Exposure control */ 66 #define IMX219_REG_EXPOSURE CCI_REG16(0x015a) 67 #define IMX219_EXPOSURE_MIN 4 68 #define IMX219_EXPOSURE_STEP 1 69 #define IMX219_EXPOSURE_DEFAULT 0x640 70 #define IMX219_EXPOSURE_MAX 65535 71 72 /* V_TIMING internal */ 73 #define IMX219_REG_VTS CCI_REG16(0x0160) 74 #define IMX219_VTS_15FPS 0x0dc6 75 #define IMX219_VTS_30FPS_1080P 0x06e3 76 #define IMX219_VTS_30FPS_BINNED 0x06e3 77 #define IMX219_VTS_30FPS_640x480 0x06e3 78 #define IMX219_VTS_MAX 0xffff 79 80 #define IMX219_VBLANK_MIN 4 81 82 /*Frame Length Line*/ 83 #define IMX219_FLL_MIN 0x08a6 84 #define IMX219_FLL_MAX 0xffff 85 #define IMX219_FLL_STEP 1 86 #define IMX219_FLL_DEFAULT 0x0c98 87 88 /* HBLANK control - read only */ 89 #define IMX219_PPL_DEFAULT 3448 90 91 #define IMX219_REG_LINE_LENGTH_A CCI_REG16(0x0162) 92 #define IMX219_REG_X_ADD_STA_A CCI_REG16(0x0164) 93 #define IMX219_REG_X_ADD_END_A CCI_REG16(0x0166) 94 #define IMX219_REG_Y_ADD_STA_A CCI_REG16(0x0168) 95 #define IMX219_REG_Y_ADD_END_A CCI_REG16(0x016a) 96 #define IMX219_REG_X_OUTPUT_SIZE CCI_REG16(0x016c) 97 #define IMX219_REG_Y_OUTPUT_SIZE CCI_REG16(0x016e) 98 #define IMX219_REG_X_ODD_INC_A CCI_REG8(0x0170) 99 #define IMX219_REG_Y_ODD_INC_A CCI_REG8(0x0171) 100 #define IMX219_REG_ORIENTATION CCI_REG8(0x0172) 101 102 /* Binning Mode */ 103 #define IMX219_REG_BINNING_MODE CCI_REG16(0x0174) 104 #define IMX219_BINNING_NONE 0x0000 105 #define IMX219_BINNING_2X2 0x0101 106 #define IMX219_BINNING_2X2_ANALOG 0x0303 107 108 #define IMX219_REG_CSI_DATA_FORMAT_A CCI_REG16(0x018c) 109 110 /* PLL Settings */ 111 #define IMX219_REG_VTPXCK_DIV CCI_REG8(0x0301) 112 #define IMX219_REG_VTSYCK_DIV CCI_REG8(0x0303) 113 #define IMX219_REG_PREPLLCK_VT_DIV CCI_REG8(0x0304) 114 #define IMX219_REG_PREPLLCK_OP_DIV CCI_REG8(0x0305) 115 #define IMX219_REG_PLL_VT_MPY CCI_REG16(0x0306) 116 #define IMX219_REG_OPPXCK_DIV CCI_REG8(0x0309) 117 #define IMX219_REG_OPSYCK_DIV CCI_REG8(0x030b) 118 #define IMX219_REG_PLL_OP_MPY CCI_REG16(0x030c) 119 120 /* Test Pattern Control */ 121 #define IMX219_REG_TEST_PATTERN CCI_REG16(0x0600) 122 #define IMX219_TEST_PATTERN_DISABLE 0 123 #define IMX219_TEST_PATTERN_SOLID_COLOR 1 124 #define IMX219_TEST_PATTERN_COLOR_BARS 2 125 #define IMX219_TEST_PATTERN_GREY_COLOR 3 126 #define IMX219_TEST_PATTERN_PN9 4 127 128 /* Test pattern colour components */ 129 #define IMX219_REG_TESTP_RED CCI_REG16(0x0602) 130 #define IMX219_REG_TESTP_GREENR CCI_REG16(0x0604) 131 #define IMX219_REG_TESTP_BLUE CCI_REG16(0x0606) 132 #define IMX219_REG_TESTP_GREENB CCI_REG16(0x0608) 133 #define IMX219_TESTP_COLOUR_MIN 0 134 #define IMX219_TESTP_COLOUR_MAX 0x03ff 135 #define IMX219_TESTP_COLOUR_STEP 1 136 #define IMX219_TESTP_RED_DEFAULT IMX219_TESTP_COLOUR_MAX 137 #define IMX219_TESTP_GREENR_DEFAULT 0 138 #define IMX219_TESTP_BLUE_DEFAULT 0 139 #define IMX219_TESTP_GREENB_DEFAULT 0 140 141 #define IMX219_REG_TP_WINDOW_WIDTH CCI_REG16(0x0624) 142 #define IMX219_REG_TP_WINDOW_HEIGHT CCI_REG16(0x0626) 143 144 /* External clock frequency is 24.0M */ 145 #define IMX219_XCLK_FREQ 24000000 146 147 /* Pixel rate is fixed for all the modes */ 148 #define IMX219_PIXEL_RATE 182400000 149 #define IMX219_PIXEL_RATE_4LANE 280800000 150 151 #define IMX219_DEFAULT_LINK_FREQ 456000000 152 #define IMX219_DEFAULT_LINK_FREQ_4LANE 363000000 153 154 /* IMX219 native and active pixel array size. */ 155 #define IMX219_NATIVE_WIDTH 3296U 156 #define IMX219_NATIVE_HEIGHT 2480U 157 #define IMX219_PIXEL_ARRAY_LEFT 8U 158 #define IMX219_PIXEL_ARRAY_TOP 8U 159 #define IMX219_PIXEL_ARRAY_WIDTH 3280U 160 #define IMX219_PIXEL_ARRAY_HEIGHT 2464U 161 162 struct imx219_reg_list { 163 unsigned int num_of_regs; 164 const struct cci_reg_sequence *regs; 165 }; 166 167 /* Mode : resolution and related config&values */ 168 struct imx219_mode { 169 /* Frame width */ 170 unsigned int width; 171 /* Frame height */ 172 unsigned int height; 173 174 /* Analog crop rectangle. */ 175 struct v4l2_rect crop; 176 177 /* V-timing */ 178 unsigned int vts_def; 179 180 /* Default register values */ 181 struct imx219_reg_list reg_list; 182 183 /* 2x2 binning is used */ 184 bool binning; 185 }; 186 187 static const struct cci_reg_sequence imx219_common_regs[] = { 188 { IMX219_REG_MODE_SELECT, 0x00 }, /* Mode Select */ 189 190 /* To Access Addresses 3000-5fff, send the following commands */ 191 { CCI_REG8(0x30eb), 0x0c }, 192 { CCI_REG8(0x30eb), 0x05 }, 193 { CCI_REG8(0x300a), 0xff }, 194 { CCI_REG8(0x300b), 0xff }, 195 { CCI_REG8(0x30eb), 0x05 }, 196 { CCI_REG8(0x30eb), 0x09 }, 197 198 /* PLL Clock Table */ 199 { IMX219_REG_VTPXCK_DIV, 5 }, 200 { IMX219_REG_VTSYCK_DIV, 1 }, 201 { IMX219_REG_PREPLLCK_VT_DIV, 3 }, /* 0x03 = AUTO set */ 202 { IMX219_REG_PREPLLCK_OP_DIV, 3 }, /* 0x03 = AUTO set */ 203 { IMX219_REG_PLL_VT_MPY, 57 }, 204 { IMX219_REG_OPSYCK_DIV, 1 }, 205 { IMX219_REG_PLL_OP_MPY, 114 }, 206 207 /* Undocumented registers */ 208 { CCI_REG8(0x455e), 0x00 }, 209 { CCI_REG8(0x471e), 0x4b }, 210 { CCI_REG8(0x4767), 0x0f }, 211 { CCI_REG8(0x4750), 0x14 }, 212 { CCI_REG8(0x4540), 0x00 }, 213 { CCI_REG8(0x47b4), 0x14 }, 214 { CCI_REG8(0x4713), 0x30 }, 215 { CCI_REG8(0x478b), 0x10 }, 216 { CCI_REG8(0x478f), 0x10 }, 217 { CCI_REG8(0x4793), 0x10 }, 218 { CCI_REG8(0x4797), 0x0e }, 219 { CCI_REG8(0x479b), 0x0e }, 220 221 /* Frame Bank Register Group "A" */ 222 { IMX219_REG_LINE_LENGTH_A, 3448 }, 223 { IMX219_REG_X_ODD_INC_A, 1 }, 224 { IMX219_REG_Y_ODD_INC_A, 1 }, 225 226 /* Output setup registers */ 227 { IMX219_REG_DPHY_CTRL, IMX219_DPHY_CTRL_TIMING_AUTO }, 228 { IMX219_REG_EXCK_FREQ, IMX219_EXCK_FREQ(IMX219_XCLK_FREQ / 1000000) }, 229 }; 230 231 /* 232 * Register sets lifted off the i2C interface from the Raspberry Pi firmware 233 * driver. 234 * 3280x2464 = mode 2, 1920x1080 = mode 1, 1640x1232 = mode 4, 640x480 = mode 7. 235 */ 236 static const struct cci_reg_sequence mode_3280x2464_regs[] = { 237 { IMX219_REG_X_ADD_STA_A, 0 }, 238 { IMX219_REG_X_ADD_END_A, 3279 }, 239 { IMX219_REG_Y_ADD_STA_A, 0 }, 240 { IMX219_REG_Y_ADD_END_A, 2463 }, 241 { IMX219_REG_X_OUTPUT_SIZE, 3280 }, 242 { IMX219_REG_Y_OUTPUT_SIZE, 2464 }, 243 { IMX219_REG_TP_WINDOW_WIDTH, 3280 }, 244 { IMX219_REG_TP_WINDOW_HEIGHT, 2464 }, 245 }; 246 247 static const struct cci_reg_sequence mode_1920_1080_regs[] = { 248 { IMX219_REG_X_ADD_STA_A, 680 }, 249 { IMX219_REG_X_ADD_END_A, 2599 }, 250 { IMX219_REG_Y_ADD_STA_A, 692 }, 251 { IMX219_REG_Y_ADD_END_A, 1771 }, 252 { IMX219_REG_X_OUTPUT_SIZE, 1920 }, 253 { IMX219_REG_Y_OUTPUT_SIZE, 1080 }, 254 { IMX219_REG_TP_WINDOW_WIDTH, 1920 }, 255 { IMX219_REG_TP_WINDOW_HEIGHT, 1080 }, 256 }; 257 258 static const struct cci_reg_sequence mode_1640_1232_regs[] = { 259 { IMX219_REG_X_ADD_STA_A, 0 }, 260 { IMX219_REG_X_ADD_END_A, 3279 }, 261 { IMX219_REG_Y_ADD_STA_A, 0 }, 262 { IMX219_REG_Y_ADD_END_A, 2463 }, 263 { IMX219_REG_X_OUTPUT_SIZE, 1640 }, 264 { IMX219_REG_Y_OUTPUT_SIZE, 1232 }, 265 { IMX219_REG_TP_WINDOW_WIDTH, 1640 }, 266 { IMX219_REG_TP_WINDOW_HEIGHT, 1232 }, 267 }; 268 269 static const struct cci_reg_sequence mode_640_480_regs[] = { 270 { IMX219_REG_X_ADD_STA_A, 1000 }, 271 { IMX219_REG_X_ADD_END_A, 2279 }, 272 { IMX219_REG_Y_ADD_STA_A, 752 }, 273 { IMX219_REG_Y_ADD_END_A, 1711 }, 274 { IMX219_REG_X_OUTPUT_SIZE, 640 }, 275 { IMX219_REG_Y_OUTPUT_SIZE, 480 }, 276 { IMX219_REG_TP_WINDOW_WIDTH, 1640 }, 277 { IMX219_REG_TP_WINDOW_HEIGHT, 1232 }, 278 }; 279 280 static const struct cci_reg_sequence raw8_framefmt_regs[] = { 281 { IMX219_REG_CSI_DATA_FORMAT_A, 0x0808 }, 282 { IMX219_REG_OPPXCK_DIV, 8 }, 283 }; 284 285 static const struct cci_reg_sequence raw10_framefmt_regs[] = { 286 { IMX219_REG_CSI_DATA_FORMAT_A, 0x0a0a }, 287 { IMX219_REG_OPPXCK_DIV, 10 }, 288 }; 289 290 static const s64 imx219_link_freq_menu[] = { 291 IMX219_DEFAULT_LINK_FREQ, 292 }; 293 294 static const s64 imx219_link_freq_4lane_menu[] = { 295 IMX219_DEFAULT_LINK_FREQ_4LANE, 296 }; 297 298 static const char * const imx219_test_pattern_menu[] = { 299 "Disabled", 300 "Color Bars", 301 "Solid Color", 302 "Grey Color Bars", 303 "PN9" 304 }; 305 306 static const int imx219_test_pattern_val[] = { 307 IMX219_TEST_PATTERN_DISABLE, 308 IMX219_TEST_PATTERN_COLOR_BARS, 309 IMX219_TEST_PATTERN_SOLID_COLOR, 310 IMX219_TEST_PATTERN_GREY_COLOR, 311 IMX219_TEST_PATTERN_PN9, 312 }; 313 314 /* regulator supplies */ 315 static const char * const imx219_supply_name[] = { 316 /* Supplies can be enabled in any order */ 317 "VANA", /* Analog (2.8V) supply */ 318 "VDIG", /* Digital Core (1.8V) supply */ 319 "VDDL", /* IF (1.2V) supply */ 320 }; 321 322 #define IMX219_NUM_SUPPLIES ARRAY_SIZE(imx219_supply_name) 323 324 /* 325 * The supported formats. 326 * This table MUST contain 4 entries per format, to cover the various flip 327 * combinations in the order 328 * - no flip 329 * - h flip 330 * - v flip 331 * - h&v flips 332 */ 333 static const u32 imx219_mbus_formats[] = { 334 MEDIA_BUS_FMT_SRGGB10_1X10, 335 MEDIA_BUS_FMT_SGRBG10_1X10, 336 MEDIA_BUS_FMT_SGBRG10_1X10, 337 MEDIA_BUS_FMT_SBGGR10_1X10, 338 339 MEDIA_BUS_FMT_SRGGB8_1X8, 340 MEDIA_BUS_FMT_SGRBG8_1X8, 341 MEDIA_BUS_FMT_SGBRG8_1X8, 342 MEDIA_BUS_FMT_SBGGR8_1X8, 343 }; 344 345 /* 346 * Initialisation delay between XCLR low->high and the moment when the sensor 347 * can start capture (i.e. can leave software stanby) must be not less than: 348 * t4 + max(t5, t6 + <time to initialize the sensor register over I2C>) 349 * where 350 * t4 is fixed, and is max 200uS, 351 * t5 is fixed, and is 6000uS, 352 * t6 depends on the sensor external clock, and is max 32000 clock periods. 353 * As per sensor datasheet, the external clock must be from 6MHz to 27MHz. 354 * So for any acceptable external clock t6 is always within the range of 355 * 1185 to 5333 uS, and is always less than t5. 356 * For this reason this is always safe to wait (t4 + t5) = 6200 uS, then 357 * initialize the sensor over I2C, and then exit the software standby. 358 * 359 * This start-up time can be optimized a bit more, if we start the writes 360 * over I2C after (t4+t6), but before (t4+t5) expires. But then sensor 361 * initialization over I2C may complete before (t4+t5) expires, and we must 362 * ensure that capture is not started before (t4+t5). 363 * 364 * This delay doesn't account for the power supply startup time. If needed, 365 * this should be taken care of via the regulator framework. E.g. in the 366 * case of DT for regulator-fixed one should define the startup-delay-us 367 * property. 368 */ 369 #define IMX219_XCLR_MIN_DELAY_US 6200 370 #define IMX219_XCLR_DELAY_RANGE_US 1000 371 372 /* Mode configs */ 373 static const struct imx219_mode supported_modes[] = { 374 { 375 /* 8MPix 15fps mode */ 376 .width = 3280, 377 .height = 2464, 378 .crop = { 379 .left = IMX219_PIXEL_ARRAY_LEFT, 380 .top = IMX219_PIXEL_ARRAY_TOP, 381 .width = 3280, 382 .height = 2464 383 }, 384 .vts_def = IMX219_VTS_15FPS, 385 .reg_list = { 386 .num_of_regs = ARRAY_SIZE(mode_3280x2464_regs), 387 .regs = mode_3280x2464_regs, 388 }, 389 .binning = false, 390 }, 391 { 392 /* 1080P 30fps cropped */ 393 .width = 1920, 394 .height = 1080, 395 .crop = { 396 .left = 688, 397 .top = 700, 398 .width = 1920, 399 .height = 1080 400 }, 401 .vts_def = IMX219_VTS_30FPS_1080P, 402 .reg_list = { 403 .num_of_regs = ARRAY_SIZE(mode_1920_1080_regs), 404 .regs = mode_1920_1080_regs, 405 }, 406 .binning = false, 407 }, 408 { 409 /* 2x2 binned 30fps mode */ 410 .width = 1640, 411 .height = 1232, 412 .crop = { 413 .left = IMX219_PIXEL_ARRAY_LEFT, 414 .top = IMX219_PIXEL_ARRAY_TOP, 415 .width = 3280, 416 .height = 2464 417 }, 418 .vts_def = IMX219_VTS_30FPS_BINNED, 419 .reg_list = { 420 .num_of_regs = ARRAY_SIZE(mode_1640_1232_regs), 421 .regs = mode_1640_1232_regs, 422 }, 423 .binning = true, 424 }, 425 { 426 /* 640x480 30fps mode */ 427 .width = 640, 428 .height = 480, 429 .crop = { 430 .left = 1008, 431 .top = 760, 432 .width = 1280, 433 .height = 960 434 }, 435 .vts_def = IMX219_VTS_30FPS_640x480, 436 .reg_list = { 437 .num_of_regs = ARRAY_SIZE(mode_640_480_regs), 438 .regs = mode_640_480_regs, 439 }, 440 .binning = true, 441 }, 442 }; 443 444 struct imx219 { 445 struct v4l2_subdev sd; 446 struct media_pad pad; 447 448 struct regmap *regmap; 449 struct clk *xclk; /* system clock to IMX219 */ 450 u32 xclk_freq; 451 452 struct gpio_desc *reset_gpio; 453 struct regulator_bulk_data supplies[IMX219_NUM_SUPPLIES]; 454 455 struct v4l2_ctrl_handler ctrl_handler; 456 /* V4L2 Controls */ 457 struct v4l2_ctrl *pixel_rate; 458 struct v4l2_ctrl *link_freq; 459 struct v4l2_ctrl *exposure; 460 struct v4l2_ctrl *vflip; 461 struct v4l2_ctrl *hflip; 462 struct v4l2_ctrl *vblank; 463 struct v4l2_ctrl *hblank; 464 465 /* Current mode */ 466 const struct imx219_mode *mode; 467 468 /* Streaming on/off */ 469 bool streaming; 470 471 /* Two or Four lanes */ 472 u8 lanes; 473 }; 474 475 static inline struct imx219 *to_imx219(struct v4l2_subdev *_sd) 476 { 477 return container_of(_sd, struct imx219, sd); 478 } 479 480 /* Get bayer order based on flip setting. */ 481 static u32 imx219_get_format_code(struct imx219 *imx219, u32 code) 482 { 483 unsigned int i; 484 485 for (i = 0; i < ARRAY_SIZE(imx219_mbus_formats); i++) 486 if (imx219_mbus_formats[i] == code) 487 break; 488 489 if (i >= ARRAY_SIZE(imx219_mbus_formats)) 490 i = 0; 491 492 i = (i & ~3) | (imx219->vflip->val ? 2 : 0) | 493 (imx219->hflip->val ? 1 : 0); 494 495 return imx219_mbus_formats[i]; 496 } 497 498 static int imx219_set_ctrl(struct v4l2_ctrl *ctrl) 499 { 500 struct imx219 *imx219 = 501 container_of(ctrl->handler, struct imx219, ctrl_handler); 502 struct i2c_client *client = v4l2_get_subdevdata(&imx219->sd); 503 int ret = 0; 504 505 if (ctrl->id == V4L2_CID_VBLANK) { 506 int exposure_max, exposure_def; 507 508 /* Update max exposure while meeting expected vblanking */ 509 exposure_max = imx219->mode->height + ctrl->val - 4; 510 exposure_def = (exposure_max < IMX219_EXPOSURE_DEFAULT) ? 511 exposure_max : IMX219_EXPOSURE_DEFAULT; 512 __v4l2_ctrl_modify_range(imx219->exposure, 513 imx219->exposure->minimum, 514 exposure_max, imx219->exposure->step, 515 exposure_def); 516 } 517 518 /* 519 * Applying V4L2 control value only happens 520 * when power is up for streaming 521 */ 522 if (pm_runtime_get_if_in_use(&client->dev) == 0) 523 return 0; 524 525 switch (ctrl->id) { 526 case V4L2_CID_ANALOGUE_GAIN: 527 cci_write(imx219->regmap, IMX219_REG_ANALOG_GAIN, 528 ctrl->val, &ret); 529 break; 530 case V4L2_CID_EXPOSURE: 531 cci_write(imx219->regmap, IMX219_REG_EXPOSURE, 532 ctrl->val, &ret); 533 break; 534 case V4L2_CID_DIGITAL_GAIN: 535 cci_write(imx219->regmap, IMX219_REG_DIGITAL_GAIN, 536 ctrl->val, &ret); 537 break; 538 case V4L2_CID_TEST_PATTERN: 539 cci_write(imx219->regmap, IMX219_REG_TEST_PATTERN, 540 imx219_test_pattern_val[ctrl->val], &ret); 541 break; 542 case V4L2_CID_HFLIP: 543 case V4L2_CID_VFLIP: 544 cci_write(imx219->regmap, IMX219_REG_ORIENTATION, 545 imx219->hflip->val | imx219->vflip->val << 1, &ret); 546 break; 547 case V4L2_CID_VBLANK: 548 cci_write(imx219->regmap, IMX219_REG_VTS, 549 imx219->mode->height + ctrl->val, &ret); 550 break; 551 case V4L2_CID_TEST_PATTERN_RED: 552 cci_write(imx219->regmap, IMX219_REG_TESTP_RED, 553 ctrl->val, &ret); 554 break; 555 case V4L2_CID_TEST_PATTERN_GREENR: 556 cci_write(imx219->regmap, IMX219_REG_TESTP_GREENR, 557 ctrl->val, &ret); 558 break; 559 case V4L2_CID_TEST_PATTERN_BLUE: 560 cci_write(imx219->regmap, IMX219_REG_TESTP_BLUE, 561 ctrl->val, &ret); 562 break; 563 case V4L2_CID_TEST_PATTERN_GREENB: 564 cci_write(imx219->regmap, IMX219_REG_TESTP_GREENB, 565 ctrl->val, &ret); 566 break; 567 default: 568 dev_info(&client->dev, 569 "ctrl(id:0x%x,val:0x%x) is not handled\n", 570 ctrl->id, ctrl->val); 571 ret = -EINVAL; 572 break; 573 } 574 575 pm_runtime_put(&client->dev); 576 577 return ret; 578 } 579 580 static const struct v4l2_ctrl_ops imx219_ctrl_ops = { 581 .s_ctrl = imx219_set_ctrl, 582 }; 583 584 static void imx219_update_pad_format(struct imx219 *imx219, 585 const struct imx219_mode *mode, 586 struct v4l2_mbus_framefmt *fmt, u32 code) 587 { 588 /* Bayer order varies with flips */ 589 fmt->code = imx219_get_format_code(imx219, code); 590 fmt->width = mode->width; 591 fmt->height = mode->height; 592 fmt->field = V4L2_FIELD_NONE; 593 fmt->colorspace = V4L2_COLORSPACE_RAW; 594 fmt->quantization = V4L2_QUANTIZATION_FULL_RANGE; 595 fmt->xfer_func = V4L2_XFER_FUNC_NONE; 596 } 597 598 static int imx219_init_cfg(struct v4l2_subdev *sd, 599 struct v4l2_subdev_state *state) 600 { 601 struct imx219 *imx219 = to_imx219(sd); 602 struct v4l2_mbus_framefmt *format; 603 struct v4l2_rect *crop; 604 605 /* Initialize the format. */ 606 format = v4l2_subdev_get_pad_format(sd, state, 0); 607 imx219_update_pad_format(imx219, &supported_modes[0], format, 608 MEDIA_BUS_FMT_SRGGB10_1X10); 609 610 /* Initialize the crop rectangle. */ 611 crop = v4l2_subdev_get_pad_crop(sd, state, 0); 612 crop->top = IMX219_PIXEL_ARRAY_TOP; 613 crop->left = IMX219_PIXEL_ARRAY_LEFT; 614 crop->width = IMX219_PIXEL_ARRAY_WIDTH; 615 crop->height = IMX219_PIXEL_ARRAY_HEIGHT; 616 617 return 0; 618 } 619 620 static int imx219_enum_mbus_code(struct v4l2_subdev *sd, 621 struct v4l2_subdev_state *sd_state, 622 struct v4l2_subdev_mbus_code_enum *code) 623 { 624 struct imx219 *imx219 = to_imx219(sd); 625 626 if (code->index >= (ARRAY_SIZE(imx219_mbus_formats) / 4)) 627 return -EINVAL; 628 629 code->code = imx219_get_format_code(imx219, imx219_mbus_formats[code->index * 4]); 630 631 return 0; 632 } 633 634 static int imx219_enum_frame_size(struct v4l2_subdev *sd, 635 struct v4l2_subdev_state *sd_state, 636 struct v4l2_subdev_frame_size_enum *fse) 637 { 638 struct imx219 *imx219 = to_imx219(sd); 639 u32 code; 640 641 if (fse->index >= ARRAY_SIZE(supported_modes)) 642 return -EINVAL; 643 644 code = imx219_get_format_code(imx219, fse->code); 645 if (fse->code != code) 646 return -EINVAL; 647 648 fse->min_width = supported_modes[fse->index].width; 649 fse->max_width = fse->min_width; 650 fse->min_height = supported_modes[fse->index].height; 651 fse->max_height = fse->min_height; 652 653 return 0; 654 } 655 656 static int imx219_set_pad_format(struct v4l2_subdev *sd, 657 struct v4l2_subdev_state *sd_state, 658 struct v4l2_subdev_format *fmt) 659 { 660 struct imx219 *imx219 = to_imx219(sd); 661 const struct imx219_mode *mode; 662 int exposure_max, exposure_def, hblank; 663 struct v4l2_mbus_framefmt *format; 664 struct v4l2_rect *crop; 665 666 mode = v4l2_find_nearest_size(supported_modes, 667 ARRAY_SIZE(supported_modes), 668 width, height, 669 fmt->format.width, fmt->format.height); 670 671 imx219_update_pad_format(imx219, mode, &fmt->format, fmt->format.code); 672 673 format = v4l2_subdev_get_pad_format(sd, sd_state, 0); 674 crop = v4l2_subdev_get_pad_crop(sd, sd_state, 0); 675 676 *format = fmt->format; 677 *crop = mode->crop; 678 679 if (fmt->which == V4L2_SUBDEV_FORMAT_ACTIVE) { 680 imx219->mode = mode; 681 /* Update limits and set FPS to default */ 682 __v4l2_ctrl_modify_range(imx219->vblank, IMX219_VBLANK_MIN, 683 IMX219_VTS_MAX - mode->height, 1, 684 mode->vts_def - mode->height); 685 __v4l2_ctrl_s_ctrl(imx219->vblank, 686 mode->vts_def - mode->height); 687 /* Update max exposure while meeting expected vblanking */ 688 exposure_max = mode->vts_def - 4; 689 exposure_def = (exposure_max < IMX219_EXPOSURE_DEFAULT) ? 690 exposure_max : IMX219_EXPOSURE_DEFAULT; 691 __v4l2_ctrl_modify_range(imx219->exposure, 692 imx219->exposure->minimum, 693 exposure_max, imx219->exposure->step, 694 exposure_def); 695 /* 696 * Currently PPL is fixed to IMX219_PPL_DEFAULT, so hblank 697 * depends on mode->width only, and is not changeble in any 698 * way other than changing the mode. 699 */ 700 hblank = IMX219_PPL_DEFAULT - mode->width; 701 __v4l2_ctrl_modify_range(imx219->hblank, hblank, hblank, 1, 702 hblank); 703 } 704 705 return 0; 706 } 707 708 static int imx219_set_framefmt(struct imx219 *imx219, 709 const struct v4l2_mbus_framefmt *format) 710 { 711 switch (format->code) { 712 case MEDIA_BUS_FMT_SRGGB8_1X8: 713 case MEDIA_BUS_FMT_SGRBG8_1X8: 714 case MEDIA_BUS_FMT_SGBRG8_1X8: 715 case MEDIA_BUS_FMT_SBGGR8_1X8: 716 return cci_multi_reg_write(imx219->regmap, raw8_framefmt_regs, 717 ARRAY_SIZE(raw8_framefmt_regs), NULL); 718 719 case MEDIA_BUS_FMT_SRGGB10_1X10: 720 case MEDIA_BUS_FMT_SGRBG10_1X10: 721 case MEDIA_BUS_FMT_SGBRG10_1X10: 722 case MEDIA_BUS_FMT_SBGGR10_1X10: 723 return cci_multi_reg_write(imx219->regmap, raw10_framefmt_regs, 724 ARRAY_SIZE(raw10_framefmt_regs), NULL); 725 } 726 727 return -EINVAL; 728 } 729 730 static int imx219_set_binning(struct imx219 *imx219, 731 const struct v4l2_mbus_framefmt *format) 732 { 733 if (!imx219->mode->binning) 734 return cci_write(imx219->regmap, IMX219_REG_BINNING_MODE, 735 IMX219_BINNING_NONE, NULL); 736 737 switch (format->code) { 738 case MEDIA_BUS_FMT_SRGGB8_1X8: 739 case MEDIA_BUS_FMT_SGRBG8_1X8: 740 case MEDIA_BUS_FMT_SGBRG8_1X8: 741 case MEDIA_BUS_FMT_SBGGR8_1X8: 742 return cci_write(imx219->regmap, IMX219_REG_BINNING_MODE, 743 IMX219_BINNING_2X2_ANALOG, NULL); 744 745 case MEDIA_BUS_FMT_SRGGB10_1X10: 746 case MEDIA_BUS_FMT_SGRBG10_1X10: 747 case MEDIA_BUS_FMT_SGBRG10_1X10: 748 case MEDIA_BUS_FMT_SBGGR10_1X10: 749 return cci_write(imx219->regmap, IMX219_REG_BINNING_MODE, 750 IMX219_BINNING_2X2, NULL); 751 } 752 753 return -EINVAL; 754 } 755 756 static int imx219_get_selection(struct v4l2_subdev *sd, 757 struct v4l2_subdev_state *sd_state, 758 struct v4l2_subdev_selection *sel) 759 { 760 switch (sel->target) { 761 case V4L2_SEL_TGT_CROP: { 762 sel->r = *v4l2_subdev_get_pad_crop(sd, sd_state, 0); 763 return 0; 764 } 765 766 case V4L2_SEL_TGT_NATIVE_SIZE: 767 sel->r.top = 0; 768 sel->r.left = 0; 769 sel->r.width = IMX219_NATIVE_WIDTH; 770 sel->r.height = IMX219_NATIVE_HEIGHT; 771 772 return 0; 773 774 case V4L2_SEL_TGT_CROP_DEFAULT: 775 case V4L2_SEL_TGT_CROP_BOUNDS: 776 sel->r.top = IMX219_PIXEL_ARRAY_TOP; 777 sel->r.left = IMX219_PIXEL_ARRAY_LEFT; 778 sel->r.width = IMX219_PIXEL_ARRAY_WIDTH; 779 sel->r.height = IMX219_PIXEL_ARRAY_HEIGHT; 780 781 return 0; 782 } 783 784 return -EINVAL; 785 } 786 787 static int imx219_configure_lanes(struct imx219 *imx219) 788 { 789 return cci_write(imx219->regmap, IMX219_REG_CSI_LANE_MODE, 790 imx219->lanes == 2 ? IMX219_CSI_2_LANE_MODE : 791 IMX219_CSI_4_LANE_MODE, NULL); 792 }; 793 794 static int imx219_start_streaming(struct imx219 *imx219, 795 struct v4l2_subdev_state *state) 796 { 797 struct i2c_client *client = v4l2_get_subdevdata(&imx219->sd); 798 const struct v4l2_mbus_framefmt *format; 799 const struct imx219_reg_list *reg_list; 800 int ret; 801 802 ret = pm_runtime_resume_and_get(&client->dev); 803 if (ret < 0) 804 return ret; 805 806 /* Send all registers that are common to all modes */ 807 ret = cci_multi_reg_write(imx219->regmap, imx219_common_regs, 808 ARRAY_SIZE(imx219_common_regs), NULL); 809 if (ret) { 810 dev_err(&client->dev, "%s failed to send mfg header\n", __func__); 811 goto err_rpm_put; 812 } 813 814 /* Configure two or four Lane mode */ 815 ret = imx219_configure_lanes(imx219); 816 if (ret) { 817 dev_err(&client->dev, "%s failed to configure lanes\n", __func__); 818 goto err_rpm_put; 819 } 820 821 /* Apply default values of current mode */ 822 reg_list = &imx219->mode->reg_list; 823 ret = cci_multi_reg_write(imx219->regmap, reg_list->regs, 824 reg_list->num_of_regs, NULL); 825 if (ret) { 826 dev_err(&client->dev, "%s failed to set mode\n", __func__); 827 goto err_rpm_put; 828 } 829 830 format = v4l2_subdev_get_pad_format(&imx219->sd, state, 0); 831 ret = imx219_set_framefmt(imx219, format); 832 if (ret) { 833 dev_err(&client->dev, "%s failed to set frame format: %d\n", 834 __func__, ret); 835 goto err_rpm_put; 836 } 837 838 ret = imx219_set_binning(imx219, format); 839 if (ret) { 840 dev_err(&client->dev, "%s failed to set binning: %d\n", 841 __func__, ret); 842 goto err_rpm_put; 843 } 844 845 /* Apply customized values from user */ 846 ret = __v4l2_ctrl_handler_setup(imx219->sd.ctrl_handler); 847 if (ret) 848 goto err_rpm_put; 849 850 /* set stream on register */ 851 ret = cci_write(imx219->regmap, IMX219_REG_MODE_SELECT, 852 IMX219_MODE_STREAMING, NULL); 853 if (ret) 854 goto err_rpm_put; 855 856 /* vflip and hflip cannot change during streaming */ 857 __v4l2_ctrl_grab(imx219->vflip, true); 858 __v4l2_ctrl_grab(imx219->hflip, true); 859 860 return 0; 861 862 err_rpm_put: 863 pm_runtime_put(&client->dev); 864 return ret; 865 } 866 867 static void imx219_stop_streaming(struct imx219 *imx219) 868 { 869 struct i2c_client *client = v4l2_get_subdevdata(&imx219->sd); 870 int ret; 871 872 /* set stream off register */ 873 ret = cci_write(imx219->regmap, IMX219_REG_MODE_SELECT, 874 IMX219_MODE_STANDBY, NULL); 875 if (ret) 876 dev_err(&client->dev, "%s failed to set stream\n", __func__); 877 878 __v4l2_ctrl_grab(imx219->vflip, false); 879 __v4l2_ctrl_grab(imx219->hflip, false); 880 881 pm_runtime_put(&client->dev); 882 } 883 884 static int imx219_set_stream(struct v4l2_subdev *sd, int enable) 885 { 886 struct imx219 *imx219 = to_imx219(sd); 887 struct v4l2_subdev_state *state; 888 int ret = 0; 889 890 state = v4l2_subdev_lock_and_get_active_state(sd); 891 892 if (imx219->streaming == enable) 893 goto unlock; 894 895 if (enable) { 896 /* 897 * Apply default & customized values 898 * and then start streaming. 899 */ 900 ret = imx219_start_streaming(imx219, state); 901 if (ret) 902 goto unlock; 903 } else { 904 imx219_stop_streaming(imx219); 905 } 906 907 imx219->streaming = enable; 908 909 unlock: 910 v4l2_subdev_unlock_state(state); 911 return ret; 912 } 913 914 /* Power/clock management functions */ 915 static int imx219_power_on(struct device *dev) 916 { 917 struct v4l2_subdev *sd = dev_get_drvdata(dev); 918 struct imx219 *imx219 = to_imx219(sd); 919 int ret; 920 921 ret = regulator_bulk_enable(IMX219_NUM_SUPPLIES, 922 imx219->supplies); 923 if (ret) { 924 dev_err(dev, "%s: failed to enable regulators\n", 925 __func__); 926 return ret; 927 } 928 929 ret = clk_prepare_enable(imx219->xclk); 930 if (ret) { 931 dev_err(dev, "%s: failed to enable clock\n", 932 __func__); 933 goto reg_off; 934 } 935 936 gpiod_set_value_cansleep(imx219->reset_gpio, 1); 937 usleep_range(IMX219_XCLR_MIN_DELAY_US, 938 IMX219_XCLR_MIN_DELAY_US + IMX219_XCLR_DELAY_RANGE_US); 939 940 return 0; 941 942 reg_off: 943 regulator_bulk_disable(IMX219_NUM_SUPPLIES, imx219->supplies); 944 945 return ret; 946 } 947 948 static int imx219_power_off(struct device *dev) 949 { 950 struct v4l2_subdev *sd = dev_get_drvdata(dev); 951 struct imx219 *imx219 = to_imx219(sd); 952 953 gpiod_set_value_cansleep(imx219->reset_gpio, 0); 954 regulator_bulk_disable(IMX219_NUM_SUPPLIES, imx219->supplies); 955 clk_disable_unprepare(imx219->xclk); 956 957 return 0; 958 } 959 960 static int __maybe_unused imx219_suspend(struct device *dev) 961 { 962 struct v4l2_subdev *sd = dev_get_drvdata(dev); 963 struct imx219 *imx219 = to_imx219(sd); 964 965 if (imx219->streaming) 966 imx219_stop_streaming(imx219); 967 968 return 0; 969 } 970 971 static int __maybe_unused imx219_resume(struct device *dev) 972 { 973 struct v4l2_subdev *sd = dev_get_drvdata(dev); 974 struct imx219 *imx219 = to_imx219(sd); 975 struct v4l2_subdev_state *state; 976 int ret; 977 978 if (imx219->streaming) { 979 state = v4l2_subdev_lock_and_get_active_state(sd); 980 ret = imx219_start_streaming(imx219, state); 981 v4l2_subdev_unlock_state(state); 982 if (ret) 983 goto error; 984 } 985 986 return 0; 987 988 error: 989 imx219_stop_streaming(imx219); 990 imx219->streaming = false; 991 992 return ret; 993 } 994 995 static int imx219_get_regulators(struct imx219 *imx219) 996 { 997 struct i2c_client *client = v4l2_get_subdevdata(&imx219->sd); 998 unsigned int i; 999 1000 for (i = 0; i < IMX219_NUM_SUPPLIES; i++) 1001 imx219->supplies[i].supply = imx219_supply_name[i]; 1002 1003 return devm_regulator_bulk_get(&client->dev, 1004 IMX219_NUM_SUPPLIES, 1005 imx219->supplies); 1006 } 1007 1008 /* Verify chip ID */ 1009 static int imx219_identify_module(struct imx219 *imx219) 1010 { 1011 struct i2c_client *client = v4l2_get_subdevdata(&imx219->sd); 1012 int ret; 1013 u64 val; 1014 1015 ret = cci_read(imx219->regmap, IMX219_REG_CHIP_ID, &val, NULL); 1016 if (ret) { 1017 dev_err(&client->dev, "failed to read chip id %x\n", 1018 IMX219_CHIP_ID); 1019 return ret; 1020 } 1021 1022 if (val != IMX219_CHIP_ID) { 1023 dev_err(&client->dev, "chip id mismatch: %x!=%llx\n", 1024 IMX219_CHIP_ID, val); 1025 return -EIO; 1026 } 1027 1028 return 0; 1029 } 1030 1031 static const struct v4l2_subdev_core_ops imx219_core_ops = { 1032 .subscribe_event = v4l2_ctrl_subdev_subscribe_event, 1033 .unsubscribe_event = v4l2_event_subdev_unsubscribe, 1034 }; 1035 1036 static const struct v4l2_subdev_video_ops imx219_video_ops = { 1037 .s_stream = imx219_set_stream, 1038 }; 1039 1040 static const struct v4l2_subdev_pad_ops imx219_pad_ops = { 1041 .init_cfg = imx219_init_cfg, 1042 .enum_mbus_code = imx219_enum_mbus_code, 1043 .get_fmt = v4l2_subdev_get_fmt, 1044 .set_fmt = imx219_set_pad_format, 1045 .get_selection = imx219_get_selection, 1046 .enum_frame_size = imx219_enum_frame_size, 1047 }; 1048 1049 static const struct v4l2_subdev_ops imx219_subdev_ops = { 1050 .core = &imx219_core_ops, 1051 .video = &imx219_video_ops, 1052 .pad = &imx219_pad_ops, 1053 }; 1054 1055 1056 static unsigned long imx219_get_pixel_rate(struct imx219 *imx219) 1057 { 1058 return (imx219->lanes == 2) ? IMX219_PIXEL_RATE : IMX219_PIXEL_RATE_4LANE; 1059 } 1060 1061 /* Initialize control handlers */ 1062 static int imx219_init_controls(struct imx219 *imx219) 1063 { 1064 struct i2c_client *client = v4l2_get_subdevdata(&imx219->sd); 1065 struct v4l2_ctrl_handler *ctrl_hdlr; 1066 unsigned int height = imx219->mode->height; 1067 struct v4l2_fwnode_device_properties props; 1068 int exposure_max, exposure_def, hblank; 1069 int i, ret; 1070 1071 ctrl_hdlr = &imx219->ctrl_handler; 1072 ret = v4l2_ctrl_handler_init(ctrl_hdlr, 12); 1073 if (ret) 1074 return ret; 1075 1076 /* By default, PIXEL_RATE is read only */ 1077 imx219->pixel_rate = v4l2_ctrl_new_std(ctrl_hdlr, &imx219_ctrl_ops, 1078 V4L2_CID_PIXEL_RATE, 1079 imx219_get_pixel_rate(imx219), 1080 imx219_get_pixel_rate(imx219), 1, 1081 imx219_get_pixel_rate(imx219)); 1082 1083 imx219->link_freq = 1084 v4l2_ctrl_new_int_menu(ctrl_hdlr, &imx219_ctrl_ops, 1085 V4L2_CID_LINK_FREQ, 1086 ARRAY_SIZE(imx219_link_freq_menu) - 1, 0, 1087 (imx219->lanes == 2) ? imx219_link_freq_menu : 1088 imx219_link_freq_4lane_menu); 1089 if (imx219->link_freq) 1090 imx219->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY; 1091 1092 /* Initial vblank/hblank/exposure parameters based on current mode */ 1093 imx219->vblank = v4l2_ctrl_new_std(ctrl_hdlr, &imx219_ctrl_ops, 1094 V4L2_CID_VBLANK, IMX219_VBLANK_MIN, 1095 IMX219_VTS_MAX - height, 1, 1096 imx219->mode->vts_def - height); 1097 hblank = IMX219_PPL_DEFAULT - imx219->mode->width; 1098 imx219->hblank = v4l2_ctrl_new_std(ctrl_hdlr, &imx219_ctrl_ops, 1099 V4L2_CID_HBLANK, hblank, hblank, 1100 1, hblank); 1101 if (imx219->hblank) 1102 imx219->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY; 1103 exposure_max = imx219->mode->vts_def - 4; 1104 exposure_def = (exposure_max < IMX219_EXPOSURE_DEFAULT) ? 1105 exposure_max : IMX219_EXPOSURE_DEFAULT; 1106 imx219->exposure = v4l2_ctrl_new_std(ctrl_hdlr, &imx219_ctrl_ops, 1107 V4L2_CID_EXPOSURE, 1108 IMX219_EXPOSURE_MIN, exposure_max, 1109 IMX219_EXPOSURE_STEP, 1110 exposure_def); 1111 1112 v4l2_ctrl_new_std(ctrl_hdlr, &imx219_ctrl_ops, V4L2_CID_ANALOGUE_GAIN, 1113 IMX219_ANA_GAIN_MIN, IMX219_ANA_GAIN_MAX, 1114 IMX219_ANA_GAIN_STEP, IMX219_ANA_GAIN_DEFAULT); 1115 1116 v4l2_ctrl_new_std(ctrl_hdlr, &imx219_ctrl_ops, V4L2_CID_DIGITAL_GAIN, 1117 IMX219_DGTL_GAIN_MIN, IMX219_DGTL_GAIN_MAX, 1118 IMX219_DGTL_GAIN_STEP, IMX219_DGTL_GAIN_DEFAULT); 1119 1120 imx219->hflip = v4l2_ctrl_new_std(ctrl_hdlr, &imx219_ctrl_ops, 1121 V4L2_CID_HFLIP, 0, 1, 1, 0); 1122 if (imx219->hflip) 1123 imx219->hflip->flags |= V4L2_CTRL_FLAG_MODIFY_LAYOUT; 1124 1125 imx219->vflip = v4l2_ctrl_new_std(ctrl_hdlr, &imx219_ctrl_ops, 1126 V4L2_CID_VFLIP, 0, 1, 1, 0); 1127 if (imx219->vflip) 1128 imx219->vflip->flags |= V4L2_CTRL_FLAG_MODIFY_LAYOUT; 1129 1130 v4l2_ctrl_new_std_menu_items(ctrl_hdlr, &imx219_ctrl_ops, 1131 V4L2_CID_TEST_PATTERN, 1132 ARRAY_SIZE(imx219_test_pattern_menu) - 1, 1133 0, 0, imx219_test_pattern_menu); 1134 for (i = 0; i < 4; i++) { 1135 /* 1136 * The assumption is that 1137 * V4L2_CID_TEST_PATTERN_GREENR == V4L2_CID_TEST_PATTERN_RED + 1 1138 * V4L2_CID_TEST_PATTERN_BLUE == V4L2_CID_TEST_PATTERN_RED + 2 1139 * V4L2_CID_TEST_PATTERN_GREENB == V4L2_CID_TEST_PATTERN_RED + 3 1140 */ 1141 v4l2_ctrl_new_std(ctrl_hdlr, &imx219_ctrl_ops, 1142 V4L2_CID_TEST_PATTERN_RED + i, 1143 IMX219_TESTP_COLOUR_MIN, 1144 IMX219_TESTP_COLOUR_MAX, 1145 IMX219_TESTP_COLOUR_STEP, 1146 IMX219_TESTP_COLOUR_MAX); 1147 /* The "Solid color" pattern is white by default */ 1148 } 1149 1150 if (ctrl_hdlr->error) { 1151 ret = ctrl_hdlr->error; 1152 dev_err(&client->dev, "%s control init failed (%d)\n", 1153 __func__, ret); 1154 goto error; 1155 } 1156 1157 ret = v4l2_fwnode_device_parse(&client->dev, &props); 1158 if (ret) 1159 goto error; 1160 1161 ret = v4l2_ctrl_new_fwnode_properties(ctrl_hdlr, &imx219_ctrl_ops, 1162 &props); 1163 if (ret) 1164 goto error; 1165 1166 imx219->sd.ctrl_handler = ctrl_hdlr; 1167 1168 return 0; 1169 1170 error: 1171 v4l2_ctrl_handler_free(ctrl_hdlr); 1172 1173 return ret; 1174 } 1175 1176 static void imx219_free_controls(struct imx219 *imx219) 1177 { 1178 v4l2_ctrl_handler_free(imx219->sd.ctrl_handler); 1179 } 1180 1181 static int imx219_check_hwcfg(struct device *dev, struct imx219 *imx219) 1182 { 1183 struct fwnode_handle *endpoint; 1184 struct v4l2_fwnode_endpoint ep_cfg = { 1185 .bus_type = V4L2_MBUS_CSI2_DPHY 1186 }; 1187 int ret = -EINVAL; 1188 1189 endpoint = fwnode_graph_get_next_endpoint(dev_fwnode(dev), NULL); 1190 if (!endpoint) { 1191 dev_err(dev, "endpoint node not found\n"); 1192 return -EINVAL; 1193 } 1194 1195 if (v4l2_fwnode_endpoint_alloc_parse(endpoint, &ep_cfg)) { 1196 dev_err(dev, "could not parse endpoint\n"); 1197 goto error_out; 1198 } 1199 1200 /* Check the number of MIPI CSI2 data lanes */ 1201 if (ep_cfg.bus.mipi_csi2.num_data_lanes != 2 && 1202 ep_cfg.bus.mipi_csi2.num_data_lanes != 4) { 1203 dev_err(dev, "only 2 or 4 data lanes are currently supported\n"); 1204 goto error_out; 1205 } 1206 imx219->lanes = ep_cfg.bus.mipi_csi2.num_data_lanes; 1207 1208 /* Check the link frequency set in device tree */ 1209 if (!ep_cfg.nr_of_link_frequencies) { 1210 dev_err(dev, "link-frequency property not found in DT\n"); 1211 goto error_out; 1212 } 1213 1214 if (ep_cfg.nr_of_link_frequencies != 1 || 1215 (ep_cfg.link_frequencies[0] != ((imx219->lanes == 2) ? 1216 IMX219_DEFAULT_LINK_FREQ : IMX219_DEFAULT_LINK_FREQ_4LANE))) { 1217 dev_err(dev, "Link frequency not supported: %lld\n", 1218 ep_cfg.link_frequencies[0]); 1219 goto error_out; 1220 } 1221 1222 ret = 0; 1223 1224 error_out: 1225 v4l2_fwnode_endpoint_free(&ep_cfg); 1226 fwnode_handle_put(endpoint); 1227 1228 return ret; 1229 } 1230 1231 static int imx219_probe(struct i2c_client *client) 1232 { 1233 struct device *dev = &client->dev; 1234 struct imx219 *imx219; 1235 int ret; 1236 1237 imx219 = devm_kzalloc(&client->dev, sizeof(*imx219), GFP_KERNEL); 1238 if (!imx219) 1239 return -ENOMEM; 1240 1241 v4l2_i2c_subdev_init(&imx219->sd, client, &imx219_subdev_ops); 1242 1243 /* Check the hardware configuration in device tree */ 1244 if (imx219_check_hwcfg(dev, imx219)) 1245 return -EINVAL; 1246 1247 imx219->regmap = devm_cci_regmap_init_i2c(client, 16); 1248 if (IS_ERR(imx219->regmap)) { 1249 ret = PTR_ERR(imx219->regmap); 1250 dev_err(dev, "failed to initialize CCI: %d\n", ret); 1251 return ret; 1252 } 1253 1254 /* Get system clock (xclk) */ 1255 imx219->xclk = devm_clk_get(dev, NULL); 1256 if (IS_ERR(imx219->xclk)) { 1257 dev_err(dev, "failed to get xclk\n"); 1258 return PTR_ERR(imx219->xclk); 1259 } 1260 1261 imx219->xclk_freq = clk_get_rate(imx219->xclk); 1262 if (imx219->xclk_freq != IMX219_XCLK_FREQ) { 1263 dev_err(dev, "xclk frequency not supported: %d Hz\n", 1264 imx219->xclk_freq); 1265 return -EINVAL; 1266 } 1267 1268 ret = imx219_get_regulators(imx219); 1269 if (ret) { 1270 dev_err(dev, "failed to get regulators\n"); 1271 return ret; 1272 } 1273 1274 /* Request optional enable pin */ 1275 imx219->reset_gpio = devm_gpiod_get_optional(dev, "reset", 1276 GPIOD_OUT_HIGH); 1277 1278 /* 1279 * The sensor must be powered for imx219_identify_module() 1280 * to be able to read the CHIP_ID register 1281 */ 1282 ret = imx219_power_on(dev); 1283 if (ret) 1284 return ret; 1285 1286 ret = imx219_identify_module(imx219); 1287 if (ret) 1288 goto error_power_off; 1289 1290 /* Set default mode to max resolution */ 1291 imx219->mode = &supported_modes[0]; 1292 1293 /* sensor doesn't enter LP-11 state upon power up until and unless 1294 * streaming is started, so upon power up switch the modes to: 1295 * streaming -> standby 1296 */ 1297 ret = cci_write(imx219->regmap, IMX219_REG_MODE_SELECT, 1298 IMX219_MODE_STREAMING, NULL); 1299 if (ret < 0) 1300 goto error_power_off; 1301 1302 usleep_range(100, 110); 1303 1304 /* put sensor back to standby mode */ 1305 ret = cci_write(imx219->regmap, IMX219_REG_MODE_SELECT, 1306 IMX219_MODE_STANDBY, NULL); 1307 if (ret < 0) 1308 goto error_power_off; 1309 1310 usleep_range(100, 110); 1311 1312 ret = imx219_init_controls(imx219); 1313 if (ret) 1314 goto error_power_off; 1315 1316 /* Initialize subdev */ 1317 imx219->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | 1318 V4L2_SUBDEV_FL_HAS_EVENTS; 1319 imx219->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR; 1320 1321 /* Initialize source pad */ 1322 imx219->pad.flags = MEDIA_PAD_FL_SOURCE; 1323 1324 ret = media_entity_pads_init(&imx219->sd.entity, 1, &imx219->pad); 1325 if (ret) { 1326 dev_err(dev, "failed to init entity pads: %d\n", ret); 1327 goto error_handler_free; 1328 } 1329 1330 imx219->sd.state_lock = imx219->ctrl_handler.lock; 1331 ret = v4l2_subdev_init_finalize(&imx219->sd); 1332 if (ret < 0) { 1333 dev_err(dev, "subdev init error: %d\n", ret); 1334 goto error_media_entity; 1335 } 1336 1337 ret = v4l2_async_register_subdev_sensor(&imx219->sd); 1338 if (ret < 0) { 1339 dev_err(dev, "failed to register sensor sub-device: %d\n", ret); 1340 goto error_subdev_cleanup; 1341 } 1342 1343 /* Enable runtime PM and turn off the device */ 1344 pm_runtime_set_active(dev); 1345 pm_runtime_enable(dev); 1346 pm_runtime_idle(dev); 1347 1348 return 0; 1349 1350 error_subdev_cleanup: 1351 v4l2_subdev_cleanup(&imx219->sd); 1352 1353 error_media_entity: 1354 media_entity_cleanup(&imx219->sd.entity); 1355 1356 error_handler_free: 1357 imx219_free_controls(imx219); 1358 1359 error_power_off: 1360 imx219_power_off(dev); 1361 1362 return ret; 1363 } 1364 1365 static void imx219_remove(struct i2c_client *client) 1366 { 1367 struct v4l2_subdev *sd = i2c_get_clientdata(client); 1368 struct imx219 *imx219 = to_imx219(sd); 1369 1370 v4l2_async_unregister_subdev(sd); 1371 v4l2_subdev_cleanup(sd); 1372 media_entity_cleanup(&sd->entity); 1373 imx219_free_controls(imx219); 1374 1375 pm_runtime_disable(&client->dev); 1376 if (!pm_runtime_status_suspended(&client->dev)) 1377 imx219_power_off(&client->dev); 1378 pm_runtime_set_suspended(&client->dev); 1379 } 1380 1381 static const struct of_device_id imx219_dt_ids[] = { 1382 { .compatible = "sony,imx219" }, 1383 { /* sentinel */ } 1384 }; 1385 MODULE_DEVICE_TABLE(of, imx219_dt_ids); 1386 1387 static const struct dev_pm_ops imx219_pm_ops = { 1388 SET_SYSTEM_SLEEP_PM_OPS(imx219_suspend, imx219_resume) 1389 SET_RUNTIME_PM_OPS(imx219_power_off, imx219_power_on, NULL) 1390 }; 1391 1392 static struct i2c_driver imx219_i2c_driver = { 1393 .driver = { 1394 .name = "imx219", 1395 .of_match_table = imx219_dt_ids, 1396 .pm = &imx219_pm_ops, 1397 }, 1398 .probe = imx219_probe, 1399 .remove = imx219_remove, 1400 }; 1401 1402 module_i2c_driver(imx219_i2c_driver); 1403 1404 MODULE_AUTHOR("Dave Stevenson <dave.stevenson@raspberrypi.com"); 1405 MODULE_DESCRIPTION("Sony IMX219 sensor driver"); 1406 MODULE_LICENSE("GPL v2"); 1407