11802d0beSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 2c5254e72SPavel Machek /* 3c5254e72SPavel Machek * et8ek8_reg.h 4c5254e72SPavel Machek * 5c5254e72SPavel Machek * Copyright (C) 2008 Nokia Corporation 6c5254e72SPavel Machek * 7c5254e72SPavel Machek * Contact: Sakari Ailus <sakari.ailus@iki.fi> 8c5254e72SPavel Machek * Tuukka Toivonen <tuukkat76@gmail.com> 9c5254e72SPavel Machek */ 10c5254e72SPavel Machek 11c5254e72SPavel Machek #ifndef ET8EK8REGS_H 12c5254e72SPavel Machek #define ET8EK8REGS_H 13c5254e72SPavel Machek 14c5254e72SPavel Machek #include <linux/i2c.h> 15c5254e72SPavel Machek #include <linux/types.h> 16c5254e72SPavel Machek #include <linux/videodev2.h> 17c5254e72SPavel Machek #include <linux/v4l2-subdev.h> 18c5254e72SPavel Machek 19c5254e72SPavel Machek struct v4l2_mbus_framefmt; 20c5254e72SPavel Machek struct v4l2_subdev_pad_mbus_code_enum; 21c5254e72SPavel Machek 22c5254e72SPavel Machek struct et8ek8_mode { 23c5254e72SPavel Machek /* Physical sensor resolution and current image window */ 24c5254e72SPavel Machek u16 sensor_width; 25c5254e72SPavel Machek u16 sensor_height; 26c5254e72SPavel Machek u16 sensor_window_origin_x; 27c5254e72SPavel Machek u16 sensor_window_origin_y; 28c5254e72SPavel Machek u16 sensor_window_width; 29c5254e72SPavel Machek u16 sensor_window_height; 30c5254e72SPavel Machek 31c5254e72SPavel Machek /* Image data coming from sensor (after scaling) */ 32c5254e72SPavel Machek u16 width; 33c5254e72SPavel Machek u16 height; 34c5254e72SPavel Machek u16 window_origin_x; 35c5254e72SPavel Machek u16 window_origin_y; 36c5254e72SPavel Machek u16 window_width; 37c5254e72SPavel Machek u16 window_height; 38c5254e72SPavel Machek 39c5254e72SPavel Machek u32 pixel_clock; /* in Hz */ 40c5254e72SPavel Machek u32 ext_clock; /* in Hz */ 41c5254e72SPavel Machek struct v4l2_fract timeperframe; 42c5254e72SPavel Machek u32 max_exp; /* Maximum exposure value */ 43c5254e72SPavel Machek u32 bus_format; /* MEDIA_BUS_FMT_ */ 44c5254e72SPavel Machek u32 sensitivity; /* 16.16 fixed point */ 45c5254e72SPavel Machek }; 46c5254e72SPavel Machek 47c5254e72SPavel Machek #define ET8EK8_REG_8BIT 1 48c5254e72SPavel Machek #define ET8EK8_REG_16BIT 2 49c5254e72SPavel Machek #define ET8EK8_REG_DELAY 100 50c5254e72SPavel Machek #define ET8EK8_REG_TERM 0xff 51c5254e72SPavel Machek struct et8ek8_reg { 52c5254e72SPavel Machek u16 type; 53c5254e72SPavel Machek u16 reg; /* 16-bit offset */ 54c5254e72SPavel Machek u32 val; /* 8/16/32-bit value */ 55c5254e72SPavel Machek }; 56c5254e72SPavel Machek 57c5254e72SPavel Machek /* Possible struct smia_reglist types. */ 58c5254e72SPavel Machek #define ET8EK8_REGLIST_STANDBY 0 59c5254e72SPavel Machek #define ET8EK8_REGLIST_POWERON 1 60c5254e72SPavel Machek #define ET8EK8_REGLIST_RESUME 2 61c5254e72SPavel Machek #define ET8EK8_REGLIST_STREAMON 3 62c5254e72SPavel Machek #define ET8EK8_REGLIST_STREAMOFF 4 63c5254e72SPavel Machek #define ET8EK8_REGLIST_DISABLED 5 64c5254e72SPavel Machek 65c5254e72SPavel Machek #define ET8EK8_REGLIST_MODE 10 66c5254e72SPavel Machek 67c5254e72SPavel Machek #define ET8EK8_REGLIST_LSC_ENABLE 100 68c5254e72SPavel Machek #define ET8EK8_REGLIST_LSC_DISABLE 101 69c5254e72SPavel Machek #define ET8EK8_REGLIST_ANR_ENABLE 102 70c5254e72SPavel Machek #define ET8EK8_REGLIST_ANR_DISABLE 103 71c5254e72SPavel Machek 72c5254e72SPavel Machek struct et8ek8_reglist { 73c5254e72SPavel Machek u32 type; 74c5254e72SPavel Machek struct et8ek8_mode mode; 75c5254e72SPavel Machek struct et8ek8_reg regs[]; 76c5254e72SPavel Machek }; 77c5254e72SPavel Machek 78c5254e72SPavel Machek #define ET8EK8_MAX_LEN 32 79c5254e72SPavel Machek struct et8ek8_meta_reglist { 80c5254e72SPavel Machek char version[ET8EK8_MAX_LEN]; 81c5254e72SPavel Machek union { 82c5254e72SPavel Machek struct et8ek8_reglist *ptr; 83c5254e72SPavel Machek } reglist[]; 84c5254e72SPavel Machek }; 85c5254e72SPavel Machek 86c5254e72SPavel Machek extern struct et8ek8_meta_reglist meta_reglist; 87c5254e72SPavel Machek 88c5254e72SPavel Machek #endif /* ET8EK8REGS */ 89