1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * et8ek8_mode.c
4  *
5  * Copyright (C) 2008 Nokia Corporation
6  *
7  * Contact: Sakari Ailus <sakari.ailus@iki.fi>
8  *          Tuukka Toivonen <tuukkat76@gmail.com>
9  */
10 
11 #include "et8ek8_reg.h"
12 
13 /*
14  * Stingray sensor mode settings for Scooby
15  */
16 
17 /* Mode1_poweron_Mode2_16VGA_2592x1968_12.07fps */
18 static struct et8ek8_reglist mode1_poweron_mode2_16vga_2592x1968_12_07fps = {
19 /* (without the +1)
20  * SPCK       = 80 MHz
21  * CCP2       = 640 MHz
22  * VCO        = 640 MHz
23  * VCOUNT     = 84 (2016)
24  * HCOUNT     = 137 (3288)
25  * CKREF_DIV  = 2
26  * CKVAR_DIV  = 200
27  * VCO_DIV    = 0
28  * SPCK_DIV   = 7
29  * MRCK_DIV   = 7
30  * LVDSCK_DIV = 0
31  */
32 	.type = ET8EK8_REGLIST_POWERON,
33 	.mode = {
34 		.sensor_width = 2592,
35 		.sensor_height = 1968,
36 		.sensor_window_origin_x = 0,
37 		.sensor_window_origin_y = 0,
38 		.sensor_window_width = 2592,
39 		.sensor_window_height = 1968,
40 		.width = 3288,
41 		.height = 2016,
42 		.window_origin_x = 0,
43 		.window_origin_y = 0,
44 		.window_width = 2592,
45 		.window_height = 1968,
46 		.pixel_clock = 80000000,
47 		.ext_clock = 9600000,
48 		.timeperframe = {
49 			.numerator = 100,
50 			.denominator = 1207
51 		},
52 		.max_exp = 2012,
53 		/* .max_gain = 0, */
54 		.bus_format = MEDIA_BUS_FMT_SGRBG10_1X10,
55 		.sensitivity = 65536
56 	},
57 	.regs = {
58 		/* Need to set firstly */
59 		{ ET8EK8_REG_8BIT, 0x126C, 0xCC },
60 		/* Strobe and Data of CCP2 delay are minimized. */
61 		{ ET8EK8_REG_8BIT, 0x1269, 0x00 },
62 		/* Refined value of Min H_COUNT  */
63 		{ ET8EK8_REG_8BIT, 0x1220, 0x89 },
64 		/* Frequency of SPCK setting (SPCK=MRCK) */
65 		{ ET8EK8_REG_8BIT, 0x123A, 0x07 },
66 		{ ET8EK8_REG_8BIT, 0x1241, 0x94 },
67 		{ ET8EK8_REG_8BIT, 0x1242, 0x02 },
68 		{ ET8EK8_REG_8BIT, 0x124B, 0x00 },
69 		{ ET8EK8_REG_8BIT, 0x1255, 0xFF },
70 		{ ET8EK8_REG_8BIT, 0x1256, 0x9F },
71 		{ ET8EK8_REG_8BIT, 0x1258, 0x00 },
72 		/* From parallel out to serial out */
73 		{ ET8EK8_REG_8BIT, 0x125D, 0x88 },
74 		/* From w/ embedded data to w/o embedded data */
75 		{ ET8EK8_REG_8BIT, 0x125E, 0xC0 },
76 		/* CCP2 out is from STOP to ACTIVE */
77 		{ ET8EK8_REG_8BIT, 0x1263, 0x98 },
78 		{ ET8EK8_REG_8BIT, 0x1268, 0xC6 },
79 		{ ET8EK8_REG_8BIT, 0x1434, 0x00 },
80 		{ ET8EK8_REG_8BIT, 0x1163, 0x44 },
81 		{ ET8EK8_REG_8BIT, 0x1166, 0x29 },
82 		{ ET8EK8_REG_8BIT, 0x1140, 0x02 },
83 		{ ET8EK8_REG_8BIT, 0x1011, 0x24 },
84 		{ ET8EK8_REG_8BIT, 0x1151, 0x80 },
85 		{ ET8EK8_REG_8BIT, 0x1152, 0x23 },
86 		/* Initial setting for improvement2 of lower frequency noise */
87 		{ ET8EK8_REG_8BIT, 0x1014, 0x05 },
88 		{ ET8EK8_REG_8BIT, 0x1033, 0x06 },
89 		{ ET8EK8_REG_8BIT, 0x1034, 0x79 },
90 		{ ET8EK8_REG_8BIT, 0x1423, 0x3F },
91 		{ ET8EK8_REG_8BIT, 0x1424, 0x3F },
92 		{ ET8EK8_REG_8BIT, 0x1426, 0x00 },
93 		/* Switch of Preset-White-balance (0d:disable / 1d:enable) */
94 		{ ET8EK8_REG_8BIT, 0x1439, 0x00 },
95 		/* Switch of blemish correction (0d:disable / 1d:enable) */
96 		{ ET8EK8_REG_8BIT, 0x161F, 0x60 },
97 		/* Switch of auto noise correction (0d:disable / 1d:enable) */
98 		{ ET8EK8_REG_8BIT, 0x1634, 0x00 },
99 		{ ET8EK8_REG_8BIT, 0x1646, 0x00 },
100 		{ ET8EK8_REG_8BIT, 0x1648, 0x00 },
101 		{ ET8EK8_REG_8BIT, 0x113E, 0x01 },
102 		{ ET8EK8_REG_8BIT, 0x113F, 0x22 },
103 		{ ET8EK8_REG_8BIT, 0x1239, 0x64 },
104 		{ ET8EK8_REG_8BIT, 0x1238, 0x02 },
105 		{ ET8EK8_REG_8BIT, 0x123B, 0x70 },
106 		{ ET8EK8_REG_8BIT, 0x123A, 0x07 },
107 		{ ET8EK8_REG_8BIT, 0x121B, 0x64 },
108 		{ ET8EK8_REG_8BIT, 0x121D, 0x64 },
109 		{ ET8EK8_REG_8BIT, 0x1221, 0x00 },
110 		{ ET8EK8_REG_8BIT, 0x1220, 0x89 },
111 		{ ET8EK8_REG_8BIT, 0x1223, 0x00 },
112 		{ ET8EK8_REG_8BIT, 0x1222, 0x54 },
113 		{ ET8EK8_REG_8BIT, 0x125D, 0x88 }, /* CCP_LVDS_MODE/  */
114 		{ ET8EK8_REG_TERM, 0, 0}
115 	}
116 };
117 
118 /* Mode1_16VGA_2592x1968_13.12fps_DPCM10-8 */
119 static struct et8ek8_reglist mode1_16vga_2592x1968_13_12fps_dpcm10_8 = {
120 /* (without the +1)
121  * SPCK       = 80 MHz
122  * CCP2       = 560 MHz
123  * VCO        = 560 MHz
124  * VCOUNT     = 84 (2016)
125  * HCOUNT     = 128 (3072)
126  * CKREF_DIV  = 2
127  * CKVAR_DIV  = 175
128  * VCO_DIV    = 0
129  * SPCK_DIV   = 6
130  * MRCK_DIV   = 7
131  * LVDSCK_DIV = 0
132  */
133 	.type = ET8EK8_REGLIST_MODE,
134 	.mode = {
135 		.sensor_width = 2592,
136 		.sensor_height = 1968,
137 		.sensor_window_origin_x = 0,
138 		.sensor_window_origin_y = 0,
139 		.sensor_window_width = 2592,
140 		.sensor_window_height = 1968,
141 		.width = 3072,
142 		.height = 2016,
143 		.window_origin_x = 0,
144 		.window_origin_y = 0,
145 		.window_width = 2592,
146 		.window_height = 1968,
147 		.pixel_clock = 80000000,
148 		.ext_clock = 9600000,
149 		.timeperframe = {
150 			.numerator = 100,
151 			.denominator = 1292
152 		},
153 		.max_exp = 2012,
154 		/* .max_gain = 0, */
155 		.bus_format = MEDIA_BUS_FMT_SGRBG10_DPCM8_1X8,
156 		.sensitivity = 65536
157 	},
158 	.regs = {
159 		{ ET8EK8_REG_8BIT, 0x1239, 0x57 },
160 		{ ET8EK8_REG_8BIT, 0x1238, 0x82 },
161 		{ ET8EK8_REG_8BIT, 0x123B, 0x70 },
162 		{ ET8EK8_REG_8BIT, 0x123A, 0x06 },
163 		{ ET8EK8_REG_8BIT, 0x121B, 0x64 },
164 		{ ET8EK8_REG_8BIT, 0x121D, 0x64 },
165 		{ ET8EK8_REG_8BIT, 0x1221, 0x00 },
166 		{ ET8EK8_REG_8BIT, 0x1220, 0x80 }, /* <-changed to v14 7E->80 */
167 		{ ET8EK8_REG_8BIT, 0x1223, 0x00 },
168 		{ ET8EK8_REG_8BIT, 0x1222, 0x54 },
169 		{ ET8EK8_REG_8BIT, 0x125D, 0x83 }, /* CCP_LVDS_MODE/  */
170 		{ ET8EK8_REG_TERM, 0, 0}
171 	}
172 };
173 
174 /* Mode3_4VGA_1296x984_29.99fps_DPCM10-8 */
175 static struct et8ek8_reglist mode3_4vga_1296x984_29_99fps_dpcm10_8 = {
176 /* (without the +1)
177  * SPCK       = 96.5333333333333 MHz
178  * CCP2       = 579.2 MHz
179  * VCO        = 579.2 MHz
180  * VCOUNT     = 84 (2016)
181  * HCOUNT     = 133 (3192)
182  * CKREF_DIV  = 2
183  * CKVAR_DIV  = 181
184  * VCO_DIV    = 0
185  * SPCK_DIV   = 5
186  * MRCK_DIV   = 7
187  * LVDSCK_DIV = 0
188  */
189 	.type = ET8EK8_REGLIST_MODE,
190 	.mode = {
191 		.sensor_width = 2592,
192 		.sensor_height = 1968,
193 		.sensor_window_origin_x = 0,
194 		.sensor_window_origin_y = 0,
195 		.sensor_window_width = 2592,
196 		.sensor_window_height = 1968,
197 		.width = 3192,
198 		.height = 1008,
199 		.window_origin_x = 0,
200 		.window_origin_y = 0,
201 		.window_width = 1296,
202 		.window_height = 984,
203 		.pixel_clock = 96533333,
204 		.ext_clock = 9600000,
205 		.timeperframe = {
206 			.numerator = 100,
207 			.denominator = 3000
208 		},
209 		.max_exp = 1004,
210 		/* .max_gain = 0, */
211 		.bus_format = MEDIA_BUS_FMT_SGRBG10_DPCM8_1X8,
212 		.sensitivity = 65536
213 	},
214 	.regs = {
215 		{ ET8EK8_REG_8BIT, 0x1239, 0x5A },
216 		{ ET8EK8_REG_8BIT, 0x1238, 0x82 },
217 		{ ET8EK8_REG_8BIT, 0x123B, 0x70 },
218 		{ ET8EK8_REG_8BIT, 0x123A, 0x05 },
219 		{ ET8EK8_REG_8BIT, 0x121B, 0x63 },
220 		{ ET8EK8_REG_8BIT, 0x1220, 0x85 },
221 		{ ET8EK8_REG_8BIT, 0x1221, 0x00 },
222 		{ ET8EK8_REG_8BIT, 0x1222, 0x54 },
223 		{ ET8EK8_REG_8BIT, 0x1223, 0x00 },
224 		{ ET8EK8_REG_8BIT, 0x121D, 0x63 },
225 		{ ET8EK8_REG_8BIT, 0x125D, 0x83 }, /* CCP_LVDS_MODE/  */
226 		{ ET8EK8_REG_TERM, 0, 0}
227 	}
228 };
229 
230 /* Mode4_SVGA_864x656_29.88fps */
231 static struct et8ek8_reglist mode4_svga_864x656_29_88fps = {
232 /* (without the +1)
233  * SPCK       = 80 MHz
234  * CCP2       = 320 MHz
235  * VCO        = 640 MHz
236  * VCOUNT     = 84 (2016)
237  * HCOUNT     = 166 (3984)
238  * CKREF_DIV  = 2
239  * CKVAR_DIV  = 200
240  * VCO_DIV    = 0
241  * SPCK_DIV   = 7
242  * MRCK_DIV   = 7
243  * LVDSCK_DIV = 1
244  */
245 	.type = ET8EK8_REGLIST_MODE,
246 	.mode = {
247 		.sensor_width = 2592,
248 		.sensor_height = 1968,
249 		.sensor_window_origin_x = 0,
250 		.sensor_window_origin_y = 0,
251 		.sensor_window_width = 2592,
252 		.sensor_window_height = 1968,
253 		.width = 3984,
254 		.height = 672,
255 		.window_origin_x = 0,
256 		.window_origin_y = 0,
257 		.window_width = 864,
258 		.window_height = 656,
259 		.pixel_clock = 80000000,
260 		.ext_clock = 9600000,
261 		.timeperframe = {
262 			.numerator = 100,
263 			.denominator = 2988
264 		},
265 		.max_exp = 668,
266 		/* .max_gain = 0, */
267 		.bus_format = MEDIA_BUS_FMT_SGRBG10_1X10,
268 		.sensitivity = 65536
269 	},
270 	.regs = {
271 		{ ET8EK8_REG_8BIT, 0x1239, 0x64 },
272 		{ ET8EK8_REG_8BIT, 0x1238, 0x02 },
273 		{ ET8EK8_REG_8BIT, 0x123B, 0x71 },
274 		{ ET8EK8_REG_8BIT, 0x123A, 0x07 },
275 		{ ET8EK8_REG_8BIT, 0x121B, 0x62 },
276 		{ ET8EK8_REG_8BIT, 0x121D, 0x62 },
277 		{ ET8EK8_REG_8BIT, 0x1221, 0x00 },
278 		{ ET8EK8_REG_8BIT, 0x1220, 0xA6 },
279 		{ ET8EK8_REG_8BIT, 0x1223, 0x00 },
280 		{ ET8EK8_REG_8BIT, 0x1222, 0x54 },
281 		{ ET8EK8_REG_8BIT, 0x125D, 0x88 }, /* CCP_LVDS_MODE/  */
282 		{ ET8EK8_REG_TERM, 0, 0}
283 	}
284 };
285 
286 /* Mode5_VGA_648x492_29.93fps */
287 static struct et8ek8_reglist mode5_vga_648x492_29_93fps = {
288 /* (without the +1)
289  * SPCK       = 80 MHz
290  * CCP2       = 320 MHz
291  * VCO        = 640 MHz
292  * VCOUNT     = 84 (2016)
293  * HCOUNT     = 221 (5304)
294  * CKREF_DIV  = 2
295  * CKVAR_DIV  = 200
296  * VCO_DIV    = 0
297  * SPCK_DIV   = 7
298  * MRCK_DIV   = 7
299  * LVDSCK_DIV = 1
300  */
301 	.type = ET8EK8_REGLIST_MODE,
302 	.mode = {
303 		.sensor_width = 2592,
304 		.sensor_height = 1968,
305 		.sensor_window_origin_x = 0,
306 		.sensor_window_origin_y = 0,
307 		.sensor_window_width = 2592,
308 		.sensor_window_height = 1968,
309 		.width = 5304,
310 		.height = 504,
311 		.window_origin_x = 0,
312 		.window_origin_y = 0,
313 		.window_width = 648,
314 		.window_height = 492,
315 		.pixel_clock = 80000000,
316 		.ext_clock = 9600000,
317 		.timeperframe = {
318 			.numerator = 100,
319 			.denominator = 2993
320 		},
321 		.max_exp = 500,
322 		/* .max_gain = 0, */
323 		.bus_format = MEDIA_BUS_FMT_SGRBG10_1X10,
324 		.sensitivity = 65536
325 	},
326 	.regs = {
327 		{ ET8EK8_REG_8BIT, 0x1239, 0x64 },
328 		{ ET8EK8_REG_8BIT, 0x1238, 0x02 },
329 		{ ET8EK8_REG_8BIT, 0x123B, 0x71 },
330 		{ ET8EK8_REG_8BIT, 0x123A, 0x07 },
331 		{ ET8EK8_REG_8BIT, 0x121B, 0x61 },
332 		{ ET8EK8_REG_8BIT, 0x121D, 0x61 },
333 		{ ET8EK8_REG_8BIT, 0x1221, 0x00 },
334 		{ ET8EK8_REG_8BIT, 0x1220, 0xDD },
335 		{ ET8EK8_REG_8BIT, 0x1223, 0x00 },
336 		{ ET8EK8_REG_8BIT, 0x1222, 0x54 },
337 		{ ET8EK8_REG_8BIT, 0x125D, 0x88 }, /* CCP_LVDS_MODE/  */
338 		{ ET8EK8_REG_TERM, 0, 0}
339 	}
340 };
341 
342 /* Mode2_16VGA_2592x1968_3.99fps */
343 static struct et8ek8_reglist mode2_16vga_2592x1968_3_99fps = {
344 /* (without the +1)
345  * SPCK       = 80 MHz
346  * CCP2       = 640 MHz
347  * VCO        = 640 MHz
348  * VCOUNT     = 254 (6096)
349  * HCOUNT     = 137 (3288)
350  * CKREF_DIV  = 2
351  * CKVAR_DIV  = 200
352  * VCO_DIV    = 0
353  * SPCK_DIV   = 7
354  * MRCK_DIV   = 7
355  * LVDSCK_DIV = 0
356  */
357 	.type = ET8EK8_REGLIST_MODE,
358 	.mode = {
359 		.sensor_width = 2592,
360 		.sensor_height = 1968,
361 		.sensor_window_origin_x = 0,
362 		.sensor_window_origin_y = 0,
363 		.sensor_window_width = 2592,
364 		.sensor_window_height = 1968,
365 		.width = 3288,
366 		.height = 6096,
367 		.window_origin_x = 0,
368 		.window_origin_y = 0,
369 		.window_width = 2592,
370 		.window_height = 1968,
371 		.pixel_clock = 80000000,
372 		.ext_clock = 9600000,
373 		.timeperframe = {
374 			.numerator = 100,
375 			.denominator = 399
376 		},
377 		.max_exp = 6092,
378 		/* .max_gain = 0, */
379 		.bus_format = MEDIA_BUS_FMT_SGRBG10_1X10,
380 		.sensitivity = 65536
381 	},
382 	.regs = {
383 		{ ET8EK8_REG_8BIT, 0x1239, 0x64 },
384 		{ ET8EK8_REG_8BIT, 0x1238, 0x02 },
385 		{ ET8EK8_REG_8BIT, 0x123B, 0x70 },
386 		{ ET8EK8_REG_8BIT, 0x123A, 0x07 },
387 		{ ET8EK8_REG_8BIT, 0x121B, 0x64 },
388 		{ ET8EK8_REG_8BIT, 0x121D, 0x64 },
389 		{ ET8EK8_REG_8BIT, 0x1221, 0x00 },
390 		{ ET8EK8_REG_8BIT, 0x1220, 0x89 },
391 		{ ET8EK8_REG_8BIT, 0x1223, 0x00 },
392 		{ ET8EK8_REG_8BIT, 0x1222, 0xFE },
393 		{ ET8EK8_REG_TERM, 0, 0}
394 	}
395 };
396 
397 /* Mode_648x492_5fps */
398 static struct et8ek8_reglist mode_648x492_5fps = {
399 /* (without the +1)
400  * SPCK       = 13.3333333333333 MHz
401  * CCP2       = 53.3333333333333 MHz
402  * VCO        = 640 MHz
403  * VCOUNT     = 84 (2016)
404  * HCOUNT     = 221 (5304)
405  * CKREF_DIV  = 2
406  * CKVAR_DIV  = 200
407  * VCO_DIV    = 5
408  * SPCK_DIV   = 7
409  * MRCK_DIV   = 7
410  * LVDSCK_DIV = 1
411  */
412 	.type = ET8EK8_REGLIST_MODE,
413 	.mode = {
414 		.sensor_width = 2592,
415 		.sensor_height = 1968,
416 		.sensor_window_origin_x = 0,
417 		.sensor_window_origin_y = 0,
418 		.sensor_window_width = 2592,
419 		.sensor_window_height = 1968,
420 		.width = 5304,
421 		.height = 504,
422 		.window_origin_x = 0,
423 		.window_origin_y = 0,
424 		.window_width = 648,
425 		.window_height = 492,
426 		.pixel_clock = 13333333,
427 		.ext_clock = 9600000,
428 		.timeperframe = {
429 			.numerator = 100,
430 			.denominator = 499
431 		},
432 		.max_exp = 500,
433 		/* .max_gain = 0, */
434 		.bus_format = MEDIA_BUS_FMT_SGRBG10_1X10,
435 		.sensitivity = 65536
436 	},
437 	.regs = {
438 		{ ET8EK8_REG_8BIT, 0x1239, 0x64 },
439 		{ ET8EK8_REG_8BIT, 0x1238, 0x02 },
440 		{ ET8EK8_REG_8BIT, 0x123B, 0x71 },
441 		{ ET8EK8_REG_8BIT, 0x123A, 0x57 },
442 		{ ET8EK8_REG_8BIT, 0x121B, 0x61 },
443 		{ ET8EK8_REG_8BIT, 0x121D, 0x61 },
444 		{ ET8EK8_REG_8BIT, 0x1221, 0x00 },
445 		{ ET8EK8_REG_8BIT, 0x1220, 0xDD },
446 		{ ET8EK8_REG_8BIT, 0x1223, 0x00 },
447 		{ ET8EK8_REG_8BIT, 0x1222, 0x54 },
448 		{ ET8EK8_REG_8BIT, 0x125D, 0x88 }, /* CCP_LVDS_MODE/  */
449 		{ ET8EK8_REG_TERM, 0, 0}
450 	}
451 };
452 
453 /* Mode3_4VGA_1296x984_5fps */
454 static struct et8ek8_reglist mode3_4vga_1296x984_5fps = {
455 /* (without the +1)
456  * SPCK       = 49.4 MHz
457  * CCP2       = 395.2 MHz
458  * VCO        = 790.4 MHz
459  * VCOUNT     = 250 (6000)
460  * HCOUNT     = 137 (3288)
461  * CKREF_DIV  = 2
462  * CKVAR_DIV  = 247
463  * VCO_DIV    = 1
464  * SPCK_DIV   = 7
465  * MRCK_DIV   = 7
466  * LVDSCK_DIV = 0
467  */
468 	.type = ET8EK8_REGLIST_MODE,
469 	.mode = {
470 		.sensor_width = 2592,
471 		.sensor_height = 1968,
472 		.sensor_window_origin_x = 0,
473 		.sensor_window_origin_y = 0,
474 		.sensor_window_width = 2592,
475 		.sensor_window_height = 1968,
476 		.width = 3288,
477 		.height = 3000,
478 		.window_origin_x = 0,
479 		.window_origin_y = 0,
480 		.window_width = 1296,
481 		.window_height = 984,
482 		.pixel_clock = 49400000,
483 		.ext_clock = 9600000,
484 		.timeperframe = {
485 			.numerator = 100,
486 			.denominator = 501
487 		},
488 		.max_exp = 2996,
489 		/* .max_gain = 0, */
490 		.bus_format = MEDIA_BUS_FMT_SGRBG10_1X10,
491 		.sensitivity = 65536
492 	},
493 	.regs = {
494 		{ ET8EK8_REG_8BIT, 0x1239, 0x7B },
495 		{ ET8EK8_REG_8BIT, 0x1238, 0x82 },
496 		{ ET8EK8_REG_8BIT, 0x123B, 0x70 },
497 		{ ET8EK8_REG_8BIT, 0x123A, 0x17 },
498 		{ ET8EK8_REG_8BIT, 0x121B, 0x63 },
499 		{ ET8EK8_REG_8BIT, 0x121D, 0x63 },
500 		{ ET8EK8_REG_8BIT, 0x1221, 0x00 },
501 		{ ET8EK8_REG_8BIT, 0x1220, 0x89 },
502 		{ ET8EK8_REG_8BIT, 0x1223, 0x00 },
503 		{ ET8EK8_REG_8BIT, 0x1222, 0xFA },
504 		{ ET8EK8_REG_8BIT, 0x125D, 0x88 }, /* CCP_LVDS_MODE/  */
505 		{ ET8EK8_REG_TERM, 0, 0}
506 	}
507 };
508 
509 /* Mode_4VGA_1296x984_25fps_DPCM10-8 */
510 static struct et8ek8_reglist mode_4vga_1296x984_25fps_dpcm10_8 = {
511 /* (without the +1)
512  * SPCK       = 84.2666666666667 MHz
513  * CCP2       = 505.6 MHz
514  * VCO        = 505.6 MHz
515  * VCOUNT     = 88 (2112)
516  * HCOUNT     = 133 (3192)
517  * CKREF_DIV  = 2
518  * CKVAR_DIV  = 158
519  * VCO_DIV    = 0
520  * SPCK_DIV   = 5
521  * MRCK_DIV   = 7
522  * LVDSCK_DIV = 0
523  */
524 	.type = ET8EK8_REGLIST_MODE,
525 	.mode = {
526 		.sensor_width = 2592,
527 		.sensor_height = 1968,
528 		.sensor_window_origin_x = 0,
529 		.sensor_window_origin_y = 0,
530 		.sensor_window_width = 2592,
531 		.sensor_window_height = 1968,
532 		.width = 3192,
533 		.height = 1056,
534 		.window_origin_x = 0,
535 		.window_origin_y = 0,
536 		.window_width = 1296,
537 		.window_height = 984,
538 		.pixel_clock = 84266667,
539 		.ext_clock = 9600000,
540 		.timeperframe = {
541 			.numerator = 100,
542 			.denominator = 2500
543 		},
544 		.max_exp = 1052,
545 		/* .max_gain = 0, */
546 		.bus_format = MEDIA_BUS_FMT_SGRBG10_DPCM8_1X8,
547 		.sensitivity = 65536
548 	},
549 	.regs = {
550 		{ ET8EK8_REG_8BIT, 0x1239, 0x4F },
551 		{ ET8EK8_REG_8BIT, 0x1238, 0x02 },
552 		{ ET8EK8_REG_8BIT, 0x123B, 0x70 },
553 		{ ET8EK8_REG_8BIT, 0x123A, 0x05 },
554 		{ ET8EK8_REG_8BIT, 0x121B, 0x63 },
555 		{ ET8EK8_REG_8BIT, 0x1220, 0x85 },
556 		{ ET8EK8_REG_8BIT, 0x1221, 0x00 },
557 		{ ET8EK8_REG_8BIT, 0x1222, 0x58 },
558 		{ ET8EK8_REG_8BIT, 0x1223, 0x00 },
559 		{ ET8EK8_REG_8BIT, 0x121D, 0x63 },
560 		{ ET8EK8_REG_8BIT, 0x125D, 0x83 },
561 		{ ET8EK8_REG_TERM, 0, 0}
562 	}
563 };
564 
565 struct et8ek8_meta_reglist meta_reglist = {
566 	.version = "V14 03-June-2008",
567 	.reglist = {
568 		{ .ptr = &mode1_poweron_mode2_16vga_2592x1968_12_07fps },
569 		{ .ptr = &mode1_16vga_2592x1968_13_12fps_dpcm10_8 },
570 		{ .ptr = &mode3_4vga_1296x984_29_99fps_dpcm10_8 },
571 		{ .ptr = &mode4_svga_864x656_29_88fps },
572 		{ .ptr = &mode5_vga_648x492_29_93fps },
573 		{ .ptr = &mode2_16vga_2592x1968_3_99fps },
574 		{ .ptr = &mode_648x492_5fps },
575 		{ .ptr = &mode3_4vga_1296x984_5fps },
576 		{ .ptr = &mode_4vga_1296x984_25fps_dpcm10_8 },
577 		{ .ptr = NULL }
578 	}
579 };
580