xref: /openbmc/linux/drivers/media/i2c/ccs/ccs-quirk.c (revision ae502e08)
1b24cc2a1SSakari Ailus // SPDX-License-Identifier: GPL-2.0-only
2b24cc2a1SSakari Ailus /*
3b24cc2a1SSakari Ailus  * drivers/media/i2c/ccs/ccs-quirk.c
4b24cc2a1SSakari Ailus  *
5b24cc2a1SSakari Ailus  * Generic driver for MIPI CCS/SMIA/SMIA++ compliant camera sensors
6b24cc2a1SSakari Ailus  *
7b24cc2a1SSakari Ailus  * Copyright (C) 2020 Intel Corporation
8b24cc2a1SSakari Ailus  * Copyright (C) 2011--2012 Nokia Corporation
97389d01cSSakari Ailus  * Contact: Sakari Ailus <sakari.ailus@linux.intel.com>
10b24cc2a1SSakari Ailus  */
11b24cc2a1SSakari Ailus 
12b24cc2a1SSakari Ailus #include <linux/delay.h>
13b24cc2a1SSakari Ailus 
14b24cc2a1SSakari Ailus #include "ccs.h"
15b24cc2a1SSakari Ailus #include "ccs-limits.h"
16b24cc2a1SSakari Ailus 
ccs_write_addr_8s(struct ccs_sensor * sensor,const struct ccs_reg_8 * regs,int len)17b24cc2a1SSakari Ailus static int ccs_write_addr_8s(struct ccs_sensor *sensor,
18b24cc2a1SSakari Ailus 			     const struct ccs_reg_8 *regs, int len)
19b24cc2a1SSakari Ailus {
20b24cc2a1SSakari Ailus 	struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
21b24cc2a1SSakari Ailus 	int rval;
22b24cc2a1SSakari Ailus 
23b24cc2a1SSakari Ailus 	for (; len > 0; len--, regs++) {
24b24cc2a1SSakari Ailus 		rval = ccs_write_addr(sensor, regs->reg, regs->val);
25b24cc2a1SSakari Ailus 		if (rval < 0) {
26b24cc2a1SSakari Ailus 			dev_err(&client->dev,
27b24cc2a1SSakari Ailus 				"error %d writing reg 0x%4.4x, val 0x%2.2x",
28b24cc2a1SSakari Ailus 				rval, regs->reg, regs->val);
29b24cc2a1SSakari Ailus 			return rval;
30b24cc2a1SSakari Ailus 		}
31b24cc2a1SSakari Ailus 	}
32b24cc2a1SSakari Ailus 
33b24cc2a1SSakari Ailus 	return 0;
34b24cc2a1SSakari Ailus }
35b24cc2a1SSakari Ailus 
jt8ew9_limits(struct ccs_sensor * sensor)36b24cc2a1SSakari Ailus static int jt8ew9_limits(struct ccs_sensor *sensor)
37b24cc2a1SSakari Ailus {
38f86ae916SSakari Ailus 	if (sensor->minfo.revision_number < 0x0300)
39b24cc2a1SSakari Ailus 		sensor->frame_skip = 1;
40b24cc2a1SSakari Ailus 
41b24cc2a1SSakari Ailus 	/* Below 24 gain doesn't have effect at all, */
42b24cc2a1SSakari Ailus 	/* but ~59 is needed for full dynamic range */
43b24cc2a1SSakari Ailus 	ccs_replace_limit(sensor, CCS_L_ANALOG_GAIN_CODE_MIN, 0, 59);
44b24cc2a1SSakari Ailus 	ccs_replace_limit(sensor, CCS_L_ANALOG_GAIN_CODE_MAX, 0, 6000);
45b24cc2a1SSakari Ailus 
46b24cc2a1SSakari Ailus 	return 0;
47b24cc2a1SSakari Ailus }
48b24cc2a1SSakari Ailus 
jt8ew9_post_poweron(struct ccs_sensor * sensor)49b24cc2a1SSakari Ailus static int jt8ew9_post_poweron(struct ccs_sensor *sensor)
50b24cc2a1SSakari Ailus {
51b24cc2a1SSakari Ailus 	static const struct ccs_reg_8 regs[] = {
52b24cc2a1SSakari Ailus 		{ 0x30a3, 0xd8 }, /* Output port control : LVDS ports only */
53b24cc2a1SSakari Ailus 		{ 0x30ae, 0x00 }, /* 0x0307 pll_multiplier maximum value on PLL input 9.6MHz ( 19.2MHz is divided on pre_pll_div) */
54b24cc2a1SSakari Ailus 		{ 0x30af, 0xd0 }, /* 0x0307 pll_multiplier maximum value on PLL input 9.6MHz ( 19.2MHz is divided on pre_pll_div) */
55b24cc2a1SSakari Ailus 		{ 0x322d, 0x04 }, /* Adjusting Processing Image Size to Scaler Toshiba Recommendation Setting */
56b24cc2a1SSakari Ailus 		{ 0x3255, 0x0f }, /* Horizontal Noise Reduction Control Toshiba Recommendation Setting */
57b24cc2a1SSakari Ailus 		{ 0x3256, 0x15 }, /* Horizontal Noise Reduction Control Toshiba Recommendation Setting */
58b24cc2a1SSakari Ailus 		{ 0x3258, 0x70 }, /* Analog Gain Control Toshiba Recommendation Setting */
59b24cc2a1SSakari Ailus 		{ 0x3259, 0x70 }, /* Analog Gain Control Toshiba Recommendation Setting */
60b24cc2a1SSakari Ailus 		{ 0x325f, 0x7c }, /* Analog Gain Control Toshiba Recommendation Setting */
61b24cc2a1SSakari Ailus 		{ 0x3302, 0x06 }, /* Pixel Reference Voltage Control Toshiba Recommendation Setting */
62b24cc2a1SSakari Ailus 		{ 0x3304, 0x00 }, /* Pixel Reference Voltage Control Toshiba Recommendation Setting */
63b24cc2a1SSakari Ailus 		{ 0x3307, 0x22 }, /* Pixel Reference Voltage Control Toshiba Recommendation Setting */
64b24cc2a1SSakari Ailus 		{ 0x3308, 0x8d }, /* Pixel Reference Voltage Control Toshiba Recommendation Setting */
65b24cc2a1SSakari Ailus 		{ 0x331e, 0x0f }, /* Black Hole Sun Correction Control Toshiba Recommendation Setting */
66b24cc2a1SSakari Ailus 		{ 0x3320, 0x30 }, /* Black Hole Sun Correction Control Toshiba Recommendation Setting */
67b24cc2a1SSakari Ailus 		{ 0x3321, 0x11 }, /* Black Hole Sun Correction Control Toshiba Recommendation Setting */
68b24cc2a1SSakari Ailus 		{ 0x3322, 0x98 }, /* Black Hole Sun Correction Control Toshiba Recommendation Setting */
69b24cc2a1SSakari Ailus 		{ 0x3323, 0x64 }, /* Black Hole Sun Correction Control Toshiba Recommendation Setting */
70b24cc2a1SSakari Ailus 		{ 0x3325, 0x83 }, /* Read Out Timing Control Toshiba Recommendation Setting */
71b24cc2a1SSakari Ailus 		{ 0x3330, 0x18 }, /* Read Out Timing Control Toshiba Recommendation Setting */
72b24cc2a1SSakari Ailus 		{ 0x333c, 0x01 }, /* Read Out Timing Control Toshiba Recommendation Setting */
73b24cc2a1SSakari Ailus 		{ 0x3345, 0x2f }, /* Black Hole Sun Correction Control Toshiba Recommendation Setting */
74b24cc2a1SSakari Ailus 		{ 0x33de, 0x38 }, /* Horizontal Noise Reduction Control Toshiba Recommendation Setting */
75b24cc2a1SSakari Ailus 		/* Taken from v03. No idea what the rest are. */
76b24cc2a1SSakari Ailus 		{ 0x32e0, 0x05 },
77b24cc2a1SSakari Ailus 		{ 0x32e1, 0x05 },
78b24cc2a1SSakari Ailus 		{ 0x32e2, 0x04 },
79b24cc2a1SSakari Ailus 		{ 0x32e5, 0x04 },
80b24cc2a1SSakari Ailus 		{ 0x32e6, 0x04 },
81b24cc2a1SSakari Ailus 
82b24cc2a1SSakari Ailus 	};
83b24cc2a1SSakari Ailus 
84b24cc2a1SSakari Ailus 	return ccs_write_addr_8s(sensor, regs, ARRAY_SIZE(regs));
85b24cc2a1SSakari Ailus }
86b24cc2a1SSakari Ailus 
87b24cc2a1SSakari Ailus const struct ccs_quirk smiapp_jt8ew9_quirk = {
88b24cc2a1SSakari Ailus 	.limits = jt8ew9_limits,
89b24cc2a1SSakari Ailus 	.post_poweron = jt8ew9_post_poweron,
90b24cc2a1SSakari Ailus };
91b24cc2a1SSakari Ailus 
imx125es_post_poweron(struct ccs_sensor * sensor)92b24cc2a1SSakari Ailus static int imx125es_post_poweron(struct ccs_sensor *sensor)
93b24cc2a1SSakari Ailus {
94b24cc2a1SSakari Ailus 	/* Taken from v02. No idea what the other two are. */
95b24cc2a1SSakari Ailus 	static const struct ccs_reg_8 regs[] = {
96b24cc2a1SSakari Ailus 		/*
97b24cc2a1SSakari Ailus 		 * 0x3302: clk during frame blanking:
98b24cc2a1SSakari Ailus 		 * 0x00 - HS mode, 0x01 - LP11
99b24cc2a1SSakari Ailus 		 */
100b24cc2a1SSakari Ailus 		{ 0x3302, 0x01 },
101b24cc2a1SSakari Ailus 		{ 0x302d, 0x00 },
102b24cc2a1SSakari Ailus 		{ 0x3b08, 0x8c },
103b24cc2a1SSakari Ailus 	};
104b24cc2a1SSakari Ailus 
105b24cc2a1SSakari Ailus 	return ccs_write_addr_8s(sensor, regs, ARRAY_SIZE(regs));
106b24cc2a1SSakari Ailus }
107b24cc2a1SSakari Ailus 
108b24cc2a1SSakari Ailus const struct ccs_quirk smiapp_imx125es_quirk = {
109b24cc2a1SSakari Ailus 	.post_poweron = imx125es_post_poweron,
110b24cc2a1SSakari Ailus };
111b24cc2a1SSakari Ailus 
jt8ev1_limits(struct ccs_sensor * sensor)112b24cc2a1SSakari Ailus static int jt8ev1_limits(struct ccs_sensor *sensor)
113b24cc2a1SSakari Ailus {
114b24cc2a1SSakari Ailus 	ccs_replace_limit(sensor, CCS_L_X_ADDR_MAX, 0, 4271);
115b24cc2a1SSakari Ailus 	ccs_replace_limit(sensor, CCS_L_MIN_LINE_BLANKING_PCK_BIN, 0, 184);
116b24cc2a1SSakari Ailus 
117b24cc2a1SSakari Ailus 	return 0;
118b24cc2a1SSakari Ailus }
119b24cc2a1SSakari Ailus 
jt8ev1_post_poweron(struct ccs_sensor * sensor)120b24cc2a1SSakari Ailus static int jt8ev1_post_poweron(struct ccs_sensor *sensor)
121b24cc2a1SSakari Ailus {
122b24cc2a1SSakari Ailus 	struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
123b24cc2a1SSakari Ailus 	int rval;
124b24cc2a1SSakari Ailus 	static const struct ccs_reg_8 regs[] = {
125b24cc2a1SSakari Ailus 		{ 0x3031, 0xcd }, /* For digital binning (EQ_MONI) */
126b24cc2a1SSakari Ailus 		{ 0x30a3, 0xd0 }, /* FLASH STROBE enable */
127b24cc2a1SSakari Ailus 		{ 0x3237, 0x00 }, /* For control of pulse timing for ADC */
128b24cc2a1SSakari Ailus 		{ 0x3238, 0x43 },
129b24cc2a1SSakari Ailus 		{ 0x3301, 0x06 }, /* For analog bias for sensor */
130b24cc2a1SSakari Ailus 		{ 0x3302, 0x06 },
131b24cc2a1SSakari Ailus 		{ 0x3304, 0x00 },
132b24cc2a1SSakari Ailus 		{ 0x3305, 0x88 },
133b24cc2a1SSakari Ailus 		{ 0x332a, 0x14 },
134b24cc2a1SSakari Ailus 		{ 0x332c, 0x6b },
135b24cc2a1SSakari Ailus 		{ 0x3336, 0x01 },
136b24cc2a1SSakari Ailus 		{ 0x333f, 0x1f },
137b24cc2a1SSakari Ailus 		{ 0x3355, 0x00 },
138b24cc2a1SSakari Ailus 		{ 0x3356, 0x20 },
139b24cc2a1SSakari Ailus 		{ 0x33bf, 0x20 }, /* Adjust the FBC speed */
140b24cc2a1SSakari Ailus 		{ 0x33c9, 0x20 },
141b24cc2a1SSakari Ailus 		{ 0x33ce, 0x30 }, /* Adjust the parameter for logic function */
142b24cc2a1SSakari Ailus 		{ 0x33cf, 0xec }, /* For Black sun */
143b24cc2a1SSakari Ailus 		{ 0x3328, 0x80 }, /* Ugh. No idea what's this. */
144b24cc2a1SSakari Ailus 	};
145b24cc2a1SSakari Ailus 	static const struct ccs_reg_8 regs_96[] = {
146b24cc2a1SSakari Ailus 		{ 0x30ae, 0x00 }, /* For control of ADC clock */
147b24cc2a1SSakari Ailus 		{ 0x30af, 0xd0 },
148b24cc2a1SSakari Ailus 		{ 0x30b0, 0x01 },
149b24cc2a1SSakari Ailus 	};
150b24cc2a1SSakari Ailus 
151b24cc2a1SSakari Ailus 	rval = ccs_write_addr_8s(sensor, regs, ARRAY_SIZE(regs));
152b24cc2a1SSakari Ailus 	if (rval < 0)
153b24cc2a1SSakari Ailus 		return rval;
154b24cc2a1SSakari Ailus 
1557b1dd0f8SSakari Ailus 	switch (sensor->hwcfg.ext_clk) {
156b24cc2a1SSakari Ailus 	case 9600000:
157b24cc2a1SSakari Ailus 		return ccs_write_addr_8s(sensor, regs_96,
158b24cc2a1SSakari Ailus 				       ARRAY_SIZE(regs_96));
159b24cc2a1SSakari Ailus 	default:
160b24cc2a1SSakari Ailus 		dev_warn(&client->dev, "no MSRs for %d Hz ext_clk\n",
1617b1dd0f8SSakari Ailus 			 sensor->hwcfg.ext_clk);
162b24cc2a1SSakari Ailus 		return 0;
163b24cc2a1SSakari Ailus 	}
164b24cc2a1SSakari Ailus }
165b24cc2a1SSakari Ailus 
jt8ev1_pre_streamon(struct ccs_sensor * sensor)166b24cc2a1SSakari Ailus static int jt8ev1_pre_streamon(struct ccs_sensor *sensor)
167b24cc2a1SSakari Ailus {
168b24cc2a1SSakari Ailus 	return ccs_write_addr(sensor, 0x3328, 0x00);
169b24cc2a1SSakari Ailus }
170b24cc2a1SSakari Ailus 
jt8ev1_post_streamoff(struct ccs_sensor * sensor)171b24cc2a1SSakari Ailus static int jt8ev1_post_streamoff(struct ccs_sensor *sensor)
172b24cc2a1SSakari Ailus {
173b24cc2a1SSakari Ailus 	int rval;
174b24cc2a1SSakari Ailus 
175b24cc2a1SSakari Ailus 	/* Workaround: allows fast standby to work properly */
176b24cc2a1SSakari Ailus 	rval = ccs_write_addr(sensor, 0x3205, 0x04);
177b24cc2a1SSakari Ailus 	if (rval < 0)
178b24cc2a1SSakari Ailus 		return rval;
179b24cc2a1SSakari Ailus 
180b24cc2a1SSakari Ailus 	/* Wait for 1 ms + one line => 2 ms is likely enough */
181b24cc2a1SSakari Ailus 	usleep_range(2000, 2050);
182b24cc2a1SSakari Ailus 
183b24cc2a1SSakari Ailus 	/* Restore it */
184b24cc2a1SSakari Ailus 	rval = ccs_write_addr(sensor, 0x3205, 0x00);
185b24cc2a1SSakari Ailus 	if (rval < 0)
186b24cc2a1SSakari Ailus 		return rval;
187b24cc2a1SSakari Ailus 
188b24cc2a1SSakari Ailus 	return ccs_write_addr(sensor, 0x3328, 0x80);
189b24cc2a1SSakari Ailus }
190b24cc2a1SSakari Ailus 
jt8ev1_init(struct ccs_sensor * sensor)191b24cc2a1SSakari Ailus static int jt8ev1_init(struct ccs_sensor *sensor)
192b24cc2a1SSakari Ailus {
193*ae502e08SSakari Ailus 	sensor->pll.flags |= CCS_PLL_FLAG_LANE_SPEED_MODEL |
194*ae502e08SSakari Ailus 		CCS_PLL_FLAG_LINK_DECOUPLED;
195*ae502e08SSakari Ailus 	sensor->pll.vt_lanes = 1;
196*ae502e08SSakari Ailus 	sensor->pll.op_lanes = sensor->pll.csi2.lanes;
197b24cc2a1SSakari Ailus 
198b24cc2a1SSakari Ailus 	return 0;
199b24cc2a1SSakari Ailus }
200b24cc2a1SSakari Ailus 
201b24cc2a1SSakari Ailus const struct ccs_quirk smiapp_jt8ev1_quirk = {
202b24cc2a1SSakari Ailus 	.limits = jt8ev1_limits,
203b24cc2a1SSakari Ailus 	.post_poweron = jt8ev1_post_poweron,
204b24cc2a1SSakari Ailus 	.pre_streamon = jt8ev1_pre_streamon,
205b24cc2a1SSakari Ailus 	.post_streamoff = jt8ev1_post_streamoff,
206b24cc2a1SSakari Ailus 	.init = jt8ev1_init,
207b24cc2a1SSakari Ailus };
208b24cc2a1SSakari Ailus 
tcm8500md_limits(struct ccs_sensor * sensor)209b24cc2a1SSakari Ailus static int tcm8500md_limits(struct ccs_sensor *sensor)
210b24cc2a1SSakari Ailus {
211b24cc2a1SSakari Ailus 	ccs_replace_limit(sensor, CCS_L_MIN_PLL_IP_CLK_FREQ_MHZ, 0, 2700000);
212b24cc2a1SSakari Ailus 
213b24cc2a1SSakari Ailus 	return 0;
214b24cc2a1SSakari Ailus }
215b24cc2a1SSakari Ailus 
216b24cc2a1SSakari Ailus const struct ccs_quirk smiapp_tcm8500md_quirk = {
217b24cc2a1SSakari Ailus 	.limits = tcm8500md_limits,
218b24cc2a1SSakari Ailus };
219