1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * drivers/media/i2c/ccs-pll.h 4 * 5 * Generic MIPI CCS/SMIA/SMIA++ PLL calculator 6 * 7 * Copyright (C) 2020 Intel Corporation 8 * Copyright (C) 2012 Nokia Corporation 9 * Contact: Sakari Ailus <sakari.ailus@linux.intel.com> 10 */ 11 12 #ifndef CCS_PLL_H 13 #define CCS_PLL_H 14 15 #include <linux/bits.h> 16 17 /* CSI-2 or CCP-2 */ 18 #define CCS_PLL_BUS_TYPE_CSI2_DPHY 0x00 19 #define CCS_PLL_BUS_TYPE_CSI2_CPHY 0x01 20 21 /* Old SMIA and implementation specific flags */ 22 /* op pix clock is for all lanes in total normally */ 23 #define CCS_PLL_FLAG_OP_PIX_CLOCK_PER_LANE BIT(0) 24 #define CCS_PLL_FLAG_NO_OP_CLOCKS BIT(1) 25 /* CCS PLL flags */ 26 #define CCS_PLL_FLAG_LANE_SPEED_MODEL BIT(2) 27 #define CCS_PLL_FLAG_LINK_DECOUPLED BIT(3) 28 #define CCS_PLL_FLAG_EXT_IP_PLL_DIVIDER BIT(4) 29 #define CCS_PLL_FLAG_FLEXIBLE_OP_PIX_CLK_DIV BIT(5) 30 31 /** 32 * struct ccs_pll_branch_fr - CCS PLL configuration (front) 33 * 34 * A single branch front-end of the CCS PLL tree. 35 * 36 * @pre_pll_clk_div: Pre-PLL clock divisor 37 * @pll_multiplier: PLL multiplier 38 * @pll_ip_clk_freq_hz: PLL input clock frequency 39 * @pll_op_clk_freq_hz: PLL output clock frequency 40 */ 41 struct ccs_pll_branch_fr { 42 uint16_t pre_pll_clk_div; 43 uint16_t pll_multiplier; 44 uint32_t pll_ip_clk_freq_hz; 45 uint32_t pll_op_clk_freq_hz; 46 }; 47 48 /** 49 * struct ccs_pll_branch_bk - CCS PLL configuration (back) 50 * 51 * A single branch back-end of the CCS PLL tree. 52 * 53 * @sys_clk_div: System clock divider 54 * @pix_clk_div: Pixel clock divider 55 * @sys_clk_freq_hz: System clock frequency 56 * @pix_clk_freq_hz: Pixel clock frequency 57 */ 58 struct ccs_pll_branch_bk { 59 uint16_t sys_clk_div; 60 uint16_t pix_clk_div; 61 uint32_t sys_clk_freq_hz; 62 uint32_t pix_clk_freq_hz; 63 }; 64 65 /** 66 * struct ccs_pll - Full CCS PLL configuration 67 * 68 * All information required to calculate CCS PLL configuration. 69 * 70 * @bus_type: Type of the data bus, CCS_PLL_BUS_TYPE_* (input) 71 * @op_lanes: Number of operational lanes (input) 72 * @vt_lanes: Number of video timing lanes (input) 73 * @csi2: CSI-2 related parameters 74 * @csi2.lanes: The number of the CSI-2 data lanes (input) 75 * @binning_vertical: Vertical binning factor (input) 76 * @binning_horizontal: Horizontal binning factor (input) 77 * @scale_m: Downscaling factor, M component, [16, max] (input) 78 * @scale_n: Downscaling factor, N component, typically 16 (input) 79 * @bits_per_pixel: Bits per pixel on the output data bus (input) 80 * @op_bits_per_lane: Number of bits per OP lane (input) 81 * @flags: CCS_PLL_FLAG_* (input) 82 * @link_freq: Chosen link frequency (input) 83 * @ext_clk_freq_hz: External clock frequency, i.e. the sensor's input clock 84 * (input) 85 * @vt_fr: Video timing front-end configuration (output) 86 * @vt_bk: Video timing back-end configuration (output) 87 * @op_bk: Operational timing back-end configuration (output) 88 * @pixel_rate_csi: Pixel rate on the output data bus (output) 89 * @pixel_rate_pixel_array: Nominal pixel rate in the sensor's pixel array 90 * (output) 91 */ 92 struct ccs_pll { 93 /* input values */ 94 uint8_t bus_type; 95 uint8_t op_lanes; 96 uint8_t vt_lanes; 97 struct { 98 uint8_t lanes; 99 } csi2; 100 uint8_t binning_horizontal; 101 uint8_t binning_vertical; 102 uint8_t scale_m; 103 uint8_t scale_n; 104 uint8_t bits_per_pixel; 105 uint8_t op_bits_per_lane; 106 uint16_t flags; 107 uint32_t link_freq; 108 uint32_t ext_clk_freq_hz; 109 110 /* output values */ 111 struct ccs_pll_branch_fr vt_fr; 112 struct ccs_pll_branch_bk vt_bk; 113 struct ccs_pll_branch_bk op_bk; 114 115 uint32_t pixel_rate_csi; 116 uint32_t pixel_rate_pixel_array; 117 }; 118 119 /** 120 * struct ccs_pll_branch_limits_fr - CCS PLL front-end limits 121 * 122 * @min_pre_pll_clk_div: Minimum pre-PLL clock divider 123 * @max_pre_pll_clk_div: Maximum pre-PLL clock divider 124 * @min_pll_ip_clk_freq_hz: Minimum PLL input clock frequency 125 * @max_pll_ip_clk_freq_hz: Maximum PLL input clock frequency 126 * @min_pll_multiplier: Minimum PLL multiplier 127 * @max_pll_multiplier: Maximum PLL multiplier 128 * @min_pll_op_clk_freq_hz: Minimum PLL output clock frequency 129 * @max_pll_op_clk_freq_hz: Maximum PLL output clock frequency 130 */ 131 struct ccs_pll_branch_limits_fr { 132 uint16_t min_pre_pll_clk_div; 133 uint16_t max_pre_pll_clk_div; 134 uint32_t min_pll_ip_clk_freq_hz; 135 uint32_t max_pll_ip_clk_freq_hz; 136 uint16_t min_pll_multiplier; 137 uint16_t max_pll_multiplier; 138 uint32_t min_pll_op_clk_freq_hz; 139 uint32_t max_pll_op_clk_freq_hz; 140 }; 141 142 /** 143 * struct ccs_pll_branch_limits_bk - CCS PLL back-end limits 144 * 145 * @min_sys_clk_div: Minimum system clock divider 146 * @max_sys_clk_div: Maximum system clock divider 147 * @min_sys_clk_freq_hz: Minimum system clock frequency 148 * @max_sys_clk_freq_hz: Maximum system clock frequency 149 * @min_pix_clk_div: Minimum pixel clock divider 150 * @max_pix_clk_div: Maximum pixel clock divider 151 * @min_pix_clk_freq_hz: Minimum pixel clock frequency 152 * @max_pix_clk_freq_hz: Maximum pixel clock frequency 153 */ 154 struct ccs_pll_branch_limits_bk { 155 uint16_t min_sys_clk_div; 156 uint16_t max_sys_clk_div; 157 uint32_t min_sys_clk_freq_hz; 158 uint32_t max_sys_clk_freq_hz; 159 uint16_t min_pix_clk_div; 160 uint16_t max_pix_clk_div; 161 uint32_t min_pix_clk_freq_hz; 162 uint32_t max_pix_clk_freq_hz; 163 }; 164 165 /** 166 * struct ccs_pll_limits - CCS PLL limits 167 * 168 * @min_ext_clk_freq_hz: Minimum external clock frequency 169 * @max_ext_clk_freq_hz: Maximum external clock frequency 170 * @vt_fr: Video timing front-end limits 171 * @vt_bk: Video timing back-end limits 172 * @op_bk: Operational timing back-end limits 173 * @min_line_length_pck_bin: Minimum line length in pixels, with binning 174 * @min_line_length_pck: Minimum line length in pixels without binning 175 */ 176 struct ccs_pll_limits { 177 /* Strict PLL limits */ 178 uint32_t min_ext_clk_freq_hz; 179 uint32_t max_ext_clk_freq_hz; 180 181 struct ccs_pll_branch_limits_fr vt_fr; 182 struct ccs_pll_branch_limits_bk vt_bk; 183 struct ccs_pll_branch_limits_bk op_bk; 184 185 /* Other relevant limits */ 186 uint32_t min_line_length_pck_bin; 187 uint32_t min_line_length_pck; 188 }; 189 190 struct device; 191 192 /** 193 * ccs_pll_calculate - Calculate CCS PLL configuration based on input parameters 194 * 195 * @dev: Device pointer, used for printing messages 196 * @limits: Limits specific to the sensor 197 * @pll: Given PLL configuration 198 * 199 * Calculate the CCS PLL configuration based on the limits as well as given 200 * device specific, system specific or user configured input data. 201 */ 202 int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *limits, 203 struct ccs_pll *pll); 204 205 #endif /* CCS_PLL_H */ 206