1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * drivers/media/i2c/ccs-pll.h 4 * 5 * Generic MIPI CCS/SMIA/SMIA++ PLL calculator 6 * 7 * Copyright (C) 2020 Intel Corporation 8 * Copyright (C) 2012 Nokia Corporation 9 * Contact: Sakari Ailus <sakari.ailus@linux.intel.com> 10 */ 11 12 #ifndef CCS_PLL_H 13 #define CCS_PLL_H 14 15 #include <linux/bits.h> 16 17 /* CSI-2 or CCP-2 */ 18 #define CCS_PLL_BUS_TYPE_CSI2_DPHY 0x00 19 #define CCS_PLL_BUS_TYPE_CSI2_CPHY 0x01 20 21 /* Old SMIA and implementation specific flags */ 22 /* op pix clock is for all lanes in total normally */ 23 #define CCS_PLL_FLAG_OP_PIX_CLOCK_PER_LANE BIT(0) 24 #define CCS_PLL_FLAG_NO_OP_CLOCKS BIT(1) 25 /* CCS PLL flags */ 26 #define CCS_PLL_FLAG_LANE_SPEED_MODEL BIT(2) 27 #define CCS_PLL_FLAG_LINK_DECOUPLED BIT(3) 28 #define CCS_PLL_FLAG_EXT_IP_PLL_DIVIDER BIT(4) 29 30 /** 31 * struct ccs_pll_branch_fr - CCS PLL configuration (front) 32 * 33 * A single branch front-end of the CCS PLL tree. 34 * 35 * @pre_pll_clk_div: Pre-PLL clock divisor 36 * @pll_multiplier: PLL multiplier 37 * @pll_ip_clk_freq_hz: PLL input clock frequency 38 * @pll_op_clk_freq_hz: PLL output clock frequency 39 */ 40 struct ccs_pll_branch_fr { 41 uint16_t pre_pll_clk_div; 42 uint16_t pll_multiplier; 43 uint32_t pll_ip_clk_freq_hz; 44 uint32_t pll_op_clk_freq_hz; 45 }; 46 47 /** 48 * struct ccs_pll_branch_bk - CCS PLL configuration (back) 49 * 50 * A single branch back-end of the CCS PLL tree. 51 * 52 * @sys_clk_div: System clock divider 53 * @pix_clk_div: Pixel clock divider 54 * @sys_clk_freq_hz: System clock frequency 55 * @pix_clk_freq_hz: Pixel clock frequency 56 */ 57 struct ccs_pll_branch_bk { 58 uint16_t sys_clk_div; 59 uint16_t pix_clk_div; 60 uint32_t sys_clk_freq_hz; 61 uint32_t pix_clk_freq_hz; 62 }; 63 64 /** 65 * struct ccs_pll - Full CCS PLL configuration 66 * 67 * All information required to calculate CCS PLL configuration. 68 * 69 * @bus_type: Type of the data bus, CCS_PLL_BUS_TYPE_* (input) 70 * @op_lanes: Number of operational lanes (input) 71 * @vt_lanes: Number of video timing lanes (input) 72 * @csi2: CSI-2 related parameters 73 * @csi2.lanes: The number of the CSI-2 data lanes (input) 74 * @binning_vertical: Vertical binning factor (input) 75 * @binning_horizontal: Horizontal binning factor (input) 76 * @scale_m: Downscaling factor, M component, [16, max] (input) 77 * @scale_n: Downscaling factor, N component, typically 16 (input) 78 * @bits_per_pixel: Bits per pixel on the output data bus (input) 79 * @flags: CCS_PLL_FLAG_* (input) 80 * @link_freq: Chosen link frequency (input) 81 * @ext_clk_freq_hz: External clock frequency, i.e. the sensor's input clock 82 * (input) 83 * @vt_fr: Video timing front-end configuration (output) 84 * @vt_bk: Video timing back-end configuration (output) 85 * @op_bk: Operational timing back-end configuration (output) 86 * @pixel_rate_csi: Pixel rate on the output data bus (output) 87 * @pixel_rate_pixel_array: Nominal pixel rate in the sensor's pixel array 88 * (output) 89 */ 90 struct ccs_pll { 91 /* input values */ 92 uint8_t bus_type; 93 uint8_t op_lanes; 94 uint8_t vt_lanes; 95 struct { 96 uint8_t lanes; 97 } csi2; 98 uint8_t binning_horizontal; 99 uint8_t binning_vertical; 100 uint8_t scale_m; 101 uint8_t scale_n; 102 uint8_t bits_per_pixel; 103 uint16_t flags; 104 uint32_t link_freq; 105 uint32_t ext_clk_freq_hz; 106 107 /* output values */ 108 struct ccs_pll_branch_fr vt_fr; 109 struct ccs_pll_branch_bk vt_bk; 110 struct ccs_pll_branch_bk op_bk; 111 112 uint32_t pixel_rate_csi; 113 uint32_t pixel_rate_pixel_array; 114 }; 115 116 /** 117 * struct ccs_pll_branch_limits_fr - CCS PLL front-end limits 118 * 119 * @min_pre_pll_clk_div: Minimum pre-PLL clock divider 120 * @max_pre_pll_clk_div: Maximum pre-PLL clock divider 121 * @min_pll_ip_clk_freq_hz: Minimum PLL input clock frequency 122 * @max_pll_ip_clk_freq_hz: Maximum PLL input clock frequency 123 * @min_pll_multiplier: Minimum PLL multiplier 124 * @max_pll_multiplier: Maximum PLL multiplier 125 * @min_pll_op_clk_freq_hz: Minimum PLL output clock frequency 126 * @max_pll_op_clk_freq_hz: Maximum PLL output clock frequency 127 */ 128 struct ccs_pll_branch_limits_fr { 129 uint16_t min_pre_pll_clk_div; 130 uint16_t max_pre_pll_clk_div; 131 uint32_t min_pll_ip_clk_freq_hz; 132 uint32_t max_pll_ip_clk_freq_hz; 133 uint16_t min_pll_multiplier; 134 uint16_t max_pll_multiplier; 135 uint32_t min_pll_op_clk_freq_hz; 136 uint32_t max_pll_op_clk_freq_hz; 137 }; 138 139 /** 140 * struct ccs_pll_branch_limits_bk - CCS PLL back-end limits 141 * 142 * @min_sys_clk_div: Minimum system clock divider 143 * @max_sys_clk_div: Maximum system clock divider 144 * @min_sys_clk_freq_hz: Minimum system clock frequency 145 * @max_sys_clk_freq_hz: Maximum system clock frequency 146 * @min_pix_clk_div: Minimum pixel clock divider 147 * @max_pix_clk_div: Maximum pixel clock divider 148 * @min_pix_clk_freq_hz: Minimum pixel clock frequency 149 * @max_pix_clk_freq_hz: Maximum pixel clock frequency 150 */ 151 struct ccs_pll_branch_limits_bk { 152 uint16_t min_sys_clk_div; 153 uint16_t max_sys_clk_div; 154 uint32_t min_sys_clk_freq_hz; 155 uint32_t max_sys_clk_freq_hz; 156 uint16_t min_pix_clk_div; 157 uint16_t max_pix_clk_div; 158 uint32_t min_pix_clk_freq_hz; 159 uint32_t max_pix_clk_freq_hz; 160 }; 161 162 /** 163 * struct ccs_pll_limits - CCS PLL limits 164 * 165 * @min_ext_clk_freq_hz: Minimum external clock frequency 166 * @max_ext_clk_freq_hz: Maximum external clock frequency 167 * @vt_fr: Video timing front-end limits 168 * @vt_bk: Video timing back-end limits 169 * @op_bk: Operational timing back-end limits 170 * @min_line_length_pck_bin: Minimum line length in pixels, with binning 171 * @min_line_length_pck: Minimum line length in pixels without binning 172 */ 173 struct ccs_pll_limits { 174 /* Strict PLL limits */ 175 uint32_t min_ext_clk_freq_hz; 176 uint32_t max_ext_clk_freq_hz; 177 178 struct ccs_pll_branch_limits_fr vt_fr; 179 struct ccs_pll_branch_limits_bk vt_bk; 180 struct ccs_pll_branch_limits_bk op_bk; 181 182 /* Other relevant limits */ 183 uint32_t min_line_length_pck_bin; 184 uint32_t min_line_length_pck; 185 }; 186 187 struct device; 188 189 /** 190 * ccs_pll_calculate - Calculate CCS PLL configuration based on input parameters 191 * 192 * @dev: Device pointer, used for printing messages 193 * @limits: Limits specific to the sensor 194 * @pll: Given PLL configuration 195 * 196 * Calculate the CCS PLL configuration based on the limits as well as given 197 * device specific, system specific or user configured input data. 198 */ 199 int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *limits, 200 struct ccs_pll *pll); 201 202 #endif /* CCS_PLL_H */ 203