1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * drivers/media/i2c/ccs-pll.h 4 * 5 * Generic MIPI CCS/SMIA/SMIA++ PLL calculator 6 * 7 * Copyright (C) 2020 Intel Corporation 8 * Copyright (C) 2012 Nokia Corporation 9 * Contact: Sakari Ailus <sakari.ailus@linux.intel.com> 10 */ 11 12 #ifndef CCS_PLL_H 13 #define CCS_PLL_H 14 15 #include <linux/bits.h> 16 17 /* CSI-2 or CCP-2 */ 18 #define CCS_PLL_BUS_TYPE_CSI2_DPHY 0x00 19 #define CCS_PLL_BUS_TYPE_CSI2_CPHY 0x01 20 21 /* Old SMIA and implementation specific flags */ 22 /* op pix clock is for all lanes in total normally */ 23 #define CCS_PLL_FLAG_OP_PIX_CLOCK_PER_LANE BIT(0) 24 #define CCS_PLL_FLAG_NO_OP_CLOCKS BIT(1) 25 /* CCS PLL flags */ 26 #define CCS_PLL_FLAG_LANE_SPEED_MODEL BIT(2) 27 #define CCS_PLL_FLAG_LINK_DECOUPLED BIT(3) 28 #define CCS_PLL_FLAG_EXT_IP_PLL_DIVIDER BIT(4) 29 #define CCS_PLL_FLAG_FLEXIBLE_OP_PIX_CLK_DIV BIT(5) 30 #define CCS_PLL_FLAG_FIFO_DERATING BIT(6) 31 #define CCS_PLL_FLAG_FIFO_OVERRATING BIT(7) 32 33 /** 34 * struct ccs_pll_branch_fr - CCS PLL configuration (front) 35 * 36 * A single branch front-end of the CCS PLL tree. 37 * 38 * @pre_pll_clk_div: Pre-PLL clock divisor 39 * @pll_multiplier: PLL multiplier 40 * @pll_ip_clk_freq_hz: PLL input clock frequency 41 * @pll_op_clk_freq_hz: PLL output clock frequency 42 */ 43 struct ccs_pll_branch_fr { 44 uint16_t pre_pll_clk_div; 45 uint16_t pll_multiplier; 46 uint32_t pll_ip_clk_freq_hz; 47 uint32_t pll_op_clk_freq_hz; 48 }; 49 50 /** 51 * struct ccs_pll_branch_bk - CCS PLL configuration (back) 52 * 53 * A single branch back-end of the CCS PLL tree. 54 * 55 * @sys_clk_div: System clock divider 56 * @pix_clk_div: Pixel clock divider 57 * @sys_clk_freq_hz: System clock frequency 58 * @pix_clk_freq_hz: Pixel clock frequency 59 */ 60 struct ccs_pll_branch_bk { 61 uint16_t sys_clk_div; 62 uint16_t pix_clk_div; 63 uint32_t sys_clk_freq_hz; 64 uint32_t pix_clk_freq_hz; 65 }; 66 67 /** 68 * struct ccs_pll - Full CCS PLL configuration 69 * 70 * All information required to calculate CCS PLL configuration. 71 * 72 * @bus_type: Type of the data bus, CCS_PLL_BUS_TYPE_* (input) 73 * @op_lanes: Number of operational lanes (input) 74 * @vt_lanes: Number of video timing lanes (input) 75 * @csi2: CSI-2 related parameters 76 * @csi2.lanes: The number of the CSI-2 data lanes (input) 77 * @binning_vertical: Vertical binning factor (input) 78 * @binning_horizontal: Horizontal binning factor (input) 79 * @scale_m: Downscaling factor, M component, [16, max] (input) 80 * @scale_n: Downscaling factor, N component, typically 16 (input) 81 * @bits_per_pixel: Bits per pixel on the output data bus (input) 82 * @op_bits_per_lane: Number of bits per OP lane (input) 83 * @flags: CCS_PLL_FLAG_* (input) 84 * @link_freq: Chosen link frequency (input) 85 * @ext_clk_freq_hz: External clock frequency, i.e. the sensor's input clock 86 * (input) 87 * @vt_fr: Video timing front-end configuration (output) 88 * @vt_bk: Video timing back-end configuration (output) 89 * @op_bk: Operational timing back-end configuration (output) 90 * @pixel_rate_csi: Pixel rate on the output data bus (output) 91 * @pixel_rate_pixel_array: Nominal pixel rate in the sensor's pixel array 92 * (output) 93 */ 94 struct ccs_pll { 95 /* input values */ 96 uint8_t bus_type; 97 uint8_t op_lanes; 98 uint8_t vt_lanes; 99 struct { 100 uint8_t lanes; 101 } csi2; 102 uint8_t binning_horizontal; 103 uint8_t binning_vertical; 104 uint8_t scale_m; 105 uint8_t scale_n; 106 uint8_t bits_per_pixel; 107 uint8_t op_bits_per_lane; 108 uint16_t flags; 109 uint32_t link_freq; 110 uint32_t ext_clk_freq_hz; 111 112 /* output values */ 113 struct ccs_pll_branch_fr vt_fr; 114 struct ccs_pll_branch_bk vt_bk; 115 struct ccs_pll_branch_bk op_bk; 116 117 uint32_t pixel_rate_csi; 118 uint32_t pixel_rate_pixel_array; 119 }; 120 121 /** 122 * struct ccs_pll_branch_limits_fr - CCS PLL front-end limits 123 * 124 * @min_pre_pll_clk_div: Minimum pre-PLL clock divider 125 * @max_pre_pll_clk_div: Maximum pre-PLL clock divider 126 * @min_pll_ip_clk_freq_hz: Minimum PLL input clock frequency 127 * @max_pll_ip_clk_freq_hz: Maximum PLL input clock frequency 128 * @min_pll_multiplier: Minimum PLL multiplier 129 * @max_pll_multiplier: Maximum PLL multiplier 130 * @min_pll_op_clk_freq_hz: Minimum PLL output clock frequency 131 * @max_pll_op_clk_freq_hz: Maximum PLL output clock frequency 132 */ 133 struct ccs_pll_branch_limits_fr { 134 uint16_t min_pre_pll_clk_div; 135 uint16_t max_pre_pll_clk_div; 136 uint32_t min_pll_ip_clk_freq_hz; 137 uint32_t max_pll_ip_clk_freq_hz; 138 uint16_t min_pll_multiplier; 139 uint16_t max_pll_multiplier; 140 uint32_t min_pll_op_clk_freq_hz; 141 uint32_t max_pll_op_clk_freq_hz; 142 }; 143 144 /** 145 * struct ccs_pll_branch_limits_bk - CCS PLL back-end limits 146 * 147 * @min_sys_clk_div: Minimum system clock divider 148 * @max_sys_clk_div: Maximum system clock divider 149 * @min_sys_clk_freq_hz: Minimum system clock frequency 150 * @max_sys_clk_freq_hz: Maximum system clock frequency 151 * @min_pix_clk_div: Minimum pixel clock divider 152 * @max_pix_clk_div: Maximum pixel clock divider 153 * @min_pix_clk_freq_hz: Minimum pixel clock frequency 154 * @max_pix_clk_freq_hz: Maximum pixel clock frequency 155 */ 156 struct ccs_pll_branch_limits_bk { 157 uint16_t min_sys_clk_div; 158 uint16_t max_sys_clk_div; 159 uint32_t min_sys_clk_freq_hz; 160 uint32_t max_sys_clk_freq_hz; 161 uint16_t min_pix_clk_div; 162 uint16_t max_pix_clk_div; 163 uint32_t min_pix_clk_freq_hz; 164 uint32_t max_pix_clk_freq_hz; 165 }; 166 167 /** 168 * struct ccs_pll_limits - CCS PLL limits 169 * 170 * @min_ext_clk_freq_hz: Minimum external clock frequency 171 * @max_ext_clk_freq_hz: Maximum external clock frequency 172 * @vt_fr: Video timing front-end limits 173 * @vt_bk: Video timing back-end limits 174 * @op_bk: Operational timing back-end limits 175 * @min_line_length_pck_bin: Minimum line length in pixels, with binning 176 * @min_line_length_pck: Minimum line length in pixels without binning 177 */ 178 struct ccs_pll_limits { 179 /* Strict PLL limits */ 180 uint32_t min_ext_clk_freq_hz; 181 uint32_t max_ext_clk_freq_hz; 182 183 struct ccs_pll_branch_limits_fr vt_fr; 184 struct ccs_pll_branch_limits_bk vt_bk; 185 struct ccs_pll_branch_limits_bk op_bk; 186 187 /* Other relevant limits */ 188 uint32_t min_line_length_pck_bin; 189 uint32_t min_line_length_pck; 190 }; 191 192 struct device; 193 194 /** 195 * ccs_pll_calculate - Calculate CCS PLL configuration based on input parameters 196 * 197 * @dev: Device pointer, used for printing messages 198 * @limits: Limits specific to the sensor 199 * @pll: Given PLL configuration 200 * 201 * Calculate the CCS PLL configuration based on the limits as well as given 202 * device specific, system specific or user configured input data. 203 */ 204 int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *limits, 205 struct ccs_pll *pll); 206 207 #endif /* CCS_PLL_H */ 208