19e05bbacSSakari Ailus /* SPDX-License-Identifier: GPL-2.0-only */ 29e05bbacSSakari Ailus /* 39e05bbacSSakari Ailus * drivers/media/i2c/ccs-pll.h 49e05bbacSSakari Ailus * 59e05bbacSSakari Ailus * Generic MIPI CCS/SMIA/SMIA++ PLL calculator 69e05bbacSSakari Ailus * 79e05bbacSSakari Ailus * Copyright (C) 2020 Intel Corporation 89e05bbacSSakari Ailus * Copyright (C) 2012 Nokia Corporation 9*7389d01cSSakari Ailus * Contact: Sakari Ailus <sakari.ailus@linux.intel.com> 109e05bbacSSakari Ailus */ 119e05bbacSSakari Ailus 129e05bbacSSakari Ailus #ifndef CCS_PLL_H 139e05bbacSSakari Ailus #define CCS_PLL_H 149e05bbacSSakari Ailus 159e05bbacSSakari Ailus /* CSI-2 or CCP-2 */ 169e05bbacSSakari Ailus #define CCS_PLL_BUS_TYPE_CSI2 0x00 179e05bbacSSakari Ailus #define CCS_PLL_BUS_TYPE_PARALLEL 0x01 189e05bbacSSakari Ailus 199e05bbacSSakari Ailus /* op pix clock is for all lanes in total normally */ 209e05bbacSSakari Ailus #define CCS_PLL_FLAG_OP_PIX_CLOCK_PER_LANE (1 << 0) 219e05bbacSSakari Ailus #define CCS_PLL_FLAG_NO_OP_CLOCKS (1 << 1) 229e05bbacSSakari Ailus 239e05bbacSSakari Ailus struct ccs_pll_branch { 249e05bbacSSakari Ailus uint16_t sys_clk_div; 259e05bbacSSakari Ailus uint16_t pix_clk_div; 269e05bbacSSakari Ailus uint32_t sys_clk_freq_hz; 279e05bbacSSakari Ailus uint32_t pix_clk_freq_hz; 289e05bbacSSakari Ailus }; 299e05bbacSSakari Ailus 309e05bbacSSakari Ailus struct ccs_pll { 319e05bbacSSakari Ailus /* input values */ 329e05bbacSSakari Ailus uint8_t bus_type; 339e05bbacSSakari Ailus union { 349e05bbacSSakari Ailus struct { 359e05bbacSSakari Ailus uint8_t lanes; 369e05bbacSSakari Ailus } csi2; 379e05bbacSSakari Ailus struct { 389e05bbacSSakari Ailus uint8_t bus_width; 399e05bbacSSakari Ailus } parallel; 409e05bbacSSakari Ailus }; 419e05bbacSSakari Ailus unsigned long flags; 429e05bbacSSakari Ailus uint8_t binning_horizontal; 439e05bbacSSakari Ailus uint8_t binning_vertical; 449e05bbacSSakari Ailus uint8_t scale_m; 459e05bbacSSakari Ailus uint8_t scale_n; 469e05bbacSSakari Ailus uint8_t bits_per_pixel; 479e05bbacSSakari Ailus uint32_t link_freq; 489e05bbacSSakari Ailus uint32_t ext_clk_freq_hz; 499e05bbacSSakari Ailus 509e05bbacSSakari Ailus /* output values */ 519e05bbacSSakari Ailus uint16_t pre_pll_clk_div; 529e05bbacSSakari Ailus uint16_t pll_multiplier; 539e05bbacSSakari Ailus uint32_t pll_ip_clk_freq_hz; 549e05bbacSSakari Ailus uint32_t pll_op_clk_freq_hz; 559e05bbacSSakari Ailus struct ccs_pll_branch vt; 569e05bbacSSakari Ailus struct ccs_pll_branch op; 579e05bbacSSakari Ailus 589e05bbacSSakari Ailus uint32_t pixel_rate_csi; 599e05bbacSSakari Ailus uint32_t pixel_rate_pixel_array; 609e05bbacSSakari Ailus }; 619e05bbacSSakari Ailus 629e05bbacSSakari Ailus struct ccs_pll_branch_limits { 639e05bbacSSakari Ailus uint16_t min_sys_clk_div; 649e05bbacSSakari Ailus uint16_t max_sys_clk_div; 659e05bbacSSakari Ailus uint32_t min_sys_clk_freq_hz; 669e05bbacSSakari Ailus uint32_t max_sys_clk_freq_hz; 679e05bbacSSakari Ailus uint16_t min_pix_clk_div; 689e05bbacSSakari Ailus uint16_t max_pix_clk_div; 699e05bbacSSakari Ailus uint32_t min_pix_clk_freq_hz; 709e05bbacSSakari Ailus uint32_t max_pix_clk_freq_hz; 719e05bbacSSakari Ailus }; 729e05bbacSSakari Ailus 739e05bbacSSakari Ailus struct ccs_pll_limits { 749e05bbacSSakari Ailus /* Strict PLL limits */ 759e05bbacSSakari Ailus uint32_t min_ext_clk_freq_hz; 769e05bbacSSakari Ailus uint32_t max_ext_clk_freq_hz; 779e05bbacSSakari Ailus uint16_t min_pre_pll_clk_div; 789e05bbacSSakari Ailus uint16_t max_pre_pll_clk_div; 799e05bbacSSakari Ailus uint32_t min_pll_ip_freq_hz; 809e05bbacSSakari Ailus uint32_t max_pll_ip_freq_hz; 819e05bbacSSakari Ailus uint16_t min_pll_multiplier; 829e05bbacSSakari Ailus uint16_t max_pll_multiplier; 839e05bbacSSakari Ailus uint32_t min_pll_op_freq_hz; 849e05bbacSSakari Ailus uint32_t max_pll_op_freq_hz; 859e05bbacSSakari Ailus 869e05bbacSSakari Ailus struct ccs_pll_branch_limits vt; 879e05bbacSSakari Ailus struct ccs_pll_branch_limits op; 889e05bbacSSakari Ailus 899e05bbacSSakari Ailus /* Other relevant limits */ 909e05bbacSSakari Ailus uint32_t min_line_length_pck_bin; 919e05bbacSSakari Ailus uint32_t min_line_length_pck; 929e05bbacSSakari Ailus }; 939e05bbacSSakari Ailus 949e05bbacSSakari Ailus struct device; 959e05bbacSSakari Ailus 969e05bbacSSakari Ailus int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *limits, 979e05bbacSSakari Ailus struct ccs_pll *pll); 989e05bbacSSakari Ailus 999e05bbacSSakari Ailus #endif /* CCS_PLL_H */ 100