xref: /openbmc/linux/drivers/media/i2c/adv7842.c (revision c93db682)
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * adv7842 - Analog Devices ADV7842 video decoder driver
4  *
5  * Copyright 2013 Cisco Systems, Inc. and/or its affiliates. All rights reserved.
6  */
7 
8 /*
9  * References (c = chapter, p = page):
10  * REF_01 - Analog devices, ADV7842,
11  *		Register Settings Recommendations, Rev. 1.9, April 2011
12  * REF_02 - Analog devices, Software User Guide, UG-206,
13  *		ADV7842 I2C Register Maps, Rev. 0, November 2010
14  * REF_03 - Analog devices, Hardware User Guide, UG-214,
15  *		ADV7842 Fast Switching 2:1 HDMI 1.4 Receiver with 3D-Comb
16  *		Decoder and Digitizer , Rev. 0, January 2011
17  */
18 
19 
20 #include <linux/kernel.h>
21 #include <linux/module.h>
22 #include <linux/slab.h>
23 #include <linux/i2c.h>
24 #include <linux/delay.h>
25 #include <linux/videodev2.h>
26 #include <linux/workqueue.h>
27 #include <linux/v4l2-dv-timings.h>
28 #include <linux/hdmi.h>
29 #include <media/cec.h>
30 #include <media/v4l2-device.h>
31 #include <media/v4l2-event.h>
32 #include <media/v4l2-ctrls.h>
33 #include <media/v4l2-dv-timings.h>
34 #include <media/i2c/adv7842.h>
35 
36 static int debug;
37 module_param(debug, int, 0644);
38 MODULE_PARM_DESC(debug, "debug level (0-2)");
39 
40 MODULE_DESCRIPTION("Analog Devices ADV7842 video decoder driver");
41 MODULE_AUTHOR("Hans Verkuil <hans.verkuil@cisco.com>");
42 MODULE_AUTHOR("Martin Bugge <marbugge@cisco.com>");
43 MODULE_LICENSE("GPL");
44 
45 /* ADV7842 system clock frequency */
46 #define ADV7842_fsc (28636360)
47 
48 #define ADV7842_RGB_OUT					(1 << 1)
49 
50 #define ADV7842_OP_FORMAT_SEL_8BIT			(0 << 0)
51 #define ADV7842_OP_FORMAT_SEL_10BIT			(1 << 0)
52 #define ADV7842_OP_FORMAT_SEL_12BIT			(2 << 0)
53 
54 #define ADV7842_OP_MODE_SEL_SDR_422			(0 << 5)
55 #define ADV7842_OP_MODE_SEL_DDR_422			(1 << 5)
56 #define ADV7842_OP_MODE_SEL_SDR_444			(2 << 5)
57 #define ADV7842_OP_MODE_SEL_DDR_444			(3 << 5)
58 #define ADV7842_OP_MODE_SEL_SDR_422_2X			(4 << 5)
59 #define ADV7842_OP_MODE_SEL_ADI_CM			(5 << 5)
60 
61 #define ADV7842_OP_CH_SEL_GBR				(0 << 5)
62 #define ADV7842_OP_CH_SEL_GRB				(1 << 5)
63 #define ADV7842_OP_CH_SEL_BGR				(2 << 5)
64 #define ADV7842_OP_CH_SEL_RGB				(3 << 5)
65 #define ADV7842_OP_CH_SEL_BRG				(4 << 5)
66 #define ADV7842_OP_CH_SEL_RBG				(5 << 5)
67 
68 #define ADV7842_OP_SWAP_CB_CR				(1 << 0)
69 
70 #define ADV7842_MAX_ADDRS (3)
71 
72 /*
73 **********************************************************************
74 *
75 *  Arrays with configuration parameters for the ADV7842
76 *
77 **********************************************************************
78 */
79 
80 struct adv7842_format_info {
81 	u32 code;
82 	u8 op_ch_sel;
83 	bool rgb_out;
84 	bool swap_cb_cr;
85 	u8 op_format_sel;
86 };
87 
88 struct adv7842_state {
89 	struct adv7842_platform_data pdata;
90 	struct v4l2_subdev sd;
91 	struct media_pad pads[ADV7842_PAD_SOURCE + 1];
92 	struct v4l2_ctrl_handler hdl;
93 	enum adv7842_mode mode;
94 	struct v4l2_dv_timings timings;
95 	enum adv7842_vid_std_select vid_std_select;
96 
97 	const struct adv7842_format_info *format;
98 
99 	v4l2_std_id norm;
100 	struct {
101 		u8 edid[256];
102 		u32 blocks;
103 		u32 present;
104 	} hdmi_edid;
105 	struct {
106 		u8 edid[256];
107 		u32 blocks;
108 		u32 present;
109 	} vga_edid;
110 	struct v4l2_fract aspect_ratio;
111 	u32 rgb_quantization_range;
112 	bool is_cea_format;
113 	struct delayed_work delayed_work_enable_hotplug;
114 	bool restart_stdi_once;
115 	bool hdmi_port_a;
116 
117 	/* i2c clients */
118 	struct i2c_client *i2c_sdp_io;
119 	struct i2c_client *i2c_sdp;
120 	struct i2c_client *i2c_cp;
121 	struct i2c_client *i2c_vdp;
122 	struct i2c_client *i2c_afe;
123 	struct i2c_client *i2c_hdmi;
124 	struct i2c_client *i2c_repeater;
125 	struct i2c_client *i2c_edid;
126 	struct i2c_client *i2c_infoframe;
127 	struct i2c_client *i2c_cec;
128 	struct i2c_client *i2c_avlink;
129 
130 	/* controls */
131 	struct v4l2_ctrl *detect_tx_5v_ctrl;
132 	struct v4l2_ctrl *analog_sampling_phase_ctrl;
133 	struct v4l2_ctrl *free_run_color_ctrl_manual;
134 	struct v4l2_ctrl *free_run_color_ctrl;
135 	struct v4l2_ctrl *rgb_quantization_range_ctrl;
136 
137 	struct cec_adapter *cec_adap;
138 	u8   cec_addr[ADV7842_MAX_ADDRS];
139 	u8   cec_valid_addrs;
140 	bool cec_enabled_adap;
141 };
142 
143 /* Unsupported timings. This device cannot support 720p30. */
144 static const struct v4l2_dv_timings adv7842_timings_exceptions[] = {
145 	V4L2_DV_BT_CEA_1280X720P30,
146 	{ }
147 };
148 
149 static bool adv7842_check_dv_timings(const struct v4l2_dv_timings *t, void *hdl)
150 {
151 	int i;
152 
153 	for (i = 0; adv7842_timings_exceptions[i].bt.width; i++)
154 		if (v4l2_match_dv_timings(t, adv7842_timings_exceptions + i, 0, false))
155 			return false;
156 	return true;
157 }
158 
159 struct adv7842_video_standards {
160 	struct v4l2_dv_timings timings;
161 	u8 vid_std;
162 	u8 v_freq;
163 };
164 
165 /* sorted by number of lines */
166 static const struct adv7842_video_standards adv7842_prim_mode_comp[] = {
167 	/* { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 }, TODO flickering */
168 	{ V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 },
169 	{ V4L2_DV_BT_CEA_1280X720P50, 0x19, 0x01 },
170 	{ V4L2_DV_BT_CEA_1280X720P60, 0x19, 0x00 },
171 	{ V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 },
172 	{ V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 },
173 	{ V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 },
174 	{ V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 },
175 	{ V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 },
176 	/* TODO add 1920x1080P60_RB (CVT timing) */
177 	{ },
178 };
179 
180 /* sorted by number of lines */
181 static const struct adv7842_video_standards adv7842_prim_mode_gr[] = {
182 	{ V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 },
183 	{ V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 },
184 	{ V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 },
185 	{ V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 },
186 	{ V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 },
187 	{ V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 },
188 	{ V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 },
189 	{ V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 },
190 	{ V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 },
191 	{ V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 },
192 	{ V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 },
193 	{ V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 },
194 	{ V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 },
195 	{ V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 },
196 	{ V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 },
197 	{ V4L2_DV_BT_DMT_1360X768P60, 0x12, 0x00 },
198 	{ V4L2_DV_BT_DMT_1366X768P60, 0x13, 0x00 },
199 	{ V4L2_DV_BT_DMT_1400X1050P60, 0x14, 0x00 },
200 	{ V4L2_DV_BT_DMT_1400X1050P75, 0x15, 0x00 },
201 	{ V4L2_DV_BT_DMT_1600X1200P60, 0x16, 0x00 }, /* TODO not tested */
202 	/* TODO add 1600X1200P60_RB (not a DMT timing) */
203 	{ V4L2_DV_BT_DMT_1680X1050P60, 0x18, 0x00 },
204 	{ V4L2_DV_BT_DMT_1920X1200P60_RB, 0x19, 0x00 }, /* TODO not tested */
205 	{ },
206 };
207 
208 /* sorted by number of lines */
209 static const struct adv7842_video_standards adv7842_prim_mode_hdmi_comp[] = {
210 	{ V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 },
211 	{ V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 },
212 	{ V4L2_DV_BT_CEA_1280X720P50, 0x13, 0x01 },
213 	{ V4L2_DV_BT_CEA_1280X720P60, 0x13, 0x00 },
214 	{ V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 },
215 	{ V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 },
216 	{ V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 },
217 	{ V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 },
218 	{ V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 },
219 	{ },
220 };
221 
222 /* sorted by number of lines */
223 static const struct adv7842_video_standards adv7842_prim_mode_hdmi_gr[] = {
224 	{ V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 },
225 	{ V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 },
226 	{ V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 },
227 	{ V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 },
228 	{ V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 },
229 	{ V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 },
230 	{ V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 },
231 	{ V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 },
232 	{ V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 },
233 	{ V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 },
234 	{ V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 },
235 	{ V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 },
236 	{ V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 },
237 	{ V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 },
238 	{ V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 },
239 	{ },
240 };
241 
242 static const struct v4l2_event adv7842_ev_fmt = {
243 	.type = V4L2_EVENT_SOURCE_CHANGE,
244 	.u.src_change.changes = V4L2_EVENT_SRC_CH_RESOLUTION,
245 };
246 
247 /* ----------------------------------------------------------------------- */
248 
249 static inline struct adv7842_state *to_state(struct v4l2_subdev *sd)
250 {
251 	return container_of(sd, struct adv7842_state, sd);
252 }
253 
254 static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
255 {
256 	return &container_of(ctrl->handler, struct adv7842_state, hdl)->sd;
257 }
258 
259 static inline unsigned hblanking(const struct v4l2_bt_timings *t)
260 {
261 	return V4L2_DV_BT_BLANKING_WIDTH(t);
262 }
263 
264 static inline unsigned htotal(const struct v4l2_bt_timings *t)
265 {
266 	return V4L2_DV_BT_FRAME_WIDTH(t);
267 }
268 
269 static inline unsigned vblanking(const struct v4l2_bt_timings *t)
270 {
271 	return V4L2_DV_BT_BLANKING_HEIGHT(t);
272 }
273 
274 static inline unsigned vtotal(const struct v4l2_bt_timings *t)
275 {
276 	return V4L2_DV_BT_FRAME_HEIGHT(t);
277 }
278 
279 
280 /* ----------------------------------------------------------------------- */
281 
282 static s32 adv_smbus_read_byte_data_check(struct i2c_client *client,
283 					  u8 command, bool check)
284 {
285 	union i2c_smbus_data data;
286 
287 	if (!i2c_smbus_xfer(client->adapter, client->addr, client->flags,
288 			    I2C_SMBUS_READ, command,
289 			    I2C_SMBUS_BYTE_DATA, &data))
290 		return data.byte;
291 	if (check)
292 		v4l_err(client, "error reading %02x, %02x\n",
293 			client->addr, command);
294 	return -EIO;
295 }
296 
297 static s32 adv_smbus_read_byte_data(struct i2c_client *client, u8 command)
298 {
299 	int i;
300 
301 	for (i = 0; i < 3; i++) {
302 		int ret = adv_smbus_read_byte_data_check(client, command, true);
303 
304 		if (ret >= 0) {
305 			if (i)
306 				v4l_err(client, "read ok after %d retries\n", i);
307 			return ret;
308 		}
309 	}
310 	v4l_err(client, "read failed\n");
311 	return -EIO;
312 }
313 
314 static s32 adv_smbus_write_byte_data(struct i2c_client *client,
315 				     u8 command, u8 value)
316 {
317 	union i2c_smbus_data data;
318 	int err;
319 	int i;
320 
321 	data.byte = value;
322 	for (i = 0; i < 3; i++) {
323 		err = i2c_smbus_xfer(client->adapter, client->addr,
324 				     client->flags,
325 				     I2C_SMBUS_WRITE, command,
326 				     I2C_SMBUS_BYTE_DATA, &data);
327 		if (!err)
328 			break;
329 	}
330 	if (err < 0)
331 		v4l_err(client, "error writing %02x, %02x, %02x\n",
332 			client->addr, command, value);
333 	return err;
334 }
335 
336 static void adv_smbus_write_byte_no_check(struct i2c_client *client,
337 					  u8 command, u8 value)
338 {
339 	union i2c_smbus_data data;
340 	data.byte = value;
341 
342 	i2c_smbus_xfer(client->adapter, client->addr,
343 		       client->flags,
344 		       I2C_SMBUS_WRITE, command,
345 		       I2C_SMBUS_BYTE_DATA, &data);
346 }
347 
348 /* ----------------------------------------------------------------------- */
349 
350 static inline int io_read(struct v4l2_subdev *sd, u8 reg)
351 {
352 	struct i2c_client *client = v4l2_get_subdevdata(sd);
353 
354 	return adv_smbus_read_byte_data(client, reg);
355 }
356 
357 static inline int io_write(struct v4l2_subdev *sd, u8 reg, u8 val)
358 {
359 	struct i2c_client *client = v4l2_get_subdevdata(sd);
360 
361 	return adv_smbus_write_byte_data(client, reg, val);
362 }
363 
364 static inline int io_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
365 {
366 	return io_write(sd, reg, (io_read(sd, reg) & mask) | val);
367 }
368 
369 static inline int io_write_clr_set(struct v4l2_subdev *sd,
370 				   u8 reg, u8 mask, u8 val)
371 {
372 	return io_write(sd, reg, (io_read(sd, reg) & ~mask) | val);
373 }
374 
375 static inline int avlink_read(struct v4l2_subdev *sd, u8 reg)
376 {
377 	struct adv7842_state *state = to_state(sd);
378 
379 	return adv_smbus_read_byte_data(state->i2c_avlink, reg);
380 }
381 
382 static inline int avlink_write(struct v4l2_subdev *sd, u8 reg, u8 val)
383 {
384 	struct adv7842_state *state = to_state(sd);
385 
386 	return adv_smbus_write_byte_data(state->i2c_avlink, reg, val);
387 }
388 
389 static inline int cec_read(struct v4l2_subdev *sd, u8 reg)
390 {
391 	struct adv7842_state *state = to_state(sd);
392 
393 	return adv_smbus_read_byte_data(state->i2c_cec, reg);
394 }
395 
396 static inline int cec_write(struct v4l2_subdev *sd, u8 reg, u8 val)
397 {
398 	struct adv7842_state *state = to_state(sd);
399 
400 	return adv_smbus_write_byte_data(state->i2c_cec, reg, val);
401 }
402 
403 static inline int cec_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
404 {
405 	return cec_write(sd, reg, (cec_read(sd, reg) & ~mask) | val);
406 }
407 
408 static inline int infoframe_read(struct v4l2_subdev *sd, u8 reg)
409 {
410 	struct adv7842_state *state = to_state(sd);
411 
412 	return adv_smbus_read_byte_data(state->i2c_infoframe, reg);
413 }
414 
415 static inline int infoframe_write(struct v4l2_subdev *sd, u8 reg, u8 val)
416 {
417 	struct adv7842_state *state = to_state(sd);
418 
419 	return adv_smbus_write_byte_data(state->i2c_infoframe, reg, val);
420 }
421 
422 static inline int sdp_io_read(struct v4l2_subdev *sd, u8 reg)
423 {
424 	struct adv7842_state *state = to_state(sd);
425 
426 	return adv_smbus_read_byte_data(state->i2c_sdp_io, reg);
427 }
428 
429 static inline int sdp_io_write(struct v4l2_subdev *sd, u8 reg, u8 val)
430 {
431 	struct adv7842_state *state = to_state(sd);
432 
433 	return adv_smbus_write_byte_data(state->i2c_sdp_io, reg, val);
434 }
435 
436 static inline int sdp_io_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
437 {
438 	return sdp_io_write(sd, reg, (sdp_io_read(sd, reg) & mask) | val);
439 }
440 
441 static inline int sdp_read(struct v4l2_subdev *sd, u8 reg)
442 {
443 	struct adv7842_state *state = to_state(sd);
444 
445 	return adv_smbus_read_byte_data(state->i2c_sdp, reg);
446 }
447 
448 static inline int sdp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
449 {
450 	struct adv7842_state *state = to_state(sd);
451 
452 	return adv_smbus_write_byte_data(state->i2c_sdp, reg, val);
453 }
454 
455 static inline int sdp_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
456 {
457 	return sdp_write(sd, reg, (sdp_read(sd, reg) & mask) | val);
458 }
459 
460 static inline int afe_read(struct v4l2_subdev *sd, u8 reg)
461 {
462 	struct adv7842_state *state = to_state(sd);
463 
464 	return adv_smbus_read_byte_data(state->i2c_afe, reg);
465 }
466 
467 static inline int afe_write(struct v4l2_subdev *sd, u8 reg, u8 val)
468 {
469 	struct adv7842_state *state = to_state(sd);
470 
471 	return adv_smbus_write_byte_data(state->i2c_afe, reg, val);
472 }
473 
474 static inline int afe_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
475 {
476 	return afe_write(sd, reg, (afe_read(sd, reg) & mask) | val);
477 }
478 
479 static inline int rep_read(struct v4l2_subdev *sd, u8 reg)
480 {
481 	struct adv7842_state *state = to_state(sd);
482 
483 	return adv_smbus_read_byte_data(state->i2c_repeater, reg);
484 }
485 
486 static inline int rep_write(struct v4l2_subdev *sd, u8 reg, u8 val)
487 {
488 	struct adv7842_state *state = to_state(sd);
489 
490 	return adv_smbus_write_byte_data(state->i2c_repeater, reg, val);
491 }
492 
493 static inline int rep_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
494 {
495 	return rep_write(sd, reg, (rep_read(sd, reg) & mask) | val);
496 }
497 
498 static inline int edid_read(struct v4l2_subdev *sd, u8 reg)
499 {
500 	struct adv7842_state *state = to_state(sd);
501 
502 	return adv_smbus_read_byte_data(state->i2c_edid, reg);
503 }
504 
505 static inline int edid_write(struct v4l2_subdev *sd, u8 reg, u8 val)
506 {
507 	struct adv7842_state *state = to_state(sd);
508 
509 	return adv_smbus_write_byte_data(state->i2c_edid, reg, val);
510 }
511 
512 static inline int hdmi_read(struct v4l2_subdev *sd, u8 reg)
513 {
514 	struct adv7842_state *state = to_state(sd);
515 
516 	return adv_smbus_read_byte_data(state->i2c_hdmi, reg);
517 }
518 
519 static inline int hdmi_write(struct v4l2_subdev *sd, u8 reg, u8 val)
520 {
521 	struct adv7842_state *state = to_state(sd);
522 
523 	return adv_smbus_write_byte_data(state->i2c_hdmi, reg, val);
524 }
525 
526 static inline int hdmi_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
527 {
528 	return hdmi_write(sd, reg, (hdmi_read(sd, reg) & mask) | val);
529 }
530 
531 static inline int cp_read(struct v4l2_subdev *sd, u8 reg)
532 {
533 	struct adv7842_state *state = to_state(sd);
534 
535 	return adv_smbus_read_byte_data(state->i2c_cp, reg);
536 }
537 
538 static inline int cp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
539 {
540 	struct adv7842_state *state = to_state(sd);
541 
542 	return adv_smbus_write_byte_data(state->i2c_cp, reg, val);
543 }
544 
545 static inline int cp_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
546 {
547 	return cp_write(sd, reg, (cp_read(sd, reg) & mask) | val);
548 }
549 
550 static inline int vdp_read(struct v4l2_subdev *sd, u8 reg)
551 {
552 	struct adv7842_state *state = to_state(sd);
553 
554 	return adv_smbus_read_byte_data(state->i2c_vdp, reg);
555 }
556 
557 static inline int vdp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
558 {
559 	struct adv7842_state *state = to_state(sd);
560 
561 	return adv_smbus_write_byte_data(state->i2c_vdp, reg, val);
562 }
563 
564 static void main_reset(struct v4l2_subdev *sd)
565 {
566 	struct i2c_client *client = v4l2_get_subdevdata(sd);
567 
568 	v4l2_dbg(1, debug, sd, "%s:\n", __func__);
569 
570 	adv_smbus_write_byte_no_check(client, 0xff, 0x80);
571 
572 	mdelay(5);
573 }
574 
575 /* -----------------------------------------------------------------------------
576  * Format helpers
577  */
578 
579 static const struct adv7842_format_info adv7842_formats[] = {
580 	{ MEDIA_BUS_FMT_RGB888_1X24, ADV7842_OP_CH_SEL_RGB, true, false,
581 	  ADV7842_OP_MODE_SEL_SDR_444 | ADV7842_OP_FORMAT_SEL_8BIT },
582 	{ MEDIA_BUS_FMT_YUYV8_2X8, ADV7842_OP_CH_SEL_RGB, false, false,
583 	  ADV7842_OP_MODE_SEL_SDR_422 | ADV7842_OP_FORMAT_SEL_8BIT },
584 	{ MEDIA_BUS_FMT_YVYU8_2X8, ADV7842_OP_CH_SEL_RGB, false, true,
585 	  ADV7842_OP_MODE_SEL_SDR_422 | ADV7842_OP_FORMAT_SEL_8BIT },
586 	{ MEDIA_BUS_FMT_YUYV10_2X10, ADV7842_OP_CH_SEL_RGB, false, false,
587 	  ADV7842_OP_MODE_SEL_SDR_422 | ADV7842_OP_FORMAT_SEL_10BIT },
588 	{ MEDIA_BUS_FMT_YVYU10_2X10, ADV7842_OP_CH_SEL_RGB, false, true,
589 	  ADV7842_OP_MODE_SEL_SDR_422 | ADV7842_OP_FORMAT_SEL_10BIT },
590 	{ MEDIA_BUS_FMT_YUYV12_2X12, ADV7842_OP_CH_SEL_RGB, false, false,
591 	  ADV7842_OP_MODE_SEL_SDR_422 | ADV7842_OP_FORMAT_SEL_12BIT },
592 	{ MEDIA_BUS_FMT_YVYU12_2X12, ADV7842_OP_CH_SEL_RGB, false, true,
593 	  ADV7842_OP_MODE_SEL_SDR_422 | ADV7842_OP_FORMAT_SEL_12BIT },
594 	{ MEDIA_BUS_FMT_UYVY8_1X16, ADV7842_OP_CH_SEL_RBG, false, false,
595 	  ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_8BIT },
596 	{ MEDIA_BUS_FMT_VYUY8_1X16, ADV7842_OP_CH_SEL_RBG, false, true,
597 	  ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_8BIT },
598 	{ MEDIA_BUS_FMT_YUYV8_1X16, ADV7842_OP_CH_SEL_RGB, false, false,
599 	  ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_8BIT },
600 	{ MEDIA_BUS_FMT_YVYU8_1X16, ADV7842_OP_CH_SEL_RGB, false, true,
601 	  ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_8BIT },
602 	{ MEDIA_BUS_FMT_UYVY10_1X20, ADV7842_OP_CH_SEL_RBG, false, false,
603 	  ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_10BIT },
604 	{ MEDIA_BUS_FMT_VYUY10_1X20, ADV7842_OP_CH_SEL_RBG, false, true,
605 	  ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_10BIT },
606 	{ MEDIA_BUS_FMT_YUYV10_1X20, ADV7842_OP_CH_SEL_RGB, false, false,
607 	  ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_10BIT },
608 	{ MEDIA_BUS_FMT_YVYU10_1X20, ADV7842_OP_CH_SEL_RGB, false, true,
609 	  ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_10BIT },
610 	{ MEDIA_BUS_FMT_UYVY12_1X24, ADV7842_OP_CH_SEL_RBG, false, false,
611 	  ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_12BIT },
612 	{ MEDIA_BUS_FMT_VYUY12_1X24, ADV7842_OP_CH_SEL_RBG, false, true,
613 	  ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_12BIT },
614 	{ MEDIA_BUS_FMT_YUYV12_1X24, ADV7842_OP_CH_SEL_RGB, false, false,
615 	  ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_12BIT },
616 	{ MEDIA_BUS_FMT_YVYU12_1X24, ADV7842_OP_CH_SEL_RGB, false, true,
617 	  ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_12BIT },
618 };
619 
620 static const struct adv7842_format_info *
621 adv7842_format_info(struct adv7842_state *state, u32 code)
622 {
623 	unsigned int i;
624 
625 	for (i = 0; i < ARRAY_SIZE(adv7842_formats); ++i) {
626 		if (adv7842_formats[i].code == code)
627 			return &adv7842_formats[i];
628 	}
629 
630 	return NULL;
631 }
632 
633 /* ----------------------------------------------------------------------- */
634 
635 static inline bool is_analog_input(struct v4l2_subdev *sd)
636 {
637 	struct adv7842_state *state = to_state(sd);
638 
639 	return ((state->mode == ADV7842_MODE_RGB) ||
640 		(state->mode == ADV7842_MODE_COMP));
641 }
642 
643 static inline bool is_digital_input(struct v4l2_subdev *sd)
644 {
645 	struct adv7842_state *state = to_state(sd);
646 
647 	return state->mode == ADV7842_MODE_HDMI;
648 }
649 
650 static const struct v4l2_dv_timings_cap adv7842_timings_cap_analog = {
651 	.type = V4L2_DV_BT_656_1120,
652 	/* keep this initialization for compatibility with GCC < 4.4.6 */
653 	.reserved = { 0 },
654 	V4L2_INIT_BT_TIMINGS(640, 1920, 350, 1200, 25000000, 170000000,
655 		V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
656 			V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT,
657 		V4L2_DV_BT_CAP_PROGRESSIVE | V4L2_DV_BT_CAP_REDUCED_BLANKING |
658 			V4L2_DV_BT_CAP_CUSTOM)
659 };
660 
661 static const struct v4l2_dv_timings_cap adv7842_timings_cap_digital = {
662 	.type = V4L2_DV_BT_656_1120,
663 	/* keep this initialization for compatibility with GCC < 4.4.6 */
664 	.reserved = { 0 },
665 	V4L2_INIT_BT_TIMINGS(640, 1920, 350, 1200, 25000000, 225000000,
666 		V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
667 			V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT,
668 		V4L2_DV_BT_CAP_PROGRESSIVE | V4L2_DV_BT_CAP_REDUCED_BLANKING |
669 			V4L2_DV_BT_CAP_CUSTOM)
670 };
671 
672 static inline const struct v4l2_dv_timings_cap *
673 adv7842_get_dv_timings_cap(struct v4l2_subdev *sd)
674 {
675 	return is_digital_input(sd) ? &adv7842_timings_cap_digital :
676 				      &adv7842_timings_cap_analog;
677 }
678 
679 /* ----------------------------------------------------------------------- */
680 
681 static u16 adv7842_read_cable_det(struct v4l2_subdev *sd)
682 {
683 	u8 reg = io_read(sd, 0x6f);
684 	u16 val = 0;
685 
686 	if (reg & 0x02)
687 		val |= 1; /* port A */
688 	if (reg & 0x01)
689 		val |= 2; /* port B */
690 	return val;
691 }
692 
693 static void adv7842_delayed_work_enable_hotplug(struct work_struct *work)
694 {
695 	struct delayed_work *dwork = to_delayed_work(work);
696 	struct adv7842_state *state = container_of(dwork,
697 			struct adv7842_state, delayed_work_enable_hotplug);
698 	struct v4l2_subdev *sd = &state->sd;
699 	int present = state->hdmi_edid.present;
700 	u8 mask = 0;
701 
702 	v4l2_dbg(2, debug, sd, "%s: enable hotplug on ports: 0x%x\n",
703 			__func__, present);
704 
705 	if (present & (0x04 << ADV7842_EDID_PORT_A))
706 		mask |= 0x20;
707 	if (present & (0x04 << ADV7842_EDID_PORT_B))
708 		mask |= 0x10;
709 	io_write_and_or(sd, 0x20, 0xcf, mask);
710 }
711 
712 static int edid_write_vga_segment(struct v4l2_subdev *sd)
713 {
714 	struct i2c_client *client = v4l2_get_subdevdata(sd);
715 	struct adv7842_state *state = to_state(sd);
716 	const u8 *edid = state->vga_edid.edid;
717 	u32 blocks = state->vga_edid.blocks;
718 	int err = 0;
719 	int i;
720 
721 	v4l2_dbg(2, debug, sd, "%s: write EDID on VGA port\n", __func__);
722 
723 	/* HPA disable on port A and B */
724 	io_write_and_or(sd, 0x20, 0xcf, 0x00);
725 
726 	/* Disable I2C access to internal EDID ram from VGA DDC port */
727 	rep_write_and_or(sd, 0x7f, 0x7f, 0x00);
728 
729 	/* edid segment pointer '1' for VGA port */
730 	rep_write_and_or(sd, 0x77, 0xef, 0x10);
731 
732 	for (i = 0; !err && i < blocks * 128; i += I2C_SMBUS_BLOCK_MAX)
733 		err = i2c_smbus_write_i2c_block_data(state->i2c_edid, i,
734 						     I2C_SMBUS_BLOCK_MAX,
735 						     edid + i);
736 	if (err)
737 		return err;
738 
739 	/* Calculates the checksums and enables I2C access
740 	 * to internal EDID ram from VGA DDC port.
741 	 */
742 	rep_write_and_or(sd, 0x7f, 0x7f, 0x80);
743 
744 	for (i = 0; i < 1000; i++) {
745 		if (rep_read(sd, 0x79) & 0x20)
746 			break;
747 		mdelay(1);
748 	}
749 	if (i == 1000) {
750 		v4l_err(client, "error enabling edid on VGA port\n");
751 		return -EIO;
752 	}
753 
754 	/* enable hotplug after 200 ms */
755 	schedule_delayed_work(&state->delayed_work_enable_hotplug, HZ / 5);
756 
757 	return 0;
758 }
759 
760 static int edid_write_hdmi_segment(struct v4l2_subdev *sd, u8 port)
761 {
762 	struct i2c_client *client = v4l2_get_subdevdata(sd);
763 	struct adv7842_state *state = to_state(sd);
764 	const u8 *edid = state->hdmi_edid.edid;
765 	u32 blocks = state->hdmi_edid.blocks;
766 	int spa_loc;
767 	u16 pa, parent_pa;
768 	int err = 0;
769 	int i;
770 
771 	v4l2_dbg(2, debug, sd, "%s: write EDID on port %c\n",
772 			__func__, (port == ADV7842_EDID_PORT_A) ? 'A' : 'B');
773 
774 	/* HPA disable on port A and B */
775 	io_write_and_or(sd, 0x20, 0xcf, 0x00);
776 
777 	/* Disable I2C access to internal EDID ram from HDMI DDC ports */
778 	rep_write_and_or(sd, 0x77, 0xf3, 0x00);
779 
780 	if (!state->hdmi_edid.present) {
781 		cec_phys_addr_invalidate(state->cec_adap);
782 		return 0;
783 	}
784 
785 	pa = v4l2_get_edid_phys_addr(edid, blocks * 128, &spa_loc);
786 	err = v4l2_phys_addr_validate(pa, &parent_pa, NULL);
787 	if (err)
788 		return err;
789 
790 	if (!spa_loc) {
791 		/*
792 		 * There is no SPA, so just set spa_loc to 128 and pa to whatever
793 		 * data is there.
794 		 */
795 		spa_loc = 128;
796 		pa = (edid[spa_loc] << 8) | edid[spa_loc + 1];
797 	}
798 
799 	/* edid segment pointer '0' for HDMI ports */
800 	rep_write_and_or(sd, 0x77, 0xef, 0x00);
801 
802 	for (i = 0; !err && i < blocks * 128; i += I2C_SMBUS_BLOCK_MAX)
803 		err = i2c_smbus_write_i2c_block_data(state->i2c_edid, i,
804 						     I2C_SMBUS_BLOCK_MAX, edid + i);
805 	if (err)
806 		return err;
807 
808 	if (port == ADV7842_EDID_PORT_A) {
809 		rep_write(sd, 0x72, pa >> 8);
810 		rep_write(sd, 0x73, pa & 0xff);
811 	} else {
812 		rep_write(sd, 0x74, pa >> 8);
813 		rep_write(sd, 0x75, pa & 0xff);
814 	}
815 	rep_write(sd, 0x76, spa_loc & 0xff);
816 	rep_write_and_or(sd, 0x77, 0xbf, (spa_loc >> 2) & 0x40);
817 
818 	/* Calculates the checksums and enables I2C access to internal
819 	 * EDID ram from HDMI DDC ports
820 	 */
821 	rep_write_and_or(sd, 0x77, 0xf3, state->hdmi_edid.present);
822 
823 	for (i = 0; i < 1000; i++) {
824 		if (rep_read(sd, 0x7d) & state->hdmi_edid.present)
825 			break;
826 		mdelay(1);
827 	}
828 	if (i == 1000) {
829 		v4l_err(client, "error enabling edid on port %c\n",
830 				(port == ADV7842_EDID_PORT_A) ? 'A' : 'B');
831 		return -EIO;
832 	}
833 	cec_s_phys_addr(state->cec_adap, parent_pa, false);
834 
835 	/* enable hotplug after 200 ms */
836 	schedule_delayed_work(&state->delayed_work_enable_hotplug, HZ / 5);
837 
838 	return 0;
839 }
840 
841 /* ----------------------------------------------------------------------- */
842 
843 #ifdef CONFIG_VIDEO_ADV_DEBUG
844 static void adv7842_inv_register(struct v4l2_subdev *sd)
845 {
846 	v4l2_info(sd, "0x000-0x0ff: IO Map\n");
847 	v4l2_info(sd, "0x100-0x1ff: AVLink Map\n");
848 	v4l2_info(sd, "0x200-0x2ff: CEC Map\n");
849 	v4l2_info(sd, "0x300-0x3ff: InfoFrame Map\n");
850 	v4l2_info(sd, "0x400-0x4ff: SDP_IO Map\n");
851 	v4l2_info(sd, "0x500-0x5ff: SDP Map\n");
852 	v4l2_info(sd, "0x600-0x6ff: AFE Map\n");
853 	v4l2_info(sd, "0x700-0x7ff: Repeater Map\n");
854 	v4l2_info(sd, "0x800-0x8ff: EDID Map\n");
855 	v4l2_info(sd, "0x900-0x9ff: HDMI Map\n");
856 	v4l2_info(sd, "0xa00-0xaff: CP Map\n");
857 	v4l2_info(sd, "0xb00-0xbff: VDP Map\n");
858 }
859 
860 static int adv7842_g_register(struct v4l2_subdev *sd,
861 			      struct v4l2_dbg_register *reg)
862 {
863 	reg->size = 1;
864 	switch (reg->reg >> 8) {
865 	case 0:
866 		reg->val = io_read(sd, reg->reg & 0xff);
867 		break;
868 	case 1:
869 		reg->val = avlink_read(sd, reg->reg & 0xff);
870 		break;
871 	case 2:
872 		reg->val = cec_read(sd, reg->reg & 0xff);
873 		break;
874 	case 3:
875 		reg->val = infoframe_read(sd, reg->reg & 0xff);
876 		break;
877 	case 4:
878 		reg->val = sdp_io_read(sd, reg->reg & 0xff);
879 		break;
880 	case 5:
881 		reg->val = sdp_read(sd, reg->reg & 0xff);
882 		break;
883 	case 6:
884 		reg->val = afe_read(sd, reg->reg & 0xff);
885 		break;
886 	case 7:
887 		reg->val = rep_read(sd, reg->reg & 0xff);
888 		break;
889 	case 8:
890 		reg->val = edid_read(sd, reg->reg & 0xff);
891 		break;
892 	case 9:
893 		reg->val = hdmi_read(sd, reg->reg & 0xff);
894 		break;
895 	case 0xa:
896 		reg->val = cp_read(sd, reg->reg & 0xff);
897 		break;
898 	case 0xb:
899 		reg->val = vdp_read(sd, reg->reg & 0xff);
900 		break;
901 	default:
902 		v4l2_info(sd, "Register %03llx not supported\n", reg->reg);
903 		adv7842_inv_register(sd);
904 		break;
905 	}
906 	return 0;
907 }
908 
909 static int adv7842_s_register(struct v4l2_subdev *sd,
910 		const struct v4l2_dbg_register *reg)
911 {
912 	u8 val = reg->val & 0xff;
913 
914 	switch (reg->reg >> 8) {
915 	case 0:
916 		io_write(sd, reg->reg & 0xff, val);
917 		break;
918 	case 1:
919 		avlink_write(sd, reg->reg & 0xff, val);
920 		break;
921 	case 2:
922 		cec_write(sd, reg->reg & 0xff, val);
923 		break;
924 	case 3:
925 		infoframe_write(sd, reg->reg & 0xff, val);
926 		break;
927 	case 4:
928 		sdp_io_write(sd, reg->reg & 0xff, val);
929 		break;
930 	case 5:
931 		sdp_write(sd, reg->reg & 0xff, val);
932 		break;
933 	case 6:
934 		afe_write(sd, reg->reg & 0xff, val);
935 		break;
936 	case 7:
937 		rep_write(sd, reg->reg & 0xff, val);
938 		break;
939 	case 8:
940 		edid_write(sd, reg->reg & 0xff, val);
941 		break;
942 	case 9:
943 		hdmi_write(sd, reg->reg & 0xff, val);
944 		break;
945 	case 0xa:
946 		cp_write(sd, reg->reg & 0xff, val);
947 		break;
948 	case 0xb:
949 		vdp_write(sd, reg->reg & 0xff, val);
950 		break;
951 	default:
952 		v4l2_info(sd, "Register %03llx not supported\n", reg->reg);
953 		adv7842_inv_register(sd);
954 		break;
955 	}
956 	return 0;
957 }
958 #endif
959 
960 static int adv7842_s_detect_tx_5v_ctrl(struct v4l2_subdev *sd)
961 {
962 	struct adv7842_state *state = to_state(sd);
963 	u16 cable_det = adv7842_read_cable_det(sd);
964 
965 	v4l2_dbg(1, debug, sd, "%s: 0x%x\n", __func__, cable_det);
966 
967 	return v4l2_ctrl_s_ctrl(state->detect_tx_5v_ctrl, cable_det);
968 }
969 
970 static int find_and_set_predefined_video_timings(struct v4l2_subdev *sd,
971 		u8 prim_mode,
972 		const struct adv7842_video_standards *predef_vid_timings,
973 		const struct v4l2_dv_timings *timings)
974 {
975 	int i;
976 
977 	for (i = 0; predef_vid_timings[i].timings.bt.width; i++) {
978 		if (!v4l2_match_dv_timings(timings, &predef_vid_timings[i].timings,
979 				  is_digital_input(sd) ? 250000 : 1000000, false))
980 			continue;
981 		/* video std */
982 		io_write(sd, 0x00, predef_vid_timings[i].vid_std);
983 		/* v_freq and prim mode */
984 		io_write(sd, 0x01, (predef_vid_timings[i].v_freq << 4) + prim_mode);
985 		return 0;
986 	}
987 
988 	return -1;
989 }
990 
991 static int configure_predefined_video_timings(struct v4l2_subdev *sd,
992 		struct v4l2_dv_timings *timings)
993 {
994 	struct adv7842_state *state = to_state(sd);
995 	int err;
996 
997 	v4l2_dbg(1, debug, sd, "%s\n", __func__);
998 
999 	/* reset to default values */
1000 	io_write(sd, 0x16, 0x43);
1001 	io_write(sd, 0x17, 0x5a);
1002 	/* disable embedded syncs for auto graphics mode */
1003 	cp_write_and_or(sd, 0x81, 0xef, 0x00);
1004 	cp_write(sd, 0x26, 0x00);
1005 	cp_write(sd, 0x27, 0x00);
1006 	cp_write(sd, 0x28, 0x00);
1007 	cp_write(sd, 0x29, 0x00);
1008 	cp_write(sd, 0x8f, 0x40);
1009 	cp_write(sd, 0x90, 0x00);
1010 	cp_write(sd, 0xa5, 0x00);
1011 	cp_write(sd, 0xa6, 0x00);
1012 	cp_write(sd, 0xa7, 0x00);
1013 	cp_write(sd, 0xab, 0x00);
1014 	cp_write(sd, 0xac, 0x00);
1015 
1016 	switch (state->mode) {
1017 	case ADV7842_MODE_COMP:
1018 	case ADV7842_MODE_RGB:
1019 		err = find_and_set_predefined_video_timings(sd,
1020 				0x01, adv7842_prim_mode_comp, timings);
1021 		if (err)
1022 			err = find_and_set_predefined_video_timings(sd,
1023 					0x02, adv7842_prim_mode_gr, timings);
1024 		break;
1025 	case ADV7842_MODE_HDMI:
1026 		err = find_and_set_predefined_video_timings(sd,
1027 				0x05, adv7842_prim_mode_hdmi_comp, timings);
1028 		if (err)
1029 			err = find_and_set_predefined_video_timings(sd,
1030 					0x06, adv7842_prim_mode_hdmi_gr, timings);
1031 		break;
1032 	default:
1033 		v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n",
1034 				__func__, state->mode);
1035 		err = -1;
1036 		break;
1037 	}
1038 
1039 
1040 	return err;
1041 }
1042 
1043 static void configure_custom_video_timings(struct v4l2_subdev *sd,
1044 		const struct v4l2_bt_timings *bt)
1045 {
1046 	struct adv7842_state *state = to_state(sd);
1047 	struct i2c_client *client = v4l2_get_subdevdata(sd);
1048 	u32 width = htotal(bt);
1049 	u32 height = vtotal(bt);
1050 	u16 cp_start_sav = bt->hsync + bt->hbackporch - 4;
1051 	u16 cp_start_eav = width - bt->hfrontporch;
1052 	u16 cp_start_vbi = height - bt->vfrontporch + 1;
1053 	u16 cp_end_vbi = bt->vsync + bt->vbackporch + 1;
1054 	u16 ch1_fr_ll = (((u32)bt->pixelclock / 100) > 0) ?
1055 		((width * (ADV7842_fsc / 100)) / ((u32)bt->pixelclock / 100)) : 0;
1056 	const u8 pll[2] = {
1057 		0xc0 | ((width >> 8) & 0x1f),
1058 		width & 0xff
1059 	};
1060 
1061 	v4l2_dbg(2, debug, sd, "%s\n", __func__);
1062 
1063 	switch (state->mode) {
1064 	case ADV7842_MODE_COMP:
1065 	case ADV7842_MODE_RGB:
1066 		/* auto graphics */
1067 		io_write(sd, 0x00, 0x07); /* video std */
1068 		io_write(sd, 0x01, 0x02); /* prim mode */
1069 		/* enable embedded syncs for auto graphics mode */
1070 		cp_write_and_or(sd, 0x81, 0xef, 0x10);
1071 
1072 		/* Should only be set in auto-graphics mode [REF_02, p. 91-92] */
1073 		/* setup PLL_DIV_MAN_EN and PLL_DIV_RATIO */
1074 		/* IO-map reg. 0x16 and 0x17 should be written in sequence */
1075 		if (i2c_smbus_write_i2c_block_data(client, 0x16, 2, pll)) {
1076 			v4l2_err(sd, "writing to reg 0x16 and 0x17 failed\n");
1077 			break;
1078 		}
1079 
1080 		/* active video - horizontal timing */
1081 		cp_write(sd, 0x26, (cp_start_sav >> 8) & 0xf);
1082 		cp_write(sd, 0x27, (cp_start_sav & 0xff));
1083 		cp_write(sd, 0x28, (cp_start_eav >> 8) & 0xf);
1084 		cp_write(sd, 0x29, (cp_start_eav & 0xff));
1085 
1086 		/* active video - vertical timing */
1087 		cp_write(sd, 0xa5, (cp_start_vbi >> 4) & 0xff);
1088 		cp_write(sd, 0xa6, ((cp_start_vbi & 0xf) << 4) |
1089 					((cp_end_vbi >> 8) & 0xf));
1090 		cp_write(sd, 0xa7, cp_end_vbi & 0xff);
1091 		break;
1092 	case ADV7842_MODE_HDMI:
1093 		/* set default prim_mode/vid_std for HDMI
1094 		   according to [REF_03, c. 4.2] */
1095 		io_write(sd, 0x00, 0x02); /* video std */
1096 		io_write(sd, 0x01, 0x06); /* prim mode */
1097 		break;
1098 	default:
1099 		v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n",
1100 				__func__, state->mode);
1101 		break;
1102 	}
1103 
1104 	cp_write(sd, 0x8f, (ch1_fr_ll >> 8) & 0x7);
1105 	cp_write(sd, 0x90, ch1_fr_ll & 0xff);
1106 	cp_write(sd, 0xab, (height >> 4) & 0xff);
1107 	cp_write(sd, 0xac, (height & 0x0f) << 4);
1108 }
1109 
1110 static void adv7842_set_offset(struct v4l2_subdev *sd, bool auto_offset, u16 offset_a, u16 offset_b, u16 offset_c)
1111 {
1112 	struct adv7842_state *state = to_state(sd);
1113 	u8 offset_buf[4];
1114 
1115 	if (auto_offset) {
1116 		offset_a = 0x3ff;
1117 		offset_b = 0x3ff;
1118 		offset_c = 0x3ff;
1119 	}
1120 
1121 	v4l2_dbg(2, debug, sd, "%s: %s offset: a = 0x%x, b = 0x%x, c = 0x%x\n",
1122 		 __func__, auto_offset ? "Auto" : "Manual",
1123 		 offset_a, offset_b, offset_c);
1124 
1125 	offset_buf[0]= (cp_read(sd, 0x77) & 0xc0) | ((offset_a & 0x3f0) >> 4);
1126 	offset_buf[1] = ((offset_a & 0x00f) << 4) | ((offset_b & 0x3c0) >> 6);
1127 	offset_buf[2] = ((offset_b & 0x03f) << 2) | ((offset_c & 0x300) >> 8);
1128 	offset_buf[3] = offset_c & 0x0ff;
1129 
1130 	/* Registers must be written in this order with no i2c access in between */
1131 	if (i2c_smbus_write_i2c_block_data(state->i2c_cp, 0x77, 4, offset_buf))
1132 		v4l2_err(sd, "%s: i2c error writing to CP reg 0x77, 0x78, 0x79, 0x7a\n", __func__);
1133 }
1134 
1135 static void adv7842_set_gain(struct v4l2_subdev *sd, bool auto_gain, u16 gain_a, u16 gain_b, u16 gain_c)
1136 {
1137 	struct adv7842_state *state = to_state(sd);
1138 	u8 gain_buf[4];
1139 	u8 gain_man = 1;
1140 	u8 agc_mode_man = 1;
1141 
1142 	if (auto_gain) {
1143 		gain_man = 0;
1144 		agc_mode_man = 0;
1145 		gain_a = 0x100;
1146 		gain_b = 0x100;
1147 		gain_c = 0x100;
1148 	}
1149 
1150 	v4l2_dbg(2, debug, sd, "%s: %s gain: a = 0x%x, b = 0x%x, c = 0x%x\n",
1151 		 __func__, auto_gain ? "Auto" : "Manual",
1152 		 gain_a, gain_b, gain_c);
1153 
1154 	gain_buf[0] = ((gain_man << 7) | (agc_mode_man << 6) | ((gain_a & 0x3f0) >> 4));
1155 	gain_buf[1] = (((gain_a & 0x00f) << 4) | ((gain_b & 0x3c0) >> 6));
1156 	gain_buf[2] = (((gain_b & 0x03f) << 2) | ((gain_c & 0x300) >> 8));
1157 	gain_buf[3] = ((gain_c & 0x0ff));
1158 
1159 	/* Registers must be written in this order with no i2c access in between */
1160 	if (i2c_smbus_write_i2c_block_data(state->i2c_cp, 0x73, 4, gain_buf))
1161 		v4l2_err(sd, "%s: i2c error writing to CP reg 0x73, 0x74, 0x75, 0x76\n", __func__);
1162 }
1163 
1164 static void set_rgb_quantization_range(struct v4l2_subdev *sd)
1165 {
1166 	struct adv7842_state *state = to_state(sd);
1167 	bool rgb_output = io_read(sd, 0x02) & 0x02;
1168 	bool hdmi_signal = hdmi_read(sd, 0x05) & 0x80;
1169 	u8 y = HDMI_COLORSPACE_RGB;
1170 
1171 	if (hdmi_signal && (io_read(sd, 0x60) & 1))
1172 		y = infoframe_read(sd, 0x01) >> 5;
1173 
1174 	v4l2_dbg(2, debug, sd, "%s: RGB quantization range: %d, RGB out: %d, HDMI: %d\n",
1175 			__func__, state->rgb_quantization_range,
1176 			rgb_output, hdmi_signal);
1177 
1178 	adv7842_set_gain(sd, true, 0x0, 0x0, 0x0);
1179 	adv7842_set_offset(sd, true, 0x0, 0x0, 0x0);
1180 	io_write_clr_set(sd, 0x02, 0x04, rgb_output ? 0 : 4);
1181 
1182 	switch (state->rgb_quantization_range) {
1183 	case V4L2_DV_RGB_RANGE_AUTO:
1184 		if (state->mode == ADV7842_MODE_RGB) {
1185 			/* Receiving analog RGB signal
1186 			 * Set RGB full range (0-255) */
1187 			io_write_and_or(sd, 0x02, 0x0f, 0x10);
1188 			break;
1189 		}
1190 
1191 		if (state->mode == ADV7842_MODE_COMP) {
1192 			/* Receiving analog YPbPr signal
1193 			 * Set automode */
1194 			io_write_and_or(sd, 0x02, 0x0f, 0xf0);
1195 			break;
1196 		}
1197 
1198 		if (hdmi_signal) {
1199 			/* Receiving HDMI signal
1200 			 * Set automode */
1201 			io_write_and_or(sd, 0x02, 0x0f, 0xf0);
1202 			break;
1203 		}
1204 
1205 		/* Receiving DVI-D signal
1206 		 * ADV7842 selects RGB limited range regardless of
1207 		 * input format (CE/IT) in automatic mode */
1208 		if (state->timings.bt.flags & V4L2_DV_FL_IS_CE_VIDEO) {
1209 			/* RGB limited range (16-235) */
1210 			io_write_and_or(sd, 0x02, 0x0f, 0x00);
1211 		} else {
1212 			/* RGB full range (0-255) */
1213 			io_write_and_or(sd, 0x02, 0x0f, 0x10);
1214 
1215 			if (is_digital_input(sd) && rgb_output) {
1216 				adv7842_set_offset(sd, false, 0x40, 0x40, 0x40);
1217 			} else {
1218 				adv7842_set_gain(sd, false, 0xe0, 0xe0, 0xe0);
1219 				adv7842_set_offset(sd, false, 0x70, 0x70, 0x70);
1220 			}
1221 		}
1222 		break;
1223 	case V4L2_DV_RGB_RANGE_LIMITED:
1224 		if (state->mode == ADV7842_MODE_COMP) {
1225 			/* YCrCb limited range (16-235) */
1226 			io_write_and_or(sd, 0x02, 0x0f, 0x20);
1227 			break;
1228 		}
1229 
1230 		if (y != HDMI_COLORSPACE_RGB)
1231 			break;
1232 
1233 		/* RGB limited range (16-235) */
1234 		io_write_and_or(sd, 0x02, 0x0f, 0x00);
1235 
1236 		break;
1237 	case V4L2_DV_RGB_RANGE_FULL:
1238 		if (state->mode == ADV7842_MODE_COMP) {
1239 			/* YCrCb full range (0-255) */
1240 			io_write_and_or(sd, 0x02, 0x0f, 0x60);
1241 			break;
1242 		}
1243 
1244 		if (y != HDMI_COLORSPACE_RGB)
1245 			break;
1246 
1247 		/* RGB full range (0-255) */
1248 		io_write_and_or(sd, 0x02, 0x0f, 0x10);
1249 
1250 		if (is_analog_input(sd) || hdmi_signal)
1251 			break;
1252 
1253 		/* Adjust gain/offset for DVI-D signals only */
1254 		if (rgb_output) {
1255 			adv7842_set_offset(sd, false, 0x40, 0x40, 0x40);
1256 		} else {
1257 			adv7842_set_gain(sd, false, 0xe0, 0xe0, 0xe0);
1258 			adv7842_set_offset(sd, false, 0x70, 0x70, 0x70);
1259 		}
1260 		break;
1261 	}
1262 }
1263 
1264 static int adv7842_s_ctrl(struct v4l2_ctrl *ctrl)
1265 {
1266 	struct v4l2_subdev *sd = to_sd(ctrl);
1267 	struct adv7842_state *state = to_state(sd);
1268 
1269 	/* TODO SDP ctrls
1270 	   contrast/brightness/hue/free run is acting a bit strange,
1271 	   not sure if sdp csc is correct.
1272 	 */
1273 	switch (ctrl->id) {
1274 	/* standard ctrls */
1275 	case V4L2_CID_BRIGHTNESS:
1276 		cp_write(sd, 0x3c, ctrl->val);
1277 		sdp_write(sd, 0x14, ctrl->val);
1278 		/* ignore lsb sdp 0x17[3:2] */
1279 		return 0;
1280 	case V4L2_CID_CONTRAST:
1281 		cp_write(sd, 0x3a, ctrl->val);
1282 		sdp_write(sd, 0x13, ctrl->val);
1283 		/* ignore lsb sdp 0x17[1:0] */
1284 		return 0;
1285 	case V4L2_CID_SATURATION:
1286 		cp_write(sd, 0x3b, ctrl->val);
1287 		sdp_write(sd, 0x15, ctrl->val);
1288 		/* ignore lsb sdp 0x17[5:4] */
1289 		return 0;
1290 	case V4L2_CID_HUE:
1291 		cp_write(sd, 0x3d, ctrl->val);
1292 		sdp_write(sd, 0x16, ctrl->val);
1293 		/* ignore lsb sdp 0x17[7:6] */
1294 		return 0;
1295 		/* custom ctrls */
1296 	case V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE:
1297 		afe_write(sd, 0xc8, ctrl->val);
1298 		return 0;
1299 	case V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL:
1300 		cp_write_and_or(sd, 0xbf, ~0x04, (ctrl->val << 2));
1301 		sdp_write_and_or(sd, 0xdd, ~0x04, (ctrl->val << 2));
1302 		return 0;
1303 	case V4L2_CID_ADV_RX_FREE_RUN_COLOR: {
1304 		u8 R = (ctrl->val & 0xff0000) >> 16;
1305 		u8 G = (ctrl->val & 0x00ff00) >> 8;
1306 		u8 B = (ctrl->val & 0x0000ff);
1307 		/* RGB -> YUV, numerical approximation */
1308 		int Y = 66 * R + 129 * G + 25 * B;
1309 		int U = -38 * R - 74 * G + 112 * B;
1310 		int V = 112 * R - 94 * G - 18 * B;
1311 
1312 		/* Scale down to 8 bits with rounding */
1313 		Y = (Y + 128) >> 8;
1314 		U = (U + 128) >> 8;
1315 		V = (V + 128) >> 8;
1316 		/* make U,V positive */
1317 		Y += 16;
1318 		U += 128;
1319 		V += 128;
1320 
1321 		v4l2_dbg(1, debug, sd, "R %x, G %x, B %x\n", R, G, B);
1322 		v4l2_dbg(1, debug, sd, "Y %x, U %x, V %x\n", Y, U, V);
1323 
1324 		/* CP */
1325 		cp_write(sd, 0xc1, R);
1326 		cp_write(sd, 0xc0, G);
1327 		cp_write(sd, 0xc2, B);
1328 		/* SDP */
1329 		sdp_write(sd, 0xde, Y);
1330 		sdp_write(sd, 0xdf, (V & 0xf0) | ((U >> 4) & 0x0f));
1331 		return 0;
1332 	}
1333 	case V4L2_CID_DV_RX_RGB_RANGE:
1334 		state->rgb_quantization_range = ctrl->val;
1335 		set_rgb_quantization_range(sd);
1336 		return 0;
1337 	}
1338 	return -EINVAL;
1339 }
1340 
1341 static int adv7842_g_volatile_ctrl(struct v4l2_ctrl *ctrl)
1342 {
1343 	struct v4l2_subdev *sd = to_sd(ctrl);
1344 
1345 	if (ctrl->id == V4L2_CID_DV_RX_IT_CONTENT_TYPE) {
1346 		ctrl->val = V4L2_DV_IT_CONTENT_TYPE_NO_ITC;
1347 		if ((io_read(sd, 0x60) & 1) && (infoframe_read(sd, 0x03) & 0x80))
1348 			ctrl->val = (infoframe_read(sd, 0x05) >> 4) & 3;
1349 		return 0;
1350 	}
1351 	return -EINVAL;
1352 }
1353 
1354 static inline bool no_power(struct v4l2_subdev *sd)
1355 {
1356 	return io_read(sd, 0x0c) & 0x24;
1357 }
1358 
1359 static inline bool no_cp_signal(struct v4l2_subdev *sd)
1360 {
1361 	return ((cp_read(sd, 0xb5) & 0xd0) != 0xd0) || !(cp_read(sd, 0xb1) & 0x80);
1362 }
1363 
1364 static inline bool is_hdmi(struct v4l2_subdev *sd)
1365 {
1366 	return hdmi_read(sd, 0x05) & 0x80;
1367 }
1368 
1369 static int adv7842_g_input_status(struct v4l2_subdev *sd, u32 *status)
1370 {
1371 	struct adv7842_state *state = to_state(sd);
1372 
1373 	*status = 0;
1374 
1375 	if (io_read(sd, 0x0c) & 0x24)
1376 		*status |= V4L2_IN_ST_NO_POWER;
1377 
1378 	if (state->mode == ADV7842_MODE_SDP) {
1379 		/* status from SDP block */
1380 		if (!(sdp_read(sd, 0x5A) & 0x01))
1381 			*status |= V4L2_IN_ST_NO_SIGNAL;
1382 
1383 		v4l2_dbg(1, debug, sd, "%s: SDP status = 0x%x\n",
1384 				__func__, *status);
1385 		return 0;
1386 	}
1387 	/* status from CP block */
1388 	if ((cp_read(sd, 0xb5) & 0xd0) != 0xd0 ||
1389 			!(cp_read(sd, 0xb1) & 0x80))
1390 		/* TODO channel 2 */
1391 		*status |= V4L2_IN_ST_NO_SIGNAL;
1392 
1393 	if (is_digital_input(sd) && ((io_read(sd, 0x74) & 0x03) != 0x03))
1394 		*status |= V4L2_IN_ST_NO_SIGNAL;
1395 
1396 	v4l2_dbg(1, debug, sd, "%s: CP status = 0x%x\n",
1397 			__func__, *status);
1398 
1399 	return 0;
1400 }
1401 
1402 struct stdi_readback {
1403 	u16 bl, lcf, lcvs;
1404 	u8 hs_pol, vs_pol;
1405 	bool interlaced;
1406 };
1407 
1408 static int stdi2dv_timings(struct v4l2_subdev *sd,
1409 		struct stdi_readback *stdi,
1410 		struct v4l2_dv_timings *timings)
1411 {
1412 	struct adv7842_state *state = to_state(sd);
1413 	u32 hfreq = (ADV7842_fsc * 8) / stdi->bl;
1414 	u32 pix_clk;
1415 	int i;
1416 
1417 	for (i = 0; v4l2_dv_timings_presets[i].bt.width; i++) {
1418 		const struct v4l2_bt_timings *bt = &v4l2_dv_timings_presets[i].bt;
1419 
1420 		if (!v4l2_valid_dv_timings(&v4l2_dv_timings_presets[i],
1421 					   adv7842_get_dv_timings_cap(sd),
1422 					   adv7842_check_dv_timings, NULL))
1423 			continue;
1424 		if (vtotal(bt) != stdi->lcf + 1)
1425 			continue;
1426 		if (bt->vsync != stdi->lcvs)
1427 			continue;
1428 
1429 		pix_clk = hfreq * htotal(bt);
1430 
1431 		if ((pix_clk < bt->pixelclock + 1000000) &&
1432 		    (pix_clk > bt->pixelclock - 1000000)) {
1433 			*timings = v4l2_dv_timings_presets[i];
1434 			return 0;
1435 		}
1436 	}
1437 
1438 	if (v4l2_detect_cvt(stdi->lcf + 1, hfreq, stdi->lcvs, 0,
1439 			(stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) |
1440 			(stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0),
1441 			false, timings))
1442 		return 0;
1443 	if (v4l2_detect_gtf(stdi->lcf + 1, hfreq, stdi->lcvs,
1444 			(stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) |
1445 			(stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0),
1446 			false, state->aspect_ratio, timings))
1447 		return 0;
1448 
1449 	v4l2_dbg(2, debug, sd,
1450 		"%s: No format candidate found for lcvs = %d, lcf=%d, bl = %d, %chsync, %cvsync\n",
1451 		__func__, stdi->lcvs, stdi->lcf, stdi->bl,
1452 		stdi->hs_pol, stdi->vs_pol);
1453 	return -1;
1454 }
1455 
1456 static int read_stdi(struct v4l2_subdev *sd, struct stdi_readback *stdi)
1457 {
1458 	u32 status;
1459 
1460 	adv7842_g_input_status(sd, &status);
1461 	if (status & V4L2_IN_ST_NO_SIGNAL) {
1462 		v4l2_dbg(2, debug, sd, "%s: no signal\n", __func__);
1463 		return -ENOLINK;
1464 	}
1465 
1466 	stdi->bl = ((cp_read(sd, 0xb1) & 0x3f) << 8) | cp_read(sd, 0xb2);
1467 	stdi->lcf = ((cp_read(sd, 0xb3) & 0x7) << 8) | cp_read(sd, 0xb4);
1468 	stdi->lcvs = cp_read(sd, 0xb3) >> 3;
1469 
1470 	if ((cp_read(sd, 0xb5) & 0x80) && ((cp_read(sd, 0xb5) & 0x03) == 0x01)) {
1471 		stdi->hs_pol = ((cp_read(sd, 0xb5) & 0x10) ?
1472 			((cp_read(sd, 0xb5) & 0x08) ? '+' : '-') : 'x');
1473 		stdi->vs_pol = ((cp_read(sd, 0xb5) & 0x40) ?
1474 			((cp_read(sd, 0xb5) & 0x20) ? '+' : '-') : 'x');
1475 	} else {
1476 		stdi->hs_pol = 'x';
1477 		stdi->vs_pol = 'x';
1478 	}
1479 	stdi->interlaced = (cp_read(sd, 0xb1) & 0x40) ? true : false;
1480 
1481 	if (stdi->lcf < 239 || stdi->bl < 8 || stdi->bl == 0x3fff) {
1482 		v4l2_dbg(2, debug, sd, "%s: invalid signal\n", __func__);
1483 		return -ENOLINK;
1484 	}
1485 
1486 	v4l2_dbg(2, debug, sd,
1487 		"%s: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %chsync, %cvsync, %s\n",
1488 		 __func__, stdi->lcf, stdi->bl, stdi->lcvs,
1489 		 stdi->hs_pol, stdi->vs_pol,
1490 		 stdi->interlaced ? "interlaced" : "progressive");
1491 
1492 	return 0;
1493 }
1494 
1495 static int adv7842_enum_dv_timings(struct v4l2_subdev *sd,
1496 				   struct v4l2_enum_dv_timings *timings)
1497 {
1498 	if (timings->pad != 0)
1499 		return -EINVAL;
1500 
1501 	return v4l2_enum_dv_timings_cap(timings,
1502 		adv7842_get_dv_timings_cap(sd), adv7842_check_dv_timings, NULL);
1503 }
1504 
1505 static int adv7842_dv_timings_cap(struct v4l2_subdev *sd,
1506 				  struct v4l2_dv_timings_cap *cap)
1507 {
1508 	if (cap->pad != 0)
1509 		return -EINVAL;
1510 
1511 	*cap = *adv7842_get_dv_timings_cap(sd);
1512 	return 0;
1513 }
1514 
1515 /* Fill the optional fields .standards and .flags in struct v4l2_dv_timings
1516    if the format is listed in adv7842_timings[] */
1517 static void adv7842_fill_optional_dv_timings_fields(struct v4l2_subdev *sd,
1518 		struct v4l2_dv_timings *timings)
1519 {
1520 	v4l2_find_dv_timings_cap(timings, adv7842_get_dv_timings_cap(sd),
1521 			is_digital_input(sd) ? 250000 : 1000000,
1522 			adv7842_check_dv_timings, NULL);
1523 	timings->bt.flags |= V4L2_DV_FL_CAN_DETECT_REDUCED_FPS;
1524 }
1525 
1526 static int adv7842_query_dv_timings(struct v4l2_subdev *sd,
1527 				    struct v4l2_dv_timings *timings)
1528 {
1529 	struct adv7842_state *state = to_state(sd);
1530 	struct v4l2_bt_timings *bt = &timings->bt;
1531 	struct stdi_readback stdi = { 0 };
1532 
1533 	v4l2_dbg(1, debug, sd, "%s:\n", __func__);
1534 
1535 	memset(timings, 0, sizeof(struct v4l2_dv_timings));
1536 
1537 	/* SDP block */
1538 	if (state->mode == ADV7842_MODE_SDP)
1539 		return -ENODATA;
1540 
1541 	/* read STDI */
1542 	if (read_stdi(sd, &stdi)) {
1543 		state->restart_stdi_once = true;
1544 		v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__);
1545 		return -ENOLINK;
1546 	}
1547 	bt->interlaced = stdi.interlaced ?
1548 		V4L2_DV_INTERLACED : V4L2_DV_PROGRESSIVE;
1549 	bt->standards = V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
1550 			V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT;
1551 
1552 	if (is_digital_input(sd)) {
1553 		u32 freq;
1554 
1555 		timings->type = V4L2_DV_BT_656_1120;
1556 
1557 		bt->width = (hdmi_read(sd, 0x07) & 0x0f) * 256 + hdmi_read(sd, 0x08);
1558 		bt->height = (hdmi_read(sd, 0x09) & 0x0f) * 256 + hdmi_read(sd, 0x0a);
1559 		freq = ((hdmi_read(sd, 0x51) << 1) + (hdmi_read(sd, 0x52) >> 7)) * 1000000;
1560 		freq += ((hdmi_read(sd, 0x52) & 0x7f) * 7813);
1561 		if (is_hdmi(sd)) {
1562 			/* adjust for deep color mode */
1563 			freq = freq * 8 / (((hdmi_read(sd, 0x0b) & 0xc0) >> 6) * 2 + 8);
1564 		}
1565 		bt->pixelclock = freq;
1566 		bt->hfrontporch = (hdmi_read(sd, 0x20) & 0x03) * 256 +
1567 			hdmi_read(sd, 0x21);
1568 		bt->hsync = (hdmi_read(sd, 0x22) & 0x03) * 256 +
1569 			hdmi_read(sd, 0x23);
1570 		bt->hbackporch = (hdmi_read(sd, 0x24) & 0x03) * 256 +
1571 			hdmi_read(sd, 0x25);
1572 		bt->vfrontporch = ((hdmi_read(sd, 0x2a) & 0x1f) * 256 +
1573 			hdmi_read(sd, 0x2b)) / 2;
1574 		bt->vsync = ((hdmi_read(sd, 0x2e) & 0x1f) * 256 +
1575 			hdmi_read(sd, 0x2f)) / 2;
1576 		bt->vbackporch = ((hdmi_read(sd, 0x32) & 0x1f) * 256 +
1577 			hdmi_read(sd, 0x33)) / 2;
1578 		bt->polarities = ((hdmi_read(sd, 0x05) & 0x10) ? V4L2_DV_VSYNC_POS_POL : 0) |
1579 			((hdmi_read(sd, 0x05) & 0x20) ? V4L2_DV_HSYNC_POS_POL : 0);
1580 		if (bt->interlaced == V4L2_DV_INTERLACED) {
1581 			bt->height += (hdmi_read(sd, 0x0b) & 0x0f) * 256 +
1582 					hdmi_read(sd, 0x0c);
1583 			bt->il_vfrontporch = ((hdmi_read(sd, 0x2c) & 0x1f) * 256 +
1584 					hdmi_read(sd, 0x2d)) / 2;
1585 			bt->il_vsync = ((hdmi_read(sd, 0x30) & 0x1f) * 256 +
1586 					hdmi_read(sd, 0x31)) / 2;
1587 			bt->il_vbackporch = ((hdmi_read(sd, 0x34) & 0x1f) * 256 +
1588 					hdmi_read(sd, 0x35)) / 2;
1589 		} else {
1590 			bt->il_vfrontporch = 0;
1591 			bt->il_vsync = 0;
1592 			bt->il_vbackporch = 0;
1593 		}
1594 		adv7842_fill_optional_dv_timings_fields(sd, timings);
1595 		if ((timings->bt.flags & V4L2_DV_FL_CAN_REDUCE_FPS) &&
1596 		    freq < bt->pixelclock) {
1597 			u32 reduced_freq = ((u32)bt->pixelclock / 1001) * 1000;
1598 			u32 delta_freq = abs(freq - reduced_freq);
1599 
1600 			if (delta_freq < ((u32)bt->pixelclock - reduced_freq) / 2)
1601 				timings->bt.flags |= V4L2_DV_FL_REDUCED_FPS;
1602 		}
1603 	} else {
1604 		/* find format
1605 		 * Since LCVS values are inaccurate [REF_03, p. 339-340],
1606 		 * stdi2dv_timings() is called with lcvs +-1 if the first attempt fails.
1607 		 */
1608 		if (!stdi2dv_timings(sd, &stdi, timings))
1609 			goto found;
1610 		stdi.lcvs += 1;
1611 		v4l2_dbg(1, debug, sd, "%s: lcvs + 1 = %d\n", __func__, stdi.lcvs);
1612 		if (!stdi2dv_timings(sd, &stdi, timings))
1613 			goto found;
1614 		stdi.lcvs -= 2;
1615 		v4l2_dbg(1, debug, sd, "%s: lcvs - 1 = %d\n", __func__, stdi.lcvs);
1616 		if (stdi2dv_timings(sd, &stdi, timings)) {
1617 			/*
1618 			 * The STDI block may measure wrong values, especially
1619 			 * for lcvs and lcf. If the driver can not find any
1620 			 * valid timing, the STDI block is restarted to measure
1621 			 * the video timings again. The function will return an
1622 			 * error, but the restart of STDI will generate a new
1623 			 * STDI interrupt and the format detection process will
1624 			 * restart.
1625 			 */
1626 			if (state->restart_stdi_once) {
1627 				v4l2_dbg(1, debug, sd, "%s: restart STDI\n", __func__);
1628 				/* TODO restart STDI for Sync Channel 2 */
1629 				/* enter one-shot mode */
1630 				cp_write_and_or(sd, 0x86, 0xf9, 0x00);
1631 				/* trigger STDI restart */
1632 				cp_write_and_or(sd, 0x86, 0xf9, 0x04);
1633 				/* reset to continuous mode */
1634 				cp_write_and_or(sd, 0x86, 0xf9, 0x02);
1635 				state->restart_stdi_once = false;
1636 				return -ENOLINK;
1637 			}
1638 			v4l2_dbg(1, debug, sd, "%s: format not supported\n", __func__);
1639 			return -ERANGE;
1640 		}
1641 		state->restart_stdi_once = true;
1642 	}
1643 found:
1644 
1645 	if (debug > 1)
1646 		v4l2_print_dv_timings(sd->name, "adv7842_query_dv_timings:",
1647 				timings, true);
1648 	return 0;
1649 }
1650 
1651 static int adv7842_s_dv_timings(struct v4l2_subdev *sd,
1652 				struct v4l2_dv_timings *timings)
1653 {
1654 	struct adv7842_state *state = to_state(sd);
1655 	struct v4l2_bt_timings *bt;
1656 	int err;
1657 
1658 	v4l2_dbg(1, debug, sd, "%s:\n", __func__);
1659 
1660 	if (state->mode == ADV7842_MODE_SDP)
1661 		return -ENODATA;
1662 
1663 	if (v4l2_match_dv_timings(&state->timings, timings, 0, false)) {
1664 		v4l2_dbg(1, debug, sd, "%s: no change\n", __func__);
1665 		return 0;
1666 	}
1667 
1668 	bt = &timings->bt;
1669 
1670 	if (!v4l2_valid_dv_timings(timings, adv7842_get_dv_timings_cap(sd),
1671 				   adv7842_check_dv_timings, NULL))
1672 		return -ERANGE;
1673 
1674 	adv7842_fill_optional_dv_timings_fields(sd, timings);
1675 
1676 	state->timings = *timings;
1677 
1678 	cp_write(sd, 0x91, bt->interlaced ? 0x40 : 0x00);
1679 
1680 	/* Use prim_mode and vid_std when available */
1681 	err = configure_predefined_video_timings(sd, timings);
1682 	if (err) {
1683 		/* custom settings when the video format
1684 		  does not have prim_mode/vid_std */
1685 		configure_custom_video_timings(sd, bt);
1686 	}
1687 
1688 	set_rgb_quantization_range(sd);
1689 
1690 
1691 	if (debug > 1)
1692 		v4l2_print_dv_timings(sd->name, "adv7842_s_dv_timings: ",
1693 				      timings, true);
1694 	return 0;
1695 }
1696 
1697 static int adv7842_g_dv_timings(struct v4l2_subdev *sd,
1698 				struct v4l2_dv_timings *timings)
1699 {
1700 	struct adv7842_state *state = to_state(sd);
1701 
1702 	if (state->mode == ADV7842_MODE_SDP)
1703 		return -ENODATA;
1704 	*timings = state->timings;
1705 	return 0;
1706 }
1707 
1708 static void enable_input(struct v4l2_subdev *sd)
1709 {
1710 	struct adv7842_state *state = to_state(sd);
1711 
1712 	set_rgb_quantization_range(sd);
1713 	switch (state->mode) {
1714 	case ADV7842_MODE_SDP:
1715 	case ADV7842_MODE_COMP:
1716 	case ADV7842_MODE_RGB:
1717 		io_write(sd, 0x15, 0xb0);   /* Disable Tristate of Pins (no audio) */
1718 		break;
1719 	case ADV7842_MODE_HDMI:
1720 		hdmi_write(sd, 0x01, 0x00); /* Enable HDMI clock terminators */
1721 		io_write(sd, 0x15, 0xa0);   /* Disable Tristate of Pins */
1722 		hdmi_write_and_or(sd, 0x1a, 0xef, 0x00); /* Unmute audio */
1723 		break;
1724 	default:
1725 		v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n",
1726 			 __func__, state->mode);
1727 		break;
1728 	}
1729 }
1730 
1731 static void disable_input(struct v4l2_subdev *sd)
1732 {
1733 	hdmi_write_and_or(sd, 0x1a, 0xef, 0x10); /* Mute audio [REF_01, c. 2.2.2] */
1734 	msleep(16); /* 512 samples with >= 32 kHz sample rate [REF_03, c. 8.29] */
1735 	io_write(sd, 0x15, 0xbe);   /* Tristate all outputs from video core */
1736 	hdmi_write(sd, 0x01, 0x78); /* Disable HDMI clock terminators */
1737 }
1738 
1739 static void sdp_csc_coeff(struct v4l2_subdev *sd,
1740 			  const struct adv7842_sdp_csc_coeff *c)
1741 {
1742 	/* csc auto/manual */
1743 	sdp_io_write_and_or(sd, 0xe0, 0xbf, c->manual ? 0x00 : 0x40);
1744 
1745 	if (!c->manual)
1746 		return;
1747 
1748 	/* csc scaling */
1749 	sdp_io_write_and_or(sd, 0xe0, 0x7f, c->scaling == 2 ? 0x80 : 0x00);
1750 
1751 	/* A coeff */
1752 	sdp_io_write_and_or(sd, 0xe0, 0xe0, c->A1 >> 8);
1753 	sdp_io_write(sd, 0xe1, c->A1);
1754 	sdp_io_write_and_or(sd, 0xe2, 0xe0, c->A2 >> 8);
1755 	sdp_io_write(sd, 0xe3, c->A2);
1756 	sdp_io_write_and_or(sd, 0xe4, 0xe0, c->A3 >> 8);
1757 	sdp_io_write(sd, 0xe5, c->A3);
1758 
1759 	/* A scale */
1760 	sdp_io_write_and_or(sd, 0xe6, 0x80, c->A4 >> 8);
1761 	sdp_io_write(sd, 0xe7, c->A4);
1762 
1763 	/* B coeff */
1764 	sdp_io_write_and_or(sd, 0xe8, 0xe0, c->B1 >> 8);
1765 	sdp_io_write(sd, 0xe9, c->B1);
1766 	sdp_io_write_and_or(sd, 0xea, 0xe0, c->B2 >> 8);
1767 	sdp_io_write(sd, 0xeb, c->B2);
1768 	sdp_io_write_and_or(sd, 0xec, 0xe0, c->B3 >> 8);
1769 	sdp_io_write(sd, 0xed, c->B3);
1770 
1771 	/* B scale */
1772 	sdp_io_write_and_or(sd, 0xee, 0x80, c->B4 >> 8);
1773 	sdp_io_write(sd, 0xef, c->B4);
1774 
1775 	/* C coeff */
1776 	sdp_io_write_and_or(sd, 0xf0, 0xe0, c->C1 >> 8);
1777 	sdp_io_write(sd, 0xf1, c->C1);
1778 	sdp_io_write_and_or(sd, 0xf2, 0xe0, c->C2 >> 8);
1779 	sdp_io_write(sd, 0xf3, c->C2);
1780 	sdp_io_write_and_or(sd, 0xf4, 0xe0, c->C3 >> 8);
1781 	sdp_io_write(sd, 0xf5, c->C3);
1782 
1783 	/* C scale */
1784 	sdp_io_write_and_or(sd, 0xf6, 0x80, c->C4 >> 8);
1785 	sdp_io_write(sd, 0xf7, c->C4);
1786 }
1787 
1788 static void select_input(struct v4l2_subdev *sd,
1789 			 enum adv7842_vid_std_select vid_std_select)
1790 {
1791 	struct adv7842_state *state = to_state(sd);
1792 
1793 	switch (state->mode) {
1794 	case ADV7842_MODE_SDP:
1795 		io_write(sd, 0x00, vid_std_select); /* video std: CVBS or YC mode */
1796 		io_write(sd, 0x01, 0); /* prim mode */
1797 		/* enable embedded syncs for auto graphics mode */
1798 		cp_write_and_or(sd, 0x81, 0xef, 0x10);
1799 
1800 		afe_write(sd, 0x00, 0x00); /* power up ADC */
1801 		afe_write(sd, 0xc8, 0x00); /* phase control */
1802 
1803 		io_write(sd, 0xdd, 0x90); /* Manual 2x output clock */
1804 		/* script says register 0xde, which don't exist in manual */
1805 
1806 		/* Manual analog input muxing mode, CVBS (6.4)*/
1807 		afe_write_and_or(sd, 0x02, 0x7f, 0x80);
1808 		if (vid_std_select == ADV7842_SDP_VID_STD_CVBS_SD_4x1) {
1809 			afe_write(sd, 0x03, 0xa0); /* ADC0 to AIN10 (CVBS), ADC1 N/C*/
1810 			afe_write(sd, 0x04, 0x00); /* ADC2 N/C,ADC3 N/C*/
1811 		} else {
1812 			afe_write(sd, 0x03, 0xa0); /* ADC0 to AIN10 (CVBS), ADC1 N/C*/
1813 			afe_write(sd, 0x04, 0xc0); /* ADC2 to AIN12, ADC3 N/C*/
1814 		}
1815 		afe_write(sd, 0x0c, 0x1f); /* ADI recommend write */
1816 		afe_write(sd, 0x12, 0x63); /* ADI recommend write */
1817 
1818 		sdp_io_write(sd, 0xb2, 0x60); /* Disable AV codes */
1819 		sdp_io_write(sd, 0xc8, 0xe3); /* Disable Ancillary data */
1820 
1821 		/* SDP recommended settings */
1822 		sdp_write(sd, 0x00, 0x3F); /* Autodetect PAL NTSC (not SECAM) */
1823 		sdp_write(sd, 0x01, 0x00); /* Pedestal Off */
1824 
1825 		sdp_write(sd, 0x03, 0xE4); /* Manual VCR Gain Luma 0x40B */
1826 		sdp_write(sd, 0x04, 0x0B); /* Manual Luma setting */
1827 		sdp_write(sd, 0x05, 0xC3); /* Manual Chroma setting 0x3FE */
1828 		sdp_write(sd, 0x06, 0xFE); /* Manual Chroma setting */
1829 		sdp_write(sd, 0x12, 0x0D); /* Frame TBC,I_P, 3D comb enabled */
1830 		sdp_write(sd, 0xA7, 0x00); /* ADI Recommended Write */
1831 		sdp_io_write(sd, 0xB0, 0x00); /* Disable H and v blanking */
1832 
1833 		/* deinterlacer enabled and 3D comb */
1834 		sdp_write_and_or(sd, 0x12, 0xf6, 0x09);
1835 
1836 		break;
1837 
1838 	case ADV7842_MODE_COMP:
1839 	case ADV7842_MODE_RGB:
1840 		/* Automatic analog input muxing mode */
1841 		afe_write_and_or(sd, 0x02, 0x7f, 0x00);
1842 		/* set mode and select free run resolution */
1843 		io_write(sd, 0x00, vid_std_select); /* video std */
1844 		io_write(sd, 0x01, 0x02); /* prim mode */
1845 		cp_write_and_or(sd, 0x81, 0xef, 0x10); /* enable embedded syncs
1846 							  for auto graphics mode */
1847 
1848 		afe_write(sd, 0x00, 0x00); /* power up ADC */
1849 		afe_write(sd, 0xc8, 0x00); /* phase control */
1850 		if (state->mode == ADV7842_MODE_COMP) {
1851 			/* force to YCrCb */
1852 			io_write_and_or(sd, 0x02, 0x0f, 0x60);
1853 		} else {
1854 			/* force to RGB */
1855 			io_write_and_or(sd, 0x02, 0x0f, 0x10);
1856 		}
1857 
1858 		/* set ADI recommended settings for digitizer */
1859 		/* "ADV7842 Register Settings Recommendations
1860 		 * (rev. 1.8, November 2010)" p. 9. */
1861 		afe_write(sd, 0x0c, 0x1f); /* ADC Range improvement */
1862 		afe_write(sd, 0x12, 0x63); /* ADC Range improvement */
1863 
1864 		/* set to default gain for RGB */
1865 		cp_write(sd, 0x73, 0x10);
1866 		cp_write(sd, 0x74, 0x04);
1867 		cp_write(sd, 0x75, 0x01);
1868 		cp_write(sd, 0x76, 0x00);
1869 
1870 		cp_write(sd, 0x3e, 0x04); /* CP core pre-gain control */
1871 		cp_write(sd, 0xc3, 0x39); /* CP coast control. Graphics mode */
1872 		cp_write(sd, 0x40, 0x5c); /* CP core pre-gain control. Graphics mode */
1873 		break;
1874 
1875 	case ADV7842_MODE_HDMI:
1876 		/* Automatic analog input muxing mode */
1877 		afe_write_and_or(sd, 0x02, 0x7f, 0x00);
1878 		/* set mode and select free run resolution */
1879 		if (state->hdmi_port_a)
1880 			hdmi_write(sd, 0x00, 0x02); /* select port A */
1881 		else
1882 			hdmi_write(sd, 0x00, 0x03); /* select port B */
1883 		io_write(sd, 0x00, vid_std_select); /* video std */
1884 		io_write(sd, 0x01, 5); /* prim mode */
1885 		cp_write_and_or(sd, 0x81, 0xef, 0x00); /* disable embedded syncs
1886 							  for auto graphics mode */
1887 
1888 		/* set ADI recommended settings for HDMI: */
1889 		/* "ADV7842 Register Settings Recommendations
1890 		 * (rev. 1.8, November 2010)" p. 3. */
1891 		hdmi_write(sd, 0xc0, 0x00);
1892 		hdmi_write(sd, 0x0d, 0x34); /* ADI recommended write */
1893 		hdmi_write(sd, 0x3d, 0x10); /* ADI recommended write */
1894 		hdmi_write(sd, 0x44, 0x85); /* TMDS PLL optimization */
1895 		hdmi_write(sd, 0x46, 0x1f); /* ADI recommended write */
1896 		hdmi_write(sd, 0x57, 0xb6); /* TMDS PLL optimization */
1897 		hdmi_write(sd, 0x58, 0x03); /* TMDS PLL optimization */
1898 		hdmi_write(sd, 0x60, 0x88); /* TMDS PLL optimization */
1899 		hdmi_write(sd, 0x61, 0x88); /* TMDS PLL optimization */
1900 		hdmi_write(sd, 0x6c, 0x18); /* Disable ISRC clearing bit,
1901 					       Improve robustness */
1902 		hdmi_write(sd, 0x75, 0x10); /* DDC drive strength */
1903 		hdmi_write(sd, 0x85, 0x1f); /* equaliser */
1904 		hdmi_write(sd, 0x87, 0x70); /* ADI recommended write */
1905 		hdmi_write(sd, 0x89, 0x04); /* equaliser */
1906 		hdmi_write(sd, 0x8a, 0x1e); /* equaliser */
1907 		hdmi_write(sd, 0x93, 0x04); /* equaliser */
1908 		hdmi_write(sd, 0x94, 0x1e); /* equaliser */
1909 		hdmi_write(sd, 0x99, 0xa1); /* ADI recommended write */
1910 		hdmi_write(sd, 0x9b, 0x09); /* ADI recommended write */
1911 		hdmi_write(sd, 0x9d, 0x02); /* equaliser */
1912 
1913 		afe_write(sd, 0x00, 0xff); /* power down ADC */
1914 		afe_write(sd, 0xc8, 0x40); /* phase control */
1915 
1916 		/* set to default gain for HDMI */
1917 		cp_write(sd, 0x73, 0x10);
1918 		cp_write(sd, 0x74, 0x04);
1919 		cp_write(sd, 0x75, 0x01);
1920 		cp_write(sd, 0x76, 0x00);
1921 
1922 		/* reset ADI recommended settings for digitizer */
1923 		/* "ADV7842 Register Settings Recommendations
1924 		 * (rev. 2.5, June 2010)" p. 17. */
1925 		afe_write(sd, 0x12, 0xfb); /* ADC noise shaping filter controls */
1926 		afe_write(sd, 0x0c, 0x0d); /* CP core gain controls */
1927 		cp_write(sd, 0x3e, 0x00); /* CP core pre-gain control */
1928 
1929 		/* CP coast control */
1930 		cp_write(sd, 0xc3, 0x33); /* Component mode */
1931 
1932 		/* color space conversion, autodetect color space */
1933 		io_write_and_or(sd, 0x02, 0x0f, 0xf0);
1934 		break;
1935 
1936 	default:
1937 		v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n",
1938 			 __func__, state->mode);
1939 		break;
1940 	}
1941 }
1942 
1943 static int adv7842_s_routing(struct v4l2_subdev *sd,
1944 		u32 input, u32 output, u32 config)
1945 {
1946 	struct adv7842_state *state = to_state(sd);
1947 
1948 	v4l2_dbg(2, debug, sd, "%s: input %d\n", __func__, input);
1949 
1950 	switch (input) {
1951 	case ADV7842_SELECT_HDMI_PORT_A:
1952 		state->mode = ADV7842_MODE_HDMI;
1953 		state->vid_std_select = ADV7842_HDMI_COMP_VID_STD_HD_1250P;
1954 		state->hdmi_port_a = true;
1955 		break;
1956 	case ADV7842_SELECT_HDMI_PORT_B:
1957 		state->mode = ADV7842_MODE_HDMI;
1958 		state->vid_std_select = ADV7842_HDMI_COMP_VID_STD_HD_1250P;
1959 		state->hdmi_port_a = false;
1960 		break;
1961 	case ADV7842_SELECT_VGA_COMP:
1962 		state->mode = ADV7842_MODE_COMP;
1963 		state->vid_std_select = ADV7842_RGB_VID_STD_AUTO_GRAPH_MODE;
1964 		break;
1965 	case ADV7842_SELECT_VGA_RGB:
1966 		state->mode = ADV7842_MODE_RGB;
1967 		state->vid_std_select = ADV7842_RGB_VID_STD_AUTO_GRAPH_MODE;
1968 		break;
1969 	case ADV7842_SELECT_SDP_CVBS:
1970 		state->mode = ADV7842_MODE_SDP;
1971 		state->vid_std_select = ADV7842_SDP_VID_STD_CVBS_SD_4x1;
1972 		break;
1973 	case ADV7842_SELECT_SDP_YC:
1974 		state->mode = ADV7842_MODE_SDP;
1975 		state->vid_std_select = ADV7842_SDP_VID_STD_YC_SD4_x1;
1976 		break;
1977 	default:
1978 		return -EINVAL;
1979 	}
1980 
1981 	disable_input(sd);
1982 	select_input(sd, state->vid_std_select);
1983 	enable_input(sd);
1984 
1985 	v4l2_subdev_notify_event(sd, &adv7842_ev_fmt);
1986 
1987 	return 0;
1988 }
1989 
1990 static int adv7842_enum_mbus_code(struct v4l2_subdev *sd,
1991 		struct v4l2_subdev_pad_config *cfg,
1992 		struct v4l2_subdev_mbus_code_enum *code)
1993 {
1994 	if (code->index >= ARRAY_SIZE(adv7842_formats))
1995 		return -EINVAL;
1996 	code->code = adv7842_formats[code->index].code;
1997 	return 0;
1998 }
1999 
2000 static void adv7842_fill_format(struct adv7842_state *state,
2001 				struct v4l2_mbus_framefmt *format)
2002 {
2003 	memset(format, 0, sizeof(*format));
2004 
2005 	format->width = state->timings.bt.width;
2006 	format->height = state->timings.bt.height;
2007 	format->field = V4L2_FIELD_NONE;
2008 	format->colorspace = V4L2_COLORSPACE_SRGB;
2009 
2010 	if (state->timings.bt.flags & V4L2_DV_FL_IS_CE_VIDEO)
2011 		format->colorspace = (state->timings.bt.height <= 576) ?
2012 			V4L2_COLORSPACE_SMPTE170M : V4L2_COLORSPACE_REC709;
2013 }
2014 
2015 /*
2016  * Compute the op_ch_sel value required to obtain on the bus the component order
2017  * corresponding to the selected format taking into account bus reordering
2018  * applied by the board at the output of the device.
2019  *
2020  * The following table gives the op_ch_value from the format component order
2021  * (expressed as op_ch_sel value in column) and the bus reordering (expressed as
2022  * adv7842_bus_order value in row).
2023  *
2024  *           |	GBR(0)	GRB(1)	BGR(2)	RGB(3)	BRG(4)	RBG(5)
2025  * ----------+-------------------------------------------------
2026  * RGB (NOP) |	GBR	GRB	BGR	RGB	BRG	RBG
2027  * GRB (1-2) |	BGR	RGB	GBR	GRB	RBG	BRG
2028  * RBG (2-3) |	GRB	GBR	BRG	RBG	BGR	RGB
2029  * BGR (1-3) |	RBG	BRG	RGB	BGR	GRB	GBR
2030  * BRG (ROR) |	BRG	RBG	GRB	GBR	RGB	BGR
2031  * GBR (ROL) |	RGB	BGR	RBG	BRG	GBR	GRB
2032  */
2033 static unsigned int adv7842_op_ch_sel(struct adv7842_state *state)
2034 {
2035 #define _SEL(a, b, c, d, e, f)	{ \
2036 	ADV7842_OP_CH_SEL_##a, ADV7842_OP_CH_SEL_##b, ADV7842_OP_CH_SEL_##c, \
2037 	ADV7842_OP_CH_SEL_##d, ADV7842_OP_CH_SEL_##e, ADV7842_OP_CH_SEL_##f }
2038 #define _BUS(x)			[ADV7842_BUS_ORDER_##x]
2039 
2040 	static const unsigned int op_ch_sel[6][6] = {
2041 		_BUS(RGB) /* NOP */ = _SEL(GBR, GRB, BGR, RGB, BRG, RBG),
2042 		_BUS(GRB) /* 1-2 */ = _SEL(BGR, RGB, GBR, GRB, RBG, BRG),
2043 		_BUS(RBG) /* 2-3 */ = _SEL(GRB, GBR, BRG, RBG, BGR, RGB),
2044 		_BUS(BGR) /* 1-3 */ = _SEL(RBG, BRG, RGB, BGR, GRB, GBR),
2045 		_BUS(BRG) /* ROR */ = _SEL(BRG, RBG, GRB, GBR, RGB, BGR),
2046 		_BUS(GBR) /* ROL */ = _SEL(RGB, BGR, RBG, BRG, GBR, GRB),
2047 	};
2048 
2049 	return op_ch_sel[state->pdata.bus_order][state->format->op_ch_sel >> 5];
2050 }
2051 
2052 static void adv7842_setup_format(struct adv7842_state *state)
2053 {
2054 	struct v4l2_subdev *sd = &state->sd;
2055 
2056 	io_write_clr_set(sd, 0x02, 0x02,
2057 			state->format->rgb_out ? ADV7842_RGB_OUT : 0);
2058 	io_write(sd, 0x03, state->format->op_format_sel |
2059 		 state->pdata.op_format_mode_sel);
2060 	io_write_clr_set(sd, 0x04, 0xe0, adv7842_op_ch_sel(state));
2061 	io_write_clr_set(sd, 0x05, 0x01,
2062 			state->format->swap_cb_cr ? ADV7842_OP_SWAP_CB_CR : 0);
2063 	set_rgb_quantization_range(sd);
2064 }
2065 
2066 static int adv7842_get_format(struct v4l2_subdev *sd,
2067 			      struct v4l2_subdev_pad_config *cfg,
2068 			      struct v4l2_subdev_format *format)
2069 {
2070 	struct adv7842_state *state = to_state(sd);
2071 
2072 	if (format->pad != ADV7842_PAD_SOURCE)
2073 		return -EINVAL;
2074 
2075 	if (state->mode == ADV7842_MODE_SDP) {
2076 		/* SPD block */
2077 		if (!(sdp_read(sd, 0x5a) & 0x01))
2078 			return -EINVAL;
2079 		format->format.code = MEDIA_BUS_FMT_YUYV8_2X8;
2080 		format->format.width = 720;
2081 		/* valid signal */
2082 		if (state->norm & V4L2_STD_525_60)
2083 			format->format.height = 480;
2084 		else
2085 			format->format.height = 576;
2086 		format->format.colorspace = V4L2_COLORSPACE_SMPTE170M;
2087 		return 0;
2088 	}
2089 
2090 	adv7842_fill_format(state, &format->format);
2091 
2092 	if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
2093 		struct v4l2_mbus_framefmt *fmt;
2094 
2095 		fmt = v4l2_subdev_get_try_format(sd, cfg, format->pad);
2096 		format->format.code = fmt->code;
2097 	} else {
2098 		format->format.code = state->format->code;
2099 	}
2100 
2101 	return 0;
2102 }
2103 
2104 static int adv7842_set_format(struct v4l2_subdev *sd,
2105 			      struct v4l2_subdev_pad_config *cfg,
2106 			      struct v4l2_subdev_format *format)
2107 {
2108 	struct adv7842_state *state = to_state(sd);
2109 	const struct adv7842_format_info *info;
2110 
2111 	if (format->pad != ADV7842_PAD_SOURCE)
2112 		return -EINVAL;
2113 
2114 	if (state->mode == ADV7842_MODE_SDP)
2115 		return adv7842_get_format(sd, cfg, format);
2116 
2117 	info = adv7842_format_info(state, format->format.code);
2118 	if (info == NULL)
2119 		info = adv7842_format_info(state, MEDIA_BUS_FMT_YUYV8_2X8);
2120 
2121 	adv7842_fill_format(state, &format->format);
2122 	format->format.code = info->code;
2123 
2124 	if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
2125 		struct v4l2_mbus_framefmt *fmt;
2126 
2127 		fmt = v4l2_subdev_get_try_format(sd, cfg, format->pad);
2128 		fmt->code = format->format.code;
2129 	} else {
2130 		state->format = info;
2131 		adv7842_setup_format(state);
2132 	}
2133 
2134 	return 0;
2135 }
2136 
2137 static void adv7842_irq_enable(struct v4l2_subdev *sd, bool enable)
2138 {
2139 	if (enable) {
2140 		/* Enable SSPD, STDI and CP locked/unlocked interrupts */
2141 		io_write(sd, 0x46, 0x9c);
2142 		/* ESDP_50HZ_DET interrupt */
2143 		io_write(sd, 0x5a, 0x10);
2144 		/* Enable CABLE_DET_A/B_ST (+5v) interrupt */
2145 		io_write(sd, 0x73, 0x03);
2146 		/* Enable V_LOCKED and DE_REGEN_LCK interrupts */
2147 		io_write(sd, 0x78, 0x03);
2148 		/* Enable SDP Standard Detection Change and SDP Video Detected */
2149 		io_write(sd, 0xa0, 0x09);
2150 		/* Enable HDMI_MODE interrupt */
2151 		io_write(sd, 0x69, 0x08);
2152 	} else {
2153 		io_write(sd, 0x46, 0x0);
2154 		io_write(sd, 0x5a, 0x0);
2155 		io_write(sd, 0x73, 0x0);
2156 		io_write(sd, 0x78, 0x0);
2157 		io_write(sd, 0xa0, 0x0);
2158 		io_write(sd, 0x69, 0x0);
2159 	}
2160 }
2161 
2162 #if IS_ENABLED(CONFIG_VIDEO_ADV7842_CEC)
2163 static void adv7842_cec_tx_raw_status(struct v4l2_subdev *sd, u8 tx_raw_status)
2164 {
2165 	struct adv7842_state *state = to_state(sd);
2166 
2167 	if ((cec_read(sd, 0x11) & 0x01) == 0) {
2168 		v4l2_dbg(1, debug, sd, "%s: tx raw: tx disabled\n", __func__);
2169 		return;
2170 	}
2171 
2172 	if (tx_raw_status & 0x02) {
2173 		v4l2_dbg(1, debug, sd, "%s: tx raw: arbitration lost\n",
2174 			 __func__);
2175 		cec_transmit_done(state->cec_adap, CEC_TX_STATUS_ARB_LOST,
2176 				  1, 0, 0, 0);
2177 		return;
2178 	}
2179 	if (tx_raw_status & 0x04) {
2180 		u8 status;
2181 		u8 nack_cnt;
2182 		u8 low_drive_cnt;
2183 
2184 		v4l2_dbg(1, debug, sd, "%s: tx raw: retry failed\n", __func__);
2185 		/*
2186 		 * We set this status bit since this hardware performs
2187 		 * retransmissions.
2188 		 */
2189 		status = CEC_TX_STATUS_MAX_RETRIES;
2190 		nack_cnt = cec_read(sd, 0x14) & 0xf;
2191 		if (nack_cnt)
2192 			status |= CEC_TX_STATUS_NACK;
2193 		low_drive_cnt = cec_read(sd, 0x14) >> 4;
2194 		if (low_drive_cnt)
2195 			status |= CEC_TX_STATUS_LOW_DRIVE;
2196 		cec_transmit_done(state->cec_adap, status,
2197 				  0, nack_cnt, low_drive_cnt, 0);
2198 		return;
2199 	}
2200 	if (tx_raw_status & 0x01) {
2201 		v4l2_dbg(1, debug, sd, "%s: tx raw: ready ok\n", __func__);
2202 		cec_transmit_done(state->cec_adap, CEC_TX_STATUS_OK, 0, 0, 0, 0);
2203 		return;
2204 	}
2205 }
2206 
2207 static void adv7842_cec_isr(struct v4l2_subdev *sd, bool *handled)
2208 {
2209 	u8 cec_irq;
2210 
2211 	/* cec controller */
2212 	cec_irq = io_read(sd, 0x93) & 0x0f;
2213 	if (!cec_irq)
2214 		return;
2215 
2216 	v4l2_dbg(1, debug, sd, "%s: cec: irq 0x%x\n", __func__, cec_irq);
2217 	adv7842_cec_tx_raw_status(sd, cec_irq);
2218 	if (cec_irq & 0x08) {
2219 		struct adv7842_state *state = to_state(sd);
2220 		struct cec_msg msg;
2221 
2222 		msg.len = cec_read(sd, 0x25) & 0x1f;
2223 		if (msg.len > 16)
2224 			msg.len = 16;
2225 
2226 		if (msg.len) {
2227 			u8 i;
2228 
2229 			for (i = 0; i < msg.len; i++)
2230 				msg.msg[i] = cec_read(sd, i + 0x15);
2231 			cec_write(sd, 0x26, 0x01); /* re-enable rx */
2232 			cec_received_msg(state->cec_adap, &msg);
2233 		}
2234 	}
2235 
2236 	io_write(sd, 0x94, cec_irq);
2237 
2238 	if (handled)
2239 		*handled = true;
2240 }
2241 
2242 static int adv7842_cec_adap_enable(struct cec_adapter *adap, bool enable)
2243 {
2244 	struct adv7842_state *state = cec_get_drvdata(adap);
2245 	struct v4l2_subdev *sd = &state->sd;
2246 
2247 	if (!state->cec_enabled_adap && enable) {
2248 		cec_write_clr_set(sd, 0x2a, 0x01, 0x01); /* power up cec */
2249 		cec_write(sd, 0x2c, 0x01);	/* cec soft reset */
2250 		cec_write_clr_set(sd, 0x11, 0x01, 0); /* initially disable tx */
2251 		/* enabled irqs: */
2252 		/* tx: ready */
2253 		/* tx: arbitration lost */
2254 		/* tx: retry timeout */
2255 		/* rx: ready */
2256 		io_write_clr_set(sd, 0x96, 0x0f, 0x0f);
2257 		cec_write(sd, 0x26, 0x01);            /* enable rx */
2258 	} else if (state->cec_enabled_adap && !enable) {
2259 		/* disable cec interrupts */
2260 		io_write_clr_set(sd, 0x96, 0x0f, 0x00);
2261 		/* disable address mask 1-3 */
2262 		cec_write_clr_set(sd, 0x27, 0x70, 0x00);
2263 		/* power down cec section */
2264 		cec_write_clr_set(sd, 0x2a, 0x01, 0x00);
2265 		state->cec_valid_addrs = 0;
2266 	}
2267 	state->cec_enabled_adap = enable;
2268 	return 0;
2269 }
2270 
2271 static int adv7842_cec_adap_log_addr(struct cec_adapter *adap, u8 addr)
2272 {
2273 	struct adv7842_state *state = cec_get_drvdata(adap);
2274 	struct v4l2_subdev *sd = &state->sd;
2275 	unsigned int i, free_idx = ADV7842_MAX_ADDRS;
2276 
2277 	if (!state->cec_enabled_adap)
2278 		return addr == CEC_LOG_ADDR_INVALID ? 0 : -EIO;
2279 
2280 	if (addr == CEC_LOG_ADDR_INVALID) {
2281 		cec_write_clr_set(sd, 0x27, 0x70, 0);
2282 		state->cec_valid_addrs = 0;
2283 		return 0;
2284 	}
2285 
2286 	for (i = 0; i < ADV7842_MAX_ADDRS; i++) {
2287 		bool is_valid = state->cec_valid_addrs & (1 << i);
2288 
2289 		if (free_idx == ADV7842_MAX_ADDRS && !is_valid)
2290 			free_idx = i;
2291 		if (is_valid && state->cec_addr[i] == addr)
2292 			return 0;
2293 	}
2294 	if (i == ADV7842_MAX_ADDRS) {
2295 		i = free_idx;
2296 		if (i == ADV7842_MAX_ADDRS)
2297 			return -ENXIO;
2298 	}
2299 	state->cec_addr[i] = addr;
2300 	state->cec_valid_addrs |= 1 << i;
2301 
2302 	switch (i) {
2303 	case 0:
2304 		/* enable address mask 0 */
2305 		cec_write_clr_set(sd, 0x27, 0x10, 0x10);
2306 		/* set address for mask 0 */
2307 		cec_write_clr_set(sd, 0x28, 0x0f, addr);
2308 		break;
2309 	case 1:
2310 		/* enable address mask 1 */
2311 		cec_write_clr_set(sd, 0x27, 0x20, 0x20);
2312 		/* set address for mask 1 */
2313 		cec_write_clr_set(sd, 0x28, 0xf0, addr << 4);
2314 		break;
2315 	case 2:
2316 		/* enable address mask 2 */
2317 		cec_write_clr_set(sd, 0x27, 0x40, 0x40);
2318 		/* set address for mask 1 */
2319 		cec_write_clr_set(sd, 0x29, 0x0f, addr);
2320 		break;
2321 	}
2322 	return 0;
2323 }
2324 
2325 static int adv7842_cec_adap_transmit(struct cec_adapter *adap, u8 attempts,
2326 				     u32 signal_free_time, struct cec_msg *msg)
2327 {
2328 	struct adv7842_state *state = cec_get_drvdata(adap);
2329 	struct v4l2_subdev *sd = &state->sd;
2330 	u8 len = msg->len;
2331 	unsigned int i;
2332 
2333 	/*
2334 	 * The number of retries is the number of attempts - 1, but retry
2335 	 * at least once. It's not clear if a value of 0 is allowed, so
2336 	 * let's do at least one retry.
2337 	 */
2338 	cec_write_clr_set(sd, 0x12, 0x70, max(1, attempts - 1) << 4);
2339 
2340 	if (len > 16) {
2341 		v4l2_err(sd, "%s: len exceeded 16 (%d)\n", __func__, len);
2342 		return -EINVAL;
2343 	}
2344 
2345 	/* write data */
2346 	for (i = 0; i < len; i++)
2347 		cec_write(sd, i, msg->msg[i]);
2348 
2349 	/* set length (data + header) */
2350 	cec_write(sd, 0x10, len);
2351 	/* start transmit, enable tx */
2352 	cec_write(sd, 0x11, 0x01);
2353 	return 0;
2354 }
2355 
2356 static const struct cec_adap_ops adv7842_cec_adap_ops = {
2357 	.adap_enable = adv7842_cec_adap_enable,
2358 	.adap_log_addr = adv7842_cec_adap_log_addr,
2359 	.adap_transmit = adv7842_cec_adap_transmit,
2360 };
2361 #endif
2362 
2363 static int adv7842_isr(struct v4l2_subdev *sd, u32 status, bool *handled)
2364 {
2365 	struct adv7842_state *state = to_state(sd);
2366 	u8 fmt_change_cp, fmt_change_digital, fmt_change_sdp;
2367 	u8 irq_status[6];
2368 
2369 	adv7842_irq_enable(sd, false);
2370 
2371 	/* read status */
2372 	irq_status[0] = io_read(sd, 0x43);
2373 	irq_status[1] = io_read(sd, 0x57);
2374 	irq_status[2] = io_read(sd, 0x70);
2375 	irq_status[3] = io_read(sd, 0x75);
2376 	irq_status[4] = io_read(sd, 0x9d);
2377 	irq_status[5] = io_read(sd, 0x66);
2378 
2379 	/* and clear */
2380 	if (irq_status[0])
2381 		io_write(sd, 0x44, irq_status[0]);
2382 	if (irq_status[1])
2383 		io_write(sd, 0x58, irq_status[1]);
2384 	if (irq_status[2])
2385 		io_write(sd, 0x71, irq_status[2]);
2386 	if (irq_status[3])
2387 		io_write(sd, 0x76, irq_status[3]);
2388 	if (irq_status[4])
2389 		io_write(sd, 0x9e, irq_status[4]);
2390 	if (irq_status[5])
2391 		io_write(sd, 0x67, irq_status[5]);
2392 
2393 	adv7842_irq_enable(sd, true);
2394 
2395 	v4l2_dbg(1, debug, sd, "%s: irq %x, %x, %x, %x, %x, %x\n", __func__,
2396 		 irq_status[0], irq_status[1], irq_status[2],
2397 		 irq_status[3], irq_status[4], irq_status[5]);
2398 
2399 	/* format change CP */
2400 	fmt_change_cp = irq_status[0] & 0x9c;
2401 
2402 	/* format change SDP */
2403 	if (state->mode == ADV7842_MODE_SDP)
2404 		fmt_change_sdp = (irq_status[1] & 0x30) | (irq_status[4] & 0x09);
2405 	else
2406 		fmt_change_sdp = 0;
2407 
2408 	/* digital format CP */
2409 	if (is_digital_input(sd))
2410 		fmt_change_digital = irq_status[3] & 0x03;
2411 	else
2412 		fmt_change_digital = 0;
2413 
2414 	/* format change */
2415 	if (fmt_change_cp || fmt_change_digital || fmt_change_sdp) {
2416 		v4l2_dbg(1, debug, sd,
2417 			 "%s: fmt_change_cp = 0x%x, fmt_change_digital = 0x%x, fmt_change_sdp = 0x%x\n",
2418 			 __func__, fmt_change_cp, fmt_change_digital,
2419 			 fmt_change_sdp);
2420 		v4l2_subdev_notify_event(sd, &adv7842_ev_fmt);
2421 		if (handled)
2422 			*handled = true;
2423 	}
2424 
2425 	/* HDMI/DVI mode */
2426 	if (irq_status[5] & 0x08) {
2427 		v4l2_dbg(1, debug, sd, "%s: irq %s mode\n", __func__,
2428 			 (io_read(sd, 0x65) & 0x08) ? "HDMI" : "DVI");
2429 		set_rgb_quantization_range(sd);
2430 		if (handled)
2431 			*handled = true;
2432 	}
2433 
2434 #if IS_ENABLED(CONFIG_VIDEO_ADV7842_CEC)
2435 	/* cec */
2436 	adv7842_cec_isr(sd, handled);
2437 #endif
2438 
2439 	/* tx 5v detect */
2440 	if (irq_status[2] & 0x3) {
2441 		v4l2_dbg(1, debug, sd, "%s: irq tx_5v\n", __func__);
2442 		adv7842_s_detect_tx_5v_ctrl(sd);
2443 		if (handled)
2444 			*handled = true;
2445 	}
2446 	return 0;
2447 }
2448 
2449 static int adv7842_get_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid)
2450 {
2451 	struct adv7842_state *state = to_state(sd);
2452 	u32 blocks = 0;
2453 	u8 *data = NULL;
2454 
2455 	memset(edid->reserved, 0, sizeof(edid->reserved));
2456 
2457 	switch (edid->pad) {
2458 	case ADV7842_EDID_PORT_A:
2459 	case ADV7842_EDID_PORT_B:
2460 		if (state->hdmi_edid.present & (0x04 << edid->pad)) {
2461 			data = state->hdmi_edid.edid;
2462 			blocks = state->hdmi_edid.blocks;
2463 		}
2464 		break;
2465 	case ADV7842_EDID_PORT_VGA:
2466 		if (state->vga_edid.present) {
2467 			data = state->vga_edid.edid;
2468 			blocks = state->vga_edid.blocks;
2469 		}
2470 		break;
2471 	default:
2472 		return -EINVAL;
2473 	}
2474 
2475 	if (edid->start_block == 0 && edid->blocks == 0) {
2476 		edid->blocks = blocks;
2477 		return 0;
2478 	}
2479 
2480 	if (!data)
2481 		return -ENODATA;
2482 
2483 	if (edid->start_block >= blocks)
2484 		return -EINVAL;
2485 
2486 	if (edid->start_block + edid->blocks > blocks)
2487 		edid->blocks = blocks - edid->start_block;
2488 
2489 	memcpy(edid->edid, data + edid->start_block * 128, edid->blocks * 128);
2490 
2491 	return 0;
2492 }
2493 
2494 static int adv7842_set_edid(struct v4l2_subdev *sd, struct v4l2_edid *e)
2495 {
2496 	struct adv7842_state *state = to_state(sd);
2497 	int err = 0;
2498 
2499 	memset(e->reserved, 0, sizeof(e->reserved));
2500 
2501 	if (e->pad > ADV7842_EDID_PORT_VGA)
2502 		return -EINVAL;
2503 	if (e->start_block != 0)
2504 		return -EINVAL;
2505 	if (e->blocks > 2) {
2506 		e->blocks = 2;
2507 		return -E2BIG;
2508 	}
2509 
2510 	/* todo, per edid */
2511 	if (e->blocks)
2512 		state->aspect_ratio = v4l2_calc_aspect_ratio(e->edid[0x15],
2513 							     e->edid[0x16]);
2514 
2515 	switch (e->pad) {
2516 	case ADV7842_EDID_PORT_VGA:
2517 		memset(&state->vga_edid.edid, 0, 256);
2518 		state->vga_edid.blocks = e->blocks;
2519 		state->vga_edid.present = e->blocks ? 0x1 : 0x0;
2520 		if (e->blocks)
2521 			memcpy(&state->vga_edid.edid, e->edid, 128 * e->blocks);
2522 		err = edid_write_vga_segment(sd);
2523 		break;
2524 	case ADV7842_EDID_PORT_A:
2525 	case ADV7842_EDID_PORT_B:
2526 		memset(&state->hdmi_edid.edid, 0, 256);
2527 		state->hdmi_edid.blocks = e->blocks;
2528 		if (e->blocks) {
2529 			state->hdmi_edid.present |= 0x04 << e->pad;
2530 			memcpy(&state->hdmi_edid.edid, e->edid, 128 * e->blocks);
2531 		} else {
2532 			state->hdmi_edid.present &= ~(0x04 << e->pad);
2533 			adv7842_s_detect_tx_5v_ctrl(sd);
2534 		}
2535 		err = edid_write_hdmi_segment(sd, e->pad);
2536 		break;
2537 	default:
2538 		return -EINVAL;
2539 	}
2540 	if (err < 0)
2541 		v4l2_err(sd, "error %d writing edid on port %d\n", err, e->pad);
2542 	return err;
2543 }
2544 
2545 struct adv7842_cfg_read_infoframe {
2546 	const char *desc;
2547 	u8 present_mask;
2548 	u8 head_addr;
2549 	u8 payload_addr;
2550 };
2551 
2552 static void log_infoframe(struct v4l2_subdev *sd, const struct adv7842_cfg_read_infoframe *cri)
2553 {
2554 	int i;
2555 	u8 buffer[32];
2556 	union hdmi_infoframe frame;
2557 	u8 len;
2558 	struct i2c_client *client = v4l2_get_subdevdata(sd);
2559 	struct device *dev = &client->dev;
2560 
2561 	if (!(io_read(sd, 0x60) & cri->present_mask)) {
2562 		v4l2_info(sd, "%s infoframe not received\n", cri->desc);
2563 		return;
2564 	}
2565 
2566 	for (i = 0; i < 3; i++)
2567 		buffer[i] = infoframe_read(sd, cri->head_addr + i);
2568 
2569 	len = buffer[2] + 1;
2570 
2571 	if (len + 3 > sizeof(buffer)) {
2572 		v4l2_err(sd, "%s: invalid %s infoframe length %d\n", __func__, cri->desc, len);
2573 		return;
2574 	}
2575 
2576 	for (i = 0; i < len; i++)
2577 		buffer[i + 3] = infoframe_read(sd, cri->payload_addr + i);
2578 
2579 	if (hdmi_infoframe_unpack(&frame, buffer, sizeof(buffer)) < 0) {
2580 		v4l2_err(sd, "%s: unpack of %s infoframe failed\n", __func__, cri->desc);
2581 		return;
2582 	}
2583 
2584 	hdmi_infoframe_log(KERN_INFO, dev, &frame);
2585 }
2586 
2587 static void adv7842_log_infoframes(struct v4l2_subdev *sd)
2588 {
2589 	int i;
2590 	static const struct adv7842_cfg_read_infoframe cri[] = {
2591 		{ "AVI", 0x01, 0xe0, 0x00 },
2592 		{ "Audio", 0x02, 0xe3, 0x1c },
2593 		{ "SDP", 0x04, 0xe6, 0x2a },
2594 		{ "Vendor", 0x10, 0xec, 0x54 }
2595 	};
2596 
2597 	if (!(hdmi_read(sd, 0x05) & 0x80)) {
2598 		v4l2_info(sd, "receive DVI-D signal, no infoframes\n");
2599 		return;
2600 	}
2601 
2602 	for (i = 0; i < ARRAY_SIZE(cri); i++)
2603 		log_infoframe(sd, &cri[i]);
2604 }
2605 
2606 #if 0
2607 /* Let's keep it here for now, as it could be useful for debug */
2608 static const char * const prim_mode_txt[] = {
2609 	"SDP",
2610 	"Component",
2611 	"Graphics",
2612 	"Reserved",
2613 	"CVBS & HDMI AUDIO",
2614 	"HDMI-Comp",
2615 	"HDMI-GR",
2616 	"Reserved",
2617 	"Reserved",
2618 	"Reserved",
2619 	"Reserved",
2620 	"Reserved",
2621 	"Reserved",
2622 	"Reserved",
2623 	"Reserved",
2624 	"Reserved",
2625 };
2626 #endif
2627 
2628 static int adv7842_sdp_log_status(struct v4l2_subdev *sd)
2629 {
2630 	/* SDP (Standard definition processor) block */
2631 	u8 sdp_signal_detected = sdp_read(sd, 0x5A) & 0x01;
2632 
2633 	v4l2_info(sd, "Chip powered %s\n", no_power(sd) ? "off" : "on");
2634 	v4l2_info(sd, "Prim-mode = 0x%x, video std = 0x%x\n",
2635 		  io_read(sd, 0x01) & 0x0f, io_read(sd, 0x00) & 0x3f);
2636 
2637 	v4l2_info(sd, "SDP: free run: %s\n",
2638 		(sdp_read(sd, 0x56) & 0x01) ? "on" : "off");
2639 	v4l2_info(sd, "SDP: %s\n", sdp_signal_detected ?
2640 		"valid SD/PR signal detected" : "invalid/no signal");
2641 	if (sdp_signal_detected) {
2642 		static const char * const sdp_std_txt[] = {
2643 			"NTSC-M/J",
2644 			"1?",
2645 			"NTSC-443",
2646 			"60HzSECAM",
2647 			"PAL-M",
2648 			"5?",
2649 			"PAL-60",
2650 			"7?", "8?", "9?", "a?", "b?",
2651 			"PAL-CombN",
2652 			"d?",
2653 			"PAL-BGHID",
2654 			"SECAM"
2655 		};
2656 		v4l2_info(sd, "SDP: standard %s\n",
2657 			sdp_std_txt[sdp_read(sd, 0x52) & 0x0f]);
2658 		v4l2_info(sd, "SDP: %s\n",
2659 			(sdp_read(sd, 0x59) & 0x08) ? "50Hz" : "60Hz");
2660 		v4l2_info(sd, "SDP: %s\n",
2661 			(sdp_read(sd, 0x57) & 0x08) ? "Interlaced" : "Progressive");
2662 		v4l2_info(sd, "SDP: deinterlacer %s\n",
2663 			(sdp_read(sd, 0x12) & 0x08) ? "enabled" : "disabled");
2664 		v4l2_info(sd, "SDP: csc %s mode\n",
2665 			(sdp_io_read(sd, 0xe0) & 0x40) ? "auto" : "manual");
2666 	}
2667 	return 0;
2668 }
2669 
2670 static int adv7842_cp_log_status(struct v4l2_subdev *sd)
2671 {
2672 	/* CP block */
2673 	struct adv7842_state *state = to_state(sd);
2674 	struct v4l2_dv_timings timings;
2675 	u8 reg_io_0x02 = io_read(sd, 0x02);
2676 	u8 reg_io_0x21 = io_read(sd, 0x21);
2677 	u8 reg_rep_0x77 = rep_read(sd, 0x77);
2678 	u8 reg_rep_0x7d = rep_read(sd, 0x7d);
2679 	bool audio_pll_locked = hdmi_read(sd, 0x04) & 0x01;
2680 	bool audio_sample_packet_detect = hdmi_read(sd, 0x18) & 0x01;
2681 	bool audio_mute = io_read(sd, 0x65) & 0x40;
2682 
2683 	static const char * const csc_coeff_sel_rb[16] = {
2684 		"bypassed", "YPbPr601 -> RGB", "reserved", "YPbPr709 -> RGB",
2685 		"reserved", "RGB -> YPbPr601", "reserved", "RGB -> YPbPr709",
2686 		"reserved", "YPbPr709 -> YPbPr601", "YPbPr601 -> YPbPr709",
2687 		"reserved", "reserved", "reserved", "reserved", "manual"
2688 	};
2689 	static const char * const input_color_space_txt[16] = {
2690 		"RGB limited range (16-235)", "RGB full range (0-255)",
2691 		"YCbCr Bt.601 (16-235)", "YCbCr Bt.709 (16-235)",
2692 		"xvYCC Bt.601", "xvYCC Bt.709",
2693 		"YCbCr Bt.601 (0-255)", "YCbCr Bt.709 (0-255)",
2694 		"invalid", "invalid", "invalid", "invalid", "invalid",
2695 		"invalid", "invalid", "automatic"
2696 	};
2697 	static const char * const rgb_quantization_range_txt[] = {
2698 		"Automatic",
2699 		"RGB limited range (16-235)",
2700 		"RGB full range (0-255)",
2701 	};
2702 	static const char * const deep_color_mode_txt[4] = {
2703 		"8-bits per channel",
2704 		"10-bits per channel",
2705 		"12-bits per channel",
2706 		"16-bits per channel (not supported)"
2707 	};
2708 
2709 	v4l2_info(sd, "-----Chip status-----\n");
2710 	v4l2_info(sd, "Chip power: %s\n", no_power(sd) ? "off" : "on");
2711 	v4l2_info(sd, "HDMI/DVI-D port selected: %s\n",
2712 			state->hdmi_port_a ? "A" : "B");
2713 	v4l2_info(sd, "EDID A %s, B %s\n",
2714 		  ((reg_rep_0x7d & 0x04) && (reg_rep_0x77 & 0x04)) ?
2715 		  "enabled" : "disabled",
2716 		  ((reg_rep_0x7d & 0x08) && (reg_rep_0x77 & 0x08)) ?
2717 		  "enabled" : "disabled");
2718 	v4l2_info(sd, "HPD A %s, B %s\n",
2719 		  reg_io_0x21 & 0x02 ? "enabled" : "disabled",
2720 		  reg_io_0x21 & 0x01 ? "enabled" : "disabled");
2721 	v4l2_info(sd, "CEC: %s\n", state->cec_enabled_adap ?
2722 			"enabled" : "disabled");
2723 	if (state->cec_enabled_adap) {
2724 		int i;
2725 
2726 		for (i = 0; i < ADV7842_MAX_ADDRS; i++) {
2727 			bool is_valid = state->cec_valid_addrs & (1 << i);
2728 
2729 			if (is_valid)
2730 				v4l2_info(sd, "CEC Logical Address: 0x%x\n",
2731 					  state->cec_addr[i]);
2732 		}
2733 	}
2734 
2735 	v4l2_info(sd, "-----Signal status-----\n");
2736 	if (state->hdmi_port_a) {
2737 		v4l2_info(sd, "Cable detected (+5V power): %s\n",
2738 			  io_read(sd, 0x6f) & 0x02 ? "true" : "false");
2739 		v4l2_info(sd, "TMDS signal detected: %s\n",
2740 			  (io_read(sd, 0x6a) & 0x02) ? "true" : "false");
2741 		v4l2_info(sd, "TMDS signal locked: %s\n",
2742 			  (io_read(sd, 0x6a) & 0x20) ? "true" : "false");
2743 	} else {
2744 		v4l2_info(sd, "Cable detected (+5V power):%s\n",
2745 			  io_read(sd, 0x6f) & 0x01 ? "true" : "false");
2746 		v4l2_info(sd, "TMDS signal detected: %s\n",
2747 			  (io_read(sd, 0x6a) & 0x01) ? "true" : "false");
2748 		v4l2_info(sd, "TMDS signal locked: %s\n",
2749 			  (io_read(sd, 0x6a) & 0x10) ? "true" : "false");
2750 	}
2751 	v4l2_info(sd, "CP free run: %s\n",
2752 		  (!!(cp_read(sd, 0xff) & 0x10) ? "on" : "off"));
2753 	v4l2_info(sd, "Prim-mode = 0x%x, video std = 0x%x, v_freq = 0x%x\n",
2754 		  io_read(sd, 0x01) & 0x0f, io_read(sd, 0x00) & 0x3f,
2755 		  (io_read(sd, 0x01) & 0x70) >> 4);
2756 
2757 	v4l2_info(sd, "-----Video Timings-----\n");
2758 	if (no_cp_signal(sd)) {
2759 		v4l2_info(sd, "STDI: not locked\n");
2760 	} else {
2761 		u32 bl = ((cp_read(sd, 0xb1) & 0x3f) << 8) | cp_read(sd, 0xb2);
2762 		u32 lcf = ((cp_read(sd, 0xb3) & 0x7) << 8) | cp_read(sd, 0xb4);
2763 		u32 lcvs = cp_read(sd, 0xb3) >> 3;
2764 		u32 fcl = ((cp_read(sd, 0xb8) & 0x1f) << 8) | cp_read(sd, 0xb9);
2765 		char hs_pol = ((cp_read(sd, 0xb5) & 0x10) ?
2766 				((cp_read(sd, 0xb5) & 0x08) ? '+' : '-') : 'x');
2767 		char vs_pol = ((cp_read(sd, 0xb5) & 0x40) ?
2768 				((cp_read(sd, 0xb5) & 0x20) ? '+' : '-') : 'x');
2769 		v4l2_info(sd,
2770 			"STDI: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, fcl = %d, %s, %chsync, %cvsync\n",
2771 			lcf, bl, lcvs, fcl,
2772 			(cp_read(sd, 0xb1) & 0x40) ?
2773 				"interlaced" : "progressive",
2774 			hs_pol, vs_pol);
2775 	}
2776 	if (adv7842_query_dv_timings(sd, &timings))
2777 		v4l2_info(sd, "No video detected\n");
2778 	else
2779 		v4l2_print_dv_timings(sd->name, "Detected format: ",
2780 				      &timings, true);
2781 	v4l2_print_dv_timings(sd->name, "Configured format: ",
2782 			&state->timings, true);
2783 
2784 	if (no_cp_signal(sd))
2785 		return 0;
2786 
2787 	v4l2_info(sd, "-----Color space-----\n");
2788 	v4l2_info(sd, "RGB quantization range ctrl: %s\n",
2789 		  rgb_quantization_range_txt[state->rgb_quantization_range]);
2790 	v4l2_info(sd, "Input color space: %s\n",
2791 		  input_color_space_txt[reg_io_0x02 >> 4]);
2792 	v4l2_info(sd, "Output color space: %s %s, alt-gamma %s\n",
2793 		  (reg_io_0x02 & 0x02) ? "RGB" : "YCbCr",
2794 		  (((reg_io_0x02 >> 2) & 0x01) ^ (reg_io_0x02 & 0x01)) ?
2795 			"(16-235)" : "(0-255)",
2796 		  (reg_io_0x02 & 0x08) ? "enabled" : "disabled");
2797 	v4l2_info(sd, "Color space conversion: %s\n",
2798 		  csc_coeff_sel_rb[cp_read(sd, 0xf4) >> 4]);
2799 
2800 	if (!is_digital_input(sd))
2801 		return 0;
2802 
2803 	v4l2_info(sd, "-----%s status-----\n", is_hdmi(sd) ? "HDMI" : "DVI-D");
2804 	v4l2_info(sd, "HDCP encrypted content: %s\n",
2805 			(hdmi_read(sd, 0x05) & 0x40) ? "true" : "false");
2806 	v4l2_info(sd, "HDCP keys read: %s%s\n",
2807 			(hdmi_read(sd, 0x04) & 0x20) ? "yes" : "no",
2808 			(hdmi_read(sd, 0x04) & 0x10) ? "ERROR" : "");
2809 	if (!is_hdmi(sd))
2810 		return 0;
2811 
2812 	v4l2_info(sd, "Audio: pll %s, samples %s, %s\n",
2813 			audio_pll_locked ? "locked" : "not locked",
2814 			audio_sample_packet_detect ? "detected" : "not detected",
2815 			audio_mute ? "muted" : "enabled");
2816 	if (audio_pll_locked && audio_sample_packet_detect) {
2817 		v4l2_info(sd, "Audio format: %s\n",
2818 			(hdmi_read(sd, 0x07) & 0x40) ? "multi-channel" : "stereo");
2819 	}
2820 	v4l2_info(sd, "Audio CTS: %u\n", (hdmi_read(sd, 0x5b) << 12) +
2821 			(hdmi_read(sd, 0x5c) << 8) +
2822 			(hdmi_read(sd, 0x5d) & 0xf0));
2823 	v4l2_info(sd, "Audio N: %u\n", ((hdmi_read(sd, 0x5d) & 0x0f) << 16) +
2824 			(hdmi_read(sd, 0x5e) << 8) +
2825 			hdmi_read(sd, 0x5f));
2826 	v4l2_info(sd, "AV Mute: %s\n",
2827 			(hdmi_read(sd, 0x04) & 0x40) ? "on" : "off");
2828 	v4l2_info(sd, "Deep color mode: %s\n",
2829 			deep_color_mode_txt[hdmi_read(sd, 0x0b) >> 6]);
2830 
2831 	adv7842_log_infoframes(sd);
2832 
2833 	return 0;
2834 }
2835 
2836 static int adv7842_log_status(struct v4l2_subdev *sd)
2837 {
2838 	struct adv7842_state *state = to_state(sd);
2839 
2840 	if (state->mode == ADV7842_MODE_SDP)
2841 		return adv7842_sdp_log_status(sd);
2842 	return adv7842_cp_log_status(sd);
2843 }
2844 
2845 static int adv7842_querystd(struct v4l2_subdev *sd, v4l2_std_id *std)
2846 {
2847 	struct adv7842_state *state = to_state(sd);
2848 
2849 	v4l2_dbg(1, debug, sd, "%s:\n", __func__);
2850 
2851 	if (state->mode != ADV7842_MODE_SDP)
2852 		return -ENODATA;
2853 
2854 	if (!(sdp_read(sd, 0x5A) & 0x01)) {
2855 		*std = 0;
2856 		v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__);
2857 		return 0;
2858 	}
2859 
2860 	switch (sdp_read(sd, 0x52) & 0x0f) {
2861 	case 0:
2862 		/* NTSC-M/J */
2863 		*std &= V4L2_STD_NTSC;
2864 		break;
2865 	case 2:
2866 		/* NTSC-443 */
2867 		*std &= V4L2_STD_NTSC_443;
2868 		break;
2869 	case 3:
2870 		/* 60HzSECAM */
2871 		*std &= V4L2_STD_SECAM;
2872 		break;
2873 	case 4:
2874 		/* PAL-M */
2875 		*std &= V4L2_STD_PAL_M;
2876 		break;
2877 	case 6:
2878 		/* PAL-60 */
2879 		*std &= V4L2_STD_PAL_60;
2880 		break;
2881 	case 0xc:
2882 		/* PAL-CombN */
2883 		*std &= V4L2_STD_PAL_Nc;
2884 		break;
2885 	case 0xe:
2886 		/* PAL-BGHID */
2887 		*std &= V4L2_STD_PAL;
2888 		break;
2889 	case 0xf:
2890 		/* SECAM */
2891 		*std &= V4L2_STD_SECAM;
2892 		break;
2893 	default:
2894 		*std &= V4L2_STD_ALL;
2895 		break;
2896 	}
2897 	return 0;
2898 }
2899 
2900 static void adv7842_s_sdp_io(struct v4l2_subdev *sd, struct adv7842_sdp_io_sync_adjustment *s)
2901 {
2902 	if (s && s->adjust) {
2903 		sdp_io_write(sd, 0x94, (s->hs_beg >> 8) & 0xf);
2904 		sdp_io_write(sd, 0x95, s->hs_beg & 0xff);
2905 		sdp_io_write(sd, 0x96, (s->hs_width >> 8) & 0xf);
2906 		sdp_io_write(sd, 0x97, s->hs_width & 0xff);
2907 		sdp_io_write(sd, 0x98, (s->de_beg >> 8) & 0xf);
2908 		sdp_io_write(sd, 0x99, s->de_beg & 0xff);
2909 		sdp_io_write(sd, 0x9a, (s->de_end >> 8) & 0xf);
2910 		sdp_io_write(sd, 0x9b, s->de_end & 0xff);
2911 		sdp_io_write(sd, 0xa8, s->vs_beg_o);
2912 		sdp_io_write(sd, 0xa9, s->vs_beg_e);
2913 		sdp_io_write(sd, 0xaa, s->vs_end_o);
2914 		sdp_io_write(sd, 0xab, s->vs_end_e);
2915 		sdp_io_write(sd, 0xac, s->de_v_beg_o);
2916 		sdp_io_write(sd, 0xad, s->de_v_beg_e);
2917 		sdp_io_write(sd, 0xae, s->de_v_end_o);
2918 		sdp_io_write(sd, 0xaf, s->de_v_end_e);
2919 	} else {
2920 		/* set to default */
2921 		sdp_io_write(sd, 0x94, 0x00);
2922 		sdp_io_write(sd, 0x95, 0x00);
2923 		sdp_io_write(sd, 0x96, 0x00);
2924 		sdp_io_write(sd, 0x97, 0x20);
2925 		sdp_io_write(sd, 0x98, 0x00);
2926 		sdp_io_write(sd, 0x99, 0x00);
2927 		sdp_io_write(sd, 0x9a, 0x00);
2928 		sdp_io_write(sd, 0x9b, 0x00);
2929 		sdp_io_write(sd, 0xa8, 0x04);
2930 		sdp_io_write(sd, 0xa9, 0x04);
2931 		sdp_io_write(sd, 0xaa, 0x04);
2932 		sdp_io_write(sd, 0xab, 0x04);
2933 		sdp_io_write(sd, 0xac, 0x04);
2934 		sdp_io_write(sd, 0xad, 0x04);
2935 		sdp_io_write(sd, 0xae, 0x04);
2936 		sdp_io_write(sd, 0xaf, 0x04);
2937 	}
2938 }
2939 
2940 static int adv7842_s_std(struct v4l2_subdev *sd, v4l2_std_id norm)
2941 {
2942 	struct adv7842_state *state = to_state(sd);
2943 	struct adv7842_platform_data *pdata = &state->pdata;
2944 
2945 	v4l2_dbg(1, debug, sd, "%s:\n", __func__);
2946 
2947 	if (state->mode != ADV7842_MODE_SDP)
2948 		return -ENODATA;
2949 
2950 	if (norm & V4L2_STD_625_50)
2951 		adv7842_s_sdp_io(sd, &pdata->sdp_io_sync_625);
2952 	else if (norm & V4L2_STD_525_60)
2953 		adv7842_s_sdp_io(sd, &pdata->sdp_io_sync_525);
2954 	else
2955 		adv7842_s_sdp_io(sd, NULL);
2956 
2957 	if (norm & V4L2_STD_ALL) {
2958 		state->norm = norm;
2959 		return 0;
2960 	}
2961 	return -EINVAL;
2962 }
2963 
2964 static int adv7842_g_std(struct v4l2_subdev *sd, v4l2_std_id *norm)
2965 {
2966 	struct adv7842_state *state = to_state(sd);
2967 
2968 	v4l2_dbg(1, debug, sd, "%s:\n", __func__);
2969 
2970 	if (state->mode != ADV7842_MODE_SDP)
2971 		return -ENODATA;
2972 
2973 	*norm = state->norm;
2974 	return 0;
2975 }
2976 
2977 /* ----------------------------------------------------------------------- */
2978 
2979 static int adv7842_core_init(struct v4l2_subdev *sd)
2980 {
2981 	struct adv7842_state *state = to_state(sd);
2982 	struct adv7842_platform_data *pdata = &state->pdata;
2983 	hdmi_write(sd, 0x48,
2984 		   (pdata->disable_pwrdnb ? 0x80 : 0) |
2985 		   (pdata->disable_cable_det_rst ? 0x40 : 0));
2986 
2987 	disable_input(sd);
2988 
2989 	/*
2990 	 * Disable I2C access to internal EDID ram from HDMI DDC ports
2991 	 * Disable auto edid enable when leaving powerdown mode
2992 	 */
2993 	rep_write_and_or(sd, 0x77, 0xd3, 0x20);
2994 
2995 	/* power */
2996 	io_write(sd, 0x0c, 0x42);   /* Power up part and power down VDP */
2997 	io_write(sd, 0x15, 0x80);   /* Power up pads */
2998 
2999 	/* video format */
3000 	io_write(sd, 0x02, 0xf0 | pdata->alt_gamma << 3);
3001 	io_write_and_or(sd, 0x05, 0xf0, pdata->blank_data << 3 |
3002 			pdata->insert_av_codes << 2 |
3003 			pdata->replicate_av_codes << 1);
3004 	adv7842_setup_format(state);
3005 
3006 	/* HDMI audio */
3007 	hdmi_write_and_or(sd, 0x1a, 0xf1, 0x08); /* Wait 1 s before unmute */
3008 
3009 	/* Drive strength */
3010 	io_write_and_or(sd, 0x14, 0xc0,
3011 			pdata->dr_str_data << 4 |
3012 			pdata->dr_str_clk << 2 |
3013 			pdata->dr_str_sync);
3014 
3015 	/* HDMI free run */
3016 	cp_write_and_or(sd, 0xba, 0xfc, pdata->hdmi_free_run_enable |
3017 					(pdata->hdmi_free_run_mode << 1));
3018 
3019 	/* SPD free run */
3020 	sdp_write_and_or(sd, 0xdd, 0xf0, pdata->sdp_free_run_force |
3021 					 (pdata->sdp_free_run_cbar_en << 1) |
3022 					 (pdata->sdp_free_run_man_col_en << 2) |
3023 					 (pdata->sdp_free_run_auto << 3));
3024 
3025 	/* TODO from platform data */
3026 	cp_write(sd, 0x69, 0x14);   /* Enable CP CSC */
3027 	io_write(sd, 0x06, 0xa6);   /* positive VS and HS and DE */
3028 	cp_write(sd, 0xf3, 0xdc); /* Low threshold to enter/exit free run mode */
3029 	afe_write(sd, 0xb5, 0x01);  /* Setting MCLK to 256Fs */
3030 
3031 	afe_write(sd, 0x02, pdata->ain_sel); /* Select analog input muxing mode */
3032 	io_write_and_or(sd, 0x30, ~(1 << 4), pdata->output_bus_lsb_to_msb << 4);
3033 
3034 	sdp_csc_coeff(sd, &pdata->sdp_csc_coeff);
3035 
3036 	/* todo, improve settings for sdram */
3037 	if (pdata->sd_ram_size >= 128) {
3038 		sdp_write(sd, 0x12, 0x0d); /* Frame TBC,3D comb enabled */
3039 		if (pdata->sd_ram_ddr) {
3040 			/* SDP setup for the AD eval board */
3041 			sdp_io_write(sd, 0x6f, 0x00); /* DDR mode */
3042 			sdp_io_write(sd, 0x75, 0x0a); /* 128 MB memory size */
3043 			sdp_io_write(sd, 0x7a, 0xa5); /* Timing Adjustment */
3044 			sdp_io_write(sd, 0x7b, 0x8f); /* Timing Adjustment */
3045 			sdp_io_write(sd, 0x60, 0x01); /* SDRAM reset */
3046 		} else {
3047 			sdp_io_write(sd, 0x75, 0x0a); /* 64 MB memory size ?*/
3048 			sdp_io_write(sd, 0x74, 0x00); /* must be zero for sdr sdram */
3049 			sdp_io_write(sd, 0x79, 0x33); /* CAS latency to 3,
3050 							 depends on memory */
3051 			sdp_io_write(sd, 0x6f, 0x01); /* SDR mode */
3052 			sdp_io_write(sd, 0x7a, 0xa5); /* Timing Adjustment */
3053 			sdp_io_write(sd, 0x7b, 0x8f); /* Timing Adjustment */
3054 			sdp_io_write(sd, 0x60, 0x01); /* SDRAM reset */
3055 		}
3056 	} else {
3057 		/*
3058 		 * Manual UG-214, rev 0 is bit confusing on this bit
3059 		 * but a '1' disables any signal if the Ram is active.
3060 		 */
3061 		sdp_io_write(sd, 0x29, 0x10); /* Tristate memory interface */
3062 	}
3063 
3064 	select_input(sd, pdata->vid_std_select);
3065 
3066 	enable_input(sd);
3067 
3068 	if (pdata->hpa_auto) {
3069 		/* HPA auto, HPA 0.5s after Edid set and Cable detect */
3070 		hdmi_write(sd, 0x69, 0x5c);
3071 	} else {
3072 		/* HPA manual */
3073 		hdmi_write(sd, 0x69, 0xa3);
3074 		/* HPA disable on port A and B */
3075 		io_write_and_or(sd, 0x20, 0xcf, 0x00);
3076 	}
3077 
3078 	/* LLC */
3079 	io_write(sd, 0x19, 0x80 | pdata->llc_dll_phase);
3080 	io_write(sd, 0x33, 0x40);
3081 
3082 	/* interrupts */
3083 	io_write(sd, 0x40, 0xf2); /* Configure INT1 */
3084 
3085 	adv7842_irq_enable(sd, true);
3086 
3087 	return v4l2_ctrl_handler_setup(sd->ctrl_handler);
3088 }
3089 
3090 /* ----------------------------------------------------------------------- */
3091 
3092 static int adv7842_ddr_ram_test(struct v4l2_subdev *sd)
3093 {
3094 	/*
3095 	 * From ADV784x external Memory test.pdf
3096 	 *
3097 	 * Reset must just been performed before running test.
3098 	 * Recommended to reset after test.
3099 	 */
3100 	int i;
3101 	int pass = 0;
3102 	int fail = 0;
3103 	int complete = 0;
3104 
3105 	io_write(sd, 0x00, 0x01);  /* Program SDP 4x1 */
3106 	io_write(sd, 0x01, 0x00);  /* Program SDP mode */
3107 	afe_write(sd, 0x80, 0x92); /* SDP Recommended Write */
3108 	afe_write(sd, 0x9B, 0x01); /* SDP Recommended Write ADV7844ES1 */
3109 	afe_write(sd, 0x9C, 0x60); /* SDP Recommended Write ADV7844ES1 */
3110 	afe_write(sd, 0x9E, 0x02); /* SDP Recommended Write ADV7844ES1 */
3111 	afe_write(sd, 0xA0, 0x0B); /* SDP Recommended Write ADV7844ES1 */
3112 	afe_write(sd, 0xC3, 0x02); /* Memory BIST Initialisation */
3113 	io_write(sd, 0x0C, 0x40);  /* Power up ADV7844 */
3114 	io_write(sd, 0x15, 0xBA);  /* Enable outputs */
3115 	sdp_write(sd, 0x12, 0x00); /* Disable 3D comb, Frame TBC & 3DNR */
3116 	io_write(sd, 0xFF, 0x04);  /* Reset memory controller */
3117 
3118 	usleep_range(5000, 6000);
3119 
3120 	sdp_write(sd, 0x12, 0x00);    /* Disable 3D Comb, Frame TBC & 3DNR */
3121 	sdp_io_write(sd, 0x2A, 0x01); /* Memory BIST Initialisation */
3122 	sdp_io_write(sd, 0x7c, 0x19); /* Memory BIST Initialisation */
3123 	sdp_io_write(sd, 0x80, 0x87); /* Memory BIST Initialisation */
3124 	sdp_io_write(sd, 0x81, 0x4a); /* Memory BIST Initialisation */
3125 	sdp_io_write(sd, 0x82, 0x2c); /* Memory BIST Initialisation */
3126 	sdp_io_write(sd, 0x83, 0x0e); /* Memory BIST Initialisation */
3127 	sdp_io_write(sd, 0x84, 0x94); /* Memory BIST Initialisation */
3128 	sdp_io_write(sd, 0x85, 0x62); /* Memory BIST Initialisation */
3129 	sdp_io_write(sd, 0x7d, 0x00); /* Memory BIST Initialisation */
3130 	sdp_io_write(sd, 0x7e, 0x1a); /* Memory BIST Initialisation */
3131 
3132 	usleep_range(5000, 6000);
3133 
3134 	sdp_io_write(sd, 0xd9, 0xd5); /* Enable BIST Test */
3135 	sdp_write(sd, 0x12, 0x05); /* Enable FRAME TBC & 3D COMB */
3136 
3137 	msleep(20);
3138 
3139 	for (i = 0; i < 10; i++) {
3140 		u8 result = sdp_io_read(sd, 0xdb);
3141 		if (result & 0x10) {
3142 			complete++;
3143 			if (result & 0x20)
3144 				fail++;
3145 			else
3146 				pass++;
3147 		}
3148 		msleep(20);
3149 	}
3150 
3151 	v4l2_dbg(1, debug, sd,
3152 		"Ram Test: completed %d of %d: pass %d, fail %d\n",
3153 		complete, i, pass, fail);
3154 
3155 	if (!complete || fail)
3156 		return -EIO;
3157 	return 0;
3158 }
3159 
3160 static void adv7842_rewrite_i2c_addresses(struct v4l2_subdev *sd,
3161 		struct adv7842_platform_data *pdata)
3162 {
3163 	io_write(sd, 0xf1, pdata->i2c_sdp << 1);
3164 	io_write(sd, 0xf2, pdata->i2c_sdp_io << 1);
3165 	io_write(sd, 0xf3, pdata->i2c_avlink << 1);
3166 	io_write(sd, 0xf4, pdata->i2c_cec << 1);
3167 	io_write(sd, 0xf5, pdata->i2c_infoframe << 1);
3168 
3169 	io_write(sd, 0xf8, pdata->i2c_afe << 1);
3170 	io_write(sd, 0xf9, pdata->i2c_repeater << 1);
3171 	io_write(sd, 0xfa, pdata->i2c_edid << 1);
3172 	io_write(sd, 0xfb, pdata->i2c_hdmi << 1);
3173 
3174 	io_write(sd, 0xfd, pdata->i2c_cp << 1);
3175 	io_write(sd, 0xfe, pdata->i2c_vdp << 1);
3176 }
3177 
3178 static int adv7842_command_ram_test(struct v4l2_subdev *sd)
3179 {
3180 	struct i2c_client *client = v4l2_get_subdevdata(sd);
3181 	struct adv7842_state *state = to_state(sd);
3182 	struct adv7842_platform_data *pdata = client->dev.platform_data;
3183 	struct v4l2_dv_timings timings;
3184 	int ret = 0;
3185 
3186 	if (!pdata)
3187 		return -ENODEV;
3188 
3189 	if (!pdata->sd_ram_size || !pdata->sd_ram_ddr) {
3190 		v4l2_info(sd, "no sdram or no ddr sdram\n");
3191 		return -EINVAL;
3192 	}
3193 
3194 	main_reset(sd);
3195 
3196 	adv7842_rewrite_i2c_addresses(sd, pdata);
3197 
3198 	/* run ram test */
3199 	ret = adv7842_ddr_ram_test(sd);
3200 
3201 	main_reset(sd);
3202 
3203 	adv7842_rewrite_i2c_addresses(sd, pdata);
3204 
3205 	/* and re-init chip and state */
3206 	adv7842_core_init(sd);
3207 
3208 	disable_input(sd);
3209 
3210 	select_input(sd, state->vid_std_select);
3211 
3212 	enable_input(sd);
3213 
3214 	edid_write_vga_segment(sd);
3215 	edid_write_hdmi_segment(sd, ADV7842_EDID_PORT_A);
3216 	edid_write_hdmi_segment(sd, ADV7842_EDID_PORT_B);
3217 
3218 	timings = state->timings;
3219 
3220 	memset(&state->timings, 0, sizeof(struct v4l2_dv_timings));
3221 
3222 	adv7842_s_dv_timings(sd, &timings);
3223 
3224 	return ret;
3225 }
3226 
3227 static long adv7842_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
3228 {
3229 	switch (cmd) {
3230 	case ADV7842_CMD_RAM_TEST:
3231 		return adv7842_command_ram_test(sd);
3232 	}
3233 	return -ENOTTY;
3234 }
3235 
3236 static int adv7842_subscribe_event(struct v4l2_subdev *sd,
3237 				   struct v4l2_fh *fh,
3238 				   struct v4l2_event_subscription *sub)
3239 {
3240 	switch (sub->type) {
3241 	case V4L2_EVENT_SOURCE_CHANGE:
3242 		return v4l2_src_change_event_subdev_subscribe(sd, fh, sub);
3243 	case V4L2_EVENT_CTRL:
3244 		return v4l2_ctrl_subdev_subscribe_event(sd, fh, sub);
3245 	default:
3246 		return -EINVAL;
3247 	}
3248 }
3249 
3250 static int adv7842_registered(struct v4l2_subdev *sd)
3251 {
3252 	struct adv7842_state *state = to_state(sd);
3253 	struct i2c_client *client = v4l2_get_subdevdata(sd);
3254 	int err;
3255 
3256 	err = cec_register_adapter(state->cec_adap, &client->dev);
3257 	if (err)
3258 		cec_delete_adapter(state->cec_adap);
3259 	return err;
3260 }
3261 
3262 static void adv7842_unregistered(struct v4l2_subdev *sd)
3263 {
3264 	struct adv7842_state *state = to_state(sd);
3265 
3266 	cec_unregister_adapter(state->cec_adap);
3267 }
3268 
3269 /* ----------------------------------------------------------------------- */
3270 
3271 static const struct v4l2_ctrl_ops adv7842_ctrl_ops = {
3272 	.s_ctrl = adv7842_s_ctrl,
3273 	.g_volatile_ctrl = adv7842_g_volatile_ctrl,
3274 };
3275 
3276 static const struct v4l2_subdev_core_ops adv7842_core_ops = {
3277 	.log_status = adv7842_log_status,
3278 	.ioctl = adv7842_ioctl,
3279 	.interrupt_service_routine = adv7842_isr,
3280 	.subscribe_event = adv7842_subscribe_event,
3281 	.unsubscribe_event = v4l2_event_subdev_unsubscribe,
3282 #ifdef CONFIG_VIDEO_ADV_DEBUG
3283 	.g_register = adv7842_g_register,
3284 	.s_register = adv7842_s_register,
3285 #endif
3286 };
3287 
3288 static const struct v4l2_subdev_video_ops adv7842_video_ops = {
3289 	.g_std = adv7842_g_std,
3290 	.s_std = adv7842_s_std,
3291 	.s_routing = adv7842_s_routing,
3292 	.querystd = adv7842_querystd,
3293 	.g_input_status = adv7842_g_input_status,
3294 	.s_dv_timings = adv7842_s_dv_timings,
3295 	.g_dv_timings = adv7842_g_dv_timings,
3296 	.query_dv_timings = adv7842_query_dv_timings,
3297 };
3298 
3299 static const struct v4l2_subdev_pad_ops adv7842_pad_ops = {
3300 	.enum_mbus_code = adv7842_enum_mbus_code,
3301 	.get_fmt = adv7842_get_format,
3302 	.set_fmt = adv7842_set_format,
3303 	.get_edid = adv7842_get_edid,
3304 	.set_edid = adv7842_set_edid,
3305 	.enum_dv_timings = adv7842_enum_dv_timings,
3306 	.dv_timings_cap = adv7842_dv_timings_cap,
3307 };
3308 
3309 static const struct v4l2_subdev_ops adv7842_ops = {
3310 	.core = &adv7842_core_ops,
3311 	.video = &adv7842_video_ops,
3312 	.pad = &adv7842_pad_ops,
3313 };
3314 
3315 static const struct v4l2_subdev_internal_ops adv7842_int_ops = {
3316 	.registered = adv7842_registered,
3317 	.unregistered = adv7842_unregistered,
3318 };
3319 
3320 /* -------------------------- custom ctrls ---------------------------------- */
3321 
3322 static const struct v4l2_ctrl_config adv7842_ctrl_analog_sampling_phase = {
3323 	.ops = &adv7842_ctrl_ops,
3324 	.id = V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE,
3325 	.name = "Analog Sampling Phase",
3326 	.type = V4L2_CTRL_TYPE_INTEGER,
3327 	.min = 0,
3328 	.max = 0x1f,
3329 	.step = 1,
3330 	.def = 0,
3331 };
3332 
3333 static const struct v4l2_ctrl_config adv7842_ctrl_free_run_color_manual = {
3334 	.ops = &adv7842_ctrl_ops,
3335 	.id = V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL,
3336 	.name = "Free Running Color, Manual",
3337 	.type = V4L2_CTRL_TYPE_BOOLEAN,
3338 	.max = 1,
3339 	.step = 1,
3340 	.def = 1,
3341 };
3342 
3343 static const struct v4l2_ctrl_config adv7842_ctrl_free_run_color = {
3344 	.ops = &adv7842_ctrl_ops,
3345 	.id = V4L2_CID_ADV_RX_FREE_RUN_COLOR,
3346 	.name = "Free Running Color",
3347 	.type = V4L2_CTRL_TYPE_INTEGER,
3348 	.max = 0xffffff,
3349 	.step = 0x1,
3350 };
3351 
3352 
3353 static void adv7842_unregister_clients(struct v4l2_subdev *sd)
3354 {
3355 	struct adv7842_state *state = to_state(sd);
3356 	i2c_unregister_device(state->i2c_avlink);
3357 	i2c_unregister_device(state->i2c_cec);
3358 	i2c_unregister_device(state->i2c_infoframe);
3359 	i2c_unregister_device(state->i2c_sdp_io);
3360 	i2c_unregister_device(state->i2c_sdp);
3361 	i2c_unregister_device(state->i2c_afe);
3362 	i2c_unregister_device(state->i2c_repeater);
3363 	i2c_unregister_device(state->i2c_edid);
3364 	i2c_unregister_device(state->i2c_hdmi);
3365 	i2c_unregister_device(state->i2c_cp);
3366 	i2c_unregister_device(state->i2c_vdp);
3367 
3368 	state->i2c_avlink = NULL;
3369 	state->i2c_cec = NULL;
3370 	state->i2c_infoframe = NULL;
3371 	state->i2c_sdp_io = NULL;
3372 	state->i2c_sdp = NULL;
3373 	state->i2c_afe = NULL;
3374 	state->i2c_repeater = NULL;
3375 	state->i2c_edid = NULL;
3376 	state->i2c_hdmi = NULL;
3377 	state->i2c_cp = NULL;
3378 	state->i2c_vdp = NULL;
3379 }
3380 
3381 static struct i2c_client *adv7842_dummy_client(struct v4l2_subdev *sd, const char *desc,
3382 					       u8 addr, u8 io_reg)
3383 {
3384 	struct i2c_client *client = v4l2_get_subdevdata(sd);
3385 	struct i2c_client *cp;
3386 
3387 	io_write(sd, io_reg, addr << 1);
3388 
3389 	if (addr == 0) {
3390 		v4l2_err(sd, "no %s i2c addr configured\n", desc);
3391 		return NULL;
3392 	}
3393 
3394 	cp = i2c_new_dummy_device(client->adapter, io_read(sd, io_reg) >> 1);
3395 	if (IS_ERR(cp)) {
3396 		v4l2_err(sd, "register %s on i2c addr 0x%x failed with %ld\n",
3397 			 desc, addr, PTR_ERR(cp));
3398 		cp = NULL;
3399 	}
3400 
3401 	return cp;
3402 }
3403 
3404 static int adv7842_register_clients(struct v4l2_subdev *sd)
3405 {
3406 	struct adv7842_state *state = to_state(sd);
3407 	struct adv7842_platform_data *pdata = &state->pdata;
3408 
3409 	state->i2c_avlink = adv7842_dummy_client(sd, "avlink", pdata->i2c_avlink, 0xf3);
3410 	state->i2c_cec = adv7842_dummy_client(sd, "cec", pdata->i2c_cec, 0xf4);
3411 	state->i2c_infoframe = adv7842_dummy_client(sd, "infoframe", pdata->i2c_infoframe, 0xf5);
3412 	state->i2c_sdp_io = adv7842_dummy_client(sd, "sdp_io", pdata->i2c_sdp_io, 0xf2);
3413 	state->i2c_sdp = adv7842_dummy_client(sd, "sdp", pdata->i2c_sdp, 0xf1);
3414 	state->i2c_afe = adv7842_dummy_client(sd, "afe", pdata->i2c_afe, 0xf8);
3415 	state->i2c_repeater = adv7842_dummy_client(sd, "repeater", pdata->i2c_repeater, 0xf9);
3416 	state->i2c_edid = adv7842_dummy_client(sd, "edid", pdata->i2c_edid, 0xfa);
3417 	state->i2c_hdmi = adv7842_dummy_client(sd, "hdmi", pdata->i2c_hdmi, 0xfb);
3418 	state->i2c_cp = adv7842_dummy_client(sd, "cp", pdata->i2c_cp, 0xfd);
3419 	state->i2c_vdp = adv7842_dummy_client(sd, "vdp", pdata->i2c_vdp, 0xfe);
3420 
3421 	if (!state->i2c_avlink ||
3422 	    !state->i2c_cec ||
3423 	    !state->i2c_infoframe ||
3424 	    !state->i2c_sdp_io ||
3425 	    !state->i2c_sdp ||
3426 	    !state->i2c_afe ||
3427 	    !state->i2c_repeater ||
3428 	    !state->i2c_edid ||
3429 	    !state->i2c_hdmi ||
3430 	    !state->i2c_cp ||
3431 	    !state->i2c_vdp)
3432 		return -1;
3433 
3434 	return 0;
3435 }
3436 
3437 static int adv7842_probe(struct i2c_client *client,
3438 			 const struct i2c_device_id *id)
3439 {
3440 	struct adv7842_state *state;
3441 	static const struct v4l2_dv_timings cea640x480 =
3442 		V4L2_DV_BT_CEA_640X480P59_94;
3443 	struct adv7842_platform_data *pdata = client->dev.platform_data;
3444 	struct v4l2_ctrl_handler *hdl;
3445 	struct v4l2_ctrl *ctrl;
3446 	struct v4l2_subdev *sd;
3447 	unsigned int i;
3448 	u16 rev;
3449 	int err;
3450 
3451 	/* Check if the adapter supports the needed features */
3452 	if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
3453 		return -EIO;
3454 
3455 	v4l_dbg(1, debug, client, "detecting adv7842 client on address 0x%x\n",
3456 		client->addr << 1);
3457 
3458 	if (!pdata) {
3459 		v4l_err(client, "No platform data!\n");
3460 		return -ENODEV;
3461 	}
3462 
3463 	state = devm_kzalloc(&client->dev, sizeof(*state), GFP_KERNEL);
3464 	if (!state)
3465 		return -ENOMEM;
3466 
3467 	/* platform data */
3468 	state->pdata = *pdata;
3469 	state->timings = cea640x480;
3470 	state->format = adv7842_format_info(state, MEDIA_BUS_FMT_YUYV8_2X8);
3471 
3472 	sd = &state->sd;
3473 	v4l2_i2c_subdev_init(sd, client, &adv7842_ops);
3474 	sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS;
3475 	sd->internal_ops = &adv7842_int_ops;
3476 	state->mode = pdata->mode;
3477 
3478 	state->hdmi_port_a = pdata->input == ADV7842_SELECT_HDMI_PORT_A;
3479 	state->restart_stdi_once = true;
3480 
3481 	/* i2c access to adv7842? */
3482 	rev = adv_smbus_read_byte_data_check(client, 0xea, false) << 8 |
3483 		adv_smbus_read_byte_data_check(client, 0xeb, false);
3484 	if (rev != 0x2012) {
3485 		v4l2_info(sd, "got rev=0x%04x on first read attempt\n", rev);
3486 		rev = adv_smbus_read_byte_data_check(client, 0xea, false) << 8 |
3487 			adv_smbus_read_byte_data_check(client, 0xeb, false);
3488 	}
3489 	if (rev != 0x2012) {
3490 		v4l2_info(sd, "not an adv7842 on address 0x%x (rev=0x%04x)\n",
3491 			  client->addr << 1, rev);
3492 		return -ENODEV;
3493 	}
3494 
3495 	if (pdata->chip_reset)
3496 		main_reset(sd);
3497 
3498 	/* control handlers */
3499 	hdl = &state->hdl;
3500 	v4l2_ctrl_handler_init(hdl, 6);
3501 
3502 	/* add in ascending ID order */
3503 	v4l2_ctrl_new_std(hdl, &adv7842_ctrl_ops,
3504 			  V4L2_CID_BRIGHTNESS, -128, 127, 1, 0);
3505 	v4l2_ctrl_new_std(hdl, &adv7842_ctrl_ops,
3506 			  V4L2_CID_CONTRAST, 0, 255, 1, 128);
3507 	v4l2_ctrl_new_std(hdl, &adv7842_ctrl_ops,
3508 			  V4L2_CID_SATURATION, 0, 255, 1, 128);
3509 	v4l2_ctrl_new_std(hdl, &adv7842_ctrl_ops,
3510 			  V4L2_CID_HUE, 0, 128, 1, 0);
3511 	ctrl = v4l2_ctrl_new_std_menu(hdl, &adv7842_ctrl_ops,
3512 			V4L2_CID_DV_RX_IT_CONTENT_TYPE, V4L2_DV_IT_CONTENT_TYPE_NO_ITC,
3513 			0, V4L2_DV_IT_CONTENT_TYPE_NO_ITC);
3514 	if (ctrl)
3515 		ctrl->flags |= V4L2_CTRL_FLAG_VOLATILE;
3516 
3517 	/* custom controls */
3518 	state->detect_tx_5v_ctrl = v4l2_ctrl_new_std(hdl, NULL,
3519 			V4L2_CID_DV_RX_POWER_PRESENT, 0, 3, 0, 0);
3520 	state->analog_sampling_phase_ctrl = v4l2_ctrl_new_custom(hdl,
3521 			&adv7842_ctrl_analog_sampling_phase, NULL);
3522 	state->free_run_color_ctrl_manual = v4l2_ctrl_new_custom(hdl,
3523 			&adv7842_ctrl_free_run_color_manual, NULL);
3524 	state->free_run_color_ctrl = v4l2_ctrl_new_custom(hdl,
3525 			&adv7842_ctrl_free_run_color, NULL);
3526 	state->rgb_quantization_range_ctrl =
3527 		v4l2_ctrl_new_std_menu(hdl, &adv7842_ctrl_ops,
3528 			V4L2_CID_DV_RX_RGB_RANGE, V4L2_DV_RGB_RANGE_FULL,
3529 			0, V4L2_DV_RGB_RANGE_AUTO);
3530 	sd->ctrl_handler = hdl;
3531 	if (hdl->error) {
3532 		err = hdl->error;
3533 		goto err_hdl;
3534 	}
3535 	if (adv7842_s_detect_tx_5v_ctrl(sd)) {
3536 		err = -ENODEV;
3537 		goto err_hdl;
3538 	}
3539 
3540 	if (adv7842_register_clients(sd) < 0) {
3541 		err = -ENOMEM;
3542 		v4l2_err(sd, "failed to create all i2c clients\n");
3543 		goto err_i2c;
3544 	}
3545 
3546 
3547 	INIT_DELAYED_WORK(&state->delayed_work_enable_hotplug,
3548 			adv7842_delayed_work_enable_hotplug);
3549 
3550 	sd->entity.function = MEDIA_ENT_F_DV_DECODER;
3551 	for (i = 0; i < ADV7842_PAD_SOURCE; ++i)
3552 		state->pads[i].flags = MEDIA_PAD_FL_SINK;
3553 	state->pads[ADV7842_PAD_SOURCE].flags = MEDIA_PAD_FL_SOURCE;
3554 	err = media_entity_pads_init(&sd->entity, ADV7842_PAD_SOURCE + 1,
3555 				     state->pads);
3556 	if (err)
3557 		goto err_work_queues;
3558 
3559 	err = adv7842_core_init(sd);
3560 	if (err)
3561 		goto err_entity;
3562 
3563 #if IS_ENABLED(CONFIG_VIDEO_ADV7842_CEC)
3564 	state->cec_adap = cec_allocate_adapter(&adv7842_cec_adap_ops,
3565 		state, dev_name(&client->dev),
3566 		CEC_CAP_DEFAULTS, ADV7842_MAX_ADDRS);
3567 	err = PTR_ERR_OR_ZERO(state->cec_adap);
3568 	if (err)
3569 		goto err_entity;
3570 #endif
3571 
3572 	v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name,
3573 		  client->addr << 1, client->adapter->name);
3574 	return 0;
3575 
3576 err_entity:
3577 	media_entity_cleanup(&sd->entity);
3578 err_work_queues:
3579 	cancel_delayed_work(&state->delayed_work_enable_hotplug);
3580 err_i2c:
3581 	adv7842_unregister_clients(sd);
3582 err_hdl:
3583 	v4l2_ctrl_handler_free(hdl);
3584 	return err;
3585 }
3586 
3587 /* ----------------------------------------------------------------------- */
3588 
3589 static int adv7842_remove(struct i2c_client *client)
3590 {
3591 	struct v4l2_subdev *sd = i2c_get_clientdata(client);
3592 	struct adv7842_state *state = to_state(sd);
3593 
3594 	adv7842_irq_enable(sd, false);
3595 	cancel_delayed_work_sync(&state->delayed_work_enable_hotplug);
3596 	v4l2_device_unregister_subdev(sd);
3597 	media_entity_cleanup(&sd->entity);
3598 	adv7842_unregister_clients(sd);
3599 	v4l2_ctrl_handler_free(sd->ctrl_handler);
3600 	return 0;
3601 }
3602 
3603 /* ----------------------------------------------------------------------- */
3604 
3605 static const struct i2c_device_id adv7842_id[] = {
3606 	{ "adv7842", 0 },
3607 	{ }
3608 };
3609 MODULE_DEVICE_TABLE(i2c, adv7842_id);
3610 
3611 /* ----------------------------------------------------------------------- */
3612 
3613 static struct i2c_driver adv7842_driver = {
3614 	.driver = {
3615 		.name = "adv7842",
3616 	},
3617 	.probe = adv7842_probe,
3618 	.remove = adv7842_remove,
3619 	.id_table = adv7842_id,
3620 };
3621 
3622 module_i2c_driver(adv7842_driver);
3623