1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * adv7842 - Analog Devices ADV7842 video decoder driver 4 * 5 * Copyright 2013 Cisco Systems, Inc. and/or its affiliates. All rights reserved. 6 */ 7 8 /* 9 * References (c = chapter, p = page): 10 * REF_01 - Analog devices, ADV7842, 11 * Register Settings Recommendations, Rev. 1.9, April 2011 12 * REF_02 - Analog devices, Software User Guide, UG-206, 13 * ADV7842 I2C Register Maps, Rev. 0, November 2010 14 * REF_03 - Analog devices, Hardware User Guide, UG-214, 15 * ADV7842 Fast Switching 2:1 HDMI 1.4 Receiver with 3D-Comb 16 * Decoder and Digitizer , Rev. 0, January 2011 17 */ 18 19 20 #include <linux/kernel.h> 21 #include <linux/module.h> 22 #include <linux/slab.h> 23 #include <linux/i2c.h> 24 #include <linux/delay.h> 25 #include <linux/videodev2.h> 26 #include <linux/workqueue.h> 27 #include <linux/v4l2-dv-timings.h> 28 #include <linux/hdmi.h> 29 #include <media/cec.h> 30 #include <media/v4l2-device.h> 31 #include <media/v4l2-event.h> 32 #include <media/v4l2-ctrls.h> 33 #include <media/v4l2-dv-timings.h> 34 #include <media/i2c/adv7842.h> 35 36 static int debug; 37 module_param(debug, int, 0644); 38 MODULE_PARM_DESC(debug, "debug level (0-2)"); 39 40 MODULE_DESCRIPTION("Analog Devices ADV7842 video decoder driver"); 41 MODULE_AUTHOR("Hans Verkuil <hans.verkuil@cisco.com>"); 42 MODULE_AUTHOR("Martin Bugge <marbugge@cisco.com>"); 43 MODULE_LICENSE("GPL"); 44 45 /* ADV7842 system clock frequency */ 46 #define ADV7842_fsc (28636360) 47 48 #define ADV7842_RGB_OUT (1 << 1) 49 50 #define ADV7842_OP_FORMAT_SEL_8BIT (0 << 0) 51 #define ADV7842_OP_FORMAT_SEL_10BIT (1 << 0) 52 #define ADV7842_OP_FORMAT_SEL_12BIT (2 << 0) 53 54 #define ADV7842_OP_MODE_SEL_SDR_422 (0 << 5) 55 #define ADV7842_OP_MODE_SEL_DDR_422 (1 << 5) 56 #define ADV7842_OP_MODE_SEL_SDR_444 (2 << 5) 57 #define ADV7842_OP_MODE_SEL_DDR_444 (3 << 5) 58 #define ADV7842_OP_MODE_SEL_SDR_422_2X (4 << 5) 59 #define ADV7842_OP_MODE_SEL_ADI_CM (5 << 5) 60 61 #define ADV7842_OP_CH_SEL_GBR (0 << 5) 62 #define ADV7842_OP_CH_SEL_GRB (1 << 5) 63 #define ADV7842_OP_CH_SEL_BGR (2 << 5) 64 #define ADV7842_OP_CH_SEL_RGB (3 << 5) 65 #define ADV7842_OP_CH_SEL_BRG (4 << 5) 66 #define ADV7842_OP_CH_SEL_RBG (5 << 5) 67 68 #define ADV7842_OP_SWAP_CB_CR (1 << 0) 69 70 #define ADV7842_MAX_ADDRS (3) 71 72 /* 73 ********************************************************************** 74 * 75 * Arrays with configuration parameters for the ADV7842 76 * 77 ********************************************************************** 78 */ 79 80 struct adv7842_format_info { 81 u32 code; 82 u8 op_ch_sel; 83 bool rgb_out; 84 bool swap_cb_cr; 85 u8 op_format_sel; 86 }; 87 88 struct adv7842_state { 89 struct adv7842_platform_data pdata; 90 struct v4l2_subdev sd; 91 struct media_pad pads[ADV7842_PAD_SOURCE + 1]; 92 struct v4l2_ctrl_handler hdl; 93 enum adv7842_mode mode; 94 struct v4l2_dv_timings timings; 95 enum adv7842_vid_std_select vid_std_select; 96 97 const struct adv7842_format_info *format; 98 99 v4l2_std_id norm; 100 struct { 101 u8 edid[512]; 102 u32 blocks; 103 u32 present; 104 } hdmi_edid; 105 struct { 106 u8 edid[128]; 107 u32 blocks; 108 u32 present; 109 } vga_edid; 110 struct v4l2_fract aspect_ratio; 111 u32 rgb_quantization_range; 112 bool is_cea_format; 113 struct delayed_work delayed_work_enable_hotplug; 114 bool restart_stdi_once; 115 bool hdmi_port_a; 116 117 /* i2c clients */ 118 struct i2c_client *i2c_sdp_io; 119 struct i2c_client *i2c_sdp; 120 struct i2c_client *i2c_cp; 121 struct i2c_client *i2c_vdp; 122 struct i2c_client *i2c_afe; 123 struct i2c_client *i2c_hdmi; 124 struct i2c_client *i2c_repeater; 125 struct i2c_client *i2c_edid; 126 struct i2c_client *i2c_infoframe; 127 struct i2c_client *i2c_cec; 128 struct i2c_client *i2c_avlink; 129 130 /* controls */ 131 struct v4l2_ctrl *detect_tx_5v_ctrl; 132 struct v4l2_ctrl *analog_sampling_phase_ctrl; 133 struct v4l2_ctrl *free_run_color_ctrl_manual; 134 struct v4l2_ctrl *free_run_color_ctrl; 135 struct v4l2_ctrl *rgb_quantization_range_ctrl; 136 137 struct cec_adapter *cec_adap; 138 u8 cec_addr[ADV7842_MAX_ADDRS]; 139 u8 cec_valid_addrs; 140 bool cec_enabled_adap; 141 }; 142 143 /* Unsupported timings. This device cannot support 720p30. */ 144 static const struct v4l2_dv_timings adv7842_timings_exceptions[] = { 145 V4L2_DV_BT_CEA_1280X720P30, 146 { } 147 }; 148 149 static bool adv7842_check_dv_timings(const struct v4l2_dv_timings *t, void *hdl) 150 { 151 int i; 152 153 for (i = 0; adv7842_timings_exceptions[i].bt.width; i++) 154 if (v4l2_match_dv_timings(t, adv7842_timings_exceptions + i, 0, false)) 155 return false; 156 return true; 157 } 158 159 struct adv7842_video_standards { 160 struct v4l2_dv_timings timings; 161 u8 vid_std; 162 u8 v_freq; 163 }; 164 165 /* sorted by number of lines */ 166 static const struct adv7842_video_standards adv7842_prim_mode_comp[] = { 167 /* { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 }, TODO flickering */ 168 { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 }, 169 { V4L2_DV_BT_CEA_1280X720P50, 0x19, 0x01 }, 170 { V4L2_DV_BT_CEA_1280X720P60, 0x19, 0x00 }, 171 { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 }, 172 { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 }, 173 { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 }, 174 { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 }, 175 { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 }, 176 /* TODO add 1920x1080P60_RB (CVT timing) */ 177 { }, 178 }; 179 180 /* sorted by number of lines */ 181 static const struct adv7842_video_standards adv7842_prim_mode_gr[] = { 182 { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 }, 183 { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 }, 184 { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 }, 185 { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 }, 186 { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 }, 187 { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 }, 188 { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 }, 189 { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 }, 190 { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 }, 191 { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 }, 192 { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 }, 193 { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 }, 194 { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 }, 195 { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 }, 196 { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 }, 197 { V4L2_DV_BT_DMT_1360X768P60, 0x12, 0x00 }, 198 { V4L2_DV_BT_DMT_1366X768P60, 0x13, 0x00 }, 199 { V4L2_DV_BT_DMT_1400X1050P60, 0x14, 0x00 }, 200 { V4L2_DV_BT_DMT_1400X1050P75, 0x15, 0x00 }, 201 { V4L2_DV_BT_DMT_1600X1200P60, 0x16, 0x00 }, /* TODO not tested */ 202 /* TODO add 1600X1200P60_RB (not a DMT timing) */ 203 { V4L2_DV_BT_DMT_1680X1050P60, 0x18, 0x00 }, 204 { V4L2_DV_BT_DMT_1920X1200P60_RB, 0x19, 0x00 }, /* TODO not tested */ 205 { }, 206 }; 207 208 /* sorted by number of lines */ 209 static const struct adv7842_video_standards adv7842_prim_mode_hdmi_comp[] = { 210 { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 }, 211 { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 }, 212 { V4L2_DV_BT_CEA_1280X720P50, 0x13, 0x01 }, 213 { V4L2_DV_BT_CEA_1280X720P60, 0x13, 0x00 }, 214 { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 }, 215 { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 }, 216 { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 }, 217 { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 }, 218 { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 }, 219 { }, 220 }; 221 222 /* sorted by number of lines */ 223 static const struct adv7842_video_standards adv7842_prim_mode_hdmi_gr[] = { 224 { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 }, 225 { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 }, 226 { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 }, 227 { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 }, 228 { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 }, 229 { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 }, 230 { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 }, 231 { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 }, 232 { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 }, 233 { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 }, 234 { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 }, 235 { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 }, 236 { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 }, 237 { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 }, 238 { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 }, 239 { }, 240 }; 241 242 static const struct v4l2_event adv7842_ev_fmt = { 243 .type = V4L2_EVENT_SOURCE_CHANGE, 244 .u.src_change.changes = V4L2_EVENT_SRC_CH_RESOLUTION, 245 }; 246 247 /* ----------------------------------------------------------------------- */ 248 249 static inline struct adv7842_state *to_state(struct v4l2_subdev *sd) 250 { 251 return container_of(sd, struct adv7842_state, sd); 252 } 253 254 static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl) 255 { 256 return &container_of(ctrl->handler, struct adv7842_state, hdl)->sd; 257 } 258 259 static inline unsigned hblanking(const struct v4l2_bt_timings *t) 260 { 261 return V4L2_DV_BT_BLANKING_WIDTH(t); 262 } 263 264 static inline unsigned htotal(const struct v4l2_bt_timings *t) 265 { 266 return V4L2_DV_BT_FRAME_WIDTH(t); 267 } 268 269 static inline unsigned vblanking(const struct v4l2_bt_timings *t) 270 { 271 return V4L2_DV_BT_BLANKING_HEIGHT(t); 272 } 273 274 static inline unsigned vtotal(const struct v4l2_bt_timings *t) 275 { 276 return V4L2_DV_BT_FRAME_HEIGHT(t); 277 } 278 279 280 /* ----------------------------------------------------------------------- */ 281 282 static s32 adv_smbus_read_byte_data_check(struct i2c_client *client, 283 u8 command, bool check) 284 { 285 union i2c_smbus_data data; 286 287 if (!i2c_smbus_xfer(client->adapter, client->addr, client->flags, 288 I2C_SMBUS_READ, command, 289 I2C_SMBUS_BYTE_DATA, &data)) 290 return data.byte; 291 if (check) 292 v4l_err(client, "error reading %02x, %02x\n", 293 client->addr, command); 294 return -EIO; 295 } 296 297 static s32 adv_smbus_read_byte_data(struct i2c_client *client, u8 command) 298 { 299 int i; 300 301 for (i = 0; i < 3; i++) { 302 int ret = adv_smbus_read_byte_data_check(client, command, true); 303 304 if (ret >= 0) { 305 if (i) 306 v4l_err(client, "read ok after %d retries\n", i); 307 return ret; 308 } 309 } 310 v4l_err(client, "read failed\n"); 311 return -EIO; 312 } 313 314 static s32 adv_smbus_write_byte_data(struct i2c_client *client, 315 u8 command, u8 value) 316 { 317 union i2c_smbus_data data; 318 int err; 319 int i; 320 321 data.byte = value; 322 for (i = 0; i < 3; i++) { 323 err = i2c_smbus_xfer(client->adapter, client->addr, 324 client->flags, 325 I2C_SMBUS_WRITE, command, 326 I2C_SMBUS_BYTE_DATA, &data); 327 if (!err) 328 break; 329 } 330 if (err < 0) 331 v4l_err(client, "error writing %02x, %02x, %02x\n", 332 client->addr, command, value); 333 return err; 334 } 335 336 static void adv_smbus_write_byte_no_check(struct i2c_client *client, 337 u8 command, u8 value) 338 { 339 union i2c_smbus_data data; 340 data.byte = value; 341 342 i2c_smbus_xfer(client->adapter, client->addr, 343 client->flags, 344 I2C_SMBUS_WRITE, command, 345 I2C_SMBUS_BYTE_DATA, &data); 346 } 347 348 /* ----------------------------------------------------------------------- */ 349 350 static inline int io_read(struct v4l2_subdev *sd, u8 reg) 351 { 352 struct i2c_client *client = v4l2_get_subdevdata(sd); 353 354 return adv_smbus_read_byte_data(client, reg); 355 } 356 357 static inline int io_write(struct v4l2_subdev *sd, u8 reg, u8 val) 358 { 359 struct i2c_client *client = v4l2_get_subdevdata(sd); 360 361 return adv_smbus_write_byte_data(client, reg, val); 362 } 363 364 static inline int io_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) 365 { 366 return io_write(sd, reg, (io_read(sd, reg) & mask) | val); 367 } 368 369 static inline int io_write_clr_set(struct v4l2_subdev *sd, 370 u8 reg, u8 mask, u8 val) 371 { 372 return io_write(sd, reg, (io_read(sd, reg) & ~mask) | val); 373 } 374 375 static inline int avlink_read(struct v4l2_subdev *sd, u8 reg) 376 { 377 struct adv7842_state *state = to_state(sd); 378 379 return adv_smbus_read_byte_data(state->i2c_avlink, reg); 380 } 381 382 static inline int avlink_write(struct v4l2_subdev *sd, u8 reg, u8 val) 383 { 384 struct adv7842_state *state = to_state(sd); 385 386 return adv_smbus_write_byte_data(state->i2c_avlink, reg, val); 387 } 388 389 static inline int cec_read(struct v4l2_subdev *sd, u8 reg) 390 { 391 struct adv7842_state *state = to_state(sd); 392 393 return adv_smbus_read_byte_data(state->i2c_cec, reg); 394 } 395 396 static inline int cec_write(struct v4l2_subdev *sd, u8 reg, u8 val) 397 { 398 struct adv7842_state *state = to_state(sd); 399 400 return adv_smbus_write_byte_data(state->i2c_cec, reg, val); 401 } 402 403 static inline int cec_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) 404 { 405 return cec_write(sd, reg, (cec_read(sd, reg) & ~mask) | val); 406 } 407 408 static inline int infoframe_read(struct v4l2_subdev *sd, u8 reg) 409 { 410 struct adv7842_state *state = to_state(sd); 411 412 return adv_smbus_read_byte_data(state->i2c_infoframe, reg); 413 } 414 415 static inline int infoframe_write(struct v4l2_subdev *sd, u8 reg, u8 val) 416 { 417 struct adv7842_state *state = to_state(sd); 418 419 return adv_smbus_write_byte_data(state->i2c_infoframe, reg, val); 420 } 421 422 static inline int sdp_io_read(struct v4l2_subdev *sd, u8 reg) 423 { 424 struct adv7842_state *state = to_state(sd); 425 426 return adv_smbus_read_byte_data(state->i2c_sdp_io, reg); 427 } 428 429 static inline int sdp_io_write(struct v4l2_subdev *sd, u8 reg, u8 val) 430 { 431 struct adv7842_state *state = to_state(sd); 432 433 return adv_smbus_write_byte_data(state->i2c_sdp_io, reg, val); 434 } 435 436 static inline int sdp_io_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) 437 { 438 return sdp_io_write(sd, reg, (sdp_io_read(sd, reg) & mask) | val); 439 } 440 441 static inline int sdp_read(struct v4l2_subdev *sd, u8 reg) 442 { 443 struct adv7842_state *state = to_state(sd); 444 445 return adv_smbus_read_byte_data(state->i2c_sdp, reg); 446 } 447 448 static inline int sdp_write(struct v4l2_subdev *sd, u8 reg, u8 val) 449 { 450 struct adv7842_state *state = to_state(sd); 451 452 return adv_smbus_write_byte_data(state->i2c_sdp, reg, val); 453 } 454 455 static inline int sdp_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) 456 { 457 return sdp_write(sd, reg, (sdp_read(sd, reg) & mask) | val); 458 } 459 460 static inline int afe_read(struct v4l2_subdev *sd, u8 reg) 461 { 462 struct adv7842_state *state = to_state(sd); 463 464 return adv_smbus_read_byte_data(state->i2c_afe, reg); 465 } 466 467 static inline int afe_write(struct v4l2_subdev *sd, u8 reg, u8 val) 468 { 469 struct adv7842_state *state = to_state(sd); 470 471 return adv_smbus_write_byte_data(state->i2c_afe, reg, val); 472 } 473 474 static inline int afe_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) 475 { 476 return afe_write(sd, reg, (afe_read(sd, reg) & mask) | val); 477 } 478 479 static inline int rep_read(struct v4l2_subdev *sd, u8 reg) 480 { 481 struct adv7842_state *state = to_state(sd); 482 483 return adv_smbus_read_byte_data(state->i2c_repeater, reg); 484 } 485 486 static inline int rep_write(struct v4l2_subdev *sd, u8 reg, u8 val) 487 { 488 struct adv7842_state *state = to_state(sd); 489 490 return adv_smbus_write_byte_data(state->i2c_repeater, reg, val); 491 } 492 493 static inline int rep_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) 494 { 495 return rep_write(sd, reg, (rep_read(sd, reg) & mask) | val); 496 } 497 498 static inline int edid_read(struct v4l2_subdev *sd, u8 reg) 499 { 500 struct adv7842_state *state = to_state(sd); 501 502 return adv_smbus_read_byte_data(state->i2c_edid, reg); 503 } 504 505 static inline int edid_write(struct v4l2_subdev *sd, u8 reg, u8 val) 506 { 507 struct adv7842_state *state = to_state(sd); 508 509 return adv_smbus_write_byte_data(state->i2c_edid, reg, val); 510 } 511 512 static inline int hdmi_read(struct v4l2_subdev *sd, u8 reg) 513 { 514 struct adv7842_state *state = to_state(sd); 515 516 return adv_smbus_read_byte_data(state->i2c_hdmi, reg); 517 } 518 519 static inline int hdmi_write(struct v4l2_subdev *sd, u8 reg, u8 val) 520 { 521 struct adv7842_state *state = to_state(sd); 522 523 return adv_smbus_write_byte_data(state->i2c_hdmi, reg, val); 524 } 525 526 static inline int hdmi_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) 527 { 528 return hdmi_write(sd, reg, (hdmi_read(sd, reg) & mask) | val); 529 } 530 531 static inline int cp_read(struct v4l2_subdev *sd, u8 reg) 532 { 533 struct adv7842_state *state = to_state(sd); 534 535 return adv_smbus_read_byte_data(state->i2c_cp, reg); 536 } 537 538 static inline int cp_write(struct v4l2_subdev *sd, u8 reg, u8 val) 539 { 540 struct adv7842_state *state = to_state(sd); 541 542 return adv_smbus_write_byte_data(state->i2c_cp, reg, val); 543 } 544 545 static inline int cp_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) 546 { 547 return cp_write(sd, reg, (cp_read(sd, reg) & mask) | val); 548 } 549 550 static inline int vdp_read(struct v4l2_subdev *sd, u8 reg) 551 { 552 struct adv7842_state *state = to_state(sd); 553 554 return adv_smbus_read_byte_data(state->i2c_vdp, reg); 555 } 556 557 static inline int vdp_write(struct v4l2_subdev *sd, u8 reg, u8 val) 558 { 559 struct adv7842_state *state = to_state(sd); 560 561 return adv_smbus_write_byte_data(state->i2c_vdp, reg, val); 562 } 563 564 static void main_reset(struct v4l2_subdev *sd) 565 { 566 struct i2c_client *client = v4l2_get_subdevdata(sd); 567 568 v4l2_dbg(1, debug, sd, "%s:\n", __func__); 569 570 adv_smbus_write_byte_no_check(client, 0xff, 0x80); 571 572 mdelay(5); 573 } 574 575 /* ----------------------------------------------------------------------------- 576 * Format helpers 577 */ 578 579 static const struct adv7842_format_info adv7842_formats[] = { 580 { MEDIA_BUS_FMT_RGB888_1X24, ADV7842_OP_CH_SEL_RGB, true, false, 581 ADV7842_OP_MODE_SEL_SDR_444 | ADV7842_OP_FORMAT_SEL_8BIT }, 582 { MEDIA_BUS_FMT_YUYV8_2X8, ADV7842_OP_CH_SEL_RGB, false, false, 583 ADV7842_OP_MODE_SEL_SDR_422 | ADV7842_OP_FORMAT_SEL_8BIT }, 584 { MEDIA_BUS_FMT_YVYU8_2X8, ADV7842_OP_CH_SEL_RGB, false, true, 585 ADV7842_OP_MODE_SEL_SDR_422 | ADV7842_OP_FORMAT_SEL_8BIT }, 586 { MEDIA_BUS_FMT_YUYV10_2X10, ADV7842_OP_CH_SEL_RGB, false, false, 587 ADV7842_OP_MODE_SEL_SDR_422 | ADV7842_OP_FORMAT_SEL_10BIT }, 588 { MEDIA_BUS_FMT_YVYU10_2X10, ADV7842_OP_CH_SEL_RGB, false, true, 589 ADV7842_OP_MODE_SEL_SDR_422 | ADV7842_OP_FORMAT_SEL_10BIT }, 590 { MEDIA_BUS_FMT_YUYV12_2X12, ADV7842_OP_CH_SEL_RGB, false, false, 591 ADV7842_OP_MODE_SEL_SDR_422 | ADV7842_OP_FORMAT_SEL_12BIT }, 592 { MEDIA_BUS_FMT_YVYU12_2X12, ADV7842_OP_CH_SEL_RGB, false, true, 593 ADV7842_OP_MODE_SEL_SDR_422 | ADV7842_OP_FORMAT_SEL_12BIT }, 594 { MEDIA_BUS_FMT_UYVY8_1X16, ADV7842_OP_CH_SEL_RBG, false, false, 595 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_8BIT }, 596 { MEDIA_BUS_FMT_VYUY8_1X16, ADV7842_OP_CH_SEL_RBG, false, true, 597 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_8BIT }, 598 { MEDIA_BUS_FMT_YUYV8_1X16, ADV7842_OP_CH_SEL_RGB, false, false, 599 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_8BIT }, 600 { MEDIA_BUS_FMT_YVYU8_1X16, ADV7842_OP_CH_SEL_RGB, false, true, 601 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_8BIT }, 602 { MEDIA_BUS_FMT_UYVY10_1X20, ADV7842_OP_CH_SEL_RBG, false, false, 603 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_10BIT }, 604 { MEDIA_BUS_FMT_VYUY10_1X20, ADV7842_OP_CH_SEL_RBG, false, true, 605 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_10BIT }, 606 { MEDIA_BUS_FMT_YUYV10_1X20, ADV7842_OP_CH_SEL_RGB, false, false, 607 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_10BIT }, 608 { MEDIA_BUS_FMT_YVYU10_1X20, ADV7842_OP_CH_SEL_RGB, false, true, 609 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_10BIT }, 610 { MEDIA_BUS_FMT_UYVY12_1X24, ADV7842_OP_CH_SEL_RBG, false, false, 611 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_12BIT }, 612 { MEDIA_BUS_FMT_VYUY12_1X24, ADV7842_OP_CH_SEL_RBG, false, true, 613 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_12BIT }, 614 { MEDIA_BUS_FMT_YUYV12_1X24, ADV7842_OP_CH_SEL_RGB, false, false, 615 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_12BIT }, 616 { MEDIA_BUS_FMT_YVYU12_1X24, ADV7842_OP_CH_SEL_RGB, false, true, 617 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_12BIT }, 618 }; 619 620 static const struct adv7842_format_info * 621 adv7842_format_info(struct adv7842_state *state, u32 code) 622 { 623 unsigned int i; 624 625 for (i = 0; i < ARRAY_SIZE(adv7842_formats); ++i) { 626 if (adv7842_formats[i].code == code) 627 return &adv7842_formats[i]; 628 } 629 630 return NULL; 631 } 632 633 /* ----------------------------------------------------------------------- */ 634 635 static inline bool is_analog_input(struct v4l2_subdev *sd) 636 { 637 struct adv7842_state *state = to_state(sd); 638 639 return ((state->mode == ADV7842_MODE_RGB) || 640 (state->mode == ADV7842_MODE_COMP)); 641 } 642 643 static inline bool is_digital_input(struct v4l2_subdev *sd) 644 { 645 struct adv7842_state *state = to_state(sd); 646 647 return state->mode == ADV7842_MODE_HDMI; 648 } 649 650 static const struct v4l2_dv_timings_cap adv7842_timings_cap_analog = { 651 .type = V4L2_DV_BT_656_1120, 652 /* keep this initialization for compatibility with GCC < 4.4.6 */ 653 .reserved = { 0 }, 654 V4L2_INIT_BT_TIMINGS(640, 1920, 350, 1200, 25000000, 170000000, 655 V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT | 656 V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT, 657 V4L2_DV_BT_CAP_PROGRESSIVE | V4L2_DV_BT_CAP_REDUCED_BLANKING | 658 V4L2_DV_BT_CAP_CUSTOM) 659 }; 660 661 static const struct v4l2_dv_timings_cap adv7842_timings_cap_digital = { 662 .type = V4L2_DV_BT_656_1120, 663 /* keep this initialization for compatibility with GCC < 4.4.6 */ 664 .reserved = { 0 }, 665 V4L2_INIT_BT_TIMINGS(640, 1920, 350, 1200, 25000000, 225000000, 666 V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT | 667 V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT, 668 V4L2_DV_BT_CAP_PROGRESSIVE | V4L2_DV_BT_CAP_REDUCED_BLANKING | 669 V4L2_DV_BT_CAP_CUSTOM) 670 }; 671 672 static inline const struct v4l2_dv_timings_cap * 673 adv7842_get_dv_timings_cap(struct v4l2_subdev *sd) 674 { 675 return is_digital_input(sd) ? &adv7842_timings_cap_digital : 676 &adv7842_timings_cap_analog; 677 } 678 679 /* ----------------------------------------------------------------------- */ 680 681 static u16 adv7842_read_cable_det(struct v4l2_subdev *sd) 682 { 683 u8 reg = io_read(sd, 0x6f); 684 u16 val = 0; 685 686 if (reg & 0x02) 687 val |= 1; /* port A */ 688 if (reg & 0x01) 689 val |= 2; /* port B */ 690 return val; 691 } 692 693 static void adv7842_delayed_work_enable_hotplug(struct work_struct *work) 694 { 695 struct delayed_work *dwork = to_delayed_work(work); 696 struct adv7842_state *state = container_of(dwork, 697 struct adv7842_state, delayed_work_enable_hotplug); 698 struct v4l2_subdev *sd = &state->sd; 699 int present = state->hdmi_edid.present; 700 u8 mask = 0; 701 702 v4l2_dbg(2, debug, sd, "%s: enable hotplug on ports: 0x%x\n", 703 __func__, present); 704 705 if (present & (0x04 << ADV7842_EDID_PORT_A)) 706 mask |= 0x20; 707 if (present & (0x04 << ADV7842_EDID_PORT_B)) 708 mask |= 0x10; 709 io_write_and_or(sd, 0x20, 0xcf, mask); 710 } 711 712 static int edid_write_vga_segment(struct v4l2_subdev *sd) 713 { 714 struct i2c_client *client = v4l2_get_subdevdata(sd); 715 struct adv7842_state *state = to_state(sd); 716 const u8 *edid = state->vga_edid.edid; 717 u32 blocks = state->vga_edid.blocks; 718 int err = 0; 719 int i; 720 721 v4l2_dbg(2, debug, sd, "%s: write EDID on VGA port\n", __func__); 722 723 if (!state->vga_edid.present) 724 return 0; 725 726 /* HPA disable on port A and B */ 727 io_write_and_or(sd, 0x20, 0xcf, 0x00); 728 729 /* Disable I2C access to internal EDID ram from VGA DDC port */ 730 rep_write_and_or(sd, 0x7f, 0x7f, 0x00); 731 732 /* edid segment pointer '1' for VGA port */ 733 rep_write_and_or(sd, 0x77, 0xef, 0x10); 734 735 for (i = 0; !err && i < blocks * 128; i += I2C_SMBUS_BLOCK_MAX) 736 err = i2c_smbus_write_i2c_block_data(state->i2c_edid, i, 737 I2C_SMBUS_BLOCK_MAX, 738 edid + i); 739 if (err) 740 return err; 741 742 /* Calculates the checksums and enables I2C access 743 * to internal EDID ram from VGA DDC port. 744 */ 745 rep_write_and_or(sd, 0x7f, 0x7f, 0x80); 746 747 for (i = 0; i < 1000; i++) { 748 if (rep_read(sd, 0x79) & 0x20) 749 break; 750 mdelay(1); 751 } 752 if (i == 1000) { 753 v4l_err(client, "error enabling edid on VGA port\n"); 754 return -EIO; 755 } 756 757 /* enable hotplug after 200 ms */ 758 schedule_delayed_work(&state->delayed_work_enable_hotplug, HZ / 5); 759 760 return 0; 761 } 762 763 static int edid_write_hdmi_segment(struct v4l2_subdev *sd, u8 port) 764 { 765 struct i2c_client *client = v4l2_get_subdevdata(sd); 766 struct adv7842_state *state = to_state(sd); 767 const u8 *edid = state->hdmi_edid.edid; 768 u32 blocks = state->hdmi_edid.blocks; 769 unsigned int spa_loc; 770 u16 pa, parent_pa; 771 int err = 0; 772 int i; 773 774 v4l2_dbg(2, debug, sd, "%s: write EDID on port %c\n", 775 __func__, (port == ADV7842_EDID_PORT_A) ? 'A' : 'B'); 776 777 /* HPA disable on port A and B */ 778 io_write_and_or(sd, 0x20, 0xcf, 0x00); 779 780 /* Disable I2C access to internal EDID ram from HDMI DDC ports */ 781 rep_write_and_or(sd, 0x77, 0xf3, 0x00); 782 783 if (!state->hdmi_edid.present) { 784 cec_phys_addr_invalidate(state->cec_adap); 785 return 0; 786 } 787 788 pa = v4l2_get_edid_phys_addr(edid, blocks * 128, &spa_loc); 789 err = v4l2_phys_addr_validate(pa, &parent_pa, NULL); 790 if (err) 791 return err; 792 793 if (!spa_loc) { 794 /* 795 * There is no SPA, so just set spa_loc to 128 and pa to whatever 796 * data is there. 797 */ 798 spa_loc = 128; 799 pa = (edid[spa_loc] << 8) | edid[spa_loc + 1]; 800 } 801 802 803 for (i = 0; !err && i < blocks * 128; i += I2C_SMBUS_BLOCK_MAX) { 804 /* set edid segment pointer for HDMI ports */ 805 if (i % 256 == 0) 806 rep_write_and_or(sd, 0x77, 0xef, i >= 256 ? 0x10 : 0x00); 807 err = i2c_smbus_write_i2c_block_data(state->i2c_edid, i, 808 I2C_SMBUS_BLOCK_MAX, edid + i); 809 } 810 if (err) 811 return err; 812 813 if (port == ADV7842_EDID_PORT_A) { 814 rep_write(sd, 0x72, pa >> 8); 815 rep_write(sd, 0x73, pa & 0xff); 816 } else { 817 rep_write(sd, 0x74, pa >> 8); 818 rep_write(sd, 0x75, pa & 0xff); 819 } 820 rep_write(sd, 0x76, spa_loc & 0xff); 821 rep_write_and_or(sd, 0x77, 0xbf, (spa_loc >> 2) & 0x40); 822 823 /* Calculates the checksums and enables I2C access to internal 824 * EDID ram from HDMI DDC ports 825 */ 826 rep_write_and_or(sd, 0x77, 0xf3, state->hdmi_edid.present); 827 828 for (i = 0; i < 1000; i++) { 829 if (rep_read(sd, 0x7d) & state->hdmi_edid.present) 830 break; 831 mdelay(1); 832 } 833 if (i == 1000) { 834 v4l_err(client, "error enabling edid on port %c\n", 835 (port == ADV7842_EDID_PORT_A) ? 'A' : 'B'); 836 return -EIO; 837 } 838 cec_s_phys_addr(state->cec_adap, parent_pa, false); 839 840 /* enable hotplug after 200 ms */ 841 schedule_delayed_work(&state->delayed_work_enable_hotplug, HZ / 5); 842 843 return 0; 844 } 845 846 /* ----------------------------------------------------------------------- */ 847 848 #ifdef CONFIG_VIDEO_ADV_DEBUG 849 static void adv7842_inv_register(struct v4l2_subdev *sd) 850 { 851 v4l2_info(sd, "0x000-0x0ff: IO Map\n"); 852 v4l2_info(sd, "0x100-0x1ff: AVLink Map\n"); 853 v4l2_info(sd, "0x200-0x2ff: CEC Map\n"); 854 v4l2_info(sd, "0x300-0x3ff: InfoFrame Map\n"); 855 v4l2_info(sd, "0x400-0x4ff: SDP_IO Map\n"); 856 v4l2_info(sd, "0x500-0x5ff: SDP Map\n"); 857 v4l2_info(sd, "0x600-0x6ff: AFE Map\n"); 858 v4l2_info(sd, "0x700-0x7ff: Repeater Map\n"); 859 v4l2_info(sd, "0x800-0x8ff: EDID Map\n"); 860 v4l2_info(sd, "0x900-0x9ff: HDMI Map\n"); 861 v4l2_info(sd, "0xa00-0xaff: CP Map\n"); 862 v4l2_info(sd, "0xb00-0xbff: VDP Map\n"); 863 } 864 865 static int adv7842_g_register(struct v4l2_subdev *sd, 866 struct v4l2_dbg_register *reg) 867 { 868 reg->size = 1; 869 switch (reg->reg >> 8) { 870 case 0: 871 reg->val = io_read(sd, reg->reg & 0xff); 872 break; 873 case 1: 874 reg->val = avlink_read(sd, reg->reg & 0xff); 875 break; 876 case 2: 877 reg->val = cec_read(sd, reg->reg & 0xff); 878 break; 879 case 3: 880 reg->val = infoframe_read(sd, reg->reg & 0xff); 881 break; 882 case 4: 883 reg->val = sdp_io_read(sd, reg->reg & 0xff); 884 break; 885 case 5: 886 reg->val = sdp_read(sd, reg->reg & 0xff); 887 break; 888 case 6: 889 reg->val = afe_read(sd, reg->reg & 0xff); 890 break; 891 case 7: 892 reg->val = rep_read(sd, reg->reg & 0xff); 893 break; 894 case 8: 895 reg->val = edid_read(sd, reg->reg & 0xff); 896 break; 897 case 9: 898 reg->val = hdmi_read(sd, reg->reg & 0xff); 899 break; 900 case 0xa: 901 reg->val = cp_read(sd, reg->reg & 0xff); 902 break; 903 case 0xb: 904 reg->val = vdp_read(sd, reg->reg & 0xff); 905 break; 906 default: 907 v4l2_info(sd, "Register %03llx not supported\n", reg->reg); 908 adv7842_inv_register(sd); 909 break; 910 } 911 return 0; 912 } 913 914 static int adv7842_s_register(struct v4l2_subdev *sd, 915 const struct v4l2_dbg_register *reg) 916 { 917 u8 val = reg->val & 0xff; 918 919 switch (reg->reg >> 8) { 920 case 0: 921 io_write(sd, reg->reg & 0xff, val); 922 break; 923 case 1: 924 avlink_write(sd, reg->reg & 0xff, val); 925 break; 926 case 2: 927 cec_write(sd, reg->reg & 0xff, val); 928 break; 929 case 3: 930 infoframe_write(sd, reg->reg & 0xff, val); 931 break; 932 case 4: 933 sdp_io_write(sd, reg->reg & 0xff, val); 934 break; 935 case 5: 936 sdp_write(sd, reg->reg & 0xff, val); 937 break; 938 case 6: 939 afe_write(sd, reg->reg & 0xff, val); 940 break; 941 case 7: 942 rep_write(sd, reg->reg & 0xff, val); 943 break; 944 case 8: 945 edid_write(sd, reg->reg & 0xff, val); 946 break; 947 case 9: 948 hdmi_write(sd, reg->reg & 0xff, val); 949 break; 950 case 0xa: 951 cp_write(sd, reg->reg & 0xff, val); 952 break; 953 case 0xb: 954 vdp_write(sd, reg->reg & 0xff, val); 955 break; 956 default: 957 v4l2_info(sd, "Register %03llx not supported\n", reg->reg); 958 adv7842_inv_register(sd); 959 break; 960 } 961 return 0; 962 } 963 #endif 964 965 static int adv7842_s_detect_tx_5v_ctrl(struct v4l2_subdev *sd) 966 { 967 struct adv7842_state *state = to_state(sd); 968 u16 cable_det = adv7842_read_cable_det(sd); 969 970 v4l2_dbg(1, debug, sd, "%s: 0x%x\n", __func__, cable_det); 971 972 return v4l2_ctrl_s_ctrl(state->detect_tx_5v_ctrl, cable_det); 973 } 974 975 static int find_and_set_predefined_video_timings(struct v4l2_subdev *sd, 976 u8 prim_mode, 977 const struct adv7842_video_standards *predef_vid_timings, 978 const struct v4l2_dv_timings *timings) 979 { 980 int i; 981 982 for (i = 0; predef_vid_timings[i].timings.bt.width; i++) { 983 if (!v4l2_match_dv_timings(timings, &predef_vid_timings[i].timings, 984 is_digital_input(sd) ? 250000 : 1000000, false)) 985 continue; 986 /* video std */ 987 io_write(sd, 0x00, predef_vid_timings[i].vid_std); 988 /* v_freq and prim mode */ 989 io_write(sd, 0x01, (predef_vid_timings[i].v_freq << 4) + prim_mode); 990 return 0; 991 } 992 993 return -1; 994 } 995 996 static int configure_predefined_video_timings(struct v4l2_subdev *sd, 997 struct v4l2_dv_timings *timings) 998 { 999 struct adv7842_state *state = to_state(sd); 1000 int err; 1001 1002 v4l2_dbg(1, debug, sd, "%s\n", __func__); 1003 1004 /* reset to default values */ 1005 io_write(sd, 0x16, 0x43); 1006 io_write(sd, 0x17, 0x5a); 1007 /* disable embedded syncs for auto graphics mode */ 1008 cp_write_and_or(sd, 0x81, 0xef, 0x00); 1009 cp_write(sd, 0x26, 0x00); 1010 cp_write(sd, 0x27, 0x00); 1011 cp_write(sd, 0x28, 0x00); 1012 cp_write(sd, 0x29, 0x00); 1013 cp_write(sd, 0x8f, 0x40); 1014 cp_write(sd, 0x90, 0x00); 1015 cp_write(sd, 0xa5, 0x00); 1016 cp_write(sd, 0xa6, 0x00); 1017 cp_write(sd, 0xa7, 0x00); 1018 cp_write(sd, 0xab, 0x00); 1019 cp_write(sd, 0xac, 0x00); 1020 1021 switch (state->mode) { 1022 case ADV7842_MODE_COMP: 1023 case ADV7842_MODE_RGB: 1024 err = find_and_set_predefined_video_timings(sd, 1025 0x01, adv7842_prim_mode_comp, timings); 1026 if (err) 1027 err = find_and_set_predefined_video_timings(sd, 1028 0x02, adv7842_prim_mode_gr, timings); 1029 break; 1030 case ADV7842_MODE_HDMI: 1031 err = find_and_set_predefined_video_timings(sd, 1032 0x05, adv7842_prim_mode_hdmi_comp, timings); 1033 if (err) 1034 err = find_and_set_predefined_video_timings(sd, 1035 0x06, adv7842_prim_mode_hdmi_gr, timings); 1036 break; 1037 default: 1038 v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n", 1039 __func__, state->mode); 1040 err = -1; 1041 break; 1042 } 1043 1044 1045 return err; 1046 } 1047 1048 static void configure_custom_video_timings(struct v4l2_subdev *sd, 1049 const struct v4l2_bt_timings *bt) 1050 { 1051 struct adv7842_state *state = to_state(sd); 1052 struct i2c_client *client = v4l2_get_subdevdata(sd); 1053 u32 width = htotal(bt); 1054 u32 height = vtotal(bt); 1055 u16 cp_start_sav = bt->hsync + bt->hbackporch - 4; 1056 u16 cp_start_eav = width - bt->hfrontporch; 1057 u16 cp_start_vbi = height - bt->vfrontporch + 1; 1058 u16 cp_end_vbi = bt->vsync + bt->vbackporch + 1; 1059 u16 ch1_fr_ll = (((u32)bt->pixelclock / 100) > 0) ? 1060 ((width * (ADV7842_fsc / 100)) / ((u32)bt->pixelclock / 100)) : 0; 1061 const u8 pll[2] = { 1062 0xc0 | ((width >> 8) & 0x1f), 1063 width & 0xff 1064 }; 1065 1066 v4l2_dbg(2, debug, sd, "%s\n", __func__); 1067 1068 switch (state->mode) { 1069 case ADV7842_MODE_COMP: 1070 case ADV7842_MODE_RGB: 1071 /* auto graphics */ 1072 io_write(sd, 0x00, 0x07); /* video std */ 1073 io_write(sd, 0x01, 0x02); /* prim mode */ 1074 /* enable embedded syncs for auto graphics mode */ 1075 cp_write_and_or(sd, 0x81, 0xef, 0x10); 1076 1077 /* Should only be set in auto-graphics mode [REF_02, p. 91-92] */ 1078 /* setup PLL_DIV_MAN_EN and PLL_DIV_RATIO */ 1079 /* IO-map reg. 0x16 and 0x17 should be written in sequence */ 1080 if (i2c_smbus_write_i2c_block_data(client, 0x16, 2, pll)) { 1081 v4l2_err(sd, "writing to reg 0x16 and 0x17 failed\n"); 1082 break; 1083 } 1084 1085 /* active video - horizontal timing */ 1086 cp_write(sd, 0x26, (cp_start_sav >> 8) & 0xf); 1087 cp_write(sd, 0x27, (cp_start_sav & 0xff)); 1088 cp_write(sd, 0x28, (cp_start_eav >> 8) & 0xf); 1089 cp_write(sd, 0x29, (cp_start_eav & 0xff)); 1090 1091 /* active video - vertical timing */ 1092 cp_write(sd, 0xa5, (cp_start_vbi >> 4) & 0xff); 1093 cp_write(sd, 0xa6, ((cp_start_vbi & 0xf) << 4) | 1094 ((cp_end_vbi >> 8) & 0xf)); 1095 cp_write(sd, 0xa7, cp_end_vbi & 0xff); 1096 break; 1097 case ADV7842_MODE_HDMI: 1098 /* set default prim_mode/vid_std for HDMI 1099 according to [REF_03, c. 4.2] */ 1100 io_write(sd, 0x00, 0x02); /* video std */ 1101 io_write(sd, 0x01, 0x06); /* prim mode */ 1102 break; 1103 default: 1104 v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n", 1105 __func__, state->mode); 1106 break; 1107 } 1108 1109 cp_write(sd, 0x8f, (ch1_fr_ll >> 8) & 0x7); 1110 cp_write(sd, 0x90, ch1_fr_ll & 0xff); 1111 cp_write(sd, 0xab, (height >> 4) & 0xff); 1112 cp_write(sd, 0xac, (height & 0x0f) << 4); 1113 } 1114 1115 static void adv7842_set_offset(struct v4l2_subdev *sd, bool auto_offset, u16 offset_a, u16 offset_b, u16 offset_c) 1116 { 1117 struct adv7842_state *state = to_state(sd); 1118 u8 offset_buf[4]; 1119 1120 if (auto_offset) { 1121 offset_a = 0x3ff; 1122 offset_b = 0x3ff; 1123 offset_c = 0x3ff; 1124 } 1125 1126 v4l2_dbg(2, debug, sd, "%s: %s offset: a = 0x%x, b = 0x%x, c = 0x%x\n", 1127 __func__, auto_offset ? "Auto" : "Manual", 1128 offset_a, offset_b, offset_c); 1129 1130 offset_buf[0]= (cp_read(sd, 0x77) & 0xc0) | ((offset_a & 0x3f0) >> 4); 1131 offset_buf[1] = ((offset_a & 0x00f) << 4) | ((offset_b & 0x3c0) >> 6); 1132 offset_buf[2] = ((offset_b & 0x03f) << 2) | ((offset_c & 0x300) >> 8); 1133 offset_buf[3] = offset_c & 0x0ff; 1134 1135 /* Registers must be written in this order with no i2c access in between */ 1136 if (i2c_smbus_write_i2c_block_data(state->i2c_cp, 0x77, 4, offset_buf)) 1137 v4l2_err(sd, "%s: i2c error writing to CP reg 0x77, 0x78, 0x79, 0x7a\n", __func__); 1138 } 1139 1140 static void adv7842_set_gain(struct v4l2_subdev *sd, bool auto_gain, u16 gain_a, u16 gain_b, u16 gain_c) 1141 { 1142 struct adv7842_state *state = to_state(sd); 1143 u8 gain_buf[4]; 1144 u8 gain_man = 1; 1145 u8 agc_mode_man = 1; 1146 1147 if (auto_gain) { 1148 gain_man = 0; 1149 agc_mode_man = 0; 1150 gain_a = 0x100; 1151 gain_b = 0x100; 1152 gain_c = 0x100; 1153 } 1154 1155 v4l2_dbg(2, debug, sd, "%s: %s gain: a = 0x%x, b = 0x%x, c = 0x%x\n", 1156 __func__, auto_gain ? "Auto" : "Manual", 1157 gain_a, gain_b, gain_c); 1158 1159 gain_buf[0] = ((gain_man << 7) | (agc_mode_man << 6) | ((gain_a & 0x3f0) >> 4)); 1160 gain_buf[1] = (((gain_a & 0x00f) << 4) | ((gain_b & 0x3c0) >> 6)); 1161 gain_buf[2] = (((gain_b & 0x03f) << 2) | ((gain_c & 0x300) >> 8)); 1162 gain_buf[3] = ((gain_c & 0x0ff)); 1163 1164 /* Registers must be written in this order with no i2c access in between */ 1165 if (i2c_smbus_write_i2c_block_data(state->i2c_cp, 0x73, 4, gain_buf)) 1166 v4l2_err(sd, "%s: i2c error writing to CP reg 0x73, 0x74, 0x75, 0x76\n", __func__); 1167 } 1168 1169 static void set_rgb_quantization_range(struct v4l2_subdev *sd) 1170 { 1171 struct adv7842_state *state = to_state(sd); 1172 bool rgb_output = io_read(sd, 0x02) & 0x02; 1173 bool hdmi_signal = hdmi_read(sd, 0x05) & 0x80; 1174 u8 y = HDMI_COLORSPACE_RGB; 1175 1176 if (hdmi_signal && (io_read(sd, 0x60) & 1)) 1177 y = infoframe_read(sd, 0x01) >> 5; 1178 1179 v4l2_dbg(2, debug, sd, "%s: RGB quantization range: %d, RGB out: %d, HDMI: %d\n", 1180 __func__, state->rgb_quantization_range, 1181 rgb_output, hdmi_signal); 1182 1183 adv7842_set_gain(sd, true, 0x0, 0x0, 0x0); 1184 adv7842_set_offset(sd, true, 0x0, 0x0, 0x0); 1185 io_write_clr_set(sd, 0x02, 0x04, rgb_output ? 0 : 4); 1186 1187 switch (state->rgb_quantization_range) { 1188 case V4L2_DV_RGB_RANGE_AUTO: 1189 if (state->mode == ADV7842_MODE_RGB) { 1190 /* Receiving analog RGB signal 1191 * Set RGB full range (0-255) */ 1192 io_write_and_or(sd, 0x02, 0x0f, 0x10); 1193 break; 1194 } 1195 1196 if (state->mode == ADV7842_MODE_COMP) { 1197 /* Receiving analog YPbPr signal 1198 * Set automode */ 1199 io_write_and_or(sd, 0x02, 0x0f, 0xf0); 1200 break; 1201 } 1202 1203 if (hdmi_signal) { 1204 /* Receiving HDMI signal 1205 * Set automode */ 1206 io_write_and_or(sd, 0x02, 0x0f, 0xf0); 1207 break; 1208 } 1209 1210 /* Receiving DVI-D signal 1211 * ADV7842 selects RGB limited range regardless of 1212 * input format (CE/IT) in automatic mode */ 1213 if (state->timings.bt.flags & V4L2_DV_FL_IS_CE_VIDEO) { 1214 /* RGB limited range (16-235) */ 1215 io_write_and_or(sd, 0x02, 0x0f, 0x00); 1216 } else { 1217 /* RGB full range (0-255) */ 1218 io_write_and_or(sd, 0x02, 0x0f, 0x10); 1219 1220 if (is_digital_input(sd) && rgb_output) { 1221 adv7842_set_offset(sd, false, 0x40, 0x40, 0x40); 1222 } else { 1223 adv7842_set_gain(sd, false, 0xe0, 0xe0, 0xe0); 1224 adv7842_set_offset(sd, false, 0x70, 0x70, 0x70); 1225 } 1226 } 1227 break; 1228 case V4L2_DV_RGB_RANGE_LIMITED: 1229 if (state->mode == ADV7842_MODE_COMP) { 1230 /* YCrCb limited range (16-235) */ 1231 io_write_and_or(sd, 0x02, 0x0f, 0x20); 1232 break; 1233 } 1234 1235 if (y != HDMI_COLORSPACE_RGB) 1236 break; 1237 1238 /* RGB limited range (16-235) */ 1239 io_write_and_or(sd, 0x02, 0x0f, 0x00); 1240 1241 break; 1242 case V4L2_DV_RGB_RANGE_FULL: 1243 if (state->mode == ADV7842_MODE_COMP) { 1244 /* YCrCb full range (0-255) */ 1245 io_write_and_or(sd, 0x02, 0x0f, 0x60); 1246 break; 1247 } 1248 1249 if (y != HDMI_COLORSPACE_RGB) 1250 break; 1251 1252 /* RGB full range (0-255) */ 1253 io_write_and_or(sd, 0x02, 0x0f, 0x10); 1254 1255 if (is_analog_input(sd) || hdmi_signal) 1256 break; 1257 1258 /* Adjust gain/offset for DVI-D signals only */ 1259 if (rgb_output) { 1260 adv7842_set_offset(sd, false, 0x40, 0x40, 0x40); 1261 } else { 1262 adv7842_set_gain(sd, false, 0xe0, 0xe0, 0xe0); 1263 adv7842_set_offset(sd, false, 0x70, 0x70, 0x70); 1264 } 1265 break; 1266 } 1267 } 1268 1269 static int adv7842_s_ctrl(struct v4l2_ctrl *ctrl) 1270 { 1271 struct v4l2_subdev *sd = to_sd(ctrl); 1272 struct adv7842_state *state = to_state(sd); 1273 1274 /* TODO SDP ctrls 1275 contrast/brightness/hue/free run is acting a bit strange, 1276 not sure if sdp csc is correct. 1277 */ 1278 switch (ctrl->id) { 1279 /* standard ctrls */ 1280 case V4L2_CID_BRIGHTNESS: 1281 cp_write(sd, 0x3c, ctrl->val); 1282 sdp_write(sd, 0x14, ctrl->val); 1283 /* ignore lsb sdp 0x17[3:2] */ 1284 return 0; 1285 case V4L2_CID_CONTRAST: 1286 cp_write(sd, 0x3a, ctrl->val); 1287 sdp_write(sd, 0x13, ctrl->val); 1288 /* ignore lsb sdp 0x17[1:0] */ 1289 return 0; 1290 case V4L2_CID_SATURATION: 1291 cp_write(sd, 0x3b, ctrl->val); 1292 sdp_write(sd, 0x15, ctrl->val); 1293 /* ignore lsb sdp 0x17[5:4] */ 1294 return 0; 1295 case V4L2_CID_HUE: 1296 cp_write(sd, 0x3d, ctrl->val); 1297 sdp_write(sd, 0x16, ctrl->val); 1298 /* ignore lsb sdp 0x17[7:6] */ 1299 return 0; 1300 /* custom ctrls */ 1301 case V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE: 1302 afe_write(sd, 0xc8, ctrl->val); 1303 return 0; 1304 case V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL: 1305 cp_write_and_or(sd, 0xbf, ~0x04, (ctrl->val << 2)); 1306 sdp_write_and_or(sd, 0xdd, ~0x04, (ctrl->val << 2)); 1307 return 0; 1308 case V4L2_CID_ADV_RX_FREE_RUN_COLOR: { 1309 u8 R = (ctrl->val & 0xff0000) >> 16; 1310 u8 G = (ctrl->val & 0x00ff00) >> 8; 1311 u8 B = (ctrl->val & 0x0000ff); 1312 /* RGB -> YUV, numerical approximation */ 1313 int Y = 66 * R + 129 * G + 25 * B; 1314 int U = -38 * R - 74 * G + 112 * B; 1315 int V = 112 * R - 94 * G - 18 * B; 1316 1317 /* Scale down to 8 bits with rounding */ 1318 Y = (Y + 128) >> 8; 1319 U = (U + 128) >> 8; 1320 V = (V + 128) >> 8; 1321 /* make U,V positive */ 1322 Y += 16; 1323 U += 128; 1324 V += 128; 1325 1326 v4l2_dbg(1, debug, sd, "R %x, G %x, B %x\n", R, G, B); 1327 v4l2_dbg(1, debug, sd, "Y %x, U %x, V %x\n", Y, U, V); 1328 1329 /* CP */ 1330 cp_write(sd, 0xc1, R); 1331 cp_write(sd, 0xc0, G); 1332 cp_write(sd, 0xc2, B); 1333 /* SDP */ 1334 sdp_write(sd, 0xde, Y); 1335 sdp_write(sd, 0xdf, (V & 0xf0) | ((U >> 4) & 0x0f)); 1336 return 0; 1337 } 1338 case V4L2_CID_DV_RX_RGB_RANGE: 1339 state->rgb_quantization_range = ctrl->val; 1340 set_rgb_quantization_range(sd); 1341 return 0; 1342 } 1343 return -EINVAL; 1344 } 1345 1346 static int adv7842_g_volatile_ctrl(struct v4l2_ctrl *ctrl) 1347 { 1348 struct v4l2_subdev *sd = to_sd(ctrl); 1349 1350 if (ctrl->id == V4L2_CID_DV_RX_IT_CONTENT_TYPE) { 1351 ctrl->val = V4L2_DV_IT_CONTENT_TYPE_NO_ITC; 1352 if ((io_read(sd, 0x60) & 1) && (infoframe_read(sd, 0x03) & 0x80)) 1353 ctrl->val = (infoframe_read(sd, 0x05) >> 4) & 3; 1354 return 0; 1355 } 1356 return -EINVAL; 1357 } 1358 1359 static inline bool no_power(struct v4l2_subdev *sd) 1360 { 1361 return io_read(sd, 0x0c) & 0x24; 1362 } 1363 1364 static inline bool no_cp_signal(struct v4l2_subdev *sd) 1365 { 1366 return ((cp_read(sd, 0xb5) & 0xd0) != 0xd0) || !(cp_read(sd, 0xb1) & 0x80); 1367 } 1368 1369 static inline bool is_hdmi(struct v4l2_subdev *sd) 1370 { 1371 return hdmi_read(sd, 0x05) & 0x80; 1372 } 1373 1374 static int adv7842_g_input_status(struct v4l2_subdev *sd, u32 *status) 1375 { 1376 struct adv7842_state *state = to_state(sd); 1377 1378 *status = 0; 1379 1380 if (io_read(sd, 0x0c) & 0x24) 1381 *status |= V4L2_IN_ST_NO_POWER; 1382 1383 if (state->mode == ADV7842_MODE_SDP) { 1384 /* status from SDP block */ 1385 if (!(sdp_read(sd, 0x5A) & 0x01)) 1386 *status |= V4L2_IN_ST_NO_SIGNAL; 1387 1388 v4l2_dbg(1, debug, sd, "%s: SDP status = 0x%x\n", 1389 __func__, *status); 1390 return 0; 1391 } 1392 /* status from CP block */ 1393 if ((cp_read(sd, 0xb5) & 0xd0) != 0xd0 || 1394 !(cp_read(sd, 0xb1) & 0x80)) 1395 /* TODO channel 2 */ 1396 *status |= V4L2_IN_ST_NO_SIGNAL; 1397 1398 if (is_digital_input(sd) && ((io_read(sd, 0x74) & 0x03) != 0x03)) 1399 *status |= V4L2_IN_ST_NO_SIGNAL; 1400 1401 v4l2_dbg(1, debug, sd, "%s: CP status = 0x%x\n", 1402 __func__, *status); 1403 1404 return 0; 1405 } 1406 1407 struct stdi_readback { 1408 u16 bl, lcf, lcvs; 1409 u8 hs_pol, vs_pol; 1410 bool interlaced; 1411 }; 1412 1413 static int stdi2dv_timings(struct v4l2_subdev *sd, 1414 struct stdi_readback *stdi, 1415 struct v4l2_dv_timings *timings) 1416 { 1417 struct adv7842_state *state = to_state(sd); 1418 u32 hfreq = (ADV7842_fsc * 8) / stdi->bl; 1419 u32 pix_clk; 1420 int i; 1421 1422 for (i = 0; v4l2_dv_timings_presets[i].bt.width; i++) { 1423 const struct v4l2_bt_timings *bt = &v4l2_dv_timings_presets[i].bt; 1424 1425 if (!v4l2_valid_dv_timings(&v4l2_dv_timings_presets[i], 1426 adv7842_get_dv_timings_cap(sd), 1427 adv7842_check_dv_timings, NULL)) 1428 continue; 1429 if (vtotal(bt) != stdi->lcf + 1) 1430 continue; 1431 if (bt->vsync != stdi->lcvs) 1432 continue; 1433 1434 pix_clk = hfreq * htotal(bt); 1435 1436 if ((pix_clk < bt->pixelclock + 1000000) && 1437 (pix_clk > bt->pixelclock - 1000000)) { 1438 *timings = v4l2_dv_timings_presets[i]; 1439 return 0; 1440 } 1441 } 1442 1443 if (v4l2_detect_cvt(stdi->lcf + 1, hfreq, stdi->lcvs, 0, 1444 (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) | 1445 (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0), 1446 false, timings)) 1447 return 0; 1448 if (v4l2_detect_gtf(stdi->lcf + 1, hfreq, stdi->lcvs, 1449 (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) | 1450 (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0), 1451 false, state->aspect_ratio, timings)) 1452 return 0; 1453 1454 v4l2_dbg(2, debug, sd, 1455 "%s: No format candidate found for lcvs = %d, lcf=%d, bl = %d, %chsync, %cvsync\n", 1456 __func__, stdi->lcvs, stdi->lcf, stdi->bl, 1457 stdi->hs_pol, stdi->vs_pol); 1458 return -1; 1459 } 1460 1461 static int read_stdi(struct v4l2_subdev *sd, struct stdi_readback *stdi) 1462 { 1463 u32 status; 1464 1465 adv7842_g_input_status(sd, &status); 1466 if (status & V4L2_IN_ST_NO_SIGNAL) { 1467 v4l2_dbg(2, debug, sd, "%s: no signal\n", __func__); 1468 return -ENOLINK; 1469 } 1470 1471 stdi->bl = ((cp_read(sd, 0xb1) & 0x3f) << 8) | cp_read(sd, 0xb2); 1472 stdi->lcf = ((cp_read(sd, 0xb3) & 0x7) << 8) | cp_read(sd, 0xb4); 1473 stdi->lcvs = cp_read(sd, 0xb3) >> 3; 1474 1475 if ((cp_read(sd, 0xb5) & 0x80) && ((cp_read(sd, 0xb5) & 0x03) == 0x01)) { 1476 stdi->hs_pol = ((cp_read(sd, 0xb5) & 0x10) ? 1477 ((cp_read(sd, 0xb5) & 0x08) ? '+' : '-') : 'x'); 1478 stdi->vs_pol = ((cp_read(sd, 0xb5) & 0x40) ? 1479 ((cp_read(sd, 0xb5) & 0x20) ? '+' : '-') : 'x'); 1480 } else { 1481 stdi->hs_pol = 'x'; 1482 stdi->vs_pol = 'x'; 1483 } 1484 stdi->interlaced = (cp_read(sd, 0xb1) & 0x40) ? true : false; 1485 1486 if (stdi->lcf < 239 || stdi->bl < 8 || stdi->bl == 0x3fff) { 1487 v4l2_dbg(2, debug, sd, "%s: invalid signal\n", __func__); 1488 return -ENOLINK; 1489 } 1490 1491 v4l2_dbg(2, debug, sd, 1492 "%s: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %chsync, %cvsync, %s\n", 1493 __func__, stdi->lcf, stdi->bl, stdi->lcvs, 1494 stdi->hs_pol, stdi->vs_pol, 1495 stdi->interlaced ? "interlaced" : "progressive"); 1496 1497 return 0; 1498 } 1499 1500 static int adv7842_enum_dv_timings(struct v4l2_subdev *sd, 1501 struct v4l2_enum_dv_timings *timings) 1502 { 1503 if (timings->pad != 0) 1504 return -EINVAL; 1505 1506 return v4l2_enum_dv_timings_cap(timings, 1507 adv7842_get_dv_timings_cap(sd), adv7842_check_dv_timings, NULL); 1508 } 1509 1510 static int adv7842_dv_timings_cap(struct v4l2_subdev *sd, 1511 struct v4l2_dv_timings_cap *cap) 1512 { 1513 if (cap->pad != 0) 1514 return -EINVAL; 1515 1516 *cap = *adv7842_get_dv_timings_cap(sd); 1517 return 0; 1518 } 1519 1520 /* Fill the optional fields .standards and .flags in struct v4l2_dv_timings 1521 if the format is listed in adv7842_timings[] */ 1522 static void adv7842_fill_optional_dv_timings_fields(struct v4l2_subdev *sd, 1523 struct v4l2_dv_timings *timings) 1524 { 1525 v4l2_find_dv_timings_cap(timings, adv7842_get_dv_timings_cap(sd), 1526 is_digital_input(sd) ? 250000 : 1000000, 1527 adv7842_check_dv_timings, NULL); 1528 timings->bt.flags |= V4L2_DV_FL_CAN_DETECT_REDUCED_FPS; 1529 } 1530 1531 static int adv7842_query_dv_timings(struct v4l2_subdev *sd, 1532 struct v4l2_dv_timings *timings) 1533 { 1534 struct adv7842_state *state = to_state(sd); 1535 struct v4l2_bt_timings *bt = &timings->bt; 1536 struct stdi_readback stdi = { 0 }; 1537 1538 v4l2_dbg(1, debug, sd, "%s:\n", __func__); 1539 1540 memset(timings, 0, sizeof(struct v4l2_dv_timings)); 1541 1542 /* SDP block */ 1543 if (state->mode == ADV7842_MODE_SDP) 1544 return -ENODATA; 1545 1546 /* read STDI */ 1547 if (read_stdi(sd, &stdi)) { 1548 state->restart_stdi_once = true; 1549 v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__); 1550 return -ENOLINK; 1551 } 1552 bt->interlaced = stdi.interlaced ? 1553 V4L2_DV_INTERLACED : V4L2_DV_PROGRESSIVE; 1554 bt->standards = V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT | 1555 V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT; 1556 1557 if (is_digital_input(sd)) { 1558 u32 freq; 1559 1560 timings->type = V4L2_DV_BT_656_1120; 1561 1562 bt->width = (hdmi_read(sd, 0x07) & 0x0f) * 256 + hdmi_read(sd, 0x08); 1563 bt->height = (hdmi_read(sd, 0x09) & 0x0f) * 256 + hdmi_read(sd, 0x0a); 1564 freq = ((hdmi_read(sd, 0x51) << 1) + (hdmi_read(sd, 0x52) >> 7)) * 1000000; 1565 freq += ((hdmi_read(sd, 0x52) & 0x7f) * 7813); 1566 if (is_hdmi(sd)) { 1567 /* adjust for deep color mode */ 1568 freq = freq * 8 / (((hdmi_read(sd, 0x0b) & 0xc0) >> 6) * 2 + 8); 1569 } 1570 bt->pixelclock = freq; 1571 bt->hfrontporch = (hdmi_read(sd, 0x20) & 0x03) * 256 + 1572 hdmi_read(sd, 0x21); 1573 bt->hsync = (hdmi_read(sd, 0x22) & 0x03) * 256 + 1574 hdmi_read(sd, 0x23); 1575 bt->hbackporch = (hdmi_read(sd, 0x24) & 0x03) * 256 + 1576 hdmi_read(sd, 0x25); 1577 bt->vfrontporch = ((hdmi_read(sd, 0x2a) & 0x1f) * 256 + 1578 hdmi_read(sd, 0x2b)) / 2; 1579 bt->vsync = ((hdmi_read(sd, 0x2e) & 0x1f) * 256 + 1580 hdmi_read(sd, 0x2f)) / 2; 1581 bt->vbackporch = ((hdmi_read(sd, 0x32) & 0x1f) * 256 + 1582 hdmi_read(sd, 0x33)) / 2; 1583 bt->polarities = ((hdmi_read(sd, 0x05) & 0x10) ? V4L2_DV_VSYNC_POS_POL : 0) | 1584 ((hdmi_read(sd, 0x05) & 0x20) ? V4L2_DV_HSYNC_POS_POL : 0); 1585 if (bt->interlaced == V4L2_DV_INTERLACED) { 1586 bt->height += (hdmi_read(sd, 0x0b) & 0x0f) * 256 + 1587 hdmi_read(sd, 0x0c); 1588 bt->il_vfrontporch = ((hdmi_read(sd, 0x2c) & 0x1f) * 256 + 1589 hdmi_read(sd, 0x2d)) / 2; 1590 bt->il_vsync = ((hdmi_read(sd, 0x30) & 0x1f) * 256 + 1591 hdmi_read(sd, 0x31)) / 2; 1592 bt->il_vbackporch = ((hdmi_read(sd, 0x34) & 0x1f) * 256 + 1593 hdmi_read(sd, 0x35)) / 2; 1594 } else { 1595 bt->il_vfrontporch = 0; 1596 bt->il_vsync = 0; 1597 bt->il_vbackporch = 0; 1598 } 1599 adv7842_fill_optional_dv_timings_fields(sd, timings); 1600 if ((timings->bt.flags & V4L2_DV_FL_CAN_REDUCE_FPS) && 1601 freq < bt->pixelclock) { 1602 u32 reduced_freq = ((u32)bt->pixelclock / 1001) * 1000; 1603 u32 delta_freq = abs(freq - reduced_freq); 1604 1605 if (delta_freq < ((u32)bt->pixelclock - reduced_freq) / 2) 1606 timings->bt.flags |= V4L2_DV_FL_REDUCED_FPS; 1607 } 1608 } else { 1609 /* find format 1610 * Since LCVS values are inaccurate [REF_03, p. 339-340], 1611 * stdi2dv_timings() is called with lcvs +-1 if the first attempt fails. 1612 */ 1613 if (!stdi2dv_timings(sd, &stdi, timings)) 1614 goto found; 1615 stdi.lcvs += 1; 1616 v4l2_dbg(1, debug, sd, "%s: lcvs + 1 = %d\n", __func__, stdi.lcvs); 1617 if (!stdi2dv_timings(sd, &stdi, timings)) 1618 goto found; 1619 stdi.lcvs -= 2; 1620 v4l2_dbg(1, debug, sd, "%s: lcvs - 1 = %d\n", __func__, stdi.lcvs); 1621 if (stdi2dv_timings(sd, &stdi, timings)) { 1622 /* 1623 * The STDI block may measure wrong values, especially 1624 * for lcvs and lcf. If the driver can not find any 1625 * valid timing, the STDI block is restarted to measure 1626 * the video timings again. The function will return an 1627 * error, but the restart of STDI will generate a new 1628 * STDI interrupt and the format detection process will 1629 * restart. 1630 */ 1631 if (state->restart_stdi_once) { 1632 v4l2_dbg(1, debug, sd, "%s: restart STDI\n", __func__); 1633 /* TODO restart STDI for Sync Channel 2 */ 1634 /* enter one-shot mode */ 1635 cp_write_and_or(sd, 0x86, 0xf9, 0x00); 1636 /* trigger STDI restart */ 1637 cp_write_and_or(sd, 0x86, 0xf9, 0x04); 1638 /* reset to continuous mode */ 1639 cp_write_and_or(sd, 0x86, 0xf9, 0x02); 1640 state->restart_stdi_once = false; 1641 return -ENOLINK; 1642 } 1643 v4l2_dbg(1, debug, sd, "%s: format not supported\n", __func__); 1644 return -ERANGE; 1645 } 1646 state->restart_stdi_once = true; 1647 } 1648 found: 1649 1650 if (debug > 1) 1651 v4l2_print_dv_timings(sd->name, "adv7842_query_dv_timings:", 1652 timings, true); 1653 return 0; 1654 } 1655 1656 static int adv7842_s_dv_timings(struct v4l2_subdev *sd, 1657 struct v4l2_dv_timings *timings) 1658 { 1659 struct adv7842_state *state = to_state(sd); 1660 struct v4l2_bt_timings *bt; 1661 int err; 1662 1663 v4l2_dbg(1, debug, sd, "%s:\n", __func__); 1664 1665 if (state->mode == ADV7842_MODE_SDP) 1666 return -ENODATA; 1667 1668 if (v4l2_match_dv_timings(&state->timings, timings, 0, false)) { 1669 v4l2_dbg(1, debug, sd, "%s: no change\n", __func__); 1670 return 0; 1671 } 1672 1673 bt = &timings->bt; 1674 1675 if (!v4l2_valid_dv_timings(timings, adv7842_get_dv_timings_cap(sd), 1676 adv7842_check_dv_timings, NULL)) 1677 return -ERANGE; 1678 1679 adv7842_fill_optional_dv_timings_fields(sd, timings); 1680 1681 state->timings = *timings; 1682 1683 cp_write(sd, 0x91, bt->interlaced ? 0x40 : 0x00); 1684 1685 /* Use prim_mode and vid_std when available */ 1686 err = configure_predefined_video_timings(sd, timings); 1687 if (err) { 1688 /* custom settings when the video format 1689 does not have prim_mode/vid_std */ 1690 configure_custom_video_timings(sd, bt); 1691 } 1692 1693 set_rgb_quantization_range(sd); 1694 1695 1696 if (debug > 1) 1697 v4l2_print_dv_timings(sd->name, "adv7842_s_dv_timings: ", 1698 timings, true); 1699 return 0; 1700 } 1701 1702 static int adv7842_g_dv_timings(struct v4l2_subdev *sd, 1703 struct v4l2_dv_timings *timings) 1704 { 1705 struct adv7842_state *state = to_state(sd); 1706 1707 if (state->mode == ADV7842_MODE_SDP) 1708 return -ENODATA; 1709 *timings = state->timings; 1710 return 0; 1711 } 1712 1713 static void enable_input(struct v4l2_subdev *sd) 1714 { 1715 struct adv7842_state *state = to_state(sd); 1716 1717 set_rgb_quantization_range(sd); 1718 switch (state->mode) { 1719 case ADV7842_MODE_SDP: 1720 case ADV7842_MODE_COMP: 1721 case ADV7842_MODE_RGB: 1722 io_write(sd, 0x15, 0xb0); /* Disable Tristate of Pins (no audio) */ 1723 break; 1724 case ADV7842_MODE_HDMI: 1725 hdmi_write(sd, 0x01, 0x00); /* Enable HDMI clock terminators */ 1726 io_write(sd, 0x15, 0xa0); /* Disable Tristate of Pins */ 1727 hdmi_write_and_or(sd, 0x1a, 0xef, 0x00); /* Unmute audio */ 1728 break; 1729 default: 1730 v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n", 1731 __func__, state->mode); 1732 break; 1733 } 1734 } 1735 1736 static void disable_input(struct v4l2_subdev *sd) 1737 { 1738 hdmi_write_and_or(sd, 0x1a, 0xef, 0x10); /* Mute audio [REF_01, c. 2.2.2] */ 1739 msleep(16); /* 512 samples with >= 32 kHz sample rate [REF_03, c. 8.29] */ 1740 io_write(sd, 0x15, 0xbe); /* Tristate all outputs from video core */ 1741 hdmi_write(sd, 0x01, 0x78); /* Disable HDMI clock terminators */ 1742 } 1743 1744 static void sdp_csc_coeff(struct v4l2_subdev *sd, 1745 const struct adv7842_sdp_csc_coeff *c) 1746 { 1747 /* csc auto/manual */ 1748 sdp_io_write_and_or(sd, 0xe0, 0xbf, c->manual ? 0x00 : 0x40); 1749 1750 if (!c->manual) 1751 return; 1752 1753 /* csc scaling */ 1754 sdp_io_write_and_or(sd, 0xe0, 0x7f, c->scaling == 2 ? 0x80 : 0x00); 1755 1756 /* A coeff */ 1757 sdp_io_write_and_or(sd, 0xe0, 0xe0, c->A1 >> 8); 1758 sdp_io_write(sd, 0xe1, c->A1); 1759 sdp_io_write_and_or(sd, 0xe2, 0xe0, c->A2 >> 8); 1760 sdp_io_write(sd, 0xe3, c->A2); 1761 sdp_io_write_and_or(sd, 0xe4, 0xe0, c->A3 >> 8); 1762 sdp_io_write(sd, 0xe5, c->A3); 1763 1764 /* A scale */ 1765 sdp_io_write_and_or(sd, 0xe6, 0x80, c->A4 >> 8); 1766 sdp_io_write(sd, 0xe7, c->A4); 1767 1768 /* B coeff */ 1769 sdp_io_write_and_or(sd, 0xe8, 0xe0, c->B1 >> 8); 1770 sdp_io_write(sd, 0xe9, c->B1); 1771 sdp_io_write_and_or(sd, 0xea, 0xe0, c->B2 >> 8); 1772 sdp_io_write(sd, 0xeb, c->B2); 1773 sdp_io_write_and_or(sd, 0xec, 0xe0, c->B3 >> 8); 1774 sdp_io_write(sd, 0xed, c->B3); 1775 1776 /* B scale */ 1777 sdp_io_write_and_or(sd, 0xee, 0x80, c->B4 >> 8); 1778 sdp_io_write(sd, 0xef, c->B4); 1779 1780 /* C coeff */ 1781 sdp_io_write_and_or(sd, 0xf0, 0xe0, c->C1 >> 8); 1782 sdp_io_write(sd, 0xf1, c->C1); 1783 sdp_io_write_and_or(sd, 0xf2, 0xe0, c->C2 >> 8); 1784 sdp_io_write(sd, 0xf3, c->C2); 1785 sdp_io_write_and_or(sd, 0xf4, 0xe0, c->C3 >> 8); 1786 sdp_io_write(sd, 0xf5, c->C3); 1787 1788 /* C scale */ 1789 sdp_io_write_and_or(sd, 0xf6, 0x80, c->C4 >> 8); 1790 sdp_io_write(sd, 0xf7, c->C4); 1791 } 1792 1793 static void select_input(struct v4l2_subdev *sd, 1794 enum adv7842_vid_std_select vid_std_select) 1795 { 1796 struct adv7842_state *state = to_state(sd); 1797 1798 switch (state->mode) { 1799 case ADV7842_MODE_SDP: 1800 io_write(sd, 0x00, vid_std_select); /* video std: CVBS or YC mode */ 1801 io_write(sd, 0x01, 0); /* prim mode */ 1802 /* enable embedded syncs for auto graphics mode */ 1803 cp_write_and_or(sd, 0x81, 0xef, 0x10); 1804 1805 afe_write(sd, 0x00, 0x00); /* power up ADC */ 1806 afe_write(sd, 0xc8, 0x00); /* phase control */ 1807 1808 io_write(sd, 0xdd, 0x90); /* Manual 2x output clock */ 1809 /* script says register 0xde, which don't exist in manual */ 1810 1811 /* Manual analog input muxing mode, CVBS (6.4)*/ 1812 afe_write_and_or(sd, 0x02, 0x7f, 0x80); 1813 if (vid_std_select == ADV7842_SDP_VID_STD_CVBS_SD_4x1) { 1814 afe_write(sd, 0x03, 0xa0); /* ADC0 to AIN10 (CVBS), ADC1 N/C*/ 1815 afe_write(sd, 0x04, 0x00); /* ADC2 N/C,ADC3 N/C*/ 1816 } else { 1817 afe_write(sd, 0x03, 0xa0); /* ADC0 to AIN10 (CVBS), ADC1 N/C*/ 1818 afe_write(sd, 0x04, 0xc0); /* ADC2 to AIN12, ADC3 N/C*/ 1819 } 1820 afe_write(sd, 0x0c, 0x1f); /* ADI recommend write */ 1821 afe_write(sd, 0x12, 0x63); /* ADI recommend write */ 1822 1823 sdp_io_write(sd, 0xb2, 0x60); /* Disable AV codes */ 1824 sdp_io_write(sd, 0xc8, 0xe3); /* Disable Ancillary data */ 1825 1826 /* SDP recommended settings */ 1827 sdp_write(sd, 0x00, 0x3F); /* Autodetect PAL NTSC (not SECAM) */ 1828 sdp_write(sd, 0x01, 0x00); /* Pedestal Off */ 1829 1830 sdp_write(sd, 0x03, 0xE4); /* Manual VCR Gain Luma 0x40B */ 1831 sdp_write(sd, 0x04, 0x0B); /* Manual Luma setting */ 1832 sdp_write(sd, 0x05, 0xC3); /* Manual Chroma setting 0x3FE */ 1833 sdp_write(sd, 0x06, 0xFE); /* Manual Chroma setting */ 1834 sdp_write(sd, 0x12, 0x0D); /* Frame TBC,I_P, 3D comb enabled */ 1835 sdp_write(sd, 0xA7, 0x00); /* ADI Recommended Write */ 1836 sdp_io_write(sd, 0xB0, 0x00); /* Disable H and v blanking */ 1837 1838 /* deinterlacer enabled and 3D comb */ 1839 sdp_write_and_or(sd, 0x12, 0xf6, 0x09); 1840 1841 break; 1842 1843 case ADV7842_MODE_COMP: 1844 case ADV7842_MODE_RGB: 1845 /* Automatic analog input muxing mode */ 1846 afe_write_and_or(sd, 0x02, 0x7f, 0x00); 1847 /* set mode and select free run resolution */ 1848 io_write(sd, 0x00, vid_std_select); /* video std */ 1849 io_write(sd, 0x01, 0x02); /* prim mode */ 1850 cp_write_and_or(sd, 0x81, 0xef, 0x10); /* enable embedded syncs 1851 for auto graphics mode */ 1852 1853 afe_write(sd, 0x00, 0x00); /* power up ADC */ 1854 afe_write(sd, 0xc8, 0x00); /* phase control */ 1855 if (state->mode == ADV7842_MODE_COMP) { 1856 /* force to YCrCb */ 1857 io_write_and_or(sd, 0x02, 0x0f, 0x60); 1858 } else { 1859 /* force to RGB */ 1860 io_write_and_or(sd, 0x02, 0x0f, 0x10); 1861 } 1862 1863 /* set ADI recommended settings for digitizer */ 1864 /* "ADV7842 Register Settings Recommendations 1865 * (rev. 1.8, November 2010)" p. 9. */ 1866 afe_write(sd, 0x0c, 0x1f); /* ADC Range improvement */ 1867 afe_write(sd, 0x12, 0x63); /* ADC Range improvement */ 1868 1869 /* set to default gain for RGB */ 1870 cp_write(sd, 0x73, 0x10); 1871 cp_write(sd, 0x74, 0x04); 1872 cp_write(sd, 0x75, 0x01); 1873 cp_write(sd, 0x76, 0x00); 1874 1875 cp_write(sd, 0x3e, 0x04); /* CP core pre-gain control */ 1876 cp_write(sd, 0xc3, 0x39); /* CP coast control. Graphics mode */ 1877 cp_write(sd, 0x40, 0x5c); /* CP core pre-gain control. Graphics mode */ 1878 break; 1879 1880 case ADV7842_MODE_HDMI: 1881 /* Automatic analog input muxing mode */ 1882 afe_write_and_or(sd, 0x02, 0x7f, 0x00); 1883 /* set mode and select free run resolution */ 1884 if (state->hdmi_port_a) 1885 hdmi_write(sd, 0x00, 0x02); /* select port A */ 1886 else 1887 hdmi_write(sd, 0x00, 0x03); /* select port B */ 1888 io_write(sd, 0x00, vid_std_select); /* video std */ 1889 io_write(sd, 0x01, 5); /* prim mode */ 1890 cp_write_and_or(sd, 0x81, 0xef, 0x00); /* disable embedded syncs 1891 for auto graphics mode */ 1892 1893 /* set ADI recommended settings for HDMI: */ 1894 /* "ADV7842 Register Settings Recommendations 1895 * (rev. 1.8, November 2010)" p. 3. */ 1896 hdmi_write(sd, 0xc0, 0x00); 1897 hdmi_write(sd, 0x0d, 0x34); /* ADI recommended write */ 1898 hdmi_write(sd, 0x3d, 0x10); /* ADI recommended write */ 1899 hdmi_write(sd, 0x44, 0x85); /* TMDS PLL optimization */ 1900 hdmi_write(sd, 0x46, 0x1f); /* ADI recommended write */ 1901 hdmi_write(sd, 0x57, 0xb6); /* TMDS PLL optimization */ 1902 hdmi_write(sd, 0x58, 0x03); /* TMDS PLL optimization */ 1903 hdmi_write(sd, 0x60, 0x88); /* TMDS PLL optimization */ 1904 hdmi_write(sd, 0x61, 0x88); /* TMDS PLL optimization */ 1905 hdmi_write(sd, 0x6c, 0x18); /* Disable ISRC clearing bit, 1906 Improve robustness */ 1907 hdmi_write(sd, 0x75, 0x10); /* DDC drive strength */ 1908 hdmi_write(sd, 0x85, 0x1f); /* equaliser */ 1909 hdmi_write(sd, 0x87, 0x70); /* ADI recommended write */ 1910 hdmi_write(sd, 0x89, 0x04); /* equaliser */ 1911 hdmi_write(sd, 0x8a, 0x1e); /* equaliser */ 1912 hdmi_write(sd, 0x93, 0x04); /* equaliser */ 1913 hdmi_write(sd, 0x94, 0x1e); /* equaliser */ 1914 hdmi_write(sd, 0x99, 0xa1); /* ADI recommended write */ 1915 hdmi_write(sd, 0x9b, 0x09); /* ADI recommended write */ 1916 hdmi_write(sd, 0x9d, 0x02); /* equaliser */ 1917 1918 afe_write(sd, 0x00, 0xff); /* power down ADC */ 1919 afe_write(sd, 0xc8, 0x40); /* phase control */ 1920 1921 /* set to default gain for HDMI */ 1922 cp_write(sd, 0x73, 0x10); 1923 cp_write(sd, 0x74, 0x04); 1924 cp_write(sd, 0x75, 0x01); 1925 cp_write(sd, 0x76, 0x00); 1926 1927 /* reset ADI recommended settings for digitizer */ 1928 /* "ADV7842 Register Settings Recommendations 1929 * (rev. 2.5, June 2010)" p. 17. */ 1930 afe_write(sd, 0x12, 0xfb); /* ADC noise shaping filter controls */ 1931 afe_write(sd, 0x0c, 0x0d); /* CP core gain controls */ 1932 cp_write(sd, 0x3e, 0x00); /* CP core pre-gain control */ 1933 1934 /* CP coast control */ 1935 cp_write(sd, 0xc3, 0x33); /* Component mode */ 1936 1937 /* color space conversion, autodetect color space */ 1938 io_write_and_or(sd, 0x02, 0x0f, 0xf0); 1939 break; 1940 1941 default: 1942 v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n", 1943 __func__, state->mode); 1944 break; 1945 } 1946 } 1947 1948 static int adv7842_s_routing(struct v4l2_subdev *sd, 1949 u32 input, u32 output, u32 config) 1950 { 1951 struct adv7842_state *state = to_state(sd); 1952 1953 v4l2_dbg(2, debug, sd, "%s: input %d\n", __func__, input); 1954 1955 switch (input) { 1956 case ADV7842_SELECT_HDMI_PORT_A: 1957 state->mode = ADV7842_MODE_HDMI; 1958 state->vid_std_select = ADV7842_HDMI_COMP_VID_STD_HD_1250P; 1959 state->hdmi_port_a = true; 1960 break; 1961 case ADV7842_SELECT_HDMI_PORT_B: 1962 state->mode = ADV7842_MODE_HDMI; 1963 state->vid_std_select = ADV7842_HDMI_COMP_VID_STD_HD_1250P; 1964 state->hdmi_port_a = false; 1965 break; 1966 case ADV7842_SELECT_VGA_COMP: 1967 state->mode = ADV7842_MODE_COMP; 1968 state->vid_std_select = ADV7842_RGB_VID_STD_AUTO_GRAPH_MODE; 1969 break; 1970 case ADV7842_SELECT_VGA_RGB: 1971 state->mode = ADV7842_MODE_RGB; 1972 state->vid_std_select = ADV7842_RGB_VID_STD_AUTO_GRAPH_MODE; 1973 break; 1974 case ADV7842_SELECT_SDP_CVBS: 1975 state->mode = ADV7842_MODE_SDP; 1976 state->vid_std_select = ADV7842_SDP_VID_STD_CVBS_SD_4x1; 1977 break; 1978 case ADV7842_SELECT_SDP_YC: 1979 state->mode = ADV7842_MODE_SDP; 1980 state->vid_std_select = ADV7842_SDP_VID_STD_YC_SD4_x1; 1981 break; 1982 default: 1983 return -EINVAL; 1984 } 1985 1986 disable_input(sd); 1987 select_input(sd, state->vid_std_select); 1988 enable_input(sd); 1989 1990 v4l2_subdev_notify_event(sd, &adv7842_ev_fmt); 1991 1992 return 0; 1993 } 1994 1995 static int adv7842_enum_mbus_code(struct v4l2_subdev *sd, 1996 struct v4l2_subdev_pad_config *cfg, 1997 struct v4l2_subdev_mbus_code_enum *code) 1998 { 1999 if (code->index >= ARRAY_SIZE(adv7842_formats)) 2000 return -EINVAL; 2001 code->code = adv7842_formats[code->index].code; 2002 return 0; 2003 } 2004 2005 static void adv7842_fill_format(struct adv7842_state *state, 2006 struct v4l2_mbus_framefmt *format) 2007 { 2008 memset(format, 0, sizeof(*format)); 2009 2010 format->width = state->timings.bt.width; 2011 format->height = state->timings.bt.height; 2012 format->field = V4L2_FIELD_NONE; 2013 format->colorspace = V4L2_COLORSPACE_SRGB; 2014 2015 if (state->timings.bt.flags & V4L2_DV_FL_IS_CE_VIDEO) 2016 format->colorspace = (state->timings.bt.height <= 576) ? 2017 V4L2_COLORSPACE_SMPTE170M : V4L2_COLORSPACE_REC709; 2018 } 2019 2020 /* 2021 * Compute the op_ch_sel value required to obtain on the bus the component order 2022 * corresponding to the selected format taking into account bus reordering 2023 * applied by the board at the output of the device. 2024 * 2025 * The following table gives the op_ch_value from the format component order 2026 * (expressed as op_ch_sel value in column) and the bus reordering (expressed as 2027 * adv7842_bus_order value in row). 2028 * 2029 * | GBR(0) GRB(1) BGR(2) RGB(3) BRG(4) RBG(5) 2030 * ----------+------------------------------------------------- 2031 * RGB (NOP) | GBR GRB BGR RGB BRG RBG 2032 * GRB (1-2) | BGR RGB GBR GRB RBG BRG 2033 * RBG (2-3) | GRB GBR BRG RBG BGR RGB 2034 * BGR (1-3) | RBG BRG RGB BGR GRB GBR 2035 * BRG (ROR) | BRG RBG GRB GBR RGB BGR 2036 * GBR (ROL) | RGB BGR RBG BRG GBR GRB 2037 */ 2038 static unsigned int adv7842_op_ch_sel(struct adv7842_state *state) 2039 { 2040 #define _SEL(a, b, c, d, e, f) { \ 2041 ADV7842_OP_CH_SEL_##a, ADV7842_OP_CH_SEL_##b, ADV7842_OP_CH_SEL_##c, \ 2042 ADV7842_OP_CH_SEL_##d, ADV7842_OP_CH_SEL_##e, ADV7842_OP_CH_SEL_##f } 2043 #define _BUS(x) [ADV7842_BUS_ORDER_##x] 2044 2045 static const unsigned int op_ch_sel[6][6] = { 2046 _BUS(RGB) /* NOP */ = _SEL(GBR, GRB, BGR, RGB, BRG, RBG), 2047 _BUS(GRB) /* 1-2 */ = _SEL(BGR, RGB, GBR, GRB, RBG, BRG), 2048 _BUS(RBG) /* 2-3 */ = _SEL(GRB, GBR, BRG, RBG, BGR, RGB), 2049 _BUS(BGR) /* 1-3 */ = _SEL(RBG, BRG, RGB, BGR, GRB, GBR), 2050 _BUS(BRG) /* ROR */ = _SEL(BRG, RBG, GRB, GBR, RGB, BGR), 2051 _BUS(GBR) /* ROL */ = _SEL(RGB, BGR, RBG, BRG, GBR, GRB), 2052 }; 2053 2054 return op_ch_sel[state->pdata.bus_order][state->format->op_ch_sel >> 5]; 2055 } 2056 2057 static void adv7842_setup_format(struct adv7842_state *state) 2058 { 2059 struct v4l2_subdev *sd = &state->sd; 2060 2061 io_write_clr_set(sd, 0x02, 0x02, 2062 state->format->rgb_out ? ADV7842_RGB_OUT : 0); 2063 io_write(sd, 0x03, state->format->op_format_sel | 2064 state->pdata.op_format_mode_sel); 2065 io_write_clr_set(sd, 0x04, 0xe0, adv7842_op_ch_sel(state)); 2066 io_write_clr_set(sd, 0x05, 0x01, 2067 state->format->swap_cb_cr ? ADV7842_OP_SWAP_CB_CR : 0); 2068 set_rgb_quantization_range(sd); 2069 } 2070 2071 static int adv7842_get_format(struct v4l2_subdev *sd, 2072 struct v4l2_subdev_pad_config *cfg, 2073 struct v4l2_subdev_format *format) 2074 { 2075 struct adv7842_state *state = to_state(sd); 2076 2077 if (format->pad != ADV7842_PAD_SOURCE) 2078 return -EINVAL; 2079 2080 if (state->mode == ADV7842_MODE_SDP) { 2081 /* SPD block */ 2082 if (!(sdp_read(sd, 0x5a) & 0x01)) 2083 return -EINVAL; 2084 format->format.code = MEDIA_BUS_FMT_YUYV8_2X8; 2085 format->format.width = 720; 2086 /* valid signal */ 2087 if (state->norm & V4L2_STD_525_60) 2088 format->format.height = 480; 2089 else 2090 format->format.height = 576; 2091 format->format.colorspace = V4L2_COLORSPACE_SMPTE170M; 2092 return 0; 2093 } 2094 2095 adv7842_fill_format(state, &format->format); 2096 2097 if (format->which == V4L2_SUBDEV_FORMAT_TRY) { 2098 struct v4l2_mbus_framefmt *fmt; 2099 2100 fmt = v4l2_subdev_get_try_format(sd, cfg, format->pad); 2101 format->format.code = fmt->code; 2102 } else { 2103 format->format.code = state->format->code; 2104 } 2105 2106 return 0; 2107 } 2108 2109 static int adv7842_set_format(struct v4l2_subdev *sd, 2110 struct v4l2_subdev_pad_config *cfg, 2111 struct v4l2_subdev_format *format) 2112 { 2113 struct adv7842_state *state = to_state(sd); 2114 const struct adv7842_format_info *info; 2115 2116 if (format->pad != ADV7842_PAD_SOURCE) 2117 return -EINVAL; 2118 2119 if (state->mode == ADV7842_MODE_SDP) 2120 return adv7842_get_format(sd, cfg, format); 2121 2122 info = adv7842_format_info(state, format->format.code); 2123 if (info == NULL) 2124 info = adv7842_format_info(state, MEDIA_BUS_FMT_YUYV8_2X8); 2125 2126 adv7842_fill_format(state, &format->format); 2127 format->format.code = info->code; 2128 2129 if (format->which == V4L2_SUBDEV_FORMAT_TRY) { 2130 struct v4l2_mbus_framefmt *fmt; 2131 2132 fmt = v4l2_subdev_get_try_format(sd, cfg, format->pad); 2133 fmt->code = format->format.code; 2134 } else { 2135 state->format = info; 2136 adv7842_setup_format(state); 2137 } 2138 2139 return 0; 2140 } 2141 2142 static void adv7842_irq_enable(struct v4l2_subdev *sd, bool enable) 2143 { 2144 if (enable) { 2145 /* Enable SSPD, STDI and CP locked/unlocked interrupts */ 2146 io_write(sd, 0x46, 0x9c); 2147 /* ESDP_50HZ_DET interrupt */ 2148 io_write(sd, 0x5a, 0x10); 2149 /* Enable CABLE_DET_A/B_ST (+5v) interrupt */ 2150 io_write(sd, 0x73, 0x03); 2151 /* Enable V_LOCKED and DE_REGEN_LCK interrupts */ 2152 io_write(sd, 0x78, 0x03); 2153 /* Enable SDP Standard Detection Change and SDP Video Detected */ 2154 io_write(sd, 0xa0, 0x09); 2155 /* Enable HDMI_MODE interrupt */ 2156 io_write(sd, 0x69, 0x08); 2157 } else { 2158 io_write(sd, 0x46, 0x0); 2159 io_write(sd, 0x5a, 0x0); 2160 io_write(sd, 0x73, 0x0); 2161 io_write(sd, 0x78, 0x0); 2162 io_write(sd, 0xa0, 0x0); 2163 io_write(sd, 0x69, 0x0); 2164 } 2165 } 2166 2167 #if IS_ENABLED(CONFIG_VIDEO_ADV7842_CEC) 2168 static void adv7842_cec_tx_raw_status(struct v4l2_subdev *sd, u8 tx_raw_status) 2169 { 2170 struct adv7842_state *state = to_state(sd); 2171 2172 if ((cec_read(sd, 0x11) & 0x01) == 0) { 2173 v4l2_dbg(1, debug, sd, "%s: tx raw: tx disabled\n", __func__); 2174 return; 2175 } 2176 2177 if (tx_raw_status & 0x02) { 2178 v4l2_dbg(1, debug, sd, "%s: tx raw: arbitration lost\n", 2179 __func__); 2180 cec_transmit_done(state->cec_adap, CEC_TX_STATUS_ARB_LOST, 2181 1, 0, 0, 0); 2182 return; 2183 } 2184 if (tx_raw_status & 0x04) { 2185 u8 status; 2186 u8 nack_cnt; 2187 u8 low_drive_cnt; 2188 2189 v4l2_dbg(1, debug, sd, "%s: tx raw: retry failed\n", __func__); 2190 /* 2191 * We set this status bit since this hardware performs 2192 * retransmissions. 2193 */ 2194 status = CEC_TX_STATUS_MAX_RETRIES; 2195 nack_cnt = cec_read(sd, 0x14) & 0xf; 2196 if (nack_cnt) 2197 status |= CEC_TX_STATUS_NACK; 2198 low_drive_cnt = cec_read(sd, 0x14) >> 4; 2199 if (low_drive_cnt) 2200 status |= CEC_TX_STATUS_LOW_DRIVE; 2201 cec_transmit_done(state->cec_adap, status, 2202 0, nack_cnt, low_drive_cnt, 0); 2203 return; 2204 } 2205 if (tx_raw_status & 0x01) { 2206 v4l2_dbg(1, debug, sd, "%s: tx raw: ready ok\n", __func__); 2207 cec_transmit_done(state->cec_adap, CEC_TX_STATUS_OK, 0, 0, 0, 0); 2208 return; 2209 } 2210 } 2211 2212 static void adv7842_cec_isr(struct v4l2_subdev *sd, bool *handled) 2213 { 2214 u8 cec_irq; 2215 2216 /* cec controller */ 2217 cec_irq = io_read(sd, 0x93) & 0x0f; 2218 if (!cec_irq) 2219 return; 2220 2221 v4l2_dbg(1, debug, sd, "%s: cec: irq 0x%x\n", __func__, cec_irq); 2222 adv7842_cec_tx_raw_status(sd, cec_irq); 2223 if (cec_irq & 0x08) { 2224 struct adv7842_state *state = to_state(sd); 2225 struct cec_msg msg; 2226 2227 msg.len = cec_read(sd, 0x25) & 0x1f; 2228 if (msg.len > 16) 2229 msg.len = 16; 2230 2231 if (msg.len) { 2232 u8 i; 2233 2234 for (i = 0; i < msg.len; i++) 2235 msg.msg[i] = cec_read(sd, i + 0x15); 2236 cec_write(sd, 0x26, 0x01); /* re-enable rx */ 2237 cec_received_msg(state->cec_adap, &msg); 2238 } 2239 } 2240 2241 io_write(sd, 0x94, cec_irq); 2242 2243 if (handled) 2244 *handled = true; 2245 } 2246 2247 static int adv7842_cec_adap_enable(struct cec_adapter *adap, bool enable) 2248 { 2249 struct adv7842_state *state = cec_get_drvdata(adap); 2250 struct v4l2_subdev *sd = &state->sd; 2251 2252 if (!state->cec_enabled_adap && enable) { 2253 cec_write_clr_set(sd, 0x2a, 0x01, 0x01); /* power up cec */ 2254 cec_write(sd, 0x2c, 0x01); /* cec soft reset */ 2255 cec_write_clr_set(sd, 0x11, 0x01, 0); /* initially disable tx */ 2256 /* enabled irqs: */ 2257 /* tx: ready */ 2258 /* tx: arbitration lost */ 2259 /* tx: retry timeout */ 2260 /* rx: ready */ 2261 io_write_clr_set(sd, 0x96, 0x0f, 0x0f); 2262 cec_write(sd, 0x26, 0x01); /* enable rx */ 2263 } else if (state->cec_enabled_adap && !enable) { 2264 /* disable cec interrupts */ 2265 io_write_clr_set(sd, 0x96, 0x0f, 0x00); 2266 /* disable address mask 1-3 */ 2267 cec_write_clr_set(sd, 0x27, 0x70, 0x00); 2268 /* power down cec section */ 2269 cec_write_clr_set(sd, 0x2a, 0x01, 0x00); 2270 state->cec_valid_addrs = 0; 2271 } 2272 state->cec_enabled_adap = enable; 2273 return 0; 2274 } 2275 2276 static int adv7842_cec_adap_log_addr(struct cec_adapter *adap, u8 addr) 2277 { 2278 struct adv7842_state *state = cec_get_drvdata(adap); 2279 struct v4l2_subdev *sd = &state->sd; 2280 unsigned int i, free_idx = ADV7842_MAX_ADDRS; 2281 2282 if (!state->cec_enabled_adap) 2283 return addr == CEC_LOG_ADDR_INVALID ? 0 : -EIO; 2284 2285 if (addr == CEC_LOG_ADDR_INVALID) { 2286 cec_write_clr_set(sd, 0x27, 0x70, 0); 2287 state->cec_valid_addrs = 0; 2288 return 0; 2289 } 2290 2291 for (i = 0; i < ADV7842_MAX_ADDRS; i++) { 2292 bool is_valid = state->cec_valid_addrs & (1 << i); 2293 2294 if (free_idx == ADV7842_MAX_ADDRS && !is_valid) 2295 free_idx = i; 2296 if (is_valid && state->cec_addr[i] == addr) 2297 return 0; 2298 } 2299 if (i == ADV7842_MAX_ADDRS) { 2300 i = free_idx; 2301 if (i == ADV7842_MAX_ADDRS) 2302 return -ENXIO; 2303 } 2304 state->cec_addr[i] = addr; 2305 state->cec_valid_addrs |= 1 << i; 2306 2307 switch (i) { 2308 case 0: 2309 /* enable address mask 0 */ 2310 cec_write_clr_set(sd, 0x27, 0x10, 0x10); 2311 /* set address for mask 0 */ 2312 cec_write_clr_set(sd, 0x28, 0x0f, addr); 2313 break; 2314 case 1: 2315 /* enable address mask 1 */ 2316 cec_write_clr_set(sd, 0x27, 0x20, 0x20); 2317 /* set address for mask 1 */ 2318 cec_write_clr_set(sd, 0x28, 0xf0, addr << 4); 2319 break; 2320 case 2: 2321 /* enable address mask 2 */ 2322 cec_write_clr_set(sd, 0x27, 0x40, 0x40); 2323 /* set address for mask 1 */ 2324 cec_write_clr_set(sd, 0x29, 0x0f, addr); 2325 break; 2326 } 2327 return 0; 2328 } 2329 2330 static int adv7842_cec_adap_transmit(struct cec_adapter *adap, u8 attempts, 2331 u32 signal_free_time, struct cec_msg *msg) 2332 { 2333 struct adv7842_state *state = cec_get_drvdata(adap); 2334 struct v4l2_subdev *sd = &state->sd; 2335 u8 len = msg->len; 2336 unsigned int i; 2337 2338 /* 2339 * The number of retries is the number of attempts - 1, but retry 2340 * at least once. It's not clear if a value of 0 is allowed, so 2341 * let's do at least one retry. 2342 */ 2343 cec_write_clr_set(sd, 0x12, 0x70, max(1, attempts - 1) << 4); 2344 2345 if (len > 16) { 2346 v4l2_err(sd, "%s: len exceeded 16 (%d)\n", __func__, len); 2347 return -EINVAL; 2348 } 2349 2350 /* write data */ 2351 for (i = 0; i < len; i++) 2352 cec_write(sd, i, msg->msg[i]); 2353 2354 /* set length (data + header) */ 2355 cec_write(sd, 0x10, len); 2356 /* start transmit, enable tx */ 2357 cec_write(sd, 0x11, 0x01); 2358 return 0; 2359 } 2360 2361 static const struct cec_adap_ops adv7842_cec_adap_ops = { 2362 .adap_enable = adv7842_cec_adap_enable, 2363 .adap_log_addr = adv7842_cec_adap_log_addr, 2364 .adap_transmit = adv7842_cec_adap_transmit, 2365 }; 2366 #endif 2367 2368 static int adv7842_isr(struct v4l2_subdev *sd, u32 status, bool *handled) 2369 { 2370 struct adv7842_state *state = to_state(sd); 2371 u8 fmt_change_cp, fmt_change_digital, fmt_change_sdp; 2372 u8 irq_status[6]; 2373 2374 adv7842_irq_enable(sd, false); 2375 2376 /* read status */ 2377 irq_status[0] = io_read(sd, 0x43); 2378 irq_status[1] = io_read(sd, 0x57); 2379 irq_status[2] = io_read(sd, 0x70); 2380 irq_status[3] = io_read(sd, 0x75); 2381 irq_status[4] = io_read(sd, 0x9d); 2382 irq_status[5] = io_read(sd, 0x66); 2383 2384 /* and clear */ 2385 if (irq_status[0]) 2386 io_write(sd, 0x44, irq_status[0]); 2387 if (irq_status[1]) 2388 io_write(sd, 0x58, irq_status[1]); 2389 if (irq_status[2]) 2390 io_write(sd, 0x71, irq_status[2]); 2391 if (irq_status[3]) 2392 io_write(sd, 0x76, irq_status[3]); 2393 if (irq_status[4]) 2394 io_write(sd, 0x9e, irq_status[4]); 2395 if (irq_status[5]) 2396 io_write(sd, 0x67, irq_status[5]); 2397 2398 adv7842_irq_enable(sd, true); 2399 2400 v4l2_dbg(1, debug, sd, "%s: irq %x, %x, %x, %x, %x, %x\n", __func__, 2401 irq_status[0], irq_status[1], irq_status[2], 2402 irq_status[3], irq_status[4], irq_status[5]); 2403 2404 /* format change CP */ 2405 fmt_change_cp = irq_status[0] & 0x9c; 2406 2407 /* format change SDP */ 2408 if (state->mode == ADV7842_MODE_SDP) 2409 fmt_change_sdp = (irq_status[1] & 0x30) | (irq_status[4] & 0x09); 2410 else 2411 fmt_change_sdp = 0; 2412 2413 /* digital format CP */ 2414 if (is_digital_input(sd)) 2415 fmt_change_digital = irq_status[3] & 0x03; 2416 else 2417 fmt_change_digital = 0; 2418 2419 /* format change */ 2420 if (fmt_change_cp || fmt_change_digital || fmt_change_sdp) { 2421 v4l2_dbg(1, debug, sd, 2422 "%s: fmt_change_cp = 0x%x, fmt_change_digital = 0x%x, fmt_change_sdp = 0x%x\n", 2423 __func__, fmt_change_cp, fmt_change_digital, 2424 fmt_change_sdp); 2425 v4l2_subdev_notify_event(sd, &adv7842_ev_fmt); 2426 if (handled) 2427 *handled = true; 2428 } 2429 2430 /* HDMI/DVI mode */ 2431 if (irq_status[5] & 0x08) { 2432 v4l2_dbg(1, debug, sd, "%s: irq %s mode\n", __func__, 2433 (io_read(sd, 0x65) & 0x08) ? "HDMI" : "DVI"); 2434 set_rgb_quantization_range(sd); 2435 if (handled) 2436 *handled = true; 2437 } 2438 2439 #if IS_ENABLED(CONFIG_VIDEO_ADV7842_CEC) 2440 /* cec */ 2441 adv7842_cec_isr(sd, handled); 2442 #endif 2443 2444 /* tx 5v detect */ 2445 if (irq_status[2] & 0x3) { 2446 v4l2_dbg(1, debug, sd, "%s: irq tx_5v\n", __func__); 2447 adv7842_s_detect_tx_5v_ctrl(sd); 2448 if (handled) 2449 *handled = true; 2450 } 2451 return 0; 2452 } 2453 2454 static int adv7842_get_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid) 2455 { 2456 struct adv7842_state *state = to_state(sd); 2457 u32 blocks = 0; 2458 u8 *data = NULL; 2459 2460 memset(edid->reserved, 0, sizeof(edid->reserved)); 2461 2462 switch (edid->pad) { 2463 case ADV7842_EDID_PORT_A: 2464 case ADV7842_EDID_PORT_B: 2465 if (state->hdmi_edid.present & (0x04 << edid->pad)) { 2466 data = state->hdmi_edid.edid; 2467 blocks = state->hdmi_edid.blocks; 2468 } 2469 break; 2470 case ADV7842_EDID_PORT_VGA: 2471 if (state->vga_edid.present) { 2472 data = state->vga_edid.edid; 2473 blocks = state->vga_edid.blocks; 2474 } 2475 break; 2476 default: 2477 return -EINVAL; 2478 } 2479 2480 if (edid->start_block == 0 && edid->blocks == 0) { 2481 edid->blocks = blocks; 2482 return 0; 2483 } 2484 2485 if (!data) 2486 return -ENODATA; 2487 2488 if (edid->start_block >= blocks) 2489 return -EINVAL; 2490 2491 if (edid->start_block + edid->blocks > blocks) 2492 edid->blocks = blocks - edid->start_block; 2493 2494 memcpy(edid->edid, data + edid->start_block * 128, edid->blocks * 128); 2495 2496 return 0; 2497 } 2498 2499 /* 2500 * If the VGA_EDID_ENABLE bit is set (Repeater Map 0x7f, bit 7), then 2501 * the first two blocks of the EDID are for the HDMI, and the first block 2502 * of segment 1 (i.e. the third block of the EDID) is for VGA. 2503 * So if a VGA EDID is installed, then the maximum size of the HDMI EDID 2504 * is 2 blocks. 2505 */ 2506 static int adv7842_set_edid(struct v4l2_subdev *sd, struct v4l2_edid *e) 2507 { 2508 struct adv7842_state *state = to_state(sd); 2509 unsigned int max_blocks = e->pad == ADV7842_EDID_PORT_VGA ? 1 : 4; 2510 int err = 0; 2511 2512 memset(e->reserved, 0, sizeof(e->reserved)); 2513 2514 if (e->pad > ADV7842_EDID_PORT_VGA) 2515 return -EINVAL; 2516 if (e->start_block != 0) 2517 return -EINVAL; 2518 if (e->pad < ADV7842_EDID_PORT_VGA && state->vga_edid.blocks) 2519 max_blocks = 2; 2520 if (e->pad == ADV7842_EDID_PORT_VGA && state->hdmi_edid.blocks > 2) 2521 return -EBUSY; 2522 if (e->blocks > max_blocks) { 2523 e->blocks = max_blocks; 2524 return -E2BIG; 2525 } 2526 2527 /* todo, per edid */ 2528 if (e->blocks) 2529 state->aspect_ratio = v4l2_calc_aspect_ratio(e->edid[0x15], 2530 e->edid[0x16]); 2531 2532 switch (e->pad) { 2533 case ADV7842_EDID_PORT_VGA: 2534 memset(&state->vga_edid.edid, 0, sizeof(state->vga_edid.edid)); 2535 state->vga_edid.blocks = e->blocks; 2536 state->vga_edid.present = e->blocks ? 0x1 : 0x0; 2537 if (e->blocks) 2538 memcpy(&state->vga_edid.edid, e->edid, 128 * e->blocks); 2539 err = edid_write_vga_segment(sd); 2540 break; 2541 case ADV7842_EDID_PORT_A: 2542 case ADV7842_EDID_PORT_B: 2543 memset(&state->hdmi_edid.edid, 0, sizeof(state->hdmi_edid.edid)); 2544 state->hdmi_edid.blocks = e->blocks; 2545 if (e->blocks) { 2546 state->hdmi_edid.present |= 0x04 << e->pad; 2547 memcpy(&state->hdmi_edid.edid, e->edid, 128 * e->blocks); 2548 } else { 2549 state->hdmi_edid.present &= ~(0x04 << e->pad); 2550 adv7842_s_detect_tx_5v_ctrl(sd); 2551 } 2552 err = edid_write_hdmi_segment(sd, e->pad); 2553 break; 2554 default: 2555 return -EINVAL; 2556 } 2557 if (err < 0) 2558 v4l2_err(sd, "error %d writing edid on port %d\n", err, e->pad); 2559 return err; 2560 } 2561 2562 struct adv7842_cfg_read_infoframe { 2563 const char *desc; 2564 u8 present_mask; 2565 u8 head_addr; 2566 u8 payload_addr; 2567 }; 2568 2569 static void log_infoframe(struct v4l2_subdev *sd, const struct adv7842_cfg_read_infoframe *cri) 2570 { 2571 int i; 2572 u8 buffer[32]; 2573 union hdmi_infoframe frame; 2574 u8 len; 2575 struct i2c_client *client = v4l2_get_subdevdata(sd); 2576 struct device *dev = &client->dev; 2577 2578 if (!(io_read(sd, 0x60) & cri->present_mask)) { 2579 v4l2_info(sd, "%s infoframe not received\n", cri->desc); 2580 return; 2581 } 2582 2583 for (i = 0; i < 3; i++) 2584 buffer[i] = infoframe_read(sd, cri->head_addr + i); 2585 2586 len = buffer[2] + 1; 2587 2588 if (len + 3 > sizeof(buffer)) { 2589 v4l2_err(sd, "%s: invalid %s infoframe length %d\n", __func__, cri->desc, len); 2590 return; 2591 } 2592 2593 for (i = 0; i < len; i++) 2594 buffer[i + 3] = infoframe_read(sd, cri->payload_addr + i); 2595 2596 if (hdmi_infoframe_unpack(&frame, buffer, sizeof(buffer)) < 0) { 2597 v4l2_err(sd, "%s: unpack of %s infoframe failed\n", __func__, cri->desc); 2598 return; 2599 } 2600 2601 hdmi_infoframe_log(KERN_INFO, dev, &frame); 2602 } 2603 2604 static void adv7842_log_infoframes(struct v4l2_subdev *sd) 2605 { 2606 int i; 2607 static const struct adv7842_cfg_read_infoframe cri[] = { 2608 { "AVI", 0x01, 0xe0, 0x00 }, 2609 { "Audio", 0x02, 0xe3, 0x1c }, 2610 { "SDP", 0x04, 0xe6, 0x2a }, 2611 { "Vendor", 0x10, 0xec, 0x54 } 2612 }; 2613 2614 if (!(hdmi_read(sd, 0x05) & 0x80)) { 2615 v4l2_info(sd, "receive DVI-D signal, no infoframes\n"); 2616 return; 2617 } 2618 2619 for (i = 0; i < ARRAY_SIZE(cri); i++) 2620 log_infoframe(sd, &cri[i]); 2621 } 2622 2623 #if 0 2624 /* Let's keep it here for now, as it could be useful for debug */ 2625 static const char * const prim_mode_txt[] = { 2626 "SDP", 2627 "Component", 2628 "Graphics", 2629 "Reserved", 2630 "CVBS & HDMI AUDIO", 2631 "HDMI-Comp", 2632 "HDMI-GR", 2633 "Reserved", 2634 "Reserved", 2635 "Reserved", 2636 "Reserved", 2637 "Reserved", 2638 "Reserved", 2639 "Reserved", 2640 "Reserved", 2641 "Reserved", 2642 }; 2643 #endif 2644 2645 static int adv7842_sdp_log_status(struct v4l2_subdev *sd) 2646 { 2647 /* SDP (Standard definition processor) block */ 2648 u8 sdp_signal_detected = sdp_read(sd, 0x5A) & 0x01; 2649 2650 v4l2_info(sd, "Chip powered %s\n", no_power(sd) ? "off" : "on"); 2651 v4l2_info(sd, "Prim-mode = 0x%x, video std = 0x%x\n", 2652 io_read(sd, 0x01) & 0x0f, io_read(sd, 0x00) & 0x3f); 2653 2654 v4l2_info(sd, "SDP: free run: %s\n", 2655 (sdp_read(sd, 0x56) & 0x01) ? "on" : "off"); 2656 v4l2_info(sd, "SDP: %s\n", sdp_signal_detected ? 2657 "valid SD/PR signal detected" : "invalid/no signal"); 2658 if (sdp_signal_detected) { 2659 static const char * const sdp_std_txt[] = { 2660 "NTSC-M/J", 2661 "1?", 2662 "NTSC-443", 2663 "60HzSECAM", 2664 "PAL-M", 2665 "5?", 2666 "PAL-60", 2667 "7?", "8?", "9?", "a?", "b?", 2668 "PAL-CombN", 2669 "d?", 2670 "PAL-BGHID", 2671 "SECAM" 2672 }; 2673 v4l2_info(sd, "SDP: standard %s\n", 2674 sdp_std_txt[sdp_read(sd, 0x52) & 0x0f]); 2675 v4l2_info(sd, "SDP: %s\n", 2676 (sdp_read(sd, 0x59) & 0x08) ? "50Hz" : "60Hz"); 2677 v4l2_info(sd, "SDP: %s\n", 2678 (sdp_read(sd, 0x57) & 0x08) ? "Interlaced" : "Progressive"); 2679 v4l2_info(sd, "SDP: deinterlacer %s\n", 2680 (sdp_read(sd, 0x12) & 0x08) ? "enabled" : "disabled"); 2681 v4l2_info(sd, "SDP: csc %s mode\n", 2682 (sdp_io_read(sd, 0xe0) & 0x40) ? "auto" : "manual"); 2683 } 2684 return 0; 2685 } 2686 2687 static int adv7842_cp_log_status(struct v4l2_subdev *sd) 2688 { 2689 /* CP block */ 2690 struct adv7842_state *state = to_state(sd); 2691 struct v4l2_dv_timings timings; 2692 u8 reg_io_0x02 = io_read(sd, 0x02); 2693 u8 reg_io_0x21 = io_read(sd, 0x21); 2694 u8 reg_rep_0x77 = rep_read(sd, 0x77); 2695 u8 reg_rep_0x7d = rep_read(sd, 0x7d); 2696 bool audio_pll_locked = hdmi_read(sd, 0x04) & 0x01; 2697 bool audio_sample_packet_detect = hdmi_read(sd, 0x18) & 0x01; 2698 bool audio_mute = io_read(sd, 0x65) & 0x40; 2699 2700 static const char * const csc_coeff_sel_rb[16] = { 2701 "bypassed", "YPbPr601 -> RGB", "reserved", "YPbPr709 -> RGB", 2702 "reserved", "RGB -> YPbPr601", "reserved", "RGB -> YPbPr709", 2703 "reserved", "YPbPr709 -> YPbPr601", "YPbPr601 -> YPbPr709", 2704 "reserved", "reserved", "reserved", "reserved", "manual" 2705 }; 2706 static const char * const input_color_space_txt[16] = { 2707 "RGB limited range (16-235)", "RGB full range (0-255)", 2708 "YCbCr Bt.601 (16-235)", "YCbCr Bt.709 (16-235)", 2709 "xvYCC Bt.601", "xvYCC Bt.709", 2710 "YCbCr Bt.601 (0-255)", "YCbCr Bt.709 (0-255)", 2711 "invalid", "invalid", "invalid", "invalid", "invalid", 2712 "invalid", "invalid", "automatic" 2713 }; 2714 static const char * const rgb_quantization_range_txt[] = { 2715 "Automatic", 2716 "RGB limited range (16-235)", 2717 "RGB full range (0-255)", 2718 }; 2719 static const char * const deep_color_mode_txt[4] = { 2720 "8-bits per channel", 2721 "10-bits per channel", 2722 "12-bits per channel", 2723 "16-bits per channel (not supported)" 2724 }; 2725 2726 v4l2_info(sd, "-----Chip status-----\n"); 2727 v4l2_info(sd, "Chip power: %s\n", no_power(sd) ? "off" : "on"); 2728 v4l2_info(sd, "HDMI/DVI-D port selected: %s\n", 2729 state->hdmi_port_a ? "A" : "B"); 2730 v4l2_info(sd, "EDID A %s, B %s\n", 2731 ((reg_rep_0x7d & 0x04) && (reg_rep_0x77 & 0x04)) ? 2732 "enabled" : "disabled", 2733 ((reg_rep_0x7d & 0x08) && (reg_rep_0x77 & 0x08)) ? 2734 "enabled" : "disabled"); 2735 v4l2_info(sd, "HPD A %s, B %s\n", 2736 reg_io_0x21 & 0x02 ? "enabled" : "disabled", 2737 reg_io_0x21 & 0x01 ? "enabled" : "disabled"); 2738 v4l2_info(sd, "CEC: %s\n", state->cec_enabled_adap ? 2739 "enabled" : "disabled"); 2740 if (state->cec_enabled_adap) { 2741 int i; 2742 2743 for (i = 0; i < ADV7842_MAX_ADDRS; i++) { 2744 bool is_valid = state->cec_valid_addrs & (1 << i); 2745 2746 if (is_valid) 2747 v4l2_info(sd, "CEC Logical Address: 0x%x\n", 2748 state->cec_addr[i]); 2749 } 2750 } 2751 2752 v4l2_info(sd, "-----Signal status-----\n"); 2753 if (state->hdmi_port_a) { 2754 v4l2_info(sd, "Cable detected (+5V power): %s\n", 2755 io_read(sd, 0x6f) & 0x02 ? "true" : "false"); 2756 v4l2_info(sd, "TMDS signal detected: %s\n", 2757 (io_read(sd, 0x6a) & 0x02) ? "true" : "false"); 2758 v4l2_info(sd, "TMDS signal locked: %s\n", 2759 (io_read(sd, 0x6a) & 0x20) ? "true" : "false"); 2760 } else { 2761 v4l2_info(sd, "Cable detected (+5V power):%s\n", 2762 io_read(sd, 0x6f) & 0x01 ? "true" : "false"); 2763 v4l2_info(sd, "TMDS signal detected: %s\n", 2764 (io_read(sd, 0x6a) & 0x01) ? "true" : "false"); 2765 v4l2_info(sd, "TMDS signal locked: %s\n", 2766 (io_read(sd, 0x6a) & 0x10) ? "true" : "false"); 2767 } 2768 v4l2_info(sd, "CP free run: %s\n", 2769 (!!(cp_read(sd, 0xff) & 0x10) ? "on" : "off")); 2770 v4l2_info(sd, "Prim-mode = 0x%x, video std = 0x%x, v_freq = 0x%x\n", 2771 io_read(sd, 0x01) & 0x0f, io_read(sd, 0x00) & 0x3f, 2772 (io_read(sd, 0x01) & 0x70) >> 4); 2773 2774 v4l2_info(sd, "-----Video Timings-----\n"); 2775 if (no_cp_signal(sd)) { 2776 v4l2_info(sd, "STDI: not locked\n"); 2777 } else { 2778 u32 bl = ((cp_read(sd, 0xb1) & 0x3f) << 8) | cp_read(sd, 0xb2); 2779 u32 lcf = ((cp_read(sd, 0xb3) & 0x7) << 8) | cp_read(sd, 0xb4); 2780 u32 lcvs = cp_read(sd, 0xb3) >> 3; 2781 u32 fcl = ((cp_read(sd, 0xb8) & 0x1f) << 8) | cp_read(sd, 0xb9); 2782 char hs_pol = ((cp_read(sd, 0xb5) & 0x10) ? 2783 ((cp_read(sd, 0xb5) & 0x08) ? '+' : '-') : 'x'); 2784 char vs_pol = ((cp_read(sd, 0xb5) & 0x40) ? 2785 ((cp_read(sd, 0xb5) & 0x20) ? '+' : '-') : 'x'); 2786 v4l2_info(sd, 2787 "STDI: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, fcl = %d, %s, %chsync, %cvsync\n", 2788 lcf, bl, lcvs, fcl, 2789 (cp_read(sd, 0xb1) & 0x40) ? 2790 "interlaced" : "progressive", 2791 hs_pol, vs_pol); 2792 } 2793 if (adv7842_query_dv_timings(sd, &timings)) 2794 v4l2_info(sd, "No video detected\n"); 2795 else 2796 v4l2_print_dv_timings(sd->name, "Detected format: ", 2797 &timings, true); 2798 v4l2_print_dv_timings(sd->name, "Configured format: ", 2799 &state->timings, true); 2800 2801 if (no_cp_signal(sd)) 2802 return 0; 2803 2804 v4l2_info(sd, "-----Color space-----\n"); 2805 v4l2_info(sd, "RGB quantization range ctrl: %s\n", 2806 rgb_quantization_range_txt[state->rgb_quantization_range]); 2807 v4l2_info(sd, "Input color space: %s\n", 2808 input_color_space_txt[reg_io_0x02 >> 4]); 2809 v4l2_info(sd, "Output color space: %s %s, alt-gamma %s\n", 2810 (reg_io_0x02 & 0x02) ? "RGB" : "YCbCr", 2811 (((reg_io_0x02 >> 2) & 0x01) ^ (reg_io_0x02 & 0x01)) ? 2812 "(16-235)" : "(0-255)", 2813 (reg_io_0x02 & 0x08) ? "enabled" : "disabled"); 2814 v4l2_info(sd, "Color space conversion: %s\n", 2815 csc_coeff_sel_rb[cp_read(sd, 0xf4) >> 4]); 2816 2817 if (!is_digital_input(sd)) 2818 return 0; 2819 2820 v4l2_info(sd, "-----%s status-----\n", is_hdmi(sd) ? "HDMI" : "DVI-D"); 2821 v4l2_info(sd, "HDCP encrypted content: %s\n", 2822 (hdmi_read(sd, 0x05) & 0x40) ? "true" : "false"); 2823 v4l2_info(sd, "HDCP keys read: %s%s\n", 2824 (hdmi_read(sd, 0x04) & 0x20) ? "yes" : "no", 2825 (hdmi_read(sd, 0x04) & 0x10) ? "ERROR" : ""); 2826 if (!is_hdmi(sd)) 2827 return 0; 2828 2829 v4l2_info(sd, "Audio: pll %s, samples %s, %s\n", 2830 audio_pll_locked ? "locked" : "not locked", 2831 audio_sample_packet_detect ? "detected" : "not detected", 2832 audio_mute ? "muted" : "enabled"); 2833 if (audio_pll_locked && audio_sample_packet_detect) { 2834 v4l2_info(sd, "Audio format: %s\n", 2835 (hdmi_read(sd, 0x07) & 0x40) ? "multi-channel" : "stereo"); 2836 } 2837 v4l2_info(sd, "Audio CTS: %u\n", (hdmi_read(sd, 0x5b) << 12) + 2838 (hdmi_read(sd, 0x5c) << 8) + 2839 (hdmi_read(sd, 0x5d) & 0xf0)); 2840 v4l2_info(sd, "Audio N: %u\n", ((hdmi_read(sd, 0x5d) & 0x0f) << 16) + 2841 (hdmi_read(sd, 0x5e) << 8) + 2842 hdmi_read(sd, 0x5f)); 2843 v4l2_info(sd, "AV Mute: %s\n", 2844 (hdmi_read(sd, 0x04) & 0x40) ? "on" : "off"); 2845 v4l2_info(sd, "Deep color mode: %s\n", 2846 deep_color_mode_txt[hdmi_read(sd, 0x0b) >> 6]); 2847 2848 adv7842_log_infoframes(sd); 2849 2850 return 0; 2851 } 2852 2853 static int adv7842_log_status(struct v4l2_subdev *sd) 2854 { 2855 struct adv7842_state *state = to_state(sd); 2856 2857 if (state->mode == ADV7842_MODE_SDP) 2858 return adv7842_sdp_log_status(sd); 2859 return adv7842_cp_log_status(sd); 2860 } 2861 2862 static int adv7842_querystd(struct v4l2_subdev *sd, v4l2_std_id *std) 2863 { 2864 struct adv7842_state *state = to_state(sd); 2865 2866 v4l2_dbg(1, debug, sd, "%s:\n", __func__); 2867 2868 if (state->mode != ADV7842_MODE_SDP) 2869 return -ENODATA; 2870 2871 if (!(sdp_read(sd, 0x5A) & 0x01)) { 2872 *std = 0; 2873 v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__); 2874 return 0; 2875 } 2876 2877 switch (sdp_read(sd, 0x52) & 0x0f) { 2878 case 0: 2879 /* NTSC-M/J */ 2880 *std &= V4L2_STD_NTSC; 2881 break; 2882 case 2: 2883 /* NTSC-443 */ 2884 *std &= V4L2_STD_NTSC_443; 2885 break; 2886 case 3: 2887 /* 60HzSECAM */ 2888 *std &= V4L2_STD_SECAM; 2889 break; 2890 case 4: 2891 /* PAL-M */ 2892 *std &= V4L2_STD_PAL_M; 2893 break; 2894 case 6: 2895 /* PAL-60 */ 2896 *std &= V4L2_STD_PAL_60; 2897 break; 2898 case 0xc: 2899 /* PAL-CombN */ 2900 *std &= V4L2_STD_PAL_Nc; 2901 break; 2902 case 0xe: 2903 /* PAL-BGHID */ 2904 *std &= V4L2_STD_PAL; 2905 break; 2906 case 0xf: 2907 /* SECAM */ 2908 *std &= V4L2_STD_SECAM; 2909 break; 2910 default: 2911 *std &= V4L2_STD_ALL; 2912 break; 2913 } 2914 return 0; 2915 } 2916 2917 static void adv7842_s_sdp_io(struct v4l2_subdev *sd, struct adv7842_sdp_io_sync_adjustment *s) 2918 { 2919 if (s && s->adjust) { 2920 sdp_io_write(sd, 0x94, (s->hs_beg >> 8) & 0xf); 2921 sdp_io_write(sd, 0x95, s->hs_beg & 0xff); 2922 sdp_io_write(sd, 0x96, (s->hs_width >> 8) & 0xf); 2923 sdp_io_write(sd, 0x97, s->hs_width & 0xff); 2924 sdp_io_write(sd, 0x98, (s->de_beg >> 8) & 0xf); 2925 sdp_io_write(sd, 0x99, s->de_beg & 0xff); 2926 sdp_io_write(sd, 0x9a, (s->de_end >> 8) & 0xf); 2927 sdp_io_write(sd, 0x9b, s->de_end & 0xff); 2928 sdp_io_write(sd, 0xa8, s->vs_beg_o); 2929 sdp_io_write(sd, 0xa9, s->vs_beg_e); 2930 sdp_io_write(sd, 0xaa, s->vs_end_o); 2931 sdp_io_write(sd, 0xab, s->vs_end_e); 2932 sdp_io_write(sd, 0xac, s->de_v_beg_o); 2933 sdp_io_write(sd, 0xad, s->de_v_beg_e); 2934 sdp_io_write(sd, 0xae, s->de_v_end_o); 2935 sdp_io_write(sd, 0xaf, s->de_v_end_e); 2936 } else { 2937 /* set to default */ 2938 sdp_io_write(sd, 0x94, 0x00); 2939 sdp_io_write(sd, 0x95, 0x00); 2940 sdp_io_write(sd, 0x96, 0x00); 2941 sdp_io_write(sd, 0x97, 0x20); 2942 sdp_io_write(sd, 0x98, 0x00); 2943 sdp_io_write(sd, 0x99, 0x00); 2944 sdp_io_write(sd, 0x9a, 0x00); 2945 sdp_io_write(sd, 0x9b, 0x00); 2946 sdp_io_write(sd, 0xa8, 0x04); 2947 sdp_io_write(sd, 0xa9, 0x04); 2948 sdp_io_write(sd, 0xaa, 0x04); 2949 sdp_io_write(sd, 0xab, 0x04); 2950 sdp_io_write(sd, 0xac, 0x04); 2951 sdp_io_write(sd, 0xad, 0x04); 2952 sdp_io_write(sd, 0xae, 0x04); 2953 sdp_io_write(sd, 0xaf, 0x04); 2954 } 2955 } 2956 2957 static int adv7842_s_std(struct v4l2_subdev *sd, v4l2_std_id norm) 2958 { 2959 struct adv7842_state *state = to_state(sd); 2960 struct adv7842_platform_data *pdata = &state->pdata; 2961 2962 v4l2_dbg(1, debug, sd, "%s:\n", __func__); 2963 2964 if (state->mode != ADV7842_MODE_SDP) 2965 return -ENODATA; 2966 2967 if (norm & V4L2_STD_625_50) 2968 adv7842_s_sdp_io(sd, &pdata->sdp_io_sync_625); 2969 else if (norm & V4L2_STD_525_60) 2970 adv7842_s_sdp_io(sd, &pdata->sdp_io_sync_525); 2971 else 2972 adv7842_s_sdp_io(sd, NULL); 2973 2974 if (norm & V4L2_STD_ALL) { 2975 state->norm = norm; 2976 return 0; 2977 } 2978 return -EINVAL; 2979 } 2980 2981 static int adv7842_g_std(struct v4l2_subdev *sd, v4l2_std_id *norm) 2982 { 2983 struct adv7842_state *state = to_state(sd); 2984 2985 v4l2_dbg(1, debug, sd, "%s:\n", __func__); 2986 2987 if (state->mode != ADV7842_MODE_SDP) 2988 return -ENODATA; 2989 2990 *norm = state->norm; 2991 return 0; 2992 } 2993 2994 /* ----------------------------------------------------------------------- */ 2995 2996 static int adv7842_core_init(struct v4l2_subdev *sd) 2997 { 2998 struct adv7842_state *state = to_state(sd); 2999 struct adv7842_platform_data *pdata = &state->pdata; 3000 hdmi_write(sd, 0x48, 3001 (pdata->disable_pwrdnb ? 0x80 : 0) | 3002 (pdata->disable_cable_det_rst ? 0x40 : 0)); 3003 3004 disable_input(sd); 3005 3006 /* 3007 * Disable I2C access to internal EDID ram from HDMI DDC ports 3008 * Disable auto edid enable when leaving powerdown mode 3009 */ 3010 rep_write_and_or(sd, 0x77, 0xd3, 0x20); 3011 3012 /* power */ 3013 io_write(sd, 0x0c, 0x42); /* Power up part and power down VDP */ 3014 io_write(sd, 0x15, 0x80); /* Power up pads */ 3015 3016 /* video format */ 3017 io_write(sd, 0x02, 0xf0 | pdata->alt_gamma << 3); 3018 io_write_and_or(sd, 0x05, 0xf0, pdata->blank_data << 3 | 3019 pdata->insert_av_codes << 2 | 3020 pdata->replicate_av_codes << 1); 3021 adv7842_setup_format(state); 3022 3023 /* HDMI audio */ 3024 hdmi_write_and_or(sd, 0x1a, 0xf1, 0x08); /* Wait 1 s before unmute */ 3025 3026 /* Drive strength */ 3027 io_write_and_or(sd, 0x14, 0xc0, 3028 pdata->dr_str_data << 4 | 3029 pdata->dr_str_clk << 2 | 3030 pdata->dr_str_sync); 3031 3032 /* HDMI free run */ 3033 cp_write_and_or(sd, 0xba, 0xfc, pdata->hdmi_free_run_enable | 3034 (pdata->hdmi_free_run_mode << 1)); 3035 3036 /* SPD free run */ 3037 sdp_write_and_or(sd, 0xdd, 0xf0, pdata->sdp_free_run_force | 3038 (pdata->sdp_free_run_cbar_en << 1) | 3039 (pdata->sdp_free_run_man_col_en << 2) | 3040 (pdata->sdp_free_run_auto << 3)); 3041 3042 /* TODO from platform data */ 3043 cp_write(sd, 0x69, 0x14); /* Enable CP CSC */ 3044 io_write(sd, 0x06, 0xa6); /* positive VS and HS and DE */ 3045 cp_write(sd, 0xf3, 0xdc); /* Low threshold to enter/exit free run mode */ 3046 afe_write(sd, 0xb5, 0x01); /* Setting MCLK to 256Fs */ 3047 3048 afe_write(sd, 0x02, pdata->ain_sel); /* Select analog input muxing mode */ 3049 io_write_and_or(sd, 0x30, ~(1 << 4), pdata->output_bus_lsb_to_msb << 4); 3050 3051 sdp_csc_coeff(sd, &pdata->sdp_csc_coeff); 3052 3053 /* todo, improve settings for sdram */ 3054 if (pdata->sd_ram_size >= 128) { 3055 sdp_write(sd, 0x12, 0x0d); /* Frame TBC,3D comb enabled */ 3056 if (pdata->sd_ram_ddr) { 3057 /* SDP setup for the AD eval board */ 3058 sdp_io_write(sd, 0x6f, 0x00); /* DDR mode */ 3059 sdp_io_write(sd, 0x75, 0x0a); /* 128 MB memory size */ 3060 sdp_io_write(sd, 0x7a, 0xa5); /* Timing Adjustment */ 3061 sdp_io_write(sd, 0x7b, 0x8f); /* Timing Adjustment */ 3062 sdp_io_write(sd, 0x60, 0x01); /* SDRAM reset */ 3063 } else { 3064 sdp_io_write(sd, 0x75, 0x0a); /* 64 MB memory size ?*/ 3065 sdp_io_write(sd, 0x74, 0x00); /* must be zero for sdr sdram */ 3066 sdp_io_write(sd, 0x79, 0x33); /* CAS latency to 3, 3067 depends on memory */ 3068 sdp_io_write(sd, 0x6f, 0x01); /* SDR mode */ 3069 sdp_io_write(sd, 0x7a, 0xa5); /* Timing Adjustment */ 3070 sdp_io_write(sd, 0x7b, 0x8f); /* Timing Adjustment */ 3071 sdp_io_write(sd, 0x60, 0x01); /* SDRAM reset */ 3072 } 3073 } else { 3074 /* 3075 * Manual UG-214, rev 0 is bit confusing on this bit 3076 * but a '1' disables any signal if the Ram is active. 3077 */ 3078 sdp_io_write(sd, 0x29, 0x10); /* Tristate memory interface */ 3079 } 3080 3081 select_input(sd, pdata->vid_std_select); 3082 3083 enable_input(sd); 3084 3085 if (pdata->hpa_auto) { 3086 /* HPA auto, HPA 0.5s after Edid set and Cable detect */ 3087 hdmi_write(sd, 0x69, 0x5c); 3088 } else { 3089 /* HPA manual */ 3090 hdmi_write(sd, 0x69, 0xa3); 3091 /* HPA disable on port A and B */ 3092 io_write_and_or(sd, 0x20, 0xcf, 0x00); 3093 } 3094 3095 /* LLC */ 3096 io_write(sd, 0x19, 0x80 | pdata->llc_dll_phase); 3097 io_write(sd, 0x33, 0x40); 3098 3099 /* interrupts */ 3100 io_write(sd, 0x40, 0xf2); /* Configure INT1 */ 3101 3102 adv7842_irq_enable(sd, true); 3103 3104 return v4l2_ctrl_handler_setup(sd->ctrl_handler); 3105 } 3106 3107 /* ----------------------------------------------------------------------- */ 3108 3109 static int adv7842_ddr_ram_test(struct v4l2_subdev *sd) 3110 { 3111 /* 3112 * From ADV784x external Memory test.pdf 3113 * 3114 * Reset must just been performed before running test. 3115 * Recommended to reset after test. 3116 */ 3117 int i; 3118 int pass = 0; 3119 int fail = 0; 3120 int complete = 0; 3121 3122 io_write(sd, 0x00, 0x01); /* Program SDP 4x1 */ 3123 io_write(sd, 0x01, 0x00); /* Program SDP mode */ 3124 afe_write(sd, 0x80, 0x92); /* SDP Recommended Write */ 3125 afe_write(sd, 0x9B, 0x01); /* SDP Recommended Write ADV7844ES1 */ 3126 afe_write(sd, 0x9C, 0x60); /* SDP Recommended Write ADV7844ES1 */ 3127 afe_write(sd, 0x9E, 0x02); /* SDP Recommended Write ADV7844ES1 */ 3128 afe_write(sd, 0xA0, 0x0B); /* SDP Recommended Write ADV7844ES1 */ 3129 afe_write(sd, 0xC3, 0x02); /* Memory BIST Initialisation */ 3130 io_write(sd, 0x0C, 0x40); /* Power up ADV7844 */ 3131 io_write(sd, 0x15, 0xBA); /* Enable outputs */ 3132 sdp_write(sd, 0x12, 0x00); /* Disable 3D comb, Frame TBC & 3DNR */ 3133 io_write(sd, 0xFF, 0x04); /* Reset memory controller */ 3134 3135 usleep_range(5000, 6000); 3136 3137 sdp_write(sd, 0x12, 0x00); /* Disable 3D Comb, Frame TBC & 3DNR */ 3138 sdp_io_write(sd, 0x2A, 0x01); /* Memory BIST Initialisation */ 3139 sdp_io_write(sd, 0x7c, 0x19); /* Memory BIST Initialisation */ 3140 sdp_io_write(sd, 0x80, 0x87); /* Memory BIST Initialisation */ 3141 sdp_io_write(sd, 0x81, 0x4a); /* Memory BIST Initialisation */ 3142 sdp_io_write(sd, 0x82, 0x2c); /* Memory BIST Initialisation */ 3143 sdp_io_write(sd, 0x83, 0x0e); /* Memory BIST Initialisation */ 3144 sdp_io_write(sd, 0x84, 0x94); /* Memory BIST Initialisation */ 3145 sdp_io_write(sd, 0x85, 0x62); /* Memory BIST Initialisation */ 3146 sdp_io_write(sd, 0x7d, 0x00); /* Memory BIST Initialisation */ 3147 sdp_io_write(sd, 0x7e, 0x1a); /* Memory BIST Initialisation */ 3148 3149 usleep_range(5000, 6000); 3150 3151 sdp_io_write(sd, 0xd9, 0xd5); /* Enable BIST Test */ 3152 sdp_write(sd, 0x12, 0x05); /* Enable FRAME TBC & 3D COMB */ 3153 3154 msleep(20); 3155 3156 for (i = 0; i < 10; i++) { 3157 u8 result = sdp_io_read(sd, 0xdb); 3158 if (result & 0x10) { 3159 complete++; 3160 if (result & 0x20) 3161 fail++; 3162 else 3163 pass++; 3164 } 3165 msleep(20); 3166 } 3167 3168 v4l2_dbg(1, debug, sd, 3169 "Ram Test: completed %d of %d: pass %d, fail %d\n", 3170 complete, i, pass, fail); 3171 3172 if (!complete || fail) 3173 return -EIO; 3174 return 0; 3175 } 3176 3177 static void adv7842_rewrite_i2c_addresses(struct v4l2_subdev *sd, 3178 struct adv7842_platform_data *pdata) 3179 { 3180 io_write(sd, 0xf1, pdata->i2c_sdp << 1); 3181 io_write(sd, 0xf2, pdata->i2c_sdp_io << 1); 3182 io_write(sd, 0xf3, pdata->i2c_avlink << 1); 3183 io_write(sd, 0xf4, pdata->i2c_cec << 1); 3184 io_write(sd, 0xf5, pdata->i2c_infoframe << 1); 3185 3186 io_write(sd, 0xf8, pdata->i2c_afe << 1); 3187 io_write(sd, 0xf9, pdata->i2c_repeater << 1); 3188 io_write(sd, 0xfa, pdata->i2c_edid << 1); 3189 io_write(sd, 0xfb, pdata->i2c_hdmi << 1); 3190 3191 io_write(sd, 0xfd, pdata->i2c_cp << 1); 3192 io_write(sd, 0xfe, pdata->i2c_vdp << 1); 3193 } 3194 3195 static int adv7842_command_ram_test(struct v4l2_subdev *sd) 3196 { 3197 struct i2c_client *client = v4l2_get_subdevdata(sd); 3198 struct adv7842_state *state = to_state(sd); 3199 struct adv7842_platform_data *pdata = client->dev.platform_data; 3200 struct v4l2_dv_timings timings; 3201 int ret = 0; 3202 3203 if (!pdata) 3204 return -ENODEV; 3205 3206 if (!pdata->sd_ram_size || !pdata->sd_ram_ddr) { 3207 v4l2_info(sd, "no sdram or no ddr sdram\n"); 3208 return -EINVAL; 3209 } 3210 3211 main_reset(sd); 3212 3213 adv7842_rewrite_i2c_addresses(sd, pdata); 3214 3215 /* run ram test */ 3216 ret = adv7842_ddr_ram_test(sd); 3217 3218 main_reset(sd); 3219 3220 adv7842_rewrite_i2c_addresses(sd, pdata); 3221 3222 /* and re-init chip and state */ 3223 adv7842_core_init(sd); 3224 3225 disable_input(sd); 3226 3227 select_input(sd, state->vid_std_select); 3228 3229 enable_input(sd); 3230 3231 edid_write_vga_segment(sd); 3232 edid_write_hdmi_segment(sd, ADV7842_EDID_PORT_A); 3233 edid_write_hdmi_segment(sd, ADV7842_EDID_PORT_B); 3234 3235 timings = state->timings; 3236 3237 memset(&state->timings, 0, sizeof(struct v4l2_dv_timings)); 3238 3239 adv7842_s_dv_timings(sd, &timings); 3240 3241 return ret; 3242 } 3243 3244 static long adv7842_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg) 3245 { 3246 switch (cmd) { 3247 case ADV7842_CMD_RAM_TEST: 3248 return adv7842_command_ram_test(sd); 3249 } 3250 return -ENOTTY; 3251 } 3252 3253 static int adv7842_subscribe_event(struct v4l2_subdev *sd, 3254 struct v4l2_fh *fh, 3255 struct v4l2_event_subscription *sub) 3256 { 3257 switch (sub->type) { 3258 case V4L2_EVENT_SOURCE_CHANGE: 3259 return v4l2_src_change_event_subdev_subscribe(sd, fh, sub); 3260 case V4L2_EVENT_CTRL: 3261 return v4l2_ctrl_subdev_subscribe_event(sd, fh, sub); 3262 default: 3263 return -EINVAL; 3264 } 3265 } 3266 3267 static int adv7842_registered(struct v4l2_subdev *sd) 3268 { 3269 struct adv7842_state *state = to_state(sd); 3270 struct i2c_client *client = v4l2_get_subdevdata(sd); 3271 int err; 3272 3273 err = cec_register_adapter(state->cec_adap, &client->dev); 3274 if (err) 3275 cec_delete_adapter(state->cec_adap); 3276 return err; 3277 } 3278 3279 static void adv7842_unregistered(struct v4l2_subdev *sd) 3280 { 3281 struct adv7842_state *state = to_state(sd); 3282 3283 cec_unregister_adapter(state->cec_adap); 3284 } 3285 3286 /* ----------------------------------------------------------------------- */ 3287 3288 static const struct v4l2_ctrl_ops adv7842_ctrl_ops = { 3289 .s_ctrl = adv7842_s_ctrl, 3290 .g_volatile_ctrl = adv7842_g_volatile_ctrl, 3291 }; 3292 3293 static const struct v4l2_subdev_core_ops adv7842_core_ops = { 3294 .log_status = adv7842_log_status, 3295 .ioctl = adv7842_ioctl, 3296 .interrupt_service_routine = adv7842_isr, 3297 .subscribe_event = adv7842_subscribe_event, 3298 .unsubscribe_event = v4l2_event_subdev_unsubscribe, 3299 #ifdef CONFIG_VIDEO_ADV_DEBUG 3300 .g_register = adv7842_g_register, 3301 .s_register = adv7842_s_register, 3302 #endif 3303 }; 3304 3305 static const struct v4l2_subdev_video_ops adv7842_video_ops = { 3306 .g_std = adv7842_g_std, 3307 .s_std = adv7842_s_std, 3308 .s_routing = adv7842_s_routing, 3309 .querystd = adv7842_querystd, 3310 .g_input_status = adv7842_g_input_status, 3311 .s_dv_timings = adv7842_s_dv_timings, 3312 .g_dv_timings = adv7842_g_dv_timings, 3313 .query_dv_timings = adv7842_query_dv_timings, 3314 }; 3315 3316 static const struct v4l2_subdev_pad_ops adv7842_pad_ops = { 3317 .enum_mbus_code = adv7842_enum_mbus_code, 3318 .get_fmt = adv7842_get_format, 3319 .set_fmt = adv7842_set_format, 3320 .get_edid = adv7842_get_edid, 3321 .set_edid = adv7842_set_edid, 3322 .enum_dv_timings = adv7842_enum_dv_timings, 3323 .dv_timings_cap = adv7842_dv_timings_cap, 3324 }; 3325 3326 static const struct v4l2_subdev_ops adv7842_ops = { 3327 .core = &adv7842_core_ops, 3328 .video = &adv7842_video_ops, 3329 .pad = &adv7842_pad_ops, 3330 }; 3331 3332 static const struct v4l2_subdev_internal_ops adv7842_int_ops = { 3333 .registered = adv7842_registered, 3334 .unregistered = adv7842_unregistered, 3335 }; 3336 3337 /* -------------------------- custom ctrls ---------------------------------- */ 3338 3339 static const struct v4l2_ctrl_config adv7842_ctrl_analog_sampling_phase = { 3340 .ops = &adv7842_ctrl_ops, 3341 .id = V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE, 3342 .name = "Analog Sampling Phase", 3343 .type = V4L2_CTRL_TYPE_INTEGER, 3344 .min = 0, 3345 .max = 0x1f, 3346 .step = 1, 3347 .def = 0, 3348 }; 3349 3350 static const struct v4l2_ctrl_config adv7842_ctrl_free_run_color_manual = { 3351 .ops = &adv7842_ctrl_ops, 3352 .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL, 3353 .name = "Free Running Color, Manual", 3354 .type = V4L2_CTRL_TYPE_BOOLEAN, 3355 .max = 1, 3356 .step = 1, 3357 .def = 1, 3358 }; 3359 3360 static const struct v4l2_ctrl_config adv7842_ctrl_free_run_color = { 3361 .ops = &adv7842_ctrl_ops, 3362 .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR, 3363 .name = "Free Running Color", 3364 .type = V4L2_CTRL_TYPE_INTEGER, 3365 .max = 0xffffff, 3366 .step = 0x1, 3367 }; 3368 3369 3370 static void adv7842_unregister_clients(struct v4l2_subdev *sd) 3371 { 3372 struct adv7842_state *state = to_state(sd); 3373 i2c_unregister_device(state->i2c_avlink); 3374 i2c_unregister_device(state->i2c_cec); 3375 i2c_unregister_device(state->i2c_infoframe); 3376 i2c_unregister_device(state->i2c_sdp_io); 3377 i2c_unregister_device(state->i2c_sdp); 3378 i2c_unregister_device(state->i2c_afe); 3379 i2c_unregister_device(state->i2c_repeater); 3380 i2c_unregister_device(state->i2c_edid); 3381 i2c_unregister_device(state->i2c_hdmi); 3382 i2c_unregister_device(state->i2c_cp); 3383 i2c_unregister_device(state->i2c_vdp); 3384 3385 state->i2c_avlink = NULL; 3386 state->i2c_cec = NULL; 3387 state->i2c_infoframe = NULL; 3388 state->i2c_sdp_io = NULL; 3389 state->i2c_sdp = NULL; 3390 state->i2c_afe = NULL; 3391 state->i2c_repeater = NULL; 3392 state->i2c_edid = NULL; 3393 state->i2c_hdmi = NULL; 3394 state->i2c_cp = NULL; 3395 state->i2c_vdp = NULL; 3396 } 3397 3398 static struct i2c_client *adv7842_dummy_client(struct v4l2_subdev *sd, const char *desc, 3399 u8 addr, u8 io_reg) 3400 { 3401 struct i2c_client *client = v4l2_get_subdevdata(sd); 3402 struct i2c_client *cp; 3403 3404 io_write(sd, io_reg, addr << 1); 3405 3406 if (addr == 0) { 3407 v4l2_err(sd, "no %s i2c addr configured\n", desc); 3408 return NULL; 3409 } 3410 3411 cp = i2c_new_dummy_device(client->adapter, io_read(sd, io_reg) >> 1); 3412 if (IS_ERR(cp)) { 3413 v4l2_err(sd, "register %s on i2c addr 0x%x failed with %ld\n", 3414 desc, addr, PTR_ERR(cp)); 3415 cp = NULL; 3416 } 3417 3418 return cp; 3419 } 3420 3421 static int adv7842_register_clients(struct v4l2_subdev *sd) 3422 { 3423 struct adv7842_state *state = to_state(sd); 3424 struct adv7842_platform_data *pdata = &state->pdata; 3425 3426 state->i2c_avlink = adv7842_dummy_client(sd, "avlink", pdata->i2c_avlink, 0xf3); 3427 state->i2c_cec = adv7842_dummy_client(sd, "cec", pdata->i2c_cec, 0xf4); 3428 state->i2c_infoframe = adv7842_dummy_client(sd, "infoframe", pdata->i2c_infoframe, 0xf5); 3429 state->i2c_sdp_io = adv7842_dummy_client(sd, "sdp_io", pdata->i2c_sdp_io, 0xf2); 3430 state->i2c_sdp = adv7842_dummy_client(sd, "sdp", pdata->i2c_sdp, 0xf1); 3431 state->i2c_afe = adv7842_dummy_client(sd, "afe", pdata->i2c_afe, 0xf8); 3432 state->i2c_repeater = adv7842_dummy_client(sd, "repeater", pdata->i2c_repeater, 0xf9); 3433 state->i2c_edid = adv7842_dummy_client(sd, "edid", pdata->i2c_edid, 0xfa); 3434 state->i2c_hdmi = adv7842_dummy_client(sd, "hdmi", pdata->i2c_hdmi, 0xfb); 3435 state->i2c_cp = adv7842_dummy_client(sd, "cp", pdata->i2c_cp, 0xfd); 3436 state->i2c_vdp = adv7842_dummy_client(sd, "vdp", pdata->i2c_vdp, 0xfe); 3437 3438 if (!state->i2c_avlink || 3439 !state->i2c_cec || 3440 !state->i2c_infoframe || 3441 !state->i2c_sdp_io || 3442 !state->i2c_sdp || 3443 !state->i2c_afe || 3444 !state->i2c_repeater || 3445 !state->i2c_edid || 3446 !state->i2c_hdmi || 3447 !state->i2c_cp || 3448 !state->i2c_vdp) 3449 return -1; 3450 3451 return 0; 3452 } 3453 3454 static int adv7842_probe(struct i2c_client *client, 3455 const struct i2c_device_id *id) 3456 { 3457 struct adv7842_state *state; 3458 static const struct v4l2_dv_timings cea640x480 = 3459 V4L2_DV_BT_CEA_640X480P59_94; 3460 struct adv7842_platform_data *pdata = client->dev.platform_data; 3461 struct v4l2_ctrl_handler *hdl; 3462 struct v4l2_ctrl *ctrl; 3463 struct v4l2_subdev *sd; 3464 unsigned int i; 3465 u16 rev; 3466 int err; 3467 3468 /* Check if the adapter supports the needed features */ 3469 if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA)) 3470 return -EIO; 3471 3472 v4l_dbg(1, debug, client, "detecting adv7842 client on address 0x%x\n", 3473 client->addr << 1); 3474 3475 if (!pdata) { 3476 v4l_err(client, "No platform data!\n"); 3477 return -ENODEV; 3478 } 3479 3480 state = devm_kzalloc(&client->dev, sizeof(*state), GFP_KERNEL); 3481 if (!state) 3482 return -ENOMEM; 3483 3484 /* platform data */ 3485 state->pdata = *pdata; 3486 state->timings = cea640x480; 3487 state->format = adv7842_format_info(state, MEDIA_BUS_FMT_YUYV8_2X8); 3488 3489 sd = &state->sd; 3490 v4l2_i2c_subdev_init(sd, client, &adv7842_ops); 3491 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS; 3492 sd->internal_ops = &adv7842_int_ops; 3493 state->mode = pdata->mode; 3494 3495 state->hdmi_port_a = pdata->input == ADV7842_SELECT_HDMI_PORT_A; 3496 state->restart_stdi_once = true; 3497 3498 /* i2c access to adv7842? */ 3499 rev = adv_smbus_read_byte_data_check(client, 0xea, false) << 8 | 3500 adv_smbus_read_byte_data_check(client, 0xeb, false); 3501 if (rev != 0x2012) { 3502 v4l2_info(sd, "got rev=0x%04x on first read attempt\n", rev); 3503 rev = adv_smbus_read_byte_data_check(client, 0xea, false) << 8 | 3504 adv_smbus_read_byte_data_check(client, 0xeb, false); 3505 } 3506 if (rev != 0x2012) { 3507 v4l2_info(sd, "not an adv7842 on address 0x%x (rev=0x%04x)\n", 3508 client->addr << 1, rev); 3509 return -ENODEV; 3510 } 3511 3512 if (pdata->chip_reset) 3513 main_reset(sd); 3514 3515 /* control handlers */ 3516 hdl = &state->hdl; 3517 v4l2_ctrl_handler_init(hdl, 6); 3518 3519 /* add in ascending ID order */ 3520 v4l2_ctrl_new_std(hdl, &adv7842_ctrl_ops, 3521 V4L2_CID_BRIGHTNESS, -128, 127, 1, 0); 3522 v4l2_ctrl_new_std(hdl, &adv7842_ctrl_ops, 3523 V4L2_CID_CONTRAST, 0, 255, 1, 128); 3524 v4l2_ctrl_new_std(hdl, &adv7842_ctrl_ops, 3525 V4L2_CID_SATURATION, 0, 255, 1, 128); 3526 v4l2_ctrl_new_std(hdl, &adv7842_ctrl_ops, 3527 V4L2_CID_HUE, 0, 128, 1, 0); 3528 ctrl = v4l2_ctrl_new_std_menu(hdl, &adv7842_ctrl_ops, 3529 V4L2_CID_DV_RX_IT_CONTENT_TYPE, V4L2_DV_IT_CONTENT_TYPE_NO_ITC, 3530 0, V4L2_DV_IT_CONTENT_TYPE_NO_ITC); 3531 if (ctrl) 3532 ctrl->flags |= V4L2_CTRL_FLAG_VOLATILE; 3533 3534 /* custom controls */ 3535 state->detect_tx_5v_ctrl = v4l2_ctrl_new_std(hdl, NULL, 3536 V4L2_CID_DV_RX_POWER_PRESENT, 0, 3, 0, 0); 3537 state->analog_sampling_phase_ctrl = v4l2_ctrl_new_custom(hdl, 3538 &adv7842_ctrl_analog_sampling_phase, NULL); 3539 state->free_run_color_ctrl_manual = v4l2_ctrl_new_custom(hdl, 3540 &adv7842_ctrl_free_run_color_manual, NULL); 3541 state->free_run_color_ctrl = v4l2_ctrl_new_custom(hdl, 3542 &adv7842_ctrl_free_run_color, NULL); 3543 state->rgb_quantization_range_ctrl = 3544 v4l2_ctrl_new_std_menu(hdl, &adv7842_ctrl_ops, 3545 V4L2_CID_DV_RX_RGB_RANGE, V4L2_DV_RGB_RANGE_FULL, 3546 0, V4L2_DV_RGB_RANGE_AUTO); 3547 sd->ctrl_handler = hdl; 3548 if (hdl->error) { 3549 err = hdl->error; 3550 goto err_hdl; 3551 } 3552 if (adv7842_s_detect_tx_5v_ctrl(sd)) { 3553 err = -ENODEV; 3554 goto err_hdl; 3555 } 3556 3557 if (adv7842_register_clients(sd) < 0) { 3558 err = -ENOMEM; 3559 v4l2_err(sd, "failed to create all i2c clients\n"); 3560 goto err_i2c; 3561 } 3562 3563 3564 INIT_DELAYED_WORK(&state->delayed_work_enable_hotplug, 3565 adv7842_delayed_work_enable_hotplug); 3566 3567 sd->entity.function = MEDIA_ENT_F_DV_DECODER; 3568 for (i = 0; i < ADV7842_PAD_SOURCE; ++i) 3569 state->pads[i].flags = MEDIA_PAD_FL_SINK; 3570 state->pads[ADV7842_PAD_SOURCE].flags = MEDIA_PAD_FL_SOURCE; 3571 err = media_entity_pads_init(&sd->entity, ADV7842_PAD_SOURCE + 1, 3572 state->pads); 3573 if (err) 3574 goto err_work_queues; 3575 3576 err = adv7842_core_init(sd); 3577 if (err) 3578 goto err_entity; 3579 3580 #if IS_ENABLED(CONFIG_VIDEO_ADV7842_CEC) 3581 state->cec_adap = cec_allocate_adapter(&adv7842_cec_adap_ops, 3582 state, dev_name(&client->dev), 3583 CEC_CAP_DEFAULTS, ADV7842_MAX_ADDRS); 3584 err = PTR_ERR_OR_ZERO(state->cec_adap); 3585 if (err) 3586 goto err_entity; 3587 #endif 3588 3589 v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name, 3590 client->addr << 1, client->adapter->name); 3591 return 0; 3592 3593 err_entity: 3594 media_entity_cleanup(&sd->entity); 3595 err_work_queues: 3596 cancel_delayed_work(&state->delayed_work_enable_hotplug); 3597 err_i2c: 3598 adv7842_unregister_clients(sd); 3599 err_hdl: 3600 v4l2_ctrl_handler_free(hdl); 3601 return err; 3602 } 3603 3604 /* ----------------------------------------------------------------------- */ 3605 3606 static int adv7842_remove(struct i2c_client *client) 3607 { 3608 struct v4l2_subdev *sd = i2c_get_clientdata(client); 3609 struct adv7842_state *state = to_state(sd); 3610 3611 adv7842_irq_enable(sd, false); 3612 cancel_delayed_work_sync(&state->delayed_work_enable_hotplug); 3613 v4l2_device_unregister_subdev(sd); 3614 media_entity_cleanup(&sd->entity); 3615 adv7842_unregister_clients(sd); 3616 v4l2_ctrl_handler_free(sd->ctrl_handler); 3617 return 0; 3618 } 3619 3620 /* ----------------------------------------------------------------------- */ 3621 3622 static const struct i2c_device_id adv7842_id[] = { 3623 { "adv7842", 0 }, 3624 { } 3625 }; 3626 MODULE_DEVICE_TABLE(i2c, adv7842_id); 3627 3628 /* ----------------------------------------------------------------------- */ 3629 3630 static struct i2c_driver adv7842_driver = { 3631 .driver = { 3632 .name = "adv7842", 3633 }, 3634 .probe = adv7842_probe, 3635 .remove = adv7842_remove, 3636 .id_table = adv7842_id, 3637 }; 3638 3639 module_i2c_driver(adv7842_driver); 3640