1 /* 2 * adv7842 - Analog Devices ADV7842 video decoder driver 3 * 4 * Copyright 2013 Cisco Systems, Inc. and/or its affiliates. All rights reserved. 5 * 6 * This program is free software; you may redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; version 2 of the License. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 11 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 12 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 13 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 14 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 15 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 16 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 17 * SOFTWARE. 18 * 19 */ 20 21 /* 22 * References (c = chapter, p = page): 23 * REF_01 - Analog devices, ADV7842, 24 * Register Settings Recommendations, Rev. 1.9, April 2011 25 * REF_02 - Analog devices, Software User Guide, UG-206, 26 * ADV7842 I2C Register Maps, Rev. 0, November 2010 27 * REF_03 - Analog devices, Hardware User Guide, UG-214, 28 * ADV7842 Fast Switching 2:1 HDMI 1.4 Receiver with 3D-Comb 29 * Decoder and Digitizer , Rev. 0, January 2011 30 */ 31 32 33 #include <linux/kernel.h> 34 #include <linux/module.h> 35 #include <linux/slab.h> 36 #include <linux/i2c.h> 37 #include <linux/delay.h> 38 #include <linux/videodev2.h> 39 #include <linux/workqueue.h> 40 #include <linux/v4l2-dv-timings.h> 41 #include <linux/hdmi.h> 42 #include <media/v4l2-device.h> 43 #include <media/v4l2-ctrls.h> 44 #include <media/v4l2-dv-timings.h> 45 #include <media/adv7842.h> 46 47 static int debug; 48 module_param(debug, int, 0644); 49 MODULE_PARM_DESC(debug, "debug level (0-2)"); 50 51 MODULE_DESCRIPTION("Analog Devices ADV7842 video decoder driver"); 52 MODULE_AUTHOR("Hans Verkuil <hans.verkuil@cisco.com>"); 53 MODULE_AUTHOR("Martin Bugge <marbugge@cisco.com>"); 54 MODULE_LICENSE("GPL"); 55 56 /* ADV7842 system clock frequency */ 57 #define ADV7842_fsc (28636360) 58 59 /* 60 ********************************************************************** 61 * 62 * Arrays with configuration parameters for the ADV7842 63 * 64 ********************************************************************** 65 */ 66 67 struct adv7842_state { 68 struct adv7842_platform_data pdata; 69 struct v4l2_subdev sd; 70 struct media_pad pad; 71 struct v4l2_ctrl_handler hdl; 72 enum adv7842_mode mode; 73 struct v4l2_dv_timings timings; 74 enum adv7842_vid_std_select vid_std_select; 75 v4l2_std_id norm; 76 struct { 77 u8 edid[256]; 78 u32 present; 79 } hdmi_edid; 80 struct { 81 u8 edid[256]; 82 u32 present; 83 } vga_edid; 84 struct v4l2_fract aspect_ratio; 85 u32 rgb_quantization_range; 86 bool is_cea_format; 87 struct workqueue_struct *work_queues; 88 struct delayed_work delayed_work_enable_hotplug; 89 bool restart_stdi_once; 90 bool hdmi_port_a; 91 92 /* i2c clients */ 93 struct i2c_client *i2c_sdp_io; 94 struct i2c_client *i2c_sdp; 95 struct i2c_client *i2c_cp; 96 struct i2c_client *i2c_vdp; 97 struct i2c_client *i2c_afe; 98 struct i2c_client *i2c_hdmi; 99 struct i2c_client *i2c_repeater; 100 struct i2c_client *i2c_edid; 101 struct i2c_client *i2c_infoframe; 102 struct i2c_client *i2c_cec; 103 struct i2c_client *i2c_avlink; 104 105 /* controls */ 106 struct v4l2_ctrl *detect_tx_5v_ctrl; 107 struct v4l2_ctrl *analog_sampling_phase_ctrl; 108 struct v4l2_ctrl *free_run_color_ctrl_manual; 109 struct v4l2_ctrl *free_run_color_ctrl; 110 struct v4l2_ctrl *rgb_quantization_range_ctrl; 111 }; 112 113 /* Unsupported timings. This device cannot support 720p30. */ 114 static const struct v4l2_dv_timings adv7842_timings_exceptions[] = { 115 V4L2_DV_BT_CEA_1280X720P30, 116 { } 117 }; 118 119 static bool adv7842_check_dv_timings(const struct v4l2_dv_timings *t, void *hdl) 120 { 121 int i; 122 123 for (i = 0; adv7842_timings_exceptions[i].bt.width; i++) 124 if (v4l2_match_dv_timings(t, adv7842_timings_exceptions + i, 0)) 125 return false; 126 return true; 127 } 128 129 struct adv7842_video_standards { 130 struct v4l2_dv_timings timings; 131 u8 vid_std; 132 u8 v_freq; 133 }; 134 135 /* sorted by number of lines */ 136 static const struct adv7842_video_standards adv7842_prim_mode_comp[] = { 137 /* { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 }, TODO flickering */ 138 { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 }, 139 { V4L2_DV_BT_CEA_1280X720P50, 0x19, 0x01 }, 140 { V4L2_DV_BT_CEA_1280X720P60, 0x19, 0x00 }, 141 { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 }, 142 { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 }, 143 { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 }, 144 { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 }, 145 { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 }, 146 /* TODO add 1920x1080P60_RB (CVT timing) */ 147 { }, 148 }; 149 150 /* sorted by number of lines */ 151 static const struct adv7842_video_standards adv7842_prim_mode_gr[] = { 152 { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 }, 153 { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 }, 154 { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 }, 155 { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 }, 156 { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 }, 157 { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 }, 158 { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 }, 159 { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 }, 160 { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 }, 161 { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 }, 162 { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 }, 163 { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 }, 164 { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 }, 165 { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 }, 166 { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 }, 167 { V4L2_DV_BT_DMT_1360X768P60, 0x12, 0x00 }, 168 { V4L2_DV_BT_DMT_1366X768P60, 0x13, 0x00 }, 169 { V4L2_DV_BT_DMT_1400X1050P60, 0x14, 0x00 }, 170 { V4L2_DV_BT_DMT_1400X1050P75, 0x15, 0x00 }, 171 { V4L2_DV_BT_DMT_1600X1200P60, 0x16, 0x00 }, /* TODO not tested */ 172 /* TODO add 1600X1200P60_RB (not a DMT timing) */ 173 { V4L2_DV_BT_DMT_1680X1050P60, 0x18, 0x00 }, 174 { V4L2_DV_BT_DMT_1920X1200P60_RB, 0x19, 0x00 }, /* TODO not tested */ 175 { }, 176 }; 177 178 /* sorted by number of lines */ 179 static const struct adv7842_video_standards adv7842_prim_mode_hdmi_comp[] = { 180 { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 }, 181 { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 }, 182 { V4L2_DV_BT_CEA_1280X720P50, 0x13, 0x01 }, 183 { V4L2_DV_BT_CEA_1280X720P60, 0x13, 0x00 }, 184 { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 }, 185 { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 }, 186 { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 }, 187 { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 }, 188 { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 }, 189 { }, 190 }; 191 192 /* sorted by number of lines */ 193 static const struct adv7842_video_standards adv7842_prim_mode_hdmi_gr[] = { 194 { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 }, 195 { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 }, 196 { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 }, 197 { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 }, 198 { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 }, 199 { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 }, 200 { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 }, 201 { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 }, 202 { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 }, 203 { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 }, 204 { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 }, 205 { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 }, 206 { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 }, 207 { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 }, 208 { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 }, 209 { }, 210 }; 211 212 /* ----------------------------------------------------------------------- */ 213 214 static inline struct adv7842_state *to_state(struct v4l2_subdev *sd) 215 { 216 return container_of(sd, struct adv7842_state, sd); 217 } 218 219 static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl) 220 { 221 return &container_of(ctrl->handler, struct adv7842_state, hdl)->sd; 222 } 223 224 static inline unsigned htotal(const struct v4l2_bt_timings *t) 225 { 226 return V4L2_DV_BT_FRAME_WIDTH(t); 227 } 228 229 static inline unsigned vtotal(const struct v4l2_bt_timings *t) 230 { 231 return V4L2_DV_BT_FRAME_HEIGHT(t); 232 } 233 234 235 /* ----------------------------------------------------------------------- */ 236 237 static s32 adv_smbus_read_byte_data_check(struct i2c_client *client, 238 u8 command, bool check) 239 { 240 union i2c_smbus_data data; 241 242 if (!i2c_smbus_xfer(client->adapter, client->addr, client->flags, 243 I2C_SMBUS_READ, command, 244 I2C_SMBUS_BYTE_DATA, &data)) 245 return data.byte; 246 if (check) 247 v4l_err(client, "error reading %02x, %02x\n", 248 client->addr, command); 249 return -EIO; 250 } 251 252 static s32 adv_smbus_read_byte_data(struct i2c_client *client, u8 command) 253 { 254 int i; 255 256 for (i = 0; i < 3; i++) { 257 int ret = adv_smbus_read_byte_data_check(client, command, true); 258 259 if (ret >= 0) { 260 if (i) 261 v4l_err(client, "read ok after %d retries\n", i); 262 return ret; 263 } 264 } 265 v4l_err(client, "read failed\n"); 266 return -EIO; 267 } 268 269 static s32 adv_smbus_write_byte_data(struct i2c_client *client, 270 u8 command, u8 value) 271 { 272 union i2c_smbus_data data; 273 int err; 274 int i; 275 276 data.byte = value; 277 for (i = 0; i < 3; i++) { 278 err = i2c_smbus_xfer(client->adapter, client->addr, 279 client->flags, 280 I2C_SMBUS_WRITE, command, 281 I2C_SMBUS_BYTE_DATA, &data); 282 if (!err) 283 break; 284 } 285 if (err < 0) 286 v4l_err(client, "error writing %02x, %02x, %02x\n", 287 client->addr, command, value); 288 return err; 289 } 290 291 static void adv_smbus_write_byte_no_check(struct i2c_client *client, 292 u8 command, u8 value) 293 { 294 union i2c_smbus_data data; 295 data.byte = value; 296 297 i2c_smbus_xfer(client->adapter, client->addr, 298 client->flags, 299 I2C_SMBUS_WRITE, command, 300 I2C_SMBUS_BYTE_DATA, &data); 301 } 302 303 static s32 adv_smbus_write_i2c_block_data(struct i2c_client *client, 304 u8 command, unsigned length, const u8 *values) 305 { 306 union i2c_smbus_data data; 307 308 if (length > I2C_SMBUS_BLOCK_MAX) 309 length = I2C_SMBUS_BLOCK_MAX; 310 data.block[0] = length; 311 memcpy(data.block + 1, values, length); 312 return i2c_smbus_xfer(client->adapter, client->addr, client->flags, 313 I2C_SMBUS_WRITE, command, 314 I2C_SMBUS_I2C_BLOCK_DATA, &data); 315 } 316 317 /* ----------------------------------------------------------------------- */ 318 319 static inline int io_read(struct v4l2_subdev *sd, u8 reg) 320 { 321 struct i2c_client *client = v4l2_get_subdevdata(sd); 322 323 return adv_smbus_read_byte_data(client, reg); 324 } 325 326 static inline int io_write(struct v4l2_subdev *sd, u8 reg, u8 val) 327 { 328 struct i2c_client *client = v4l2_get_subdevdata(sd); 329 330 return adv_smbus_write_byte_data(client, reg, val); 331 } 332 333 static inline int io_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) 334 { 335 return io_write(sd, reg, (io_read(sd, reg) & mask) | val); 336 } 337 338 static inline int avlink_read(struct v4l2_subdev *sd, u8 reg) 339 { 340 struct adv7842_state *state = to_state(sd); 341 342 return adv_smbus_read_byte_data(state->i2c_avlink, reg); 343 } 344 345 static inline int avlink_write(struct v4l2_subdev *sd, u8 reg, u8 val) 346 { 347 struct adv7842_state *state = to_state(sd); 348 349 return adv_smbus_write_byte_data(state->i2c_avlink, reg, val); 350 } 351 352 static inline int cec_read(struct v4l2_subdev *sd, u8 reg) 353 { 354 struct adv7842_state *state = to_state(sd); 355 356 return adv_smbus_read_byte_data(state->i2c_cec, reg); 357 } 358 359 static inline int cec_write(struct v4l2_subdev *sd, u8 reg, u8 val) 360 { 361 struct adv7842_state *state = to_state(sd); 362 363 return adv_smbus_write_byte_data(state->i2c_cec, reg, val); 364 } 365 366 static inline int cec_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) 367 { 368 return cec_write(sd, reg, (cec_read(sd, reg) & mask) | val); 369 } 370 371 static inline int infoframe_read(struct v4l2_subdev *sd, u8 reg) 372 { 373 struct adv7842_state *state = to_state(sd); 374 375 return adv_smbus_read_byte_data(state->i2c_infoframe, reg); 376 } 377 378 static inline int infoframe_write(struct v4l2_subdev *sd, u8 reg, u8 val) 379 { 380 struct adv7842_state *state = to_state(sd); 381 382 return adv_smbus_write_byte_data(state->i2c_infoframe, reg, val); 383 } 384 385 static inline int sdp_io_read(struct v4l2_subdev *sd, u8 reg) 386 { 387 struct adv7842_state *state = to_state(sd); 388 389 return adv_smbus_read_byte_data(state->i2c_sdp_io, reg); 390 } 391 392 static inline int sdp_io_write(struct v4l2_subdev *sd, u8 reg, u8 val) 393 { 394 struct adv7842_state *state = to_state(sd); 395 396 return adv_smbus_write_byte_data(state->i2c_sdp_io, reg, val); 397 } 398 399 static inline int sdp_io_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) 400 { 401 return sdp_io_write(sd, reg, (sdp_io_read(sd, reg) & mask) | val); 402 } 403 404 static inline int sdp_read(struct v4l2_subdev *sd, u8 reg) 405 { 406 struct adv7842_state *state = to_state(sd); 407 408 return adv_smbus_read_byte_data(state->i2c_sdp, reg); 409 } 410 411 static inline int sdp_write(struct v4l2_subdev *sd, u8 reg, u8 val) 412 { 413 struct adv7842_state *state = to_state(sd); 414 415 return adv_smbus_write_byte_data(state->i2c_sdp, reg, val); 416 } 417 418 static inline int sdp_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) 419 { 420 return sdp_write(sd, reg, (sdp_read(sd, reg) & mask) | val); 421 } 422 423 static inline int afe_read(struct v4l2_subdev *sd, u8 reg) 424 { 425 struct adv7842_state *state = to_state(sd); 426 427 return adv_smbus_read_byte_data(state->i2c_afe, reg); 428 } 429 430 static inline int afe_write(struct v4l2_subdev *sd, u8 reg, u8 val) 431 { 432 struct adv7842_state *state = to_state(sd); 433 434 return adv_smbus_write_byte_data(state->i2c_afe, reg, val); 435 } 436 437 static inline int afe_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) 438 { 439 return afe_write(sd, reg, (afe_read(sd, reg) & mask) | val); 440 } 441 442 static inline int rep_read(struct v4l2_subdev *sd, u8 reg) 443 { 444 struct adv7842_state *state = to_state(sd); 445 446 return adv_smbus_read_byte_data(state->i2c_repeater, reg); 447 } 448 449 static inline int rep_write(struct v4l2_subdev *sd, u8 reg, u8 val) 450 { 451 struct adv7842_state *state = to_state(sd); 452 453 return adv_smbus_write_byte_data(state->i2c_repeater, reg, val); 454 } 455 456 static inline int rep_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) 457 { 458 return rep_write(sd, reg, (rep_read(sd, reg) & mask) | val); 459 } 460 461 static inline int edid_read(struct v4l2_subdev *sd, u8 reg) 462 { 463 struct adv7842_state *state = to_state(sd); 464 465 return adv_smbus_read_byte_data(state->i2c_edid, reg); 466 } 467 468 static inline int edid_write(struct v4l2_subdev *sd, u8 reg, u8 val) 469 { 470 struct adv7842_state *state = to_state(sd); 471 472 return adv_smbus_write_byte_data(state->i2c_edid, reg, val); 473 } 474 475 static inline int hdmi_read(struct v4l2_subdev *sd, u8 reg) 476 { 477 struct adv7842_state *state = to_state(sd); 478 479 return adv_smbus_read_byte_data(state->i2c_hdmi, reg); 480 } 481 482 static inline int hdmi_write(struct v4l2_subdev *sd, u8 reg, u8 val) 483 { 484 struct adv7842_state *state = to_state(sd); 485 486 return adv_smbus_write_byte_data(state->i2c_hdmi, reg, val); 487 } 488 489 static inline int hdmi_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) 490 { 491 return hdmi_write(sd, reg, (hdmi_read(sd, reg) & mask) | val); 492 } 493 494 static inline int cp_read(struct v4l2_subdev *sd, u8 reg) 495 { 496 struct adv7842_state *state = to_state(sd); 497 498 return adv_smbus_read_byte_data(state->i2c_cp, reg); 499 } 500 501 static inline int cp_write(struct v4l2_subdev *sd, u8 reg, u8 val) 502 { 503 struct adv7842_state *state = to_state(sd); 504 505 return adv_smbus_write_byte_data(state->i2c_cp, reg, val); 506 } 507 508 static inline int cp_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) 509 { 510 return cp_write(sd, reg, (cp_read(sd, reg) & mask) | val); 511 } 512 513 static inline int vdp_read(struct v4l2_subdev *sd, u8 reg) 514 { 515 struct adv7842_state *state = to_state(sd); 516 517 return adv_smbus_read_byte_data(state->i2c_vdp, reg); 518 } 519 520 static inline int vdp_write(struct v4l2_subdev *sd, u8 reg, u8 val) 521 { 522 struct adv7842_state *state = to_state(sd); 523 524 return adv_smbus_write_byte_data(state->i2c_vdp, reg, val); 525 } 526 527 static void main_reset(struct v4l2_subdev *sd) 528 { 529 struct i2c_client *client = v4l2_get_subdevdata(sd); 530 531 v4l2_dbg(1, debug, sd, "%s:\n", __func__); 532 533 adv_smbus_write_byte_no_check(client, 0xff, 0x80); 534 535 mdelay(5); 536 } 537 538 /* ----------------------------------------------------------------------- */ 539 540 static inline bool is_analog_input(struct v4l2_subdev *sd) 541 { 542 struct adv7842_state *state = to_state(sd); 543 544 return ((state->mode == ADV7842_MODE_RGB) || 545 (state->mode == ADV7842_MODE_COMP)); 546 } 547 548 static inline bool is_digital_input(struct v4l2_subdev *sd) 549 { 550 struct adv7842_state *state = to_state(sd); 551 552 return state->mode == ADV7842_MODE_HDMI; 553 } 554 555 static const struct v4l2_dv_timings_cap adv7842_timings_cap_analog = { 556 .type = V4L2_DV_BT_656_1120, 557 /* keep this initialization for compatibility with GCC < 4.4.6 */ 558 .reserved = { 0 }, 559 V4L2_INIT_BT_TIMINGS(0, 1920, 0, 1200, 25000000, 170000000, 560 V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT | 561 V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT, 562 V4L2_DV_BT_CAP_PROGRESSIVE | V4L2_DV_BT_CAP_REDUCED_BLANKING | 563 V4L2_DV_BT_CAP_CUSTOM) 564 }; 565 566 static const struct v4l2_dv_timings_cap adv7842_timings_cap_digital = { 567 .type = V4L2_DV_BT_656_1120, 568 /* keep this initialization for compatibility with GCC < 4.4.6 */ 569 .reserved = { 0 }, 570 V4L2_INIT_BT_TIMINGS(0, 1920, 0, 1200, 25000000, 225000000, 571 V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT | 572 V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT, 573 V4L2_DV_BT_CAP_PROGRESSIVE | V4L2_DV_BT_CAP_REDUCED_BLANKING | 574 V4L2_DV_BT_CAP_CUSTOM) 575 }; 576 577 static inline const struct v4l2_dv_timings_cap * 578 adv7842_get_dv_timings_cap(struct v4l2_subdev *sd) 579 { 580 return is_digital_input(sd) ? &adv7842_timings_cap_digital : 581 &adv7842_timings_cap_analog; 582 } 583 584 /* ----------------------------------------------------------------------- */ 585 586 static void adv7842_delayed_work_enable_hotplug(struct work_struct *work) 587 { 588 struct delayed_work *dwork = to_delayed_work(work); 589 struct adv7842_state *state = container_of(dwork, 590 struct adv7842_state, delayed_work_enable_hotplug); 591 struct v4l2_subdev *sd = &state->sd; 592 int present = state->hdmi_edid.present; 593 u8 mask = 0; 594 595 v4l2_dbg(2, debug, sd, "%s: enable hotplug on ports: 0x%x\n", 596 __func__, present); 597 598 if (present & (0x04 << ADV7842_EDID_PORT_A)) 599 mask |= 0x20; 600 if (present & (0x04 << ADV7842_EDID_PORT_B)) 601 mask |= 0x10; 602 io_write_and_or(sd, 0x20, 0xcf, mask); 603 } 604 605 static int edid_write_vga_segment(struct v4l2_subdev *sd) 606 { 607 struct i2c_client *client = v4l2_get_subdevdata(sd); 608 struct adv7842_state *state = to_state(sd); 609 const u8 *val = state->vga_edid.edid; 610 int err = 0; 611 int i; 612 613 v4l2_dbg(2, debug, sd, "%s: write EDID on VGA port\n", __func__); 614 615 /* HPA disable on port A and B */ 616 io_write_and_or(sd, 0x20, 0xcf, 0x00); 617 618 /* Disable I2C access to internal EDID ram from VGA DDC port */ 619 rep_write_and_or(sd, 0x7f, 0x7f, 0x00); 620 621 /* edid segment pointer '1' for VGA port */ 622 rep_write_and_or(sd, 0x77, 0xef, 0x10); 623 624 for (i = 0; !err && i < 256; i += I2C_SMBUS_BLOCK_MAX) 625 err = adv_smbus_write_i2c_block_data(state->i2c_edid, i, 626 I2C_SMBUS_BLOCK_MAX, val + i); 627 if (err) 628 return err; 629 630 /* Calculates the checksums and enables I2C access 631 * to internal EDID ram from VGA DDC port. 632 */ 633 rep_write_and_or(sd, 0x7f, 0x7f, 0x80); 634 635 for (i = 0; i < 1000; i++) { 636 if (rep_read(sd, 0x79) & 0x20) 637 break; 638 mdelay(1); 639 } 640 if (i == 1000) { 641 v4l_err(client, "error enabling edid on VGA port\n"); 642 return -EIO; 643 } 644 645 /* enable hotplug after 200 ms */ 646 queue_delayed_work(state->work_queues, 647 &state->delayed_work_enable_hotplug, HZ / 5); 648 649 return 0; 650 } 651 652 static int edid_spa_location(const u8 *edid) 653 { 654 u8 d; 655 656 /* 657 * TODO, improve and update for other CEA extensions 658 * currently only for 1 segment (256 bytes), 659 * i.e. 1 extension block and CEA revision 3. 660 */ 661 if ((edid[0x7e] != 1) || 662 (edid[0x80] != 0x02) || 663 (edid[0x81] != 0x03)) { 664 return -EINVAL; 665 } 666 /* 667 * search Vendor Specific Data Block (tag 3) 668 */ 669 d = edid[0x82] & 0x7f; 670 if (d > 4) { 671 int i = 0x84; 672 int end = 0x80 + d; 673 do { 674 u8 tag = edid[i]>>5; 675 u8 len = edid[i] & 0x1f; 676 677 if ((tag == 3) && (len >= 5)) 678 return i + 4; 679 i += len + 1; 680 } while (i < end); 681 } 682 return -EINVAL; 683 } 684 685 static int edid_write_hdmi_segment(struct v4l2_subdev *sd, u8 port) 686 { 687 struct i2c_client *client = v4l2_get_subdevdata(sd); 688 struct adv7842_state *state = to_state(sd); 689 const u8 *val = state->hdmi_edid.edid; 690 int spa_loc = edid_spa_location(val); 691 int err = 0; 692 int i; 693 694 v4l2_dbg(2, debug, sd, "%s: write EDID on port %c (spa at 0x%x)\n", 695 __func__, (port == ADV7842_EDID_PORT_A) ? 'A' : 'B', spa_loc); 696 697 /* HPA disable on port A and B */ 698 io_write_and_or(sd, 0x20, 0xcf, 0x00); 699 700 /* Disable I2C access to internal EDID ram from HDMI DDC ports */ 701 rep_write_and_or(sd, 0x77, 0xf3, 0x00); 702 703 if (!state->hdmi_edid.present) 704 return 0; 705 706 /* edid segment pointer '0' for HDMI ports */ 707 rep_write_and_or(sd, 0x77, 0xef, 0x00); 708 709 for (i = 0; !err && i < 256; i += I2C_SMBUS_BLOCK_MAX) 710 err = adv_smbus_write_i2c_block_data(state->i2c_edid, i, 711 I2C_SMBUS_BLOCK_MAX, val + i); 712 if (err) 713 return err; 714 715 if (spa_loc < 0) 716 spa_loc = 0xc0; /* Default value [REF_02, p. 199] */ 717 718 if (port == ADV7842_EDID_PORT_A) { 719 rep_write(sd, 0x72, val[spa_loc]); 720 rep_write(sd, 0x73, val[spa_loc + 1]); 721 } else { 722 rep_write(sd, 0x74, val[spa_loc]); 723 rep_write(sd, 0x75, val[spa_loc + 1]); 724 } 725 rep_write(sd, 0x76, spa_loc & 0xff); 726 rep_write_and_or(sd, 0x77, 0xbf, (spa_loc >> 2) & 0x40); 727 728 /* Calculates the checksums and enables I2C access to internal 729 * EDID ram from HDMI DDC ports 730 */ 731 rep_write_and_or(sd, 0x77, 0xf3, state->hdmi_edid.present); 732 733 for (i = 0; i < 1000; i++) { 734 if (rep_read(sd, 0x7d) & state->hdmi_edid.present) 735 break; 736 mdelay(1); 737 } 738 if (i == 1000) { 739 v4l_err(client, "error enabling edid on port %c\n", 740 (port == ADV7842_EDID_PORT_A) ? 'A' : 'B'); 741 return -EIO; 742 } 743 744 /* enable hotplug after 200 ms */ 745 queue_delayed_work(state->work_queues, 746 &state->delayed_work_enable_hotplug, HZ / 5); 747 748 return 0; 749 } 750 751 /* ----------------------------------------------------------------------- */ 752 753 #ifdef CONFIG_VIDEO_ADV_DEBUG 754 static void adv7842_inv_register(struct v4l2_subdev *sd) 755 { 756 v4l2_info(sd, "0x000-0x0ff: IO Map\n"); 757 v4l2_info(sd, "0x100-0x1ff: AVLink Map\n"); 758 v4l2_info(sd, "0x200-0x2ff: CEC Map\n"); 759 v4l2_info(sd, "0x300-0x3ff: InfoFrame Map\n"); 760 v4l2_info(sd, "0x400-0x4ff: SDP_IO Map\n"); 761 v4l2_info(sd, "0x500-0x5ff: SDP Map\n"); 762 v4l2_info(sd, "0x600-0x6ff: AFE Map\n"); 763 v4l2_info(sd, "0x700-0x7ff: Repeater Map\n"); 764 v4l2_info(sd, "0x800-0x8ff: EDID Map\n"); 765 v4l2_info(sd, "0x900-0x9ff: HDMI Map\n"); 766 v4l2_info(sd, "0xa00-0xaff: CP Map\n"); 767 v4l2_info(sd, "0xb00-0xbff: VDP Map\n"); 768 } 769 770 static int adv7842_g_register(struct v4l2_subdev *sd, 771 struct v4l2_dbg_register *reg) 772 { 773 reg->size = 1; 774 switch (reg->reg >> 8) { 775 case 0: 776 reg->val = io_read(sd, reg->reg & 0xff); 777 break; 778 case 1: 779 reg->val = avlink_read(sd, reg->reg & 0xff); 780 break; 781 case 2: 782 reg->val = cec_read(sd, reg->reg & 0xff); 783 break; 784 case 3: 785 reg->val = infoframe_read(sd, reg->reg & 0xff); 786 break; 787 case 4: 788 reg->val = sdp_io_read(sd, reg->reg & 0xff); 789 break; 790 case 5: 791 reg->val = sdp_read(sd, reg->reg & 0xff); 792 break; 793 case 6: 794 reg->val = afe_read(sd, reg->reg & 0xff); 795 break; 796 case 7: 797 reg->val = rep_read(sd, reg->reg & 0xff); 798 break; 799 case 8: 800 reg->val = edid_read(sd, reg->reg & 0xff); 801 break; 802 case 9: 803 reg->val = hdmi_read(sd, reg->reg & 0xff); 804 break; 805 case 0xa: 806 reg->val = cp_read(sd, reg->reg & 0xff); 807 break; 808 case 0xb: 809 reg->val = vdp_read(sd, reg->reg & 0xff); 810 break; 811 default: 812 v4l2_info(sd, "Register %03llx not supported\n", reg->reg); 813 adv7842_inv_register(sd); 814 break; 815 } 816 return 0; 817 } 818 819 static int adv7842_s_register(struct v4l2_subdev *sd, 820 const struct v4l2_dbg_register *reg) 821 { 822 u8 val = reg->val & 0xff; 823 824 switch (reg->reg >> 8) { 825 case 0: 826 io_write(sd, reg->reg & 0xff, val); 827 break; 828 case 1: 829 avlink_write(sd, reg->reg & 0xff, val); 830 break; 831 case 2: 832 cec_write(sd, reg->reg & 0xff, val); 833 break; 834 case 3: 835 infoframe_write(sd, reg->reg & 0xff, val); 836 break; 837 case 4: 838 sdp_io_write(sd, reg->reg & 0xff, val); 839 break; 840 case 5: 841 sdp_write(sd, reg->reg & 0xff, val); 842 break; 843 case 6: 844 afe_write(sd, reg->reg & 0xff, val); 845 break; 846 case 7: 847 rep_write(sd, reg->reg & 0xff, val); 848 break; 849 case 8: 850 edid_write(sd, reg->reg & 0xff, val); 851 break; 852 case 9: 853 hdmi_write(sd, reg->reg & 0xff, val); 854 break; 855 case 0xa: 856 cp_write(sd, reg->reg & 0xff, val); 857 break; 858 case 0xb: 859 vdp_write(sd, reg->reg & 0xff, val); 860 break; 861 default: 862 v4l2_info(sd, "Register %03llx not supported\n", reg->reg); 863 adv7842_inv_register(sd); 864 break; 865 } 866 return 0; 867 } 868 #endif 869 870 static int adv7842_s_detect_tx_5v_ctrl(struct v4l2_subdev *sd) 871 { 872 struct adv7842_state *state = to_state(sd); 873 int prev = v4l2_ctrl_g_ctrl(state->detect_tx_5v_ctrl); 874 u8 reg_io_6f = io_read(sd, 0x6f); 875 int val = 0; 876 877 if (reg_io_6f & 0x02) 878 val |= 1; /* port A */ 879 if (reg_io_6f & 0x01) 880 val |= 2; /* port B */ 881 882 v4l2_dbg(1, debug, sd, "%s: 0x%x -> 0x%x\n", __func__, prev, val); 883 884 if (val != prev) 885 return v4l2_ctrl_s_ctrl(state->detect_tx_5v_ctrl, val); 886 return 0; 887 } 888 889 static int find_and_set_predefined_video_timings(struct v4l2_subdev *sd, 890 u8 prim_mode, 891 const struct adv7842_video_standards *predef_vid_timings, 892 const struct v4l2_dv_timings *timings) 893 { 894 int i; 895 896 for (i = 0; predef_vid_timings[i].timings.bt.width; i++) { 897 if (!v4l2_match_dv_timings(timings, &predef_vid_timings[i].timings, 898 is_digital_input(sd) ? 250000 : 1000000)) 899 continue; 900 /* video std */ 901 io_write(sd, 0x00, predef_vid_timings[i].vid_std); 902 /* v_freq and prim mode */ 903 io_write(sd, 0x01, (predef_vid_timings[i].v_freq << 4) + prim_mode); 904 return 0; 905 } 906 907 return -1; 908 } 909 910 static int configure_predefined_video_timings(struct v4l2_subdev *sd, 911 struct v4l2_dv_timings *timings) 912 { 913 struct adv7842_state *state = to_state(sd); 914 int err; 915 916 v4l2_dbg(1, debug, sd, "%s\n", __func__); 917 918 /* reset to default values */ 919 io_write(sd, 0x16, 0x43); 920 io_write(sd, 0x17, 0x5a); 921 /* disable embedded syncs for auto graphics mode */ 922 cp_write_and_or(sd, 0x81, 0xef, 0x00); 923 cp_write(sd, 0x26, 0x00); 924 cp_write(sd, 0x27, 0x00); 925 cp_write(sd, 0x28, 0x00); 926 cp_write(sd, 0x29, 0x00); 927 cp_write(sd, 0x8f, 0x40); 928 cp_write(sd, 0x90, 0x00); 929 cp_write(sd, 0xa5, 0x00); 930 cp_write(sd, 0xa6, 0x00); 931 cp_write(sd, 0xa7, 0x00); 932 cp_write(sd, 0xab, 0x00); 933 cp_write(sd, 0xac, 0x00); 934 935 switch (state->mode) { 936 case ADV7842_MODE_COMP: 937 case ADV7842_MODE_RGB: 938 err = find_and_set_predefined_video_timings(sd, 939 0x01, adv7842_prim_mode_comp, timings); 940 if (err) 941 err = find_and_set_predefined_video_timings(sd, 942 0x02, adv7842_prim_mode_gr, timings); 943 break; 944 case ADV7842_MODE_HDMI: 945 err = find_and_set_predefined_video_timings(sd, 946 0x05, adv7842_prim_mode_hdmi_comp, timings); 947 if (err) 948 err = find_and_set_predefined_video_timings(sd, 949 0x06, adv7842_prim_mode_hdmi_gr, timings); 950 break; 951 default: 952 v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n", 953 __func__, state->mode); 954 err = -1; 955 break; 956 } 957 958 959 return err; 960 } 961 962 static void configure_custom_video_timings(struct v4l2_subdev *sd, 963 const struct v4l2_bt_timings *bt) 964 { 965 struct adv7842_state *state = to_state(sd); 966 struct i2c_client *client = v4l2_get_subdevdata(sd); 967 u32 width = htotal(bt); 968 u32 height = vtotal(bt); 969 u16 cp_start_sav = bt->hsync + bt->hbackporch - 4; 970 u16 cp_start_eav = width - bt->hfrontporch; 971 u16 cp_start_vbi = height - bt->vfrontporch + 1; 972 u16 cp_end_vbi = bt->vsync + bt->vbackporch + 1; 973 u16 ch1_fr_ll = (((u32)bt->pixelclock / 100) > 0) ? 974 ((width * (ADV7842_fsc / 100)) / ((u32)bt->pixelclock / 100)) : 0; 975 const u8 pll[2] = { 976 0xc0 | ((width >> 8) & 0x1f), 977 width & 0xff 978 }; 979 980 v4l2_dbg(2, debug, sd, "%s\n", __func__); 981 982 switch (state->mode) { 983 case ADV7842_MODE_COMP: 984 case ADV7842_MODE_RGB: 985 /* auto graphics */ 986 io_write(sd, 0x00, 0x07); /* video std */ 987 io_write(sd, 0x01, 0x02); /* prim mode */ 988 /* enable embedded syncs for auto graphics mode */ 989 cp_write_and_or(sd, 0x81, 0xef, 0x10); 990 991 /* Should only be set in auto-graphics mode [REF_02, p. 91-92] */ 992 /* setup PLL_DIV_MAN_EN and PLL_DIV_RATIO */ 993 /* IO-map reg. 0x16 and 0x17 should be written in sequence */ 994 if (adv_smbus_write_i2c_block_data(client, 0x16, 2, pll)) { 995 v4l2_err(sd, "writing to reg 0x16 and 0x17 failed\n"); 996 break; 997 } 998 999 /* active video - horizontal timing */ 1000 cp_write(sd, 0x26, (cp_start_sav >> 8) & 0xf); 1001 cp_write(sd, 0x27, (cp_start_sav & 0xff)); 1002 cp_write(sd, 0x28, (cp_start_eav >> 8) & 0xf); 1003 cp_write(sd, 0x29, (cp_start_eav & 0xff)); 1004 1005 /* active video - vertical timing */ 1006 cp_write(sd, 0xa5, (cp_start_vbi >> 4) & 0xff); 1007 cp_write(sd, 0xa6, ((cp_start_vbi & 0xf) << 4) | 1008 ((cp_end_vbi >> 8) & 0xf)); 1009 cp_write(sd, 0xa7, cp_end_vbi & 0xff); 1010 break; 1011 case ADV7842_MODE_HDMI: 1012 /* set default prim_mode/vid_std for HDMI 1013 according to [REF_03, c. 4.2] */ 1014 io_write(sd, 0x00, 0x02); /* video std */ 1015 io_write(sd, 0x01, 0x06); /* prim mode */ 1016 break; 1017 default: 1018 v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n", 1019 __func__, state->mode); 1020 break; 1021 } 1022 1023 cp_write(sd, 0x8f, (ch1_fr_ll >> 8) & 0x7); 1024 cp_write(sd, 0x90, ch1_fr_ll & 0xff); 1025 cp_write(sd, 0xab, (height >> 4) & 0xff); 1026 cp_write(sd, 0xac, (height & 0x0f) << 4); 1027 } 1028 1029 static void adv7842_set_offset(struct v4l2_subdev *sd, bool auto_offset, u16 offset_a, u16 offset_b, u16 offset_c) 1030 { 1031 struct adv7842_state *state = to_state(sd); 1032 u8 offset_buf[4]; 1033 1034 if (auto_offset) { 1035 offset_a = 0x3ff; 1036 offset_b = 0x3ff; 1037 offset_c = 0x3ff; 1038 } 1039 1040 v4l2_dbg(2, debug, sd, "%s: %s offset: a = 0x%x, b = 0x%x, c = 0x%x\n", 1041 __func__, auto_offset ? "Auto" : "Manual", 1042 offset_a, offset_b, offset_c); 1043 1044 offset_buf[0]= (cp_read(sd, 0x77) & 0xc0) | ((offset_a & 0x3f0) >> 4); 1045 offset_buf[1] = ((offset_a & 0x00f) << 4) | ((offset_b & 0x3c0) >> 6); 1046 offset_buf[2] = ((offset_b & 0x03f) << 2) | ((offset_c & 0x300) >> 8); 1047 offset_buf[3] = offset_c & 0x0ff; 1048 1049 /* Registers must be written in this order with no i2c access in between */ 1050 if (adv_smbus_write_i2c_block_data(state->i2c_cp, 0x77, 4, offset_buf)) 1051 v4l2_err(sd, "%s: i2c error writing to CP reg 0x77, 0x78, 0x79, 0x7a\n", __func__); 1052 } 1053 1054 static void adv7842_set_gain(struct v4l2_subdev *sd, bool auto_gain, u16 gain_a, u16 gain_b, u16 gain_c) 1055 { 1056 struct adv7842_state *state = to_state(sd); 1057 u8 gain_buf[4]; 1058 u8 gain_man = 1; 1059 u8 agc_mode_man = 1; 1060 1061 if (auto_gain) { 1062 gain_man = 0; 1063 agc_mode_man = 0; 1064 gain_a = 0x100; 1065 gain_b = 0x100; 1066 gain_c = 0x100; 1067 } 1068 1069 v4l2_dbg(2, debug, sd, "%s: %s gain: a = 0x%x, b = 0x%x, c = 0x%x\n", 1070 __func__, auto_gain ? "Auto" : "Manual", 1071 gain_a, gain_b, gain_c); 1072 1073 gain_buf[0] = ((gain_man << 7) | (agc_mode_man << 6) | ((gain_a & 0x3f0) >> 4)); 1074 gain_buf[1] = (((gain_a & 0x00f) << 4) | ((gain_b & 0x3c0) >> 6)); 1075 gain_buf[2] = (((gain_b & 0x03f) << 2) | ((gain_c & 0x300) >> 8)); 1076 gain_buf[3] = ((gain_c & 0x0ff)); 1077 1078 /* Registers must be written in this order with no i2c access in between */ 1079 if (adv_smbus_write_i2c_block_data(state->i2c_cp, 0x73, 4, gain_buf)) 1080 v4l2_err(sd, "%s: i2c error writing to CP reg 0x73, 0x74, 0x75, 0x76\n", __func__); 1081 } 1082 1083 static void set_rgb_quantization_range(struct v4l2_subdev *sd) 1084 { 1085 struct adv7842_state *state = to_state(sd); 1086 bool rgb_output = io_read(sd, 0x02) & 0x02; 1087 bool hdmi_signal = hdmi_read(sd, 0x05) & 0x80; 1088 1089 v4l2_dbg(2, debug, sd, "%s: RGB quantization range: %d, RGB out: %d, HDMI: %d\n", 1090 __func__, state->rgb_quantization_range, 1091 rgb_output, hdmi_signal); 1092 1093 adv7842_set_gain(sd, true, 0x0, 0x0, 0x0); 1094 adv7842_set_offset(sd, true, 0x0, 0x0, 0x0); 1095 1096 switch (state->rgb_quantization_range) { 1097 case V4L2_DV_RGB_RANGE_AUTO: 1098 if (state->mode == ADV7842_MODE_RGB) { 1099 /* Receiving analog RGB signal 1100 * Set RGB full range (0-255) */ 1101 io_write_and_or(sd, 0x02, 0x0f, 0x10); 1102 break; 1103 } 1104 1105 if (state->mode == ADV7842_MODE_COMP) { 1106 /* Receiving analog YPbPr signal 1107 * Set automode */ 1108 io_write_and_or(sd, 0x02, 0x0f, 0xf0); 1109 break; 1110 } 1111 1112 if (hdmi_signal) { 1113 /* Receiving HDMI signal 1114 * Set automode */ 1115 io_write_and_or(sd, 0x02, 0x0f, 0xf0); 1116 break; 1117 } 1118 1119 /* Receiving DVI-D signal 1120 * ADV7842 selects RGB limited range regardless of 1121 * input format (CE/IT) in automatic mode */ 1122 if (state->timings.bt.flags & V4L2_DV_FL_IS_CE_VIDEO) { 1123 /* RGB limited range (16-235) */ 1124 io_write_and_or(sd, 0x02, 0x0f, 0x00); 1125 } else { 1126 /* RGB full range (0-255) */ 1127 io_write_and_or(sd, 0x02, 0x0f, 0x10); 1128 1129 if (is_digital_input(sd) && rgb_output) { 1130 adv7842_set_offset(sd, false, 0x40, 0x40, 0x40); 1131 } else { 1132 adv7842_set_gain(sd, false, 0xe0, 0xe0, 0xe0); 1133 adv7842_set_offset(sd, false, 0x70, 0x70, 0x70); 1134 } 1135 } 1136 break; 1137 case V4L2_DV_RGB_RANGE_LIMITED: 1138 if (state->mode == ADV7842_MODE_COMP) { 1139 /* YCrCb limited range (16-235) */ 1140 io_write_and_or(sd, 0x02, 0x0f, 0x20); 1141 break; 1142 } 1143 1144 /* RGB limited range (16-235) */ 1145 io_write_and_or(sd, 0x02, 0x0f, 0x00); 1146 1147 break; 1148 case V4L2_DV_RGB_RANGE_FULL: 1149 if (state->mode == ADV7842_MODE_COMP) { 1150 /* YCrCb full range (0-255) */ 1151 io_write_and_or(sd, 0x02, 0x0f, 0x60); 1152 break; 1153 } 1154 1155 /* RGB full range (0-255) */ 1156 io_write_and_or(sd, 0x02, 0x0f, 0x10); 1157 1158 if (is_analog_input(sd) || hdmi_signal) 1159 break; 1160 1161 /* Adjust gain/offset for DVI-D signals only */ 1162 if (rgb_output) { 1163 adv7842_set_offset(sd, false, 0x40, 0x40, 0x40); 1164 } else { 1165 adv7842_set_gain(sd, false, 0xe0, 0xe0, 0xe0); 1166 adv7842_set_offset(sd, false, 0x70, 0x70, 0x70); 1167 } 1168 break; 1169 } 1170 } 1171 1172 static int adv7842_s_ctrl(struct v4l2_ctrl *ctrl) 1173 { 1174 struct v4l2_subdev *sd = to_sd(ctrl); 1175 struct adv7842_state *state = to_state(sd); 1176 1177 /* TODO SDP ctrls 1178 contrast/brightness/hue/free run is acting a bit strange, 1179 not sure if sdp csc is correct. 1180 */ 1181 switch (ctrl->id) { 1182 /* standard ctrls */ 1183 case V4L2_CID_BRIGHTNESS: 1184 cp_write(sd, 0x3c, ctrl->val); 1185 sdp_write(sd, 0x14, ctrl->val); 1186 /* ignore lsb sdp 0x17[3:2] */ 1187 return 0; 1188 case V4L2_CID_CONTRAST: 1189 cp_write(sd, 0x3a, ctrl->val); 1190 sdp_write(sd, 0x13, ctrl->val); 1191 /* ignore lsb sdp 0x17[1:0] */ 1192 return 0; 1193 case V4L2_CID_SATURATION: 1194 cp_write(sd, 0x3b, ctrl->val); 1195 sdp_write(sd, 0x15, ctrl->val); 1196 /* ignore lsb sdp 0x17[5:4] */ 1197 return 0; 1198 case V4L2_CID_HUE: 1199 cp_write(sd, 0x3d, ctrl->val); 1200 sdp_write(sd, 0x16, ctrl->val); 1201 /* ignore lsb sdp 0x17[7:6] */ 1202 return 0; 1203 /* custom ctrls */ 1204 case V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE: 1205 afe_write(sd, 0xc8, ctrl->val); 1206 return 0; 1207 case V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL: 1208 cp_write_and_or(sd, 0xbf, ~0x04, (ctrl->val << 2)); 1209 sdp_write_and_or(sd, 0xdd, ~0x04, (ctrl->val << 2)); 1210 return 0; 1211 case V4L2_CID_ADV_RX_FREE_RUN_COLOR: { 1212 u8 R = (ctrl->val & 0xff0000) >> 16; 1213 u8 G = (ctrl->val & 0x00ff00) >> 8; 1214 u8 B = (ctrl->val & 0x0000ff); 1215 /* RGB -> YUV, numerical approximation */ 1216 int Y = 66 * R + 129 * G + 25 * B; 1217 int U = -38 * R - 74 * G + 112 * B; 1218 int V = 112 * R - 94 * G - 18 * B; 1219 1220 /* Scale down to 8 bits with rounding */ 1221 Y = (Y + 128) >> 8; 1222 U = (U + 128) >> 8; 1223 V = (V + 128) >> 8; 1224 /* make U,V positive */ 1225 Y += 16; 1226 U += 128; 1227 V += 128; 1228 1229 v4l2_dbg(1, debug, sd, "R %x, G %x, B %x\n", R, G, B); 1230 v4l2_dbg(1, debug, sd, "Y %x, U %x, V %x\n", Y, U, V); 1231 1232 /* CP */ 1233 cp_write(sd, 0xc1, R); 1234 cp_write(sd, 0xc0, G); 1235 cp_write(sd, 0xc2, B); 1236 /* SDP */ 1237 sdp_write(sd, 0xde, Y); 1238 sdp_write(sd, 0xdf, (V & 0xf0) | ((U >> 4) & 0x0f)); 1239 return 0; 1240 } 1241 case V4L2_CID_DV_RX_RGB_RANGE: 1242 state->rgb_quantization_range = ctrl->val; 1243 set_rgb_quantization_range(sd); 1244 return 0; 1245 } 1246 return -EINVAL; 1247 } 1248 1249 static inline bool no_power(struct v4l2_subdev *sd) 1250 { 1251 return io_read(sd, 0x0c) & 0x24; 1252 } 1253 1254 static inline bool no_cp_signal(struct v4l2_subdev *sd) 1255 { 1256 return ((cp_read(sd, 0xb5) & 0xd0) != 0xd0) || !(cp_read(sd, 0xb1) & 0x80); 1257 } 1258 1259 static inline bool is_hdmi(struct v4l2_subdev *sd) 1260 { 1261 return hdmi_read(sd, 0x05) & 0x80; 1262 } 1263 1264 static int adv7842_g_input_status(struct v4l2_subdev *sd, u32 *status) 1265 { 1266 struct adv7842_state *state = to_state(sd); 1267 1268 *status = 0; 1269 1270 if (io_read(sd, 0x0c) & 0x24) 1271 *status |= V4L2_IN_ST_NO_POWER; 1272 1273 if (state->mode == ADV7842_MODE_SDP) { 1274 /* status from SDP block */ 1275 if (!(sdp_read(sd, 0x5A) & 0x01)) 1276 *status |= V4L2_IN_ST_NO_SIGNAL; 1277 1278 v4l2_dbg(1, debug, sd, "%s: SDP status = 0x%x\n", 1279 __func__, *status); 1280 return 0; 1281 } 1282 /* status from CP block */ 1283 if ((cp_read(sd, 0xb5) & 0xd0) != 0xd0 || 1284 !(cp_read(sd, 0xb1) & 0x80)) 1285 /* TODO channel 2 */ 1286 *status |= V4L2_IN_ST_NO_SIGNAL; 1287 1288 if (is_digital_input(sd) && ((io_read(sd, 0x74) & 0x03) != 0x03)) 1289 *status |= V4L2_IN_ST_NO_SIGNAL; 1290 1291 v4l2_dbg(1, debug, sd, "%s: CP status = 0x%x\n", 1292 __func__, *status); 1293 1294 return 0; 1295 } 1296 1297 struct stdi_readback { 1298 u16 bl, lcf, lcvs; 1299 u8 hs_pol, vs_pol; 1300 bool interlaced; 1301 }; 1302 1303 static int stdi2dv_timings(struct v4l2_subdev *sd, 1304 struct stdi_readback *stdi, 1305 struct v4l2_dv_timings *timings) 1306 { 1307 struct adv7842_state *state = to_state(sd); 1308 u32 hfreq = (ADV7842_fsc * 8) / stdi->bl; 1309 u32 pix_clk; 1310 int i; 1311 1312 for (i = 0; v4l2_dv_timings_presets[i].bt.width; i++) { 1313 const struct v4l2_bt_timings *bt = &v4l2_dv_timings_presets[i].bt; 1314 1315 if (!v4l2_valid_dv_timings(&v4l2_dv_timings_presets[i], 1316 adv7842_get_dv_timings_cap(sd), 1317 adv7842_check_dv_timings, NULL)) 1318 continue; 1319 if (vtotal(bt) != stdi->lcf + 1) 1320 continue; 1321 if (bt->vsync != stdi->lcvs) 1322 continue; 1323 1324 pix_clk = hfreq * htotal(bt); 1325 1326 if ((pix_clk < bt->pixelclock + 1000000) && 1327 (pix_clk > bt->pixelclock - 1000000)) { 1328 *timings = v4l2_dv_timings_presets[i]; 1329 return 0; 1330 } 1331 } 1332 1333 if (v4l2_detect_cvt(stdi->lcf + 1, hfreq, stdi->lcvs, 1334 (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) | 1335 (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0), 1336 timings)) 1337 return 0; 1338 if (v4l2_detect_gtf(stdi->lcf + 1, hfreq, stdi->lcvs, 1339 (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) | 1340 (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0), 1341 state->aspect_ratio, timings)) 1342 return 0; 1343 1344 v4l2_dbg(2, debug, sd, 1345 "%s: No format candidate found for lcvs = %d, lcf=%d, bl = %d, %chsync, %cvsync\n", 1346 __func__, stdi->lcvs, stdi->lcf, stdi->bl, 1347 stdi->hs_pol, stdi->vs_pol); 1348 return -1; 1349 } 1350 1351 static int read_stdi(struct v4l2_subdev *sd, struct stdi_readback *stdi) 1352 { 1353 u32 status; 1354 1355 adv7842_g_input_status(sd, &status); 1356 if (status & V4L2_IN_ST_NO_SIGNAL) { 1357 v4l2_dbg(2, debug, sd, "%s: no signal\n", __func__); 1358 return -ENOLINK; 1359 } 1360 1361 stdi->bl = ((cp_read(sd, 0xb1) & 0x3f) << 8) | cp_read(sd, 0xb2); 1362 stdi->lcf = ((cp_read(sd, 0xb3) & 0x7) << 8) | cp_read(sd, 0xb4); 1363 stdi->lcvs = cp_read(sd, 0xb3) >> 3; 1364 1365 if ((cp_read(sd, 0xb5) & 0x80) && ((cp_read(sd, 0xb5) & 0x03) == 0x01)) { 1366 stdi->hs_pol = ((cp_read(sd, 0xb5) & 0x10) ? 1367 ((cp_read(sd, 0xb5) & 0x08) ? '+' : '-') : 'x'); 1368 stdi->vs_pol = ((cp_read(sd, 0xb5) & 0x40) ? 1369 ((cp_read(sd, 0xb5) & 0x20) ? '+' : '-') : 'x'); 1370 } else { 1371 stdi->hs_pol = 'x'; 1372 stdi->vs_pol = 'x'; 1373 } 1374 stdi->interlaced = (cp_read(sd, 0xb1) & 0x40) ? true : false; 1375 1376 if (stdi->lcf < 239 || stdi->bl < 8 || stdi->bl == 0x3fff) { 1377 v4l2_dbg(2, debug, sd, "%s: invalid signal\n", __func__); 1378 return -ENOLINK; 1379 } 1380 1381 v4l2_dbg(2, debug, sd, 1382 "%s: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %chsync, %cvsync, %s\n", 1383 __func__, stdi->lcf, stdi->bl, stdi->lcvs, 1384 stdi->hs_pol, stdi->vs_pol, 1385 stdi->interlaced ? "interlaced" : "progressive"); 1386 1387 return 0; 1388 } 1389 1390 static int adv7842_enum_dv_timings(struct v4l2_subdev *sd, 1391 struct v4l2_enum_dv_timings *timings) 1392 { 1393 if (timings->pad != 0) 1394 return -EINVAL; 1395 1396 return v4l2_enum_dv_timings_cap(timings, 1397 adv7842_get_dv_timings_cap(sd), adv7842_check_dv_timings, NULL); 1398 } 1399 1400 static int adv7842_dv_timings_cap(struct v4l2_subdev *sd, 1401 struct v4l2_dv_timings_cap *cap) 1402 { 1403 if (cap->pad != 0) 1404 return -EINVAL; 1405 1406 *cap = *adv7842_get_dv_timings_cap(sd); 1407 return 0; 1408 } 1409 1410 /* Fill the optional fields .standards and .flags in struct v4l2_dv_timings 1411 if the format is listed in adv7842_timings[] */ 1412 static void adv7842_fill_optional_dv_timings_fields(struct v4l2_subdev *sd, 1413 struct v4l2_dv_timings *timings) 1414 { 1415 v4l2_find_dv_timings_cap(timings, adv7842_get_dv_timings_cap(sd), 1416 is_digital_input(sd) ? 250000 : 1000000, 1417 adv7842_check_dv_timings, NULL); 1418 } 1419 1420 static int adv7842_query_dv_timings(struct v4l2_subdev *sd, 1421 struct v4l2_dv_timings *timings) 1422 { 1423 struct adv7842_state *state = to_state(sd); 1424 struct v4l2_bt_timings *bt = &timings->bt; 1425 struct stdi_readback stdi = { 0 }; 1426 1427 v4l2_dbg(1, debug, sd, "%s:\n", __func__); 1428 1429 memset(timings, 0, sizeof(struct v4l2_dv_timings)); 1430 1431 /* SDP block */ 1432 if (state->mode == ADV7842_MODE_SDP) 1433 return -ENODATA; 1434 1435 /* read STDI */ 1436 if (read_stdi(sd, &stdi)) { 1437 state->restart_stdi_once = true; 1438 v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__); 1439 return -ENOLINK; 1440 } 1441 bt->interlaced = stdi.interlaced ? 1442 V4L2_DV_INTERLACED : V4L2_DV_PROGRESSIVE; 1443 1444 if (is_digital_input(sd)) { 1445 uint32_t freq; 1446 1447 timings->type = V4L2_DV_BT_656_1120; 1448 1449 bt->width = (hdmi_read(sd, 0x07) & 0x0f) * 256 + hdmi_read(sd, 0x08); 1450 bt->height = (hdmi_read(sd, 0x09) & 0x0f) * 256 + hdmi_read(sd, 0x0a); 1451 freq = ((hdmi_read(sd, 0x51) << 1) + (hdmi_read(sd, 0x52) >> 7)) * 1000000; 1452 freq += ((hdmi_read(sd, 0x52) & 0x7f) * 7813); 1453 if (is_hdmi(sd)) { 1454 /* adjust for deep color mode */ 1455 freq = freq * 8 / (((hdmi_read(sd, 0x0b) & 0xc0) >> 6) * 2 + 8); 1456 } 1457 bt->pixelclock = freq; 1458 bt->hfrontporch = (hdmi_read(sd, 0x20) & 0x03) * 256 + 1459 hdmi_read(sd, 0x21); 1460 bt->hsync = (hdmi_read(sd, 0x22) & 0x03) * 256 + 1461 hdmi_read(sd, 0x23); 1462 bt->hbackporch = (hdmi_read(sd, 0x24) & 0x03) * 256 + 1463 hdmi_read(sd, 0x25); 1464 bt->vfrontporch = ((hdmi_read(sd, 0x2a) & 0x1f) * 256 + 1465 hdmi_read(sd, 0x2b)) / 2; 1466 bt->vsync = ((hdmi_read(sd, 0x2e) & 0x1f) * 256 + 1467 hdmi_read(sd, 0x2f)) / 2; 1468 bt->vbackporch = ((hdmi_read(sd, 0x32) & 0x1f) * 256 + 1469 hdmi_read(sd, 0x33)) / 2; 1470 bt->polarities = ((hdmi_read(sd, 0x05) & 0x10) ? V4L2_DV_VSYNC_POS_POL : 0) | 1471 ((hdmi_read(sd, 0x05) & 0x20) ? V4L2_DV_HSYNC_POS_POL : 0); 1472 if (bt->interlaced == V4L2_DV_INTERLACED) { 1473 bt->height += (hdmi_read(sd, 0x0b) & 0x0f) * 256 + 1474 hdmi_read(sd, 0x0c); 1475 bt->il_vfrontporch = ((hdmi_read(sd, 0x2c) & 0x1f) * 256 + 1476 hdmi_read(sd, 0x2d)) / 2; 1477 bt->il_vsync = ((hdmi_read(sd, 0x30) & 0x1f) * 256 + 1478 hdmi_read(sd, 0x31)) / 2; 1479 bt->il_vbackporch = ((hdmi_read(sd, 0x34) & 0x1f) * 256 + 1480 hdmi_read(sd, 0x35)) / 2; 1481 } 1482 adv7842_fill_optional_dv_timings_fields(sd, timings); 1483 } else { 1484 /* find format 1485 * Since LCVS values are inaccurate [REF_03, p. 339-340], 1486 * stdi2dv_timings() is called with lcvs +-1 if the first attempt fails. 1487 */ 1488 if (!stdi2dv_timings(sd, &stdi, timings)) 1489 goto found; 1490 stdi.lcvs += 1; 1491 v4l2_dbg(1, debug, sd, "%s: lcvs + 1 = %d\n", __func__, stdi.lcvs); 1492 if (!stdi2dv_timings(sd, &stdi, timings)) 1493 goto found; 1494 stdi.lcvs -= 2; 1495 v4l2_dbg(1, debug, sd, "%s: lcvs - 1 = %d\n", __func__, stdi.lcvs); 1496 if (stdi2dv_timings(sd, &stdi, timings)) { 1497 /* 1498 * The STDI block may measure wrong values, especially 1499 * for lcvs and lcf. If the driver can not find any 1500 * valid timing, the STDI block is restarted to measure 1501 * the video timings again. The function will return an 1502 * error, but the restart of STDI will generate a new 1503 * STDI interrupt and the format detection process will 1504 * restart. 1505 */ 1506 if (state->restart_stdi_once) { 1507 v4l2_dbg(1, debug, sd, "%s: restart STDI\n", __func__); 1508 /* TODO restart STDI for Sync Channel 2 */ 1509 /* enter one-shot mode */ 1510 cp_write_and_or(sd, 0x86, 0xf9, 0x00); 1511 /* trigger STDI restart */ 1512 cp_write_and_or(sd, 0x86, 0xf9, 0x04); 1513 /* reset to continuous mode */ 1514 cp_write_and_or(sd, 0x86, 0xf9, 0x02); 1515 state->restart_stdi_once = false; 1516 return -ENOLINK; 1517 } 1518 v4l2_dbg(1, debug, sd, "%s: format not supported\n", __func__); 1519 return -ERANGE; 1520 } 1521 state->restart_stdi_once = true; 1522 } 1523 found: 1524 1525 if (debug > 1) 1526 v4l2_print_dv_timings(sd->name, "adv7842_query_dv_timings:", 1527 timings, true); 1528 return 0; 1529 } 1530 1531 static int adv7842_s_dv_timings(struct v4l2_subdev *sd, 1532 struct v4l2_dv_timings *timings) 1533 { 1534 struct adv7842_state *state = to_state(sd); 1535 struct v4l2_bt_timings *bt; 1536 int err; 1537 1538 v4l2_dbg(1, debug, sd, "%s:\n", __func__); 1539 1540 if (state->mode == ADV7842_MODE_SDP) 1541 return -ENODATA; 1542 1543 if (v4l2_match_dv_timings(&state->timings, timings, 0)) { 1544 v4l2_dbg(1, debug, sd, "%s: no change\n", __func__); 1545 return 0; 1546 } 1547 1548 bt = &timings->bt; 1549 1550 if (!v4l2_valid_dv_timings(timings, adv7842_get_dv_timings_cap(sd), 1551 adv7842_check_dv_timings, NULL)) 1552 return -ERANGE; 1553 1554 adv7842_fill_optional_dv_timings_fields(sd, timings); 1555 1556 state->timings = *timings; 1557 1558 cp_write(sd, 0x91, bt->interlaced ? 0x40 : 0x00); 1559 1560 /* Use prim_mode and vid_std when available */ 1561 err = configure_predefined_video_timings(sd, timings); 1562 if (err) { 1563 /* custom settings when the video format 1564 does not have prim_mode/vid_std */ 1565 configure_custom_video_timings(sd, bt); 1566 } 1567 1568 set_rgb_quantization_range(sd); 1569 1570 1571 if (debug > 1) 1572 v4l2_print_dv_timings(sd->name, "adv7842_s_dv_timings: ", 1573 timings, true); 1574 return 0; 1575 } 1576 1577 static int adv7842_g_dv_timings(struct v4l2_subdev *sd, 1578 struct v4l2_dv_timings *timings) 1579 { 1580 struct adv7842_state *state = to_state(sd); 1581 1582 if (state->mode == ADV7842_MODE_SDP) 1583 return -ENODATA; 1584 *timings = state->timings; 1585 return 0; 1586 } 1587 1588 static void enable_input(struct v4l2_subdev *sd) 1589 { 1590 struct adv7842_state *state = to_state(sd); 1591 1592 set_rgb_quantization_range(sd); 1593 switch (state->mode) { 1594 case ADV7842_MODE_SDP: 1595 case ADV7842_MODE_COMP: 1596 case ADV7842_MODE_RGB: 1597 io_write(sd, 0x15, 0xb0); /* Disable Tristate of Pins (no audio) */ 1598 break; 1599 case ADV7842_MODE_HDMI: 1600 hdmi_write(sd, 0x01, 0x00); /* Enable HDMI clock terminators */ 1601 io_write(sd, 0x15, 0xa0); /* Disable Tristate of Pins */ 1602 hdmi_write_and_or(sd, 0x1a, 0xef, 0x00); /* Unmute audio */ 1603 break; 1604 default: 1605 v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n", 1606 __func__, state->mode); 1607 break; 1608 } 1609 } 1610 1611 static void disable_input(struct v4l2_subdev *sd) 1612 { 1613 hdmi_write_and_or(sd, 0x1a, 0xef, 0x10); /* Mute audio [REF_01, c. 2.2.2] */ 1614 msleep(16); /* 512 samples with >= 32 kHz sample rate [REF_03, c. 8.29] */ 1615 io_write(sd, 0x15, 0xbe); /* Tristate all outputs from video core */ 1616 hdmi_write(sd, 0x01, 0x78); /* Disable HDMI clock terminators */ 1617 } 1618 1619 static void sdp_csc_coeff(struct v4l2_subdev *sd, 1620 const struct adv7842_sdp_csc_coeff *c) 1621 { 1622 /* csc auto/manual */ 1623 sdp_io_write_and_or(sd, 0xe0, 0xbf, c->manual ? 0x00 : 0x40); 1624 1625 if (!c->manual) 1626 return; 1627 1628 /* csc scaling */ 1629 sdp_io_write_and_or(sd, 0xe0, 0x7f, c->scaling == 2 ? 0x80 : 0x00); 1630 1631 /* A coeff */ 1632 sdp_io_write_and_or(sd, 0xe0, 0xe0, c->A1 >> 8); 1633 sdp_io_write(sd, 0xe1, c->A1); 1634 sdp_io_write_and_or(sd, 0xe2, 0xe0, c->A2 >> 8); 1635 sdp_io_write(sd, 0xe3, c->A2); 1636 sdp_io_write_and_or(sd, 0xe4, 0xe0, c->A3 >> 8); 1637 sdp_io_write(sd, 0xe5, c->A3); 1638 1639 /* A scale */ 1640 sdp_io_write_and_or(sd, 0xe6, 0x80, c->A4 >> 8); 1641 sdp_io_write(sd, 0xe7, c->A4); 1642 1643 /* B coeff */ 1644 sdp_io_write_and_or(sd, 0xe8, 0xe0, c->B1 >> 8); 1645 sdp_io_write(sd, 0xe9, c->B1); 1646 sdp_io_write_and_or(sd, 0xea, 0xe0, c->B2 >> 8); 1647 sdp_io_write(sd, 0xeb, c->B2); 1648 sdp_io_write_and_or(sd, 0xec, 0xe0, c->B3 >> 8); 1649 sdp_io_write(sd, 0xed, c->B3); 1650 1651 /* B scale */ 1652 sdp_io_write_and_or(sd, 0xee, 0x80, c->B4 >> 8); 1653 sdp_io_write(sd, 0xef, c->B4); 1654 1655 /* C coeff */ 1656 sdp_io_write_and_or(sd, 0xf0, 0xe0, c->C1 >> 8); 1657 sdp_io_write(sd, 0xf1, c->C1); 1658 sdp_io_write_and_or(sd, 0xf2, 0xe0, c->C2 >> 8); 1659 sdp_io_write(sd, 0xf3, c->C2); 1660 sdp_io_write_and_or(sd, 0xf4, 0xe0, c->C3 >> 8); 1661 sdp_io_write(sd, 0xf5, c->C3); 1662 1663 /* C scale */ 1664 sdp_io_write_and_or(sd, 0xf6, 0x80, c->C4 >> 8); 1665 sdp_io_write(sd, 0xf7, c->C4); 1666 } 1667 1668 static void select_input(struct v4l2_subdev *sd, 1669 enum adv7842_vid_std_select vid_std_select) 1670 { 1671 struct adv7842_state *state = to_state(sd); 1672 1673 switch (state->mode) { 1674 case ADV7842_MODE_SDP: 1675 io_write(sd, 0x00, vid_std_select); /* video std: CVBS or YC mode */ 1676 io_write(sd, 0x01, 0); /* prim mode */ 1677 /* enable embedded syncs for auto graphics mode */ 1678 cp_write_and_or(sd, 0x81, 0xef, 0x10); 1679 1680 afe_write(sd, 0x00, 0x00); /* power up ADC */ 1681 afe_write(sd, 0xc8, 0x00); /* phase control */ 1682 1683 io_write(sd, 0xdd, 0x90); /* Manual 2x output clock */ 1684 /* script says register 0xde, which don't exist in manual */ 1685 1686 /* Manual analog input muxing mode, CVBS (6.4)*/ 1687 afe_write_and_or(sd, 0x02, 0x7f, 0x80); 1688 if (vid_std_select == ADV7842_SDP_VID_STD_CVBS_SD_4x1) { 1689 afe_write(sd, 0x03, 0xa0); /* ADC0 to AIN10 (CVBS), ADC1 N/C*/ 1690 afe_write(sd, 0x04, 0x00); /* ADC2 N/C,ADC3 N/C*/ 1691 } else { 1692 afe_write(sd, 0x03, 0xa0); /* ADC0 to AIN10 (CVBS), ADC1 N/C*/ 1693 afe_write(sd, 0x04, 0xc0); /* ADC2 to AIN12, ADC3 N/C*/ 1694 } 1695 afe_write(sd, 0x0c, 0x1f); /* ADI recommend write */ 1696 afe_write(sd, 0x12, 0x63); /* ADI recommend write */ 1697 1698 sdp_io_write(sd, 0xb2, 0x60); /* Disable AV codes */ 1699 sdp_io_write(sd, 0xc8, 0xe3); /* Disable Ancillary data */ 1700 1701 /* SDP recommended settings */ 1702 sdp_write(sd, 0x00, 0x3F); /* Autodetect PAL NTSC (not SECAM) */ 1703 sdp_write(sd, 0x01, 0x00); /* Pedestal Off */ 1704 1705 sdp_write(sd, 0x03, 0xE4); /* Manual VCR Gain Luma 0x40B */ 1706 sdp_write(sd, 0x04, 0x0B); /* Manual Luma setting */ 1707 sdp_write(sd, 0x05, 0xC3); /* Manual Chroma setting 0x3FE */ 1708 sdp_write(sd, 0x06, 0xFE); /* Manual Chroma setting */ 1709 sdp_write(sd, 0x12, 0x0D); /* Frame TBC,I_P, 3D comb enabled */ 1710 sdp_write(sd, 0xA7, 0x00); /* ADI Recommended Write */ 1711 sdp_io_write(sd, 0xB0, 0x00); /* Disable H and v blanking */ 1712 1713 /* deinterlacer enabled and 3D comb */ 1714 sdp_write_and_or(sd, 0x12, 0xf6, 0x09); 1715 1716 break; 1717 1718 case ADV7842_MODE_COMP: 1719 case ADV7842_MODE_RGB: 1720 /* Automatic analog input muxing mode */ 1721 afe_write_and_or(sd, 0x02, 0x7f, 0x00); 1722 /* set mode and select free run resolution */ 1723 io_write(sd, 0x00, vid_std_select); /* video std */ 1724 io_write(sd, 0x01, 0x02); /* prim mode */ 1725 cp_write_and_or(sd, 0x81, 0xef, 0x10); /* enable embedded syncs 1726 for auto graphics mode */ 1727 1728 afe_write(sd, 0x00, 0x00); /* power up ADC */ 1729 afe_write(sd, 0xc8, 0x00); /* phase control */ 1730 if (state->mode == ADV7842_MODE_COMP) { 1731 /* force to YCrCb */ 1732 io_write_and_or(sd, 0x02, 0x0f, 0x60); 1733 } else { 1734 /* force to RGB */ 1735 io_write_and_or(sd, 0x02, 0x0f, 0x10); 1736 } 1737 1738 /* set ADI recommended settings for digitizer */ 1739 /* "ADV7842 Register Settings Recommendations 1740 * (rev. 1.8, November 2010)" p. 9. */ 1741 afe_write(sd, 0x0c, 0x1f); /* ADC Range improvement */ 1742 afe_write(sd, 0x12, 0x63); /* ADC Range improvement */ 1743 1744 /* set to default gain for RGB */ 1745 cp_write(sd, 0x73, 0x10); 1746 cp_write(sd, 0x74, 0x04); 1747 cp_write(sd, 0x75, 0x01); 1748 cp_write(sd, 0x76, 0x00); 1749 1750 cp_write(sd, 0x3e, 0x04); /* CP core pre-gain control */ 1751 cp_write(sd, 0xc3, 0x39); /* CP coast control. Graphics mode */ 1752 cp_write(sd, 0x40, 0x5c); /* CP core pre-gain control. Graphics mode */ 1753 break; 1754 1755 case ADV7842_MODE_HDMI: 1756 /* Automatic analog input muxing mode */ 1757 afe_write_and_or(sd, 0x02, 0x7f, 0x00); 1758 /* set mode and select free run resolution */ 1759 if (state->hdmi_port_a) 1760 hdmi_write(sd, 0x00, 0x02); /* select port A */ 1761 else 1762 hdmi_write(sd, 0x00, 0x03); /* select port B */ 1763 io_write(sd, 0x00, vid_std_select); /* video std */ 1764 io_write(sd, 0x01, 5); /* prim mode */ 1765 cp_write_and_or(sd, 0x81, 0xef, 0x00); /* disable embedded syncs 1766 for auto graphics mode */ 1767 1768 /* set ADI recommended settings for HDMI: */ 1769 /* "ADV7842 Register Settings Recommendations 1770 * (rev. 1.8, November 2010)" p. 3. */ 1771 hdmi_write(sd, 0xc0, 0x00); 1772 hdmi_write(sd, 0x0d, 0x34); /* ADI recommended write */ 1773 hdmi_write(sd, 0x3d, 0x10); /* ADI recommended write */ 1774 hdmi_write(sd, 0x44, 0x85); /* TMDS PLL optimization */ 1775 hdmi_write(sd, 0x46, 0x1f); /* ADI recommended write */ 1776 hdmi_write(sd, 0x57, 0xb6); /* TMDS PLL optimization */ 1777 hdmi_write(sd, 0x58, 0x03); /* TMDS PLL optimization */ 1778 hdmi_write(sd, 0x60, 0x88); /* TMDS PLL optimization */ 1779 hdmi_write(sd, 0x61, 0x88); /* TMDS PLL optimization */ 1780 hdmi_write(sd, 0x6c, 0x18); /* Disable ISRC clearing bit, 1781 Improve robustness */ 1782 hdmi_write(sd, 0x75, 0x10); /* DDC drive strength */ 1783 hdmi_write(sd, 0x85, 0x1f); /* equaliser */ 1784 hdmi_write(sd, 0x87, 0x70); /* ADI recommended write */ 1785 hdmi_write(sd, 0x89, 0x04); /* equaliser */ 1786 hdmi_write(sd, 0x8a, 0x1e); /* equaliser */ 1787 hdmi_write(sd, 0x93, 0x04); /* equaliser */ 1788 hdmi_write(sd, 0x94, 0x1e); /* equaliser */ 1789 hdmi_write(sd, 0x99, 0xa1); /* ADI recommended write */ 1790 hdmi_write(sd, 0x9b, 0x09); /* ADI recommended write */ 1791 hdmi_write(sd, 0x9d, 0x02); /* equaliser */ 1792 1793 afe_write(sd, 0x00, 0xff); /* power down ADC */ 1794 afe_write(sd, 0xc8, 0x40); /* phase control */ 1795 1796 /* set to default gain for HDMI */ 1797 cp_write(sd, 0x73, 0x10); 1798 cp_write(sd, 0x74, 0x04); 1799 cp_write(sd, 0x75, 0x01); 1800 cp_write(sd, 0x76, 0x00); 1801 1802 /* reset ADI recommended settings for digitizer */ 1803 /* "ADV7842 Register Settings Recommendations 1804 * (rev. 2.5, June 2010)" p. 17. */ 1805 afe_write(sd, 0x12, 0xfb); /* ADC noise shaping filter controls */ 1806 afe_write(sd, 0x0c, 0x0d); /* CP core gain controls */ 1807 cp_write(sd, 0x3e, 0x00); /* CP core pre-gain control */ 1808 1809 /* CP coast control */ 1810 cp_write(sd, 0xc3, 0x33); /* Component mode */ 1811 1812 /* color space conversion, autodetect color space */ 1813 io_write_and_or(sd, 0x02, 0x0f, 0xf0); 1814 break; 1815 1816 default: 1817 v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n", 1818 __func__, state->mode); 1819 break; 1820 } 1821 } 1822 1823 static int adv7842_s_routing(struct v4l2_subdev *sd, 1824 u32 input, u32 output, u32 config) 1825 { 1826 struct adv7842_state *state = to_state(sd); 1827 1828 v4l2_dbg(2, debug, sd, "%s: input %d\n", __func__, input); 1829 1830 switch (input) { 1831 case ADV7842_SELECT_HDMI_PORT_A: 1832 state->mode = ADV7842_MODE_HDMI; 1833 state->vid_std_select = ADV7842_HDMI_COMP_VID_STD_HD_1250P; 1834 state->hdmi_port_a = true; 1835 break; 1836 case ADV7842_SELECT_HDMI_PORT_B: 1837 state->mode = ADV7842_MODE_HDMI; 1838 state->vid_std_select = ADV7842_HDMI_COMP_VID_STD_HD_1250P; 1839 state->hdmi_port_a = false; 1840 break; 1841 case ADV7842_SELECT_VGA_COMP: 1842 state->mode = ADV7842_MODE_COMP; 1843 state->vid_std_select = ADV7842_RGB_VID_STD_AUTO_GRAPH_MODE; 1844 break; 1845 case ADV7842_SELECT_VGA_RGB: 1846 state->mode = ADV7842_MODE_RGB; 1847 state->vid_std_select = ADV7842_RGB_VID_STD_AUTO_GRAPH_MODE; 1848 break; 1849 case ADV7842_SELECT_SDP_CVBS: 1850 state->mode = ADV7842_MODE_SDP; 1851 state->vid_std_select = ADV7842_SDP_VID_STD_CVBS_SD_4x1; 1852 break; 1853 case ADV7842_SELECT_SDP_YC: 1854 state->mode = ADV7842_MODE_SDP; 1855 state->vid_std_select = ADV7842_SDP_VID_STD_YC_SD4_x1; 1856 break; 1857 default: 1858 return -EINVAL; 1859 } 1860 1861 disable_input(sd); 1862 select_input(sd, state->vid_std_select); 1863 enable_input(sd); 1864 1865 v4l2_subdev_notify(sd, ADV7842_FMT_CHANGE, NULL); 1866 1867 return 0; 1868 } 1869 1870 static int adv7842_enum_mbus_fmt(struct v4l2_subdev *sd, unsigned int index, 1871 u32 *code) 1872 { 1873 if (index) 1874 return -EINVAL; 1875 /* Good enough for now */ 1876 *code = MEDIA_BUS_FMT_FIXED; 1877 return 0; 1878 } 1879 1880 static int adv7842_g_mbus_fmt(struct v4l2_subdev *sd, 1881 struct v4l2_mbus_framefmt *fmt) 1882 { 1883 struct adv7842_state *state = to_state(sd); 1884 1885 fmt->width = state->timings.bt.width; 1886 fmt->height = state->timings.bt.height; 1887 fmt->code = MEDIA_BUS_FMT_FIXED; 1888 fmt->field = V4L2_FIELD_NONE; 1889 1890 if (state->mode == ADV7842_MODE_SDP) { 1891 /* SPD block */ 1892 if (!(sdp_read(sd, 0x5A) & 0x01)) 1893 return -EINVAL; 1894 fmt->width = 720; 1895 /* valid signal */ 1896 if (state->norm & V4L2_STD_525_60) 1897 fmt->height = 480; 1898 else 1899 fmt->height = 576; 1900 fmt->colorspace = V4L2_COLORSPACE_SMPTE170M; 1901 return 0; 1902 } 1903 1904 fmt->colorspace = V4L2_COLORSPACE_SRGB; 1905 if (state->timings.bt.flags & V4L2_DV_FL_IS_CE_VIDEO) { 1906 fmt->colorspace = (state->timings.bt.height <= 576) ? 1907 V4L2_COLORSPACE_SMPTE170M : V4L2_COLORSPACE_REC709; 1908 } 1909 return 0; 1910 } 1911 1912 static void adv7842_irq_enable(struct v4l2_subdev *sd, bool enable) 1913 { 1914 if (enable) { 1915 /* Enable SSPD, STDI and CP locked/unlocked interrupts */ 1916 io_write(sd, 0x46, 0x9c); 1917 /* ESDP_50HZ_DET interrupt */ 1918 io_write(sd, 0x5a, 0x10); 1919 /* Enable CABLE_DET_A/B_ST (+5v) interrupt */ 1920 io_write(sd, 0x73, 0x03); 1921 /* Enable V_LOCKED and DE_REGEN_LCK interrupts */ 1922 io_write(sd, 0x78, 0x03); 1923 /* Enable SDP Standard Detection Change and SDP Video Detected */ 1924 io_write(sd, 0xa0, 0x09); 1925 /* Enable HDMI_MODE interrupt */ 1926 io_write(sd, 0x69, 0x08); 1927 } else { 1928 io_write(sd, 0x46, 0x0); 1929 io_write(sd, 0x5a, 0x0); 1930 io_write(sd, 0x73, 0x0); 1931 io_write(sd, 0x78, 0x0); 1932 io_write(sd, 0xa0, 0x0); 1933 io_write(sd, 0x69, 0x0); 1934 } 1935 } 1936 1937 static int adv7842_isr(struct v4l2_subdev *sd, u32 status, bool *handled) 1938 { 1939 struct adv7842_state *state = to_state(sd); 1940 u8 fmt_change_cp, fmt_change_digital, fmt_change_sdp; 1941 u8 irq_status[6]; 1942 1943 adv7842_irq_enable(sd, false); 1944 1945 /* read status */ 1946 irq_status[0] = io_read(sd, 0x43); 1947 irq_status[1] = io_read(sd, 0x57); 1948 irq_status[2] = io_read(sd, 0x70); 1949 irq_status[3] = io_read(sd, 0x75); 1950 irq_status[4] = io_read(sd, 0x9d); 1951 irq_status[5] = io_read(sd, 0x66); 1952 1953 /* and clear */ 1954 if (irq_status[0]) 1955 io_write(sd, 0x44, irq_status[0]); 1956 if (irq_status[1]) 1957 io_write(sd, 0x58, irq_status[1]); 1958 if (irq_status[2]) 1959 io_write(sd, 0x71, irq_status[2]); 1960 if (irq_status[3]) 1961 io_write(sd, 0x76, irq_status[3]); 1962 if (irq_status[4]) 1963 io_write(sd, 0x9e, irq_status[4]); 1964 if (irq_status[5]) 1965 io_write(sd, 0x67, irq_status[5]); 1966 1967 adv7842_irq_enable(sd, true); 1968 1969 v4l2_dbg(1, debug, sd, "%s: irq %x, %x, %x, %x, %x, %x\n", __func__, 1970 irq_status[0], irq_status[1], irq_status[2], 1971 irq_status[3], irq_status[4], irq_status[5]); 1972 1973 /* format change CP */ 1974 fmt_change_cp = irq_status[0] & 0x9c; 1975 1976 /* format change SDP */ 1977 if (state->mode == ADV7842_MODE_SDP) 1978 fmt_change_sdp = (irq_status[1] & 0x30) | (irq_status[4] & 0x09); 1979 else 1980 fmt_change_sdp = 0; 1981 1982 /* digital format CP */ 1983 if (is_digital_input(sd)) 1984 fmt_change_digital = irq_status[3] & 0x03; 1985 else 1986 fmt_change_digital = 0; 1987 1988 /* format change */ 1989 if (fmt_change_cp || fmt_change_digital || fmt_change_sdp) { 1990 v4l2_dbg(1, debug, sd, 1991 "%s: fmt_change_cp = 0x%x, fmt_change_digital = 0x%x, fmt_change_sdp = 0x%x\n", 1992 __func__, fmt_change_cp, fmt_change_digital, 1993 fmt_change_sdp); 1994 v4l2_subdev_notify(sd, ADV7842_FMT_CHANGE, NULL); 1995 if (handled) 1996 *handled = true; 1997 } 1998 1999 /* HDMI/DVI mode */ 2000 if (irq_status[5] & 0x08) { 2001 v4l2_dbg(1, debug, sd, "%s: irq %s mode\n", __func__, 2002 (io_read(sd, 0x65) & 0x08) ? "HDMI" : "DVI"); 2003 set_rgb_quantization_range(sd); 2004 if (handled) 2005 *handled = true; 2006 } 2007 2008 /* tx 5v detect */ 2009 if (irq_status[2] & 0x3) { 2010 v4l2_dbg(1, debug, sd, "%s: irq tx_5v\n", __func__); 2011 adv7842_s_detect_tx_5v_ctrl(sd); 2012 if (handled) 2013 *handled = true; 2014 } 2015 return 0; 2016 } 2017 2018 static int adv7842_get_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid) 2019 { 2020 struct adv7842_state *state = to_state(sd); 2021 u8 *data = NULL; 2022 2023 memset(edid->reserved, 0, sizeof(edid->reserved)); 2024 2025 switch (edid->pad) { 2026 case ADV7842_EDID_PORT_A: 2027 case ADV7842_EDID_PORT_B: 2028 if (state->hdmi_edid.present & (0x04 << edid->pad)) 2029 data = state->hdmi_edid.edid; 2030 break; 2031 case ADV7842_EDID_PORT_VGA: 2032 if (state->vga_edid.present) 2033 data = state->vga_edid.edid; 2034 break; 2035 default: 2036 return -EINVAL; 2037 } 2038 2039 if (edid->start_block == 0 && edid->blocks == 0) { 2040 edid->blocks = data ? 2 : 0; 2041 return 0; 2042 } 2043 2044 if (!data) 2045 return -ENODATA; 2046 2047 if (edid->start_block >= 2) 2048 return -EINVAL; 2049 2050 if (edid->start_block + edid->blocks > 2) 2051 edid->blocks = 2 - edid->start_block; 2052 2053 memcpy(edid->edid, data + edid->start_block * 128, edid->blocks * 128); 2054 2055 return 0; 2056 } 2057 2058 static int adv7842_set_edid(struct v4l2_subdev *sd, struct v4l2_edid *e) 2059 { 2060 struct adv7842_state *state = to_state(sd); 2061 int err = 0; 2062 2063 memset(e->reserved, 0, sizeof(e->reserved)); 2064 2065 if (e->pad > ADV7842_EDID_PORT_VGA) 2066 return -EINVAL; 2067 if (e->start_block != 0) 2068 return -EINVAL; 2069 if (e->blocks > 2) { 2070 e->blocks = 2; 2071 return -E2BIG; 2072 } 2073 2074 /* todo, per edid */ 2075 state->aspect_ratio = v4l2_calc_aspect_ratio(e->edid[0x15], 2076 e->edid[0x16]); 2077 2078 switch (e->pad) { 2079 case ADV7842_EDID_PORT_VGA: 2080 memset(&state->vga_edid.edid, 0, 256); 2081 state->vga_edid.present = e->blocks ? 0x1 : 0x0; 2082 memcpy(&state->vga_edid.edid, e->edid, 128 * e->blocks); 2083 err = edid_write_vga_segment(sd); 2084 break; 2085 case ADV7842_EDID_PORT_A: 2086 case ADV7842_EDID_PORT_B: 2087 memset(&state->hdmi_edid.edid, 0, 256); 2088 if (e->blocks) 2089 state->hdmi_edid.present |= 0x04 << e->pad; 2090 else 2091 state->hdmi_edid.present &= ~(0x04 << e->pad); 2092 memcpy(&state->hdmi_edid.edid, e->edid, 128 * e->blocks); 2093 err = edid_write_hdmi_segment(sd, e->pad); 2094 break; 2095 default: 2096 return -EINVAL; 2097 } 2098 if (err < 0) 2099 v4l2_err(sd, "error %d writing edid on port %d\n", err, e->pad); 2100 return err; 2101 } 2102 2103 struct adv7842_cfg_read_infoframe { 2104 const char *desc; 2105 u8 present_mask; 2106 u8 head_addr; 2107 u8 payload_addr; 2108 }; 2109 2110 static void log_infoframe(struct v4l2_subdev *sd, struct adv7842_cfg_read_infoframe *cri) 2111 { 2112 int i; 2113 uint8_t buffer[32]; 2114 union hdmi_infoframe frame; 2115 u8 len; 2116 struct i2c_client *client = v4l2_get_subdevdata(sd); 2117 struct device *dev = &client->dev; 2118 2119 if (!(io_read(sd, 0x60) & cri->present_mask)) { 2120 v4l2_info(sd, "%s infoframe not received\n", cri->desc); 2121 return; 2122 } 2123 2124 for (i = 0; i < 3; i++) 2125 buffer[i] = infoframe_read(sd, cri->head_addr + i); 2126 2127 len = buffer[2] + 1; 2128 2129 if (len + 3 > sizeof(buffer)) { 2130 v4l2_err(sd, "%s: invalid %s infoframe length %d\n", __func__, cri->desc, len); 2131 return; 2132 } 2133 2134 for (i = 0; i < len; i++) 2135 buffer[i + 3] = infoframe_read(sd, cri->payload_addr + i); 2136 2137 if (hdmi_infoframe_unpack(&frame, buffer) < 0) { 2138 v4l2_err(sd, "%s: unpack of %s infoframe failed\n", __func__, cri->desc); 2139 return; 2140 } 2141 2142 hdmi_infoframe_log(KERN_INFO, dev, &frame); 2143 } 2144 2145 static void adv7842_log_infoframes(struct v4l2_subdev *sd) 2146 { 2147 int i; 2148 struct adv7842_cfg_read_infoframe cri[] = { 2149 { "AVI", 0x01, 0xe0, 0x00 }, 2150 { "Audio", 0x02, 0xe3, 0x1c }, 2151 { "SDP", 0x04, 0xe6, 0x2a }, 2152 { "Vendor", 0x10, 0xec, 0x54 } 2153 }; 2154 2155 if (!(hdmi_read(sd, 0x05) & 0x80)) { 2156 v4l2_info(sd, "receive DVI-D signal, no infoframes\n"); 2157 return; 2158 } 2159 2160 for (i = 0; i < ARRAY_SIZE(cri); i++) 2161 log_infoframe(sd, &cri[i]); 2162 } 2163 2164 static const char * const prim_mode_txt[] = { 2165 "SDP", 2166 "Component", 2167 "Graphics", 2168 "Reserved", 2169 "CVBS & HDMI AUDIO", 2170 "HDMI-Comp", 2171 "HDMI-GR", 2172 "Reserved", 2173 "Reserved", 2174 "Reserved", 2175 "Reserved", 2176 "Reserved", 2177 "Reserved", 2178 "Reserved", 2179 "Reserved", 2180 "Reserved", 2181 }; 2182 2183 static int adv7842_sdp_log_status(struct v4l2_subdev *sd) 2184 { 2185 /* SDP (Standard definition processor) block */ 2186 uint8_t sdp_signal_detected = sdp_read(sd, 0x5A) & 0x01; 2187 2188 v4l2_info(sd, "Chip powered %s\n", no_power(sd) ? "off" : "on"); 2189 v4l2_info(sd, "Prim-mode = 0x%x, video std = 0x%x\n", 2190 io_read(sd, 0x01) & 0x0f, io_read(sd, 0x00) & 0x3f); 2191 2192 v4l2_info(sd, "SDP: free run: %s\n", 2193 (sdp_read(sd, 0x56) & 0x01) ? "on" : "off"); 2194 v4l2_info(sd, "SDP: %s\n", sdp_signal_detected ? 2195 "valid SD/PR signal detected" : "invalid/no signal"); 2196 if (sdp_signal_detected) { 2197 static const char * const sdp_std_txt[] = { 2198 "NTSC-M/J", 2199 "1?", 2200 "NTSC-443", 2201 "60HzSECAM", 2202 "PAL-M", 2203 "5?", 2204 "PAL-60", 2205 "7?", "8?", "9?", "a?", "b?", 2206 "PAL-CombN", 2207 "d?", 2208 "PAL-BGHID", 2209 "SECAM" 2210 }; 2211 v4l2_info(sd, "SDP: standard %s\n", 2212 sdp_std_txt[sdp_read(sd, 0x52) & 0x0f]); 2213 v4l2_info(sd, "SDP: %s\n", 2214 (sdp_read(sd, 0x59) & 0x08) ? "50Hz" : "60Hz"); 2215 v4l2_info(sd, "SDP: %s\n", 2216 (sdp_read(sd, 0x57) & 0x08) ? "Interlaced" : "Progressive"); 2217 v4l2_info(sd, "SDP: deinterlacer %s\n", 2218 (sdp_read(sd, 0x12) & 0x08) ? "enabled" : "disabled"); 2219 v4l2_info(sd, "SDP: csc %s mode\n", 2220 (sdp_io_read(sd, 0xe0) & 0x40) ? "auto" : "manual"); 2221 } 2222 return 0; 2223 } 2224 2225 static int adv7842_cp_log_status(struct v4l2_subdev *sd) 2226 { 2227 /* CP block */ 2228 struct adv7842_state *state = to_state(sd); 2229 struct v4l2_dv_timings timings; 2230 uint8_t reg_io_0x02 = io_read(sd, 0x02); 2231 uint8_t reg_io_0x21 = io_read(sd, 0x21); 2232 uint8_t reg_rep_0x77 = rep_read(sd, 0x77); 2233 uint8_t reg_rep_0x7d = rep_read(sd, 0x7d); 2234 bool audio_pll_locked = hdmi_read(sd, 0x04) & 0x01; 2235 bool audio_sample_packet_detect = hdmi_read(sd, 0x18) & 0x01; 2236 bool audio_mute = io_read(sd, 0x65) & 0x40; 2237 2238 static const char * const csc_coeff_sel_rb[16] = { 2239 "bypassed", "YPbPr601 -> RGB", "reserved", "YPbPr709 -> RGB", 2240 "reserved", "RGB -> YPbPr601", "reserved", "RGB -> YPbPr709", 2241 "reserved", "YPbPr709 -> YPbPr601", "YPbPr601 -> YPbPr709", 2242 "reserved", "reserved", "reserved", "reserved", "manual" 2243 }; 2244 static const char * const input_color_space_txt[16] = { 2245 "RGB limited range (16-235)", "RGB full range (0-255)", 2246 "YCbCr Bt.601 (16-235)", "YCbCr Bt.709 (16-235)", 2247 "xvYCC Bt.601", "xvYCC Bt.709", 2248 "YCbCr Bt.601 (0-255)", "YCbCr Bt.709 (0-255)", 2249 "invalid", "invalid", "invalid", "invalid", "invalid", 2250 "invalid", "invalid", "automatic" 2251 }; 2252 static const char * const rgb_quantization_range_txt[] = { 2253 "Automatic", 2254 "RGB limited range (16-235)", 2255 "RGB full range (0-255)", 2256 }; 2257 static const char * const deep_color_mode_txt[4] = { 2258 "8-bits per channel", 2259 "10-bits per channel", 2260 "12-bits per channel", 2261 "16-bits per channel (not supported)" 2262 }; 2263 2264 v4l2_info(sd, "-----Chip status-----\n"); 2265 v4l2_info(sd, "Chip power: %s\n", no_power(sd) ? "off" : "on"); 2266 v4l2_info(sd, "HDMI/DVI-D port selected: %s\n", 2267 state->hdmi_port_a ? "A" : "B"); 2268 v4l2_info(sd, "EDID A %s, B %s\n", 2269 ((reg_rep_0x7d & 0x04) && (reg_rep_0x77 & 0x04)) ? 2270 "enabled" : "disabled", 2271 ((reg_rep_0x7d & 0x08) && (reg_rep_0x77 & 0x08)) ? 2272 "enabled" : "disabled"); 2273 v4l2_info(sd, "HPD A %s, B %s\n", 2274 reg_io_0x21 & 0x02 ? "enabled" : "disabled", 2275 reg_io_0x21 & 0x01 ? "enabled" : "disabled"); 2276 v4l2_info(sd, "CEC %s\n", !!(cec_read(sd, 0x2a) & 0x01) ? 2277 "enabled" : "disabled"); 2278 2279 v4l2_info(sd, "-----Signal status-----\n"); 2280 if (state->hdmi_port_a) { 2281 v4l2_info(sd, "Cable detected (+5V power): %s\n", 2282 io_read(sd, 0x6f) & 0x02 ? "true" : "false"); 2283 v4l2_info(sd, "TMDS signal detected: %s\n", 2284 (io_read(sd, 0x6a) & 0x02) ? "true" : "false"); 2285 v4l2_info(sd, "TMDS signal locked: %s\n", 2286 (io_read(sd, 0x6a) & 0x20) ? "true" : "false"); 2287 } else { 2288 v4l2_info(sd, "Cable detected (+5V power):%s\n", 2289 io_read(sd, 0x6f) & 0x01 ? "true" : "false"); 2290 v4l2_info(sd, "TMDS signal detected: %s\n", 2291 (io_read(sd, 0x6a) & 0x01) ? "true" : "false"); 2292 v4l2_info(sd, "TMDS signal locked: %s\n", 2293 (io_read(sd, 0x6a) & 0x10) ? "true" : "false"); 2294 } 2295 v4l2_info(sd, "CP free run: %s\n", 2296 (!!(cp_read(sd, 0xff) & 0x10) ? "on" : "off")); 2297 v4l2_info(sd, "Prim-mode = 0x%x, video std = 0x%x, v_freq = 0x%x\n", 2298 io_read(sd, 0x01) & 0x0f, io_read(sd, 0x00) & 0x3f, 2299 (io_read(sd, 0x01) & 0x70) >> 4); 2300 2301 v4l2_info(sd, "-----Video Timings-----\n"); 2302 if (no_cp_signal(sd)) { 2303 v4l2_info(sd, "STDI: not locked\n"); 2304 } else { 2305 uint32_t bl = ((cp_read(sd, 0xb1) & 0x3f) << 8) | cp_read(sd, 0xb2); 2306 uint32_t lcf = ((cp_read(sd, 0xb3) & 0x7) << 8) | cp_read(sd, 0xb4); 2307 uint32_t lcvs = cp_read(sd, 0xb3) >> 3; 2308 uint32_t fcl = ((cp_read(sd, 0xb8) & 0x1f) << 8) | cp_read(sd, 0xb9); 2309 char hs_pol = ((cp_read(sd, 0xb5) & 0x10) ? 2310 ((cp_read(sd, 0xb5) & 0x08) ? '+' : '-') : 'x'); 2311 char vs_pol = ((cp_read(sd, 0xb5) & 0x40) ? 2312 ((cp_read(sd, 0xb5) & 0x20) ? '+' : '-') : 'x'); 2313 v4l2_info(sd, 2314 "STDI: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, fcl = %d, %s, %chsync, %cvsync\n", 2315 lcf, bl, lcvs, fcl, 2316 (cp_read(sd, 0xb1) & 0x40) ? 2317 "interlaced" : "progressive", 2318 hs_pol, vs_pol); 2319 } 2320 if (adv7842_query_dv_timings(sd, &timings)) 2321 v4l2_info(sd, "No video detected\n"); 2322 else 2323 v4l2_print_dv_timings(sd->name, "Detected format: ", 2324 &timings, true); 2325 v4l2_print_dv_timings(sd->name, "Configured format: ", 2326 &state->timings, true); 2327 2328 if (no_cp_signal(sd)) 2329 return 0; 2330 2331 v4l2_info(sd, "-----Color space-----\n"); 2332 v4l2_info(sd, "RGB quantization range ctrl: %s\n", 2333 rgb_quantization_range_txt[state->rgb_quantization_range]); 2334 v4l2_info(sd, "Input color space: %s\n", 2335 input_color_space_txt[reg_io_0x02 >> 4]); 2336 v4l2_info(sd, "Output color space: %s %s, saturator %s\n", 2337 (reg_io_0x02 & 0x02) ? "RGB" : "YCbCr", 2338 (reg_io_0x02 & 0x04) ? "(16-235)" : "(0-255)", 2339 ((reg_io_0x02 & 0x04) ^ (reg_io_0x02 & 0x01)) ? 2340 "enabled" : "disabled"); 2341 v4l2_info(sd, "Color space conversion: %s\n", 2342 csc_coeff_sel_rb[cp_read(sd, 0xf4) >> 4]); 2343 2344 if (!is_digital_input(sd)) 2345 return 0; 2346 2347 v4l2_info(sd, "-----%s status-----\n", is_hdmi(sd) ? "HDMI" : "DVI-D"); 2348 v4l2_info(sd, "HDCP encrypted content: %s\n", 2349 (hdmi_read(sd, 0x05) & 0x40) ? "true" : "false"); 2350 v4l2_info(sd, "HDCP keys read: %s%s\n", 2351 (hdmi_read(sd, 0x04) & 0x20) ? "yes" : "no", 2352 (hdmi_read(sd, 0x04) & 0x10) ? "ERROR" : ""); 2353 if (!is_hdmi(sd)) 2354 return 0; 2355 2356 v4l2_info(sd, "Audio: pll %s, samples %s, %s\n", 2357 audio_pll_locked ? "locked" : "not locked", 2358 audio_sample_packet_detect ? "detected" : "not detected", 2359 audio_mute ? "muted" : "enabled"); 2360 if (audio_pll_locked && audio_sample_packet_detect) { 2361 v4l2_info(sd, "Audio format: %s\n", 2362 (hdmi_read(sd, 0x07) & 0x40) ? "multi-channel" : "stereo"); 2363 } 2364 v4l2_info(sd, "Audio CTS: %u\n", (hdmi_read(sd, 0x5b) << 12) + 2365 (hdmi_read(sd, 0x5c) << 8) + 2366 (hdmi_read(sd, 0x5d) & 0xf0)); 2367 v4l2_info(sd, "Audio N: %u\n", ((hdmi_read(sd, 0x5d) & 0x0f) << 16) + 2368 (hdmi_read(sd, 0x5e) << 8) + 2369 hdmi_read(sd, 0x5f)); 2370 v4l2_info(sd, "AV Mute: %s\n", 2371 (hdmi_read(sd, 0x04) & 0x40) ? "on" : "off"); 2372 v4l2_info(sd, "Deep color mode: %s\n", 2373 deep_color_mode_txt[hdmi_read(sd, 0x0b) >> 6]); 2374 2375 adv7842_log_infoframes(sd); 2376 2377 return 0; 2378 } 2379 2380 static int adv7842_log_status(struct v4l2_subdev *sd) 2381 { 2382 struct adv7842_state *state = to_state(sd); 2383 2384 if (state->mode == ADV7842_MODE_SDP) 2385 return adv7842_sdp_log_status(sd); 2386 return adv7842_cp_log_status(sd); 2387 } 2388 2389 static int adv7842_querystd(struct v4l2_subdev *sd, v4l2_std_id *std) 2390 { 2391 struct adv7842_state *state = to_state(sd); 2392 2393 v4l2_dbg(1, debug, sd, "%s:\n", __func__); 2394 2395 if (state->mode != ADV7842_MODE_SDP) 2396 return -ENODATA; 2397 2398 if (!(sdp_read(sd, 0x5A) & 0x01)) { 2399 *std = 0; 2400 v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__); 2401 return 0; 2402 } 2403 2404 switch (sdp_read(sd, 0x52) & 0x0f) { 2405 case 0: 2406 /* NTSC-M/J */ 2407 *std &= V4L2_STD_NTSC; 2408 break; 2409 case 2: 2410 /* NTSC-443 */ 2411 *std &= V4L2_STD_NTSC_443; 2412 break; 2413 case 3: 2414 /* 60HzSECAM */ 2415 *std &= V4L2_STD_SECAM; 2416 break; 2417 case 4: 2418 /* PAL-M */ 2419 *std &= V4L2_STD_PAL_M; 2420 break; 2421 case 6: 2422 /* PAL-60 */ 2423 *std &= V4L2_STD_PAL_60; 2424 break; 2425 case 0xc: 2426 /* PAL-CombN */ 2427 *std &= V4L2_STD_PAL_Nc; 2428 break; 2429 case 0xe: 2430 /* PAL-BGHID */ 2431 *std &= V4L2_STD_PAL; 2432 break; 2433 case 0xf: 2434 /* SECAM */ 2435 *std &= V4L2_STD_SECAM; 2436 break; 2437 default: 2438 *std &= V4L2_STD_ALL; 2439 break; 2440 } 2441 return 0; 2442 } 2443 2444 static void adv7842_s_sdp_io(struct v4l2_subdev *sd, struct adv7842_sdp_io_sync_adjustment *s) 2445 { 2446 if (s && s->adjust) { 2447 sdp_io_write(sd, 0x94, (s->hs_beg >> 8) & 0xf); 2448 sdp_io_write(sd, 0x95, s->hs_beg & 0xff); 2449 sdp_io_write(sd, 0x96, (s->hs_width >> 8) & 0xf); 2450 sdp_io_write(sd, 0x97, s->hs_width & 0xff); 2451 sdp_io_write(sd, 0x98, (s->de_beg >> 8) & 0xf); 2452 sdp_io_write(sd, 0x99, s->de_beg & 0xff); 2453 sdp_io_write(sd, 0x9a, (s->de_end >> 8) & 0xf); 2454 sdp_io_write(sd, 0x9b, s->de_end & 0xff); 2455 sdp_io_write(sd, 0xa8, s->vs_beg_o); 2456 sdp_io_write(sd, 0xa9, s->vs_beg_e); 2457 sdp_io_write(sd, 0xaa, s->vs_end_o); 2458 sdp_io_write(sd, 0xab, s->vs_end_e); 2459 sdp_io_write(sd, 0xac, s->de_v_beg_o); 2460 sdp_io_write(sd, 0xad, s->de_v_beg_e); 2461 sdp_io_write(sd, 0xae, s->de_v_end_o); 2462 sdp_io_write(sd, 0xaf, s->de_v_end_e); 2463 } else { 2464 /* set to default */ 2465 sdp_io_write(sd, 0x94, 0x00); 2466 sdp_io_write(sd, 0x95, 0x00); 2467 sdp_io_write(sd, 0x96, 0x00); 2468 sdp_io_write(sd, 0x97, 0x20); 2469 sdp_io_write(sd, 0x98, 0x00); 2470 sdp_io_write(sd, 0x99, 0x00); 2471 sdp_io_write(sd, 0x9a, 0x00); 2472 sdp_io_write(sd, 0x9b, 0x00); 2473 sdp_io_write(sd, 0xa8, 0x04); 2474 sdp_io_write(sd, 0xa9, 0x04); 2475 sdp_io_write(sd, 0xaa, 0x04); 2476 sdp_io_write(sd, 0xab, 0x04); 2477 sdp_io_write(sd, 0xac, 0x04); 2478 sdp_io_write(sd, 0xad, 0x04); 2479 sdp_io_write(sd, 0xae, 0x04); 2480 sdp_io_write(sd, 0xaf, 0x04); 2481 } 2482 } 2483 2484 static int adv7842_s_std(struct v4l2_subdev *sd, v4l2_std_id norm) 2485 { 2486 struct adv7842_state *state = to_state(sd); 2487 struct adv7842_platform_data *pdata = &state->pdata; 2488 2489 v4l2_dbg(1, debug, sd, "%s:\n", __func__); 2490 2491 if (state->mode != ADV7842_MODE_SDP) 2492 return -ENODATA; 2493 2494 if (norm & V4L2_STD_625_50) 2495 adv7842_s_sdp_io(sd, &pdata->sdp_io_sync_625); 2496 else if (norm & V4L2_STD_525_60) 2497 adv7842_s_sdp_io(sd, &pdata->sdp_io_sync_525); 2498 else 2499 adv7842_s_sdp_io(sd, NULL); 2500 2501 if (norm & V4L2_STD_ALL) { 2502 state->norm = norm; 2503 return 0; 2504 } 2505 return -EINVAL; 2506 } 2507 2508 static int adv7842_g_std(struct v4l2_subdev *sd, v4l2_std_id *norm) 2509 { 2510 struct adv7842_state *state = to_state(sd); 2511 2512 v4l2_dbg(1, debug, sd, "%s:\n", __func__); 2513 2514 if (state->mode != ADV7842_MODE_SDP) 2515 return -ENODATA; 2516 2517 *norm = state->norm; 2518 return 0; 2519 } 2520 2521 /* ----------------------------------------------------------------------- */ 2522 2523 static int adv7842_core_init(struct v4l2_subdev *sd) 2524 { 2525 struct adv7842_state *state = to_state(sd); 2526 struct adv7842_platform_data *pdata = &state->pdata; 2527 hdmi_write(sd, 0x48, 2528 (pdata->disable_pwrdnb ? 0x80 : 0) | 2529 (pdata->disable_cable_det_rst ? 0x40 : 0)); 2530 2531 disable_input(sd); 2532 2533 /* 2534 * Disable I2C access to internal EDID ram from HDMI DDC ports 2535 * Disable auto edid enable when leaving powerdown mode 2536 */ 2537 rep_write_and_or(sd, 0x77, 0xd3, 0x20); 2538 2539 /* power */ 2540 io_write(sd, 0x0c, 0x42); /* Power up part and power down VDP */ 2541 io_write(sd, 0x15, 0x80); /* Power up pads */ 2542 2543 /* video format */ 2544 io_write(sd, 0x02, 2545 0xf0 | 2546 pdata->alt_gamma << 3 | 2547 pdata->op_656_range << 2 | 2548 pdata->rgb_out << 1 | 2549 pdata->alt_data_sat << 0); 2550 io_write(sd, 0x03, pdata->op_format_sel); 2551 io_write_and_or(sd, 0x04, 0x1f, pdata->op_ch_sel << 5); 2552 io_write_and_or(sd, 0x05, 0xf0, pdata->blank_data << 3 | 2553 pdata->insert_av_codes << 2 | 2554 pdata->replicate_av_codes << 1 | 2555 pdata->invert_cbcr << 0); 2556 2557 /* HDMI audio */ 2558 hdmi_write_and_or(sd, 0x1a, 0xf1, 0x08); /* Wait 1 s before unmute */ 2559 2560 /* Drive strength */ 2561 io_write_and_or(sd, 0x14, 0xc0, 2562 pdata->dr_str_data << 4 | 2563 pdata->dr_str_clk << 2 | 2564 pdata->dr_str_sync); 2565 2566 /* HDMI free run */ 2567 cp_write_and_or(sd, 0xba, 0xfc, pdata->hdmi_free_run_enable | 2568 (pdata->hdmi_free_run_mode << 1)); 2569 2570 /* SPD free run */ 2571 sdp_write_and_or(sd, 0xdd, 0xf0, pdata->sdp_free_run_force | 2572 (pdata->sdp_free_run_cbar_en << 1) | 2573 (pdata->sdp_free_run_man_col_en << 2) | 2574 (pdata->sdp_free_run_auto << 3)); 2575 2576 /* TODO from platform data */ 2577 cp_write(sd, 0x69, 0x14); /* Enable CP CSC */ 2578 io_write(sd, 0x06, 0xa6); /* positive VS and HS and DE */ 2579 cp_write(sd, 0xf3, 0xdc); /* Low threshold to enter/exit free run mode */ 2580 afe_write(sd, 0xb5, 0x01); /* Setting MCLK to 256Fs */ 2581 2582 afe_write(sd, 0x02, pdata->ain_sel); /* Select analog input muxing mode */ 2583 io_write_and_or(sd, 0x30, ~(1 << 4), pdata->output_bus_lsb_to_msb << 4); 2584 2585 sdp_csc_coeff(sd, &pdata->sdp_csc_coeff); 2586 2587 /* todo, improve settings for sdram */ 2588 if (pdata->sd_ram_size >= 128) { 2589 sdp_write(sd, 0x12, 0x0d); /* Frame TBC,3D comb enabled */ 2590 if (pdata->sd_ram_ddr) { 2591 /* SDP setup for the AD eval board */ 2592 sdp_io_write(sd, 0x6f, 0x00); /* DDR mode */ 2593 sdp_io_write(sd, 0x75, 0x0a); /* 128 MB memory size */ 2594 sdp_io_write(sd, 0x7a, 0xa5); /* Timing Adjustment */ 2595 sdp_io_write(sd, 0x7b, 0x8f); /* Timing Adjustment */ 2596 sdp_io_write(sd, 0x60, 0x01); /* SDRAM reset */ 2597 } else { 2598 sdp_io_write(sd, 0x75, 0x0a); /* 64 MB memory size ?*/ 2599 sdp_io_write(sd, 0x74, 0x00); /* must be zero for sdr sdram */ 2600 sdp_io_write(sd, 0x79, 0x33); /* CAS latency to 3, 2601 depends on memory */ 2602 sdp_io_write(sd, 0x6f, 0x01); /* SDR mode */ 2603 sdp_io_write(sd, 0x7a, 0xa5); /* Timing Adjustment */ 2604 sdp_io_write(sd, 0x7b, 0x8f); /* Timing Adjustment */ 2605 sdp_io_write(sd, 0x60, 0x01); /* SDRAM reset */ 2606 } 2607 } else { 2608 /* 2609 * Manual UG-214, rev 0 is bit confusing on this bit 2610 * but a '1' disables any signal if the Ram is active. 2611 */ 2612 sdp_io_write(sd, 0x29, 0x10); /* Tristate memory interface */ 2613 } 2614 2615 select_input(sd, pdata->vid_std_select); 2616 2617 enable_input(sd); 2618 2619 if (pdata->hpa_auto) { 2620 /* HPA auto, HPA 0.5s after Edid set and Cable detect */ 2621 hdmi_write(sd, 0x69, 0x5c); 2622 } else { 2623 /* HPA manual */ 2624 hdmi_write(sd, 0x69, 0xa3); 2625 /* HPA disable on port A and B */ 2626 io_write_and_or(sd, 0x20, 0xcf, 0x00); 2627 } 2628 2629 /* LLC */ 2630 io_write(sd, 0x19, 0x80 | pdata->llc_dll_phase); 2631 io_write(sd, 0x33, 0x40); 2632 2633 /* interrupts */ 2634 io_write(sd, 0x40, 0xf2); /* Configure INT1 */ 2635 2636 adv7842_irq_enable(sd, true); 2637 2638 return v4l2_ctrl_handler_setup(sd->ctrl_handler); 2639 } 2640 2641 /* ----------------------------------------------------------------------- */ 2642 2643 static int adv7842_ddr_ram_test(struct v4l2_subdev *sd) 2644 { 2645 /* 2646 * From ADV784x external Memory test.pdf 2647 * 2648 * Reset must just been performed before running test. 2649 * Recommended to reset after test. 2650 */ 2651 int i; 2652 int pass = 0; 2653 int fail = 0; 2654 int complete = 0; 2655 2656 io_write(sd, 0x00, 0x01); /* Program SDP 4x1 */ 2657 io_write(sd, 0x01, 0x00); /* Program SDP mode */ 2658 afe_write(sd, 0x80, 0x92); /* SDP Recommeneded Write */ 2659 afe_write(sd, 0x9B, 0x01); /* SDP Recommeneded Write ADV7844ES1 */ 2660 afe_write(sd, 0x9C, 0x60); /* SDP Recommeneded Write ADV7844ES1 */ 2661 afe_write(sd, 0x9E, 0x02); /* SDP Recommeneded Write ADV7844ES1 */ 2662 afe_write(sd, 0xA0, 0x0B); /* SDP Recommeneded Write ADV7844ES1 */ 2663 afe_write(sd, 0xC3, 0x02); /* Memory BIST Initialisation */ 2664 io_write(sd, 0x0C, 0x40); /* Power up ADV7844 */ 2665 io_write(sd, 0x15, 0xBA); /* Enable outputs */ 2666 sdp_write(sd, 0x12, 0x00); /* Disable 3D comb, Frame TBC & 3DNR */ 2667 io_write(sd, 0xFF, 0x04); /* Reset memory controller */ 2668 2669 mdelay(5); 2670 2671 sdp_write(sd, 0x12, 0x00); /* Disable 3D Comb, Frame TBC & 3DNR */ 2672 sdp_io_write(sd, 0x2A, 0x01); /* Memory BIST Initialisation */ 2673 sdp_io_write(sd, 0x7c, 0x19); /* Memory BIST Initialisation */ 2674 sdp_io_write(sd, 0x80, 0x87); /* Memory BIST Initialisation */ 2675 sdp_io_write(sd, 0x81, 0x4a); /* Memory BIST Initialisation */ 2676 sdp_io_write(sd, 0x82, 0x2c); /* Memory BIST Initialisation */ 2677 sdp_io_write(sd, 0x83, 0x0e); /* Memory BIST Initialisation */ 2678 sdp_io_write(sd, 0x84, 0x94); /* Memory BIST Initialisation */ 2679 sdp_io_write(sd, 0x85, 0x62); /* Memory BIST Initialisation */ 2680 sdp_io_write(sd, 0x7d, 0x00); /* Memory BIST Initialisation */ 2681 sdp_io_write(sd, 0x7e, 0x1a); /* Memory BIST Initialisation */ 2682 2683 mdelay(5); 2684 2685 sdp_io_write(sd, 0xd9, 0xd5); /* Enable BIST Test */ 2686 sdp_write(sd, 0x12, 0x05); /* Enable FRAME TBC & 3D COMB */ 2687 2688 mdelay(20); 2689 2690 for (i = 0; i < 10; i++) { 2691 u8 result = sdp_io_read(sd, 0xdb); 2692 if (result & 0x10) { 2693 complete++; 2694 if (result & 0x20) 2695 fail++; 2696 else 2697 pass++; 2698 } 2699 mdelay(20); 2700 } 2701 2702 v4l2_dbg(1, debug, sd, 2703 "Ram Test: completed %d of %d: pass %d, fail %d\n", 2704 complete, i, pass, fail); 2705 2706 if (!complete || fail) 2707 return -EIO; 2708 return 0; 2709 } 2710 2711 static void adv7842_rewrite_i2c_addresses(struct v4l2_subdev *sd, 2712 struct adv7842_platform_data *pdata) 2713 { 2714 io_write(sd, 0xf1, pdata->i2c_sdp << 1); 2715 io_write(sd, 0xf2, pdata->i2c_sdp_io << 1); 2716 io_write(sd, 0xf3, pdata->i2c_avlink << 1); 2717 io_write(sd, 0xf4, pdata->i2c_cec << 1); 2718 io_write(sd, 0xf5, pdata->i2c_infoframe << 1); 2719 2720 io_write(sd, 0xf8, pdata->i2c_afe << 1); 2721 io_write(sd, 0xf9, pdata->i2c_repeater << 1); 2722 io_write(sd, 0xfa, pdata->i2c_edid << 1); 2723 io_write(sd, 0xfb, pdata->i2c_hdmi << 1); 2724 2725 io_write(sd, 0xfd, pdata->i2c_cp << 1); 2726 io_write(sd, 0xfe, pdata->i2c_vdp << 1); 2727 } 2728 2729 static int adv7842_command_ram_test(struct v4l2_subdev *sd) 2730 { 2731 struct i2c_client *client = v4l2_get_subdevdata(sd); 2732 struct adv7842_state *state = to_state(sd); 2733 struct adv7842_platform_data *pdata = client->dev.platform_data; 2734 struct v4l2_dv_timings timings; 2735 int ret = 0; 2736 2737 if (!pdata) 2738 return -ENODEV; 2739 2740 if (!pdata->sd_ram_size || !pdata->sd_ram_ddr) { 2741 v4l2_info(sd, "no sdram or no ddr sdram\n"); 2742 return -EINVAL; 2743 } 2744 2745 main_reset(sd); 2746 2747 adv7842_rewrite_i2c_addresses(sd, pdata); 2748 2749 /* run ram test */ 2750 ret = adv7842_ddr_ram_test(sd); 2751 2752 main_reset(sd); 2753 2754 adv7842_rewrite_i2c_addresses(sd, pdata); 2755 2756 /* and re-init chip and state */ 2757 adv7842_core_init(sd); 2758 2759 disable_input(sd); 2760 2761 select_input(sd, state->vid_std_select); 2762 2763 enable_input(sd); 2764 2765 edid_write_vga_segment(sd); 2766 edid_write_hdmi_segment(sd, ADV7842_EDID_PORT_A); 2767 edid_write_hdmi_segment(sd, ADV7842_EDID_PORT_B); 2768 2769 timings = state->timings; 2770 2771 memset(&state->timings, 0, sizeof(struct v4l2_dv_timings)); 2772 2773 adv7842_s_dv_timings(sd, &timings); 2774 2775 return ret; 2776 } 2777 2778 static long adv7842_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg) 2779 { 2780 switch (cmd) { 2781 case ADV7842_CMD_RAM_TEST: 2782 return adv7842_command_ram_test(sd); 2783 } 2784 return -ENOTTY; 2785 } 2786 2787 /* ----------------------------------------------------------------------- */ 2788 2789 static const struct v4l2_ctrl_ops adv7842_ctrl_ops = { 2790 .s_ctrl = adv7842_s_ctrl, 2791 }; 2792 2793 static const struct v4l2_subdev_core_ops adv7842_core_ops = { 2794 .log_status = adv7842_log_status, 2795 .ioctl = adv7842_ioctl, 2796 .interrupt_service_routine = adv7842_isr, 2797 #ifdef CONFIG_VIDEO_ADV_DEBUG 2798 .g_register = adv7842_g_register, 2799 .s_register = adv7842_s_register, 2800 #endif 2801 }; 2802 2803 static const struct v4l2_subdev_video_ops adv7842_video_ops = { 2804 .g_std = adv7842_g_std, 2805 .s_std = adv7842_s_std, 2806 .s_routing = adv7842_s_routing, 2807 .querystd = adv7842_querystd, 2808 .g_input_status = adv7842_g_input_status, 2809 .s_dv_timings = adv7842_s_dv_timings, 2810 .g_dv_timings = adv7842_g_dv_timings, 2811 .query_dv_timings = adv7842_query_dv_timings, 2812 .enum_mbus_fmt = adv7842_enum_mbus_fmt, 2813 .g_mbus_fmt = adv7842_g_mbus_fmt, 2814 .try_mbus_fmt = adv7842_g_mbus_fmt, 2815 .s_mbus_fmt = adv7842_g_mbus_fmt, 2816 }; 2817 2818 static const struct v4l2_subdev_pad_ops adv7842_pad_ops = { 2819 .get_edid = adv7842_get_edid, 2820 .set_edid = adv7842_set_edid, 2821 .enum_dv_timings = adv7842_enum_dv_timings, 2822 .dv_timings_cap = adv7842_dv_timings_cap, 2823 }; 2824 2825 static const struct v4l2_subdev_ops adv7842_ops = { 2826 .core = &adv7842_core_ops, 2827 .video = &adv7842_video_ops, 2828 .pad = &adv7842_pad_ops, 2829 }; 2830 2831 /* -------------------------- custom ctrls ---------------------------------- */ 2832 2833 static const struct v4l2_ctrl_config adv7842_ctrl_analog_sampling_phase = { 2834 .ops = &adv7842_ctrl_ops, 2835 .id = V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE, 2836 .name = "Analog Sampling Phase", 2837 .type = V4L2_CTRL_TYPE_INTEGER, 2838 .min = 0, 2839 .max = 0x1f, 2840 .step = 1, 2841 .def = 0, 2842 }; 2843 2844 static const struct v4l2_ctrl_config adv7842_ctrl_free_run_color_manual = { 2845 .ops = &adv7842_ctrl_ops, 2846 .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL, 2847 .name = "Free Running Color, Manual", 2848 .type = V4L2_CTRL_TYPE_BOOLEAN, 2849 .max = 1, 2850 .step = 1, 2851 .def = 1, 2852 }; 2853 2854 static const struct v4l2_ctrl_config adv7842_ctrl_free_run_color = { 2855 .ops = &adv7842_ctrl_ops, 2856 .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR, 2857 .name = "Free Running Color", 2858 .type = V4L2_CTRL_TYPE_INTEGER, 2859 .max = 0xffffff, 2860 .step = 0x1, 2861 }; 2862 2863 2864 static void adv7842_unregister_clients(struct v4l2_subdev *sd) 2865 { 2866 struct adv7842_state *state = to_state(sd); 2867 if (state->i2c_avlink) 2868 i2c_unregister_device(state->i2c_avlink); 2869 if (state->i2c_cec) 2870 i2c_unregister_device(state->i2c_cec); 2871 if (state->i2c_infoframe) 2872 i2c_unregister_device(state->i2c_infoframe); 2873 if (state->i2c_sdp_io) 2874 i2c_unregister_device(state->i2c_sdp_io); 2875 if (state->i2c_sdp) 2876 i2c_unregister_device(state->i2c_sdp); 2877 if (state->i2c_afe) 2878 i2c_unregister_device(state->i2c_afe); 2879 if (state->i2c_repeater) 2880 i2c_unregister_device(state->i2c_repeater); 2881 if (state->i2c_edid) 2882 i2c_unregister_device(state->i2c_edid); 2883 if (state->i2c_hdmi) 2884 i2c_unregister_device(state->i2c_hdmi); 2885 if (state->i2c_cp) 2886 i2c_unregister_device(state->i2c_cp); 2887 if (state->i2c_vdp) 2888 i2c_unregister_device(state->i2c_vdp); 2889 2890 state->i2c_avlink = NULL; 2891 state->i2c_cec = NULL; 2892 state->i2c_infoframe = NULL; 2893 state->i2c_sdp_io = NULL; 2894 state->i2c_sdp = NULL; 2895 state->i2c_afe = NULL; 2896 state->i2c_repeater = NULL; 2897 state->i2c_edid = NULL; 2898 state->i2c_hdmi = NULL; 2899 state->i2c_cp = NULL; 2900 state->i2c_vdp = NULL; 2901 } 2902 2903 static struct i2c_client *adv7842_dummy_client(struct v4l2_subdev *sd, const char *desc, 2904 u8 addr, u8 io_reg) 2905 { 2906 struct i2c_client *client = v4l2_get_subdevdata(sd); 2907 struct i2c_client *cp; 2908 2909 io_write(sd, io_reg, addr << 1); 2910 2911 if (addr == 0) { 2912 v4l2_err(sd, "no %s i2c addr configured\n", desc); 2913 return NULL; 2914 } 2915 2916 cp = i2c_new_dummy(client->adapter, io_read(sd, io_reg) >> 1); 2917 if (!cp) 2918 v4l2_err(sd, "register %s on i2c addr 0x%x failed\n", desc, addr); 2919 2920 return cp; 2921 } 2922 2923 static int adv7842_register_clients(struct v4l2_subdev *sd) 2924 { 2925 struct adv7842_state *state = to_state(sd); 2926 struct adv7842_platform_data *pdata = &state->pdata; 2927 2928 state->i2c_avlink = adv7842_dummy_client(sd, "avlink", pdata->i2c_avlink, 0xf3); 2929 state->i2c_cec = adv7842_dummy_client(sd, "cec", pdata->i2c_cec, 0xf4); 2930 state->i2c_infoframe = adv7842_dummy_client(sd, "infoframe", pdata->i2c_infoframe, 0xf5); 2931 state->i2c_sdp_io = adv7842_dummy_client(sd, "sdp_io", pdata->i2c_sdp_io, 0xf2); 2932 state->i2c_sdp = adv7842_dummy_client(sd, "sdp", pdata->i2c_sdp, 0xf1); 2933 state->i2c_afe = adv7842_dummy_client(sd, "afe", pdata->i2c_afe, 0xf8); 2934 state->i2c_repeater = adv7842_dummy_client(sd, "repeater", pdata->i2c_repeater, 0xf9); 2935 state->i2c_edid = adv7842_dummy_client(sd, "edid", pdata->i2c_edid, 0xfa); 2936 state->i2c_hdmi = adv7842_dummy_client(sd, "hdmi", pdata->i2c_hdmi, 0xfb); 2937 state->i2c_cp = adv7842_dummy_client(sd, "cp", pdata->i2c_cp, 0xfd); 2938 state->i2c_vdp = adv7842_dummy_client(sd, "vdp", pdata->i2c_vdp, 0xfe); 2939 2940 if (!state->i2c_avlink || 2941 !state->i2c_cec || 2942 !state->i2c_infoframe || 2943 !state->i2c_sdp_io || 2944 !state->i2c_sdp || 2945 !state->i2c_afe || 2946 !state->i2c_repeater || 2947 !state->i2c_edid || 2948 !state->i2c_hdmi || 2949 !state->i2c_cp || 2950 !state->i2c_vdp) 2951 return -1; 2952 2953 return 0; 2954 } 2955 2956 static int adv7842_probe(struct i2c_client *client, 2957 const struct i2c_device_id *id) 2958 { 2959 struct adv7842_state *state; 2960 static const struct v4l2_dv_timings cea640x480 = 2961 V4L2_DV_BT_CEA_640X480P59_94; 2962 struct adv7842_platform_data *pdata = client->dev.platform_data; 2963 struct v4l2_ctrl_handler *hdl; 2964 struct v4l2_subdev *sd; 2965 u16 rev; 2966 int err; 2967 2968 /* Check if the adapter supports the needed features */ 2969 if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA)) 2970 return -EIO; 2971 2972 v4l_dbg(1, debug, client, "detecting adv7842 client on address 0x%x\n", 2973 client->addr << 1); 2974 2975 if (!pdata) { 2976 v4l_err(client, "No platform data!\n"); 2977 return -ENODEV; 2978 } 2979 2980 state = devm_kzalloc(&client->dev, sizeof(struct adv7842_state), GFP_KERNEL); 2981 if (!state) { 2982 v4l_err(client, "Could not allocate adv7842_state memory!\n"); 2983 return -ENOMEM; 2984 } 2985 2986 /* platform data */ 2987 state->pdata = *pdata; 2988 state->timings = cea640x480; 2989 2990 sd = &state->sd; 2991 v4l2_i2c_subdev_init(sd, client, &adv7842_ops); 2992 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; 2993 state->mode = pdata->mode; 2994 2995 state->hdmi_port_a = pdata->input == ADV7842_SELECT_HDMI_PORT_A; 2996 state->restart_stdi_once = true; 2997 2998 /* i2c access to adv7842? */ 2999 rev = adv_smbus_read_byte_data_check(client, 0xea, false) << 8 | 3000 adv_smbus_read_byte_data_check(client, 0xeb, false); 3001 if (rev != 0x2012) { 3002 v4l2_info(sd, "got rev=0x%04x on first read attempt\n", rev); 3003 rev = adv_smbus_read_byte_data_check(client, 0xea, false) << 8 | 3004 adv_smbus_read_byte_data_check(client, 0xeb, false); 3005 } 3006 if (rev != 0x2012) { 3007 v4l2_info(sd, "not an adv7842 on address 0x%x (rev=0x%04x)\n", 3008 client->addr << 1, rev); 3009 return -ENODEV; 3010 } 3011 3012 if (pdata->chip_reset) 3013 main_reset(sd); 3014 3015 /* control handlers */ 3016 hdl = &state->hdl; 3017 v4l2_ctrl_handler_init(hdl, 6); 3018 3019 /* add in ascending ID order */ 3020 v4l2_ctrl_new_std(hdl, &adv7842_ctrl_ops, 3021 V4L2_CID_BRIGHTNESS, -128, 127, 1, 0); 3022 v4l2_ctrl_new_std(hdl, &adv7842_ctrl_ops, 3023 V4L2_CID_CONTRAST, 0, 255, 1, 128); 3024 v4l2_ctrl_new_std(hdl, &adv7842_ctrl_ops, 3025 V4L2_CID_SATURATION, 0, 255, 1, 128); 3026 v4l2_ctrl_new_std(hdl, &adv7842_ctrl_ops, 3027 V4L2_CID_HUE, 0, 128, 1, 0); 3028 3029 /* custom controls */ 3030 state->detect_tx_5v_ctrl = v4l2_ctrl_new_std(hdl, NULL, 3031 V4L2_CID_DV_RX_POWER_PRESENT, 0, 3, 0, 0); 3032 state->analog_sampling_phase_ctrl = v4l2_ctrl_new_custom(hdl, 3033 &adv7842_ctrl_analog_sampling_phase, NULL); 3034 state->free_run_color_ctrl_manual = v4l2_ctrl_new_custom(hdl, 3035 &adv7842_ctrl_free_run_color_manual, NULL); 3036 state->free_run_color_ctrl = v4l2_ctrl_new_custom(hdl, 3037 &adv7842_ctrl_free_run_color, NULL); 3038 state->rgb_quantization_range_ctrl = 3039 v4l2_ctrl_new_std_menu(hdl, &adv7842_ctrl_ops, 3040 V4L2_CID_DV_RX_RGB_RANGE, V4L2_DV_RGB_RANGE_FULL, 3041 0, V4L2_DV_RGB_RANGE_AUTO); 3042 sd->ctrl_handler = hdl; 3043 if (hdl->error) { 3044 err = hdl->error; 3045 goto err_hdl; 3046 } 3047 state->detect_tx_5v_ctrl->is_private = true; 3048 state->rgb_quantization_range_ctrl->is_private = true; 3049 state->analog_sampling_phase_ctrl->is_private = true; 3050 state->free_run_color_ctrl_manual->is_private = true; 3051 state->free_run_color_ctrl->is_private = true; 3052 3053 if (adv7842_s_detect_tx_5v_ctrl(sd)) { 3054 err = -ENODEV; 3055 goto err_hdl; 3056 } 3057 3058 if (adv7842_register_clients(sd) < 0) { 3059 err = -ENOMEM; 3060 v4l2_err(sd, "failed to create all i2c clients\n"); 3061 goto err_i2c; 3062 } 3063 3064 /* work queues */ 3065 state->work_queues = create_singlethread_workqueue(client->name); 3066 if (!state->work_queues) { 3067 v4l2_err(sd, "Could not create work queue\n"); 3068 err = -ENOMEM; 3069 goto err_i2c; 3070 } 3071 3072 INIT_DELAYED_WORK(&state->delayed_work_enable_hotplug, 3073 adv7842_delayed_work_enable_hotplug); 3074 3075 state->pad.flags = MEDIA_PAD_FL_SOURCE; 3076 err = media_entity_init(&sd->entity, 1, &state->pad, 0); 3077 if (err) 3078 goto err_work_queues; 3079 3080 err = adv7842_core_init(sd); 3081 if (err) 3082 goto err_entity; 3083 3084 v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name, 3085 client->addr << 1, client->adapter->name); 3086 return 0; 3087 3088 err_entity: 3089 media_entity_cleanup(&sd->entity); 3090 err_work_queues: 3091 cancel_delayed_work(&state->delayed_work_enable_hotplug); 3092 destroy_workqueue(state->work_queues); 3093 err_i2c: 3094 adv7842_unregister_clients(sd); 3095 err_hdl: 3096 v4l2_ctrl_handler_free(hdl); 3097 return err; 3098 } 3099 3100 /* ----------------------------------------------------------------------- */ 3101 3102 static int adv7842_remove(struct i2c_client *client) 3103 { 3104 struct v4l2_subdev *sd = i2c_get_clientdata(client); 3105 struct adv7842_state *state = to_state(sd); 3106 3107 adv7842_irq_enable(sd, false); 3108 3109 cancel_delayed_work(&state->delayed_work_enable_hotplug); 3110 destroy_workqueue(state->work_queues); 3111 v4l2_device_unregister_subdev(sd); 3112 media_entity_cleanup(&sd->entity); 3113 adv7842_unregister_clients(sd); 3114 v4l2_ctrl_handler_free(sd->ctrl_handler); 3115 return 0; 3116 } 3117 3118 /* ----------------------------------------------------------------------- */ 3119 3120 static struct i2c_device_id adv7842_id[] = { 3121 { "adv7842", 0 }, 3122 { } 3123 }; 3124 MODULE_DEVICE_TABLE(i2c, adv7842_id); 3125 3126 /* ----------------------------------------------------------------------- */ 3127 3128 static struct i2c_driver adv7842_driver = { 3129 .driver = { 3130 .owner = THIS_MODULE, 3131 .name = "adv7842", 3132 }, 3133 .probe = adv7842_probe, 3134 .remove = adv7842_remove, 3135 .id_table = adv7842_id, 3136 }; 3137 3138 module_i2c_driver(adv7842_driver); 3139