1 /* 2 * adv7842 - Analog Devices ADV7842 video decoder driver 3 * 4 * Copyright 2013 Cisco Systems, Inc. and/or its affiliates. All rights reserved. 5 * 6 * This program is free software; you may redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; version 2 of the License. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 11 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 12 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 13 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 14 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 15 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 16 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 17 * SOFTWARE. 18 * 19 */ 20 21 /* 22 * References (c = chapter, p = page): 23 * REF_01 - Analog devices, ADV7842, 24 * Register Settings Recommendations, Rev. 1.9, April 2011 25 * REF_02 - Analog devices, Software User Guide, UG-206, 26 * ADV7842 I2C Register Maps, Rev. 0, November 2010 27 * REF_03 - Analog devices, Hardware User Guide, UG-214, 28 * ADV7842 Fast Switching 2:1 HDMI 1.4 Receiver with 3D-Comb 29 * Decoder and Digitizer , Rev. 0, January 2011 30 */ 31 32 33 #include <linux/kernel.h> 34 #include <linux/module.h> 35 #include <linux/slab.h> 36 #include <linux/i2c.h> 37 #include <linux/delay.h> 38 #include <linux/videodev2.h> 39 #include <linux/workqueue.h> 40 #include <linux/v4l2-dv-timings.h> 41 #include <media/v4l2-device.h> 42 #include <media/v4l2-ctrls.h> 43 #include <media/v4l2-dv-timings.h> 44 #include <media/adv7842.h> 45 46 static int debug; 47 module_param(debug, int, 0644); 48 MODULE_PARM_DESC(debug, "debug level (0-2)"); 49 50 MODULE_DESCRIPTION("Analog Devices ADV7842 video decoder driver"); 51 MODULE_AUTHOR("Hans Verkuil <hans.verkuil@cisco.com>"); 52 MODULE_AUTHOR("Martin Bugge <marbugge@cisco.com>"); 53 MODULE_LICENSE("GPL"); 54 55 /* ADV7842 system clock frequency */ 56 #define ADV7842_fsc (28636360) 57 58 /* 59 ********************************************************************** 60 * 61 * Arrays with configuration parameters for the ADV7842 62 * 63 ********************************************************************** 64 */ 65 66 struct adv7842_state { 67 struct adv7842_platform_data pdata; 68 struct v4l2_subdev sd; 69 struct media_pad pad; 70 struct v4l2_ctrl_handler hdl; 71 enum adv7842_mode mode; 72 struct v4l2_dv_timings timings; 73 enum adv7842_vid_std_select vid_std_select; 74 v4l2_std_id norm; 75 struct { 76 u8 edid[256]; 77 u32 present; 78 } hdmi_edid; 79 struct { 80 u8 edid[256]; 81 u32 present; 82 } vga_edid; 83 struct v4l2_fract aspect_ratio; 84 u32 rgb_quantization_range; 85 bool is_cea_format; 86 struct workqueue_struct *work_queues; 87 struct delayed_work delayed_work_enable_hotplug; 88 bool restart_stdi_once; 89 bool hdmi_port_a; 90 91 /* i2c clients */ 92 struct i2c_client *i2c_sdp_io; 93 struct i2c_client *i2c_sdp; 94 struct i2c_client *i2c_cp; 95 struct i2c_client *i2c_vdp; 96 struct i2c_client *i2c_afe; 97 struct i2c_client *i2c_hdmi; 98 struct i2c_client *i2c_repeater; 99 struct i2c_client *i2c_edid; 100 struct i2c_client *i2c_infoframe; 101 struct i2c_client *i2c_cec; 102 struct i2c_client *i2c_avlink; 103 104 /* controls */ 105 struct v4l2_ctrl *detect_tx_5v_ctrl; 106 struct v4l2_ctrl *analog_sampling_phase_ctrl; 107 struct v4l2_ctrl *free_run_color_ctrl_manual; 108 struct v4l2_ctrl *free_run_color_ctrl; 109 struct v4l2_ctrl *rgb_quantization_range_ctrl; 110 }; 111 112 /* Unsupported timings. This device cannot support 720p30. */ 113 static const struct v4l2_dv_timings adv7842_timings_exceptions[] = { 114 V4L2_DV_BT_CEA_1280X720P30, 115 { } 116 }; 117 118 static bool adv7842_check_dv_timings(const struct v4l2_dv_timings *t, void *hdl) 119 { 120 int i; 121 122 for (i = 0; adv7842_timings_exceptions[i].bt.width; i++) 123 if (v4l2_match_dv_timings(t, adv7842_timings_exceptions + i, 0)) 124 return false; 125 return true; 126 } 127 128 struct adv7842_video_standards { 129 struct v4l2_dv_timings timings; 130 u8 vid_std; 131 u8 v_freq; 132 }; 133 134 /* sorted by number of lines */ 135 static const struct adv7842_video_standards adv7842_prim_mode_comp[] = { 136 /* { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 }, TODO flickering */ 137 { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 }, 138 { V4L2_DV_BT_CEA_1280X720P50, 0x19, 0x01 }, 139 { V4L2_DV_BT_CEA_1280X720P60, 0x19, 0x00 }, 140 { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 }, 141 { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 }, 142 { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 }, 143 { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 }, 144 { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 }, 145 /* TODO add 1920x1080P60_RB (CVT timing) */ 146 { }, 147 }; 148 149 /* sorted by number of lines */ 150 static const struct adv7842_video_standards adv7842_prim_mode_gr[] = { 151 { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 }, 152 { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 }, 153 { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 }, 154 { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 }, 155 { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 }, 156 { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 }, 157 { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 }, 158 { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 }, 159 { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 }, 160 { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 }, 161 { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 }, 162 { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 }, 163 { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 }, 164 { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 }, 165 { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 }, 166 { V4L2_DV_BT_DMT_1360X768P60, 0x12, 0x00 }, 167 { V4L2_DV_BT_DMT_1366X768P60, 0x13, 0x00 }, 168 { V4L2_DV_BT_DMT_1400X1050P60, 0x14, 0x00 }, 169 { V4L2_DV_BT_DMT_1400X1050P75, 0x15, 0x00 }, 170 { V4L2_DV_BT_DMT_1600X1200P60, 0x16, 0x00 }, /* TODO not tested */ 171 /* TODO add 1600X1200P60_RB (not a DMT timing) */ 172 { V4L2_DV_BT_DMT_1680X1050P60, 0x18, 0x00 }, 173 { V4L2_DV_BT_DMT_1920X1200P60_RB, 0x19, 0x00 }, /* TODO not tested */ 174 { }, 175 }; 176 177 /* sorted by number of lines */ 178 static const struct adv7842_video_standards adv7842_prim_mode_hdmi_comp[] = { 179 { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 }, 180 { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 }, 181 { V4L2_DV_BT_CEA_1280X720P50, 0x13, 0x01 }, 182 { V4L2_DV_BT_CEA_1280X720P60, 0x13, 0x00 }, 183 { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 }, 184 { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 }, 185 { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 }, 186 { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 }, 187 { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 }, 188 { }, 189 }; 190 191 /* sorted by number of lines */ 192 static const struct adv7842_video_standards adv7842_prim_mode_hdmi_gr[] = { 193 { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 }, 194 { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 }, 195 { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 }, 196 { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 }, 197 { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 }, 198 { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 }, 199 { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 }, 200 { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 }, 201 { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 }, 202 { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 }, 203 { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 }, 204 { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 }, 205 { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 }, 206 { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 }, 207 { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 }, 208 { }, 209 }; 210 211 /* ----------------------------------------------------------------------- */ 212 213 static inline struct adv7842_state *to_state(struct v4l2_subdev *sd) 214 { 215 return container_of(sd, struct adv7842_state, sd); 216 } 217 218 static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl) 219 { 220 return &container_of(ctrl->handler, struct adv7842_state, hdl)->sd; 221 } 222 223 static inline unsigned hblanking(const struct v4l2_bt_timings *t) 224 { 225 return V4L2_DV_BT_BLANKING_WIDTH(t); 226 } 227 228 static inline unsigned htotal(const struct v4l2_bt_timings *t) 229 { 230 return V4L2_DV_BT_FRAME_WIDTH(t); 231 } 232 233 static inline unsigned vblanking(const struct v4l2_bt_timings *t) 234 { 235 return V4L2_DV_BT_BLANKING_HEIGHT(t); 236 } 237 238 static inline unsigned vtotal(const struct v4l2_bt_timings *t) 239 { 240 return V4L2_DV_BT_FRAME_HEIGHT(t); 241 } 242 243 244 /* ----------------------------------------------------------------------- */ 245 246 static s32 adv_smbus_read_byte_data_check(struct i2c_client *client, 247 u8 command, bool check) 248 { 249 union i2c_smbus_data data; 250 251 if (!i2c_smbus_xfer(client->adapter, client->addr, client->flags, 252 I2C_SMBUS_READ, command, 253 I2C_SMBUS_BYTE_DATA, &data)) 254 return data.byte; 255 if (check) 256 v4l_err(client, "error reading %02x, %02x\n", 257 client->addr, command); 258 return -EIO; 259 } 260 261 static s32 adv_smbus_read_byte_data(struct i2c_client *client, u8 command) 262 { 263 int i; 264 265 for (i = 0; i < 3; i++) { 266 int ret = adv_smbus_read_byte_data_check(client, command, true); 267 268 if (ret >= 0) { 269 if (i) 270 v4l_err(client, "read ok after %d retries\n", i); 271 return ret; 272 } 273 } 274 v4l_err(client, "read failed\n"); 275 return -EIO; 276 } 277 278 static s32 adv_smbus_write_byte_data(struct i2c_client *client, 279 u8 command, u8 value) 280 { 281 union i2c_smbus_data data; 282 int err; 283 int i; 284 285 data.byte = value; 286 for (i = 0; i < 3; i++) { 287 err = i2c_smbus_xfer(client->adapter, client->addr, 288 client->flags, 289 I2C_SMBUS_WRITE, command, 290 I2C_SMBUS_BYTE_DATA, &data); 291 if (!err) 292 break; 293 } 294 if (err < 0) 295 v4l_err(client, "error writing %02x, %02x, %02x\n", 296 client->addr, command, value); 297 return err; 298 } 299 300 static void adv_smbus_write_byte_no_check(struct i2c_client *client, 301 u8 command, u8 value) 302 { 303 union i2c_smbus_data data; 304 data.byte = value; 305 306 i2c_smbus_xfer(client->adapter, client->addr, 307 client->flags, 308 I2C_SMBUS_WRITE, command, 309 I2C_SMBUS_BYTE_DATA, &data); 310 } 311 312 static s32 adv_smbus_write_i2c_block_data(struct i2c_client *client, 313 u8 command, unsigned length, const u8 *values) 314 { 315 union i2c_smbus_data data; 316 317 if (length > I2C_SMBUS_BLOCK_MAX) 318 length = I2C_SMBUS_BLOCK_MAX; 319 data.block[0] = length; 320 memcpy(data.block + 1, values, length); 321 return i2c_smbus_xfer(client->adapter, client->addr, client->flags, 322 I2C_SMBUS_WRITE, command, 323 I2C_SMBUS_I2C_BLOCK_DATA, &data); 324 } 325 326 /* ----------------------------------------------------------------------- */ 327 328 static inline int io_read(struct v4l2_subdev *sd, u8 reg) 329 { 330 struct i2c_client *client = v4l2_get_subdevdata(sd); 331 332 return adv_smbus_read_byte_data(client, reg); 333 } 334 335 static inline int io_write(struct v4l2_subdev *sd, u8 reg, u8 val) 336 { 337 struct i2c_client *client = v4l2_get_subdevdata(sd); 338 339 return adv_smbus_write_byte_data(client, reg, val); 340 } 341 342 static inline int io_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) 343 { 344 return io_write(sd, reg, (io_read(sd, reg) & mask) | val); 345 } 346 347 static inline int avlink_read(struct v4l2_subdev *sd, u8 reg) 348 { 349 struct adv7842_state *state = to_state(sd); 350 351 return adv_smbus_read_byte_data(state->i2c_avlink, reg); 352 } 353 354 static inline int avlink_write(struct v4l2_subdev *sd, u8 reg, u8 val) 355 { 356 struct adv7842_state *state = to_state(sd); 357 358 return adv_smbus_write_byte_data(state->i2c_avlink, reg, val); 359 } 360 361 static inline int cec_read(struct v4l2_subdev *sd, u8 reg) 362 { 363 struct adv7842_state *state = to_state(sd); 364 365 return adv_smbus_read_byte_data(state->i2c_cec, reg); 366 } 367 368 static inline int cec_write(struct v4l2_subdev *sd, u8 reg, u8 val) 369 { 370 struct adv7842_state *state = to_state(sd); 371 372 return adv_smbus_write_byte_data(state->i2c_cec, reg, val); 373 } 374 375 static inline int cec_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) 376 { 377 return cec_write(sd, reg, (cec_read(sd, reg) & mask) | val); 378 } 379 380 static inline int infoframe_read(struct v4l2_subdev *sd, u8 reg) 381 { 382 struct adv7842_state *state = to_state(sd); 383 384 return adv_smbus_read_byte_data(state->i2c_infoframe, reg); 385 } 386 387 static inline int infoframe_write(struct v4l2_subdev *sd, u8 reg, u8 val) 388 { 389 struct adv7842_state *state = to_state(sd); 390 391 return adv_smbus_write_byte_data(state->i2c_infoframe, reg, val); 392 } 393 394 static inline int sdp_io_read(struct v4l2_subdev *sd, u8 reg) 395 { 396 struct adv7842_state *state = to_state(sd); 397 398 return adv_smbus_read_byte_data(state->i2c_sdp_io, reg); 399 } 400 401 static inline int sdp_io_write(struct v4l2_subdev *sd, u8 reg, u8 val) 402 { 403 struct adv7842_state *state = to_state(sd); 404 405 return adv_smbus_write_byte_data(state->i2c_sdp_io, reg, val); 406 } 407 408 static inline int sdp_io_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) 409 { 410 return sdp_io_write(sd, reg, (sdp_io_read(sd, reg) & mask) | val); 411 } 412 413 static inline int sdp_read(struct v4l2_subdev *sd, u8 reg) 414 { 415 struct adv7842_state *state = to_state(sd); 416 417 return adv_smbus_read_byte_data(state->i2c_sdp, reg); 418 } 419 420 static inline int sdp_write(struct v4l2_subdev *sd, u8 reg, u8 val) 421 { 422 struct adv7842_state *state = to_state(sd); 423 424 return adv_smbus_write_byte_data(state->i2c_sdp, reg, val); 425 } 426 427 static inline int sdp_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) 428 { 429 return sdp_write(sd, reg, (sdp_read(sd, reg) & mask) | val); 430 } 431 432 static inline int afe_read(struct v4l2_subdev *sd, u8 reg) 433 { 434 struct adv7842_state *state = to_state(sd); 435 436 return adv_smbus_read_byte_data(state->i2c_afe, reg); 437 } 438 439 static inline int afe_write(struct v4l2_subdev *sd, u8 reg, u8 val) 440 { 441 struct adv7842_state *state = to_state(sd); 442 443 return adv_smbus_write_byte_data(state->i2c_afe, reg, val); 444 } 445 446 static inline int afe_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) 447 { 448 return afe_write(sd, reg, (afe_read(sd, reg) & mask) | val); 449 } 450 451 static inline int rep_read(struct v4l2_subdev *sd, u8 reg) 452 { 453 struct adv7842_state *state = to_state(sd); 454 455 return adv_smbus_read_byte_data(state->i2c_repeater, reg); 456 } 457 458 static inline int rep_write(struct v4l2_subdev *sd, u8 reg, u8 val) 459 { 460 struct adv7842_state *state = to_state(sd); 461 462 return adv_smbus_write_byte_data(state->i2c_repeater, reg, val); 463 } 464 465 static inline int rep_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) 466 { 467 return rep_write(sd, reg, (rep_read(sd, reg) & mask) | val); 468 } 469 470 static inline int edid_read(struct v4l2_subdev *sd, u8 reg) 471 { 472 struct adv7842_state *state = to_state(sd); 473 474 return adv_smbus_read_byte_data(state->i2c_edid, reg); 475 } 476 477 static inline int edid_write(struct v4l2_subdev *sd, u8 reg, u8 val) 478 { 479 struct adv7842_state *state = to_state(sd); 480 481 return adv_smbus_write_byte_data(state->i2c_edid, reg, val); 482 } 483 484 static inline int hdmi_read(struct v4l2_subdev *sd, u8 reg) 485 { 486 struct adv7842_state *state = to_state(sd); 487 488 return adv_smbus_read_byte_data(state->i2c_hdmi, reg); 489 } 490 491 static inline int hdmi_write(struct v4l2_subdev *sd, u8 reg, u8 val) 492 { 493 struct adv7842_state *state = to_state(sd); 494 495 return adv_smbus_write_byte_data(state->i2c_hdmi, reg, val); 496 } 497 498 static inline int hdmi_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) 499 { 500 return hdmi_write(sd, reg, (hdmi_read(sd, reg) & mask) | val); 501 } 502 503 static inline int cp_read(struct v4l2_subdev *sd, u8 reg) 504 { 505 struct adv7842_state *state = to_state(sd); 506 507 return adv_smbus_read_byte_data(state->i2c_cp, reg); 508 } 509 510 static inline int cp_write(struct v4l2_subdev *sd, u8 reg, u8 val) 511 { 512 struct adv7842_state *state = to_state(sd); 513 514 return adv_smbus_write_byte_data(state->i2c_cp, reg, val); 515 } 516 517 static inline int cp_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) 518 { 519 return cp_write(sd, reg, (cp_read(sd, reg) & mask) | val); 520 } 521 522 static inline int vdp_read(struct v4l2_subdev *sd, u8 reg) 523 { 524 struct adv7842_state *state = to_state(sd); 525 526 return adv_smbus_read_byte_data(state->i2c_vdp, reg); 527 } 528 529 static inline int vdp_write(struct v4l2_subdev *sd, u8 reg, u8 val) 530 { 531 struct adv7842_state *state = to_state(sd); 532 533 return adv_smbus_write_byte_data(state->i2c_vdp, reg, val); 534 } 535 536 static void main_reset(struct v4l2_subdev *sd) 537 { 538 struct i2c_client *client = v4l2_get_subdevdata(sd); 539 540 v4l2_dbg(1, debug, sd, "%s:\n", __func__); 541 542 adv_smbus_write_byte_no_check(client, 0xff, 0x80); 543 544 mdelay(5); 545 } 546 547 /* ----------------------------------------------------------------------- */ 548 549 static inline bool is_digital_input(struct v4l2_subdev *sd) 550 { 551 struct adv7842_state *state = to_state(sd); 552 553 return state->mode == ADV7842_MODE_HDMI; 554 } 555 556 static const struct v4l2_dv_timings_cap adv7842_timings_cap_analog = { 557 .type = V4L2_DV_BT_656_1120, 558 /* keep this initialization for compatibility with GCC < 4.4.6 */ 559 .reserved = { 0 }, 560 V4L2_INIT_BT_TIMINGS(0, 1920, 0, 1200, 25000000, 170000000, 561 V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT | 562 V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT, 563 V4L2_DV_BT_CAP_PROGRESSIVE | V4L2_DV_BT_CAP_REDUCED_BLANKING | 564 V4L2_DV_BT_CAP_CUSTOM) 565 }; 566 567 static const struct v4l2_dv_timings_cap adv7842_timings_cap_digital = { 568 .type = V4L2_DV_BT_656_1120, 569 /* keep this initialization for compatibility with GCC < 4.4.6 */ 570 .reserved = { 0 }, 571 V4L2_INIT_BT_TIMINGS(0, 1920, 0, 1200, 25000000, 225000000, 572 V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT | 573 V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT, 574 V4L2_DV_BT_CAP_PROGRESSIVE | V4L2_DV_BT_CAP_REDUCED_BLANKING | 575 V4L2_DV_BT_CAP_CUSTOM) 576 }; 577 578 static inline const struct v4l2_dv_timings_cap * 579 adv7842_get_dv_timings_cap(struct v4l2_subdev *sd) 580 { 581 return is_digital_input(sd) ? &adv7842_timings_cap_digital : 582 &adv7842_timings_cap_analog; 583 } 584 585 /* ----------------------------------------------------------------------- */ 586 587 static void adv7842_delayed_work_enable_hotplug(struct work_struct *work) 588 { 589 struct delayed_work *dwork = to_delayed_work(work); 590 struct adv7842_state *state = container_of(dwork, 591 struct adv7842_state, delayed_work_enable_hotplug); 592 struct v4l2_subdev *sd = &state->sd; 593 int present = state->hdmi_edid.present; 594 u8 mask = 0; 595 596 v4l2_dbg(2, debug, sd, "%s: enable hotplug on ports: 0x%x\n", 597 __func__, present); 598 599 if (present & (0x04 << ADV7842_EDID_PORT_A)) 600 mask |= 0x20; 601 if (present & (0x04 << ADV7842_EDID_PORT_B)) 602 mask |= 0x10; 603 io_write_and_or(sd, 0x20, 0xcf, mask); 604 } 605 606 static int edid_write_vga_segment(struct v4l2_subdev *sd) 607 { 608 struct i2c_client *client = v4l2_get_subdevdata(sd); 609 struct adv7842_state *state = to_state(sd); 610 const u8 *val = state->vga_edid.edid; 611 int err = 0; 612 int i; 613 614 v4l2_dbg(2, debug, sd, "%s: write EDID on VGA port\n", __func__); 615 616 /* HPA disable on port A and B */ 617 io_write_and_or(sd, 0x20, 0xcf, 0x00); 618 619 /* Disable I2C access to internal EDID ram from VGA DDC port */ 620 rep_write_and_or(sd, 0x7f, 0x7f, 0x00); 621 622 /* edid segment pointer '1' for VGA port */ 623 rep_write_and_or(sd, 0x77, 0xef, 0x10); 624 625 for (i = 0; !err && i < 256; i += I2C_SMBUS_BLOCK_MAX) 626 err = adv_smbus_write_i2c_block_data(state->i2c_edid, i, 627 I2C_SMBUS_BLOCK_MAX, val + i); 628 if (err) 629 return err; 630 631 /* Calculates the checksums and enables I2C access 632 * to internal EDID ram from VGA DDC port. 633 */ 634 rep_write_and_or(sd, 0x7f, 0x7f, 0x80); 635 636 for (i = 0; i < 1000; i++) { 637 if (rep_read(sd, 0x79) & 0x20) 638 break; 639 mdelay(1); 640 } 641 if (i == 1000) { 642 v4l_err(client, "error enabling edid on VGA port\n"); 643 return -EIO; 644 } 645 646 /* enable hotplug after 200 ms */ 647 queue_delayed_work(state->work_queues, 648 &state->delayed_work_enable_hotplug, HZ / 5); 649 650 return 0; 651 } 652 653 static int edid_spa_location(const u8 *edid) 654 { 655 u8 d; 656 657 /* 658 * TODO, improve and update for other CEA extensions 659 * currently only for 1 segment (256 bytes), 660 * i.e. 1 extension block and CEA revision 3. 661 */ 662 if ((edid[0x7e] != 1) || 663 (edid[0x80] != 0x02) || 664 (edid[0x81] != 0x03)) { 665 return -EINVAL; 666 } 667 /* 668 * search Vendor Specific Data Block (tag 3) 669 */ 670 d = edid[0x82] & 0x7f; 671 if (d > 4) { 672 int i = 0x84; 673 int end = 0x80 + d; 674 do { 675 u8 tag = edid[i]>>5; 676 u8 len = edid[i] & 0x1f; 677 678 if ((tag == 3) && (len >= 5)) 679 return i + 4; 680 i += len + 1; 681 } while (i < end); 682 } 683 return -EINVAL; 684 } 685 686 static int edid_write_hdmi_segment(struct v4l2_subdev *sd, u8 port) 687 { 688 struct i2c_client *client = v4l2_get_subdevdata(sd); 689 struct adv7842_state *state = to_state(sd); 690 const u8 *val = state->hdmi_edid.edid; 691 int spa_loc = edid_spa_location(val); 692 int err = 0; 693 int i; 694 695 v4l2_dbg(2, debug, sd, "%s: write EDID on port %c (spa at 0x%x)\n", 696 __func__, (port == ADV7842_EDID_PORT_A) ? 'A' : 'B', spa_loc); 697 698 /* HPA disable on port A and B */ 699 io_write_and_or(sd, 0x20, 0xcf, 0x00); 700 701 /* Disable I2C access to internal EDID ram from HDMI DDC ports */ 702 rep_write_and_or(sd, 0x77, 0xf3, 0x00); 703 704 if (!state->hdmi_edid.present) 705 return 0; 706 707 /* edid segment pointer '0' for HDMI ports */ 708 rep_write_and_or(sd, 0x77, 0xef, 0x00); 709 710 for (i = 0; !err && i < 256; i += I2C_SMBUS_BLOCK_MAX) 711 err = adv_smbus_write_i2c_block_data(state->i2c_edid, i, 712 I2C_SMBUS_BLOCK_MAX, val + i); 713 if (err) 714 return err; 715 716 if (spa_loc < 0) 717 spa_loc = 0xc0; /* Default value [REF_02, p. 199] */ 718 719 if (port == ADV7842_EDID_PORT_A) { 720 rep_write(sd, 0x72, val[spa_loc]); 721 rep_write(sd, 0x73, val[spa_loc + 1]); 722 } else { 723 rep_write(sd, 0x74, val[spa_loc]); 724 rep_write(sd, 0x75, val[spa_loc + 1]); 725 } 726 rep_write(sd, 0x76, spa_loc & 0xff); 727 rep_write_and_or(sd, 0x77, 0xbf, (spa_loc >> 2) & 0x40); 728 729 /* Calculates the checksums and enables I2C access to internal 730 * EDID ram from HDMI DDC ports 731 */ 732 rep_write_and_or(sd, 0x77, 0xf3, state->hdmi_edid.present); 733 734 for (i = 0; i < 1000; i++) { 735 if (rep_read(sd, 0x7d) & state->hdmi_edid.present) 736 break; 737 mdelay(1); 738 } 739 if (i == 1000) { 740 v4l_err(client, "error enabling edid on port %c\n", 741 (port == ADV7842_EDID_PORT_A) ? 'A' : 'B'); 742 return -EIO; 743 } 744 745 /* enable hotplug after 200 ms */ 746 queue_delayed_work(state->work_queues, 747 &state->delayed_work_enable_hotplug, HZ / 5); 748 749 return 0; 750 } 751 752 /* ----------------------------------------------------------------------- */ 753 754 #ifdef CONFIG_VIDEO_ADV_DEBUG 755 static void adv7842_inv_register(struct v4l2_subdev *sd) 756 { 757 v4l2_info(sd, "0x000-0x0ff: IO Map\n"); 758 v4l2_info(sd, "0x100-0x1ff: AVLink Map\n"); 759 v4l2_info(sd, "0x200-0x2ff: CEC Map\n"); 760 v4l2_info(sd, "0x300-0x3ff: InfoFrame Map\n"); 761 v4l2_info(sd, "0x400-0x4ff: SDP_IO Map\n"); 762 v4l2_info(sd, "0x500-0x5ff: SDP Map\n"); 763 v4l2_info(sd, "0x600-0x6ff: AFE Map\n"); 764 v4l2_info(sd, "0x700-0x7ff: Repeater Map\n"); 765 v4l2_info(sd, "0x800-0x8ff: EDID Map\n"); 766 v4l2_info(sd, "0x900-0x9ff: HDMI Map\n"); 767 v4l2_info(sd, "0xa00-0xaff: CP Map\n"); 768 v4l2_info(sd, "0xb00-0xbff: VDP Map\n"); 769 } 770 771 static int adv7842_g_register(struct v4l2_subdev *sd, 772 struct v4l2_dbg_register *reg) 773 { 774 reg->size = 1; 775 switch (reg->reg >> 8) { 776 case 0: 777 reg->val = io_read(sd, reg->reg & 0xff); 778 break; 779 case 1: 780 reg->val = avlink_read(sd, reg->reg & 0xff); 781 break; 782 case 2: 783 reg->val = cec_read(sd, reg->reg & 0xff); 784 break; 785 case 3: 786 reg->val = infoframe_read(sd, reg->reg & 0xff); 787 break; 788 case 4: 789 reg->val = sdp_io_read(sd, reg->reg & 0xff); 790 break; 791 case 5: 792 reg->val = sdp_read(sd, reg->reg & 0xff); 793 break; 794 case 6: 795 reg->val = afe_read(sd, reg->reg & 0xff); 796 break; 797 case 7: 798 reg->val = rep_read(sd, reg->reg & 0xff); 799 break; 800 case 8: 801 reg->val = edid_read(sd, reg->reg & 0xff); 802 break; 803 case 9: 804 reg->val = hdmi_read(sd, reg->reg & 0xff); 805 break; 806 case 0xa: 807 reg->val = cp_read(sd, reg->reg & 0xff); 808 break; 809 case 0xb: 810 reg->val = vdp_read(sd, reg->reg & 0xff); 811 break; 812 default: 813 v4l2_info(sd, "Register %03llx not supported\n", reg->reg); 814 adv7842_inv_register(sd); 815 break; 816 } 817 return 0; 818 } 819 820 static int adv7842_s_register(struct v4l2_subdev *sd, 821 const struct v4l2_dbg_register *reg) 822 { 823 u8 val = reg->val & 0xff; 824 825 switch (reg->reg >> 8) { 826 case 0: 827 io_write(sd, reg->reg & 0xff, val); 828 break; 829 case 1: 830 avlink_write(sd, reg->reg & 0xff, val); 831 break; 832 case 2: 833 cec_write(sd, reg->reg & 0xff, val); 834 break; 835 case 3: 836 infoframe_write(sd, reg->reg & 0xff, val); 837 break; 838 case 4: 839 sdp_io_write(sd, reg->reg & 0xff, val); 840 break; 841 case 5: 842 sdp_write(sd, reg->reg & 0xff, val); 843 break; 844 case 6: 845 afe_write(sd, reg->reg & 0xff, val); 846 break; 847 case 7: 848 rep_write(sd, reg->reg & 0xff, val); 849 break; 850 case 8: 851 edid_write(sd, reg->reg & 0xff, val); 852 break; 853 case 9: 854 hdmi_write(sd, reg->reg & 0xff, val); 855 break; 856 case 0xa: 857 cp_write(sd, reg->reg & 0xff, val); 858 break; 859 case 0xb: 860 vdp_write(sd, reg->reg & 0xff, val); 861 break; 862 default: 863 v4l2_info(sd, "Register %03llx not supported\n", reg->reg); 864 adv7842_inv_register(sd); 865 break; 866 } 867 return 0; 868 } 869 #endif 870 871 static int adv7842_s_detect_tx_5v_ctrl(struct v4l2_subdev *sd) 872 { 873 struct adv7842_state *state = to_state(sd); 874 int prev = v4l2_ctrl_g_ctrl(state->detect_tx_5v_ctrl); 875 u8 reg_io_6f = io_read(sd, 0x6f); 876 int val = 0; 877 878 if (reg_io_6f & 0x02) 879 val |= 1; /* port A */ 880 if (reg_io_6f & 0x01) 881 val |= 2; /* port B */ 882 883 v4l2_dbg(1, debug, sd, "%s: 0x%x -> 0x%x\n", __func__, prev, val); 884 885 if (val != prev) 886 return v4l2_ctrl_s_ctrl(state->detect_tx_5v_ctrl, val); 887 return 0; 888 } 889 890 static int find_and_set_predefined_video_timings(struct v4l2_subdev *sd, 891 u8 prim_mode, 892 const struct adv7842_video_standards *predef_vid_timings, 893 const struct v4l2_dv_timings *timings) 894 { 895 int i; 896 897 for (i = 0; predef_vid_timings[i].timings.bt.width; i++) { 898 if (!v4l2_match_dv_timings(timings, &predef_vid_timings[i].timings, 899 is_digital_input(sd) ? 250000 : 1000000)) 900 continue; 901 /* video std */ 902 io_write(sd, 0x00, predef_vid_timings[i].vid_std); 903 /* v_freq and prim mode */ 904 io_write(sd, 0x01, (predef_vid_timings[i].v_freq << 4) + prim_mode); 905 return 0; 906 } 907 908 return -1; 909 } 910 911 static int configure_predefined_video_timings(struct v4l2_subdev *sd, 912 struct v4l2_dv_timings *timings) 913 { 914 struct adv7842_state *state = to_state(sd); 915 int err; 916 917 v4l2_dbg(1, debug, sd, "%s\n", __func__); 918 919 /* reset to default values */ 920 io_write(sd, 0x16, 0x43); 921 io_write(sd, 0x17, 0x5a); 922 /* disable embedded syncs for auto graphics mode */ 923 cp_write_and_or(sd, 0x81, 0xef, 0x00); 924 cp_write(sd, 0x26, 0x00); 925 cp_write(sd, 0x27, 0x00); 926 cp_write(sd, 0x28, 0x00); 927 cp_write(sd, 0x29, 0x00); 928 cp_write(sd, 0x8f, 0x40); 929 cp_write(sd, 0x90, 0x00); 930 cp_write(sd, 0xa5, 0x00); 931 cp_write(sd, 0xa6, 0x00); 932 cp_write(sd, 0xa7, 0x00); 933 cp_write(sd, 0xab, 0x00); 934 cp_write(sd, 0xac, 0x00); 935 936 switch (state->mode) { 937 case ADV7842_MODE_COMP: 938 case ADV7842_MODE_RGB: 939 err = find_and_set_predefined_video_timings(sd, 940 0x01, adv7842_prim_mode_comp, timings); 941 if (err) 942 err = find_and_set_predefined_video_timings(sd, 943 0x02, adv7842_prim_mode_gr, timings); 944 break; 945 case ADV7842_MODE_HDMI: 946 err = find_and_set_predefined_video_timings(sd, 947 0x05, adv7842_prim_mode_hdmi_comp, timings); 948 if (err) 949 err = find_and_set_predefined_video_timings(sd, 950 0x06, adv7842_prim_mode_hdmi_gr, timings); 951 break; 952 default: 953 v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n", 954 __func__, state->mode); 955 err = -1; 956 break; 957 } 958 959 960 return err; 961 } 962 963 static void configure_custom_video_timings(struct v4l2_subdev *sd, 964 const struct v4l2_bt_timings *bt) 965 { 966 struct adv7842_state *state = to_state(sd); 967 struct i2c_client *client = v4l2_get_subdevdata(sd); 968 u32 width = htotal(bt); 969 u32 height = vtotal(bt); 970 u16 cp_start_sav = bt->hsync + bt->hbackporch - 4; 971 u16 cp_start_eav = width - bt->hfrontporch; 972 u16 cp_start_vbi = height - bt->vfrontporch + 1; 973 u16 cp_end_vbi = bt->vsync + bt->vbackporch + 1; 974 u16 ch1_fr_ll = (((u32)bt->pixelclock / 100) > 0) ? 975 ((width * (ADV7842_fsc / 100)) / ((u32)bt->pixelclock / 100)) : 0; 976 const u8 pll[2] = { 977 0xc0 | ((width >> 8) & 0x1f), 978 width & 0xff 979 }; 980 981 v4l2_dbg(2, debug, sd, "%s\n", __func__); 982 983 switch (state->mode) { 984 case ADV7842_MODE_COMP: 985 case ADV7842_MODE_RGB: 986 /* auto graphics */ 987 io_write(sd, 0x00, 0x07); /* video std */ 988 io_write(sd, 0x01, 0x02); /* prim mode */ 989 /* enable embedded syncs for auto graphics mode */ 990 cp_write_and_or(sd, 0x81, 0xef, 0x10); 991 992 /* Should only be set in auto-graphics mode [REF_02, p. 91-92] */ 993 /* setup PLL_DIV_MAN_EN and PLL_DIV_RATIO */ 994 /* IO-map reg. 0x16 and 0x17 should be written in sequence */ 995 if (adv_smbus_write_i2c_block_data(client, 0x16, 2, pll)) { 996 v4l2_err(sd, "writing to reg 0x16 and 0x17 failed\n"); 997 break; 998 } 999 1000 /* active video - horizontal timing */ 1001 cp_write(sd, 0x26, (cp_start_sav >> 8) & 0xf); 1002 cp_write(sd, 0x27, (cp_start_sav & 0xff)); 1003 cp_write(sd, 0x28, (cp_start_eav >> 8) & 0xf); 1004 cp_write(sd, 0x29, (cp_start_eav & 0xff)); 1005 1006 /* active video - vertical timing */ 1007 cp_write(sd, 0xa5, (cp_start_vbi >> 4) & 0xff); 1008 cp_write(sd, 0xa6, ((cp_start_vbi & 0xf) << 4) | 1009 ((cp_end_vbi >> 8) & 0xf)); 1010 cp_write(sd, 0xa7, cp_end_vbi & 0xff); 1011 break; 1012 case ADV7842_MODE_HDMI: 1013 /* set default prim_mode/vid_std for HDMI 1014 according to [REF_03, c. 4.2] */ 1015 io_write(sd, 0x00, 0x02); /* video std */ 1016 io_write(sd, 0x01, 0x06); /* prim mode */ 1017 break; 1018 default: 1019 v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n", 1020 __func__, state->mode); 1021 break; 1022 } 1023 1024 cp_write(sd, 0x8f, (ch1_fr_ll >> 8) & 0x7); 1025 cp_write(sd, 0x90, ch1_fr_ll & 0xff); 1026 cp_write(sd, 0xab, (height >> 4) & 0xff); 1027 cp_write(sd, 0xac, (height & 0x0f) << 4); 1028 } 1029 1030 static void set_rgb_quantization_range(struct v4l2_subdev *sd) 1031 { 1032 struct adv7842_state *state = to_state(sd); 1033 1034 v4l2_dbg(2, debug, sd, "%s: rgb_quantization_range = %d\n", 1035 __func__, state->rgb_quantization_range); 1036 1037 switch (state->rgb_quantization_range) { 1038 case V4L2_DV_RGB_RANGE_AUTO: 1039 if (state->mode == ADV7842_MODE_RGB) { 1040 /* Receiving analog RGB signal 1041 * Set RGB full range (0-255) */ 1042 io_write_and_or(sd, 0x02, 0x0f, 0x10); 1043 break; 1044 } 1045 1046 if (state->mode == ADV7842_MODE_COMP) { 1047 /* Receiving analog YPbPr signal 1048 * Set automode */ 1049 io_write_and_or(sd, 0x02, 0x0f, 0xf0); 1050 break; 1051 } 1052 1053 if (hdmi_read(sd, 0x05) & 0x80) { 1054 /* Receiving HDMI signal 1055 * Set automode */ 1056 io_write_and_or(sd, 0x02, 0x0f, 0xf0); 1057 break; 1058 } 1059 1060 /* Receiving DVI-D signal 1061 * ADV7842 selects RGB limited range regardless of 1062 * input format (CE/IT) in automatic mode */ 1063 if (state->timings.bt.standards & V4L2_DV_BT_STD_CEA861) { 1064 /* RGB limited range (16-235) */ 1065 io_write_and_or(sd, 0x02, 0x0f, 0x00); 1066 } else { 1067 /* RGB full range (0-255) */ 1068 io_write_and_or(sd, 0x02, 0x0f, 0x10); 1069 } 1070 break; 1071 case V4L2_DV_RGB_RANGE_LIMITED: 1072 if (state->mode == ADV7842_MODE_COMP) { 1073 /* YCrCb limited range (16-235) */ 1074 io_write_and_or(sd, 0x02, 0x0f, 0x20); 1075 } else { 1076 /* RGB limited range (16-235) */ 1077 io_write_and_or(sd, 0x02, 0x0f, 0x00); 1078 } 1079 break; 1080 case V4L2_DV_RGB_RANGE_FULL: 1081 if (state->mode == ADV7842_MODE_COMP) { 1082 /* YCrCb full range (0-255) */ 1083 io_write_and_or(sd, 0x02, 0x0f, 0x60); 1084 } else { 1085 /* RGB full range (0-255) */ 1086 io_write_and_or(sd, 0x02, 0x0f, 0x10); 1087 } 1088 break; 1089 } 1090 } 1091 1092 static int adv7842_s_ctrl(struct v4l2_ctrl *ctrl) 1093 { 1094 struct v4l2_subdev *sd = to_sd(ctrl); 1095 struct adv7842_state *state = to_state(sd); 1096 1097 /* TODO SDP ctrls 1098 contrast/brightness/hue/free run is acting a bit strange, 1099 not sure if sdp csc is correct. 1100 */ 1101 switch (ctrl->id) { 1102 /* standard ctrls */ 1103 case V4L2_CID_BRIGHTNESS: 1104 cp_write(sd, 0x3c, ctrl->val); 1105 sdp_write(sd, 0x14, ctrl->val); 1106 /* ignore lsb sdp 0x17[3:2] */ 1107 return 0; 1108 case V4L2_CID_CONTRAST: 1109 cp_write(sd, 0x3a, ctrl->val); 1110 sdp_write(sd, 0x13, ctrl->val); 1111 /* ignore lsb sdp 0x17[1:0] */ 1112 return 0; 1113 case V4L2_CID_SATURATION: 1114 cp_write(sd, 0x3b, ctrl->val); 1115 sdp_write(sd, 0x15, ctrl->val); 1116 /* ignore lsb sdp 0x17[5:4] */ 1117 return 0; 1118 case V4L2_CID_HUE: 1119 cp_write(sd, 0x3d, ctrl->val); 1120 sdp_write(sd, 0x16, ctrl->val); 1121 /* ignore lsb sdp 0x17[7:6] */ 1122 return 0; 1123 /* custom ctrls */ 1124 case V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE: 1125 afe_write(sd, 0xc8, ctrl->val); 1126 return 0; 1127 case V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL: 1128 cp_write_and_or(sd, 0xbf, ~0x04, (ctrl->val << 2)); 1129 sdp_write_and_or(sd, 0xdd, ~0x04, (ctrl->val << 2)); 1130 return 0; 1131 case V4L2_CID_ADV_RX_FREE_RUN_COLOR: { 1132 u8 R = (ctrl->val & 0xff0000) >> 16; 1133 u8 G = (ctrl->val & 0x00ff00) >> 8; 1134 u8 B = (ctrl->val & 0x0000ff); 1135 /* RGB -> YUV, numerical approximation */ 1136 int Y = 66 * R + 129 * G + 25 * B; 1137 int U = -38 * R - 74 * G + 112 * B; 1138 int V = 112 * R - 94 * G - 18 * B; 1139 1140 /* Scale down to 8 bits with rounding */ 1141 Y = (Y + 128) >> 8; 1142 U = (U + 128) >> 8; 1143 V = (V + 128) >> 8; 1144 /* make U,V positive */ 1145 Y += 16; 1146 U += 128; 1147 V += 128; 1148 1149 v4l2_dbg(1, debug, sd, "R %x, G %x, B %x\n", R, G, B); 1150 v4l2_dbg(1, debug, sd, "Y %x, U %x, V %x\n", Y, U, V); 1151 1152 /* CP */ 1153 cp_write(sd, 0xc1, R); 1154 cp_write(sd, 0xc0, G); 1155 cp_write(sd, 0xc2, B); 1156 /* SDP */ 1157 sdp_write(sd, 0xde, Y); 1158 sdp_write(sd, 0xdf, (V & 0xf0) | ((U >> 4) & 0x0f)); 1159 return 0; 1160 } 1161 case V4L2_CID_DV_RX_RGB_RANGE: 1162 state->rgb_quantization_range = ctrl->val; 1163 set_rgb_quantization_range(sd); 1164 return 0; 1165 } 1166 return -EINVAL; 1167 } 1168 1169 static inline bool no_power(struct v4l2_subdev *sd) 1170 { 1171 return io_read(sd, 0x0c) & 0x24; 1172 } 1173 1174 static inline bool no_cp_signal(struct v4l2_subdev *sd) 1175 { 1176 return ((cp_read(sd, 0xb5) & 0xd0) != 0xd0) || !(cp_read(sd, 0xb1) & 0x80); 1177 } 1178 1179 static inline bool is_hdmi(struct v4l2_subdev *sd) 1180 { 1181 return hdmi_read(sd, 0x05) & 0x80; 1182 } 1183 1184 static int adv7842_g_input_status(struct v4l2_subdev *sd, u32 *status) 1185 { 1186 struct adv7842_state *state = to_state(sd); 1187 1188 *status = 0; 1189 1190 if (io_read(sd, 0x0c) & 0x24) 1191 *status |= V4L2_IN_ST_NO_POWER; 1192 1193 if (state->mode == ADV7842_MODE_SDP) { 1194 /* status from SDP block */ 1195 if (!(sdp_read(sd, 0x5A) & 0x01)) 1196 *status |= V4L2_IN_ST_NO_SIGNAL; 1197 1198 v4l2_dbg(1, debug, sd, "%s: SDP status = 0x%x\n", 1199 __func__, *status); 1200 return 0; 1201 } 1202 /* status from CP block */ 1203 if ((cp_read(sd, 0xb5) & 0xd0) != 0xd0 || 1204 !(cp_read(sd, 0xb1) & 0x80)) 1205 /* TODO channel 2 */ 1206 *status |= V4L2_IN_ST_NO_SIGNAL; 1207 1208 if (is_digital_input(sd) && ((io_read(sd, 0x74) & 0x03) != 0x03)) 1209 *status |= V4L2_IN_ST_NO_SIGNAL; 1210 1211 v4l2_dbg(1, debug, sd, "%s: CP status = 0x%x\n", 1212 __func__, *status); 1213 1214 return 0; 1215 } 1216 1217 struct stdi_readback { 1218 u16 bl, lcf, lcvs; 1219 u8 hs_pol, vs_pol; 1220 bool interlaced; 1221 }; 1222 1223 static int stdi2dv_timings(struct v4l2_subdev *sd, 1224 struct stdi_readback *stdi, 1225 struct v4l2_dv_timings *timings) 1226 { 1227 struct adv7842_state *state = to_state(sd); 1228 u32 hfreq = (ADV7842_fsc * 8) / stdi->bl; 1229 u32 pix_clk; 1230 int i; 1231 1232 for (i = 0; v4l2_dv_timings_presets[i].bt.width; i++) { 1233 const struct v4l2_bt_timings *bt = &v4l2_dv_timings_presets[i].bt; 1234 1235 if (!v4l2_valid_dv_timings(&v4l2_dv_timings_presets[i], 1236 adv7842_get_dv_timings_cap(sd), 1237 adv7842_check_dv_timings, NULL)) 1238 continue; 1239 if (vtotal(bt) != stdi->lcf + 1) 1240 continue; 1241 if (bt->vsync != stdi->lcvs) 1242 continue; 1243 1244 pix_clk = hfreq * htotal(bt); 1245 1246 if ((pix_clk < bt->pixelclock + 1000000) && 1247 (pix_clk > bt->pixelclock - 1000000)) { 1248 *timings = v4l2_dv_timings_presets[i]; 1249 return 0; 1250 } 1251 } 1252 1253 if (v4l2_detect_cvt(stdi->lcf + 1, hfreq, stdi->lcvs, 1254 (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) | 1255 (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0), 1256 timings)) 1257 return 0; 1258 if (v4l2_detect_gtf(stdi->lcf + 1, hfreq, stdi->lcvs, 1259 (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) | 1260 (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0), 1261 state->aspect_ratio, timings)) 1262 return 0; 1263 1264 v4l2_dbg(2, debug, sd, 1265 "%s: No format candidate found for lcvs = %d, lcf=%d, bl = %d, %chsync, %cvsync\n", 1266 __func__, stdi->lcvs, stdi->lcf, stdi->bl, 1267 stdi->hs_pol, stdi->vs_pol); 1268 return -1; 1269 } 1270 1271 static int read_stdi(struct v4l2_subdev *sd, struct stdi_readback *stdi) 1272 { 1273 u32 status; 1274 1275 adv7842_g_input_status(sd, &status); 1276 if (status & V4L2_IN_ST_NO_SIGNAL) { 1277 v4l2_dbg(2, debug, sd, "%s: no signal\n", __func__); 1278 return -ENOLINK; 1279 } 1280 1281 stdi->bl = ((cp_read(sd, 0xb1) & 0x3f) << 8) | cp_read(sd, 0xb2); 1282 stdi->lcf = ((cp_read(sd, 0xb3) & 0x7) << 8) | cp_read(sd, 0xb4); 1283 stdi->lcvs = cp_read(sd, 0xb3) >> 3; 1284 1285 if ((cp_read(sd, 0xb5) & 0x80) && ((cp_read(sd, 0xb5) & 0x03) == 0x01)) { 1286 stdi->hs_pol = ((cp_read(sd, 0xb5) & 0x10) ? 1287 ((cp_read(sd, 0xb5) & 0x08) ? '+' : '-') : 'x'); 1288 stdi->vs_pol = ((cp_read(sd, 0xb5) & 0x40) ? 1289 ((cp_read(sd, 0xb5) & 0x20) ? '+' : '-') : 'x'); 1290 } else { 1291 stdi->hs_pol = 'x'; 1292 stdi->vs_pol = 'x'; 1293 } 1294 stdi->interlaced = (cp_read(sd, 0xb1) & 0x40) ? true : false; 1295 1296 if (stdi->lcf < 239 || stdi->bl < 8 || stdi->bl == 0x3fff) { 1297 v4l2_dbg(2, debug, sd, "%s: invalid signal\n", __func__); 1298 return -ENOLINK; 1299 } 1300 1301 v4l2_dbg(2, debug, sd, 1302 "%s: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %chsync, %cvsync, %s\n", 1303 __func__, stdi->lcf, stdi->bl, stdi->lcvs, 1304 stdi->hs_pol, stdi->vs_pol, 1305 stdi->interlaced ? "interlaced" : "progressive"); 1306 1307 return 0; 1308 } 1309 1310 static int adv7842_enum_dv_timings(struct v4l2_subdev *sd, 1311 struct v4l2_enum_dv_timings *timings) 1312 { 1313 return v4l2_enum_dv_timings_cap(timings, 1314 adv7842_get_dv_timings_cap(sd), adv7842_check_dv_timings, NULL); 1315 } 1316 1317 static int adv7842_dv_timings_cap(struct v4l2_subdev *sd, 1318 struct v4l2_dv_timings_cap *cap) 1319 { 1320 *cap = *adv7842_get_dv_timings_cap(sd); 1321 return 0; 1322 } 1323 1324 /* Fill the optional fields .standards and .flags in struct v4l2_dv_timings 1325 if the format is listed in adv7842_timings[] */ 1326 static void adv7842_fill_optional_dv_timings_fields(struct v4l2_subdev *sd, 1327 struct v4l2_dv_timings *timings) 1328 { 1329 v4l2_find_dv_timings_cap(timings, adv7842_get_dv_timings_cap(sd), 1330 is_digital_input(sd) ? 250000 : 1000000, 1331 adv7842_check_dv_timings, NULL); 1332 } 1333 1334 static int adv7842_query_dv_timings(struct v4l2_subdev *sd, 1335 struct v4l2_dv_timings *timings) 1336 { 1337 struct adv7842_state *state = to_state(sd); 1338 struct v4l2_bt_timings *bt = &timings->bt; 1339 struct stdi_readback stdi = { 0 }; 1340 1341 v4l2_dbg(1, debug, sd, "%s:\n", __func__); 1342 1343 /* SDP block */ 1344 if (state->mode == ADV7842_MODE_SDP) 1345 return -ENODATA; 1346 1347 /* read STDI */ 1348 if (read_stdi(sd, &stdi)) { 1349 state->restart_stdi_once = true; 1350 v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__); 1351 return -ENOLINK; 1352 } 1353 bt->interlaced = stdi.interlaced ? 1354 V4L2_DV_INTERLACED : V4L2_DV_PROGRESSIVE; 1355 1356 if (is_digital_input(sd)) { 1357 uint32_t freq; 1358 1359 timings->type = V4L2_DV_BT_656_1120; 1360 1361 bt->width = (hdmi_read(sd, 0x07) & 0x0f) * 256 + hdmi_read(sd, 0x08); 1362 bt->height = (hdmi_read(sd, 0x09) & 0x0f) * 256 + hdmi_read(sd, 0x0a); 1363 freq = (hdmi_read(sd, 0x06) * 1000000) + 1364 ((hdmi_read(sd, 0x3b) & 0x30) >> 4) * 250000; 1365 1366 if (is_hdmi(sd)) { 1367 /* adjust for deep color mode */ 1368 freq = freq * 8 / (((hdmi_read(sd, 0x0b) & 0xc0) >> 5) + 8); 1369 } 1370 bt->pixelclock = freq; 1371 bt->hfrontporch = (hdmi_read(sd, 0x20) & 0x03) * 256 + 1372 hdmi_read(sd, 0x21); 1373 bt->hsync = (hdmi_read(sd, 0x22) & 0x03) * 256 + 1374 hdmi_read(sd, 0x23); 1375 bt->hbackporch = (hdmi_read(sd, 0x24) & 0x03) * 256 + 1376 hdmi_read(sd, 0x25); 1377 bt->vfrontporch = ((hdmi_read(sd, 0x2a) & 0x1f) * 256 + 1378 hdmi_read(sd, 0x2b)) / 2; 1379 bt->vsync = ((hdmi_read(sd, 0x2e) & 0x1f) * 256 + 1380 hdmi_read(sd, 0x2f)) / 2; 1381 bt->vbackporch = ((hdmi_read(sd, 0x32) & 0x1f) * 256 + 1382 hdmi_read(sd, 0x33)) / 2; 1383 bt->polarities = ((hdmi_read(sd, 0x05) & 0x10) ? V4L2_DV_VSYNC_POS_POL : 0) | 1384 ((hdmi_read(sd, 0x05) & 0x20) ? V4L2_DV_HSYNC_POS_POL : 0); 1385 if (bt->interlaced == V4L2_DV_INTERLACED) { 1386 bt->height += (hdmi_read(sd, 0x0b) & 0x0f) * 256 + 1387 hdmi_read(sd, 0x0c); 1388 bt->il_vfrontporch = ((hdmi_read(sd, 0x2c) & 0x1f) * 256 + 1389 hdmi_read(sd, 0x2d)) / 2; 1390 bt->il_vsync = ((hdmi_read(sd, 0x30) & 0x1f) * 256 + 1391 hdmi_read(sd, 0x31)) / 2; 1392 bt->vbackporch = ((hdmi_read(sd, 0x34) & 0x1f) * 256 + 1393 hdmi_read(sd, 0x35)) / 2; 1394 } 1395 adv7842_fill_optional_dv_timings_fields(sd, timings); 1396 } else { 1397 /* find format 1398 * Since LCVS values are inaccurate [REF_03, p. 339-340], 1399 * stdi2dv_timings() is called with lcvs +-1 if the first attempt fails. 1400 */ 1401 if (!stdi2dv_timings(sd, &stdi, timings)) 1402 goto found; 1403 stdi.lcvs += 1; 1404 v4l2_dbg(1, debug, sd, "%s: lcvs + 1 = %d\n", __func__, stdi.lcvs); 1405 if (!stdi2dv_timings(sd, &stdi, timings)) 1406 goto found; 1407 stdi.lcvs -= 2; 1408 v4l2_dbg(1, debug, sd, "%s: lcvs - 1 = %d\n", __func__, stdi.lcvs); 1409 if (stdi2dv_timings(sd, &stdi, timings)) { 1410 /* 1411 * The STDI block may measure wrong values, especially 1412 * for lcvs and lcf. If the driver can not find any 1413 * valid timing, the STDI block is restarted to measure 1414 * the video timings again. The function will return an 1415 * error, but the restart of STDI will generate a new 1416 * STDI interrupt and the format detection process will 1417 * restart. 1418 */ 1419 if (state->restart_stdi_once) { 1420 v4l2_dbg(1, debug, sd, "%s: restart STDI\n", __func__); 1421 /* TODO restart STDI for Sync Channel 2 */ 1422 /* enter one-shot mode */ 1423 cp_write_and_or(sd, 0x86, 0xf9, 0x00); 1424 /* trigger STDI restart */ 1425 cp_write_and_or(sd, 0x86, 0xf9, 0x04); 1426 /* reset to continuous mode */ 1427 cp_write_and_or(sd, 0x86, 0xf9, 0x02); 1428 state->restart_stdi_once = false; 1429 return -ENOLINK; 1430 } 1431 v4l2_dbg(1, debug, sd, "%s: format not supported\n", __func__); 1432 return -ERANGE; 1433 } 1434 state->restart_stdi_once = true; 1435 } 1436 found: 1437 1438 if (debug > 1) 1439 v4l2_print_dv_timings(sd->name, "adv7842_query_dv_timings:", 1440 timings, true); 1441 return 0; 1442 } 1443 1444 static int adv7842_s_dv_timings(struct v4l2_subdev *sd, 1445 struct v4l2_dv_timings *timings) 1446 { 1447 struct adv7842_state *state = to_state(sd); 1448 struct v4l2_bt_timings *bt; 1449 int err; 1450 1451 v4l2_dbg(1, debug, sd, "%s:\n", __func__); 1452 1453 if (state->mode == ADV7842_MODE_SDP) 1454 return -ENODATA; 1455 1456 if (v4l2_match_dv_timings(&state->timings, timings, 0)) { 1457 v4l2_dbg(1, debug, sd, "%s: no change\n", __func__); 1458 return 0; 1459 } 1460 1461 bt = &timings->bt; 1462 1463 if (!v4l2_valid_dv_timings(timings, adv7842_get_dv_timings_cap(sd), 1464 adv7842_check_dv_timings, NULL)) 1465 return -ERANGE; 1466 1467 adv7842_fill_optional_dv_timings_fields(sd, timings); 1468 1469 state->timings = *timings; 1470 1471 cp_write(sd, 0x91, bt->interlaced ? 0x40 : 0x00); 1472 1473 /* Use prim_mode and vid_std when available */ 1474 err = configure_predefined_video_timings(sd, timings); 1475 if (err) { 1476 /* custom settings when the video format 1477 does not have prim_mode/vid_std */ 1478 configure_custom_video_timings(sd, bt); 1479 } 1480 1481 set_rgb_quantization_range(sd); 1482 1483 1484 if (debug > 1) 1485 v4l2_print_dv_timings(sd->name, "adv7842_s_dv_timings: ", 1486 timings, true); 1487 return 0; 1488 } 1489 1490 static int adv7842_g_dv_timings(struct v4l2_subdev *sd, 1491 struct v4l2_dv_timings *timings) 1492 { 1493 struct adv7842_state *state = to_state(sd); 1494 1495 if (state->mode == ADV7842_MODE_SDP) 1496 return -ENODATA; 1497 *timings = state->timings; 1498 return 0; 1499 } 1500 1501 static void enable_input(struct v4l2_subdev *sd) 1502 { 1503 struct adv7842_state *state = to_state(sd); 1504 1505 set_rgb_quantization_range(sd); 1506 switch (state->mode) { 1507 case ADV7842_MODE_SDP: 1508 case ADV7842_MODE_COMP: 1509 case ADV7842_MODE_RGB: 1510 io_write(sd, 0x15, 0xb0); /* Disable Tristate of Pins (no audio) */ 1511 break; 1512 case ADV7842_MODE_HDMI: 1513 hdmi_write(sd, 0x01, 0x00); /* Enable HDMI clock terminators */ 1514 io_write(sd, 0x15, 0xa0); /* Disable Tristate of Pins */ 1515 hdmi_write_and_or(sd, 0x1a, 0xef, 0x00); /* Unmute audio */ 1516 break; 1517 default: 1518 v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n", 1519 __func__, state->mode); 1520 break; 1521 } 1522 } 1523 1524 static void disable_input(struct v4l2_subdev *sd) 1525 { 1526 hdmi_write_and_or(sd, 0x1a, 0xef, 0x10); /* Mute audio [REF_01, c. 2.2.2] */ 1527 msleep(16); /* 512 samples with >= 32 kHz sample rate [REF_03, c. 8.29] */ 1528 io_write(sd, 0x15, 0xbe); /* Tristate all outputs from video core */ 1529 hdmi_write(sd, 0x01, 0x78); /* Disable HDMI clock terminators */ 1530 } 1531 1532 static void sdp_csc_coeff(struct v4l2_subdev *sd, 1533 const struct adv7842_sdp_csc_coeff *c) 1534 { 1535 /* csc auto/manual */ 1536 sdp_io_write_and_or(sd, 0xe0, 0xbf, c->manual ? 0x00 : 0x40); 1537 1538 if (!c->manual) 1539 return; 1540 1541 /* csc scaling */ 1542 sdp_io_write_and_or(sd, 0xe0, 0x7f, c->scaling == 2 ? 0x80 : 0x00); 1543 1544 /* A coeff */ 1545 sdp_io_write_and_or(sd, 0xe0, 0xe0, c->A1 >> 8); 1546 sdp_io_write(sd, 0xe1, c->A1); 1547 sdp_io_write_and_or(sd, 0xe2, 0xe0, c->A2 >> 8); 1548 sdp_io_write(sd, 0xe3, c->A2); 1549 sdp_io_write_and_or(sd, 0xe4, 0xe0, c->A3 >> 8); 1550 sdp_io_write(sd, 0xe5, c->A3); 1551 1552 /* A scale */ 1553 sdp_io_write_and_or(sd, 0xe6, 0x80, c->A4 >> 8); 1554 sdp_io_write(sd, 0xe7, c->A4); 1555 1556 /* B coeff */ 1557 sdp_io_write_and_or(sd, 0xe8, 0xe0, c->B1 >> 8); 1558 sdp_io_write(sd, 0xe9, c->B1); 1559 sdp_io_write_and_or(sd, 0xea, 0xe0, c->B2 >> 8); 1560 sdp_io_write(sd, 0xeb, c->B2); 1561 sdp_io_write_and_or(sd, 0xec, 0xe0, c->B3 >> 8); 1562 sdp_io_write(sd, 0xed, c->B3); 1563 1564 /* B scale */ 1565 sdp_io_write_and_or(sd, 0xee, 0x80, c->B4 >> 8); 1566 sdp_io_write(sd, 0xef, c->B4); 1567 1568 /* C coeff */ 1569 sdp_io_write_and_or(sd, 0xf0, 0xe0, c->C1 >> 8); 1570 sdp_io_write(sd, 0xf1, c->C1); 1571 sdp_io_write_and_or(sd, 0xf2, 0xe0, c->C2 >> 8); 1572 sdp_io_write(sd, 0xf3, c->C2); 1573 sdp_io_write_and_or(sd, 0xf4, 0xe0, c->C3 >> 8); 1574 sdp_io_write(sd, 0xf5, c->C3); 1575 1576 /* C scale */ 1577 sdp_io_write_and_or(sd, 0xf6, 0x80, c->C4 >> 8); 1578 sdp_io_write(sd, 0xf7, c->C4); 1579 } 1580 1581 static void select_input(struct v4l2_subdev *sd, 1582 enum adv7842_vid_std_select vid_std_select) 1583 { 1584 struct adv7842_state *state = to_state(sd); 1585 1586 switch (state->mode) { 1587 case ADV7842_MODE_SDP: 1588 io_write(sd, 0x00, vid_std_select); /* video std: CVBS or YC mode */ 1589 io_write(sd, 0x01, 0); /* prim mode */ 1590 /* enable embedded syncs for auto graphics mode */ 1591 cp_write_and_or(sd, 0x81, 0xef, 0x10); 1592 1593 afe_write(sd, 0x00, 0x00); /* power up ADC */ 1594 afe_write(sd, 0xc8, 0x00); /* phase control */ 1595 1596 io_write(sd, 0xdd, 0x90); /* Manual 2x output clock */ 1597 /* script says register 0xde, which don't exist in manual */ 1598 1599 /* Manual analog input muxing mode, CVBS (6.4)*/ 1600 afe_write_and_or(sd, 0x02, 0x7f, 0x80); 1601 if (vid_std_select == ADV7842_SDP_VID_STD_CVBS_SD_4x1) { 1602 afe_write(sd, 0x03, 0xa0); /* ADC0 to AIN10 (CVBS), ADC1 N/C*/ 1603 afe_write(sd, 0x04, 0x00); /* ADC2 N/C,ADC3 N/C*/ 1604 } else { 1605 afe_write(sd, 0x03, 0xa0); /* ADC0 to AIN10 (CVBS), ADC1 N/C*/ 1606 afe_write(sd, 0x04, 0xc0); /* ADC2 to AIN12, ADC3 N/C*/ 1607 } 1608 afe_write(sd, 0x0c, 0x1f); /* ADI recommend write */ 1609 afe_write(sd, 0x12, 0x63); /* ADI recommend write */ 1610 1611 sdp_io_write(sd, 0xb2, 0x60); /* Disable AV codes */ 1612 sdp_io_write(sd, 0xc8, 0xe3); /* Disable Ancillary data */ 1613 1614 /* SDP recommended settings */ 1615 sdp_write(sd, 0x00, 0x3F); /* Autodetect PAL NTSC (not SECAM) */ 1616 sdp_write(sd, 0x01, 0x00); /* Pedestal Off */ 1617 1618 sdp_write(sd, 0x03, 0xE4); /* Manual VCR Gain Luma 0x40B */ 1619 sdp_write(sd, 0x04, 0x0B); /* Manual Luma setting */ 1620 sdp_write(sd, 0x05, 0xC3); /* Manual Chroma setting 0x3FE */ 1621 sdp_write(sd, 0x06, 0xFE); /* Manual Chroma setting */ 1622 sdp_write(sd, 0x12, 0x0D); /* Frame TBC,I_P, 3D comb enabled */ 1623 sdp_write(sd, 0xA7, 0x00); /* ADI Recommended Write */ 1624 sdp_io_write(sd, 0xB0, 0x00); /* Disable H and v blanking */ 1625 1626 /* deinterlacer enabled and 3D comb */ 1627 sdp_write_and_or(sd, 0x12, 0xf6, 0x09); 1628 1629 break; 1630 1631 case ADV7842_MODE_COMP: 1632 case ADV7842_MODE_RGB: 1633 /* Automatic analog input muxing mode */ 1634 afe_write_and_or(sd, 0x02, 0x7f, 0x00); 1635 /* set mode and select free run resolution */ 1636 io_write(sd, 0x00, vid_std_select); /* video std */ 1637 io_write(sd, 0x01, 0x02); /* prim mode */ 1638 cp_write_and_or(sd, 0x81, 0xef, 0x10); /* enable embedded syncs 1639 for auto graphics mode */ 1640 1641 afe_write(sd, 0x00, 0x00); /* power up ADC */ 1642 afe_write(sd, 0xc8, 0x00); /* phase control */ 1643 if (state->mode == ADV7842_MODE_COMP) { 1644 /* force to YCrCb */ 1645 io_write_and_or(sd, 0x02, 0x0f, 0x60); 1646 } else { 1647 /* force to RGB */ 1648 io_write_and_or(sd, 0x02, 0x0f, 0x10); 1649 } 1650 1651 /* set ADI recommended settings for digitizer */ 1652 /* "ADV7842 Register Settings Recommendations 1653 * (rev. 1.8, November 2010)" p. 9. */ 1654 afe_write(sd, 0x0c, 0x1f); /* ADC Range improvement */ 1655 afe_write(sd, 0x12, 0x63); /* ADC Range improvement */ 1656 1657 /* set to default gain for RGB */ 1658 cp_write(sd, 0x73, 0x10); 1659 cp_write(sd, 0x74, 0x04); 1660 cp_write(sd, 0x75, 0x01); 1661 cp_write(sd, 0x76, 0x00); 1662 1663 cp_write(sd, 0x3e, 0x04); /* CP core pre-gain control */ 1664 cp_write(sd, 0xc3, 0x39); /* CP coast control. Graphics mode */ 1665 cp_write(sd, 0x40, 0x5c); /* CP core pre-gain control. Graphics mode */ 1666 break; 1667 1668 case ADV7842_MODE_HDMI: 1669 /* Automatic analog input muxing mode */ 1670 afe_write_and_or(sd, 0x02, 0x7f, 0x00); 1671 /* set mode and select free run resolution */ 1672 if (state->hdmi_port_a) 1673 hdmi_write(sd, 0x00, 0x02); /* select port A */ 1674 else 1675 hdmi_write(sd, 0x00, 0x03); /* select port B */ 1676 io_write(sd, 0x00, vid_std_select); /* video std */ 1677 io_write(sd, 0x01, 5); /* prim mode */ 1678 cp_write_and_or(sd, 0x81, 0xef, 0x00); /* disable embedded syncs 1679 for auto graphics mode */ 1680 1681 /* set ADI recommended settings for HDMI: */ 1682 /* "ADV7842 Register Settings Recommendations 1683 * (rev. 1.8, November 2010)" p. 3. */ 1684 hdmi_write(sd, 0xc0, 0x00); 1685 hdmi_write(sd, 0x0d, 0x34); /* ADI recommended write */ 1686 hdmi_write(sd, 0x3d, 0x10); /* ADI recommended write */ 1687 hdmi_write(sd, 0x44, 0x85); /* TMDS PLL optimization */ 1688 hdmi_write(sd, 0x46, 0x1f); /* ADI recommended write */ 1689 hdmi_write(sd, 0x57, 0xb6); /* TMDS PLL optimization */ 1690 hdmi_write(sd, 0x58, 0x03); /* TMDS PLL optimization */ 1691 hdmi_write(sd, 0x60, 0x88); /* TMDS PLL optimization */ 1692 hdmi_write(sd, 0x61, 0x88); /* TMDS PLL optimization */ 1693 hdmi_write(sd, 0x6c, 0x18); /* Disable ISRC clearing bit, 1694 Improve robustness */ 1695 hdmi_write(sd, 0x75, 0x10); /* DDC drive strength */ 1696 hdmi_write(sd, 0x85, 0x1f); /* equaliser */ 1697 hdmi_write(sd, 0x87, 0x70); /* ADI recommended write */ 1698 hdmi_write(sd, 0x89, 0x04); /* equaliser */ 1699 hdmi_write(sd, 0x8a, 0x1e); /* equaliser */ 1700 hdmi_write(sd, 0x93, 0x04); /* equaliser */ 1701 hdmi_write(sd, 0x94, 0x1e); /* equaliser */ 1702 hdmi_write(sd, 0x99, 0xa1); /* ADI recommended write */ 1703 hdmi_write(sd, 0x9b, 0x09); /* ADI recommended write */ 1704 hdmi_write(sd, 0x9d, 0x02); /* equaliser */ 1705 1706 afe_write(sd, 0x00, 0xff); /* power down ADC */ 1707 afe_write(sd, 0xc8, 0x40); /* phase control */ 1708 1709 /* set to default gain for HDMI */ 1710 cp_write(sd, 0x73, 0x10); 1711 cp_write(sd, 0x74, 0x04); 1712 cp_write(sd, 0x75, 0x01); 1713 cp_write(sd, 0x76, 0x00); 1714 1715 /* reset ADI recommended settings for digitizer */ 1716 /* "ADV7842 Register Settings Recommendations 1717 * (rev. 2.5, June 2010)" p. 17. */ 1718 afe_write(sd, 0x12, 0xfb); /* ADC noise shaping filter controls */ 1719 afe_write(sd, 0x0c, 0x0d); /* CP core gain controls */ 1720 cp_write(sd, 0x3e, 0x80); /* CP core pre-gain control, 1721 enable color control */ 1722 /* CP coast control */ 1723 cp_write(sd, 0xc3, 0x33); /* Component mode */ 1724 1725 /* color space conversion, autodetect color space */ 1726 io_write_and_or(sd, 0x02, 0x0f, 0xf0); 1727 break; 1728 1729 default: 1730 v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n", 1731 __func__, state->mode); 1732 break; 1733 } 1734 } 1735 1736 static int adv7842_s_routing(struct v4l2_subdev *sd, 1737 u32 input, u32 output, u32 config) 1738 { 1739 struct adv7842_state *state = to_state(sd); 1740 1741 v4l2_dbg(2, debug, sd, "%s: input %d\n", __func__, input); 1742 1743 switch (input) { 1744 case ADV7842_SELECT_HDMI_PORT_A: 1745 state->mode = ADV7842_MODE_HDMI; 1746 state->vid_std_select = ADV7842_HDMI_COMP_VID_STD_HD_1250P; 1747 state->hdmi_port_a = true; 1748 break; 1749 case ADV7842_SELECT_HDMI_PORT_B: 1750 state->mode = ADV7842_MODE_HDMI; 1751 state->vid_std_select = ADV7842_HDMI_COMP_VID_STD_HD_1250P; 1752 state->hdmi_port_a = false; 1753 break; 1754 case ADV7842_SELECT_VGA_COMP: 1755 state->mode = ADV7842_MODE_COMP; 1756 state->vid_std_select = ADV7842_RGB_VID_STD_AUTO_GRAPH_MODE; 1757 break; 1758 case ADV7842_SELECT_VGA_RGB: 1759 state->mode = ADV7842_MODE_RGB; 1760 state->vid_std_select = ADV7842_RGB_VID_STD_AUTO_GRAPH_MODE; 1761 break; 1762 case ADV7842_SELECT_SDP_CVBS: 1763 state->mode = ADV7842_MODE_SDP; 1764 state->vid_std_select = ADV7842_SDP_VID_STD_CVBS_SD_4x1; 1765 break; 1766 case ADV7842_SELECT_SDP_YC: 1767 state->mode = ADV7842_MODE_SDP; 1768 state->vid_std_select = ADV7842_SDP_VID_STD_YC_SD4_x1; 1769 break; 1770 default: 1771 return -EINVAL; 1772 } 1773 1774 disable_input(sd); 1775 select_input(sd, state->vid_std_select); 1776 enable_input(sd); 1777 1778 v4l2_subdev_notify(sd, ADV7842_FMT_CHANGE, NULL); 1779 1780 return 0; 1781 } 1782 1783 static int adv7842_enum_mbus_fmt(struct v4l2_subdev *sd, unsigned int index, 1784 enum v4l2_mbus_pixelcode *code) 1785 { 1786 if (index) 1787 return -EINVAL; 1788 /* Good enough for now */ 1789 *code = V4L2_MBUS_FMT_FIXED; 1790 return 0; 1791 } 1792 1793 static int adv7842_g_mbus_fmt(struct v4l2_subdev *sd, 1794 struct v4l2_mbus_framefmt *fmt) 1795 { 1796 struct adv7842_state *state = to_state(sd); 1797 1798 fmt->width = state->timings.bt.width; 1799 fmt->height = state->timings.bt.height; 1800 fmt->code = V4L2_MBUS_FMT_FIXED; 1801 fmt->field = V4L2_FIELD_NONE; 1802 1803 if (state->mode == ADV7842_MODE_SDP) { 1804 /* SPD block */ 1805 if (!(sdp_read(sd, 0x5A) & 0x01)) 1806 return -EINVAL; 1807 fmt->width = 720; 1808 /* valid signal */ 1809 if (state->norm & V4L2_STD_525_60) 1810 fmt->height = 480; 1811 else 1812 fmt->height = 576; 1813 fmt->colorspace = V4L2_COLORSPACE_SMPTE170M; 1814 return 0; 1815 } 1816 1817 if (state->timings.bt.standards & V4L2_DV_BT_STD_CEA861) { 1818 fmt->colorspace = (state->timings.bt.height <= 576) ? 1819 V4L2_COLORSPACE_SMPTE170M : V4L2_COLORSPACE_REC709; 1820 } 1821 return 0; 1822 } 1823 1824 static void adv7842_irq_enable(struct v4l2_subdev *sd, bool enable) 1825 { 1826 if (enable) { 1827 /* Enable SSPD, STDI and CP locked/unlocked interrupts */ 1828 io_write(sd, 0x46, 0x9c); 1829 /* ESDP_50HZ_DET interrupt */ 1830 io_write(sd, 0x5a, 0x10); 1831 /* Enable CABLE_DET_A/B_ST (+5v) interrupt */ 1832 io_write(sd, 0x73, 0x03); 1833 /* Enable V_LOCKED and DE_REGEN_LCK interrupts */ 1834 io_write(sd, 0x78, 0x03); 1835 /* Enable SDP Standard Detection Change and SDP Video Detected */ 1836 io_write(sd, 0xa0, 0x09); 1837 /* Enable HDMI_MODE interrupt */ 1838 io_write(sd, 0x69, 0x08); 1839 } else { 1840 io_write(sd, 0x46, 0x0); 1841 io_write(sd, 0x5a, 0x0); 1842 io_write(sd, 0x73, 0x0); 1843 io_write(sd, 0x78, 0x0); 1844 io_write(sd, 0xa0, 0x0); 1845 io_write(sd, 0x69, 0x0); 1846 } 1847 } 1848 1849 static int adv7842_isr(struct v4l2_subdev *sd, u32 status, bool *handled) 1850 { 1851 struct adv7842_state *state = to_state(sd); 1852 u8 fmt_change_cp, fmt_change_digital, fmt_change_sdp; 1853 u8 irq_status[6]; 1854 1855 adv7842_irq_enable(sd, false); 1856 1857 /* read status */ 1858 irq_status[0] = io_read(sd, 0x43); 1859 irq_status[1] = io_read(sd, 0x57); 1860 irq_status[2] = io_read(sd, 0x70); 1861 irq_status[3] = io_read(sd, 0x75); 1862 irq_status[4] = io_read(sd, 0x9d); 1863 irq_status[5] = io_read(sd, 0x66); 1864 1865 /* and clear */ 1866 if (irq_status[0]) 1867 io_write(sd, 0x44, irq_status[0]); 1868 if (irq_status[1]) 1869 io_write(sd, 0x58, irq_status[1]); 1870 if (irq_status[2]) 1871 io_write(sd, 0x71, irq_status[2]); 1872 if (irq_status[3]) 1873 io_write(sd, 0x76, irq_status[3]); 1874 if (irq_status[4]) 1875 io_write(sd, 0x9e, irq_status[4]); 1876 if (irq_status[5]) 1877 io_write(sd, 0x67, irq_status[5]); 1878 1879 adv7842_irq_enable(sd, true); 1880 1881 v4l2_dbg(1, debug, sd, "%s: irq %x, %x, %x, %x, %x, %x\n", __func__, 1882 irq_status[0], irq_status[1], irq_status[2], 1883 irq_status[3], irq_status[4], irq_status[5]); 1884 1885 /* format change CP */ 1886 fmt_change_cp = irq_status[0] & 0x9c; 1887 1888 /* format change SDP */ 1889 if (state->mode == ADV7842_MODE_SDP) 1890 fmt_change_sdp = (irq_status[1] & 0x30) | (irq_status[4] & 0x09); 1891 else 1892 fmt_change_sdp = 0; 1893 1894 /* digital format CP */ 1895 if (is_digital_input(sd)) 1896 fmt_change_digital = irq_status[3] & 0x03; 1897 else 1898 fmt_change_digital = 0; 1899 1900 /* format change */ 1901 if (fmt_change_cp || fmt_change_digital || fmt_change_sdp) { 1902 v4l2_dbg(1, debug, sd, 1903 "%s: fmt_change_cp = 0x%x, fmt_change_digital = 0x%x, fmt_change_sdp = 0x%x\n", 1904 __func__, fmt_change_cp, fmt_change_digital, 1905 fmt_change_sdp); 1906 v4l2_subdev_notify(sd, ADV7842_FMT_CHANGE, NULL); 1907 if (handled) 1908 *handled = true; 1909 } 1910 1911 /* HDMI/DVI mode */ 1912 if (irq_status[5] & 0x08) { 1913 v4l2_dbg(1, debug, sd, "%s: irq %s mode\n", __func__, 1914 (io_read(sd, 0x65) & 0x08) ? "HDMI" : "DVI"); 1915 if (handled) 1916 *handled = true; 1917 } 1918 1919 /* tx 5v detect */ 1920 if (irq_status[2] & 0x3) { 1921 v4l2_dbg(1, debug, sd, "%s: irq tx_5v\n", __func__); 1922 adv7842_s_detect_tx_5v_ctrl(sd); 1923 if (handled) 1924 *handled = true; 1925 } 1926 return 0; 1927 } 1928 1929 static int adv7842_get_edid(struct v4l2_subdev *sd, struct v4l2_subdev_edid *edid) 1930 { 1931 struct adv7842_state *state = to_state(sd); 1932 u8 *data = NULL; 1933 1934 if (edid->pad > ADV7842_EDID_PORT_VGA) 1935 return -EINVAL; 1936 if (edid->blocks == 0) 1937 return -EINVAL; 1938 if (edid->blocks > 2) 1939 return -EINVAL; 1940 if (edid->start_block > 1) 1941 return -EINVAL; 1942 if (edid->start_block == 1) 1943 edid->blocks = 1; 1944 if (!edid->edid) 1945 return -EINVAL; 1946 1947 switch (edid->pad) { 1948 case ADV7842_EDID_PORT_A: 1949 case ADV7842_EDID_PORT_B: 1950 if (state->hdmi_edid.present & (0x04 << edid->pad)) 1951 data = state->hdmi_edid.edid; 1952 break; 1953 case ADV7842_EDID_PORT_VGA: 1954 if (state->vga_edid.present) 1955 data = state->vga_edid.edid; 1956 break; 1957 default: 1958 return -EINVAL; 1959 } 1960 if (!data) 1961 return -ENODATA; 1962 1963 memcpy(edid->edid, 1964 data + edid->start_block * 128, 1965 edid->blocks * 128); 1966 return 0; 1967 } 1968 1969 static int adv7842_set_edid(struct v4l2_subdev *sd, struct v4l2_subdev_edid *e) 1970 { 1971 struct adv7842_state *state = to_state(sd); 1972 int err = 0; 1973 1974 if (e->pad > ADV7842_EDID_PORT_VGA) 1975 return -EINVAL; 1976 if (e->start_block != 0) 1977 return -EINVAL; 1978 if (e->blocks > 2) 1979 return -E2BIG; 1980 if (!e->edid) 1981 return -EINVAL; 1982 1983 /* todo, per edid */ 1984 state->aspect_ratio = v4l2_calc_aspect_ratio(e->edid[0x15], 1985 e->edid[0x16]); 1986 1987 switch (e->pad) { 1988 case ADV7842_EDID_PORT_VGA: 1989 memset(&state->vga_edid.edid, 0, 256); 1990 state->vga_edid.present = e->blocks ? 0x1 : 0x0; 1991 memcpy(&state->vga_edid.edid, e->edid, 128 * e->blocks); 1992 err = edid_write_vga_segment(sd); 1993 break; 1994 case ADV7842_EDID_PORT_A: 1995 case ADV7842_EDID_PORT_B: 1996 memset(&state->hdmi_edid.edid, 0, 256); 1997 if (e->blocks) 1998 state->hdmi_edid.present |= 0x04 << e->pad; 1999 else 2000 state->hdmi_edid.present &= ~(0x04 << e->pad); 2001 memcpy(&state->hdmi_edid.edid, e->edid, 128 * e->blocks); 2002 err = edid_write_hdmi_segment(sd, e->pad); 2003 break; 2004 default: 2005 return -EINVAL; 2006 } 2007 if (err < 0) 2008 v4l2_err(sd, "error %d writing edid on port %d\n", err, e->pad); 2009 return err; 2010 } 2011 2012 /*********** avi info frame CEA-861-E **************/ 2013 /* TODO move to common library */ 2014 2015 struct avi_info_frame { 2016 uint8_t f17; 2017 uint8_t y10; 2018 uint8_t a0; 2019 uint8_t b10; 2020 uint8_t s10; 2021 uint8_t c10; 2022 uint8_t m10; 2023 uint8_t r3210; 2024 uint8_t itc; 2025 uint8_t ec210; 2026 uint8_t q10; 2027 uint8_t sc10; 2028 uint8_t f47; 2029 uint8_t vic; 2030 uint8_t yq10; 2031 uint8_t cn10; 2032 uint8_t pr3210; 2033 uint16_t etb; 2034 uint16_t sbb; 2035 uint16_t elb; 2036 uint16_t srb; 2037 }; 2038 2039 static const char *y10_txt[4] = { 2040 "RGB", 2041 "YCbCr 4:2:2", 2042 "YCbCr 4:4:4", 2043 "Future", 2044 }; 2045 2046 static const char *c10_txt[4] = { 2047 "No Data", 2048 "SMPTE 170M", 2049 "ITU-R 709", 2050 "Extended Colorimetry information valied", 2051 }; 2052 2053 static const char *itc_txt[2] = { 2054 "No Data", 2055 "IT content", 2056 }; 2057 2058 static const char *ec210_txt[8] = { 2059 "xvYCC601", 2060 "xvYCC709", 2061 "sYCC601", 2062 "AdobeYCC601", 2063 "AdobeRGB", 2064 "5 reserved", 2065 "6 reserved", 2066 "7 reserved", 2067 }; 2068 2069 static const char *q10_txt[4] = { 2070 "Default", 2071 "Limited Range", 2072 "Full Range", 2073 "Reserved", 2074 }; 2075 2076 static void parse_avi_infoframe(struct v4l2_subdev *sd, uint8_t *buf, 2077 struct avi_info_frame *avi) 2078 { 2079 avi->f17 = (buf[1] >> 7) & 0x1; 2080 avi->y10 = (buf[1] >> 5) & 0x3; 2081 avi->a0 = (buf[1] >> 4) & 0x1; 2082 avi->b10 = (buf[1] >> 2) & 0x3; 2083 avi->s10 = buf[1] & 0x3; 2084 avi->c10 = (buf[2] >> 6) & 0x3; 2085 avi->m10 = (buf[2] >> 4) & 0x3; 2086 avi->r3210 = buf[2] & 0xf; 2087 avi->itc = (buf[3] >> 7) & 0x1; 2088 avi->ec210 = (buf[3] >> 4) & 0x7; 2089 avi->q10 = (buf[3] >> 2) & 0x3; 2090 avi->sc10 = buf[3] & 0x3; 2091 avi->f47 = (buf[4] >> 7) & 0x1; 2092 avi->vic = buf[4] & 0x7f; 2093 avi->yq10 = (buf[5] >> 6) & 0x3; 2094 avi->cn10 = (buf[5] >> 4) & 0x3; 2095 avi->pr3210 = buf[5] & 0xf; 2096 avi->etb = buf[6] + 256*buf[7]; 2097 avi->sbb = buf[8] + 256*buf[9]; 2098 avi->elb = buf[10] + 256*buf[11]; 2099 avi->srb = buf[12] + 256*buf[13]; 2100 } 2101 2102 static void print_avi_infoframe(struct v4l2_subdev *sd) 2103 { 2104 int i; 2105 uint8_t buf[14]; 2106 uint8_t avi_inf_len; 2107 struct avi_info_frame avi; 2108 2109 if (!(hdmi_read(sd, 0x05) & 0x80)) { 2110 v4l2_info(sd, "receive DVI-D signal (AVI infoframe not supported)\n"); 2111 return; 2112 } 2113 if (!(io_read(sd, 0x60) & 0x01)) { 2114 v4l2_info(sd, "AVI infoframe not received\n"); 2115 return; 2116 } 2117 2118 if (io_read(sd, 0x88) & 0x10) { 2119 /* Note: the ADV7842 calculated incorrect checksums for InfoFrames 2120 with a length of 14 or 15. See the ADV7842 Register Settings 2121 Recommendations document for more details. */ 2122 v4l2_info(sd, "AVI infoframe checksum error\n"); 2123 return; 2124 } 2125 2126 avi_inf_len = infoframe_read(sd, 0xe2); 2127 v4l2_info(sd, "AVI infoframe version %d (%d byte)\n", 2128 infoframe_read(sd, 0xe1), avi_inf_len); 2129 2130 if (infoframe_read(sd, 0xe1) != 0x02) 2131 return; 2132 2133 for (i = 0; i < 14; i++) 2134 buf[i] = infoframe_read(sd, i); 2135 2136 v4l2_info(sd, "\t%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n", 2137 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6], buf[7], 2138 buf[8], buf[9], buf[10], buf[11], buf[12], buf[13]); 2139 2140 parse_avi_infoframe(sd, buf, &avi); 2141 2142 if (avi.vic) 2143 v4l2_info(sd, "\tVIC: %d\n", avi.vic); 2144 if (avi.itc) 2145 v4l2_info(sd, "\t%s\n", itc_txt[avi.itc]); 2146 2147 if (avi.y10) 2148 v4l2_info(sd, "\t%s %s\n", y10_txt[avi.y10], !avi.c10 ? "" : 2149 (avi.c10 == 0x3 ? ec210_txt[avi.ec210] : c10_txt[avi.c10])); 2150 else 2151 v4l2_info(sd, "\t%s %s\n", y10_txt[avi.y10], q10_txt[avi.q10]); 2152 } 2153 2154 static const char * const prim_mode_txt[] = { 2155 "SDP", 2156 "Component", 2157 "Graphics", 2158 "Reserved", 2159 "CVBS & HDMI AUDIO", 2160 "HDMI-Comp", 2161 "HDMI-GR", 2162 "Reserved", 2163 "Reserved", 2164 "Reserved", 2165 "Reserved", 2166 "Reserved", 2167 "Reserved", 2168 "Reserved", 2169 "Reserved", 2170 "Reserved", 2171 }; 2172 2173 static int adv7842_sdp_log_status(struct v4l2_subdev *sd) 2174 { 2175 /* SDP (Standard definition processor) block */ 2176 uint8_t sdp_signal_detected = sdp_read(sd, 0x5A) & 0x01; 2177 2178 v4l2_info(sd, "Chip powered %s\n", no_power(sd) ? "off" : "on"); 2179 v4l2_info(sd, "Prim-mode = 0x%x, video std = 0x%x\n", 2180 io_read(sd, 0x01) & 0x0f, io_read(sd, 0x00) & 0x3f); 2181 2182 v4l2_info(sd, "SDP: free run: %s\n", 2183 (sdp_read(sd, 0x56) & 0x01) ? "on" : "off"); 2184 v4l2_info(sd, "SDP: %s\n", sdp_signal_detected ? 2185 "valid SD/PR signal detected" : "invalid/no signal"); 2186 if (sdp_signal_detected) { 2187 static const char * const sdp_std_txt[] = { 2188 "NTSC-M/J", 2189 "1?", 2190 "NTSC-443", 2191 "60HzSECAM", 2192 "PAL-M", 2193 "5?", 2194 "PAL-60", 2195 "7?", "8?", "9?", "a?", "b?", 2196 "PAL-CombN", 2197 "d?", 2198 "PAL-BGHID", 2199 "SECAM" 2200 }; 2201 v4l2_info(sd, "SDP: standard %s\n", 2202 sdp_std_txt[sdp_read(sd, 0x52) & 0x0f]); 2203 v4l2_info(sd, "SDP: %s\n", 2204 (sdp_read(sd, 0x59) & 0x08) ? "50Hz" : "60Hz"); 2205 v4l2_info(sd, "SDP: %s\n", 2206 (sdp_read(sd, 0x57) & 0x08) ? "Interlaced" : "Progressive"); 2207 v4l2_info(sd, "SDP: deinterlacer %s\n", 2208 (sdp_read(sd, 0x12) & 0x08) ? "enabled" : "disabled"); 2209 v4l2_info(sd, "SDP: csc %s mode\n", 2210 (sdp_io_read(sd, 0xe0) & 0x40) ? "auto" : "manual"); 2211 } 2212 return 0; 2213 } 2214 2215 static int adv7842_cp_log_status(struct v4l2_subdev *sd) 2216 { 2217 /* CP block */ 2218 struct adv7842_state *state = to_state(sd); 2219 struct v4l2_dv_timings timings; 2220 uint8_t reg_io_0x02 = io_read(sd, 0x02); 2221 uint8_t reg_io_0x21 = io_read(sd, 0x21); 2222 uint8_t reg_rep_0x77 = rep_read(sd, 0x77); 2223 uint8_t reg_rep_0x7d = rep_read(sd, 0x7d); 2224 bool audio_pll_locked = hdmi_read(sd, 0x04) & 0x01; 2225 bool audio_sample_packet_detect = hdmi_read(sd, 0x18) & 0x01; 2226 bool audio_mute = io_read(sd, 0x65) & 0x40; 2227 2228 static const char * const csc_coeff_sel_rb[16] = { 2229 "bypassed", "YPbPr601 -> RGB", "reserved", "YPbPr709 -> RGB", 2230 "reserved", "RGB -> YPbPr601", "reserved", "RGB -> YPbPr709", 2231 "reserved", "YPbPr709 -> YPbPr601", "YPbPr601 -> YPbPr709", 2232 "reserved", "reserved", "reserved", "reserved", "manual" 2233 }; 2234 static const char * const input_color_space_txt[16] = { 2235 "RGB limited range (16-235)", "RGB full range (0-255)", 2236 "YCbCr Bt.601 (16-235)", "YCbCr Bt.709 (16-235)", 2237 "xvYCC Bt.601", "xvYCC Bt.709", 2238 "YCbCr Bt.601 (0-255)", "YCbCr Bt.709 (0-255)", 2239 "invalid", "invalid", "invalid", "invalid", "invalid", 2240 "invalid", "invalid", "automatic" 2241 }; 2242 static const char * const rgb_quantization_range_txt[] = { 2243 "Automatic", 2244 "RGB limited range (16-235)", 2245 "RGB full range (0-255)", 2246 }; 2247 static const char * const deep_color_mode_txt[4] = { 2248 "8-bits per channel", 2249 "10-bits per channel", 2250 "12-bits per channel", 2251 "16-bits per channel (not supported)" 2252 }; 2253 2254 v4l2_info(sd, "-----Chip status-----\n"); 2255 v4l2_info(sd, "Chip power: %s\n", no_power(sd) ? "off" : "on"); 2256 v4l2_info(sd, "HDMI/DVI-D port selected: %s\n", 2257 state->hdmi_port_a ? "A" : "B"); 2258 v4l2_info(sd, "EDID A %s, B %s\n", 2259 ((reg_rep_0x7d & 0x04) && (reg_rep_0x77 & 0x04)) ? 2260 "enabled" : "disabled", 2261 ((reg_rep_0x7d & 0x08) && (reg_rep_0x77 & 0x08)) ? 2262 "enabled" : "disabled"); 2263 v4l2_info(sd, "HPD A %s, B %s\n", 2264 reg_io_0x21 & 0x02 ? "enabled" : "disabled", 2265 reg_io_0x21 & 0x01 ? "enabled" : "disabled"); 2266 v4l2_info(sd, "CEC %s\n", !!(cec_read(sd, 0x2a) & 0x01) ? 2267 "enabled" : "disabled"); 2268 2269 v4l2_info(sd, "-----Signal status-----\n"); 2270 if (state->hdmi_port_a) { 2271 v4l2_info(sd, "Cable detected (+5V power): %s\n", 2272 io_read(sd, 0x6f) & 0x02 ? "true" : "false"); 2273 v4l2_info(sd, "TMDS signal detected: %s\n", 2274 (io_read(sd, 0x6a) & 0x02) ? "true" : "false"); 2275 v4l2_info(sd, "TMDS signal locked: %s\n", 2276 (io_read(sd, 0x6a) & 0x20) ? "true" : "false"); 2277 } else { 2278 v4l2_info(sd, "Cable detected (+5V power):%s\n", 2279 io_read(sd, 0x6f) & 0x01 ? "true" : "false"); 2280 v4l2_info(sd, "TMDS signal detected: %s\n", 2281 (io_read(sd, 0x6a) & 0x01) ? "true" : "false"); 2282 v4l2_info(sd, "TMDS signal locked: %s\n", 2283 (io_read(sd, 0x6a) & 0x10) ? "true" : "false"); 2284 } 2285 v4l2_info(sd, "CP free run: %s\n", 2286 (!!(cp_read(sd, 0xff) & 0x10) ? "on" : "off")); 2287 v4l2_info(sd, "Prim-mode = 0x%x, video std = 0x%x, v_freq = 0x%x\n", 2288 io_read(sd, 0x01) & 0x0f, io_read(sd, 0x00) & 0x3f, 2289 (io_read(sd, 0x01) & 0x70) >> 4); 2290 2291 v4l2_info(sd, "-----Video Timings-----\n"); 2292 if (no_cp_signal(sd)) { 2293 v4l2_info(sd, "STDI: not locked\n"); 2294 } else { 2295 uint32_t bl = ((cp_read(sd, 0xb1) & 0x3f) << 8) | cp_read(sd, 0xb2); 2296 uint32_t lcf = ((cp_read(sd, 0xb3) & 0x7) << 8) | cp_read(sd, 0xb4); 2297 uint32_t lcvs = cp_read(sd, 0xb3) >> 3; 2298 uint32_t fcl = ((cp_read(sd, 0xb8) & 0x1f) << 8) | cp_read(sd, 0xb9); 2299 char hs_pol = ((cp_read(sd, 0xb5) & 0x10) ? 2300 ((cp_read(sd, 0xb5) & 0x08) ? '+' : '-') : 'x'); 2301 char vs_pol = ((cp_read(sd, 0xb5) & 0x40) ? 2302 ((cp_read(sd, 0xb5) & 0x20) ? '+' : '-') : 'x'); 2303 v4l2_info(sd, 2304 "STDI: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, fcl = %d, %s, %chsync, %cvsync\n", 2305 lcf, bl, lcvs, fcl, 2306 (cp_read(sd, 0xb1) & 0x40) ? 2307 "interlaced" : "progressive", 2308 hs_pol, vs_pol); 2309 } 2310 if (adv7842_query_dv_timings(sd, &timings)) 2311 v4l2_info(sd, "No video detected\n"); 2312 else 2313 v4l2_print_dv_timings(sd->name, "Detected format: ", 2314 &timings, true); 2315 v4l2_print_dv_timings(sd->name, "Configured format: ", 2316 &state->timings, true); 2317 2318 if (no_cp_signal(sd)) 2319 return 0; 2320 2321 v4l2_info(sd, "-----Color space-----\n"); 2322 v4l2_info(sd, "RGB quantization range ctrl: %s\n", 2323 rgb_quantization_range_txt[state->rgb_quantization_range]); 2324 v4l2_info(sd, "Input color space: %s\n", 2325 input_color_space_txt[reg_io_0x02 >> 4]); 2326 v4l2_info(sd, "Output color space: %s %s, saturator %s\n", 2327 (reg_io_0x02 & 0x02) ? "RGB" : "YCbCr", 2328 (reg_io_0x02 & 0x04) ? "(16-235)" : "(0-255)", 2329 ((reg_io_0x02 & 0x04) ^ (reg_io_0x02 & 0x01)) ? 2330 "enabled" : "disabled"); 2331 v4l2_info(sd, "Color space conversion: %s\n", 2332 csc_coeff_sel_rb[cp_read(sd, 0xf4) >> 4]); 2333 2334 if (!is_digital_input(sd)) 2335 return 0; 2336 2337 v4l2_info(sd, "-----%s status-----\n", is_hdmi(sd) ? "HDMI" : "DVI-D"); 2338 v4l2_info(sd, "HDCP encrypted content: %s\n", 2339 (hdmi_read(sd, 0x05) & 0x40) ? "true" : "false"); 2340 v4l2_info(sd, "HDCP keys read: %s%s\n", 2341 (hdmi_read(sd, 0x04) & 0x20) ? "yes" : "no", 2342 (hdmi_read(sd, 0x04) & 0x10) ? "ERROR" : ""); 2343 if (!is_hdmi(sd)) 2344 return 0; 2345 2346 v4l2_info(sd, "Audio: pll %s, samples %s, %s\n", 2347 audio_pll_locked ? "locked" : "not locked", 2348 audio_sample_packet_detect ? "detected" : "not detected", 2349 audio_mute ? "muted" : "enabled"); 2350 if (audio_pll_locked && audio_sample_packet_detect) { 2351 v4l2_info(sd, "Audio format: %s\n", 2352 (hdmi_read(sd, 0x07) & 0x40) ? "multi-channel" : "stereo"); 2353 } 2354 v4l2_info(sd, "Audio CTS: %u\n", (hdmi_read(sd, 0x5b) << 12) + 2355 (hdmi_read(sd, 0x5c) << 8) + 2356 (hdmi_read(sd, 0x5d) & 0xf0)); 2357 v4l2_info(sd, "Audio N: %u\n", ((hdmi_read(sd, 0x5d) & 0x0f) << 16) + 2358 (hdmi_read(sd, 0x5e) << 8) + 2359 hdmi_read(sd, 0x5f)); 2360 v4l2_info(sd, "AV Mute: %s\n", 2361 (hdmi_read(sd, 0x04) & 0x40) ? "on" : "off"); 2362 v4l2_info(sd, "Deep color mode: %s\n", 2363 deep_color_mode_txt[hdmi_read(sd, 0x0b) >> 6]); 2364 2365 print_avi_infoframe(sd); 2366 return 0; 2367 } 2368 2369 static int adv7842_log_status(struct v4l2_subdev *sd) 2370 { 2371 struct adv7842_state *state = to_state(sd); 2372 2373 if (state->mode == ADV7842_MODE_SDP) 2374 return adv7842_sdp_log_status(sd); 2375 return adv7842_cp_log_status(sd); 2376 } 2377 2378 static int adv7842_querystd(struct v4l2_subdev *sd, v4l2_std_id *std) 2379 { 2380 struct adv7842_state *state = to_state(sd); 2381 2382 v4l2_dbg(1, debug, sd, "%s:\n", __func__); 2383 2384 if (state->mode != ADV7842_MODE_SDP) 2385 return -ENODATA; 2386 2387 if (!(sdp_read(sd, 0x5A) & 0x01)) { 2388 *std = 0; 2389 v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__); 2390 return 0; 2391 } 2392 2393 switch (sdp_read(sd, 0x52) & 0x0f) { 2394 case 0: 2395 /* NTSC-M/J */ 2396 *std &= V4L2_STD_NTSC; 2397 break; 2398 case 2: 2399 /* NTSC-443 */ 2400 *std &= V4L2_STD_NTSC_443; 2401 break; 2402 case 3: 2403 /* 60HzSECAM */ 2404 *std &= V4L2_STD_SECAM; 2405 break; 2406 case 4: 2407 /* PAL-M */ 2408 *std &= V4L2_STD_PAL_M; 2409 break; 2410 case 6: 2411 /* PAL-60 */ 2412 *std &= V4L2_STD_PAL_60; 2413 break; 2414 case 0xc: 2415 /* PAL-CombN */ 2416 *std &= V4L2_STD_PAL_Nc; 2417 break; 2418 case 0xe: 2419 /* PAL-BGHID */ 2420 *std &= V4L2_STD_PAL; 2421 break; 2422 case 0xf: 2423 /* SECAM */ 2424 *std &= V4L2_STD_SECAM; 2425 break; 2426 default: 2427 *std &= V4L2_STD_ALL; 2428 break; 2429 } 2430 return 0; 2431 } 2432 2433 static void adv7842_s_sdp_io(struct v4l2_subdev *sd, struct adv7842_sdp_io_sync_adjustment *s) 2434 { 2435 if (s && s->adjust) { 2436 sdp_io_write(sd, 0x94, (s->hs_beg >> 8) & 0xf); 2437 sdp_io_write(sd, 0x95, s->hs_beg & 0xff); 2438 sdp_io_write(sd, 0x96, (s->hs_width >> 8) & 0xf); 2439 sdp_io_write(sd, 0x97, s->hs_width & 0xff); 2440 sdp_io_write(sd, 0x98, (s->de_beg >> 8) & 0xf); 2441 sdp_io_write(sd, 0x99, s->de_beg & 0xff); 2442 sdp_io_write(sd, 0x9a, (s->de_end >> 8) & 0xf); 2443 sdp_io_write(sd, 0x9b, s->de_end & 0xff); 2444 sdp_io_write(sd, 0xa8, s->vs_beg_o); 2445 sdp_io_write(sd, 0xa9, s->vs_beg_e); 2446 sdp_io_write(sd, 0xaa, s->vs_end_o); 2447 sdp_io_write(sd, 0xab, s->vs_end_e); 2448 sdp_io_write(sd, 0xac, s->de_v_beg_o); 2449 sdp_io_write(sd, 0xad, s->de_v_beg_e); 2450 sdp_io_write(sd, 0xae, s->de_v_end_o); 2451 sdp_io_write(sd, 0xaf, s->de_v_end_e); 2452 } else { 2453 /* set to default */ 2454 sdp_io_write(sd, 0x94, 0x00); 2455 sdp_io_write(sd, 0x95, 0x00); 2456 sdp_io_write(sd, 0x96, 0x00); 2457 sdp_io_write(sd, 0x97, 0x20); 2458 sdp_io_write(sd, 0x98, 0x00); 2459 sdp_io_write(sd, 0x99, 0x00); 2460 sdp_io_write(sd, 0x9a, 0x00); 2461 sdp_io_write(sd, 0x9b, 0x00); 2462 sdp_io_write(sd, 0xa8, 0x04); 2463 sdp_io_write(sd, 0xa9, 0x04); 2464 sdp_io_write(sd, 0xaa, 0x04); 2465 sdp_io_write(sd, 0xab, 0x04); 2466 sdp_io_write(sd, 0xac, 0x04); 2467 sdp_io_write(sd, 0xad, 0x04); 2468 sdp_io_write(sd, 0xae, 0x04); 2469 sdp_io_write(sd, 0xaf, 0x04); 2470 } 2471 } 2472 2473 static int adv7842_s_std(struct v4l2_subdev *sd, v4l2_std_id norm) 2474 { 2475 struct adv7842_state *state = to_state(sd); 2476 struct adv7842_platform_data *pdata = &state->pdata; 2477 2478 v4l2_dbg(1, debug, sd, "%s:\n", __func__); 2479 2480 if (state->mode != ADV7842_MODE_SDP) 2481 return -ENODATA; 2482 2483 if (norm & V4L2_STD_625_50) 2484 adv7842_s_sdp_io(sd, &pdata->sdp_io_sync_625); 2485 else if (norm & V4L2_STD_525_60) 2486 adv7842_s_sdp_io(sd, &pdata->sdp_io_sync_525); 2487 else 2488 adv7842_s_sdp_io(sd, NULL); 2489 2490 if (norm & V4L2_STD_ALL) { 2491 state->norm = norm; 2492 return 0; 2493 } 2494 return -EINVAL; 2495 } 2496 2497 static int adv7842_g_std(struct v4l2_subdev *sd, v4l2_std_id *norm) 2498 { 2499 struct adv7842_state *state = to_state(sd); 2500 2501 v4l2_dbg(1, debug, sd, "%s:\n", __func__); 2502 2503 if (state->mode != ADV7842_MODE_SDP) 2504 return -ENODATA; 2505 2506 *norm = state->norm; 2507 return 0; 2508 } 2509 2510 /* ----------------------------------------------------------------------- */ 2511 2512 static int adv7842_core_init(struct v4l2_subdev *sd) 2513 { 2514 struct adv7842_state *state = to_state(sd); 2515 struct adv7842_platform_data *pdata = &state->pdata; 2516 hdmi_write(sd, 0x48, 2517 (pdata->disable_pwrdnb ? 0x80 : 0) | 2518 (pdata->disable_cable_det_rst ? 0x40 : 0)); 2519 2520 disable_input(sd); 2521 2522 /* power */ 2523 io_write(sd, 0x0c, 0x42); /* Power up part and power down VDP */ 2524 io_write(sd, 0x15, 0x80); /* Power up pads */ 2525 2526 /* video format */ 2527 io_write(sd, 0x02, 2528 0xf0 | 2529 pdata->alt_gamma << 3 | 2530 pdata->op_656_range << 2 | 2531 pdata->rgb_out << 1 | 2532 pdata->alt_data_sat << 0); 2533 io_write(sd, 0x03, pdata->op_format_sel); 2534 io_write_and_or(sd, 0x04, 0x1f, pdata->op_ch_sel << 5); 2535 io_write_and_or(sd, 0x05, 0xf0, pdata->blank_data << 3 | 2536 pdata->insert_av_codes << 2 | 2537 pdata->replicate_av_codes << 1 | 2538 pdata->invert_cbcr << 0); 2539 2540 /* HDMI audio */ 2541 hdmi_write_and_or(sd, 0x1a, 0xf1, 0x08); /* Wait 1 s before unmute */ 2542 2543 /* Drive strength */ 2544 io_write_and_or(sd, 0x14, 0xc0, 2545 pdata->dr_str_data << 4 | 2546 pdata->dr_str_clk << 2 | 2547 pdata->dr_str_sync); 2548 2549 /* HDMI free run */ 2550 cp_write_and_or(sd, 0xba, 0xfc, pdata->hdmi_free_run_enable | 2551 (pdata->hdmi_free_run_mode << 1)); 2552 2553 /* SPD free run */ 2554 sdp_write_and_or(sd, 0xdd, 0xf0, pdata->sdp_free_run_force | 2555 (pdata->sdp_free_run_cbar_en << 1) | 2556 (pdata->sdp_free_run_man_col_en << 2) | 2557 (pdata->sdp_free_run_force << 3)); 2558 2559 /* TODO from platform data */ 2560 cp_write(sd, 0x69, 0x14); /* Enable CP CSC */ 2561 io_write(sd, 0x06, 0xa6); /* positive VS and HS and DE */ 2562 cp_write(sd, 0xf3, 0xdc); /* Low threshold to enter/exit free run mode */ 2563 afe_write(sd, 0xb5, 0x01); /* Setting MCLK to 256Fs */ 2564 2565 afe_write(sd, 0x02, pdata->ain_sel); /* Select analog input muxing mode */ 2566 io_write_and_or(sd, 0x30, ~(1 << 4), pdata->output_bus_lsb_to_msb << 4); 2567 2568 sdp_csc_coeff(sd, &pdata->sdp_csc_coeff); 2569 2570 /* todo, improve settings for sdram */ 2571 if (pdata->sd_ram_size >= 128) { 2572 sdp_write(sd, 0x12, 0x0d); /* Frame TBC,3D comb enabled */ 2573 if (pdata->sd_ram_ddr) { 2574 /* SDP setup for the AD eval board */ 2575 sdp_io_write(sd, 0x6f, 0x00); /* DDR mode */ 2576 sdp_io_write(sd, 0x75, 0x0a); /* 128 MB memory size */ 2577 sdp_io_write(sd, 0x7a, 0xa5); /* Timing Adjustment */ 2578 sdp_io_write(sd, 0x7b, 0x8f); /* Timing Adjustment */ 2579 sdp_io_write(sd, 0x60, 0x01); /* SDRAM reset */ 2580 } else { 2581 sdp_io_write(sd, 0x75, 0x0a); /* 64 MB memory size ?*/ 2582 sdp_io_write(sd, 0x74, 0x00); /* must be zero for sdr sdram */ 2583 sdp_io_write(sd, 0x79, 0x33); /* CAS latency to 3, 2584 depends on memory */ 2585 sdp_io_write(sd, 0x6f, 0x01); /* SDR mode */ 2586 sdp_io_write(sd, 0x7a, 0xa5); /* Timing Adjustment */ 2587 sdp_io_write(sd, 0x7b, 0x8f); /* Timing Adjustment */ 2588 sdp_io_write(sd, 0x60, 0x01); /* SDRAM reset */ 2589 } 2590 } else { 2591 /* 2592 * Manual UG-214, rev 0 is bit confusing on this bit 2593 * but a '1' disables any signal if the Ram is active. 2594 */ 2595 sdp_io_write(sd, 0x29, 0x10); /* Tristate memory interface */ 2596 } 2597 2598 select_input(sd, pdata->vid_std_select); 2599 2600 enable_input(sd); 2601 2602 /* disable I2C access to internal EDID ram from HDMI DDC ports */ 2603 rep_write_and_or(sd, 0x77, 0xf3, 0x00); 2604 2605 hdmi_write(sd, 0x69, 0xa3); /* HPA manual */ 2606 /* HPA disable on port A and B */ 2607 io_write_and_or(sd, 0x20, 0xcf, 0x00); 2608 2609 /* LLC */ 2610 io_write(sd, 0x19, 0x80 | pdata->llc_dll_phase); 2611 io_write(sd, 0x33, 0x40); 2612 2613 /* interrupts */ 2614 io_write(sd, 0x40, 0xf2); /* Configure INT1 */ 2615 2616 adv7842_irq_enable(sd, true); 2617 2618 return v4l2_ctrl_handler_setup(sd->ctrl_handler); 2619 } 2620 2621 /* ----------------------------------------------------------------------- */ 2622 2623 static int adv7842_ddr_ram_test(struct v4l2_subdev *sd) 2624 { 2625 /* 2626 * From ADV784x external Memory test.pdf 2627 * 2628 * Reset must just been performed before running test. 2629 * Recommended to reset after test. 2630 */ 2631 int i; 2632 int pass = 0; 2633 int fail = 0; 2634 int complete = 0; 2635 2636 io_write(sd, 0x00, 0x01); /* Program SDP 4x1 */ 2637 io_write(sd, 0x01, 0x00); /* Program SDP mode */ 2638 afe_write(sd, 0x80, 0x92); /* SDP Recommeneded Write */ 2639 afe_write(sd, 0x9B, 0x01); /* SDP Recommeneded Write ADV7844ES1 */ 2640 afe_write(sd, 0x9C, 0x60); /* SDP Recommeneded Write ADV7844ES1 */ 2641 afe_write(sd, 0x9E, 0x02); /* SDP Recommeneded Write ADV7844ES1 */ 2642 afe_write(sd, 0xA0, 0x0B); /* SDP Recommeneded Write ADV7844ES1 */ 2643 afe_write(sd, 0xC3, 0x02); /* Memory BIST Initialisation */ 2644 io_write(sd, 0x0C, 0x40); /* Power up ADV7844 */ 2645 io_write(sd, 0x15, 0xBA); /* Enable outputs */ 2646 sdp_write(sd, 0x12, 0x00); /* Disable 3D comb, Frame TBC & 3DNR */ 2647 io_write(sd, 0xFF, 0x04); /* Reset memory controller */ 2648 2649 mdelay(5); 2650 2651 sdp_write(sd, 0x12, 0x00); /* Disable 3D Comb, Frame TBC & 3DNR */ 2652 sdp_io_write(sd, 0x2A, 0x01); /* Memory BIST Initialisation */ 2653 sdp_io_write(sd, 0x7c, 0x19); /* Memory BIST Initialisation */ 2654 sdp_io_write(sd, 0x80, 0x87); /* Memory BIST Initialisation */ 2655 sdp_io_write(sd, 0x81, 0x4a); /* Memory BIST Initialisation */ 2656 sdp_io_write(sd, 0x82, 0x2c); /* Memory BIST Initialisation */ 2657 sdp_io_write(sd, 0x83, 0x0e); /* Memory BIST Initialisation */ 2658 sdp_io_write(sd, 0x84, 0x94); /* Memory BIST Initialisation */ 2659 sdp_io_write(sd, 0x85, 0x62); /* Memory BIST Initialisation */ 2660 sdp_io_write(sd, 0x7d, 0x00); /* Memory BIST Initialisation */ 2661 sdp_io_write(sd, 0x7e, 0x1a); /* Memory BIST Initialisation */ 2662 2663 mdelay(5); 2664 2665 sdp_io_write(sd, 0xd9, 0xd5); /* Enable BIST Test */ 2666 sdp_write(sd, 0x12, 0x05); /* Enable FRAME TBC & 3D COMB */ 2667 2668 mdelay(20); 2669 2670 for (i = 0; i < 10; i++) { 2671 u8 result = sdp_io_read(sd, 0xdb); 2672 if (result & 0x10) { 2673 complete++; 2674 if (result & 0x20) 2675 fail++; 2676 else 2677 pass++; 2678 } 2679 mdelay(20); 2680 } 2681 2682 v4l2_dbg(1, debug, sd, 2683 "Ram Test: completed %d of %d: pass %d, fail %d\n", 2684 complete, i, pass, fail); 2685 2686 if (!complete || fail) 2687 return -EIO; 2688 return 0; 2689 } 2690 2691 static void adv7842_rewrite_i2c_addresses(struct v4l2_subdev *sd, 2692 struct adv7842_platform_data *pdata) 2693 { 2694 io_write(sd, 0xf1, pdata->i2c_sdp << 1); 2695 io_write(sd, 0xf2, pdata->i2c_sdp_io << 1); 2696 io_write(sd, 0xf3, pdata->i2c_avlink << 1); 2697 io_write(sd, 0xf4, pdata->i2c_cec << 1); 2698 io_write(sd, 0xf5, pdata->i2c_infoframe << 1); 2699 2700 io_write(sd, 0xf8, pdata->i2c_afe << 1); 2701 io_write(sd, 0xf9, pdata->i2c_repeater << 1); 2702 io_write(sd, 0xfa, pdata->i2c_edid << 1); 2703 io_write(sd, 0xfb, pdata->i2c_hdmi << 1); 2704 2705 io_write(sd, 0xfd, pdata->i2c_cp << 1); 2706 io_write(sd, 0xfe, pdata->i2c_vdp << 1); 2707 } 2708 2709 static int adv7842_command_ram_test(struct v4l2_subdev *sd) 2710 { 2711 struct i2c_client *client = v4l2_get_subdevdata(sd); 2712 struct adv7842_state *state = to_state(sd); 2713 struct adv7842_platform_data *pdata = client->dev.platform_data; 2714 struct v4l2_dv_timings timings; 2715 int ret = 0; 2716 2717 if (!pdata) 2718 return -ENODEV; 2719 2720 if (!pdata->sd_ram_size || !pdata->sd_ram_ddr) { 2721 v4l2_info(sd, "no sdram or no ddr sdram\n"); 2722 return -EINVAL; 2723 } 2724 2725 main_reset(sd); 2726 2727 adv7842_rewrite_i2c_addresses(sd, pdata); 2728 2729 /* run ram test */ 2730 ret = adv7842_ddr_ram_test(sd); 2731 2732 main_reset(sd); 2733 2734 adv7842_rewrite_i2c_addresses(sd, pdata); 2735 2736 /* and re-init chip and state */ 2737 adv7842_core_init(sd); 2738 2739 disable_input(sd); 2740 2741 select_input(sd, state->vid_std_select); 2742 2743 enable_input(sd); 2744 2745 edid_write_vga_segment(sd); 2746 edid_write_hdmi_segment(sd, ADV7842_EDID_PORT_A); 2747 edid_write_hdmi_segment(sd, ADV7842_EDID_PORT_B); 2748 2749 timings = state->timings; 2750 2751 memset(&state->timings, 0, sizeof(struct v4l2_dv_timings)); 2752 2753 adv7842_s_dv_timings(sd, &timings); 2754 2755 return ret; 2756 } 2757 2758 static long adv7842_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg) 2759 { 2760 switch (cmd) { 2761 case ADV7842_CMD_RAM_TEST: 2762 return adv7842_command_ram_test(sd); 2763 } 2764 return -ENOTTY; 2765 } 2766 2767 /* ----------------------------------------------------------------------- */ 2768 2769 static const struct v4l2_ctrl_ops adv7842_ctrl_ops = { 2770 .s_ctrl = adv7842_s_ctrl, 2771 }; 2772 2773 static const struct v4l2_subdev_core_ops adv7842_core_ops = { 2774 .log_status = adv7842_log_status, 2775 .g_std = adv7842_g_std, 2776 .s_std = adv7842_s_std, 2777 .ioctl = adv7842_ioctl, 2778 .interrupt_service_routine = adv7842_isr, 2779 #ifdef CONFIG_VIDEO_ADV_DEBUG 2780 .g_register = adv7842_g_register, 2781 .s_register = adv7842_s_register, 2782 #endif 2783 }; 2784 2785 static const struct v4l2_subdev_video_ops adv7842_video_ops = { 2786 .s_routing = adv7842_s_routing, 2787 .querystd = adv7842_querystd, 2788 .g_input_status = adv7842_g_input_status, 2789 .s_dv_timings = adv7842_s_dv_timings, 2790 .g_dv_timings = adv7842_g_dv_timings, 2791 .query_dv_timings = adv7842_query_dv_timings, 2792 .enum_dv_timings = adv7842_enum_dv_timings, 2793 .dv_timings_cap = adv7842_dv_timings_cap, 2794 .enum_mbus_fmt = adv7842_enum_mbus_fmt, 2795 .g_mbus_fmt = adv7842_g_mbus_fmt, 2796 .try_mbus_fmt = adv7842_g_mbus_fmt, 2797 .s_mbus_fmt = adv7842_g_mbus_fmt, 2798 }; 2799 2800 static const struct v4l2_subdev_pad_ops adv7842_pad_ops = { 2801 .get_edid = adv7842_get_edid, 2802 .set_edid = adv7842_set_edid, 2803 }; 2804 2805 static const struct v4l2_subdev_ops adv7842_ops = { 2806 .core = &adv7842_core_ops, 2807 .video = &adv7842_video_ops, 2808 .pad = &adv7842_pad_ops, 2809 }; 2810 2811 /* -------------------------- custom ctrls ---------------------------------- */ 2812 2813 static const struct v4l2_ctrl_config adv7842_ctrl_analog_sampling_phase = { 2814 .ops = &adv7842_ctrl_ops, 2815 .id = V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE, 2816 .name = "Analog Sampling Phase", 2817 .type = V4L2_CTRL_TYPE_INTEGER, 2818 .min = 0, 2819 .max = 0x1f, 2820 .step = 1, 2821 .def = 0, 2822 }; 2823 2824 static const struct v4l2_ctrl_config adv7842_ctrl_free_run_color_manual = { 2825 .ops = &adv7842_ctrl_ops, 2826 .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL, 2827 .name = "Free Running Color, Manual", 2828 .type = V4L2_CTRL_TYPE_BOOLEAN, 2829 .max = 1, 2830 .step = 1, 2831 .def = 1, 2832 }; 2833 2834 static const struct v4l2_ctrl_config adv7842_ctrl_free_run_color = { 2835 .ops = &adv7842_ctrl_ops, 2836 .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR, 2837 .name = "Free Running Color", 2838 .type = V4L2_CTRL_TYPE_INTEGER, 2839 .max = 0xffffff, 2840 .step = 0x1, 2841 }; 2842 2843 2844 static void adv7842_unregister_clients(struct v4l2_subdev *sd) 2845 { 2846 struct adv7842_state *state = to_state(sd); 2847 if (state->i2c_avlink) 2848 i2c_unregister_device(state->i2c_avlink); 2849 if (state->i2c_cec) 2850 i2c_unregister_device(state->i2c_cec); 2851 if (state->i2c_infoframe) 2852 i2c_unregister_device(state->i2c_infoframe); 2853 if (state->i2c_sdp_io) 2854 i2c_unregister_device(state->i2c_sdp_io); 2855 if (state->i2c_sdp) 2856 i2c_unregister_device(state->i2c_sdp); 2857 if (state->i2c_afe) 2858 i2c_unregister_device(state->i2c_afe); 2859 if (state->i2c_repeater) 2860 i2c_unregister_device(state->i2c_repeater); 2861 if (state->i2c_edid) 2862 i2c_unregister_device(state->i2c_edid); 2863 if (state->i2c_hdmi) 2864 i2c_unregister_device(state->i2c_hdmi); 2865 if (state->i2c_cp) 2866 i2c_unregister_device(state->i2c_cp); 2867 if (state->i2c_vdp) 2868 i2c_unregister_device(state->i2c_vdp); 2869 2870 state->i2c_avlink = NULL; 2871 state->i2c_cec = NULL; 2872 state->i2c_infoframe = NULL; 2873 state->i2c_sdp_io = NULL; 2874 state->i2c_sdp = NULL; 2875 state->i2c_afe = NULL; 2876 state->i2c_repeater = NULL; 2877 state->i2c_edid = NULL; 2878 state->i2c_hdmi = NULL; 2879 state->i2c_cp = NULL; 2880 state->i2c_vdp = NULL; 2881 } 2882 2883 static struct i2c_client *adv7842_dummy_client(struct v4l2_subdev *sd, const char *desc, 2884 u8 addr, u8 io_reg) 2885 { 2886 struct i2c_client *client = v4l2_get_subdevdata(sd); 2887 struct i2c_client *cp; 2888 2889 io_write(sd, io_reg, addr << 1); 2890 2891 if (addr == 0) { 2892 v4l2_err(sd, "no %s i2c addr configured\n", desc); 2893 return NULL; 2894 } 2895 2896 cp = i2c_new_dummy(client->adapter, io_read(sd, io_reg) >> 1); 2897 if (!cp) 2898 v4l2_err(sd, "register %s on i2c addr 0x%x failed\n", desc, addr); 2899 2900 return cp; 2901 } 2902 2903 static int adv7842_register_clients(struct v4l2_subdev *sd) 2904 { 2905 struct adv7842_state *state = to_state(sd); 2906 struct adv7842_platform_data *pdata = &state->pdata; 2907 2908 state->i2c_avlink = adv7842_dummy_client(sd, "avlink", pdata->i2c_avlink, 0xf3); 2909 state->i2c_cec = adv7842_dummy_client(sd, "cec", pdata->i2c_cec, 0xf4); 2910 state->i2c_infoframe = adv7842_dummy_client(sd, "infoframe", pdata->i2c_infoframe, 0xf5); 2911 state->i2c_sdp_io = adv7842_dummy_client(sd, "sdp_io", pdata->i2c_sdp_io, 0xf2); 2912 state->i2c_sdp = adv7842_dummy_client(sd, "sdp", pdata->i2c_sdp, 0xf1); 2913 state->i2c_afe = adv7842_dummy_client(sd, "afe", pdata->i2c_afe, 0xf8); 2914 state->i2c_repeater = adv7842_dummy_client(sd, "repeater", pdata->i2c_repeater, 0xf9); 2915 state->i2c_edid = adv7842_dummy_client(sd, "edid", pdata->i2c_edid, 0xfa); 2916 state->i2c_hdmi = adv7842_dummy_client(sd, "hdmi", pdata->i2c_hdmi, 0xfb); 2917 state->i2c_cp = adv7842_dummy_client(sd, "cp", pdata->i2c_cp, 0xfd); 2918 state->i2c_vdp = adv7842_dummy_client(sd, "vdp", pdata->i2c_vdp, 0xfe); 2919 2920 if (!state->i2c_avlink || 2921 !state->i2c_cec || 2922 !state->i2c_infoframe || 2923 !state->i2c_sdp_io || 2924 !state->i2c_sdp || 2925 !state->i2c_afe || 2926 !state->i2c_repeater || 2927 !state->i2c_edid || 2928 !state->i2c_hdmi || 2929 !state->i2c_cp || 2930 !state->i2c_vdp) 2931 return -1; 2932 2933 return 0; 2934 } 2935 2936 static int adv7842_probe(struct i2c_client *client, 2937 const struct i2c_device_id *id) 2938 { 2939 struct adv7842_state *state; 2940 static const struct v4l2_dv_timings cea640x480 = 2941 V4L2_DV_BT_CEA_640X480P59_94; 2942 struct adv7842_platform_data *pdata = client->dev.platform_data; 2943 struct v4l2_ctrl_handler *hdl; 2944 struct v4l2_subdev *sd; 2945 u16 rev; 2946 int err; 2947 2948 /* Check if the adapter supports the needed features */ 2949 if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA)) 2950 return -EIO; 2951 2952 v4l_dbg(1, debug, client, "detecting adv7842 client on address 0x%x\n", 2953 client->addr << 1); 2954 2955 if (!pdata) { 2956 v4l_err(client, "No platform data!\n"); 2957 return -ENODEV; 2958 } 2959 2960 state = devm_kzalloc(&client->dev, sizeof(struct adv7842_state), GFP_KERNEL); 2961 if (!state) { 2962 v4l_err(client, "Could not allocate adv7842_state memory!\n"); 2963 return -ENOMEM; 2964 } 2965 2966 /* platform data */ 2967 state->pdata = *pdata; 2968 state->timings = cea640x480; 2969 2970 sd = &state->sd; 2971 v4l2_i2c_subdev_init(sd, client, &adv7842_ops); 2972 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; 2973 state->mode = pdata->mode; 2974 2975 state->hdmi_port_a = pdata->input == ADV7842_SELECT_HDMI_PORT_A; 2976 state->restart_stdi_once = true; 2977 2978 /* i2c access to adv7842? */ 2979 rev = adv_smbus_read_byte_data_check(client, 0xea, false) << 8 | 2980 adv_smbus_read_byte_data_check(client, 0xeb, false); 2981 if (rev != 0x2012) { 2982 v4l2_info(sd, "got rev=0x%04x on first read attempt\n", rev); 2983 rev = adv_smbus_read_byte_data_check(client, 0xea, false) << 8 | 2984 adv_smbus_read_byte_data_check(client, 0xeb, false); 2985 } 2986 if (rev != 0x2012) { 2987 v4l2_info(sd, "not an adv7842 on address 0x%x (rev=0x%04x)\n", 2988 client->addr << 1, rev); 2989 return -ENODEV; 2990 } 2991 2992 if (pdata->chip_reset) 2993 main_reset(sd); 2994 2995 /* control handlers */ 2996 hdl = &state->hdl; 2997 v4l2_ctrl_handler_init(hdl, 6); 2998 2999 /* add in ascending ID order */ 3000 v4l2_ctrl_new_std(hdl, &adv7842_ctrl_ops, 3001 V4L2_CID_BRIGHTNESS, -128, 127, 1, 0); 3002 v4l2_ctrl_new_std(hdl, &adv7842_ctrl_ops, 3003 V4L2_CID_CONTRAST, 0, 255, 1, 128); 3004 v4l2_ctrl_new_std(hdl, &adv7842_ctrl_ops, 3005 V4L2_CID_SATURATION, 0, 255, 1, 128); 3006 v4l2_ctrl_new_std(hdl, &adv7842_ctrl_ops, 3007 V4L2_CID_HUE, 0, 128, 1, 0); 3008 3009 /* custom controls */ 3010 state->detect_tx_5v_ctrl = v4l2_ctrl_new_std(hdl, NULL, 3011 V4L2_CID_DV_RX_POWER_PRESENT, 0, 3, 0, 0); 3012 state->analog_sampling_phase_ctrl = v4l2_ctrl_new_custom(hdl, 3013 &adv7842_ctrl_analog_sampling_phase, NULL); 3014 state->free_run_color_ctrl_manual = v4l2_ctrl_new_custom(hdl, 3015 &adv7842_ctrl_free_run_color_manual, NULL); 3016 state->free_run_color_ctrl = v4l2_ctrl_new_custom(hdl, 3017 &adv7842_ctrl_free_run_color, NULL); 3018 state->rgb_quantization_range_ctrl = 3019 v4l2_ctrl_new_std_menu(hdl, &adv7842_ctrl_ops, 3020 V4L2_CID_DV_RX_RGB_RANGE, V4L2_DV_RGB_RANGE_FULL, 3021 0, V4L2_DV_RGB_RANGE_AUTO); 3022 sd->ctrl_handler = hdl; 3023 if (hdl->error) { 3024 err = hdl->error; 3025 goto err_hdl; 3026 } 3027 state->detect_tx_5v_ctrl->is_private = true; 3028 state->rgb_quantization_range_ctrl->is_private = true; 3029 state->analog_sampling_phase_ctrl->is_private = true; 3030 state->free_run_color_ctrl_manual->is_private = true; 3031 state->free_run_color_ctrl->is_private = true; 3032 3033 if (adv7842_s_detect_tx_5v_ctrl(sd)) { 3034 err = -ENODEV; 3035 goto err_hdl; 3036 } 3037 3038 if (adv7842_register_clients(sd) < 0) { 3039 err = -ENOMEM; 3040 v4l2_err(sd, "failed to create all i2c clients\n"); 3041 goto err_i2c; 3042 } 3043 3044 /* work queues */ 3045 state->work_queues = create_singlethread_workqueue(client->name); 3046 if (!state->work_queues) { 3047 v4l2_err(sd, "Could not create work queue\n"); 3048 err = -ENOMEM; 3049 goto err_i2c; 3050 } 3051 3052 INIT_DELAYED_WORK(&state->delayed_work_enable_hotplug, 3053 adv7842_delayed_work_enable_hotplug); 3054 3055 state->pad.flags = MEDIA_PAD_FL_SOURCE; 3056 err = media_entity_init(&sd->entity, 1, &state->pad, 0); 3057 if (err) 3058 goto err_work_queues; 3059 3060 err = adv7842_core_init(sd); 3061 if (err) 3062 goto err_entity; 3063 3064 v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name, 3065 client->addr << 1, client->adapter->name); 3066 return 0; 3067 3068 err_entity: 3069 media_entity_cleanup(&sd->entity); 3070 err_work_queues: 3071 cancel_delayed_work(&state->delayed_work_enable_hotplug); 3072 destroy_workqueue(state->work_queues); 3073 err_i2c: 3074 adv7842_unregister_clients(sd); 3075 err_hdl: 3076 v4l2_ctrl_handler_free(hdl); 3077 return err; 3078 } 3079 3080 /* ----------------------------------------------------------------------- */ 3081 3082 static int adv7842_remove(struct i2c_client *client) 3083 { 3084 struct v4l2_subdev *sd = i2c_get_clientdata(client); 3085 struct adv7842_state *state = to_state(sd); 3086 3087 adv7842_irq_enable(sd, false); 3088 3089 cancel_delayed_work(&state->delayed_work_enable_hotplug); 3090 destroy_workqueue(state->work_queues); 3091 v4l2_device_unregister_subdev(sd); 3092 media_entity_cleanup(&sd->entity); 3093 adv7842_unregister_clients(sd); 3094 v4l2_ctrl_handler_free(sd->ctrl_handler); 3095 return 0; 3096 } 3097 3098 /* ----------------------------------------------------------------------- */ 3099 3100 static struct i2c_device_id adv7842_id[] = { 3101 { "adv7842", 0 }, 3102 { } 3103 }; 3104 MODULE_DEVICE_TABLE(i2c, adv7842_id); 3105 3106 /* ----------------------------------------------------------------------- */ 3107 3108 static struct i2c_driver adv7842_driver = { 3109 .driver = { 3110 .owner = THIS_MODULE, 3111 .name = "adv7842", 3112 }, 3113 .probe = adv7842_probe, 3114 .remove = adv7842_remove, 3115 .id_table = adv7842_id, 3116 }; 3117 3118 module_i2c_driver(adv7842_driver); 3119