1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * adv7842 - Analog Devices ADV7842 video decoder driver 4 * 5 * Copyright 2013 Cisco Systems, Inc. and/or its affiliates. All rights reserved. 6 */ 7 8 /* 9 * References (c = chapter, p = page): 10 * REF_01 - Analog devices, ADV7842, 11 * Register Settings Recommendations, Rev. 1.9, April 2011 12 * REF_02 - Analog devices, Software User Guide, UG-206, 13 * ADV7842 I2C Register Maps, Rev. 0, November 2010 14 * REF_03 - Analog devices, Hardware User Guide, UG-214, 15 * ADV7842 Fast Switching 2:1 HDMI 1.4 Receiver with 3D-Comb 16 * Decoder and Digitizer , Rev. 0, January 2011 17 */ 18 19 20 #include <linux/kernel.h> 21 #include <linux/module.h> 22 #include <linux/slab.h> 23 #include <linux/i2c.h> 24 #include <linux/delay.h> 25 #include <linux/videodev2.h> 26 #include <linux/workqueue.h> 27 #include <linux/v4l2-dv-timings.h> 28 #include <linux/hdmi.h> 29 #include <media/cec.h> 30 #include <media/v4l2-device.h> 31 #include <media/v4l2-event.h> 32 #include <media/v4l2-ctrls.h> 33 #include <media/v4l2-dv-timings.h> 34 #include <media/i2c/adv7842.h> 35 36 static int debug; 37 module_param(debug, int, 0644); 38 MODULE_PARM_DESC(debug, "debug level (0-2)"); 39 40 MODULE_DESCRIPTION("Analog Devices ADV7842 video decoder driver"); 41 MODULE_AUTHOR("Hans Verkuil <hans.verkuil@cisco.com>"); 42 MODULE_AUTHOR("Martin Bugge <marbugge@cisco.com>"); 43 MODULE_LICENSE("GPL"); 44 45 /* ADV7842 system clock frequency */ 46 #define ADV7842_fsc (28636360) 47 48 #define ADV7842_RGB_OUT (1 << 1) 49 50 #define ADV7842_OP_FORMAT_SEL_8BIT (0 << 0) 51 #define ADV7842_OP_FORMAT_SEL_10BIT (1 << 0) 52 #define ADV7842_OP_FORMAT_SEL_12BIT (2 << 0) 53 54 #define ADV7842_OP_MODE_SEL_SDR_422 (0 << 5) 55 #define ADV7842_OP_MODE_SEL_DDR_422 (1 << 5) 56 #define ADV7842_OP_MODE_SEL_SDR_444 (2 << 5) 57 #define ADV7842_OP_MODE_SEL_DDR_444 (3 << 5) 58 #define ADV7842_OP_MODE_SEL_SDR_422_2X (4 << 5) 59 #define ADV7842_OP_MODE_SEL_ADI_CM (5 << 5) 60 61 #define ADV7842_OP_CH_SEL_GBR (0 << 5) 62 #define ADV7842_OP_CH_SEL_GRB (1 << 5) 63 #define ADV7842_OP_CH_SEL_BGR (2 << 5) 64 #define ADV7842_OP_CH_SEL_RGB (3 << 5) 65 #define ADV7842_OP_CH_SEL_BRG (4 << 5) 66 #define ADV7842_OP_CH_SEL_RBG (5 << 5) 67 68 #define ADV7842_OP_SWAP_CB_CR (1 << 0) 69 70 #define ADV7842_MAX_ADDRS (3) 71 72 /* 73 ********************************************************************** 74 * 75 * Arrays with configuration parameters for the ADV7842 76 * 77 ********************************************************************** 78 */ 79 80 struct adv7842_format_info { 81 u32 code; 82 u8 op_ch_sel; 83 bool rgb_out; 84 bool swap_cb_cr; 85 u8 op_format_sel; 86 }; 87 88 struct adv7842_state { 89 struct adv7842_platform_data pdata; 90 struct v4l2_subdev sd; 91 struct media_pad pad; 92 struct v4l2_ctrl_handler hdl; 93 enum adv7842_mode mode; 94 struct v4l2_dv_timings timings; 95 enum adv7842_vid_std_select vid_std_select; 96 97 const struct adv7842_format_info *format; 98 99 v4l2_std_id norm; 100 struct { 101 u8 edid[256]; 102 u32 present; 103 } hdmi_edid; 104 struct { 105 u8 edid[256]; 106 u32 present; 107 } vga_edid; 108 struct v4l2_fract aspect_ratio; 109 u32 rgb_quantization_range; 110 bool is_cea_format; 111 struct delayed_work delayed_work_enable_hotplug; 112 bool restart_stdi_once; 113 bool hdmi_port_a; 114 115 /* i2c clients */ 116 struct i2c_client *i2c_sdp_io; 117 struct i2c_client *i2c_sdp; 118 struct i2c_client *i2c_cp; 119 struct i2c_client *i2c_vdp; 120 struct i2c_client *i2c_afe; 121 struct i2c_client *i2c_hdmi; 122 struct i2c_client *i2c_repeater; 123 struct i2c_client *i2c_edid; 124 struct i2c_client *i2c_infoframe; 125 struct i2c_client *i2c_cec; 126 struct i2c_client *i2c_avlink; 127 128 /* controls */ 129 struct v4l2_ctrl *detect_tx_5v_ctrl; 130 struct v4l2_ctrl *analog_sampling_phase_ctrl; 131 struct v4l2_ctrl *free_run_color_ctrl_manual; 132 struct v4l2_ctrl *free_run_color_ctrl; 133 struct v4l2_ctrl *rgb_quantization_range_ctrl; 134 135 struct cec_adapter *cec_adap; 136 u8 cec_addr[ADV7842_MAX_ADDRS]; 137 u8 cec_valid_addrs; 138 bool cec_enabled_adap; 139 }; 140 141 /* Unsupported timings. This device cannot support 720p30. */ 142 static const struct v4l2_dv_timings adv7842_timings_exceptions[] = { 143 V4L2_DV_BT_CEA_1280X720P30, 144 { } 145 }; 146 147 static bool adv7842_check_dv_timings(const struct v4l2_dv_timings *t, void *hdl) 148 { 149 int i; 150 151 for (i = 0; adv7842_timings_exceptions[i].bt.width; i++) 152 if (v4l2_match_dv_timings(t, adv7842_timings_exceptions + i, 0, false)) 153 return false; 154 return true; 155 } 156 157 struct adv7842_video_standards { 158 struct v4l2_dv_timings timings; 159 u8 vid_std; 160 u8 v_freq; 161 }; 162 163 /* sorted by number of lines */ 164 static const struct adv7842_video_standards adv7842_prim_mode_comp[] = { 165 /* { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 }, TODO flickering */ 166 { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 }, 167 { V4L2_DV_BT_CEA_1280X720P50, 0x19, 0x01 }, 168 { V4L2_DV_BT_CEA_1280X720P60, 0x19, 0x00 }, 169 { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 }, 170 { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 }, 171 { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 }, 172 { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 }, 173 { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 }, 174 /* TODO add 1920x1080P60_RB (CVT timing) */ 175 { }, 176 }; 177 178 /* sorted by number of lines */ 179 static const struct adv7842_video_standards adv7842_prim_mode_gr[] = { 180 { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 }, 181 { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 }, 182 { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 }, 183 { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 }, 184 { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 }, 185 { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 }, 186 { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 }, 187 { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 }, 188 { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 }, 189 { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 }, 190 { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 }, 191 { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 }, 192 { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 }, 193 { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 }, 194 { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 }, 195 { V4L2_DV_BT_DMT_1360X768P60, 0x12, 0x00 }, 196 { V4L2_DV_BT_DMT_1366X768P60, 0x13, 0x00 }, 197 { V4L2_DV_BT_DMT_1400X1050P60, 0x14, 0x00 }, 198 { V4L2_DV_BT_DMT_1400X1050P75, 0x15, 0x00 }, 199 { V4L2_DV_BT_DMT_1600X1200P60, 0x16, 0x00 }, /* TODO not tested */ 200 /* TODO add 1600X1200P60_RB (not a DMT timing) */ 201 { V4L2_DV_BT_DMT_1680X1050P60, 0x18, 0x00 }, 202 { V4L2_DV_BT_DMT_1920X1200P60_RB, 0x19, 0x00 }, /* TODO not tested */ 203 { }, 204 }; 205 206 /* sorted by number of lines */ 207 static const struct adv7842_video_standards adv7842_prim_mode_hdmi_comp[] = { 208 { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 }, 209 { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 }, 210 { V4L2_DV_BT_CEA_1280X720P50, 0x13, 0x01 }, 211 { V4L2_DV_BT_CEA_1280X720P60, 0x13, 0x00 }, 212 { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 }, 213 { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 }, 214 { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 }, 215 { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 }, 216 { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 }, 217 { }, 218 }; 219 220 /* sorted by number of lines */ 221 static const struct adv7842_video_standards adv7842_prim_mode_hdmi_gr[] = { 222 { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 }, 223 { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 }, 224 { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 }, 225 { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 }, 226 { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 }, 227 { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 }, 228 { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 }, 229 { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 }, 230 { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 }, 231 { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 }, 232 { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 }, 233 { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 }, 234 { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 }, 235 { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 }, 236 { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 }, 237 { }, 238 }; 239 240 static const struct v4l2_event adv7842_ev_fmt = { 241 .type = V4L2_EVENT_SOURCE_CHANGE, 242 .u.src_change.changes = V4L2_EVENT_SRC_CH_RESOLUTION, 243 }; 244 245 /* ----------------------------------------------------------------------- */ 246 247 static inline struct adv7842_state *to_state(struct v4l2_subdev *sd) 248 { 249 return container_of(sd, struct adv7842_state, sd); 250 } 251 252 static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl) 253 { 254 return &container_of(ctrl->handler, struct adv7842_state, hdl)->sd; 255 } 256 257 static inline unsigned hblanking(const struct v4l2_bt_timings *t) 258 { 259 return V4L2_DV_BT_BLANKING_WIDTH(t); 260 } 261 262 static inline unsigned htotal(const struct v4l2_bt_timings *t) 263 { 264 return V4L2_DV_BT_FRAME_WIDTH(t); 265 } 266 267 static inline unsigned vblanking(const struct v4l2_bt_timings *t) 268 { 269 return V4L2_DV_BT_BLANKING_HEIGHT(t); 270 } 271 272 static inline unsigned vtotal(const struct v4l2_bt_timings *t) 273 { 274 return V4L2_DV_BT_FRAME_HEIGHT(t); 275 } 276 277 278 /* ----------------------------------------------------------------------- */ 279 280 static s32 adv_smbus_read_byte_data_check(struct i2c_client *client, 281 u8 command, bool check) 282 { 283 union i2c_smbus_data data; 284 285 if (!i2c_smbus_xfer(client->adapter, client->addr, client->flags, 286 I2C_SMBUS_READ, command, 287 I2C_SMBUS_BYTE_DATA, &data)) 288 return data.byte; 289 if (check) 290 v4l_err(client, "error reading %02x, %02x\n", 291 client->addr, command); 292 return -EIO; 293 } 294 295 static s32 adv_smbus_read_byte_data(struct i2c_client *client, u8 command) 296 { 297 int i; 298 299 for (i = 0; i < 3; i++) { 300 int ret = adv_smbus_read_byte_data_check(client, command, true); 301 302 if (ret >= 0) { 303 if (i) 304 v4l_err(client, "read ok after %d retries\n", i); 305 return ret; 306 } 307 } 308 v4l_err(client, "read failed\n"); 309 return -EIO; 310 } 311 312 static s32 adv_smbus_write_byte_data(struct i2c_client *client, 313 u8 command, u8 value) 314 { 315 union i2c_smbus_data data; 316 int err; 317 int i; 318 319 data.byte = value; 320 for (i = 0; i < 3; i++) { 321 err = i2c_smbus_xfer(client->adapter, client->addr, 322 client->flags, 323 I2C_SMBUS_WRITE, command, 324 I2C_SMBUS_BYTE_DATA, &data); 325 if (!err) 326 break; 327 } 328 if (err < 0) 329 v4l_err(client, "error writing %02x, %02x, %02x\n", 330 client->addr, command, value); 331 return err; 332 } 333 334 static void adv_smbus_write_byte_no_check(struct i2c_client *client, 335 u8 command, u8 value) 336 { 337 union i2c_smbus_data data; 338 data.byte = value; 339 340 i2c_smbus_xfer(client->adapter, client->addr, 341 client->flags, 342 I2C_SMBUS_WRITE, command, 343 I2C_SMBUS_BYTE_DATA, &data); 344 } 345 346 /* ----------------------------------------------------------------------- */ 347 348 static inline int io_read(struct v4l2_subdev *sd, u8 reg) 349 { 350 struct i2c_client *client = v4l2_get_subdevdata(sd); 351 352 return adv_smbus_read_byte_data(client, reg); 353 } 354 355 static inline int io_write(struct v4l2_subdev *sd, u8 reg, u8 val) 356 { 357 struct i2c_client *client = v4l2_get_subdevdata(sd); 358 359 return adv_smbus_write_byte_data(client, reg, val); 360 } 361 362 static inline int io_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) 363 { 364 return io_write(sd, reg, (io_read(sd, reg) & mask) | val); 365 } 366 367 static inline int io_write_clr_set(struct v4l2_subdev *sd, 368 u8 reg, u8 mask, u8 val) 369 { 370 return io_write(sd, reg, (io_read(sd, reg) & ~mask) | val); 371 } 372 373 static inline int avlink_read(struct v4l2_subdev *sd, u8 reg) 374 { 375 struct adv7842_state *state = to_state(sd); 376 377 return adv_smbus_read_byte_data(state->i2c_avlink, reg); 378 } 379 380 static inline int avlink_write(struct v4l2_subdev *sd, u8 reg, u8 val) 381 { 382 struct adv7842_state *state = to_state(sd); 383 384 return adv_smbus_write_byte_data(state->i2c_avlink, reg, val); 385 } 386 387 static inline int cec_read(struct v4l2_subdev *sd, u8 reg) 388 { 389 struct adv7842_state *state = to_state(sd); 390 391 return adv_smbus_read_byte_data(state->i2c_cec, reg); 392 } 393 394 static inline int cec_write(struct v4l2_subdev *sd, u8 reg, u8 val) 395 { 396 struct adv7842_state *state = to_state(sd); 397 398 return adv_smbus_write_byte_data(state->i2c_cec, reg, val); 399 } 400 401 static inline int cec_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) 402 { 403 return cec_write(sd, reg, (cec_read(sd, reg) & ~mask) | val); 404 } 405 406 static inline int infoframe_read(struct v4l2_subdev *sd, u8 reg) 407 { 408 struct adv7842_state *state = to_state(sd); 409 410 return adv_smbus_read_byte_data(state->i2c_infoframe, reg); 411 } 412 413 static inline int infoframe_write(struct v4l2_subdev *sd, u8 reg, u8 val) 414 { 415 struct adv7842_state *state = to_state(sd); 416 417 return adv_smbus_write_byte_data(state->i2c_infoframe, reg, val); 418 } 419 420 static inline int sdp_io_read(struct v4l2_subdev *sd, u8 reg) 421 { 422 struct adv7842_state *state = to_state(sd); 423 424 return adv_smbus_read_byte_data(state->i2c_sdp_io, reg); 425 } 426 427 static inline int sdp_io_write(struct v4l2_subdev *sd, u8 reg, u8 val) 428 { 429 struct adv7842_state *state = to_state(sd); 430 431 return adv_smbus_write_byte_data(state->i2c_sdp_io, reg, val); 432 } 433 434 static inline int sdp_io_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) 435 { 436 return sdp_io_write(sd, reg, (sdp_io_read(sd, reg) & mask) | val); 437 } 438 439 static inline int sdp_read(struct v4l2_subdev *sd, u8 reg) 440 { 441 struct adv7842_state *state = to_state(sd); 442 443 return adv_smbus_read_byte_data(state->i2c_sdp, reg); 444 } 445 446 static inline int sdp_write(struct v4l2_subdev *sd, u8 reg, u8 val) 447 { 448 struct adv7842_state *state = to_state(sd); 449 450 return adv_smbus_write_byte_data(state->i2c_sdp, reg, val); 451 } 452 453 static inline int sdp_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) 454 { 455 return sdp_write(sd, reg, (sdp_read(sd, reg) & mask) | val); 456 } 457 458 static inline int afe_read(struct v4l2_subdev *sd, u8 reg) 459 { 460 struct adv7842_state *state = to_state(sd); 461 462 return adv_smbus_read_byte_data(state->i2c_afe, reg); 463 } 464 465 static inline int afe_write(struct v4l2_subdev *sd, u8 reg, u8 val) 466 { 467 struct adv7842_state *state = to_state(sd); 468 469 return adv_smbus_write_byte_data(state->i2c_afe, reg, val); 470 } 471 472 static inline int afe_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) 473 { 474 return afe_write(sd, reg, (afe_read(sd, reg) & mask) | val); 475 } 476 477 static inline int rep_read(struct v4l2_subdev *sd, u8 reg) 478 { 479 struct adv7842_state *state = to_state(sd); 480 481 return adv_smbus_read_byte_data(state->i2c_repeater, reg); 482 } 483 484 static inline int rep_write(struct v4l2_subdev *sd, u8 reg, u8 val) 485 { 486 struct adv7842_state *state = to_state(sd); 487 488 return adv_smbus_write_byte_data(state->i2c_repeater, reg, val); 489 } 490 491 static inline int rep_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) 492 { 493 return rep_write(sd, reg, (rep_read(sd, reg) & mask) | val); 494 } 495 496 static inline int edid_read(struct v4l2_subdev *sd, u8 reg) 497 { 498 struct adv7842_state *state = to_state(sd); 499 500 return adv_smbus_read_byte_data(state->i2c_edid, reg); 501 } 502 503 static inline int edid_write(struct v4l2_subdev *sd, u8 reg, u8 val) 504 { 505 struct adv7842_state *state = to_state(sd); 506 507 return adv_smbus_write_byte_data(state->i2c_edid, reg, val); 508 } 509 510 static inline int hdmi_read(struct v4l2_subdev *sd, u8 reg) 511 { 512 struct adv7842_state *state = to_state(sd); 513 514 return adv_smbus_read_byte_data(state->i2c_hdmi, reg); 515 } 516 517 static inline int hdmi_write(struct v4l2_subdev *sd, u8 reg, u8 val) 518 { 519 struct adv7842_state *state = to_state(sd); 520 521 return adv_smbus_write_byte_data(state->i2c_hdmi, reg, val); 522 } 523 524 static inline int hdmi_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) 525 { 526 return hdmi_write(sd, reg, (hdmi_read(sd, reg) & mask) | val); 527 } 528 529 static inline int cp_read(struct v4l2_subdev *sd, u8 reg) 530 { 531 struct adv7842_state *state = to_state(sd); 532 533 return adv_smbus_read_byte_data(state->i2c_cp, reg); 534 } 535 536 static inline int cp_write(struct v4l2_subdev *sd, u8 reg, u8 val) 537 { 538 struct adv7842_state *state = to_state(sd); 539 540 return adv_smbus_write_byte_data(state->i2c_cp, reg, val); 541 } 542 543 static inline int cp_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) 544 { 545 return cp_write(sd, reg, (cp_read(sd, reg) & mask) | val); 546 } 547 548 static inline int vdp_read(struct v4l2_subdev *sd, u8 reg) 549 { 550 struct adv7842_state *state = to_state(sd); 551 552 return adv_smbus_read_byte_data(state->i2c_vdp, reg); 553 } 554 555 static inline int vdp_write(struct v4l2_subdev *sd, u8 reg, u8 val) 556 { 557 struct adv7842_state *state = to_state(sd); 558 559 return adv_smbus_write_byte_data(state->i2c_vdp, reg, val); 560 } 561 562 static void main_reset(struct v4l2_subdev *sd) 563 { 564 struct i2c_client *client = v4l2_get_subdevdata(sd); 565 566 v4l2_dbg(1, debug, sd, "%s:\n", __func__); 567 568 adv_smbus_write_byte_no_check(client, 0xff, 0x80); 569 570 mdelay(5); 571 } 572 573 /* ----------------------------------------------------------------------------- 574 * Format helpers 575 */ 576 577 static const struct adv7842_format_info adv7842_formats[] = { 578 { MEDIA_BUS_FMT_RGB888_1X24, ADV7842_OP_CH_SEL_RGB, true, false, 579 ADV7842_OP_MODE_SEL_SDR_444 | ADV7842_OP_FORMAT_SEL_8BIT }, 580 { MEDIA_BUS_FMT_YUYV8_2X8, ADV7842_OP_CH_SEL_RGB, false, false, 581 ADV7842_OP_MODE_SEL_SDR_422 | ADV7842_OP_FORMAT_SEL_8BIT }, 582 { MEDIA_BUS_FMT_YVYU8_2X8, ADV7842_OP_CH_SEL_RGB, false, true, 583 ADV7842_OP_MODE_SEL_SDR_422 | ADV7842_OP_FORMAT_SEL_8BIT }, 584 { MEDIA_BUS_FMT_YUYV10_2X10, ADV7842_OP_CH_SEL_RGB, false, false, 585 ADV7842_OP_MODE_SEL_SDR_422 | ADV7842_OP_FORMAT_SEL_10BIT }, 586 { MEDIA_BUS_FMT_YVYU10_2X10, ADV7842_OP_CH_SEL_RGB, false, true, 587 ADV7842_OP_MODE_SEL_SDR_422 | ADV7842_OP_FORMAT_SEL_10BIT }, 588 { MEDIA_BUS_FMT_YUYV12_2X12, ADV7842_OP_CH_SEL_RGB, false, false, 589 ADV7842_OP_MODE_SEL_SDR_422 | ADV7842_OP_FORMAT_SEL_12BIT }, 590 { MEDIA_BUS_FMT_YVYU12_2X12, ADV7842_OP_CH_SEL_RGB, false, true, 591 ADV7842_OP_MODE_SEL_SDR_422 | ADV7842_OP_FORMAT_SEL_12BIT }, 592 { MEDIA_BUS_FMT_UYVY8_1X16, ADV7842_OP_CH_SEL_RBG, false, false, 593 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_8BIT }, 594 { MEDIA_BUS_FMT_VYUY8_1X16, ADV7842_OP_CH_SEL_RBG, false, true, 595 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_8BIT }, 596 { MEDIA_BUS_FMT_YUYV8_1X16, ADV7842_OP_CH_SEL_RGB, false, false, 597 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_8BIT }, 598 { MEDIA_BUS_FMT_YVYU8_1X16, ADV7842_OP_CH_SEL_RGB, false, true, 599 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_8BIT }, 600 { MEDIA_BUS_FMT_UYVY10_1X20, ADV7842_OP_CH_SEL_RBG, false, false, 601 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_10BIT }, 602 { MEDIA_BUS_FMT_VYUY10_1X20, ADV7842_OP_CH_SEL_RBG, false, true, 603 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_10BIT }, 604 { MEDIA_BUS_FMT_YUYV10_1X20, ADV7842_OP_CH_SEL_RGB, false, false, 605 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_10BIT }, 606 { MEDIA_BUS_FMT_YVYU10_1X20, ADV7842_OP_CH_SEL_RGB, false, true, 607 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_10BIT }, 608 { MEDIA_BUS_FMT_UYVY12_1X24, ADV7842_OP_CH_SEL_RBG, false, false, 609 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_12BIT }, 610 { MEDIA_BUS_FMT_VYUY12_1X24, ADV7842_OP_CH_SEL_RBG, false, true, 611 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_12BIT }, 612 { MEDIA_BUS_FMT_YUYV12_1X24, ADV7842_OP_CH_SEL_RGB, false, false, 613 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_12BIT }, 614 { MEDIA_BUS_FMT_YVYU12_1X24, ADV7842_OP_CH_SEL_RGB, false, true, 615 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_12BIT }, 616 }; 617 618 static const struct adv7842_format_info * 619 adv7842_format_info(struct adv7842_state *state, u32 code) 620 { 621 unsigned int i; 622 623 for (i = 0; i < ARRAY_SIZE(adv7842_formats); ++i) { 624 if (adv7842_formats[i].code == code) 625 return &adv7842_formats[i]; 626 } 627 628 return NULL; 629 } 630 631 /* ----------------------------------------------------------------------- */ 632 633 static inline bool is_analog_input(struct v4l2_subdev *sd) 634 { 635 struct adv7842_state *state = to_state(sd); 636 637 return ((state->mode == ADV7842_MODE_RGB) || 638 (state->mode == ADV7842_MODE_COMP)); 639 } 640 641 static inline bool is_digital_input(struct v4l2_subdev *sd) 642 { 643 struct adv7842_state *state = to_state(sd); 644 645 return state->mode == ADV7842_MODE_HDMI; 646 } 647 648 static const struct v4l2_dv_timings_cap adv7842_timings_cap_analog = { 649 .type = V4L2_DV_BT_656_1120, 650 /* keep this initialization for compatibility with GCC < 4.4.6 */ 651 .reserved = { 0 }, 652 V4L2_INIT_BT_TIMINGS(640, 1920, 350, 1200, 25000000, 170000000, 653 V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT | 654 V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT, 655 V4L2_DV_BT_CAP_PROGRESSIVE | V4L2_DV_BT_CAP_REDUCED_BLANKING | 656 V4L2_DV_BT_CAP_CUSTOM) 657 }; 658 659 static const struct v4l2_dv_timings_cap adv7842_timings_cap_digital = { 660 .type = V4L2_DV_BT_656_1120, 661 /* keep this initialization for compatibility with GCC < 4.4.6 */ 662 .reserved = { 0 }, 663 V4L2_INIT_BT_TIMINGS(640, 1920, 350, 1200, 25000000, 225000000, 664 V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT | 665 V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT, 666 V4L2_DV_BT_CAP_PROGRESSIVE | V4L2_DV_BT_CAP_REDUCED_BLANKING | 667 V4L2_DV_BT_CAP_CUSTOM) 668 }; 669 670 static inline const struct v4l2_dv_timings_cap * 671 adv7842_get_dv_timings_cap(struct v4l2_subdev *sd) 672 { 673 return is_digital_input(sd) ? &adv7842_timings_cap_digital : 674 &adv7842_timings_cap_analog; 675 } 676 677 /* ----------------------------------------------------------------------- */ 678 679 static u16 adv7842_read_cable_det(struct v4l2_subdev *sd) 680 { 681 u8 reg = io_read(sd, 0x6f); 682 u16 val = 0; 683 684 if (reg & 0x02) 685 val |= 1; /* port A */ 686 if (reg & 0x01) 687 val |= 2; /* port B */ 688 return val; 689 } 690 691 static void adv7842_delayed_work_enable_hotplug(struct work_struct *work) 692 { 693 struct delayed_work *dwork = to_delayed_work(work); 694 struct adv7842_state *state = container_of(dwork, 695 struct adv7842_state, delayed_work_enable_hotplug); 696 struct v4l2_subdev *sd = &state->sd; 697 int present = state->hdmi_edid.present; 698 u8 mask = 0; 699 700 v4l2_dbg(2, debug, sd, "%s: enable hotplug on ports: 0x%x\n", 701 __func__, present); 702 703 if (present & (0x04 << ADV7842_EDID_PORT_A)) 704 mask |= 0x20; 705 if (present & (0x04 << ADV7842_EDID_PORT_B)) 706 mask |= 0x10; 707 io_write_and_or(sd, 0x20, 0xcf, mask); 708 } 709 710 static int edid_write_vga_segment(struct v4l2_subdev *sd) 711 { 712 struct i2c_client *client = v4l2_get_subdevdata(sd); 713 struct adv7842_state *state = to_state(sd); 714 const u8 *val = state->vga_edid.edid; 715 int err = 0; 716 int i; 717 718 v4l2_dbg(2, debug, sd, "%s: write EDID on VGA port\n", __func__); 719 720 /* HPA disable on port A and B */ 721 io_write_and_or(sd, 0x20, 0xcf, 0x00); 722 723 /* Disable I2C access to internal EDID ram from VGA DDC port */ 724 rep_write_and_or(sd, 0x7f, 0x7f, 0x00); 725 726 /* edid segment pointer '1' for VGA port */ 727 rep_write_and_or(sd, 0x77, 0xef, 0x10); 728 729 for (i = 0; !err && i < 256; i += I2C_SMBUS_BLOCK_MAX) 730 err = i2c_smbus_write_i2c_block_data(state->i2c_edid, i, 731 I2C_SMBUS_BLOCK_MAX, 732 val + i); 733 if (err) 734 return err; 735 736 /* Calculates the checksums and enables I2C access 737 * to internal EDID ram from VGA DDC port. 738 */ 739 rep_write_and_or(sd, 0x7f, 0x7f, 0x80); 740 741 for (i = 0; i < 1000; i++) { 742 if (rep_read(sd, 0x79) & 0x20) 743 break; 744 mdelay(1); 745 } 746 if (i == 1000) { 747 v4l_err(client, "error enabling edid on VGA port\n"); 748 return -EIO; 749 } 750 751 /* enable hotplug after 200 ms */ 752 schedule_delayed_work(&state->delayed_work_enable_hotplug, HZ / 5); 753 754 return 0; 755 } 756 757 static int edid_write_hdmi_segment(struct v4l2_subdev *sd, u8 port) 758 { 759 struct i2c_client *client = v4l2_get_subdevdata(sd); 760 struct adv7842_state *state = to_state(sd); 761 const u8 *edid = state->hdmi_edid.edid; 762 int spa_loc; 763 u16 pa; 764 int err = 0; 765 int i; 766 767 v4l2_dbg(2, debug, sd, "%s: write EDID on port %c\n", 768 __func__, (port == ADV7842_EDID_PORT_A) ? 'A' : 'B'); 769 770 /* HPA disable on port A and B */ 771 io_write_and_or(sd, 0x20, 0xcf, 0x00); 772 773 /* Disable I2C access to internal EDID ram from HDMI DDC ports */ 774 rep_write_and_or(sd, 0x77, 0xf3, 0x00); 775 776 if (!state->hdmi_edid.present) { 777 cec_phys_addr_invalidate(state->cec_adap); 778 return 0; 779 } 780 781 pa = v4l2_get_edid_phys_addr(edid, 256, &spa_loc); 782 err = v4l2_phys_addr_validate(pa, &pa, NULL); 783 if (err) 784 return err; 785 786 /* 787 * Return an error if no location of the source physical address 788 * was found. 789 */ 790 if (spa_loc == 0) 791 return -EINVAL; 792 793 /* edid segment pointer '0' for HDMI ports */ 794 rep_write_and_or(sd, 0x77, 0xef, 0x00); 795 796 for (i = 0; !err && i < 256; i += I2C_SMBUS_BLOCK_MAX) 797 err = i2c_smbus_write_i2c_block_data(state->i2c_edid, i, 798 I2C_SMBUS_BLOCK_MAX, edid + i); 799 if (err) 800 return err; 801 802 if (port == ADV7842_EDID_PORT_A) { 803 rep_write(sd, 0x72, edid[spa_loc]); 804 rep_write(sd, 0x73, edid[spa_loc + 1]); 805 } else { 806 rep_write(sd, 0x74, edid[spa_loc]); 807 rep_write(sd, 0x75, edid[spa_loc + 1]); 808 } 809 rep_write(sd, 0x76, spa_loc & 0xff); 810 rep_write_and_or(sd, 0x77, 0xbf, (spa_loc >> 2) & 0x40); 811 812 /* Calculates the checksums and enables I2C access to internal 813 * EDID ram from HDMI DDC ports 814 */ 815 rep_write_and_or(sd, 0x77, 0xf3, state->hdmi_edid.present); 816 817 for (i = 0; i < 1000; i++) { 818 if (rep_read(sd, 0x7d) & state->hdmi_edid.present) 819 break; 820 mdelay(1); 821 } 822 if (i == 1000) { 823 v4l_err(client, "error enabling edid on port %c\n", 824 (port == ADV7842_EDID_PORT_A) ? 'A' : 'B'); 825 return -EIO; 826 } 827 cec_s_phys_addr(state->cec_adap, pa, false); 828 829 /* enable hotplug after 200 ms */ 830 schedule_delayed_work(&state->delayed_work_enable_hotplug, HZ / 5); 831 832 return 0; 833 } 834 835 /* ----------------------------------------------------------------------- */ 836 837 #ifdef CONFIG_VIDEO_ADV_DEBUG 838 static void adv7842_inv_register(struct v4l2_subdev *sd) 839 { 840 v4l2_info(sd, "0x000-0x0ff: IO Map\n"); 841 v4l2_info(sd, "0x100-0x1ff: AVLink Map\n"); 842 v4l2_info(sd, "0x200-0x2ff: CEC Map\n"); 843 v4l2_info(sd, "0x300-0x3ff: InfoFrame Map\n"); 844 v4l2_info(sd, "0x400-0x4ff: SDP_IO Map\n"); 845 v4l2_info(sd, "0x500-0x5ff: SDP Map\n"); 846 v4l2_info(sd, "0x600-0x6ff: AFE Map\n"); 847 v4l2_info(sd, "0x700-0x7ff: Repeater Map\n"); 848 v4l2_info(sd, "0x800-0x8ff: EDID Map\n"); 849 v4l2_info(sd, "0x900-0x9ff: HDMI Map\n"); 850 v4l2_info(sd, "0xa00-0xaff: CP Map\n"); 851 v4l2_info(sd, "0xb00-0xbff: VDP Map\n"); 852 } 853 854 static int adv7842_g_register(struct v4l2_subdev *sd, 855 struct v4l2_dbg_register *reg) 856 { 857 reg->size = 1; 858 switch (reg->reg >> 8) { 859 case 0: 860 reg->val = io_read(sd, reg->reg & 0xff); 861 break; 862 case 1: 863 reg->val = avlink_read(sd, reg->reg & 0xff); 864 break; 865 case 2: 866 reg->val = cec_read(sd, reg->reg & 0xff); 867 break; 868 case 3: 869 reg->val = infoframe_read(sd, reg->reg & 0xff); 870 break; 871 case 4: 872 reg->val = sdp_io_read(sd, reg->reg & 0xff); 873 break; 874 case 5: 875 reg->val = sdp_read(sd, reg->reg & 0xff); 876 break; 877 case 6: 878 reg->val = afe_read(sd, reg->reg & 0xff); 879 break; 880 case 7: 881 reg->val = rep_read(sd, reg->reg & 0xff); 882 break; 883 case 8: 884 reg->val = edid_read(sd, reg->reg & 0xff); 885 break; 886 case 9: 887 reg->val = hdmi_read(sd, reg->reg & 0xff); 888 break; 889 case 0xa: 890 reg->val = cp_read(sd, reg->reg & 0xff); 891 break; 892 case 0xb: 893 reg->val = vdp_read(sd, reg->reg & 0xff); 894 break; 895 default: 896 v4l2_info(sd, "Register %03llx not supported\n", reg->reg); 897 adv7842_inv_register(sd); 898 break; 899 } 900 return 0; 901 } 902 903 static int adv7842_s_register(struct v4l2_subdev *sd, 904 const struct v4l2_dbg_register *reg) 905 { 906 u8 val = reg->val & 0xff; 907 908 switch (reg->reg >> 8) { 909 case 0: 910 io_write(sd, reg->reg & 0xff, val); 911 break; 912 case 1: 913 avlink_write(sd, reg->reg & 0xff, val); 914 break; 915 case 2: 916 cec_write(sd, reg->reg & 0xff, val); 917 break; 918 case 3: 919 infoframe_write(sd, reg->reg & 0xff, val); 920 break; 921 case 4: 922 sdp_io_write(sd, reg->reg & 0xff, val); 923 break; 924 case 5: 925 sdp_write(sd, reg->reg & 0xff, val); 926 break; 927 case 6: 928 afe_write(sd, reg->reg & 0xff, val); 929 break; 930 case 7: 931 rep_write(sd, reg->reg & 0xff, val); 932 break; 933 case 8: 934 edid_write(sd, reg->reg & 0xff, val); 935 break; 936 case 9: 937 hdmi_write(sd, reg->reg & 0xff, val); 938 break; 939 case 0xa: 940 cp_write(sd, reg->reg & 0xff, val); 941 break; 942 case 0xb: 943 vdp_write(sd, reg->reg & 0xff, val); 944 break; 945 default: 946 v4l2_info(sd, "Register %03llx not supported\n", reg->reg); 947 adv7842_inv_register(sd); 948 break; 949 } 950 return 0; 951 } 952 #endif 953 954 static int adv7842_s_detect_tx_5v_ctrl(struct v4l2_subdev *sd) 955 { 956 struct adv7842_state *state = to_state(sd); 957 u16 cable_det = adv7842_read_cable_det(sd); 958 959 v4l2_dbg(1, debug, sd, "%s: 0x%x\n", __func__, cable_det); 960 961 return v4l2_ctrl_s_ctrl(state->detect_tx_5v_ctrl, cable_det); 962 } 963 964 static int find_and_set_predefined_video_timings(struct v4l2_subdev *sd, 965 u8 prim_mode, 966 const struct adv7842_video_standards *predef_vid_timings, 967 const struct v4l2_dv_timings *timings) 968 { 969 int i; 970 971 for (i = 0; predef_vid_timings[i].timings.bt.width; i++) { 972 if (!v4l2_match_dv_timings(timings, &predef_vid_timings[i].timings, 973 is_digital_input(sd) ? 250000 : 1000000, false)) 974 continue; 975 /* video std */ 976 io_write(sd, 0x00, predef_vid_timings[i].vid_std); 977 /* v_freq and prim mode */ 978 io_write(sd, 0x01, (predef_vid_timings[i].v_freq << 4) + prim_mode); 979 return 0; 980 } 981 982 return -1; 983 } 984 985 static int configure_predefined_video_timings(struct v4l2_subdev *sd, 986 struct v4l2_dv_timings *timings) 987 { 988 struct adv7842_state *state = to_state(sd); 989 int err; 990 991 v4l2_dbg(1, debug, sd, "%s\n", __func__); 992 993 /* reset to default values */ 994 io_write(sd, 0x16, 0x43); 995 io_write(sd, 0x17, 0x5a); 996 /* disable embedded syncs for auto graphics mode */ 997 cp_write_and_or(sd, 0x81, 0xef, 0x00); 998 cp_write(sd, 0x26, 0x00); 999 cp_write(sd, 0x27, 0x00); 1000 cp_write(sd, 0x28, 0x00); 1001 cp_write(sd, 0x29, 0x00); 1002 cp_write(sd, 0x8f, 0x40); 1003 cp_write(sd, 0x90, 0x00); 1004 cp_write(sd, 0xa5, 0x00); 1005 cp_write(sd, 0xa6, 0x00); 1006 cp_write(sd, 0xa7, 0x00); 1007 cp_write(sd, 0xab, 0x00); 1008 cp_write(sd, 0xac, 0x00); 1009 1010 switch (state->mode) { 1011 case ADV7842_MODE_COMP: 1012 case ADV7842_MODE_RGB: 1013 err = find_and_set_predefined_video_timings(sd, 1014 0x01, adv7842_prim_mode_comp, timings); 1015 if (err) 1016 err = find_and_set_predefined_video_timings(sd, 1017 0x02, adv7842_prim_mode_gr, timings); 1018 break; 1019 case ADV7842_MODE_HDMI: 1020 err = find_and_set_predefined_video_timings(sd, 1021 0x05, adv7842_prim_mode_hdmi_comp, timings); 1022 if (err) 1023 err = find_and_set_predefined_video_timings(sd, 1024 0x06, adv7842_prim_mode_hdmi_gr, timings); 1025 break; 1026 default: 1027 v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n", 1028 __func__, state->mode); 1029 err = -1; 1030 break; 1031 } 1032 1033 1034 return err; 1035 } 1036 1037 static void configure_custom_video_timings(struct v4l2_subdev *sd, 1038 const struct v4l2_bt_timings *bt) 1039 { 1040 struct adv7842_state *state = to_state(sd); 1041 struct i2c_client *client = v4l2_get_subdevdata(sd); 1042 u32 width = htotal(bt); 1043 u32 height = vtotal(bt); 1044 u16 cp_start_sav = bt->hsync + bt->hbackporch - 4; 1045 u16 cp_start_eav = width - bt->hfrontporch; 1046 u16 cp_start_vbi = height - bt->vfrontporch + 1; 1047 u16 cp_end_vbi = bt->vsync + bt->vbackporch + 1; 1048 u16 ch1_fr_ll = (((u32)bt->pixelclock / 100) > 0) ? 1049 ((width * (ADV7842_fsc / 100)) / ((u32)bt->pixelclock / 100)) : 0; 1050 const u8 pll[2] = { 1051 0xc0 | ((width >> 8) & 0x1f), 1052 width & 0xff 1053 }; 1054 1055 v4l2_dbg(2, debug, sd, "%s\n", __func__); 1056 1057 switch (state->mode) { 1058 case ADV7842_MODE_COMP: 1059 case ADV7842_MODE_RGB: 1060 /* auto graphics */ 1061 io_write(sd, 0x00, 0x07); /* video std */ 1062 io_write(sd, 0x01, 0x02); /* prim mode */ 1063 /* enable embedded syncs for auto graphics mode */ 1064 cp_write_and_or(sd, 0x81, 0xef, 0x10); 1065 1066 /* Should only be set in auto-graphics mode [REF_02, p. 91-92] */ 1067 /* setup PLL_DIV_MAN_EN and PLL_DIV_RATIO */ 1068 /* IO-map reg. 0x16 and 0x17 should be written in sequence */ 1069 if (i2c_smbus_write_i2c_block_data(client, 0x16, 2, pll)) { 1070 v4l2_err(sd, "writing to reg 0x16 and 0x17 failed\n"); 1071 break; 1072 } 1073 1074 /* active video - horizontal timing */ 1075 cp_write(sd, 0x26, (cp_start_sav >> 8) & 0xf); 1076 cp_write(sd, 0x27, (cp_start_sav & 0xff)); 1077 cp_write(sd, 0x28, (cp_start_eav >> 8) & 0xf); 1078 cp_write(sd, 0x29, (cp_start_eav & 0xff)); 1079 1080 /* active video - vertical timing */ 1081 cp_write(sd, 0xa5, (cp_start_vbi >> 4) & 0xff); 1082 cp_write(sd, 0xa6, ((cp_start_vbi & 0xf) << 4) | 1083 ((cp_end_vbi >> 8) & 0xf)); 1084 cp_write(sd, 0xa7, cp_end_vbi & 0xff); 1085 break; 1086 case ADV7842_MODE_HDMI: 1087 /* set default prim_mode/vid_std for HDMI 1088 according to [REF_03, c. 4.2] */ 1089 io_write(sd, 0x00, 0x02); /* video std */ 1090 io_write(sd, 0x01, 0x06); /* prim mode */ 1091 break; 1092 default: 1093 v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n", 1094 __func__, state->mode); 1095 break; 1096 } 1097 1098 cp_write(sd, 0x8f, (ch1_fr_ll >> 8) & 0x7); 1099 cp_write(sd, 0x90, ch1_fr_ll & 0xff); 1100 cp_write(sd, 0xab, (height >> 4) & 0xff); 1101 cp_write(sd, 0xac, (height & 0x0f) << 4); 1102 } 1103 1104 static void adv7842_set_offset(struct v4l2_subdev *sd, bool auto_offset, u16 offset_a, u16 offset_b, u16 offset_c) 1105 { 1106 struct adv7842_state *state = to_state(sd); 1107 u8 offset_buf[4]; 1108 1109 if (auto_offset) { 1110 offset_a = 0x3ff; 1111 offset_b = 0x3ff; 1112 offset_c = 0x3ff; 1113 } 1114 1115 v4l2_dbg(2, debug, sd, "%s: %s offset: a = 0x%x, b = 0x%x, c = 0x%x\n", 1116 __func__, auto_offset ? "Auto" : "Manual", 1117 offset_a, offset_b, offset_c); 1118 1119 offset_buf[0]= (cp_read(sd, 0x77) & 0xc0) | ((offset_a & 0x3f0) >> 4); 1120 offset_buf[1] = ((offset_a & 0x00f) << 4) | ((offset_b & 0x3c0) >> 6); 1121 offset_buf[2] = ((offset_b & 0x03f) << 2) | ((offset_c & 0x300) >> 8); 1122 offset_buf[3] = offset_c & 0x0ff; 1123 1124 /* Registers must be written in this order with no i2c access in between */ 1125 if (i2c_smbus_write_i2c_block_data(state->i2c_cp, 0x77, 4, offset_buf)) 1126 v4l2_err(sd, "%s: i2c error writing to CP reg 0x77, 0x78, 0x79, 0x7a\n", __func__); 1127 } 1128 1129 static void adv7842_set_gain(struct v4l2_subdev *sd, bool auto_gain, u16 gain_a, u16 gain_b, u16 gain_c) 1130 { 1131 struct adv7842_state *state = to_state(sd); 1132 u8 gain_buf[4]; 1133 u8 gain_man = 1; 1134 u8 agc_mode_man = 1; 1135 1136 if (auto_gain) { 1137 gain_man = 0; 1138 agc_mode_man = 0; 1139 gain_a = 0x100; 1140 gain_b = 0x100; 1141 gain_c = 0x100; 1142 } 1143 1144 v4l2_dbg(2, debug, sd, "%s: %s gain: a = 0x%x, b = 0x%x, c = 0x%x\n", 1145 __func__, auto_gain ? "Auto" : "Manual", 1146 gain_a, gain_b, gain_c); 1147 1148 gain_buf[0] = ((gain_man << 7) | (agc_mode_man << 6) | ((gain_a & 0x3f0) >> 4)); 1149 gain_buf[1] = (((gain_a & 0x00f) << 4) | ((gain_b & 0x3c0) >> 6)); 1150 gain_buf[2] = (((gain_b & 0x03f) << 2) | ((gain_c & 0x300) >> 8)); 1151 gain_buf[3] = ((gain_c & 0x0ff)); 1152 1153 /* Registers must be written in this order with no i2c access in between */ 1154 if (i2c_smbus_write_i2c_block_data(state->i2c_cp, 0x73, 4, gain_buf)) 1155 v4l2_err(sd, "%s: i2c error writing to CP reg 0x73, 0x74, 0x75, 0x76\n", __func__); 1156 } 1157 1158 static void set_rgb_quantization_range(struct v4l2_subdev *sd) 1159 { 1160 struct adv7842_state *state = to_state(sd); 1161 bool rgb_output = io_read(sd, 0x02) & 0x02; 1162 bool hdmi_signal = hdmi_read(sd, 0x05) & 0x80; 1163 u8 y = HDMI_COLORSPACE_RGB; 1164 1165 if (hdmi_signal && (io_read(sd, 0x60) & 1)) 1166 y = infoframe_read(sd, 0x01) >> 5; 1167 1168 v4l2_dbg(2, debug, sd, "%s: RGB quantization range: %d, RGB out: %d, HDMI: %d\n", 1169 __func__, state->rgb_quantization_range, 1170 rgb_output, hdmi_signal); 1171 1172 adv7842_set_gain(sd, true, 0x0, 0x0, 0x0); 1173 adv7842_set_offset(sd, true, 0x0, 0x0, 0x0); 1174 io_write_clr_set(sd, 0x02, 0x04, rgb_output ? 0 : 4); 1175 1176 switch (state->rgb_quantization_range) { 1177 case V4L2_DV_RGB_RANGE_AUTO: 1178 if (state->mode == ADV7842_MODE_RGB) { 1179 /* Receiving analog RGB signal 1180 * Set RGB full range (0-255) */ 1181 io_write_and_or(sd, 0x02, 0x0f, 0x10); 1182 break; 1183 } 1184 1185 if (state->mode == ADV7842_MODE_COMP) { 1186 /* Receiving analog YPbPr signal 1187 * Set automode */ 1188 io_write_and_or(sd, 0x02, 0x0f, 0xf0); 1189 break; 1190 } 1191 1192 if (hdmi_signal) { 1193 /* Receiving HDMI signal 1194 * Set automode */ 1195 io_write_and_or(sd, 0x02, 0x0f, 0xf0); 1196 break; 1197 } 1198 1199 /* Receiving DVI-D signal 1200 * ADV7842 selects RGB limited range regardless of 1201 * input format (CE/IT) in automatic mode */ 1202 if (state->timings.bt.flags & V4L2_DV_FL_IS_CE_VIDEO) { 1203 /* RGB limited range (16-235) */ 1204 io_write_and_or(sd, 0x02, 0x0f, 0x00); 1205 } else { 1206 /* RGB full range (0-255) */ 1207 io_write_and_or(sd, 0x02, 0x0f, 0x10); 1208 1209 if (is_digital_input(sd) && rgb_output) { 1210 adv7842_set_offset(sd, false, 0x40, 0x40, 0x40); 1211 } else { 1212 adv7842_set_gain(sd, false, 0xe0, 0xe0, 0xe0); 1213 adv7842_set_offset(sd, false, 0x70, 0x70, 0x70); 1214 } 1215 } 1216 break; 1217 case V4L2_DV_RGB_RANGE_LIMITED: 1218 if (state->mode == ADV7842_MODE_COMP) { 1219 /* YCrCb limited range (16-235) */ 1220 io_write_and_or(sd, 0x02, 0x0f, 0x20); 1221 break; 1222 } 1223 1224 if (y != HDMI_COLORSPACE_RGB) 1225 break; 1226 1227 /* RGB limited range (16-235) */ 1228 io_write_and_or(sd, 0x02, 0x0f, 0x00); 1229 1230 break; 1231 case V4L2_DV_RGB_RANGE_FULL: 1232 if (state->mode == ADV7842_MODE_COMP) { 1233 /* YCrCb full range (0-255) */ 1234 io_write_and_or(sd, 0x02, 0x0f, 0x60); 1235 break; 1236 } 1237 1238 if (y != HDMI_COLORSPACE_RGB) 1239 break; 1240 1241 /* RGB full range (0-255) */ 1242 io_write_and_or(sd, 0x02, 0x0f, 0x10); 1243 1244 if (is_analog_input(sd) || hdmi_signal) 1245 break; 1246 1247 /* Adjust gain/offset for DVI-D signals only */ 1248 if (rgb_output) { 1249 adv7842_set_offset(sd, false, 0x40, 0x40, 0x40); 1250 } else { 1251 adv7842_set_gain(sd, false, 0xe0, 0xe0, 0xe0); 1252 adv7842_set_offset(sd, false, 0x70, 0x70, 0x70); 1253 } 1254 break; 1255 } 1256 } 1257 1258 static int adv7842_s_ctrl(struct v4l2_ctrl *ctrl) 1259 { 1260 struct v4l2_subdev *sd = to_sd(ctrl); 1261 struct adv7842_state *state = to_state(sd); 1262 1263 /* TODO SDP ctrls 1264 contrast/brightness/hue/free run is acting a bit strange, 1265 not sure if sdp csc is correct. 1266 */ 1267 switch (ctrl->id) { 1268 /* standard ctrls */ 1269 case V4L2_CID_BRIGHTNESS: 1270 cp_write(sd, 0x3c, ctrl->val); 1271 sdp_write(sd, 0x14, ctrl->val); 1272 /* ignore lsb sdp 0x17[3:2] */ 1273 return 0; 1274 case V4L2_CID_CONTRAST: 1275 cp_write(sd, 0x3a, ctrl->val); 1276 sdp_write(sd, 0x13, ctrl->val); 1277 /* ignore lsb sdp 0x17[1:0] */ 1278 return 0; 1279 case V4L2_CID_SATURATION: 1280 cp_write(sd, 0x3b, ctrl->val); 1281 sdp_write(sd, 0x15, ctrl->val); 1282 /* ignore lsb sdp 0x17[5:4] */ 1283 return 0; 1284 case V4L2_CID_HUE: 1285 cp_write(sd, 0x3d, ctrl->val); 1286 sdp_write(sd, 0x16, ctrl->val); 1287 /* ignore lsb sdp 0x17[7:6] */ 1288 return 0; 1289 /* custom ctrls */ 1290 case V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE: 1291 afe_write(sd, 0xc8, ctrl->val); 1292 return 0; 1293 case V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL: 1294 cp_write_and_or(sd, 0xbf, ~0x04, (ctrl->val << 2)); 1295 sdp_write_and_or(sd, 0xdd, ~0x04, (ctrl->val << 2)); 1296 return 0; 1297 case V4L2_CID_ADV_RX_FREE_RUN_COLOR: { 1298 u8 R = (ctrl->val & 0xff0000) >> 16; 1299 u8 G = (ctrl->val & 0x00ff00) >> 8; 1300 u8 B = (ctrl->val & 0x0000ff); 1301 /* RGB -> YUV, numerical approximation */ 1302 int Y = 66 * R + 129 * G + 25 * B; 1303 int U = -38 * R - 74 * G + 112 * B; 1304 int V = 112 * R - 94 * G - 18 * B; 1305 1306 /* Scale down to 8 bits with rounding */ 1307 Y = (Y + 128) >> 8; 1308 U = (U + 128) >> 8; 1309 V = (V + 128) >> 8; 1310 /* make U,V positive */ 1311 Y += 16; 1312 U += 128; 1313 V += 128; 1314 1315 v4l2_dbg(1, debug, sd, "R %x, G %x, B %x\n", R, G, B); 1316 v4l2_dbg(1, debug, sd, "Y %x, U %x, V %x\n", Y, U, V); 1317 1318 /* CP */ 1319 cp_write(sd, 0xc1, R); 1320 cp_write(sd, 0xc0, G); 1321 cp_write(sd, 0xc2, B); 1322 /* SDP */ 1323 sdp_write(sd, 0xde, Y); 1324 sdp_write(sd, 0xdf, (V & 0xf0) | ((U >> 4) & 0x0f)); 1325 return 0; 1326 } 1327 case V4L2_CID_DV_RX_RGB_RANGE: 1328 state->rgb_quantization_range = ctrl->val; 1329 set_rgb_quantization_range(sd); 1330 return 0; 1331 } 1332 return -EINVAL; 1333 } 1334 1335 static int adv7842_g_volatile_ctrl(struct v4l2_ctrl *ctrl) 1336 { 1337 struct v4l2_subdev *sd = to_sd(ctrl); 1338 1339 if (ctrl->id == V4L2_CID_DV_RX_IT_CONTENT_TYPE) { 1340 ctrl->val = V4L2_DV_IT_CONTENT_TYPE_NO_ITC; 1341 if ((io_read(sd, 0x60) & 1) && (infoframe_read(sd, 0x03) & 0x80)) 1342 ctrl->val = (infoframe_read(sd, 0x05) >> 4) & 3; 1343 return 0; 1344 } 1345 return -EINVAL; 1346 } 1347 1348 static inline bool no_power(struct v4l2_subdev *sd) 1349 { 1350 return io_read(sd, 0x0c) & 0x24; 1351 } 1352 1353 static inline bool no_cp_signal(struct v4l2_subdev *sd) 1354 { 1355 return ((cp_read(sd, 0xb5) & 0xd0) != 0xd0) || !(cp_read(sd, 0xb1) & 0x80); 1356 } 1357 1358 static inline bool is_hdmi(struct v4l2_subdev *sd) 1359 { 1360 return hdmi_read(sd, 0x05) & 0x80; 1361 } 1362 1363 static int adv7842_g_input_status(struct v4l2_subdev *sd, u32 *status) 1364 { 1365 struct adv7842_state *state = to_state(sd); 1366 1367 *status = 0; 1368 1369 if (io_read(sd, 0x0c) & 0x24) 1370 *status |= V4L2_IN_ST_NO_POWER; 1371 1372 if (state->mode == ADV7842_MODE_SDP) { 1373 /* status from SDP block */ 1374 if (!(sdp_read(sd, 0x5A) & 0x01)) 1375 *status |= V4L2_IN_ST_NO_SIGNAL; 1376 1377 v4l2_dbg(1, debug, sd, "%s: SDP status = 0x%x\n", 1378 __func__, *status); 1379 return 0; 1380 } 1381 /* status from CP block */ 1382 if ((cp_read(sd, 0xb5) & 0xd0) != 0xd0 || 1383 !(cp_read(sd, 0xb1) & 0x80)) 1384 /* TODO channel 2 */ 1385 *status |= V4L2_IN_ST_NO_SIGNAL; 1386 1387 if (is_digital_input(sd) && ((io_read(sd, 0x74) & 0x03) != 0x03)) 1388 *status |= V4L2_IN_ST_NO_SIGNAL; 1389 1390 v4l2_dbg(1, debug, sd, "%s: CP status = 0x%x\n", 1391 __func__, *status); 1392 1393 return 0; 1394 } 1395 1396 struct stdi_readback { 1397 u16 bl, lcf, lcvs; 1398 u8 hs_pol, vs_pol; 1399 bool interlaced; 1400 }; 1401 1402 static int stdi2dv_timings(struct v4l2_subdev *sd, 1403 struct stdi_readback *stdi, 1404 struct v4l2_dv_timings *timings) 1405 { 1406 struct adv7842_state *state = to_state(sd); 1407 u32 hfreq = (ADV7842_fsc * 8) / stdi->bl; 1408 u32 pix_clk; 1409 int i; 1410 1411 for (i = 0; v4l2_dv_timings_presets[i].bt.width; i++) { 1412 const struct v4l2_bt_timings *bt = &v4l2_dv_timings_presets[i].bt; 1413 1414 if (!v4l2_valid_dv_timings(&v4l2_dv_timings_presets[i], 1415 adv7842_get_dv_timings_cap(sd), 1416 adv7842_check_dv_timings, NULL)) 1417 continue; 1418 if (vtotal(bt) != stdi->lcf + 1) 1419 continue; 1420 if (bt->vsync != stdi->lcvs) 1421 continue; 1422 1423 pix_clk = hfreq * htotal(bt); 1424 1425 if ((pix_clk < bt->pixelclock + 1000000) && 1426 (pix_clk > bt->pixelclock - 1000000)) { 1427 *timings = v4l2_dv_timings_presets[i]; 1428 return 0; 1429 } 1430 } 1431 1432 if (v4l2_detect_cvt(stdi->lcf + 1, hfreq, stdi->lcvs, 0, 1433 (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) | 1434 (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0), 1435 false, timings)) 1436 return 0; 1437 if (v4l2_detect_gtf(stdi->lcf + 1, hfreq, stdi->lcvs, 1438 (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) | 1439 (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0), 1440 false, state->aspect_ratio, timings)) 1441 return 0; 1442 1443 v4l2_dbg(2, debug, sd, 1444 "%s: No format candidate found for lcvs = %d, lcf=%d, bl = %d, %chsync, %cvsync\n", 1445 __func__, stdi->lcvs, stdi->lcf, stdi->bl, 1446 stdi->hs_pol, stdi->vs_pol); 1447 return -1; 1448 } 1449 1450 static int read_stdi(struct v4l2_subdev *sd, struct stdi_readback *stdi) 1451 { 1452 u32 status; 1453 1454 adv7842_g_input_status(sd, &status); 1455 if (status & V4L2_IN_ST_NO_SIGNAL) { 1456 v4l2_dbg(2, debug, sd, "%s: no signal\n", __func__); 1457 return -ENOLINK; 1458 } 1459 1460 stdi->bl = ((cp_read(sd, 0xb1) & 0x3f) << 8) | cp_read(sd, 0xb2); 1461 stdi->lcf = ((cp_read(sd, 0xb3) & 0x7) << 8) | cp_read(sd, 0xb4); 1462 stdi->lcvs = cp_read(sd, 0xb3) >> 3; 1463 1464 if ((cp_read(sd, 0xb5) & 0x80) && ((cp_read(sd, 0xb5) & 0x03) == 0x01)) { 1465 stdi->hs_pol = ((cp_read(sd, 0xb5) & 0x10) ? 1466 ((cp_read(sd, 0xb5) & 0x08) ? '+' : '-') : 'x'); 1467 stdi->vs_pol = ((cp_read(sd, 0xb5) & 0x40) ? 1468 ((cp_read(sd, 0xb5) & 0x20) ? '+' : '-') : 'x'); 1469 } else { 1470 stdi->hs_pol = 'x'; 1471 stdi->vs_pol = 'x'; 1472 } 1473 stdi->interlaced = (cp_read(sd, 0xb1) & 0x40) ? true : false; 1474 1475 if (stdi->lcf < 239 || stdi->bl < 8 || stdi->bl == 0x3fff) { 1476 v4l2_dbg(2, debug, sd, "%s: invalid signal\n", __func__); 1477 return -ENOLINK; 1478 } 1479 1480 v4l2_dbg(2, debug, sd, 1481 "%s: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %chsync, %cvsync, %s\n", 1482 __func__, stdi->lcf, stdi->bl, stdi->lcvs, 1483 stdi->hs_pol, stdi->vs_pol, 1484 stdi->interlaced ? "interlaced" : "progressive"); 1485 1486 return 0; 1487 } 1488 1489 static int adv7842_enum_dv_timings(struct v4l2_subdev *sd, 1490 struct v4l2_enum_dv_timings *timings) 1491 { 1492 if (timings->pad != 0) 1493 return -EINVAL; 1494 1495 return v4l2_enum_dv_timings_cap(timings, 1496 adv7842_get_dv_timings_cap(sd), adv7842_check_dv_timings, NULL); 1497 } 1498 1499 static int adv7842_dv_timings_cap(struct v4l2_subdev *sd, 1500 struct v4l2_dv_timings_cap *cap) 1501 { 1502 if (cap->pad != 0) 1503 return -EINVAL; 1504 1505 *cap = *adv7842_get_dv_timings_cap(sd); 1506 return 0; 1507 } 1508 1509 /* Fill the optional fields .standards and .flags in struct v4l2_dv_timings 1510 if the format is listed in adv7842_timings[] */ 1511 static void adv7842_fill_optional_dv_timings_fields(struct v4l2_subdev *sd, 1512 struct v4l2_dv_timings *timings) 1513 { 1514 v4l2_find_dv_timings_cap(timings, adv7842_get_dv_timings_cap(sd), 1515 is_digital_input(sd) ? 250000 : 1000000, 1516 adv7842_check_dv_timings, NULL); 1517 timings->bt.flags |= V4L2_DV_FL_CAN_DETECT_REDUCED_FPS; 1518 } 1519 1520 static int adv7842_query_dv_timings(struct v4l2_subdev *sd, 1521 struct v4l2_dv_timings *timings) 1522 { 1523 struct adv7842_state *state = to_state(sd); 1524 struct v4l2_bt_timings *bt = &timings->bt; 1525 struct stdi_readback stdi = { 0 }; 1526 1527 v4l2_dbg(1, debug, sd, "%s:\n", __func__); 1528 1529 memset(timings, 0, sizeof(struct v4l2_dv_timings)); 1530 1531 /* SDP block */ 1532 if (state->mode == ADV7842_MODE_SDP) 1533 return -ENODATA; 1534 1535 /* read STDI */ 1536 if (read_stdi(sd, &stdi)) { 1537 state->restart_stdi_once = true; 1538 v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__); 1539 return -ENOLINK; 1540 } 1541 bt->interlaced = stdi.interlaced ? 1542 V4L2_DV_INTERLACED : V4L2_DV_PROGRESSIVE; 1543 bt->standards = V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT | 1544 V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT; 1545 1546 if (is_digital_input(sd)) { 1547 u32 freq; 1548 1549 timings->type = V4L2_DV_BT_656_1120; 1550 1551 bt->width = (hdmi_read(sd, 0x07) & 0x0f) * 256 + hdmi_read(sd, 0x08); 1552 bt->height = (hdmi_read(sd, 0x09) & 0x0f) * 256 + hdmi_read(sd, 0x0a); 1553 freq = ((hdmi_read(sd, 0x51) << 1) + (hdmi_read(sd, 0x52) >> 7)) * 1000000; 1554 freq += ((hdmi_read(sd, 0x52) & 0x7f) * 7813); 1555 if (is_hdmi(sd)) { 1556 /* adjust for deep color mode */ 1557 freq = freq * 8 / (((hdmi_read(sd, 0x0b) & 0xc0) >> 6) * 2 + 8); 1558 } 1559 bt->pixelclock = freq; 1560 bt->hfrontporch = (hdmi_read(sd, 0x20) & 0x03) * 256 + 1561 hdmi_read(sd, 0x21); 1562 bt->hsync = (hdmi_read(sd, 0x22) & 0x03) * 256 + 1563 hdmi_read(sd, 0x23); 1564 bt->hbackporch = (hdmi_read(sd, 0x24) & 0x03) * 256 + 1565 hdmi_read(sd, 0x25); 1566 bt->vfrontporch = ((hdmi_read(sd, 0x2a) & 0x1f) * 256 + 1567 hdmi_read(sd, 0x2b)) / 2; 1568 bt->vsync = ((hdmi_read(sd, 0x2e) & 0x1f) * 256 + 1569 hdmi_read(sd, 0x2f)) / 2; 1570 bt->vbackporch = ((hdmi_read(sd, 0x32) & 0x1f) * 256 + 1571 hdmi_read(sd, 0x33)) / 2; 1572 bt->polarities = ((hdmi_read(sd, 0x05) & 0x10) ? V4L2_DV_VSYNC_POS_POL : 0) | 1573 ((hdmi_read(sd, 0x05) & 0x20) ? V4L2_DV_HSYNC_POS_POL : 0); 1574 if (bt->interlaced == V4L2_DV_INTERLACED) { 1575 bt->height += (hdmi_read(sd, 0x0b) & 0x0f) * 256 + 1576 hdmi_read(sd, 0x0c); 1577 bt->il_vfrontporch = ((hdmi_read(sd, 0x2c) & 0x1f) * 256 + 1578 hdmi_read(sd, 0x2d)) / 2; 1579 bt->il_vsync = ((hdmi_read(sd, 0x30) & 0x1f) * 256 + 1580 hdmi_read(sd, 0x31)) / 2; 1581 bt->il_vbackporch = ((hdmi_read(sd, 0x34) & 0x1f) * 256 + 1582 hdmi_read(sd, 0x35)) / 2; 1583 } else { 1584 bt->il_vfrontporch = 0; 1585 bt->il_vsync = 0; 1586 bt->il_vbackporch = 0; 1587 } 1588 adv7842_fill_optional_dv_timings_fields(sd, timings); 1589 if ((timings->bt.flags & V4L2_DV_FL_CAN_REDUCE_FPS) && 1590 freq < bt->pixelclock) { 1591 u32 reduced_freq = ((u32)bt->pixelclock / 1001) * 1000; 1592 u32 delta_freq = abs(freq - reduced_freq); 1593 1594 if (delta_freq < ((u32)bt->pixelclock - reduced_freq) / 2) 1595 timings->bt.flags |= V4L2_DV_FL_REDUCED_FPS; 1596 } 1597 } else { 1598 /* find format 1599 * Since LCVS values are inaccurate [REF_03, p. 339-340], 1600 * stdi2dv_timings() is called with lcvs +-1 if the first attempt fails. 1601 */ 1602 if (!stdi2dv_timings(sd, &stdi, timings)) 1603 goto found; 1604 stdi.lcvs += 1; 1605 v4l2_dbg(1, debug, sd, "%s: lcvs + 1 = %d\n", __func__, stdi.lcvs); 1606 if (!stdi2dv_timings(sd, &stdi, timings)) 1607 goto found; 1608 stdi.lcvs -= 2; 1609 v4l2_dbg(1, debug, sd, "%s: lcvs - 1 = %d\n", __func__, stdi.lcvs); 1610 if (stdi2dv_timings(sd, &stdi, timings)) { 1611 /* 1612 * The STDI block may measure wrong values, especially 1613 * for lcvs and lcf. If the driver can not find any 1614 * valid timing, the STDI block is restarted to measure 1615 * the video timings again. The function will return an 1616 * error, but the restart of STDI will generate a new 1617 * STDI interrupt and the format detection process will 1618 * restart. 1619 */ 1620 if (state->restart_stdi_once) { 1621 v4l2_dbg(1, debug, sd, "%s: restart STDI\n", __func__); 1622 /* TODO restart STDI for Sync Channel 2 */ 1623 /* enter one-shot mode */ 1624 cp_write_and_or(sd, 0x86, 0xf9, 0x00); 1625 /* trigger STDI restart */ 1626 cp_write_and_or(sd, 0x86, 0xf9, 0x04); 1627 /* reset to continuous mode */ 1628 cp_write_and_or(sd, 0x86, 0xf9, 0x02); 1629 state->restart_stdi_once = false; 1630 return -ENOLINK; 1631 } 1632 v4l2_dbg(1, debug, sd, "%s: format not supported\n", __func__); 1633 return -ERANGE; 1634 } 1635 state->restart_stdi_once = true; 1636 } 1637 found: 1638 1639 if (debug > 1) 1640 v4l2_print_dv_timings(sd->name, "adv7842_query_dv_timings:", 1641 timings, true); 1642 return 0; 1643 } 1644 1645 static int adv7842_s_dv_timings(struct v4l2_subdev *sd, 1646 struct v4l2_dv_timings *timings) 1647 { 1648 struct adv7842_state *state = to_state(sd); 1649 struct v4l2_bt_timings *bt; 1650 int err; 1651 1652 v4l2_dbg(1, debug, sd, "%s:\n", __func__); 1653 1654 if (state->mode == ADV7842_MODE_SDP) 1655 return -ENODATA; 1656 1657 if (v4l2_match_dv_timings(&state->timings, timings, 0, false)) { 1658 v4l2_dbg(1, debug, sd, "%s: no change\n", __func__); 1659 return 0; 1660 } 1661 1662 bt = &timings->bt; 1663 1664 if (!v4l2_valid_dv_timings(timings, adv7842_get_dv_timings_cap(sd), 1665 adv7842_check_dv_timings, NULL)) 1666 return -ERANGE; 1667 1668 adv7842_fill_optional_dv_timings_fields(sd, timings); 1669 1670 state->timings = *timings; 1671 1672 cp_write(sd, 0x91, bt->interlaced ? 0x40 : 0x00); 1673 1674 /* Use prim_mode and vid_std when available */ 1675 err = configure_predefined_video_timings(sd, timings); 1676 if (err) { 1677 /* custom settings when the video format 1678 does not have prim_mode/vid_std */ 1679 configure_custom_video_timings(sd, bt); 1680 } 1681 1682 set_rgb_quantization_range(sd); 1683 1684 1685 if (debug > 1) 1686 v4l2_print_dv_timings(sd->name, "adv7842_s_dv_timings: ", 1687 timings, true); 1688 return 0; 1689 } 1690 1691 static int adv7842_g_dv_timings(struct v4l2_subdev *sd, 1692 struct v4l2_dv_timings *timings) 1693 { 1694 struct adv7842_state *state = to_state(sd); 1695 1696 if (state->mode == ADV7842_MODE_SDP) 1697 return -ENODATA; 1698 *timings = state->timings; 1699 return 0; 1700 } 1701 1702 static void enable_input(struct v4l2_subdev *sd) 1703 { 1704 struct adv7842_state *state = to_state(sd); 1705 1706 set_rgb_quantization_range(sd); 1707 switch (state->mode) { 1708 case ADV7842_MODE_SDP: 1709 case ADV7842_MODE_COMP: 1710 case ADV7842_MODE_RGB: 1711 io_write(sd, 0x15, 0xb0); /* Disable Tristate of Pins (no audio) */ 1712 break; 1713 case ADV7842_MODE_HDMI: 1714 hdmi_write(sd, 0x01, 0x00); /* Enable HDMI clock terminators */ 1715 io_write(sd, 0x15, 0xa0); /* Disable Tristate of Pins */ 1716 hdmi_write_and_or(sd, 0x1a, 0xef, 0x00); /* Unmute audio */ 1717 break; 1718 default: 1719 v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n", 1720 __func__, state->mode); 1721 break; 1722 } 1723 } 1724 1725 static void disable_input(struct v4l2_subdev *sd) 1726 { 1727 hdmi_write_and_or(sd, 0x1a, 0xef, 0x10); /* Mute audio [REF_01, c. 2.2.2] */ 1728 msleep(16); /* 512 samples with >= 32 kHz sample rate [REF_03, c. 8.29] */ 1729 io_write(sd, 0x15, 0xbe); /* Tristate all outputs from video core */ 1730 hdmi_write(sd, 0x01, 0x78); /* Disable HDMI clock terminators */ 1731 } 1732 1733 static void sdp_csc_coeff(struct v4l2_subdev *sd, 1734 const struct adv7842_sdp_csc_coeff *c) 1735 { 1736 /* csc auto/manual */ 1737 sdp_io_write_and_or(sd, 0xe0, 0xbf, c->manual ? 0x00 : 0x40); 1738 1739 if (!c->manual) 1740 return; 1741 1742 /* csc scaling */ 1743 sdp_io_write_and_or(sd, 0xe0, 0x7f, c->scaling == 2 ? 0x80 : 0x00); 1744 1745 /* A coeff */ 1746 sdp_io_write_and_or(sd, 0xe0, 0xe0, c->A1 >> 8); 1747 sdp_io_write(sd, 0xe1, c->A1); 1748 sdp_io_write_and_or(sd, 0xe2, 0xe0, c->A2 >> 8); 1749 sdp_io_write(sd, 0xe3, c->A2); 1750 sdp_io_write_and_or(sd, 0xe4, 0xe0, c->A3 >> 8); 1751 sdp_io_write(sd, 0xe5, c->A3); 1752 1753 /* A scale */ 1754 sdp_io_write_and_or(sd, 0xe6, 0x80, c->A4 >> 8); 1755 sdp_io_write(sd, 0xe7, c->A4); 1756 1757 /* B coeff */ 1758 sdp_io_write_and_or(sd, 0xe8, 0xe0, c->B1 >> 8); 1759 sdp_io_write(sd, 0xe9, c->B1); 1760 sdp_io_write_and_or(sd, 0xea, 0xe0, c->B2 >> 8); 1761 sdp_io_write(sd, 0xeb, c->B2); 1762 sdp_io_write_and_or(sd, 0xec, 0xe0, c->B3 >> 8); 1763 sdp_io_write(sd, 0xed, c->B3); 1764 1765 /* B scale */ 1766 sdp_io_write_and_or(sd, 0xee, 0x80, c->B4 >> 8); 1767 sdp_io_write(sd, 0xef, c->B4); 1768 1769 /* C coeff */ 1770 sdp_io_write_and_or(sd, 0xf0, 0xe0, c->C1 >> 8); 1771 sdp_io_write(sd, 0xf1, c->C1); 1772 sdp_io_write_and_or(sd, 0xf2, 0xe0, c->C2 >> 8); 1773 sdp_io_write(sd, 0xf3, c->C2); 1774 sdp_io_write_and_or(sd, 0xf4, 0xe0, c->C3 >> 8); 1775 sdp_io_write(sd, 0xf5, c->C3); 1776 1777 /* C scale */ 1778 sdp_io_write_and_or(sd, 0xf6, 0x80, c->C4 >> 8); 1779 sdp_io_write(sd, 0xf7, c->C4); 1780 } 1781 1782 static void select_input(struct v4l2_subdev *sd, 1783 enum adv7842_vid_std_select vid_std_select) 1784 { 1785 struct adv7842_state *state = to_state(sd); 1786 1787 switch (state->mode) { 1788 case ADV7842_MODE_SDP: 1789 io_write(sd, 0x00, vid_std_select); /* video std: CVBS or YC mode */ 1790 io_write(sd, 0x01, 0); /* prim mode */ 1791 /* enable embedded syncs for auto graphics mode */ 1792 cp_write_and_or(sd, 0x81, 0xef, 0x10); 1793 1794 afe_write(sd, 0x00, 0x00); /* power up ADC */ 1795 afe_write(sd, 0xc8, 0x00); /* phase control */ 1796 1797 io_write(sd, 0xdd, 0x90); /* Manual 2x output clock */ 1798 /* script says register 0xde, which don't exist in manual */ 1799 1800 /* Manual analog input muxing mode, CVBS (6.4)*/ 1801 afe_write_and_or(sd, 0x02, 0x7f, 0x80); 1802 if (vid_std_select == ADV7842_SDP_VID_STD_CVBS_SD_4x1) { 1803 afe_write(sd, 0x03, 0xa0); /* ADC0 to AIN10 (CVBS), ADC1 N/C*/ 1804 afe_write(sd, 0x04, 0x00); /* ADC2 N/C,ADC3 N/C*/ 1805 } else { 1806 afe_write(sd, 0x03, 0xa0); /* ADC0 to AIN10 (CVBS), ADC1 N/C*/ 1807 afe_write(sd, 0x04, 0xc0); /* ADC2 to AIN12, ADC3 N/C*/ 1808 } 1809 afe_write(sd, 0x0c, 0x1f); /* ADI recommend write */ 1810 afe_write(sd, 0x12, 0x63); /* ADI recommend write */ 1811 1812 sdp_io_write(sd, 0xb2, 0x60); /* Disable AV codes */ 1813 sdp_io_write(sd, 0xc8, 0xe3); /* Disable Ancillary data */ 1814 1815 /* SDP recommended settings */ 1816 sdp_write(sd, 0x00, 0x3F); /* Autodetect PAL NTSC (not SECAM) */ 1817 sdp_write(sd, 0x01, 0x00); /* Pedestal Off */ 1818 1819 sdp_write(sd, 0x03, 0xE4); /* Manual VCR Gain Luma 0x40B */ 1820 sdp_write(sd, 0x04, 0x0B); /* Manual Luma setting */ 1821 sdp_write(sd, 0x05, 0xC3); /* Manual Chroma setting 0x3FE */ 1822 sdp_write(sd, 0x06, 0xFE); /* Manual Chroma setting */ 1823 sdp_write(sd, 0x12, 0x0D); /* Frame TBC,I_P, 3D comb enabled */ 1824 sdp_write(sd, 0xA7, 0x00); /* ADI Recommended Write */ 1825 sdp_io_write(sd, 0xB0, 0x00); /* Disable H and v blanking */ 1826 1827 /* deinterlacer enabled and 3D comb */ 1828 sdp_write_and_or(sd, 0x12, 0xf6, 0x09); 1829 1830 break; 1831 1832 case ADV7842_MODE_COMP: 1833 case ADV7842_MODE_RGB: 1834 /* Automatic analog input muxing mode */ 1835 afe_write_and_or(sd, 0x02, 0x7f, 0x00); 1836 /* set mode and select free run resolution */ 1837 io_write(sd, 0x00, vid_std_select); /* video std */ 1838 io_write(sd, 0x01, 0x02); /* prim mode */ 1839 cp_write_and_or(sd, 0x81, 0xef, 0x10); /* enable embedded syncs 1840 for auto graphics mode */ 1841 1842 afe_write(sd, 0x00, 0x00); /* power up ADC */ 1843 afe_write(sd, 0xc8, 0x00); /* phase control */ 1844 if (state->mode == ADV7842_MODE_COMP) { 1845 /* force to YCrCb */ 1846 io_write_and_or(sd, 0x02, 0x0f, 0x60); 1847 } else { 1848 /* force to RGB */ 1849 io_write_and_or(sd, 0x02, 0x0f, 0x10); 1850 } 1851 1852 /* set ADI recommended settings for digitizer */ 1853 /* "ADV7842 Register Settings Recommendations 1854 * (rev. 1.8, November 2010)" p. 9. */ 1855 afe_write(sd, 0x0c, 0x1f); /* ADC Range improvement */ 1856 afe_write(sd, 0x12, 0x63); /* ADC Range improvement */ 1857 1858 /* set to default gain for RGB */ 1859 cp_write(sd, 0x73, 0x10); 1860 cp_write(sd, 0x74, 0x04); 1861 cp_write(sd, 0x75, 0x01); 1862 cp_write(sd, 0x76, 0x00); 1863 1864 cp_write(sd, 0x3e, 0x04); /* CP core pre-gain control */ 1865 cp_write(sd, 0xc3, 0x39); /* CP coast control. Graphics mode */ 1866 cp_write(sd, 0x40, 0x5c); /* CP core pre-gain control. Graphics mode */ 1867 break; 1868 1869 case ADV7842_MODE_HDMI: 1870 /* Automatic analog input muxing mode */ 1871 afe_write_and_or(sd, 0x02, 0x7f, 0x00); 1872 /* set mode and select free run resolution */ 1873 if (state->hdmi_port_a) 1874 hdmi_write(sd, 0x00, 0x02); /* select port A */ 1875 else 1876 hdmi_write(sd, 0x00, 0x03); /* select port B */ 1877 io_write(sd, 0x00, vid_std_select); /* video std */ 1878 io_write(sd, 0x01, 5); /* prim mode */ 1879 cp_write_and_or(sd, 0x81, 0xef, 0x00); /* disable embedded syncs 1880 for auto graphics mode */ 1881 1882 /* set ADI recommended settings for HDMI: */ 1883 /* "ADV7842 Register Settings Recommendations 1884 * (rev. 1.8, November 2010)" p. 3. */ 1885 hdmi_write(sd, 0xc0, 0x00); 1886 hdmi_write(sd, 0x0d, 0x34); /* ADI recommended write */ 1887 hdmi_write(sd, 0x3d, 0x10); /* ADI recommended write */ 1888 hdmi_write(sd, 0x44, 0x85); /* TMDS PLL optimization */ 1889 hdmi_write(sd, 0x46, 0x1f); /* ADI recommended write */ 1890 hdmi_write(sd, 0x57, 0xb6); /* TMDS PLL optimization */ 1891 hdmi_write(sd, 0x58, 0x03); /* TMDS PLL optimization */ 1892 hdmi_write(sd, 0x60, 0x88); /* TMDS PLL optimization */ 1893 hdmi_write(sd, 0x61, 0x88); /* TMDS PLL optimization */ 1894 hdmi_write(sd, 0x6c, 0x18); /* Disable ISRC clearing bit, 1895 Improve robustness */ 1896 hdmi_write(sd, 0x75, 0x10); /* DDC drive strength */ 1897 hdmi_write(sd, 0x85, 0x1f); /* equaliser */ 1898 hdmi_write(sd, 0x87, 0x70); /* ADI recommended write */ 1899 hdmi_write(sd, 0x89, 0x04); /* equaliser */ 1900 hdmi_write(sd, 0x8a, 0x1e); /* equaliser */ 1901 hdmi_write(sd, 0x93, 0x04); /* equaliser */ 1902 hdmi_write(sd, 0x94, 0x1e); /* equaliser */ 1903 hdmi_write(sd, 0x99, 0xa1); /* ADI recommended write */ 1904 hdmi_write(sd, 0x9b, 0x09); /* ADI recommended write */ 1905 hdmi_write(sd, 0x9d, 0x02); /* equaliser */ 1906 1907 afe_write(sd, 0x00, 0xff); /* power down ADC */ 1908 afe_write(sd, 0xc8, 0x40); /* phase control */ 1909 1910 /* set to default gain for HDMI */ 1911 cp_write(sd, 0x73, 0x10); 1912 cp_write(sd, 0x74, 0x04); 1913 cp_write(sd, 0x75, 0x01); 1914 cp_write(sd, 0x76, 0x00); 1915 1916 /* reset ADI recommended settings for digitizer */ 1917 /* "ADV7842 Register Settings Recommendations 1918 * (rev. 2.5, June 2010)" p. 17. */ 1919 afe_write(sd, 0x12, 0xfb); /* ADC noise shaping filter controls */ 1920 afe_write(sd, 0x0c, 0x0d); /* CP core gain controls */ 1921 cp_write(sd, 0x3e, 0x00); /* CP core pre-gain control */ 1922 1923 /* CP coast control */ 1924 cp_write(sd, 0xc3, 0x33); /* Component mode */ 1925 1926 /* color space conversion, autodetect color space */ 1927 io_write_and_or(sd, 0x02, 0x0f, 0xf0); 1928 break; 1929 1930 default: 1931 v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n", 1932 __func__, state->mode); 1933 break; 1934 } 1935 } 1936 1937 static int adv7842_s_routing(struct v4l2_subdev *sd, 1938 u32 input, u32 output, u32 config) 1939 { 1940 struct adv7842_state *state = to_state(sd); 1941 1942 v4l2_dbg(2, debug, sd, "%s: input %d\n", __func__, input); 1943 1944 switch (input) { 1945 case ADV7842_SELECT_HDMI_PORT_A: 1946 state->mode = ADV7842_MODE_HDMI; 1947 state->vid_std_select = ADV7842_HDMI_COMP_VID_STD_HD_1250P; 1948 state->hdmi_port_a = true; 1949 break; 1950 case ADV7842_SELECT_HDMI_PORT_B: 1951 state->mode = ADV7842_MODE_HDMI; 1952 state->vid_std_select = ADV7842_HDMI_COMP_VID_STD_HD_1250P; 1953 state->hdmi_port_a = false; 1954 break; 1955 case ADV7842_SELECT_VGA_COMP: 1956 state->mode = ADV7842_MODE_COMP; 1957 state->vid_std_select = ADV7842_RGB_VID_STD_AUTO_GRAPH_MODE; 1958 break; 1959 case ADV7842_SELECT_VGA_RGB: 1960 state->mode = ADV7842_MODE_RGB; 1961 state->vid_std_select = ADV7842_RGB_VID_STD_AUTO_GRAPH_MODE; 1962 break; 1963 case ADV7842_SELECT_SDP_CVBS: 1964 state->mode = ADV7842_MODE_SDP; 1965 state->vid_std_select = ADV7842_SDP_VID_STD_CVBS_SD_4x1; 1966 break; 1967 case ADV7842_SELECT_SDP_YC: 1968 state->mode = ADV7842_MODE_SDP; 1969 state->vid_std_select = ADV7842_SDP_VID_STD_YC_SD4_x1; 1970 break; 1971 default: 1972 return -EINVAL; 1973 } 1974 1975 disable_input(sd); 1976 select_input(sd, state->vid_std_select); 1977 enable_input(sd); 1978 1979 v4l2_subdev_notify_event(sd, &adv7842_ev_fmt); 1980 1981 return 0; 1982 } 1983 1984 static int adv7842_enum_mbus_code(struct v4l2_subdev *sd, 1985 struct v4l2_subdev_pad_config *cfg, 1986 struct v4l2_subdev_mbus_code_enum *code) 1987 { 1988 if (code->index >= ARRAY_SIZE(adv7842_formats)) 1989 return -EINVAL; 1990 code->code = adv7842_formats[code->index].code; 1991 return 0; 1992 } 1993 1994 static void adv7842_fill_format(struct adv7842_state *state, 1995 struct v4l2_mbus_framefmt *format) 1996 { 1997 memset(format, 0, sizeof(*format)); 1998 1999 format->width = state->timings.bt.width; 2000 format->height = state->timings.bt.height; 2001 format->field = V4L2_FIELD_NONE; 2002 format->colorspace = V4L2_COLORSPACE_SRGB; 2003 2004 if (state->timings.bt.flags & V4L2_DV_FL_IS_CE_VIDEO) 2005 format->colorspace = (state->timings.bt.height <= 576) ? 2006 V4L2_COLORSPACE_SMPTE170M : V4L2_COLORSPACE_REC709; 2007 } 2008 2009 /* 2010 * Compute the op_ch_sel value required to obtain on the bus the component order 2011 * corresponding to the selected format taking into account bus reordering 2012 * applied by the board at the output of the device. 2013 * 2014 * The following table gives the op_ch_value from the format component order 2015 * (expressed as op_ch_sel value in column) and the bus reordering (expressed as 2016 * adv7842_bus_order value in row). 2017 * 2018 * | GBR(0) GRB(1) BGR(2) RGB(3) BRG(4) RBG(5) 2019 * ----------+------------------------------------------------- 2020 * RGB (NOP) | GBR GRB BGR RGB BRG RBG 2021 * GRB (1-2) | BGR RGB GBR GRB RBG BRG 2022 * RBG (2-3) | GRB GBR BRG RBG BGR RGB 2023 * BGR (1-3) | RBG BRG RGB BGR GRB GBR 2024 * BRG (ROR) | BRG RBG GRB GBR RGB BGR 2025 * GBR (ROL) | RGB BGR RBG BRG GBR GRB 2026 */ 2027 static unsigned int adv7842_op_ch_sel(struct adv7842_state *state) 2028 { 2029 #define _SEL(a, b, c, d, e, f) { \ 2030 ADV7842_OP_CH_SEL_##a, ADV7842_OP_CH_SEL_##b, ADV7842_OP_CH_SEL_##c, \ 2031 ADV7842_OP_CH_SEL_##d, ADV7842_OP_CH_SEL_##e, ADV7842_OP_CH_SEL_##f } 2032 #define _BUS(x) [ADV7842_BUS_ORDER_##x] 2033 2034 static const unsigned int op_ch_sel[6][6] = { 2035 _BUS(RGB) /* NOP */ = _SEL(GBR, GRB, BGR, RGB, BRG, RBG), 2036 _BUS(GRB) /* 1-2 */ = _SEL(BGR, RGB, GBR, GRB, RBG, BRG), 2037 _BUS(RBG) /* 2-3 */ = _SEL(GRB, GBR, BRG, RBG, BGR, RGB), 2038 _BUS(BGR) /* 1-3 */ = _SEL(RBG, BRG, RGB, BGR, GRB, GBR), 2039 _BUS(BRG) /* ROR */ = _SEL(BRG, RBG, GRB, GBR, RGB, BGR), 2040 _BUS(GBR) /* ROL */ = _SEL(RGB, BGR, RBG, BRG, GBR, GRB), 2041 }; 2042 2043 return op_ch_sel[state->pdata.bus_order][state->format->op_ch_sel >> 5]; 2044 } 2045 2046 static void adv7842_setup_format(struct adv7842_state *state) 2047 { 2048 struct v4l2_subdev *sd = &state->sd; 2049 2050 io_write_clr_set(sd, 0x02, 0x02, 2051 state->format->rgb_out ? ADV7842_RGB_OUT : 0); 2052 io_write(sd, 0x03, state->format->op_format_sel | 2053 state->pdata.op_format_mode_sel); 2054 io_write_clr_set(sd, 0x04, 0xe0, adv7842_op_ch_sel(state)); 2055 io_write_clr_set(sd, 0x05, 0x01, 2056 state->format->swap_cb_cr ? ADV7842_OP_SWAP_CB_CR : 0); 2057 set_rgb_quantization_range(sd); 2058 } 2059 2060 static int adv7842_get_format(struct v4l2_subdev *sd, 2061 struct v4l2_subdev_pad_config *cfg, 2062 struct v4l2_subdev_format *format) 2063 { 2064 struct adv7842_state *state = to_state(sd); 2065 2066 if (format->pad != ADV7842_PAD_SOURCE) 2067 return -EINVAL; 2068 2069 if (state->mode == ADV7842_MODE_SDP) { 2070 /* SPD block */ 2071 if (!(sdp_read(sd, 0x5a) & 0x01)) 2072 return -EINVAL; 2073 format->format.code = MEDIA_BUS_FMT_YUYV8_2X8; 2074 format->format.width = 720; 2075 /* valid signal */ 2076 if (state->norm & V4L2_STD_525_60) 2077 format->format.height = 480; 2078 else 2079 format->format.height = 576; 2080 format->format.colorspace = V4L2_COLORSPACE_SMPTE170M; 2081 return 0; 2082 } 2083 2084 adv7842_fill_format(state, &format->format); 2085 2086 if (format->which == V4L2_SUBDEV_FORMAT_TRY) { 2087 struct v4l2_mbus_framefmt *fmt; 2088 2089 fmt = v4l2_subdev_get_try_format(sd, cfg, format->pad); 2090 format->format.code = fmt->code; 2091 } else { 2092 format->format.code = state->format->code; 2093 } 2094 2095 return 0; 2096 } 2097 2098 static int adv7842_set_format(struct v4l2_subdev *sd, 2099 struct v4l2_subdev_pad_config *cfg, 2100 struct v4l2_subdev_format *format) 2101 { 2102 struct adv7842_state *state = to_state(sd); 2103 const struct adv7842_format_info *info; 2104 2105 if (format->pad != ADV7842_PAD_SOURCE) 2106 return -EINVAL; 2107 2108 if (state->mode == ADV7842_MODE_SDP) 2109 return adv7842_get_format(sd, cfg, format); 2110 2111 info = adv7842_format_info(state, format->format.code); 2112 if (info == NULL) 2113 info = adv7842_format_info(state, MEDIA_BUS_FMT_YUYV8_2X8); 2114 2115 adv7842_fill_format(state, &format->format); 2116 format->format.code = info->code; 2117 2118 if (format->which == V4L2_SUBDEV_FORMAT_TRY) { 2119 struct v4l2_mbus_framefmt *fmt; 2120 2121 fmt = v4l2_subdev_get_try_format(sd, cfg, format->pad); 2122 fmt->code = format->format.code; 2123 } else { 2124 state->format = info; 2125 adv7842_setup_format(state); 2126 } 2127 2128 return 0; 2129 } 2130 2131 static void adv7842_irq_enable(struct v4l2_subdev *sd, bool enable) 2132 { 2133 if (enable) { 2134 /* Enable SSPD, STDI and CP locked/unlocked interrupts */ 2135 io_write(sd, 0x46, 0x9c); 2136 /* ESDP_50HZ_DET interrupt */ 2137 io_write(sd, 0x5a, 0x10); 2138 /* Enable CABLE_DET_A/B_ST (+5v) interrupt */ 2139 io_write(sd, 0x73, 0x03); 2140 /* Enable V_LOCKED and DE_REGEN_LCK interrupts */ 2141 io_write(sd, 0x78, 0x03); 2142 /* Enable SDP Standard Detection Change and SDP Video Detected */ 2143 io_write(sd, 0xa0, 0x09); 2144 /* Enable HDMI_MODE interrupt */ 2145 io_write(sd, 0x69, 0x08); 2146 } else { 2147 io_write(sd, 0x46, 0x0); 2148 io_write(sd, 0x5a, 0x0); 2149 io_write(sd, 0x73, 0x0); 2150 io_write(sd, 0x78, 0x0); 2151 io_write(sd, 0xa0, 0x0); 2152 io_write(sd, 0x69, 0x0); 2153 } 2154 } 2155 2156 #if IS_ENABLED(CONFIG_VIDEO_ADV7842_CEC) 2157 static void adv7842_cec_tx_raw_status(struct v4l2_subdev *sd, u8 tx_raw_status) 2158 { 2159 struct adv7842_state *state = to_state(sd); 2160 2161 if ((cec_read(sd, 0x11) & 0x01) == 0) { 2162 v4l2_dbg(1, debug, sd, "%s: tx raw: tx disabled\n", __func__); 2163 return; 2164 } 2165 2166 if (tx_raw_status & 0x02) { 2167 v4l2_dbg(1, debug, sd, "%s: tx raw: arbitration lost\n", 2168 __func__); 2169 cec_transmit_done(state->cec_adap, CEC_TX_STATUS_ARB_LOST, 2170 1, 0, 0, 0); 2171 return; 2172 } 2173 if (tx_raw_status & 0x04) { 2174 u8 status; 2175 u8 nack_cnt; 2176 u8 low_drive_cnt; 2177 2178 v4l2_dbg(1, debug, sd, "%s: tx raw: retry failed\n", __func__); 2179 /* 2180 * We set this status bit since this hardware performs 2181 * retransmissions. 2182 */ 2183 status = CEC_TX_STATUS_MAX_RETRIES; 2184 nack_cnt = cec_read(sd, 0x14) & 0xf; 2185 if (nack_cnt) 2186 status |= CEC_TX_STATUS_NACK; 2187 low_drive_cnt = cec_read(sd, 0x14) >> 4; 2188 if (low_drive_cnt) 2189 status |= CEC_TX_STATUS_LOW_DRIVE; 2190 cec_transmit_done(state->cec_adap, status, 2191 0, nack_cnt, low_drive_cnt, 0); 2192 return; 2193 } 2194 if (tx_raw_status & 0x01) { 2195 v4l2_dbg(1, debug, sd, "%s: tx raw: ready ok\n", __func__); 2196 cec_transmit_done(state->cec_adap, CEC_TX_STATUS_OK, 0, 0, 0, 0); 2197 return; 2198 } 2199 } 2200 2201 static void adv7842_cec_isr(struct v4l2_subdev *sd, bool *handled) 2202 { 2203 u8 cec_irq; 2204 2205 /* cec controller */ 2206 cec_irq = io_read(sd, 0x93) & 0x0f; 2207 if (!cec_irq) 2208 return; 2209 2210 v4l2_dbg(1, debug, sd, "%s: cec: irq 0x%x\n", __func__, cec_irq); 2211 adv7842_cec_tx_raw_status(sd, cec_irq); 2212 if (cec_irq & 0x08) { 2213 struct adv7842_state *state = to_state(sd); 2214 struct cec_msg msg; 2215 2216 msg.len = cec_read(sd, 0x25) & 0x1f; 2217 if (msg.len > 16) 2218 msg.len = 16; 2219 2220 if (msg.len) { 2221 u8 i; 2222 2223 for (i = 0; i < msg.len; i++) 2224 msg.msg[i] = cec_read(sd, i + 0x15); 2225 cec_write(sd, 0x26, 0x01); /* re-enable rx */ 2226 cec_received_msg(state->cec_adap, &msg); 2227 } 2228 } 2229 2230 io_write(sd, 0x94, cec_irq); 2231 2232 if (handled) 2233 *handled = true; 2234 } 2235 2236 static int adv7842_cec_adap_enable(struct cec_adapter *adap, bool enable) 2237 { 2238 struct adv7842_state *state = cec_get_drvdata(adap); 2239 struct v4l2_subdev *sd = &state->sd; 2240 2241 if (!state->cec_enabled_adap && enable) { 2242 cec_write_clr_set(sd, 0x2a, 0x01, 0x01); /* power up cec */ 2243 cec_write(sd, 0x2c, 0x01); /* cec soft reset */ 2244 cec_write_clr_set(sd, 0x11, 0x01, 0); /* initially disable tx */ 2245 /* enabled irqs: */ 2246 /* tx: ready */ 2247 /* tx: arbitration lost */ 2248 /* tx: retry timeout */ 2249 /* rx: ready */ 2250 io_write_clr_set(sd, 0x96, 0x0f, 0x0f); 2251 cec_write(sd, 0x26, 0x01); /* enable rx */ 2252 } else if (state->cec_enabled_adap && !enable) { 2253 /* disable cec interrupts */ 2254 io_write_clr_set(sd, 0x96, 0x0f, 0x00); 2255 /* disable address mask 1-3 */ 2256 cec_write_clr_set(sd, 0x27, 0x70, 0x00); 2257 /* power down cec section */ 2258 cec_write_clr_set(sd, 0x2a, 0x01, 0x00); 2259 state->cec_valid_addrs = 0; 2260 } 2261 state->cec_enabled_adap = enable; 2262 return 0; 2263 } 2264 2265 static int adv7842_cec_adap_log_addr(struct cec_adapter *adap, u8 addr) 2266 { 2267 struct adv7842_state *state = cec_get_drvdata(adap); 2268 struct v4l2_subdev *sd = &state->sd; 2269 unsigned int i, free_idx = ADV7842_MAX_ADDRS; 2270 2271 if (!state->cec_enabled_adap) 2272 return addr == CEC_LOG_ADDR_INVALID ? 0 : -EIO; 2273 2274 if (addr == CEC_LOG_ADDR_INVALID) { 2275 cec_write_clr_set(sd, 0x27, 0x70, 0); 2276 state->cec_valid_addrs = 0; 2277 return 0; 2278 } 2279 2280 for (i = 0; i < ADV7842_MAX_ADDRS; i++) { 2281 bool is_valid = state->cec_valid_addrs & (1 << i); 2282 2283 if (free_idx == ADV7842_MAX_ADDRS && !is_valid) 2284 free_idx = i; 2285 if (is_valid && state->cec_addr[i] == addr) 2286 return 0; 2287 } 2288 if (i == ADV7842_MAX_ADDRS) { 2289 i = free_idx; 2290 if (i == ADV7842_MAX_ADDRS) 2291 return -ENXIO; 2292 } 2293 state->cec_addr[i] = addr; 2294 state->cec_valid_addrs |= 1 << i; 2295 2296 switch (i) { 2297 case 0: 2298 /* enable address mask 0 */ 2299 cec_write_clr_set(sd, 0x27, 0x10, 0x10); 2300 /* set address for mask 0 */ 2301 cec_write_clr_set(sd, 0x28, 0x0f, addr); 2302 break; 2303 case 1: 2304 /* enable address mask 1 */ 2305 cec_write_clr_set(sd, 0x27, 0x20, 0x20); 2306 /* set address for mask 1 */ 2307 cec_write_clr_set(sd, 0x28, 0xf0, addr << 4); 2308 break; 2309 case 2: 2310 /* enable address mask 2 */ 2311 cec_write_clr_set(sd, 0x27, 0x40, 0x40); 2312 /* set address for mask 1 */ 2313 cec_write_clr_set(sd, 0x29, 0x0f, addr); 2314 break; 2315 } 2316 return 0; 2317 } 2318 2319 static int adv7842_cec_adap_transmit(struct cec_adapter *adap, u8 attempts, 2320 u32 signal_free_time, struct cec_msg *msg) 2321 { 2322 struct adv7842_state *state = cec_get_drvdata(adap); 2323 struct v4l2_subdev *sd = &state->sd; 2324 u8 len = msg->len; 2325 unsigned int i; 2326 2327 /* 2328 * The number of retries is the number of attempts - 1, but retry 2329 * at least once. It's not clear if a value of 0 is allowed, so 2330 * let's do at least one retry. 2331 */ 2332 cec_write_clr_set(sd, 0x12, 0x70, max(1, attempts - 1) << 4); 2333 2334 if (len > 16) { 2335 v4l2_err(sd, "%s: len exceeded 16 (%d)\n", __func__, len); 2336 return -EINVAL; 2337 } 2338 2339 /* write data */ 2340 for (i = 0; i < len; i++) 2341 cec_write(sd, i, msg->msg[i]); 2342 2343 /* set length (data + header) */ 2344 cec_write(sd, 0x10, len); 2345 /* start transmit, enable tx */ 2346 cec_write(sd, 0x11, 0x01); 2347 return 0; 2348 } 2349 2350 static const struct cec_adap_ops adv7842_cec_adap_ops = { 2351 .adap_enable = adv7842_cec_adap_enable, 2352 .adap_log_addr = adv7842_cec_adap_log_addr, 2353 .adap_transmit = adv7842_cec_adap_transmit, 2354 }; 2355 #endif 2356 2357 static int adv7842_isr(struct v4l2_subdev *sd, u32 status, bool *handled) 2358 { 2359 struct adv7842_state *state = to_state(sd); 2360 u8 fmt_change_cp, fmt_change_digital, fmt_change_sdp; 2361 u8 irq_status[6]; 2362 2363 adv7842_irq_enable(sd, false); 2364 2365 /* read status */ 2366 irq_status[0] = io_read(sd, 0x43); 2367 irq_status[1] = io_read(sd, 0x57); 2368 irq_status[2] = io_read(sd, 0x70); 2369 irq_status[3] = io_read(sd, 0x75); 2370 irq_status[4] = io_read(sd, 0x9d); 2371 irq_status[5] = io_read(sd, 0x66); 2372 2373 /* and clear */ 2374 if (irq_status[0]) 2375 io_write(sd, 0x44, irq_status[0]); 2376 if (irq_status[1]) 2377 io_write(sd, 0x58, irq_status[1]); 2378 if (irq_status[2]) 2379 io_write(sd, 0x71, irq_status[2]); 2380 if (irq_status[3]) 2381 io_write(sd, 0x76, irq_status[3]); 2382 if (irq_status[4]) 2383 io_write(sd, 0x9e, irq_status[4]); 2384 if (irq_status[5]) 2385 io_write(sd, 0x67, irq_status[5]); 2386 2387 adv7842_irq_enable(sd, true); 2388 2389 v4l2_dbg(1, debug, sd, "%s: irq %x, %x, %x, %x, %x, %x\n", __func__, 2390 irq_status[0], irq_status[1], irq_status[2], 2391 irq_status[3], irq_status[4], irq_status[5]); 2392 2393 /* format change CP */ 2394 fmt_change_cp = irq_status[0] & 0x9c; 2395 2396 /* format change SDP */ 2397 if (state->mode == ADV7842_MODE_SDP) 2398 fmt_change_sdp = (irq_status[1] & 0x30) | (irq_status[4] & 0x09); 2399 else 2400 fmt_change_sdp = 0; 2401 2402 /* digital format CP */ 2403 if (is_digital_input(sd)) 2404 fmt_change_digital = irq_status[3] & 0x03; 2405 else 2406 fmt_change_digital = 0; 2407 2408 /* format change */ 2409 if (fmt_change_cp || fmt_change_digital || fmt_change_sdp) { 2410 v4l2_dbg(1, debug, sd, 2411 "%s: fmt_change_cp = 0x%x, fmt_change_digital = 0x%x, fmt_change_sdp = 0x%x\n", 2412 __func__, fmt_change_cp, fmt_change_digital, 2413 fmt_change_sdp); 2414 v4l2_subdev_notify_event(sd, &adv7842_ev_fmt); 2415 if (handled) 2416 *handled = true; 2417 } 2418 2419 /* HDMI/DVI mode */ 2420 if (irq_status[5] & 0x08) { 2421 v4l2_dbg(1, debug, sd, "%s: irq %s mode\n", __func__, 2422 (io_read(sd, 0x65) & 0x08) ? "HDMI" : "DVI"); 2423 set_rgb_quantization_range(sd); 2424 if (handled) 2425 *handled = true; 2426 } 2427 2428 #if IS_ENABLED(CONFIG_VIDEO_ADV7842_CEC) 2429 /* cec */ 2430 adv7842_cec_isr(sd, handled); 2431 #endif 2432 2433 /* tx 5v detect */ 2434 if (irq_status[2] & 0x3) { 2435 v4l2_dbg(1, debug, sd, "%s: irq tx_5v\n", __func__); 2436 adv7842_s_detect_tx_5v_ctrl(sd); 2437 if (handled) 2438 *handled = true; 2439 } 2440 return 0; 2441 } 2442 2443 static int adv7842_get_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid) 2444 { 2445 struct adv7842_state *state = to_state(sd); 2446 u8 *data = NULL; 2447 2448 memset(edid->reserved, 0, sizeof(edid->reserved)); 2449 2450 switch (edid->pad) { 2451 case ADV7842_EDID_PORT_A: 2452 case ADV7842_EDID_PORT_B: 2453 if (state->hdmi_edid.present & (0x04 << edid->pad)) 2454 data = state->hdmi_edid.edid; 2455 break; 2456 case ADV7842_EDID_PORT_VGA: 2457 if (state->vga_edid.present) 2458 data = state->vga_edid.edid; 2459 break; 2460 default: 2461 return -EINVAL; 2462 } 2463 2464 if (edid->start_block == 0 && edid->blocks == 0) { 2465 edid->blocks = data ? 2 : 0; 2466 return 0; 2467 } 2468 2469 if (!data) 2470 return -ENODATA; 2471 2472 if (edid->start_block >= 2) 2473 return -EINVAL; 2474 2475 if (edid->start_block + edid->blocks > 2) 2476 edid->blocks = 2 - edid->start_block; 2477 2478 memcpy(edid->edid, data + edid->start_block * 128, edid->blocks * 128); 2479 2480 return 0; 2481 } 2482 2483 static int adv7842_set_edid(struct v4l2_subdev *sd, struct v4l2_edid *e) 2484 { 2485 struct adv7842_state *state = to_state(sd); 2486 int err = 0; 2487 2488 memset(e->reserved, 0, sizeof(e->reserved)); 2489 2490 if (e->pad > ADV7842_EDID_PORT_VGA) 2491 return -EINVAL; 2492 if (e->start_block != 0) 2493 return -EINVAL; 2494 if (e->blocks > 2) { 2495 e->blocks = 2; 2496 return -E2BIG; 2497 } 2498 2499 /* todo, per edid */ 2500 state->aspect_ratio = v4l2_calc_aspect_ratio(e->edid[0x15], 2501 e->edid[0x16]); 2502 2503 switch (e->pad) { 2504 case ADV7842_EDID_PORT_VGA: 2505 memset(&state->vga_edid.edid, 0, 256); 2506 state->vga_edid.present = e->blocks ? 0x1 : 0x0; 2507 memcpy(&state->vga_edid.edid, e->edid, 128 * e->blocks); 2508 err = edid_write_vga_segment(sd); 2509 break; 2510 case ADV7842_EDID_PORT_A: 2511 case ADV7842_EDID_PORT_B: 2512 memset(&state->hdmi_edid.edid, 0, 256); 2513 if (e->blocks) { 2514 state->hdmi_edid.present |= 0x04 << e->pad; 2515 } else { 2516 state->hdmi_edid.present &= ~(0x04 << e->pad); 2517 adv7842_s_detect_tx_5v_ctrl(sd); 2518 } 2519 memcpy(&state->hdmi_edid.edid, e->edid, 128 * e->blocks); 2520 err = edid_write_hdmi_segment(sd, e->pad); 2521 break; 2522 default: 2523 return -EINVAL; 2524 } 2525 if (err < 0) 2526 v4l2_err(sd, "error %d writing edid on port %d\n", err, e->pad); 2527 return err; 2528 } 2529 2530 struct adv7842_cfg_read_infoframe { 2531 const char *desc; 2532 u8 present_mask; 2533 u8 head_addr; 2534 u8 payload_addr; 2535 }; 2536 2537 static void log_infoframe(struct v4l2_subdev *sd, const struct adv7842_cfg_read_infoframe *cri) 2538 { 2539 int i; 2540 u8 buffer[32]; 2541 union hdmi_infoframe frame; 2542 u8 len; 2543 struct i2c_client *client = v4l2_get_subdevdata(sd); 2544 struct device *dev = &client->dev; 2545 2546 if (!(io_read(sd, 0x60) & cri->present_mask)) { 2547 v4l2_info(sd, "%s infoframe not received\n", cri->desc); 2548 return; 2549 } 2550 2551 for (i = 0; i < 3; i++) 2552 buffer[i] = infoframe_read(sd, cri->head_addr + i); 2553 2554 len = buffer[2] + 1; 2555 2556 if (len + 3 > sizeof(buffer)) { 2557 v4l2_err(sd, "%s: invalid %s infoframe length %d\n", __func__, cri->desc, len); 2558 return; 2559 } 2560 2561 for (i = 0; i < len; i++) 2562 buffer[i + 3] = infoframe_read(sd, cri->payload_addr + i); 2563 2564 if (hdmi_infoframe_unpack(&frame, buffer, sizeof(buffer)) < 0) { 2565 v4l2_err(sd, "%s: unpack of %s infoframe failed\n", __func__, cri->desc); 2566 return; 2567 } 2568 2569 hdmi_infoframe_log(KERN_INFO, dev, &frame); 2570 } 2571 2572 static void adv7842_log_infoframes(struct v4l2_subdev *sd) 2573 { 2574 int i; 2575 static const struct adv7842_cfg_read_infoframe cri[] = { 2576 { "AVI", 0x01, 0xe0, 0x00 }, 2577 { "Audio", 0x02, 0xe3, 0x1c }, 2578 { "SDP", 0x04, 0xe6, 0x2a }, 2579 { "Vendor", 0x10, 0xec, 0x54 } 2580 }; 2581 2582 if (!(hdmi_read(sd, 0x05) & 0x80)) { 2583 v4l2_info(sd, "receive DVI-D signal, no infoframes\n"); 2584 return; 2585 } 2586 2587 for (i = 0; i < ARRAY_SIZE(cri); i++) 2588 log_infoframe(sd, &cri[i]); 2589 } 2590 2591 #if 0 2592 /* Let's keep it here for now, as it could be useful for debug */ 2593 static const char * const prim_mode_txt[] = { 2594 "SDP", 2595 "Component", 2596 "Graphics", 2597 "Reserved", 2598 "CVBS & HDMI AUDIO", 2599 "HDMI-Comp", 2600 "HDMI-GR", 2601 "Reserved", 2602 "Reserved", 2603 "Reserved", 2604 "Reserved", 2605 "Reserved", 2606 "Reserved", 2607 "Reserved", 2608 "Reserved", 2609 "Reserved", 2610 }; 2611 #endif 2612 2613 static int adv7842_sdp_log_status(struct v4l2_subdev *sd) 2614 { 2615 /* SDP (Standard definition processor) block */ 2616 u8 sdp_signal_detected = sdp_read(sd, 0x5A) & 0x01; 2617 2618 v4l2_info(sd, "Chip powered %s\n", no_power(sd) ? "off" : "on"); 2619 v4l2_info(sd, "Prim-mode = 0x%x, video std = 0x%x\n", 2620 io_read(sd, 0x01) & 0x0f, io_read(sd, 0x00) & 0x3f); 2621 2622 v4l2_info(sd, "SDP: free run: %s\n", 2623 (sdp_read(sd, 0x56) & 0x01) ? "on" : "off"); 2624 v4l2_info(sd, "SDP: %s\n", sdp_signal_detected ? 2625 "valid SD/PR signal detected" : "invalid/no signal"); 2626 if (sdp_signal_detected) { 2627 static const char * const sdp_std_txt[] = { 2628 "NTSC-M/J", 2629 "1?", 2630 "NTSC-443", 2631 "60HzSECAM", 2632 "PAL-M", 2633 "5?", 2634 "PAL-60", 2635 "7?", "8?", "9?", "a?", "b?", 2636 "PAL-CombN", 2637 "d?", 2638 "PAL-BGHID", 2639 "SECAM" 2640 }; 2641 v4l2_info(sd, "SDP: standard %s\n", 2642 sdp_std_txt[sdp_read(sd, 0x52) & 0x0f]); 2643 v4l2_info(sd, "SDP: %s\n", 2644 (sdp_read(sd, 0x59) & 0x08) ? "50Hz" : "60Hz"); 2645 v4l2_info(sd, "SDP: %s\n", 2646 (sdp_read(sd, 0x57) & 0x08) ? "Interlaced" : "Progressive"); 2647 v4l2_info(sd, "SDP: deinterlacer %s\n", 2648 (sdp_read(sd, 0x12) & 0x08) ? "enabled" : "disabled"); 2649 v4l2_info(sd, "SDP: csc %s mode\n", 2650 (sdp_io_read(sd, 0xe0) & 0x40) ? "auto" : "manual"); 2651 } 2652 return 0; 2653 } 2654 2655 static int adv7842_cp_log_status(struct v4l2_subdev *sd) 2656 { 2657 /* CP block */ 2658 struct adv7842_state *state = to_state(sd); 2659 struct v4l2_dv_timings timings; 2660 u8 reg_io_0x02 = io_read(sd, 0x02); 2661 u8 reg_io_0x21 = io_read(sd, 0x21); 2662 u8 reg_rep_0x77 = rep_read(sd, 0x77); 2663 u8 reg_rep_0x7d = rep_read(sd, 0x7d); 2664 bool audio_pll_locked = hdmi_read(sd, 0x04) & 0x01; 2665 bool audio_sample_packet_detect = hdmi_read(sd, 0x18) & 0x01; 2666 bool audio_mute = io_read(sd, 0x65) & 0x40; 2667 2668 static const char * const csc_coeff_sel_rb[16] = { 2669 "bypassed", "YPbPr601 -> RGB", "reserved", "YPbPr709 -> RGB", 2670 "reserved", "RGB -> YPbPr601", "reserved", "RGB -> YPbPr709", 2671 "reserved", "YPbPr709 -> YPbPr601", "YPbPr601 -> YPbPr709", 2672 "reserved", "reserved", "reserved", "reserved", "manual" 2673 }; 2674 static const char * const input_color_space_txt[16] = { 2675 "RGB limited range (16-235)", "RGB full range (0-255)", 2676 "YCbCr Bt.601 (16-235)", "YCbCr Bt.709 (16-235)", 2677 "xvYCC Bt.601", "xvYCC Bt.709", 2678 "YCbCr Bt.601 (0-255)", "YCbCr Bt.709 (0-255)", 2679 "invalid", "invalid", "invalid", "invalid", "invalid", 2680 "invalid", "invalid", "automatic" 2681 }; 2682 static const char * const rgb_quantization_range_txt[] = { 2683 "Automatic", 2684 "RGB limited range (16-235)", 2685 "RGB full range (0-255)", 2686 }; 2687 static const char * const deep_color_mode_txt[4] = { 2688 "8-bits per channel", 2689 "10-bits per channel", 2690 "12-bits per channel", 2691 "16-bits per channel (not supported)" 2692 }; 2693 2694 v4l2_info(sd, "-----Chip status-----\n"); 2695 v4l2_info(sd, "Chip power: %s\n", no_power(sd) ? "off" : "on"); 2696 v4l2_info(sd, "HDMI/DVI-D port selected: %s\n", 2697 state->hdmi_port_a ? "A" : "B"); 2698 v4l2_info(sd, "EDID A %s, B %s\n", 2699 ((reg_rep_0x7d & 0x04) && (reg_rep_0x77 & 0x04)) ? 2700 "enabled" : "disabled", 2701 ((reg_rep_0x7d & 0x08) && (reg_rep_0x77 & 0x08)) ? 2702 "enabled" : "disabled"); 2703 v4l2_info(sd, "HPD A %s, B %s\n", 2704 reg_io_0x21 & 0x02 ? "enabled" : "disabled", 2705 reg_io_0x21 & 0x01 ? "enabled" : "disabled"); 2706 v4l2_info(sd, "CEC: %s\n", state->cec_enabled_adap ? 2707 "enabled" : "disabled"); 2708 if (state->cec_enabled_adap) { 2709 int i; 2710 2711 for (i = 0; i < ADV7842_MAX_ADDRS; i++) { 2712 bool is_valid = state->cec_valid_addrs & (1 << i); 2713 2714 if (is_valid) 2715 v4l2_info(sd, "CEC Logical Address: 0x%x\n", 2716 state->cec_addr[i]); 2717 } 2718 } 2719 2720 v4l2_info(sd, "-----Signal status-----\n"); 2721 if (state->hdmi_port_a) { 2722 v4l2_info(sd, "Cable detected (+5V power): %s\n", 2723 io_read(sd, 0x6f) & 0x02 ? "true" : "false"); 2724 v4l2_info(sd, "TMDS signal detected: %s\n", 2725 (io_read(sd, 0x6a) & 0x02) ? "true" : "false"); 2726 v4l2_info(sd, "TMDS signal locked: %s\n", 2727 (io_read(sd, 0x6a) & 0x20) ? "true" : "false"); 2728 } else { 2729 v4l2_info(sd, "Cable detected (+5V power):%s\n", 2730 io_read(sd, 0x6f) & 0x01 ? "true" : "false"); 2731 v4l2_info(sd, "TMDS signal detected: %s\n", 2732 (io_read(sd, 0x6a) & 0x01) ? "true" : "false"); 2733 v4l2_info(sd, "TMDS signal locked: %s\n", 2734 (io_read(sd, 0x6a) & 0x10) ? "true" : "false"); 2735 } 2736 v4l2_info(sd, "CP free run: %s\n", 2737 (!!(cp_read(sd, 0xff) & 0x10) ? "on" : "off")); 2738 v4l2_info(sd, "Prim-mode = 0x%x, video std = 0x%x, v_freq = 0x%x\n", 2739 io_read(sd, 0x01) & 0x0f, io_read(sd, 0x00) & 0x3f, 2740 (io_read(sd, 0x01) & 0x70) >> 4); 2741 2742 v4l2_info(sd, "-----Video Timings-----\n"); 2743 if (no_cp_signal(sd)) { 2744 v4l2_info(sd, "STDI: not locked\n"); 2745 } else { 2746 u32 bl = ((cp_read(sd, 0xb1) & 0x3f) << 8) | cp_read(sd, 0xb2); 2747 u32 lcf = ((cp_read(sd, 0xb3) & 0x7) << 8) | cp_read(sd, 0xb4); 2748 u32 lcvs = cp_read(sd, 0xb3) >> 3; 2749 u32 fcl = ((cp_read(sd, 0xb8) & 0x1f) << 8) | cp_read(sd, 0xb9); 2750 char hs_pol = ((cp_read(sd, 0xb5) & 0x10) ? 2751 ((cp_read(sd, 0xb5) & 0x08) ? '+' : '-') : 'x'); 2752 char vs_pol = ((cp_read(sd, 0xb5) & 0x40) ? 2753 ((cp_read(sd, 0xb5) & 0x20) ? '+' : '-') : 'x'); 2754 v4l2_info(sd, 2755 "STDI: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, fcl = %d, %s, %chsync, %cvsync\n", 2756 lcf, bl, lcvs, fcl, 2757 (cp_read(sd, 0xb1) & 0x40) ? 2758 "interlaced" : "progressive", 2759 hs_pol, vs_pol); 2760 } 2761 if (adv7842_query_dv_timings(sd, &timings)) 2762 v4l2_info(sd, "No video detected\n"); 2763 else 2764 v4l2_print_dv_timings(sd->name, "Detected format: ", 2765 &timings, true); 2766 v4l2_print_dv_timings(sd->name, "Configured format: ", 2767 &state->timings, true); 2768 2769 if (no_cp_signal(sd)) 2770 return 0; 2771 2772 v4l2_info(sd, "-----Color space-----\n"); 2773 v4l2_info(sd, "RGB quantization range ctrl: %s\n", 2774 rgb_quantization_range_txt[state->rgb_quantization_range]); 2775 v4l2_info(sd, "Input color space: %s\n", 2776 input_color_space_txt[reg_io_0x02 >> 4]); 2777 v4l2_info(sd, "Output color space: %s %s, alt-gamma %s\n", 2778 (reg_io_0x02 & 0x02) ? "RGB" : "YCbCr", 2779 (((reg_io_0x02 >> 2) & 0x01) ^ (reg_io_0x02 & 0x01)) ? 2780 "(16-235)" : "(0-255)", 2781 (reg_io_0x02 & 0x08) ? "enabled" : "disabled"); 2782 v4l2_info(sd, "Color space conversion: %s\n", 2783 csc_coeff_sel_rb[cp_read(sd, 0xf4) >> 4]); 2784 2785 if (!is_digital_input(sd)) 2786 return 0; 2787 2788 v4l2_info(sd, "-----%s status-----\n", is_hdmi(sd) ? "HDMI" : "DVI-D"); 2789 v4l2_info(sd, "HDCP encrypted content: %s\n", 2790 (hdmi_read(sd, 0x05) & 0x40) ? "true" : "false"); 2791 v4l2_info(sd, "HDCP keys read: %s%s\n", 2792 (hdmi_read(sd, 0x04) & 0x20) ? "yes" : "no", 2793 (hdmi_read(sd, 0x04) & 0x10) ? "ERROR" : ""); 2794 if (!is_hdmi(sd)) 2795 return 0; 2796 2797 v4l2_info(sd, "Audio: pll %s, samples %s, %s\n", 2798 audio_pll_locked ? "locked" : "not locked", 2799 audio_sample_packet_detect ? "detected" : "not detected", 2800 audio_mute ? "muted" : "enabled"); 2801 if (audio_pll_locked && audio_sample_packet_detect) { 2802 v4l2_info(sd, "Audio format: %s\n", 2803 (hdmi_read(sd, 0x07) & 0x40) ? "multi-channel" : "stereo"); 2804 } 2805 v4l2_info(sd, "Audio CTS: %u\n", (hdmi_read(sd, 0x5b) << 12) + 2806 (hdmi_read(sd, 0x5c) << 8) + 2807 (hdmi_read(sd, 0x5d) & 0xf0)); 2808 v4l2_info(sd, "Audio N: %u\n", ((hdmi_read(sd, 0x5d) & 0x0f) << 16) + 2809 (hdmi_read(sd, 0x5e) << 8) + 2810 hdmi_read(sd, 0x5f)); 2811 v4l2_info(sd, "AV Mute: %s\n", 2812 (hdmi_read(sd, 0x04) & 0x40) ? "on" : "off"); 2813 v4l2_info(sd, "Deep color mode: %s\n", 2814 deep_color_mode_txt[hdmi_read(sd, 0x0b) >> 6]); 2815 2816 adv7842_log_infoframes(sd); 2817 2818 return 0; 2819 } 2820 2821 static int adv7842_log_status(struct v4l2_subdev *sd) 2822 { 2823 struct adv7842_state *state = to_state(sd); 2824 2825 if (state->mode == ADV7842_MODE_SDP) 2826 return adv7842_sdp_log_status(sd); 2827 return adv7842_cp_log_status(sd); 2828 } 2829 2830 static int adv7842_querystd(struct v4l2_subdev *sd, v4l2_std_id *std) 2831 { 2832 struct adv7842_state *state = to_state(sd); 2833 2834 v4l2_dbg(1, debug, sd, "%s:\n", __func__); 2835 2836 if (state->mode != ADV7842_MODE_SDP) 2837 return -ENODATA; 2838 2839 if (!(sdp_read(sd, 0x5A) & 0x01)) { 2840 *std = 0; 2841 v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__); 2842 return 0; 2843 } 2844 2845 switch (sdp_read(sd, 0x52) & 0x0f) { 2846 case 0: 2847 /* NTSC-M/J */ 2848 *std &= V4L2_STD_NTSC; 2849 break; 2850 case 2: 2851 /* NTSC-443 */ 2852 *std &= V4L2_STD_NTSC_443; 2853 break; 2854 case 3: 2855 /* 60HzSECAM */ 2856 *std &= V4L2_STD_SECAM; 2857 break; 2858 case 4: 2859 /* PAL-M */ 2860 *std &= V4L2_STD_PAL_M; 2861 break; 2862 case 6: 2863 /* PAL-60 */ 2864 *std &= V4L2_STD_PAL_60; 2865 break; 2866 case 0xc: 2867 /* PAL-CombN */ 2868 *std &= V4L2_STD_PAL_Nc; 2869 break; 2870 case 0xe: 2871 /* PAL-BGHID */ 2872 *std &= V4L2_STD_PAL; 2873 break; 2874 case 0xf: 2875 /* SECAM */ 2876 *std &= V4L2_STD_SECAM; 2877 break; 2878 default: 2879 *std &= V4L2_STD_ALL; 2880 break; 2881 } 2882 return 0; 2883 } 2884 2885 static void adv7842_s_sdp_io(struct v4l2_subdev *sd, struct adv7842_sdp_io_sync_adjustment *s) 2886 { 2887 if (s && s->adjust) { 2888 sdp_io_write(sd, 0x94, (s->hs_beg >> 8) & 0xf); 2889 sdp_io_write(sd, 0x95, s->hs_beg & 0xff); 2890 sdp_io_write(sd, 0x96, (s->hs_width >> 8) & 0xf); 2891 sdp_io_write(sd, 0x97, s->hs_width & 0xff); 2892 sdp_io_write(sd, 0x98, (s->de_beg >> 8) & 0xf); 2893 sdp_io_write(sd, 0x99, s->de_beg & 0xff); 2894 sdp_io_write(sd, 0x9a, (s->de_end >> 8) & 0xf); 2895 sdp_io_write(sd, 0x9b, s->de_end & 0xff); 2896 sdp_io_write(sd, 0xa8, s->vs_beg_o); 2897 sdp_io_write(sd, 0xa9, s->vs_beg_e); 2898 sdp_io_write(sd, 0xaa, s->vs_end_o); 2899 sdp_io_write(sd, 0xab, s->vs_end_e); 2900 sdp_io_write(sd, 0xac, s->de_v_beg_o); 2901 sdp_io_write(sd, 0xad, s->de_v_beg_e); 2902 sdp_io_write(sd, 0xae, s->de_v_end_o); 2903 sdp_io_write(sd, 0xaf, s->de_v_end_e); 2904 } else { 2905 /* set to default */ 2906 sdp_io_write(sd, 0x94, 0x00); 2907 sdp_io_write(sd, 0x95, 0x00); 2908 sdp_io_write(sd, 0x96, 0x00); 2909 sdp_io_write(sd, 0x97, 0x20); 2910 sdp_io_write(sd, 0x98, 0x00); 2911 sdp_io_write(sd, 0x99, 0x00); 2912 sdp_io_write(sd, 0x9a, 0x00); 2913 sdp_io_write(sd, 0x9b, 0x00); 2914 sdp_io_write(sd, 0xa8, 0x04); 2915 sdp_io_write(sd, 0xa9, 0x04); 2916 sdp_io_write(sd, 0xaa, 0x04); 2917 sdp_io_write(sd, 0xab, 0x04); 2918 sdp_io_write(sd, 0xac, 0x04); 2919 sdp_io_write(sd, 0xad, 0x04); 2920 sdp_io_write(sd, 0xae, 0x04); 2921 sdp_io_write(sd, 0xaf, 0x04); 2922 } 2923 } 2924 2925 static int adv7842_s_std(struct v4l2_subdev *sd, v4l2_std_id norm) 2926 { 2927 struct adv7842_state *state = to_state(sd); 2928 struct adv7842_platform_data *pdata = &state->pdata; 2929 2930 v4l2_dbg(1, debug, sd, "%s:\n", __func__); 2931 2932 if (state->mode != ADV7842_MODE_SDP) 2933 return -ENODATA; 2934 2935 if (norm & V4L2_STD_625_50) 2936 adv7842_s_sdp_io(sd, &pdata->sdp_io_sync_625); 2937 else if (norm & V4L2_STD_525_60) 2938 adv7842_s_sdp_io(sd, &pdata->sdp_io_sync_525); 2939 else 2940 adv7842_s_sdp_io(sd, NULL); 2941 2942 if (norm & V4L2_STD_ALL) { 2943 state->norm = norm; 2944 return 0; 2945 } 2946 return -EINVAL; 2947 } 2948 2949 static int adv7842_g_std(struct v4l2_subdev *sd, v4l2_std_id *norm) 2950 { 2951 struct adv7842_state *state = to_state(sd); 2952 2953 v4l2_dbg(1, debug, sd, "%s:\n", __func__); 2954 2955 if (state->mode != ADV7842_MODE_SDP) 2956 return -ENODATA; 2957 2958 *norm = state->norm; 2959 return 0; 2960 } 2961 2962 /* ----------------------------------------------------------------------- */ 2963 2964 static int adv7842_core_init(struct v4l2_subdev *sd) 2965 { 2966 struct adv7842_state *state = to_state(sd); 2967 struct adv7842_platform_data *pdata = &state->pdata; 2968 hdmi_write(sd, 0x48, 2969 (pdata->disable_pwrdnb ? 0x80 : 0) | 2970 (pdata->disable_cable_det_rst ? 0x40 : 0)); 2971 2972 disable_input(sd); 2973 2974 /* 2975 * Disable I2C access to internal EDID ram from HDMI DDC ports 2976 * Disable auto edid enable when leaving powerdown mode 2977 */ 2978 rep_write_and_or(sd, 0x77, 0xd3, 0x20); 2979 2980 /* power */ 2981 io_write(sd, 0x0c, 0x42); /* Power up part and power down VDP */ 2982 io_write(sd, 0x15, 0x80); /* Power up pads */ 2983 2984 /* video format */ 2985 io_write(sd, 0x02, 0xf0 | pdata->alt_gamma << 3); 2986 io_write_and_or(sd, 0x05, 0xf0, pdata->blank_data << 3 | 2987 pdata->insert_av_codes << 2 | 2988 pdata->replicate_av_codes << 1); 2989 adv7842_setup_format(state); 2990 2991 /* HDMI audio */ 2992 hdmi_write_and_or(sd, 0x1a, 0xf1, 0x08); /* Wait 1 s before unmute */ 2993 2994 /* Drive strength */ 2995 io_write_and_or(sd, 0x14, 0xc0, 2996 pdata->dr_str_data << 4 | 2997 pdata->dr_str_clk << 2 | 2998 pdata->dr_str_sync); 2999 3000 /* HDMI free run */ 3001 cp_write_and_or(sd, 0xba, 0xfc, pdata->hdmi_free_run_enable | 3002 (pdata->hdmi_free_run_mode << 1)); 3003 3004 /* SPD free run */ 3005 sdp_write_and_or(sd, 0xdd, 0xf0, pdata->sdp_free_run_force | 3006 (pdata->sdp_free_run_cbar_en << 1) | 3007 (pdata->sdp_free_run_man_col_en << 2) | 3008 (pdata->sdp_free_run_auto << 3)); 3009 3010 /* TODO from platform data */ 3011 cp_write(sd, 0x69, 0x14); /* Enable CP CSC */ 3012 io_write(sd, 0x06, 0xa6); /* positive VS and HS and DE */ 3013 cp_write(sd, 0xf3, 0xdc); /* Low threshold to enter/exit free run mode */ 3014 afe_write(sd, 0xb5, 0x01); /* Setting MCLK to 256Fs */ 3015 3016 afe_write(sd, 0x02, pdata->ain_sel); /* Select analog input muxing mode */ 3017 io_write_and_or(sd, 0x30, ~(1 << 4), pdata->output_bus_lsb_to_msb << 4); 3018 3019 sdp_csc_coeff(sd, &pdata->sdp_csc_coeff); 3020 3021 /* todo, improve settings for sdram */ 3022 if (pdata->sd_ram_size >= 128) { 3023 sdp_write(sd, 0x12, 0x0d); /* Frame TBC,3D comb enabled */ 3024 if (pdata->sd_ram_ddr) { 3025 /* SDP setup for the AD eval board */ 3026 sdp_io_write(sd, 0x6f, 0x00); /* DDR mode */ 3027 sdp_io_write(sd, 0x75, 0x0a); /* 128 MB memory size */ 3028 sdp_io_write(sd, 0x7a, 0xa5); /* Timing Adjustment */ 3029 sdp_io_write(sd, 0x7b, 0x8f); /* Timing Adjustment */ 3030 sdp_io_write(sd, 0x60, 0x01); /* SDRAM reset */ 3031 } else { 3032 sdp_io_write(sd, 0x75, 0x0a); /* 64 MB memory size ?*/ 3033 sdp_io_write(sd, 0x74, 0x00); /* must be zero for sdr sdram */ 3034 sdp_io_write(sd, 0x79, 0x33); /* CAS latency to 3, 3035 depends on memory */ 3036 sdp_io_write(sd, 0x6f, 0x01); /* SDR mode */ 3037 sdp_io_write(sd, 0x7a, 0xa5); /* Timing Adjustment */ 3038 sdp_io_write(sd, 0x7b, 0x8f); /* Timing Adjustment */ 3039 sdp_io_write(sd, 0x60, 0x01); /* SDRAM reset */ 3040 } 3041 } else { 3042 /* 3043 * Manual UG-214, rev 0 is bit confusing on this bit 3044 * but a '1' disables any signal if the Ram is active. 3045 */ 3046 sdp_io_write(sd, 0x29, 0x10); /* Tristate memory interface */ 3047 } 3048 3049 select_input(sd, pdata->vid_std_select); 3050 3051 enable_input(sd); 3052 3053 if (pdata->hpa_auto) { 3054 /* HPA auto, HPA 0.5s after Edid set and Cable detect */ 3055 hdmi_write(sd, 0x69, 0x5c); 3056 } else { 3057 /* HPA manual */ 3058 hdmi_write(sd, 0x69, 0xa3); 3059 /* HPA disable on port A and B */ 3060 io_write_and_or(sd, 0x20, 0xcf, 0x00); 3061 } 3062 3063 /* LLC */ 3064 io_write(sd, 0x19, 0x80 | pdata->llc_dll_phase); 3065 io_write(sd, 0x33, 0x40); 3066 3067 /* interrupts */ 3068 io_write(sd, 0x40, 0xf2); /* Configure INT1 */ 3069 3070 adv7842_irq_enable(sd, true); 3071 3072 return v4l2_ctrl_handler_setup(sd->ctrl_handler); 3073 } 3074 3075 /* ----------------------------------------------------------------------- */ 3076 3077 static int adv7842_ddr_ram_test(struct v4l2_subdev *sd) 3078 { 3079 /* 3080 * From ADV784x external Memory test.pdf 3081 * 3082 * Reset must just been performed before running test. 3083 * Recommended to reset after test. 3084 */ 3085 int i; 3086 int pass = 0; 3087 int fail = 0; 3088 int complete = 0; 3089 3090 io_write(sd, 0x00, 0x01); /* Program SDP 4x1 */ 3091 io_write(sd, 0x01, 0x00); /* Program SDP mode */ 3092 afe_write(sd, 0x80, 0x92); /* SDP Recommended Write */ 3093 afe_write(sd, 0x9B, 0x01); /* SDP Recommended Write ADV7844ES1 */ 3094 afe_write(sd, 0x9C, 0x60); /* SDP Recommended Write ADV7844ES1 */ 3095 afe_write(sd, 0x9E, 0x02); /* SDP Recommended Write ADV7844ES1 */ 3096 afe_write(sd, 0xA0, 0x0B); /* SDP Recommended Write ADV7844ES1 */ 3097 afe_write(sd, 0xC3, 0x02); /* Memory BIST Initialisation */ 3098 io_write(sd, 0x0C, 0x40); /* Power up ADV7844 */ 3099 io_write(sd, 0x15, 0xBA); /* Enable outputs */ 3100 sdp_write(sd, 0x12, 0x00); /* Disable 3D comb, Frame TBC & 3DNR */ 3101 io_write(sd, 0xFF, 0x04); /* Reset memory controller */ 3102 3103 usleep_range(5000, 6000); 3104 3105 sdp_write(sd, 0x12, 0x00); /* Disable 3D Comb, Frame TBC & 3DNR */ 3106 sdp_io_write(sd, 0x2A, 0x01); /* Memory BIST Initialisation */ 3107 sdp_io_write(sd, 0x7c, 0x19); /* Memory BIST Initialisation */ 3108 sdp_io_write(sd, 0x80, 0x87); /* Memory BIST Initialisation */ 3109 sdp_io_write(sd, 0x81, 0x4a); /* Memory BIST Initialisation */ 3110 sdp_io_write(sd, 0x82, 0x2c); /* Memory BIST Initialisation */ 3111 sdp_io_write(sd, 0x83, 0x0e); /* Memory BIST Initialisation */ 3112 sdp_io_write(sd, 0x84, 0x94); /* Memory BIST Initialisation */ 3113 sdp_io_write(sd, 0x85, 0x62); /* Memory BIST Initialisation */ 3114 sdp_io_write(sd, 0x7d, 0x00); /* Memory BIST Initialisation */ 3115 sdp_io_write(sd, 0x7e, 0x1a); /* Memory BIST Initialisation */ 3116 3117 usleep_range(5000, 6000); 3118 3119 sdp_io_write(sd, 0xd9, 0xd5); /* Enable BIST Test */ 3120 sdp_write(sd, 0x12, 0x05); /* Enable FRAME TBC & 3D COMB */ 3121 3122 msleep(20); 3123 3124 for (i = 0; i < 10; i++) { 3125 u8 result = sdp_io_read(sd, 0xdb); 3126 if (result & 0x10) { 3127 complete++; 3128 if (result & 0x20) 3129 fail++; 3130 else 3131 pass++; 3132 } 3133 msleep(20); 3134 } 3135 3136 v4l2_dbg(1, debug, sd, 3137 "Ram Test: completed %d of %d: pass %d, fail %d\n", 3138 complete, i, pass, fail); 3139 3140 if (!complete || fail) 3141 return -EIO; 3142 return 0; 3143 } 3144 3145 static void adv7842_rewrite_i2c_addresses(struct v4l2_subdev *sd, 3146 struct adv7842_platform_data *pdata) 3147 { 3148 io_write(sd, 0xf1, pdata->i2c_sdp << 1); 3149 io_write(sd, 0xf2, pdata->i2c_sdp_io << 1); 3150 io_write(sd, 0xf3, pdata->i2c_avlink << 1); 3151 io_write(sd, 0xf4, pdata->i2c_cec << 1); 3152 io_write(sd, 0xf5, pdata->i2c_infoframe << 1); 3153 3154 io_write(sd, 0xf8, pdata->i2c_afe << 1); 3155 io_write(sd, 0xf9, pdata->i2c_repeater << 1); 3156 io_write(sd, 0xfa, pdata->i2c_edid << 1); 3157 io_write(sd, 0xfb, pdata->i2c_hdmi << 1); 3158 3159 io_write(sd, 0xfd, pdata->i2c_cp << 1); 3160 io_write(sd, 0xfe, pdata->i2c_vdp << 1); 3161 } 3162 3163 static int adv7842_command_ram_test(struct v4l2_subdev *sd) 3164 { 3165 struct i2c_client *client = v4l2_get_subdevdata(sd); 3166 struct adv7842_state *state = to_state(sd); 3167 struct adv7842_platform_data *pdata = client->dev.platform_data; 3168 struct v4l2_dv_timings timings; 3169 int ret = 0; 3170 3171 if (!pdata) 3172 return -ENODEV; 3173 3174 if (!pdata->sd_ram_size || !pdata->sd_ram_ddr) { 3175 v4l2_info(sd, "no sdram or no ddr sdram\n"); 3176 return -EINVAL; 3177 } 3178 3179 main_reset(sd); 3180 3181 adv7842_rewrite_i2c_addresses(sd, pdata); 3182 3183 /* run ram test */ 3184 ret = adv7842_ddr_ram_test(sd); 3185 3186 main_reset(sd); 3187 3188 adv7842_rewrite_i2c_addresses(sd, pdata); 3189 3190 /* and re-init chip and state */ 3191 adv7842_core_init(sd); 3192 3193 disable_input(sd); 3194 3195 select_input(sd, state->vid_std_select); 3196 3197 enable_input(sd); 3198 3199 edid_write_vga_segment(sd); 3200 edid_write_hdmi_segment(sd, ADV7842_EDID_PORT_A); 3201 edid_write_hdmi_segment(sd, ADV7842_EDID_PORT_B); 3202 3203 timings = state->timings; 3204 3205 memset(&state->timings, 0, sizeof(struct v4l2_dv_timings)); 3206 3207 adv7842_s_dv_timings(sd, &timings); 3208 3209 return ret; 3210 } 3211 3212 static long adv7842_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg) 3213 { 3214 switch (cmd) { 3215 case ADV7842_CMD_RAM_TEST: 3216 return adv7842_command_ram_test(sd); 3217 } 3218 return -ENOTTY; 3219 } 3220 3221 static int adv7842_subscribe_event(struct v4l2_subdev *sd, 3222 struct v4l2_fh *fh, 3223 struct v4l2_event_subscription *sub) 3224 { 3225 switch (sub->type) { 3226 case V4L2_EVENT_SOURCE_CHANGE: 3227 return v4l2_src_change_event_subdev_subscribe(sd, fh, sub); 3228 case V4L2_EVENT_CTRL: 3229 return v4l2_ctrl_subdev_subscribe_event(sd, fh, sub); 3230 default: 3231 return -EINVAL; 3232 } 3233 } 3234 3235 static int adv7842_registered(struct v4l2_subdev *sd) 3236 { 3237 struct adv7842_state *state = to_state(sd); 3238 struct i2c_client *client = v4l2_get_subdevdata(sd); 3239 int err; 3240 3241 err = cec_register_adapter(state->cec_adap, &client->dev); 3242 if (err) 3243 cec_delete_adapter(state->cec_adap); 3244 return err; 3245 } 3246 3247 static void adv7842_unregistered(struct v4l2_subdev *sd) 3248 { 3249 struct adv7842_state *state = to_state(sd); 3250 3251 cec_unregister_adapter(state->cec_adap); 3252 } 3253 3254 /* ----------------------------------------------------------------------- */ 3255 3256 static const struct v4l2_ctrl_ops adv7842_ctrl_ops = { 3257 .s_ctrl = adv7842_s_ctrl, 3258 .g_volatile_ctrl = adv7842_g_volatile_ctrl, 3259 }; 3260 3261 static const struct v4l2_subdev_core_ops adv7842_core_ops = { 3262 .log_status = adv7842_log_status, 3263 .ioctl = adv7842_ioctl, 3264 .interrupt_service_routine = adv7842_isr, 3265 .subscribe_event = adv7842_subscribe_event, 3266 .unsubscribe_event = v4l2_event_subdev_unsubscribe, 3267 #ifdef CONFIG_VIDEO_ADV_DEBUG 3268 .g_register = adv7842_g_register, 3269 .s_register = adv7842_s_register, 3270 #endif 3271 }; 3272 3273 static const struct v4l2_subdev_video_ops adv7842_video_ops = { 3274 .g_std = adv7842_g_std, 3275 .s_std = adv7842_s_std, 3276 .s_routing = adv7842_s_routing, 3277 .querystd = adv7842_querystd, 3278 .g_input_status = adv7842_g_input_status, 3279 .s_dv_timings = adv7842_s_dv_timings, 3280 .g_dv_timings = adv7842_g_dv_timings, 3281 .query_dv_timings = adv7842_query_dv_timings, 3282 }; 3283 3284 static const struct v4l2_subdev_pad_ops adv7842_pad_ops = { 3285 .enum_mbus_code = adv7842_enum_mbus_code, 3286 .get_fmt = adv7842_get_format, 3287 .set_fmt = adv7842_set_format, 3288 .get_edid = adv7842_get_edid, 3289 .set_edid = adv7842_set_edid, 3290 .enum_dv_timings = adv7842_enum_dv_timings, 3291 .dv_timings_cap = adv7842_dv_timings_cap, 3292 }; 3293 3294 static const struct v4l2_subdev_ops adv7842_ops = { 3295 .core = &adv7842_core_ops, 3296 .video = &adv7842_video_ops, 3297 .pad = &adv7842_pad_ops, 3298 }; 3299 3300 static const struct v4l2_subdev_internal_ops adv7842_int_ops = { 3301 .registered = adv7842_registered, 3302 .unregistered = adv7842_unregistered, 3303 }; 3304 3305 /* -------------------------- custom ctrls ---------------------------------- */ 3306 3307 static const struct v4l2_ctrl_config adv7842_ctrl_analog_sampling_phase = { 3308 .ops = &adv7842_ctrl_ops, 3309 .id = V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE, 3310 .name = "Analog Sampling Phase", 3311 .type = V4L2_CTRL_TYPE_INTEGER, 3312 .min = 0, 3313 .max = 0x1f, 3314 .step = 1, 3315 .def = 0, 3316 }; 3317 3318 static const struct v4l2_ctrl_config adv7842_ctrl_free_run_color_manual = { 3319 .ops = &adv7842_ctrl_ops, 3320 .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL, 3321 .name = "Free Running Color, Manual", 3322 .type = V4L2_CTRL_TYPE_BOOLEAN, 3323 .max = 1, 3324 .step = 1, 3325 .def = 1, 3326 }; 3327 3328 static const struct v4l2_ctrl_config adv7842_ctrl_free_run_color = { 3329 .ops = &adv7842_ctrl_ops, 3330 .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR, 3331 .name = "Free Running Color", 3332 .type = V4L2_CTRL_TYPE_INTEGER, 3333 .max = 0xffffff, 3334 .step = 0x1, 3335 }; 3336 3337 3338 static void adv7842_unregister_clients(struct v4l2_subdev *sd) 3339 { 3340 struct adv7842_state *state = to_state(sd); 3341 i2c_unregister_device(state->i2c_avlink); 3342 i2c_unregister_device(state->i2c_cec); 3343 i2c_unregister_device(state->i2c_infoframe); 3344 i2c_unregister_device(state->i2c_sdp_io); 3345 i2c_unregister_device(state->i2c_sdp); 3346 i2c_unregister_device(state->i2c_afe); 3347 i2c_unregister_device(state->i2c_repeater); 3348 i2c_unregister_device(state->i2c_edid); 3349 i2c_unregister_device(state->i2c_hdmi); 3350 i2c_unregister_device(state->i2c_cp); 3351 i2c_unregister_device(state->i2c_vdp); 3352 3353 state->i2c_avlink = NULL; 3354 state->i2c_cec = NULL; 3355 state->i2c_infoframe = NULL; 3356 state->i2c_sdp_io = NULL; 3357 state->i2c_sdp = NULL; 3358 state->i2c_afe = NULL; 3359 state->i2c_repeater = NULL; 3360 state->i2c_edid = NULL; 3361 state->i2c_hdmi = NULL; 3362 state->i2c_cp = NULL; 3363 state->i2c_vdp = NULL; 3364 } 3365 3366 static struct i2c_client *adv7842_dummy_client(struct v4l2_subdev *sd, const char *desc, 3367 u8 addr, u8 io_reg) 3368 { 3369 struct i2c_client *client = v4l2_get_subdevdata(sd); 3370 struct i2c_client *cp; 3371 3372 io_write(sd, io_reg, addr << 1); 3373 3374 if (addr == 0) { 3375 v4l2_err(sd, "no %s i2c addr configured\n", desc); 3376 return NULL; 3377 } 3378 3379 cp = i2c_new_dummy_device(client->adapter, io_read(sd, io_reg) >> 1); 3380 if (IS_ERR(cp)) { 3381 v4l2_err(sd, "register %s on i2c addr 0x%x failed with %ld\n", 3382 desc, addr, PTR_ERR(cp)); 3383 cp = NULL; 3384 } 3385 3386 return cp; 3387 } 3388 3389 static int adv7842_register_clients(struct v4l2_subdev *sd) 3390 { 3391 struct adv7842_state *state = to_state(sd); 3392 struct adv7842_platform_data *pdata = &state->pdata; 3393 3394 state->i2c_avlink = adv7842_dummy_client(sd, "avlink", pdata->i2c_avlink, 0xf3); 3395 state->i2c_cec = adv7842_dummy_client(sd, "cec", pdata->i2c_cec, 0xf4); 3396 state->i2c_infoframe = adv7842_dummy_client(sd, "infoframe", pdata->i2c_infoframe, 0xf5); 3397 state->i2c_sdp_io = adv7842_dummy_client(sd, "sdp_io", pdata->i2c_sdp_io, 0xf2); 3398 state->i2c_sdp = adv7842_dummy_client(sd, "sdp", pdata->i2c_sdp, 0xf1); 3399 state->i2c_afe = adv7842_dummy_client(sd, "afe", pdata->i2c_afe, 0xf8); 3400 state->i2c_repeater = adv7842_dummy_client(sd, "repeater", pdata->i2c_repeater, 0xf9); 3401 state->i2c_edid = adv7842_dummy_client(sd, "edid", pdata->i2c_edid, 0xfa); 3402 state->i2c_hdmi = adv7842_dummy_client(sd, "hdmi", pdata->i2c_hdmi, 0xfb); 3403 state->i2c_cp = adv7842_dummy_client(sd, "cp", pdata->i2c_cp, 0xfd); 3404 state->i2c_vdp = adv7842_dummy_client(sd, "vdp", pdata->i2c_vdp, 0xfe); 3405 3406 if (!state->i2c_avlink || 3407 !state->i2c_cec || 3408 !state->i2c_infoframe || 3409 !state->i2c_sdp_io || 3410 !state->i2c_sdp || 3411 !state->i2c_afe || 3412 !state->i2c_repeater || 3413 !state->i2c_edid || 3414 !state->i2c_hdmi || 3415 !state->i2c_cp || 3416 !state->i2c_vdp) 3417 return -1; 3418 3419 return 0; 3420 } 3421 3422 static int adv7842_probe(struct i2c_client *client, 3423 const struct i2c_device_id *id) 3424 { 3425 struct adv7842_state *state; 3426 static const struct v4l2_dv_timings cea640x480 = 3427 V4L2_DV_BT_CEA_640X480P59_94; 3428 struct adv7842_platform_data *pdata = client->dev.platform_data; 3429 struct v4l2_ctrl_handler *hdl; 3430 struct v4l2_ctrl *ctrl; 3431 struct v4l2_subdev *sd; 3432 u16 rev; 3433 int err; 3434 3435 /* Check if the adapter supports the needed features */ 3436 if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA)) 3437 return -EIO; 3438 3439 v4l_dbg(1, debug, client, "detecting adv7842 client on address 0x%x\n", 3440 client->addr << 1); 3441 3442 if (!pdata) { 3443 v4l_err(client, "No platform data!\n"); 3444 return -ENODEV; 3445 } 3446 3447 state = devm_kzalloc(&client->dev, sizeof(*state), GFP_KERNEL); 3448 if (!state) 3449 return -ENOMEM; 3450 3451 /* platform data */ 3452 state->pdata = *pdata; 3453 state->timings = cea640x480; 3454 state->format = adv7842_format_info(state, MEDIA_BUS_FMT_YUYV8_2X8); 3455 3456 sd = &state->sd; 3457 v4l2_i2c_subdev_init(sd, client, &adv7842_ops); 3458 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS; 3459 sd->internal_ops = &adv7842_int_ops; 3460 state->mode = pdata->mode; 3461 3462 state->hdmi_port_a = pdata->input == ADV7842_SELECT_HDMI_PORT_A; 3463 state->restart_stdi_once = true; 3464 3465 /* i2c access to adv7842? */ 3466 rev = adv_smbus_read_byte_data_check(client, 0xea, false) << 8 | 3467 adv_smbus_read_byte_data_check(client, 0xeb, false); 3468 if (rev != 0x2012) { 3469 v4l2_info(sd, "got rev=0x%04x on first read attempt\n", rev); 3470 rev = adv_smbus_read_byte_data_check(client, 0xea, false) << 8 | 3471 adv_smbus_read_byte_data_check(client, 0xeb, false); 3472 } 3473 if (rev != 0x2012) { 3474 v4l2_info(sd, "not an adv7842 on address 0x%x (rev=0x%04x)\n", 3475 client->addr << 1, rev); 3476 return -ENODEV; 3477 } 3478 3479 if (pdata->chip_reset) 3480 main_reset(sd); 3481 3482 /* control handlers */ 3483 hdl = &state->hdl; 3484 v4l2_ctrl_handler_init(hdl, 6); 3485 3486 /* add in ascending ID order */ 3487 v4l2_ctrl_new_std(hdl, &adv7842_ctrl_ops, 3488 V4L2_CID_BRIGHTNESS, -128, 127, 1, 0); 3489 v4l2_ctrl_new_std(hdl, &adv7842_ctrl_ops, 3490 V4L2_CID_CONTRAST, 0, 255, 1, 128); 3491 v4l2_ctrl_new_std(hdl, &adv7842_ctrl_ops, 3492 V4L2_CID_SATURATION, 0, 255, 1, 128); 3493 v4l2_ctrl_new_std(hdl, &adv7842_ctrl_ops, 3494 V4L2_CID_HUE, 0, 128, 1, 0); 3495 ctrl = v4l2_ctrl_new_std_menu(hdl, &adv7842_ctrl_ops, 3496 V4L2_CID_DV_RX_IT_CONTENT_TYPE, V4L2_DV_IT_CONTENT_TYPE_NO_ITC, 3497 0, V4L2_DV_IT_CONTENT_TYPE_NO_ITC); 3498 if (ctrl) 3499 ctrl->flags |= V4L2_CTRL_FLAG_VOLATILE; 3500 3501 /* custom controls */ 3502 state->detect_tx_5v_ctrl = v4l2_ctrl_new_std(hdl, NULL, 3503 V4L2_CID_DV_RX_POWER_PRESENT, 0, 3, 0, 0); 3504 state->analog_sampling_phase_ctrl = v4l2_ctrl_new_custom(hdl, 3505 &adv7842_ctrl_analog_sampling_phase, NULL); 3506 state->free_run_color_ctrl_manual = v4l2_ctrl_new_custom(hdl, 3507 &adv7842_ctrl_free_run_color_manual, NULL); 3508 state->free_run_color_ctrl = v4l2_ctrl_new_custom(hdl, 3509 &adv7842_ctrl_free_run_color, NULL); 3510 state->rgb_quantization_range_ctrl = 3511 v4l2_ctrl_new_std_menu(hdl, &adv7842_ctrl_ops, 3512 V4L2_CID_DV_RX_RGB_RANGE, V4L2_DV_RGB_RANGE_FULL, 3513 0, V4L2_DV_RGB_RANGE_AUTO); 3514 sd->ctrl_handler = hdl; 3515 if (hdl->error) { 3516 err = hdl->error; 3517 goto err_hdl; 3518 } 3519 if (adv7842_s_detect_tx_5v_ctrl(sd)) { 3520 err = -ENODEV; 3521 goto err_hdl; 3522 } 3523 3524 if (adv7842_register_clients(sd) < 0) { 3525 err = -ENOMEM; 3526 v4l2_err(sd, "failed to create all i2c clients\n"); 3527 goto err_i2c; 3528 } 3529 3530 3531 INIT_DELAYED_WORK(&state->delayed_work_enable_hotplug, 3532 adv7842_delayed_work_enable_hotplug); 3533 3534 sd->entity.function = MEDIA_ENT_F_DV_DECODER; 3535 state->pad.flags = MEDIA_PAD_FL_SOURCE; 3536 err = media_entity_pads_init(&sd->entity, 1, &state->pad); 3537 if (err) 3538 goto err_work_queues; 3539 3540 err = adv7842_core_init(sd); 3541 if (err) 3542 goto err_entity; 3543 3544 #if IS_ENABLED(CONFIG_VIDEO_ADV7842_CEC) 3545 state->cec_adap = cec_allocate_adapter(&adv7842_cec_adap_ops, 3546 state, dev_name(&client->dev), 3547 CEC_CAP_DEFAULTS, ADV7842_MAX_ADDRS); 3548 err = PTR_ERR_OR_ZERO(state->cec_adap); 3549 if (err) 3550 goto err_entity; 3551 #endif 3552 3553 v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name, 3554 client->addr << 1, client->adapter->name); 3555 return 0; 3556 3557 err_entity: 3558 media_entity_cleanup(&sd->entity); 3559 err_work_queues: 3560 cancel_delayed_work(&state->delayed_work_enable_hotplug); 3561 err_i2c: 3562 adv7842_unregister_clients(sd); 3563 err_hdl: 3564 v4l2_ctrl_handler_free(hdl); 3565 return err; 3566 } 3567 3568 /* ----------------------------------------------------------------------- */ 3569 3570 static int adv7842_remove(struct i2c_client *client) 3571 { 3572 struct v4l2_subdev *sd = i2c_get_clientdata(client); 3573 struct adv7842_state *state = to_state(sd); 3574 3575 adv7842_irq_enable(sd, false); 3576 cancel_delayed_work(&state->delayed_work_enable_hotplug); 3577 v4l2_device_unregister_subdev(sd); 3578 media_entity_cleanup(&sd->entity); 3579 adv7842_unregister_clients(sd); 3580 v4l2_ctrl_handler_free(sd->ctrl_handler); 3581 return 0; 3582 } 3583 3584 /* ----------------------------------------------------------------------- */ 3585 3586 static const struct i2c_device_id adv7842_id[] = { 3587 { "adv7842", 0 }, 3588 { } 3589 }; 3590 MODULE_DEVICE_TABLE(i2c, adv7842_id); 3591 3592 /* ----------------------------------------------------------------------- */ 3593 3594 static struct i2c_driver adv7842_driver = { 3595 .driver = { 3596 .name = "adv7842", 3597 }, 3598 .probe = adv7842_probe, 3599 .remove = adv7842_remove, 3600 .id_table = adv7842_id, 3601 }; 3602 3603 module_i2c_driver(adv7842_driver); 3604