1 /* 2 * adv7842 - Analog Devices ADV7842 video decoder driver 3 * 4 * Copyright 2013 Cisco Systems, Inc. and/or its affiliates. All rights reserved. 5 * 6 * This program is free software; you may redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; version 2 of the License. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 11 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 12 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 13 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 14 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 15 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 16 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 17 * SOFTWARE. 18 * 19 */ 20 21 /* 22 * References (c = chapter, p = page): 23 * REF_01 - Analog devices, ADV7842, Register Settings Recommendations, 24 * Revision 2.5, June 2010 25 * REF_02 - Analog devices, Register map documentation, Documentation of 26 * the register maps, Software manual, Rev. F, June 2010 27 */ 28 29 30 #include <linux/kernel.h> 31 #include <linux/module.h> 32 #include <linux/slab.h> 33 #include <linux/i2c.h> 34 #include <linux/delay.h> 35 #include <linux/videodev2.h> 36 #include <linux/workqueue.h> 37 #include <linux/v4l2-dv-timings.h> 38 #include <media/v4l2-device.h> 39 #include <media/v4l2-ctrls.h> 40 #include <media/v4l2-dv-timings.h> 41 #include <media/adv7842.h> 42 43 static int debug; 44 module_param(debug, int, 0644); 45 MODULE_PARM_DESC(debug, "debug level (0-2)"); 46 47 MODULE_DESCRIPTION("Analog Devices ADV7842 video decoder driver"); 48 MODULE_AUTHOR("Hans Verkuil <hans.verkuil@cisco.com>"); 49 MODULE_AUTHOR("Martin Bugge <marbugge@cisco.com>"); 50 MODULE_LICENSE("GPL"); 51 52 /* ADV7842 system clock frequency */ 53 #define ADV7842_fsc (28636360) 54 55 /* 56 ********************************************************************** 57 * 58 * Arrays with configuration parameters for the ADV7842 59 * 60 ********************************************************************** 61 */ 62 63 struct adv7842_state { 64 struct v4l2_subdev sd; 65 struct media_pad pad; 66 struct v4l2_ctrl_handler hdl; 67 enum adv7842_mode mode; 68 struct v4l2_dv_timings timings; 69 enum adv7842_vid_std_select vid_std_select; 70 v4l2_std_id norm; 71 struct { 72 u8 edid[256]; 73 u32 present; 74 } hdmi_edid; 75 struct { 76 u8 edid[256]; 77 u32 present; 78 } vga_edid; 79 struct v4l2_fract aspect_ratio; 80 u32 rgb_quantization_range; 81 bool is_cea_format; 82 struct workqueue_struct *work_queues; 83 struct delayed_work delayed_work_enable_hotplug; 84 bool connector_hdmi; 85 bool hdmi_port_a; 86 87 /* i2c clients */ 88 struct i2c_client *i2c_sdp_io; 89 struct i2c_client *i2c_sdp; 90 struct i2c_client *i2c_cp; 91 struct i2c_client *i2c_vdp; 92 struct i2c_client *i2c_afe; 93 struct i2c_client *i2c_hdmi; 94 struct i2c_client *i2c_repeater; 95 struct i2c_client *i2c_edid; 96 struct i2c_client *i2c_infoframe; 97 struct i2c_client *i2c_cec; 98 struct i2c_client *i2c_avlink; 99 100 /* controls */ 101 struct v4l2_ctrl *detect_tx_5v_ctrl; 102 struct v4l2_ctrl *analog_sampling_phase_ctrl; 103 struct v4l2_ctrl *free_run_color_ctrl_manual; 104 struct v4l2_ctrl *free_run_color_ctrl; 105 struct v4l2_ctrl *rgb_quantization_range_ctrl; 106 }; 107 108 /* Unsupported timings. This device cannot support 720p30. */ 109 static const struct v4l2_dv_timings adv7842_timings_exceptions[] = { 110 V4L2_DV_BT_CEA_1280X720P30, 111 { } 112 }; 113 114 static bool adv7842_check_dv_timings(const struct v4l2_dv_timings *t, void *hdl) 115 { 116 int i; 117 118 for (i = 0; adv7842_timings_exceptions[i].bt.width; i++) 119 if (v4l2_match_dv_timings(t, adv7842_timings_exceptions + i, 0)) 120 return false; 121 return true; 122 } 123 124 struct adv7842_video_standards { 125 struct v4l2_dv_timings timings; 126 u8 vid_std; 127 u8 v_freq; 128 }; 129 130 /* sorted by number of lines */ 131 static const struct adv7842_video_standards adv7842_prim_mode_comp[] = { 132 /* { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 }, TODO flickering */ 133 { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 }, 134 { V4L2_DV_BT_CEA_1280X720P50, 0x19, 0x01 }, 135 { V4L2_DV_BT_CEA_1280X720P60, 0x19, 0x00 }, 136 { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 }, 137 { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 }, 138 { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 }, 139 { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 }, 140 { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 }, 141 /* TODO add 1920x1080P60_RB (CVT timing) */ 142 { }, 143 }; 144 145 /* sorted by number of lines */ 146 static const struct adv7842_video_standards adv7842_prim_mode_gr[] = { 147 { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 }, 148 { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 }, 149 { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 }, 150 { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 }, 151 { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 }, 152 { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 }, 153 { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 }, 154 { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 }, 155 { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 }, 156 { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 }, 157 { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 }, 158 { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 }, 159 { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 }, 160 { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 }, 161 { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 }, 162 { V4L2_DV_BT_DMT_1360X768P60, 0x12, 0x00 }, 163 { V4L2_DV_BT_DMT_1366X768P60, 0x13, 0x00 }, 164 { V4L2_DV_BT_DMT_1400X1050P60, 0x14, 0x00 }, 165 { V4L2_DV_BT_DMT_1400X1050P75, 0x15, 0x00 }, 166 { V4L2_DV_BT_DMT_1600X1200P60, 0x16, 0x00 }, /* TODO not tested */ 167 /* TODO add 1600X1200P60_RB (not a DMT timing) */ 168 { V4L2_DV_BT_DMT_1680X1050P60, 0x18, 0x00 }, 169 { V4L2_DV_BT_DMT_1920X1200P60_RB, 0x19, 0x00 }, /* TODO not tested */ 170 { }, 171 }; 172 173 /* sorted by number of lines */ 174 static const struct adv7842_video_standards adv7842_prim_mode_hdmi_comp[] = { 175 { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 }, 176 { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 }, 177 { V4L2_DV_BT_CEA_1280X720P50, 0x13, 0x01 }, 178 { V4L2_DV_BT_CEA_1280X720P60, 0x13, 0x00 }, 179 { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 }, 180 { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 }, 181 { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 }, 182 { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 }, 183 { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 }, 184 { }, 185 }; 186 187 /* sorted by number of lines */ 188 static const struct adv7842_video_standards adv7842_prim_mode_hdmi_gr[] = { 189 { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 }, 190 { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 }, 191 { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 }, 192 { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 }, 193 { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 }, 194 { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 }, 195 { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 }, 196 { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 }, 197 { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 }, 198 { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 }, 199 { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 }, 200 { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 }, 201 { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 }, 202 { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 }, 203 { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 }, 204 { }, 205 }; 206 207 /* ----------------------------------------------------------------------- */ 208 209 static inline struct adv7842_state *to_state(struct v4l2_subdev *sd) 210 { 211 return container_of(sd, struct adv7842_state, sd); 212 } 213 214 static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl) 215 { 216 return &container_of(ctrl->handler, struct adv7842_state, hdl)->sd; 217 } 218 219 static inline unsigned hblanking(const struct v4l2_bt_timings *t) 220 { 221 return V4L2_DV_BT_BLANKING_WIDTH(t); 222 } 223 224 static inline unsigned htotal(const struct v4l2_bt_timings *t) 225 { 226 return V4L2_DV_BT_FRAME_WIDTH(t); 227 } 228 229 static inline unsigned vblanking(const struct v4l2_bt_timings *t) 230 { 231 return V4L2_DV_BT_BLANKING_HEIGHT(t); 232 } 233 234 static inline unsigned vtotal(const struct v4l2_bt_timings *t) 235 { 236 return V4L2_DV_BT_FRAME_HEIGHT(t); 237 } 238 239 240 /* ----------------------------------------------------------------------- */ 241 242 static s32 adv_smbus_read_byte_data_check(struct i2c_client *client, 243 u8 command, bool check) 244 { 245 union i2c_smbus_data data; 246 247 if (!i2c_smbus_xfer(client->adapter, client->addr, client->flags, 248 I2C_SMBUS_READ, command, 249 I2C_SMBUS_BYTE_DATA, &data)) 250 return data.byte; 251 if (check) 252 v4l_err(client, "error reading %02x, %02x\n", 253 client->addr, command); 254 return -EIO; 255 } 256 257 static s32 adv_smbus_read_byte_data(struct i2c_client *client, u8 command) 258 { 259 int i; 260 261 for (i = 0; i < 3; i++) { 262 int ret = adv_smbus_read_byte_data_check(client, command, true); 263 264 if (ret >= 0) { 265 if (i) 266 v4l_err(client, "read ok after %d retries\n", i); 267 return ret; 268 } 269 } 270 v4l_err(client, "read failed\n"); 271 return -EIO; 272 } 273 274 static s32 adv_smbus_write_byte_data(struct i2c_client *client, 275 u8 command, u8 value) 276 { 277 union i2c_smbus_data data; 278 int err; 279 int i; 280 281 data.byte = value; 282 for (i = 0; i < 3; i++) { 283 err = i2c_smbus_xfer(client->adapter, client->addr, 284 client->flags, 285 I2C_SMBUS_WRITE, command, 286 I2C_SMBUS_BYTE_DATA, &data); 287 if (!err) 288 break; 289 } 290 if (err < 0) 291 v4l_err(client, "error writing %02x, %02x, %02x\n", 292 client->addr, command, value); 293 return err; 294 } 295 296 static void adv_smbus_write_byte_no_check(struct i2c_client *client, 297 u8 command, u8 value) 298 { 299 union i2c_smbus_data data; 300 data.byte = value; 301 302 i2c_smbus_xfer(client->adapter, client->addr, 303 client->flags, 304 I2C_SMBUS_WRITE, command, 305 I2C_SMBUS_BYTE_DATA, &data); 306 } 307 308 static s32 adv_smbus_write_i2c_block_data(struct i2c_client *client, 309 u8 command, unsigned length, const u8 *values) 310 { 311 union i2c_smbus_data data; 312 313 if (length > I2C_SMBUS_BLOCK_MAX) 314 length = I2C_SMBUS_BLOCK_MAX; 315 data.block[0] = length; 316 memcpy(data.block + 1, values, length); 317 return i2c_smbus_xfer(client->adapter, client->addr, client->flags, 318 I2C_SMBUS_WRITE, command, 319 I2C_SMBUS_I2C_BLOCK_DATA, &data); 320 } 321 322 /* ----------------------------------------------------------------------- */ 323 324 static inline int io_read(struct v4l2_subdev *sd, u8 reg) 325 { 326 struct i2c_client *client = v4l2_get_subdevdata(sd); 327 328 return adv_smbus_read_byte_data(client, reg); 329 } 330 331 static inline int io_write(struct v4l2_subdev *sd, u8 reg, u8 val) 332 { 333 struct i2c_client *client = v4l2_get_subdevdata(sd); 334 335 return adv_smbus_write_byte_data(client, reg, val); 336 } 337 338 static inline int io_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) 339 { 340 return io_write(sd, reg, (io_read(sd, reg) & mask) | val); 341 } 342 343 static inline int avlink_read(struct v4l2_subdev *sd, u8 reg) 344 { 345 struct adv7842_state *state = to_state(sd); 346 347 return adv_smbus_read_byte_data(state->i2c_avlink, reg); 348 } 349 350 static inline int avlink_write(struct v4l2_subdev *sd, u8 reg, u8 val) 351 { 352 struct adv7842_state *state = to_state(sd); 353 354 return adv_smbus_write_byte_data(state->i2c_avlink, reg, val); 355 } 356 357 static inline int cec_read(struct v4l2_subdev *sd, u8 reg) 358 { 359 struct adv7842_state *state = to_state(sd); 360 361 return adv_smbus_read_byte_data(state->i2c_cec, reg); 362 } 363 364 static inline int cec_write(struct v4l2_subdev *sd, u8 reg, u8 val) 365 { 366 struct adv7842_state *state = to_state(sd); 367 368 return adv_smbus_write_byte_data(state->i2c_cec, reg, val); 369 } 370 371 static inline int cec_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) 372 { 373 return cec_write(sd, reg, (cec_read(sd, reg) & mask) | val); 374 } 375 376 static inline int infoframe_read(struct v4l2_subdev *sd, u8 reg) 377 { 378 struct adv7842_state *state = to_state(sd); 379 380 return adv_smbus_read_byte_data(state->i2c_infoframe, reg); 381 } 382 383 static inline int infoframe_write(struct v4l2_subdev *sd, u8 reg, u8 val) 384 { 385 struct adv7842_state *state = to_state(sd); 386 387 return adv_smbus_write_byte_data(state->i2c_infoframe, reg, val); 388 } 389 390 static inline int sdp_io_read(struct v4l2_subdev *sd, u8 reg) 391 { 392 struct adv7842_state *state = to_state(sd); 393 394 return adv_smbus_read_byte_data(state->i2c_sdp_io, reg); 395 } 396 397 static inline int sdp_io_write(struct v4l2_subdev *sd, u8 reg, u8 val) 398 { 399 struct adv7842_state *state = to_state(sd); 400 401 return adv_smbus_write_byte_data(state->i2c_sdp_io, reg, val); 402 } 403 404 static inline int sdp_io_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) 405 { 406 return sdp_io_write(sd, reg, (sdp_io_read(sd, reg) & mask) | val); 407 } 408 409 static inline int sdp_read(struct v4l2_subdev *sd, u8 reg) 410 { 411 struct adv7842_state *state = to_state(sd); 412 413 return adv_smbus_read_byte_data(state->i2c_sdp, reg); 414 } 415 416 static inline int sdp_write(struct v4l2_subdev *sd, u8 reg, u8 val) 417 { 418 struct adv7842_state *state = to_state(sd); 419 420 return adv_smbus_write_byte_data(state->i2c_sdp, reg, val); 421 } 422 423 static inline int sdp_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) 424 { 425 return sdp_write(sd, reg, (sdp_read(sd, reg) & mask) | val); 426 } 427 428 static inline int afe_read(struct v4l2_subdev *sd, u8 reg) 429 { 430 struct adv7842_state *state = to_state(sd); 431 432 return adv_smbus_read_byte_data(state->i2c_afe, reg); 433 } 434 435 static inline int afe_write(struct v4l2_subdev *sd, u8 reg, u8 val) 436 { 437 struct adv7842_state *state = to_state(sd); 438 439 return adv_smbus_write_byte_data(state->i2c_afe, reg, val); 440 } 441 442 static inline int afe_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) 443 { 444 return afe_write(sd, reg, (afe_read(sd, reg) & mask) | val); 445 } 446 447 static inline int rep_read(struct v4l2_subdev *sd, u8 reg) 448 { 449 struct adv7842_state *state = to_state(sd); 450 451 return adv_smbus_read_byte_data(state->i2c_repeater, reg); 452 } 453 454 static inline int rep_write(struct v4l2_subdev *sd, u8 reg, u8 val) 455 { 456 struct adv7842_state *state = to_state(sd); 457 458 return adv_smbus_write_byte_data(state->i2c_repeater, reg, val); 459 } 460 461 static inline int rep_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) 462 { 463 return rep_write(sd, reg, (rep_read(sd, reg) & mask) | val); 464 } 465 466 static inline int edid_read(struct v4l2_subdev *sd, u8 reg) 467 { 468 struct adv7842_state *state = to_state(sd); 469 470 return adv_smbus_read_byte_data(state->i2c_edid, reg); 471 } 472 473 static inline int edid_write(struct v4l2_subdev *sd, u8 reg, u8 val) 474 { 475 struct adv7842_state *state = to_state(sd); 476 477 return adv_smbus_write_byte_data(state->i2c_edid, reg, val); 478 } 479 480 static inline int hdmi_read(struct v4l2_subdev *sd, u8 reg) 481 { 482 struct adv7842_state *state = to_state(sd); 483 484 return adv_smbus_read_byte_data(state->i2c_hdmi, reg); 485 } 486 487 static inline int hdmi_write(struct v4l2_subdev *sd, u8 reg, u8 val) 488 { 489 struct adv7842_state *state = to_state(sd); 490 491 return adv_smbus_write_byte_data(state->i2c_hdmi, reg, val); 492 } 493 494 static inline int cp_read(struct v4l2_subdev *sd, u8 reg) 495 { 496 struct adv7842_state *state = to_state(sd); 497 498 return adv_smbus_read_byte_data(state->i2c_cp, reg); 499 } 500 501 static inline int cp_write(struct v4l2_subdev *sd, u8 reg, u8 val) 502 { 503 struct adv7842_state *state = to_state(sd); 504 505 return adv_smbus_write_byte_data(state->i2c_cp, reg, val); 506 } 507 508 static inline int cp_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) 509 { 510 return cp_write(sd, reg, (cp_read(sd, reg) & mask) | val); 511 } 512 513 static inline int vdp_read(struct v4l2_subdev *sd, u8 reg) 514 { 515 struct adv7842_state *state = to_state(sd); 516 517 return adv_smbus_read_byte_data(state->i2c_vdp, reg); 518 } 519 520 static inline int vdp_write(struct v4l2_subdev *sd, u8 reg, u8 val) 521 { 522 struct adv7842_state *state = to_state(sd); 523 524 return adv_smbus_write_byte_data(state->i2c_vdp, reg, val); 525 } 526 527 static void main_reset(struct v4l2_subdev *sd) 528 { 529 struct i2c_client *client = v4l2_get_subdevdata(sd); 530 531 v4l2_dbg(1, debug, sd, "%s:\n", __func__); 532 533 adv_smbus_write_byte_no_check(client, 0xff, 0x80); 534 535 mdelay(2); 536 } 537 538 /* ----------------------------------------------------------------------- */ 539 540 static inline bool is_digital_input(struct v4l2_subdev *sd) 541 { 542 struct adv7842_state *state = to_state(sd); 543 544 return state->mode == ADV7842_MODE_HDMI; 545 } 546 547 static const struct v4l2_dv_timings_cap adv7842_timings_cap_analog = { 548 .type = V4L2_DV_BT_656_1120, 549 /* keep this initialization for compatibility with GCC < 4.4.6 */ 550 .reserved = { 0 }, 551 V4L2_INIT_BT_TIMINGS(0, 1920, 0, 1200, 25000000, 170000000, 552 V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT | 553 V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT, 554 V4L2_DV_BT_CAP_PROGRESSIVE | V4L2_DV_BT_CAP_REDUCED_BLANKING | 555 V4L2_DV_BT_CAP_CUSTOM) 556 }; 557 558 static const struct v4l2_dv_timings_cap adv7842_timings_cap_digital = { 559 .type = V4L2_DV_BT_656_1120, 560 /* keep this initialization for compatibility with GCC < 4.4.6 */ 561 .reserved = { 0 }, 562 V4L2_INIT_BT_TIMINGS(0, 1920, 0, 1200, 25000000, 225000000, 563 V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT | 564 V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT, 565 V4L2_DV_BT_CAP_PROGRESSIVE | V4L2_DV_BT_CAP_REDUCED_BLANKING | 566 V4L2_DV_BT_CAP_CUSTOM) 567 }; 568 569 static inline const struct v4l2_dv_timings_cap * 570 adv7842_get_dv_timings_cap(struct v4l2_subdev *sd) 571 { 572 return is_digital_input(sd) ? &adv7842_timings_cap_digital : 573 &adv7842_timings_cap_analog; 574 } 575 576 /* ----------------------------------------------------------------------- */ 577 578 static void adv7842_delayed_work_enable_hotplug(struct work_struct *work) 579 { 580 struct delayed_work *dwork = to_delayed_work(work); 581 struct adv7842_state *state = container_of(dwork, 582 struct adv7842_state, delayed_work_enable_hotplug); 583 struct v4l2_subdev *sd = &state->sd; 584 int present = state->hdmi_edid.present; 585 u8 mask = 0; 586 587 v4l2_dbg(2, debug, sd, "%s: enable hotplug on ports: 0x%x\n", 588 __func__, present); 589 590 if (present & 0x1) 591 mask |= 0x20; /* port A */ 592 if (present & 0x2) 593 mask |= 0x10; /* port B */ 594 io_write_and_or(sd, 0x20, 0xcf, mask); 595 } 596 597 static int edid_write_vga_segment(struct v4l2_subdev *sd) 598 { 599 struct i2c_client *client = v4l2_get_subdevdata(sd); 600 struct adv7842_state *state = to_state(sd); 601 const u8 *val = state->vga_edid.edid; 602 int err = 0; 603 int i; 604 605 v4l2_dbg(2, debug, sd, "%s: write EDID on VGA port\n", __func__); 606 607 /* HPA disable on port A and B */ 608 io_write_and_or(sd, 0x20, 0xcf, 0x00); 609 610 /* Disable I2C access to internal EDID ram from VGA DDC port */ 611 rep_write_and_or(sd, 0x7f, 0x7f, 0x00); 612 613 /* edid segment pointer '1' for VGA port */ 614 rep_write_and_or(sd, 0x77, 0xef, 0x10); 615 616 for (i = 0; !err && i < 256; i += I2C_SMBUS_BLOCK_MAX) 617 err = adv_smbus_write_i2c_block_data(state->i2c_edid, i, 618 I2C_SMBUS_BLOCK_MAX, val + i); 619 if (err) 620 return err; 621 622 /* Calculates the checksums and enables I2C access 623 * to internal EDID ram from VGA DDC port. 624 */ 625 rep_write_and_or(sd, 0x7f, 0x7f, 0x80); 626 627 for (i = 0; i < 1000; i++) { 628 if (rep_read(sd, 0x79) & 0x20) 629 break; 630 mdelay(1); 631 } 632 if (i == 1000) { 633 v4l_err(client, "error enabling edid on VGA port\n"); 634 return -EIO; 635 } 636 637 /* enable hotplug after 200 ms */ 638 queue_delayed_work(state->work_queues, 639 &state->delayed_work_enable_hotplug, HZ / 5); 640 641 return 0; 642 } 643 644 static int edid_spa_location(const u8 *edid) 645 { 646 u8 d; 647 648 /* 649 * TODO, improve and update for other CEA extensions 650 * currently only for 1 segment (256 bytes), 651 * i.e. 1 extension block and CEA revision 3. 652 */ 653 if ((edid[0x7e] != 1) || 654 (edid[0x80] != 0x02) || 655 (edid[0x81] != 0x03)) { 656 return -EINVAL; 657 } 658 /* 659 * search Vendor Specific Data Block (tag 3) 660 */ 661 d = edid[0x82] & 0x7f; 662 if (d > 4) { 663 int i = 0x84; 664 int end = 0x80 + d; 665 do { 666 u8 tag = edid[i]>>5; 667 u8 len = edid[i] & 0x1f; 668 669 if ((tag == 3) && (len >= 5)) 670 return i + 4; 671 i += len + 1; 672 } while (i < end); 673 } 674 return -EINVAL; 675 } 676 677 static int edid_write_hdmi_segment(struct v4l2_subdev *sd, u8 port) 678 { 679 struct i2c_client *client = v4l2_get_subdevdata(sd); 680 struct adv7842_state *state = to_state(sd); 681 const u8 *val = state->hdmi_edid.edid; 682 u8 cur_mask = rep_read(sd, 0x77) & 0x0c; 683 u8 mask = port == 0 ? 0x4 : 0x8; 684 int spa_loc = edid_spa_location(val); 685 int err = 0; 686 int i; 687 688 v4l2_dbg(2, debug, sd, "%s: write EDID on port %d (spa at 0x%x)\n", 689 __func__, port, spa_loc); 690 691 /* HPA disable on port A and B */ 692 io_write_and_or(sd, 0x20, 0xcf, 0x00); 693 694 /* Disable I2C access to internal EDID ram from HDMI DDC ports */ 695 rep_write_and_or(sd, 0x77, 0xf3, 0x00); 696 697 /* edid segment pointer '0' for HDMI ports */ 698 rep_write_and_or(sd, 0x77, 0xef, 0x00); 699 700 for (i = 0; !err && i < 256; i += I2C_SMBUS_BLOCK_MAX) 701 err = adv_smbus_write_i2c_block_data(state->i2c_edid, i, 702 I2C_SMBUS_BLOCK_MAX, val + i); 703 if (err) 704 return err; 705 706 if (spa_loc > 0) { 707 if (port == 0) { 708 /* port A SPA */ 709 rep_write(sd, 0x72, val[spa_loc]); 710 rep_write(sd, 0x73, val[spa_loc + 1]); 711 } else { 712 /* port B SPA */ 713 rep_write(sd, 0x74, val[spa_loc]); 714 rep_write(sd, 0x75, val[spa_loc + 1]); 715 } 716 rep_write(sd, 0x76, spa_loc); 717 } else { 718 /* default register values for SPA */ 719 if (port == 0) { 720 /* port A SPA */ 721 rep_write(sd, 0x72, 0); 722 rep_write(sd, 0x73, 0); 723 } else { 724 /* port B SPA */ 725 rep_write(sd, 0x74, 0); 726 rep_write(sd, 0x75, 0); 727 } 728 rep_write(sd, 0x76, 0xc0); 729 } 730 rep_write_and_or(sd, 0x77, 0xbf, 0x00); 731 732 /* Calculates the checksums and enables I2C access to internal 733 * EDID ram from HDMI DDC ports 734 */ 735 rep_write_and_or(sd, 0x77, 0xf3, mask | cur_mask); 736 737 for (i = 0; i < 1000; i++) { 738 if (rep_read(sd, 0x7d) & mask) 739 break; 740 mdelay(1); 741 } 742 if (i == 1000) { 743 v4l_err(client, "error enabling edid on port %d\n", port); 744 return -EIO; 745 } 746 747 /* enable hotplug after 200 ms */ 748 queue_delayed_work(state->work_queues, 749 &state->delayed_work_enable_hotplug, HZ / 5); 750 751 return 0; 752 } 753 754 /* ----------------------------------------------------------------------- */ 755 756 #ifdef CONFIG_VIDEO_ADV_DEBUG 757 static void adv7842_inv_register(struct v4l2_subdev *sd) 758 { 759 v4l2_info(sd, "0x000-0x0ff: IO Map\n"); 760 v4l2_info(sd, "0x100-0x1ff: AVLink Map\n"); 761 v4l2_info(sd, "0x200-0x2ff: CEC Map\n"); 762 v4l2_info(sd, "0x300-0x3ff: InfoFrame Map\n"); 763 v4l2_info(sd, "0x400-0x4ff: SDP_IO Map\n"); 764 v4l2_info(sd, "0x500-0x5ff: SDP Map\n"); 765 v4l2_info(sd, "0x600-0x6ff: AFE Map\n"); 766 v4l2_info(sd, "0x700-0x7ff: Repeater Map\n"); 767 v4l2_info(sd, "0x800-0x8ff: EDID Map\n"); 768 v4l2_info(sd, "0x900-0x9ff: HDMI Map\n"); 769 v4l2_info(sd, "0xa00-0xaff: CP Map\n"); 770 v4l2_info(sd, "0xb00-0xbff: VDP Map\n"); 771 } 772 773 static int adv7842_g_register(struct v4l2_subdev *sd, 774 struct v4l2_dbg_register *reg) 775 { 776 reg->size = 1; 777 switch (reg->reg >> 8) { 778 case 0: 779 reg->val = io_read(sd, reg->reg & 0xff); 780 break; 781 case 1: 782 reg->val = avlink_read(sd, reg->reg & 0xff); 783 break; 784 case 2: 785 reg->val = cec_read(sd, reg->reg & 0xff); 786 break; 787 case 3: 788 reg->val = infoframe_read(sd, reg->reg & 0xff); 789 break; 790 case 4: 791 reg->val = sdp_io_read(sd, reg->reg & 0xff); 792 break; 793 case 5: 794 reg->val = sdp_read(sd, reg->reg & 0xff); 795 break; 796 case 6: 797 reg->val = afe_read(sd, reg->reg & 0xff); 798 break; 799 case 7: 800 reg->val = rep_read(sd, reg->reg & 0xff); 801 break; 802 case 8: 803 reg->val = edid_read(sd, reg->reg & 0xff); 804 break; 805 case 9: 806 reg->val = hdmi_read(sd, reg->reg & 0xff); 807 break; 808 case 0xa: 809 reg->val = cp_read(sd, reg->reg & 0xff); 810 break; 811 case 0xb: 812 reg->val = vdp_read(sd, reg->reg & 0xff); 813 break; 814 default: 815 v4l2_info(sd, "Register %03llx not supported\n", reg->reg); 816 adv7842_inv_register(sd); 817 break; 818 } 819 return 0; 820 } 821 822 static int adv7842_s_register(struct v4l2_subdev *sd, 823 const struct v4l2_dbg_register *reg) 824 { 825 u8 val = reg->val & 0xff; 826 827 switch (reg->reg >> 8) { 828 case 0: 829 io_write(sd, reg->reg & 0xff, val); 830 break; 831 case 1: 832 avlink_write(sd, reg->reg & 0xff, val); 833 break; 834 case 2: 835 cec_write(sd, reg->reg & 0xff, val); 836 break; 837 case 3: 838 infoframe_write(sd, reg->reg & 0xff, val); 839 break; 840 case 4: 841 sdp_io_write(sd, reg->reg & 0xff, val); 842 break; 843 case 5: 844 sdp_write(sd, reg->reg & 0xff, val); 845 break; 846 case 6: 847 afe_write(sd, reg->reg & 0xff, val); 848 break; 849 case 7: 850 rep_write(sd, reg->reg & 0xff, val); 851 break; 852 case 8: 853 edid_write(sd, reg->reg & 0xff, val); 854 break; 855 case 9: 856 hdmi_write(sd, reg->reg & 0xff, val); 857 break; 858 case 0xa: 859 cp_write(sd, reg->reg & 0xff, val); 860 break; 861 case 0xb: 862 vdp_write(sd, reg->reg & 0xff, val); 863 break; 864 default: 865 v4l2_info(sd, "Register %03llx not supported\n", reg->reg); 866 adv7842_inv_register(sd); 867 break; 868 } 869 return 0; 870 } 871 #endif 872 873 static int adv7842_s_detect_tx_5v_ctrl(struct v4l2_subdev *sd) 874 { 875 struct adv7842_state *state = to_state(sd); 876 int prev = v4l2_ctrl_g_ctrl(state->detect_tx_5v_ctrl); 877 u8 reg_io_6f = io_read(sd, 0x6f); 878 int val = 0; 879 880 if (reg_io_6f & 0x02) 881 val |= 1; /* port A */ 882 if (reg_io_6f & 0x01) 883 val |= 2; /* port B */ 884 885 v4l2_dbg(1, debug, sd, "%s: 0x%x -> 0x%x\n", __func__, prev, val); 886 887 if (val != prev) 888 return v4l2_ctrl_s_ctrl(state->detect_tx_5v_ctrl, val); 889 return 0; 890 } 891 892 static int find_and_set_predefined_video_timings(struct v4l2_subdev *sd, 893 u8 prim_mode, 894 const struct adv7842_video_standards *predef_vid_timings, 895 const struct v4l2_dv_timings *timings) 896 { 897 int i; 898 899 for (i = 0; predef_vid_timings[i].timings.bt.width; i++) { 900 if (!v4l2_match_dv_timings(timings, &predef_vid_timings[i].timings, 901 is_digital_input(sd) ? 250000 : 1000000)) 902 continue; 903 /* video std */ 904 io_write(sd, 0x00, predef_vid_timings[i].vid_std); 905 /* v_freq and prim mode */ 906 io_write(sd, 0x01, (predef_vid_timings[i].v_freq << 4) + prim_mode); 907 return 0; 908 } 909 910 return -1; 911 } 912 913 static int configure_predefined_video_timings(struct v4l2_subdev *sd, 914 struct v4l2_dv_timings *timings) 915 { 916 struct adv7842_state *state = to_state(sd); 917 int err; 918 919 v4l2_dbg(1, debug, sd, "%s\n", __func__); 920 921 /* reset to default values */ 922 io_write(sd, 0x16, 0x43); 923 io_write(sd, 0x17, 0x5a); 924 /* disable embedded syncs for auto graphics mode */ 925 cp_write_and_or(sd, 0x81, 0xef, 0x00); 926 cp_write(sd, 0x26, 0x00); 927 cp_write(sd, 0x27, 0x00); 928 cp_write(sd, 0x28, 0x00); 929 cp_write(sd, 0x29, 0x00); 930 cp_write(sd, 0x8f, 0x00); 931 cp_write(sd, 0x90, 0x00); 932 cp_write(sd, 0xa5, 0x00); 933 cp_write(sd, 0xa6, 0x00); 934 cp_write(sd, 0xa7, 0x00); 935 cp_write(sd, 0xab, 0x00); 936 cp_write(sd, 0xac, 0x00); 937 938 switch (state->mode) { 939 case ADV7842_MODE_COMP: 940 case ADV7842_MODE_RGB: 941 err = find_and_set_predefined_video_timings(sd, 942 0x01, adv7842_prim_mode_comp, timings); 943 if (err) 944 err = find_and_set_predefined_video_timings(sd, 945 0x02, adv7842_prim_mode_gr, timings); 946 break; 947 case ADV7842_MODE_HDMI: 948 err = find_and_set_predefined_video_timings(sd, 949 0x05, adv7842_prim_mode_hdmi_comp, timings); 950 if (err) 951 err = find_and_set_predefined_video_timings(sd, 952 0x06, adv7842_prim_mode_hdmi_gr, timings); 953 break; 954 default: 955 v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n", 956 __func__, state->mode); 957 err = -1; 958 break; 959 } 960 961 962 return err; 963 } 964 965 static void configure_custom_video_timings(struct v4l2_subdev *sd, 966 const struct v4l2_bt_timings *bt) 967 { 968 struct adv7842_state *state = to_state(sd); 969 struct i2c_client *client = v4l2_get_subdevdata(sd); 970 u32 width = htotal(bt); 971 u32 height = vtotal(bt); 972 u16 cp_start_sav = bt->hsync + bt->hbackporch - 4; 973 u16 cp_start_eav = width - bt->hfrontporch; 974 u16 cp_start_vbi = height - bt->vfrontporch + 1; 975 u16 cp_end_vbi = bt->vsync + bt->vbackporch + 1; 976 u16 ch1_fr_ll = (((u32)bt->pixelclock / 100) > 0) ? 977 ((width * (ADV7842_fsc / 100)) / ((u32)bt->pixelclock / 100)) : 0; 978 const u8 pll[2] = { 979 0xc0 | ((width >> 8) & 0x1f), 980 width & 0xff 981 }; 982 983 v4l2_dbg(2, debug, sd, "%s\n", __func__); 984 985 switch (state->mode) { 986 case ADV7842_MODE_COMP: 987 case ADV7842_MODE_RGB: 988 /* auto graphics */ 989 io_write(sd, 0x00, 0x07); /* video std */ 990 io_write(sd, 0x01, 0x02); /* prim mode */ 991 /* enable embedded syncs for auto graphics mode */ 992 cp_write_and_or(sd, 0x81, 0xef, 0x10); 993 994 /* Should only be set in auto-graphics mode [REF_02, p. 91-92] */ 995 /* setup PLL_DIV_MAN_EN and PLL_DIV_RATIO */ 996 /* IO-map reg. 0x16 and 0x17 should be written in sequence */ 997 if (adv_smbus_write_i2c_block_data(client, 0x16, 2, pll)) { 998 v4l2_err(sd, "writing to reg 0x16 and 0x17 failed\n"); 999 break; 1000 } 1001 1002 /* active video - horizontal timing */ 1003 cp_write(sd, 0x26, (cp_start_sav >> 8) & 0xf); 1004 cp_write(sd, 0x27, (cp_start_sav & 0xff)); 1005 cp_write(sd, 0x28, (cp_start_eav >> 8) & 0xf); 1006 cp_write(sd, 0x29, (cp_start_eav & 0xff)); 1007 1008 /* active video - vertical timing */ 1009 cp_write(sd, 0xa5, (cp_start_vbi >> 4) & 0xff); 1010 cp_write(sd, 0xa6, ((cp_start_vbi & 0xf) << 4) | 1011 ((cp_end_vbi >> 8) & 0xf)); 1012 cp_write(sd, 0xa7, cp_end_vbi & 0xff); 1013 break; 1014 case ADV7842_MODE_HDMI: 1015 /* set default prim_mode/vid_std for HDMI 1016 according to [REF_03, c. 4.2] */ 1017 io_write(sd, 0x00, 0x02); /* video std */ 1018 io_write(sd, 0x01, 0x06); /* prim mode */ 1019 break; 1020 default: 1021 v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n", 1022 __func__, state->mode); 1023 break; 1024 } 1025 1026 cp_write(sd, 0x8f, (ch1_fr_ll >> 8) & 0x7); 1027 cp_write(sd, 0x90, ch1_fr_ll & 0xff); 1028 cp_write(sd, 0xab, (height >> 4) & 0xff); 1029 cp_write(sd, 0xac, (height & 0x0f) << 4); 1030 } 1031 1032 static void set_rgb_quantization_range(struct v4l2_subdev *sd) 1033 { 1034 struct adv7842_state *state = to_state(sd); 1035 1036 switch (state->rgb_quantization_range) { 1037 case V4L2_DV_RGB_RANGE_AUTO: 1038 /* automatic */ 1039 if (is_digital_input(sd) && !(hdmi_read(sd, 0x05) & 0x80)) { 1040 /* receiving DVI-D signal */ 1041 1042 /* ADV7842 selects RGB limited range regardless of 1043 input format (CE/IT) in automatic mode */ 1044 if (state->timings.bt.standards & V4L2_DV_BT_STD_CEA861) { 1045 /* RGB limited range (16-235) */ 1046 io_write_and_or(sd, 0x02, 0x0f, 0x00); 1047 1048 } else { 1049 /* RGB full range (0-255) */ 1050 io_write_and_or(sd, 0x02, 0x0f, 0x10); 1051 } 1052 } else { 1053 /* receiving HDMI or analog signal, set automode */ 1054 io_write_and_or(sd, 0x02, 0x0f, 0xf0); 1055 } 1056 break; 1057 case V4L2_DV_RGB_RANGE_LIMITED: 1058 /* RGB limited range (16-235) */ 1059 io_write_and_or(sd, 0x02, 0x0f, 0x00); 1060 break; 1061 case V4L2_DV_RGB_RANGE_FULL: 1062 /* RGB full range (0-255) */ 1063 io_write_and_or(sd, 0x02, 0x0f, 0x10); 1064 break; 1065 } 1066 } 1067 1068 static int adv7842_s_ctrl(struct v4l2_ctrl *ctrl) 1069 { 1070 struct v4l2_subdev *sd = to_sd(ctrl); 1071 struct adv7842_state *state = to_state(sd); 1072 1073 /* TODO SDP ctrls 1074 contrast/brightness/hue/free run is acting a bit strange, 1075 not sure if sdp csc is correct. 1076 */ 1077 switch (ctrl->id) { 1078 /* standard ctrls */ 1079 case V4L2_CID_BRIGHTNESS: 1080 cp_write(sd, 0x3c, ctrl->val); 1081 sdp_write(sd, 0x14, ctrl->val); 1082 /* ignore lsb sdp 0x17[3:2] */ 1083 return 0; 1084 case V4L2_CID_CONTRAST: 1085 cp_write(sd, 0x3a, ctrl->val); 1086 sdp_write(sd, 0x13, ctrl->val); 1087 /* ignore lsb sdp 0x17[1:0] */ 1088 return 0; 1089 case V4L2_CID_SATURATION: 1090 cp_write(sd, 0x3b, ctrl->val); 1091 sdp_write(sd, 0x15, ctrl->val); 1092 /* ignore lsb sdp 0x17[5:4] */ 1093 return 0; 1094 case V4L2_CID_HUE: 1095 cp_write(sd, 0x3d, ctrl->val); 1096 sdp_write(sd, 0x16, ctrl->val); 1097 /* ignore lsb sdp 0x17[7:6] */ 1098 return 0; 1099 /* custom ctrls */ 1100 case V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE: 1101 afe_write(sd, 0xc8, ctrl->val); 1102 return 0; 1103 case V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL: 1104 cp_write_and_or(sd, 0xbf, ~0x04, (ctrl->val << 2)); 1105 sdp_write_and_or(sd, 0xdd, ~0x04, (ctrl->val << 2)); 1106 return 0; 1107 case V4L2_CID_ADV_RX_FREE_RUN_COLOR: { 1108 u8 R = (ctrl->val & 0xff0000) >> 16; 1109 u8 G = (ctrl->val & 0x00ff00) >> 8; 1110 u8 B = (ctrl->val & 0x0000ff); 1111 /* RGB -> YUV, numerical approximation */ 1112 int Y = 66 * R + 129 * G + 25 * B; 1113 int U = -38 * R - 74 * G + 112 * B; 1114 int V = 112 * R - 94 * G - 18 * B; 1115 1116 /* Scale down to 8 bits with rounding */ 1117 Y = (Y + 128) >> 8; 1118 U = (U + 128) >> 8; 1119 V = (V + 128) >> 8; 1120 /* make U,V positive */ 1121 Y += 16; 1122 U += 128; 1123 V += 128; 1124 1125 v4l2_dbg(1, debug, sd, "R %x, G %x, B %x\n", R, G, B); 1126 v4l2_dbg(1, debug, sd, "Y %x, U %x, V %x\n", Y, U, V); 1127 1128 /* CP */ 1129 cp_write(sd, 0xc1, R); 1130 cp_write(sd, 0xc0, G); 1131 cp_write(sd, 0xc2, B); 1132 /* SDP */ 1133 sdp_write(sd, 0xde, Y); 1134 sdp_write(sd, 0xdf, (V & 0xf0) | ((U >> 4) & 0x0f)); 1135 return 0; 1136 } 1137 case V4L2_CID_DV_RX_RGB_RANGE: 1138 state->rgb_quantization_range = ctrl->val; 1139 set_rgb_quantization_range(sd); 1140 return 0; 1141 } 1142 return -EINVAL; 1143 } 1144 1145 static inline bool no_power(struct v4l2_subdev *sd) 1146 { 1147 return io_read(sd, 0x0c) & 0x24; 1148 } 1149 1150 static inline bool no_cp_signal(struct v4l2_subdev *sd) 1151 { 1152 return ((cp_read(sd, 0xb5) & 0xd0) != 0xd0) || !(cp_read(sd, 0xb1) & 0x80); 1153 } 1154 1155 static inline bool is_hdmi(struct v4l2_subdev *sd) 1156 { 1157 return hdmi_read(sd, 0x05) & 0x80; 1158 } 1159 1160 static int adv7842_g_input_status(struct v4l2_subdev *sd, u32 *status) 1161 { 1162 struct adv7842_state *state = to_state(sd); 1163 1164 *status = 0; 1165 1166 if (io_read(sd, 0x0c) & 0x24) 1167 *status |= V4L2_IN_ST_NO_POWER; 1168 1169 if (state->mode == ADV7842_MODE_SDP) { 1170 /* status from SDP block */ 1171 if (!(sdp_read(sd, 0x5A) & 0x01)) 1172 *status |= V4L2_IN_ST_NO_SIGNAL; 1173 1174 v4l2_dbg(1, debug, sd, "%s: SDP status = 0x%x\n", 1175 __func__, *status); 1176 return 0; 1177 } 1178 /* status from CP block */ 1179 if ((cp_read(sd, 0xb5) & 0xd0) != 0xd0 || 1180 !(cp_read(sd, 0xb1) & 0x80)) 1181 /* TODO channel 2 */ 1182 *status |= V4L2_IN_ST_NO_SIGNAL; 1183 1184 if (is_digital_input(sd) && ((io_read(sd, 0x74) & 0x03) != 0x03)) 1185 *status |= V4L2_IN_ST_NO_SIGNAL; 1186 1187 v4l2_dbg(1, debug, sd, "%s: CP status = 0x%x\n", 1188 __func__, *status); 1189 1190 return 0; 1191 } 1192 1193 struct stdi_readback { 1194 u16 bl, lcf, lcvs; 1195 u8 hs_pol, vs_pol; 1196 bool interlaced; 1197 }; 1198 1199 static int stdi2dv_timings(struct v4l2_subdev *sd, 1200 struct stdi_readback *stdi, 1201 struct v4l2_dv_timings *timings) 1202 { 1203 struct adv7842_state *state = to_state(sd); 1204 u32 hfreq = (ADV7842_fsc * 8) / stdi->bl; 1205 u32 pix_clk; 1206 int i; 1207 1208 for (i = 0; v4l2_dv_timings_presets[i].bt.width; i++) { 1209 const struct v4l2_bt_timings *bt = &v4l2_dv_timings_presets[i].bt; 1210 1211 if (!v4l2_valid_dv_timings(&v4l2_dv_timings_presets[i], 1212 adv7842_get_dv_timings_cap(sd), 1213 adv7842_check_dv_timings, NULL)) 1214 continue; 1215 if (vtotal(bt) != stdi->lcf + 1) 1216 continue; 1217 if (bt->vsync != stdi->lcvs) 1218 continue; 1219 1220 pix_clk = hfreq * htotal(bt); 1221 1222 if ((pix_clk < bt->pixelclock + 1000000) && 1223 (pix_clk > bt->pixelclock - 1000000)) { 1224 *timings = v4l2_dv_timings_presets[i]; 1225 return 0; 1226 } 1227 } 1228 1229 if (v4l2_detect_cvt(stdi->lcf + 1, hfreq, stdi->lcvs, 1230 (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) | 1231 (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0), 1232 timings)) 1233 return 0; 1234 if (v4l2_detect_gtf(stdi->lcf + 1, hfreq, stdi->lcvs, 1235 (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) | 1236 (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0), 1237 state->aspect_ratio, timings)) 1238 return 0; 1239 1240 v4l2_dbg(2, debug, sd, 1241 "%s: No format candidate found for lcvs = %d, lcf=%d, bl = %d, %chsync, %cvsync\n", 1242 __func__, stdi->lcvs, stdi->lcf, stdi->bl, 1243 stdi->hs_pol, stdi->vs_pol); 1244 return -1; 1245 } 1246 1247 static int read_stdi(struct v4l2_subdev *sd, struct stdi_readback *stdi) 1248 { 1249 u32 status; 1250 1251 adv7842_g_input_status(sd, &status); 1252 if (status & V4L2_IN_ST_NO_SIGNAL) { 1253 v4l2_dbg(2, debug, sd, "%s: no signal\n", __func__); 1254 return -ENOLINK; 1255 } 1256 1257 stdi->bl = ((cp_read(sd, 0xb1) & 0x3f) << 8) | cp_read(sd, 0xb2); 1258 stdi->lcf = ((cp_read(sd, 0xb3) & 0x7) << 8) | cp_read(sd, 0xb4); 1259 stdi->lcvs = cp_read(sd, 0xb3) >> 3; 1260 1261 if ((cp_read(sd, 0xb5) & 0x80) && ((cp_read(sd, 0xb5) & 0x03) == 0x01)) { 1262 stdi->hs_pol = ((cp_read(sd, 0xb5) & 0x10) ? 1263 ((cp_read(sd, 0xb5) & 0x08) ? '+' : '-') : 'x'); 1264 stdi->vs_pol = ((cp_read(sd, 0xb5) & 0x40) ? 1265 ((cp_read(sd, 0xb5) & 0x20) ? '+' : '-') : 'x'); 1266 } else { 1267 stdi->hs_pol = 'x'; 1268 stdi->vs_pol = 'x'; 1269 } 1270 stdi->interlaced = (cp_read(sd, 0xb1) & 0x40) ? true : false; 1271 1272 if (stdi->lcf < 239 || stdi->bl < 8 || stdi->bl == 0x3fff) { 1273 v4l2_dbg(2, debug, sd, "%s: invalid signal\n", __func__); 1274 return -ENOLINK; 1275 } 1276 1277 v4l2_dbg(2, debug, sd, 1278 "%s: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %chsync, %cvsync, %s\n", 1279 __func__, stdi->lcf, stdi->bl, stdi->lcvs, 1280 stdi->hs_pol, stdi->vs_pol, 1281 stdi->interlaced ? "interlaced" : "progressive"); 1282 1283 return 0; 1284 } 1285 1286 static int adv7842_enum_dv_timings(struct v4l2_subdev *sd, 1287 struct v4l2_enum_dv_timings *timings) 1288 { 1289 return v4l2_enum_dv_timings_cap(timings, 1290 adv7842_get_dv_timings_cap(sd), adv7842_check_dv_timings, NULL); 1291 } 1292 1293 static int adv7842_dv_timings_cap(struct v4l2_subdev *sd, 1294 struct v4l2_dv_timings_cap *cap) 1295 { 1296 *cap = *adv7842_get_dv_timings_cap(sd); 1297 return 0; 1298 } 1299 1300 /* Fill the optional fields .standards and .flags in struct v4l2_dv_timings 1301 if the format is listed in adv7604_timings[] */ 1302 static void adv7842_fill_optional_dv_timings_fields(struct v4l2_subdev *sd, 1303 struct v4l2_dv_timings *timings) 1304 { 1305 v4l2_find_dv_timings_cap(timings, adv7842_get_dv_timings_cap(sd), 1306 is_digital_input(sd) ? 250000 : 1000000, 1307 adv7842_check_dv_timings, NULL); 1308 } 1309 1310 static int adv7842_query_dv_timings(struct v4l2_subdev *sd, 1311 struct v4l2_dv_timings *timings) 1312 { 1313 struct adv7842_state *state = to_state(sd); 1314 struct v4l2_bt_timings *bt = &timings->bt; 1315 struct stdi_readback stdi = { 0 }; 1316 1317 /* SDP block */ 1318 if (state->mode == ADV7842_MODE_SDP) 1319 return -ENODATA; 1320 1321 /* read STDI */ 1322 if (read_stdi(sd, &stdi)) { 1323 v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__); 1324 return -ENOLINK; 1325 } 1326 bt->interlaced = stdi.interlaced ? 1327 V4L2_DV_INTERLACED : V4L2_DV_PROGRESSIVE; 1328 bt->polarities = ((hdmi_read(sd, 0x05) & 0x10) ? V4L2_DV_VSYNC_POS_POL : 0) | 1329 ((hdmi_read(sd, 0x05) & 0x20) ? V4L2_DV_HSYNC_POS_POL : 0); 1330 bt->vsync = stdi.lcvs; 1331 1332 if (is_digital_input(sd)) { 1333 bool lock = hdmi_read(sd, 0x04) & 0x02; 1334 bool interlaced = hdmi_read(sd, 0x0b) & 0x20; 1335 unsigned w = (hdmi_read(sd, 0x07) & 0x1f) * 256 + hdmi_read(sd, 0x08); 1336 unsigned h = (hdmi_read(sd, 0x09) & 0x1f) * 256 + hdmi_read(sd, 0x0a); 1337 unsigned w_total = (hdmi_read(sd, 0x1e) & 0x3f) * 256 + 1338 hdmi_read(sd, 0x1f); 1339 unsigned h_total = ((hdmi_read(sd, 0x26) & 0x3f) * 256 + 1340 hdmi_read(sd, 0x27)) / 2; 1341 unsigned freq = (((hdmi_read(sd, 0x51) << 1) + 1342 (hdmi_read(sd, 0x52) >> 7)) * 1000000) + 1343 ((hdmi_read(sd, 0x52) & 0x7f) * 1000000) / 128; 1344 int i; 1345 1346 if (is_hdmi(sd)) { 1347 /* adjust for deep color mode */ 1348 freq = freq * 8 / (((hdmi_read(sd, 0x0b) & 0xc0)>>6) * 2 + 8); 1349 } 1350 1351 /* No lock? */ 1352 if (!lock) { 1353 v4l2_dbg(1, debug, sd, "%s: no lock on TMDS signal\n", __func__); 1354 return -ENOLCK; 1355 } 1356 /* Interlaced? */ 1357 if (interlaced) { 1358 v4l2_dbg(1, debug, sd, "%s: interlaced video not supported\n", __func__); 1359 return -ERANGE; 1360 } 1361 1362 for (i = 0; v4l2_dv_timings_presets[i].bt.width; i++) { 1363 const struct v4l2_bt_timings *bt = &v4l2_dv_timings_presets[i].bt; 1364 1365 if (!v4l2_valid_dv_timings(&v4l2_dv_timings_presets[i], 1366 adv7842_get_dv_timings_cap(sd), 1367 adv7842_check_dv_timings, NULL)) 1368 continue; 1369 if (w_total != htotal(bt) || h_total != vtotal(bt)) 1370 continue; 1371 1372 if (w != bt->width || h != bt->height) 1373 continue; 1374 1375 if (abs(freq - bt->pixelclock) > 1000000) 1376 continue; 1377 *timings = v4l2_dv_timings_presets[i]; 1378 return 0; 1379 } 1380 1381 timings->type = V4L2_DV_BT_656_1120; 1382 1383 bt->width = w; 1384 bt->height = h; 1385 bt->interlaced = (hdmi_read(sd, 0x0b) & 0x20) ? 1386 V4L2_DV_INTERLACED : V4L2_DV_PROGRESSIVE; 1387 bt->polarities = ((hdmi_read(sd, 0x05) & 0x10) ? 1388 V4L2_DV_VSYNC_POS_POL : 0) | ((hdmi_read(sd, 0x05) & 0x20) ? 1389 V4L2_DV_HSYNC_POS_POL : 0); 1390 bt->pixelclock = (((hdmi_read(sd, 0x51) << 1) + 1391 (hdmi_read(sd, 0x52) >> 7)) * 1000000) + 1392 ((hdmi_read(sd, 0x52) & 0x7f) * 1000000) / 128; 1393 bt->hfrontporch = (hdmi_read(sd, 0x20) & 0x1f) * 256 + 1394 hdmi_read(sd, 0x21); 1395 bt->hsync = (hdmi_read(sd, 0x22) & 0x1f) * 256 + 1396 hdmi_read(sd, 0x23); 1397 bt->hbackporch = (hdmi_read(sd, 0x24) & 0x1f) * 256 + 1398 hdmi_read(sd, 0x25); 1399 bt->vfrontporch = ((hdmi_read(sd, 0x2a) & 0x3f) * 256 + 1400 hdmi_read(sd, 0x2b)) / 2; 1401 bt->il_vfrontporch = ((hdmi_read(sd, 0x2c) & 0x3f) * 256 + 1402 hdmi_read(sd, 0x2d)) / 2; 1403 bt->vsync = ((hdmi_read(sd, 0x2e) & 0x3f) * 256 + 1404 hdmi_read(sd, 0x2f)) / 2; 1405 bt->il_vsync = ((hdmi_read(sd, 0x30) & 0x3f) * 256 + 1406 hdmi_read(sd, 0x31)) / 2; 1407 bt->vbackporch = ((hdmi_read(sd, 0x32) & 0x3f) * 256 + 1408 hdmi_read(sd, 0x33)) / 2; 1409 bt->il_vbackporch = ((hdmi_read(sd, 0x34) & 0x3f) * 256 + 1410 hdmi_read(sd, 0x35)) / 2; 1411 1412 bt->standards = 0; 1413 bt->flags = 0; 1414 } else { 1415 /* Interlaced? */ 1416 if (stdi.interlaced) { 1417 v4l2_dbg(1, debug, sd, "%s: interlaced video not supported\n", __func__); 1418 return -ERANGE; 1419 } 1420 1421 if (stdi2dv_timings(sd, &stdi, timings)) { 1422 v4l2_dbg(1, debug, sd, "%s: format not supported\n", __func__); 1423 return -ERANGE; 1424 } 1425 } 1426 1427 if (debug > 1) 1428 v4l2_print_dv_timings(sd->name, "adv7842_query_dv_timings: ", 1429 timings, true); 1430 return 0; 1431 } 1432 1433 static int adv7842_s_dv_timings(struct v4l2_subdev *sd, 1434 struct v4l2_dv_timings *timings) 1435 { 1436 struct adv7842_state *state = to_state(sd); 1437 struct v4l2_bt_timings *bt; 1438 int err; 1439 1440 if (state->mode == ADV7842_MODE_SDP) 1441 return -ENODATA; 1442 1443 bt = &timings->bt; 1444 1445 if (!v4l2_valid_dv_timings(timings, adv7842_get_dv_timings_cap(sd), 1446 adv7842_check_dv_timings, NULL)) 1447 return -ERANGE; 1448 1449 adv7842_fill_optional_dv_timings_fields(sd, timings); 1450 1451 state->timings = *timings; 1452 1453 cp_write(sd, 0x91, bt->interlaced ? 0x50 : 0x10); 1454 1455 /* Use prim_mode and vid_std when available */ 1456 err = configure_predefined_video_timings(sd, timings); 1457 if (err) { 1458 /* custom settings when the video format 1459 does not have prim_mode/vid_std */ 1460 configure_custom_video_timings(sd, bt); 1461 } 1462 1463 set_rgb_quantization_range(sd); 1464 1465 1466 if (debug > 1) 1467 v4l2_print_dv_timings(sd->name, "adv7842_s_dv_timings: ", 1468 timings, true); 1469 return 0; 1470 } 1471 1472 static int adv7842_g_dv_timings(struct v4l2_subdev *sd, 1473 struct v4l2_dv_timings *timings) 1474 { 1475 struct adv7842_state *state = to_state(sd); 1476 1477 if (state->mode == ADV7842_MODE_SDP) 1478 return -ENODATA; 1479 *timings = state->timings; 1480 return 0; 1481 } 1482 1483 static void enable_input(struct v4l2_subdev *sd) 1484 { 1485 struct adv7842_state *state = to_state(sd); 1486 switch (state->mode) { 1487 case ADV7842_MODE_SDP: 1488 case ADV7842_MODE_COMP: 1489 case ADV7842_MODE_RGB: 1490 /* enable */ 1491 io_write(sd, 0x15, 0xb0); /* Disable Tristate of Pins (no audio) */ 1492 break; 1493 case ADV7842_MODE_HDMI: 1494 /* enable */ 1495 hdmi_write(sd, 0x1a, 0x0a); /* Unmute audio */ 1496 hdmi_write(sd, 0x01, 0x00); /* Enable HDMI clock terminators */ 1497 io_write(sd, 0x15, 0xa0); /* Disable Tristate of Pins */ 1498 break; 1499 default: 1500 v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n", 1501 __func__, state->mode); 1502 break; 1503 } 1504 } 1505 1506 static void disable_input(struct v4l2_subdev *sd) 1507 { 1508 /* disable */ 1509 io_write(sd, 0x15, 0xbe); /* Tristate all outputs from video core */ 1510 hdmi_write(sd, 0x1a, 0x1a); /* Mute audio */ 1511 hdmi_write(sd, 0x01, 0x78); /* Disable HDMI clock terminators */ 1512 } 1513 1514 static void sdp_csc_coeff(struct v4l2_subdev *sd, 1515 const struct adv7842_sdp_csc_coeff *c) 1516 { 1517 /* csc auto/manual */ 1518 sdp_io_write_and_or(sd, 0xe0, 0xbf, c->manual ? 0x00 : 0x40); 1519 1520 if (!c->manual) 1521 return; 1522 1523 /* csc scaling */ 1524 sdp_io_write_and_or(sd, 0xe0, 0x7f, c->scaling == 2 ? 0x80 : 0x00); 1525 1526 /* A coeff */ 1527 sdp_io_write_and_or(sd, 0xe0, 0xe0, c->A1 >> 8); 1528 sdp_io_write(sd, 0xe1, c->A1); 1529 sdp_io_write_and_or(sd, 0xe2, 0xe0, c->A2 >> 8); 1530 sdp_io_write(sd, 0xe3, c->A2); 1531 sdp_io_write_and_or(sd, 0xe4, 0xe0, c->A3 >> 8); 1532 sdp_io_write(sd, 0xe5, c->A3); 1533 1534 /* A scale */ 1535 sdp_io_write_and_or(sd, 0xe6, 0x80, c->A4 >> 8); 1536 sdp_io_write(sd, 0xe7, c->A4); 1537 1538 /* B coeff */ 1539 sdp_io_write_and_or(sd, 0xe8, 0xe0, c->B1 >> 8); 1540 sdp_io_write(sd, 0xe9, c->B1); 1541 sdp_io_write_and_or(sd, 0xea, 0xe0, c->B2 >> 8); 1542 sdp_io_write(sd, 0xeb, c->B2); 1543 sdp_io_write_and_or(sd, 0xec, 0xe0, c->B3 >> 8); 1544 sdp_io_write(sd, 0xed, c->B3); 1545 1546 /* B scale */ 1547 sdp_io_write_and_or(sd, 0xee, 0x80, c->B4 >> 8); 1548 sdp_io_write(sd, 0xef, c->B4); 1549 1550 /* C coeff */ 1551 sdp_io_write_and_or(sd, 0xf0, 0xe0, c->C1 >> 8); 1552 sdp_io_write(sd, 0xf1, c->C1); 1553 sdp_io_write_and_or(sd, 0xf2, 0xe0, c->C2 >> 8); 1554 sdp_io_write(sd, 0xf3, c->C2); 1555 sdp_io_write_and_or(sd, 0xf4, 0xe0, c->C3 >> 8); 1556 sdp_io_write(sd, 0xf5, c->C3); 1557 1558 /* C scale */ 1559 sdp_io_write_and_or(sd, 0xf6, 0x80, c->C4 >> 8); 1560 sdp_io_write(sd, 0xf7, c->C4); 1561 } 1562 1563 static void select_input(struct v4l2_subdev *sd, 1564 enum adv7842_vid_std_select vid_std_select) 1565 { 1566 struct adv7842_state *state = to_state(sd); 1567 1568 switch (state->mode) { 1569 case ADV7842_MODE_SDP: 1570 io_write(sd, 0x00, vid_std_select); /* video std: CVBS or YC mode */ 1571 io_write(sd, 0x01, 0); /* prim mode */ 1572 /* enable embedded syncs for auto graphics mode */ 1573 cp_write_and_or(sd, 0x81, 0xef, 0x10); 1574 1575 afe_write(sd, 0x00, 0x00); /* power up ADC */ 1576 afe_write(sd, 0xc8, 0x00); /* phase control */ 1577 1578 io_write(sd, 0x19, 0x83); /* LLC DLL phase */ 1579 io_write(sd, 0x33, 0x40); /* LLC DLL enable */ 1580 1581 io_write(sd, 0xdd, 0x90); /* Manual 2x output clock */ 1582 /* script says register 0xde, which don't exist in manual */ 1583 1584 /* Manual analog input muxing mode, CVBS (6.4)*/ 1585 afe_write_and_or(sd, 0x02, 0x7f, 0x80); 1586 if (vid_std_select == ADV7842_SDP_VID_STD_CVBS_SD_4x1) { 1587 afe_write(sd, 0x03, 0xa0); /* ADC0 to AIN10 (CVBS), ADC1 N/C*/ 1588 afe_write(sd, 0x04, 0x00); /* ADC2 N/C,ADC3 N/C*/ 1589 } else { 1590 afe_write(sd, 0x03, 0xa0); /* ADC0 to AIN10 (CVBS), ADC1 N/C*/ 1591 afe_write(sd, 0x04, 0xc0); /* ADC2 to AIN12, ADC3 N/C*/ 1592 } 1593 afe_write(sd, 0x0c, 0x1f); /* ADI recommend write */ 1594 afe_write(sd, 0x12, 0x63); /* ADI recommend write */ 1595 1596 sdp_io_write(sd, 0xb2, 0x60); /* Disable AV codes */ 1597 sdp_io_write(sd, 0xc8, 0xe3); /* Disable Ancillary data */ 1598 1599 /* SDP recommended settings */ 1600 sdp_write(sd, 0x00, 0x3F); /* Autodetect PAL NTSC (not SECAM) */ 1601 sdp_write(sd, 0x01, 0x00); /* Pedestal Off */ 1602 1603 sdp_write(sd, 0x03, 0xE4); /* Manual VCR Gain Luma 0x40B */ 1604 sdp_write(sd, 0x04, 0x0B); /* Manual Luma setting */ 1605 sdp_write(sd, 0x05, 0xC3); /* Manual Chroma setting 0x3FE */ 1606 sdp_write(sd, 0x06, 0xFE); /* Manual Chroma setting */ 1607 sdp_write(sd, 0x12, 0x0D); /* Frame TBC,I_P, 3D comb enabled */ 1608 sdp_write(sd, 0xA7, 0x00); /* ADI Recommended Write */ 1609 sdp_io_write(sd, 0xB0, 0x00); /* Disable H and v blanking */ 1610 1611 /* deinterlacer enabled and 3D comb */ 1612 sdp_write_and_or(sd, 0x12, 0xf6, 0x09); 1613 1614 sdp_write(sd, 0xdd, 0x08); /* free run auto */ 1615 1616 break; 1617 1618 case ADV7842_MODE_COMP: 1619 case ADV7842_MODE_RGB: 1620 /* Automatic analog input muxing mode */ 1621 afe_write_and_or(sd, 0x02, 0x7f, 0x00); 1622 /* set mode and select free run resolution */ 1623 io_write(sd, 0x00, vid_std_select); /* video std */ 1624 io_write(sd, 0x01, 0x02); /* prim mode */ 1625 cp_write_and_or(sd, 0x81, 0xef, 0x10); /* enable embedded syncs 1626 for auto graphics mode */ 1627 1628 afe_write(sd, 0x00, 0x00); /* power up ADC */ 1629 afe_write(sd, 0xc8, 0x00); /* phase control */ 1630 1631 /* set ADI recommended settings for digitizer */ 1632 /* "ADV7842 Register Settings Recommendations 1633 * (rev. 1.8, November 2010)" p. 9. */ 1634 afe_write(sd, 0x0c, 0x1f); /* ADC Range improvement */ 1635 afe_write(sd, 0x12, 0x63); /* ADC Range improvement */ 1636 1637 /* set to default gain for RGB */ 1638 cp_write(sd, 0x73, 0x10); 1639 cp_write(sd, 0x74, 0x04); 1640 cp_write(sd, 0x75, 0x01); 1641 cp_write(sd, 0x76, 0x00); 1642 1643 cp_write(sd, 0x3e, 0x04); /* CP core pre-gain control */ 1644 cp_write(sd, 0xc3, 0x39); /* CP coast control. Graphics mode */ 1645 cp_write(sd, 0x40, 0x5c); /* CP core pre-gain control. Graphics mode */ 1646 break; 1647 1648 case ADV7842_MODE_HDMI: 1649 /* Automatic analog input muxing mode */ 1650 afe_write_and_or(sd, 0x02, 0x7f, 0x00); 1651 /* set mode and select free run resolution */ 1652 if (state->hdmi_port_a) 1653 hdmi_write(sd, 0x00, 0x02); /* select port A */ 1654 else 1655 hdmi_write(sd, 0x00, 0x03); /* select port B */ 1656 io_write(sd, 0x00, vid_std_select); /* video std */ 1657 io_write(sd, 0x01, 5); /* prim mode */ 1658 cp_write_and_or(sd, 0x81, 0xef, 0x00); /* disable embedded syncs 1659 for auto graphics mode */ 1660 1661 /* set ADI recommended settings for HDMI: */ 1662 /* "ADV7842 Register Settings Recommendations 1663 * (rev. 1.8, November 2010)" p. 3. */ 1664 hdmi_write(sd, 0xc0, 0x00); 1665 hdmi_write(sd, 0x0d, 0x34); /* ADI recommended write */ 1666 hdmi_write(sd, 0x3d, 0x10); /* ADI recommended write */ 1667 hdmi_write(sd, 0x44, 0x85); /* TMDS PLL optimization */ 1668 hdmi_write(sd, 0x46, 0x1f); /* ADI recommended write */ 1669 hdmi_write(sd, 0x57, 0xb6); /* TMDS PLL optimization */ 1670 hdmi_write(sd, 0x58, 0x03); /* TMDS PLL optimization */ 1671 hdmi_write(sd, 0x60, 0x88); /* TMDS PLL optimization */ 1672 hdmi_write(sd, 0x61, 0x88); /* TMDS PLL optimization */ 1673 hdmi_write(sd, 0x6c, 0x18); /* Disable ISRC clearing bit, 1674 Improve robustness */ 1675 hdmi_write(sd, 0x75, 0x10); /* DDC drive strength */ 1676 hdmi_write(sd, 0x85, 0x1f); /* equaliser */ 1677 hdmi_write(sd, 0x87, 0x70); /* ADI recommended write */ 1678 hdmi_write(sd, 0x89, 0x04); /* equaliser */ 1679 hdmi_write(sd, 0x8a, 0x1e); /* equaliser */ 1680 hdmi_write(sd, 0x93, 0x04); /* equaliser */ 1681 hdmi_write(sd, 0x94, 0x1e); /* equaliser */ 1682 hdmi_write(sd, 0x99, 0xa1); /* ADI recommended write */ 1683 hdmi_write(sd, 0x9b, 0x09); /* ADI recommended write */ 1684 hdmi_write(sd, 0x9d, 0x02); /* equaliser */ 1685 1686 afe_write(sd, 0x00, 0xff); /* power down ADC */ 1687 afe_write(sd, 0xc8, 0x40); /* phase control */ 1688 1689 /* set to default gain for HDMI */ 1690 cp_write(sd, 0x73, 0x10); 1691 cp_write(sd, 0x74, 0x04); 1692 cp_write(sd, 0x75, 0x01); 1693 cp_write(sd, 0x76, 0x00); 1694 1695 /* reset ADI recommended settings for digitizer */ 1696 /* "ADV7842 Register Settings Recommendations 1697 * (rev. 2.5, June 2010)" p. 17. */ 1698 afe_write(sd, 0x12, 0xfb); /* ADC noise shaping filter controls */ 1699 afe_write(sd, 0x0c, 0x0d); /* CP core gain controls */ 1700 cp_write(sd, 0x3e, 0x80); /* CP core pre-gain control, 1701 enable color control */ 1702 /* CP coast control */ 1703 cp_write(sd, 0xc3, 0x33); /* Component mode */ 1704 1705 /* color space conversion, autodetect color space */ 1706 io_write_and_or(sd, 0x02, 0x0f, 0xf0); 1707 break; 1708 1709 default: 1710 v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n", 1711 __func__, state->mode); 1712 break; 1713 } 1714 } 1715 1716 static int adv7842_s_routing(struct v4l2_subdev *sd, 1717 u32 input, u32 output, u32 config) 1718 { 1719 struct adv7842_state *state = to_state(sd); 1720 1721 v4l2_dbg(2, debug, sd, "%s: input %d\n", __func__, input); 1722 1723 switch (input) { 1724 case ADV7842_SELECT_HDMI_PORT_A: 1725 /* TODO select HDMI_COMP or HDMI_GR */ 1726 state->mode = ADV7842_MODE_HDMI; 1727 state->vid_std_select = ADV7842_HDMI_COMP_VID_STD_HD_1250P; 1728 state->hdmi_port_a = true; 1729 break; 1730 case ADV7842_SELECT_HDMI_PORT_B: 1731 /* TODO select HDMI_COMP or HDMI_GR */ 1732 state->mode = ADV7842_MODE_HDMI; 1733 state->vid_std_select = ADV7842_HDMI_COMP_VID_STD_HD_1250P; 1734 state->hdmi_port_a = false; 1735 break; 1736 case ADV7842_SELECT_VGA_COMP: 1737 v4l2_info(sd, "%s: VGA component: todo\n", __func__); 1738 case ADV7842_SELECT_VGA_RGB: 1739 state->mode = ADV7842_MODE_RGB; 1740 state->vid_std_select = ADV7842_RGB_VID_STD_AUTO_GRAPH_MODE; 1741 break; 1742 case ADV7842_SELECT_SDP_CVBS: 1743 state->mode = ADV7842_MODE_SDP; 1744 state->vid_std_select = ADV7842_SDP_VID_STD_CVBS_SD_4x1; 1745 break; 1746 case ADV7842_SELECT_SDP_YC: 1747 state->mode = ADV7842_MODE_SDP; 1748 state->vid_std_select = ADV7842_SDP_VID_STD_YC_SD4_x1; 1749 break; 1750 default: 1751 return -EINVAL; 1752 } 1753 1754 disable_input(sd); 1755 select_input(sd, state->vid_std_select); 1756 enable_input(sd); 1757 1758 v4l2_subdev_notify(sd, ADV7842_FMT_CHANGE, NULL); 1759 1760 return 0; 1761 } 1762 1763 static int adv7842_enum_mbus_fmt(struct v4l2_subdev *sd, unsigned int index, 1764 enum v4l2_mbus_pixelcode *code) 1765 { 1766 if (index) 1767 return -EINVAL; 1768 /* Good enough for now */ 1769 *code = V4L2_MBUS_FMT_FIXED; 1770 return 0; 1771 } 1772 1773 static int adv7842_g_mbus_fmt(struct v4l2_subdev *sd, 1774 struct v4l2_mbus_framefmt *fmt) 1775 { 1776 struct adv7842_state *state = to_state(sd); 1777 1778 fmt->width = state->timings.bt.width; 1779 fmt->height = state->timings.bt.height; 1780 fmt->code = V4L2_MBUS_FMT_FIXED; 1781 fmt->field = V4L2_FIELD_NONE; 1782 1783 if (state->mode == ADV7842_MODE_SDP) { 1784 /* SPD block */ 1785 if (!(sdp_read(sd, 0x5A) & 0x01)) 1786 return -EINVAL; 1787 fmt->width = 720; 1788 /* valid signal */ 1789 if (state->norm & V4L2_STD_525_60) 1790 fmt->height = 480; 1791 else 1792 fmt->height = 576; 1793 fmt->colorspace = V4L2_COLORSPACE_SMPTE170M; 1794 return 0; 1795 } 1796 1797 if (state->timings.bt.standards & V4L2_DV_BT_STD_CEA861) { 1798 fmt->colorspace = (state->timings.bt.height <= 576) ? 1799 V4L2_COLORSPACE_SMPTE170M : V4L2_COLORSPACE_REC709; 1800 } 1801 return 0; 1802 } 1803 1804 static void adv7842_irq_enable(struct v4l2_subdev *sd, bool enable) 1805 { 1806 if (enable) { 1807 /* Enable SSPD, STDI and CP locked/unlocked interrupts */ 1808 io_write(sd, 0x46, 0x9c); 1809 /* ESDP_50HZ_DET interrupt */ 1810 io_write(sd, 0x5a, 0x10); 1811 /* Enable CABLE_DET_A/B_ST (+5v) interrupt */ 1812 io_write(sd, 0x73, 0x03); 1813 /* Enable V_LOCKED and DE_REGEN_LCK interrupts */ 1814 io_write(sd, 0x78, 0x03); 1815 /* Enable SDP Standard Detection Change and SDP Video Detected */ 1816 io_write(sd, 0xa0, 0x09); 1817 } else { 1818 io_write(sd, 0x46, 0x0); 1819 io_write(sd, 0x5a, 0x0); 1820 io_write(sd, 0x73, 0x0); 1821 io_write(sd, 0x78, 0x0); 1822 io_write(sd, 0xa0, 0x0); 1823 } 1824 } 1825 1826 static int adv7842_isr(struct v4l2_subdev *sd, u32 status, bool *handled) 1827 { 1828 struct adv7842_state *state = to_state(sd); 1829 u8 fmt_change_cp, fmt_change_digital, fmt_change_sdp; 1830 u8 irq_status[5]; 1831 u8 irq_cfg = io_read(sd, 0x40); 1832 1833 /* disable irq-pin output */ 1834 io_write(sd, 0x40, irq_cfg | 0x3); 1835 1836 /* read status */ 1837 irq_status[0] = io_read(sd, 0x43); 1838 irq_status[1] = io_read(sd, 0x57); 1839 irq_status[2] = io_read(sd, 0x70); 1840 irq_status[3] = io_read(sd, 0x75); 1841 irq_status[4] = io_read(sd, 0x9d); 1842 1843 /* and clear */ 1844 if (irq_status[0]) 1845 io_write(sd, 0x44, irq_status[0]); 1846 if (irq_status[1]) 1847 io_write(sd, 0x58, irq_status[1]); 1848 if (irq_status[2]) 1849 io_write(sd, 0x71, irq_status[2]); 1850 if (irq_status[3]) 1851 io_write(sd, 0x76, irq_status[3]); 1852 if (irq_status[4]) 1853 io_write(sd, 0x9e, irq_status[4]); 1854 1855 v4l2_dbg(1, debug, sd, "%s: irq %x, %x, %x, %x, %x\n", __func__, 1856 irq_status[0], irq_status[1], irq_status[2], 1857 irq_status[3], irq_status[4]); 1858 1859 /* format change CP */ 1860 fmt_change_cp = irq_status[0] & 0x9c; 1861 1862 /* format change SDP */ 1863 if (state->mode == ADV7842_MODE_SDP) 1864 fmt_change_sdp = (irq_status[1] & 0x30) | (irq_status[4] & 0x09); 1865 else 1866 fmt_change_sdp = 0; 1867 1868 /* digital format CP */ 1869 if (is_digital_input(sd)) 1870 fmt_change_digital = irq_status[3] & 0x03; 1871 else 1872 fmt_change_digital = 0; 1873 1874 /* notify */ 1875 if (fmt_change_cp || fmt_change_digital || fmt_change_sdp) { 1876 v4l2_dbg(1, debug, sd, 1877 "%s: fmt_change_cp = 0x%x, fmt_change_digital = 0x%x, fmt_change_sdp = 0x%x\n", 1878 __func__, fmt_change_cp, fmt_change_digital, 1879 fmt_change_sdp); 1880 v4l2_subdev_notify(sd, ADV7842_FMT_CHANGE, NULL); 1881 } 1882 1883 /* 5v cable detect */ 1884 if (irq_status[2]) 1885 adv7842_s_detect_tx_5v_ctrl(sd); 1886 1887 if (handled) 1888 *handled = true; 1889 1890 /* re-enable irq-pin output */ 1891 io_write(sd, 0x40, irq_cfg); 1892 1893 return 0; 1894 } 1895 1896 static int adv7842_set_edid(struct v4l2_subdev *sd, struct v4l2_subdev_edid *e) 1897 { 1898 struct adv7842_state *state = to_state(sd); 1899 int err = 0; 1900 1901 if (e->pad > 2) 1902 return -EINVAL; 1903 if (e->start_block != 0) 1904 return -EINVAL; 1905 if (e->blocks > 2) 1906 return -E2BIG; 1907 if (!e->edid) 1908 return -EINVAL; 1909 1910 /* todo, per edid */ 1911 state->aspect_ratio = v4l2_calc_aspect_ratio(e->edid[0x15], 1912 e->edid[0x16]); 1913 1914 if (e->pad == 2) { 1915 memset(&state->vga_edid.edid, 0, 256); 1916 state->vga_edid.present = e->blocks ? 0x1 : 0x0; 1917 memcpy(&state->vga_edid.edid, e->edid, 128 * e->blocks); 1918 err = edid_write_vga_segment(sd); 1919 } else { 1920 u32 mask = 0x1<<e->pad; 1921 memset(&state->hdmi_edid.edid, 0, 256); 1922 if (e->blocks) 1923 state->hdmi_edid.present |= mask; 1924 else 1925 state->hdmi_edid.present &= ~mask; 1926 memcpy(&state->hdmi_edid.edid, e->edid, 128*e->blocks); 1927 err = edid_write_hdmi_segment(sd, e->pad); 1928 } 1929 if (err < 0) 1930 v4l2_err(sd, "error %d writing edid on port %d\n", err, e->pad); 1931 return err; 1932 } 1933 1934 /*********** avi info frame CEA-861-E **************/ 1935 /* TODO move to common library */ 1936 1937 struct avi_info_frame { 1938 uint8_t f17; 1939 uint8_t y10; 1940 uint8_t a0; 1941 uint8_t b10; 1942 uint8_t s10; 1943 uint8_t c10; 1944 uint8_t m10; 1945 uint8_t r3210; 1946 uint8_t itc; 1947 uint8_t ec210; 1948 uint8_t q10; 1949 uint8_t sc10; 1950 uint8_t f47; 1951 uint8_t vic; 1952 uint8_t yq10; 1953 uint8_t cn10; 1954 uint8_t pr3210; 1955 uint16_t etb; 1956 uint16_t sbb; 1957 uint16_t elb; 1958 uint16_t srb; 1959 }; 1960 1961 static const char *y10_txt[4] = { 1962 "RGB", 1963 "YCbCr 4:2:2", 1964 "YCbCr 4:4:4", 1965 "Future", 1966 }; 1967 1968 static const char *c10_txt[4] = { 1969 "No Data", 1970 "SMPTE 170M", 1971 "ITU-R 709", 1972 "Extended Colorimetry information valied", 1973 }; 1974 1975 static const char *itc_txt[2] = { 1976 "No Data", 1977 "IT content", 1978 }; 1979 1980 static const char *ec210_txt[8] = { 1981 "xvYCC601", 1982 "xvYCC709", 1983 "sYCC601", 1984 "AdobeYCC601", 1985 "AdobeRGB", 1986 "5 reserved", 1987 "6 reserved", 1988 "7 reserved", 1989 }; 1990 1991 static const char *q10_txt[4] = { 1992 "Default", 1993 "Limited Range", 1994 "Full Range", 1995 "Reserved", 1996 }; 1997 1998 static void parse_avi_infoframe(struct v4l2_subdev *sd, uint8_t *buf, 1999 struct avi_info_frame *avi) 2000 { 2001 avi->f17 = (buf[1] >> 7) & 0x1; 2002 avi->y10 = (buf[1] >> 5) & 0x3; 2003 avi->a0 = (buf[1] >> 4) & 0x1; 2004 avi->b10 = (buf[1] >> 2) & 0x3; 2005 avi->s10 = buf[1] & 0x3; 2006 avi->c10 = (buf[2] >> 6) & 0x3; 2007 avi->m10 = (buf[2] >> 4) & 0x3; 2008 avi->r3210 = buf[2] & 0xf; 2009 avi->itc = (buf[3] >> 7) & 0x1; 2010 avi->ec210 = (buf[3] >> 4) & 0x7; 2011 avi->q10 = (buf[3] >> 2) & 0x3; 2012 avi->sc10 = buf[3] & 0x3; 2013 avi->f47 = (buf[4] >> 7) & 0x1; 2014 avi->vic = buf[4] & 0x7f; 2015 avi->yq10 = (buf[5] >> 6) & 0x3; 2016 avi->cn10 = (buf[5] >> 4) & 0x3; 2017 avi->pr3210 = buf[5] & 0xf; 2018 avi->etb = buf[6] + 256*buf[7]; 2019 avi->sbb = buf[8] + 256*buf[9]; 2020 avi->elb = buf[10] + 256*buf[11]; 2021 avi->srb = buf[12] + 256*buf[13]; 2022 } 2023 2024 static void print_avi_infoframe(struct v4l2_subdev *sd) 2025 { 2026 int i; 2027 uint8_t buf[14]; 2028 uint8_t avi_inf_len; 2029 struct avi_info_frame avi; 2030 2031 if (!(hdmi_read(sd, 0x05) & 0x80)) { 2032 v4l2_info(sd, "receive DVI-D signal (AVI infoframe not supported)\n"); 2033 return; 2034 } 2035 if (!(io_read(sd, 0x60) & 0x01)) { 2036 v4l2_info(sd, "AVI infoframe not received\n"); 2037 return; 2038 } 2039 2040 if (io_read(sd, 0x88) & 0x10) { 2041 /* Note: the ADV7842 calculated incorrect checksums for InfoFrames 2042 with a length of 14 or 15. See the ADV7842 Register Settings 2043 Recommendations document for more details. */ 2044 v4l2_info(sd, "AVI infoframe checksum error\n"); 2045 return; 2046 } 2047 2048 avi_inf_len = infoframe_read(sd, 0xe2); 2049 v4l2_info(sd, "AVI infoframe version %d (%d byte)\n", 2050 infoframe_read(sd, 0xe1), avi_inf_len); 2051 2052 if (infoframe_read(sd, 0xe1) != 0x02) 2053 return; 2054 2055 for (i = 0; i < 14; i++) 2056 buf[i] = infoframe_read(sd, i); 2057 2058 v4l2_info(sd, "\t%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n", 2059 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6], buf[7], 2060 buf[8], buf[9], buf[10], buf[11], buf[12], buf[13]); 2061 2062 parse_avi_infoframe(sd, buf, &avi); 2063 2064 if (avi.vic) 2065 v4l2_info(sd, "\tVIC: %d\n", avi.vic); 2066 if (avi.itc) 2067 v4l2_info(sd, "\t%s\n", itc_txt[avi.itc]); 2068 2069 if (avi.y10) 2070 v4l2_info(sd, "\t%s %s\n", y10_txt[avi.y10], !avi.c10 ? "" : 2071 (avi.c10 == 0x3 ? ec210_txt[avi.ec210] : c10_txt[avi.c10])); 2072 else 2073 v4l2_info(sd, "\t%s %s\n", y10_txt[avi.y10], q10_txt[avi.q10]); 2074 } 2075 2076 static const char * const prim_mode_txt[] = { 2077 "SDP", 2078 "Component", 2079 "Graphics", 2080 "Reserved", 2081 "CVBS & HDMI AUDIO", 2082 "HDMI-Comp", 2083 "HDMI-GR", 2084 "Reserved", 2085 "Reserved", 2086 "Reserved", 2087 "Reserved", 2088 "Reserved", 2089 "Reserved", 2090 "Reserved", 2091 "Reserved", 2092 "Reserved", 2093 }; 2094 2095 static int adv7842_sdp_log_status(struct v4l2_subdev *sd) 2096 { 2097 /* SDP (Standard definition processor) block */ 2098 uint8_t sdp_signal_detected = sdp_read(sd, 0x5A) & 0x01; 2099 2100 v4l2_info(sd, "Chip powered %s\n", no_power(sd) ? "off" : "on"); 2101 v4l2_info(sd, "Prim-mode = 0x%x, video std = 0x%x\n", 2102 io_read(sd, 0x01) & 0x0f, io_read(sd, 0x00) & 0x3f); 2103 2104 v4l2_info(sd, "SDP: free run: %s\n", 2105 (sdp_read(sd, 0x56) & 0x01) ? "on" : "off"); 2106 v4l2_info(sd, "SDP: %s\n", sdp_signal_detected ? 2107 "valid SD/PR signal detected" : "invalid/no signal"); 2108 if (sdp_signal_detected) { 2109 static const char * const sdp_std_txt[] = { 2110 "NTSC-M/J", 2111 "1?", 2112 "NTSC-443", 2113 "60HzSECAM", 2114 "PAL-M", 2115 "5?", 2116 "PAL-60", 2117 "7?", "8?", "9?", "a?", "b?", 2118 "PAL-CombN", 2119 "d?", 2120 "PAL-BGHID", 2121 "SECAM" 2122 }; 2123 v4l2_info(sd, "SDP: standard %s\n", 2124 sdp_std_txt[sdp_read(sd, 0x52) & 0x0f]); 2125 v4l2_info(sd, "SDP: %s\n", 2126 (sdp_read(sd, 0x59) & 0x08) ? "50Hz" : "60Hz"); 2127 v4l2_info(sd, "SDP: %s\n", 2128 (sdp_read(sd, 0x57) & 0x08) ? "Interlaced" : "Progressive"); 2129 v4l2_info(sd, "SDP: deinterlacer %s\n", 2130 (sdp_read(sd, 0x12) & 0x08) ? "enabled" : "disabled"); 2131 v4l2_info(sd, "SDP: csc %s mode\n", 2132 (sdp_io_read(sd, 0xe0) & 0x40) ? "auto" : "manual"); 2133 } 2134 return 0; 2135 } 2136 2137 static int adv7842_cp_log_status(struct v4l2_subdev *sd) 2138 { 2139 /* CP block */ 2140 struct adv7842_state *state = to_state(sd); 2141 struct v4l2_dv_timings timings; 2142 uint8_t reg_io_0x02 = io_read(sd, 0x02); 2143 uint8_t reg_io_0x21 = io_read(sd, 0x21); 2144 uint8_t reg_rep_0x77 = rep_read(sd, 0x77); 2145 uint8_t reg_rep_0x7d = rep_read(sd, 0x7d); 2146 bool audio_pll_locked = hdmi_read(sd, 0x04) & 0x01; 2147 bool audio_sample_packet_detect = hdmi_read(sd, 0x18) & 0x01; 2148 bool audio_mute = io_read(sd, 0x65) & 0x40; 2149 2150 static const char * const csc_coeff_sel_rb[16] = { 2151 "bypassed", "YPbPr601 -> RGB", "reserved", "YPbPr709 -> RGB", 2152 "reserved", "RGB -> YPbPr601", "reserved", "RGB -> YPbPr709", 2153 "reserved", "YPbPr709 -> YPbPr601", "YPbPr601 -> YPbPr709", 2154 "reserved", "reserved", "reserved", "reserved", "manual" 2155 }; 2156 static const char * const input_color_space_txt[16] = { 2157 "RGB limited range (16-235)", "RGB full range (0-255)", 2158 "YCbCr Bt.601 (16-235)", "YCbCr Bt.709 (16-235)", 2159 "XvYCC Bt.601", "XvYCC Bt.709", 2160 "YCbCr Bt.601 (0-255)", "YCbCr Bt.709 (0-255)", 2161 "invalid", "invalid", "invalid", "invalid", "invalid", 2162 "invalid", "invalid", "automatic" 2163 }; 2164 static const char * const rgb_quantization_range_txt[] = { 2165 "Automatic", 2166 "RGB limited range (16-235)", 2167 "RGB full range (0-255)", 2168 }; 2169 static const char * const deep_color_mode_txt[4] = { 2170 "8-bits per channel", 2171 "10-bits per channel", 2172 "12-bits per channel", 2173 "16-bits per channel (not supported)" 2174 }; 2175 2176 v4l2_info(sd, "-----Chip status-----\n"); 2177 v4l2_info(sd, "Chip power: %s\n", no_power(sd) ? "off" : "on"); 2178 v4l2_info(sd, "Connector type: %s\n", state->connector_hdmi ? 2179 "HDMI" : (is_digital_input(sd) ? "DVI-D" : "DVI-A")); 2180 v4l2_info(sd, "HDMI/DVI-D port selected: %s\n", 2181 state->hdmi_port_a ? "A" : "B"); 2182 v4l2_info(sd, "EDID A %s, B %s\n", 2183 ((reg_rep_0x7d & 0x04) && (reg_rep_0x77 & 0x04)) ? 2184 "enabled" : "disabled", 2185 ((reg_rep_0x7d & 0x08) && (reg_rep_0x77 & 0x08)) ? 2186 "enabled" : "disabled"); 2187 v4l2_info(sd, "HPD A %s, B %s\n", 2188 reg_io_0x21 & 0x02 ? "enabled" : "disabled", 2189 reg_io_0x21 & 0x01 ? "enabled" : "disabled"); 2190 v4l2_info(sd, "CEC %s\n", !!(cec_read(sd, 0x2a) & 0x01) ? 2191 "enabled" : "disabled"); 2192 2193 v4l2_info(sd, "-----Signal status-----\n"); 2194 if (state->hdmi_port_a) { 2195 v4l2_info(sd, "Cable detected (+5V power): %s\n", 2196 io_read(sd, 0x6f) & 0x02 ? "true" : "false"); 2197 v4l2_info(sd, "TMDS signal detected: %s\n", 2198 (io_read(sd, 0x6a) & 0x02) ? "true" : "false"); 2199 v4l2_info(sd, "TMDS signal locked: %s\n", 2200 (io_read(sd, 0x6a) & 0x20) ? "true" : "false"); 2201 } else { 2202 v4l2_info(sd, "Cable detected (+5V power):%s\n", 2203 io_read(sd, 0x6f) & 0x01 ? "true" : "false"); 2204 v4l2_info(sd, "TMDS signal detected: %s\n", 2205 (io_read(sd, 0x6a) & 0x01) ? "true" : "false"); 2206 v4l2_info(sd, "TMDS signal locked: %s\n", 2207 (io_read(sd, 0x6a) & 0x10) ? "true" : "false"); 2208 } 2209 v4l2_info(sd, "CP free run: %s\n", 2210 (!!(cp_read(sd, 0xff) & 0x10) ? "on" : "off")); 2211 v4l2_info(sd, "Prim-mode = 0x%x, video std = 0x%x, v_freq = 0x%x\n", 2212 io_read(sd, 0x01) & 0x0f, io_read(sd, 0x00) & 0x3f, 2213 (io_read(sd, 0x01) & 0x70) >> 4); 2214 2215 v4l2_info(sd, "-----Video Timings-----\n"); 2216 if (no_cp_signal(sd)) { 2217 v4l2_info(sd, "STDI: not locked\n"); 2218 } else { 2219 uint32_t bl = ((cp_read(sd, 0xb1) & 0x3f) << 8) | cp_read(sd, 0xb2); 2220 uint32_t lcf = ((cp_read(sd, 0xb3) & 0x7) << 8) | cp_read(sd, 0xb4); 2221 uint32_t lcvs = cp_read(sd, 0xb3) >> 3; 2222 uint32_t fcl = ((cp_read(sd, 0xb8) & 0x1f) << 8) | cp_read(sd, 0xb9); 2223 char hs_pol = ((cp_read(sd, 0xb5) & 0x10) ? 2224 ((cp_read(sd, 0xb5) & 0x08) ? '+' : '-') : 'x'); 2225 char vs_pol = ((cp_read(sd, 0xb5) & 0x40) ? 2226 ((cp_read(sd, 0xb5) & 0x20) ? '+' : '-') : 'x'); 2227 v4l2_info(sd, 2228 "STDI: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, fcl = %d, %s, %chsync, %cvsync\n", 2229 lcf, bl, lcvs, fcl, 2230 (cp_read(sd, 0xb1) & 0x40) ? 2231 "interlaced" : "progressive", 2232 hs_pol, vs_pol); 2233 } 2234 if (adv7842_query_dv_timings(sd, &timings)) 2235 v4l2_info(sd, "No video detected\n"); 2236 else 2237 v4l2_print_dv_timings(sd->name, "Detected format: ", 2238 &timings, true); 2239 v4l2_print_dv_timings(sd->name, "Configured format: ", 2240 &state->timings, true); 2241 2242 if (no_cp_signal(sd)) 2243 return 0; 2244 2245 v4l2_info(sd, "-----Color space-----\n"); 2246 v4l2_info(sd, "RGB quantization range ctrl: %s\n", 2247 rgb_quantization_range_txt[state->rgb_quantization_range]); 2248 v4l2_info(sd, "Input color space: %s\n", 2249 input_color_space_txt[reg_io_0x02 >> 4]); 2250 v4l2_info(sd, "Output color space: %s %s, saturator %s\n", 2251 (reg_io_0x02 & 0x02) ? "RGB" : "YCbCr", 2252 (reg_io_0x02 & 0x04) ? "(16-235)" : "(0-255)", 2253 ((reg_io_0x02 & 0x04) ^ (reg_io_0x02 & 0x01)) ? 2254 "enabled" : "disabled"); 2255 v4l2_info(sd, "Color space conversion: %s\n", 2256 csc_coeff_sel_rb[cp_read(sd, 0xf4) >> 4]); 2257 2258 if (!is_digital_input(sd)) 2259 return 0; 2260 2261 v4l2_info(sd, "-----%s status-----\n", is_hdmi(sd) ? "HDMI" : "DVI-D"); 2262 v4l2_info(sd, "HDCP encrypted content: %s\n", 2263 (hdmi_read(sd, 0x05) & 0x40) ? "true" : "false"); 2264 v4l2_info(sd, "HDCP keys read: %s%s\n", 2265 (hdmi_read(sd, 0x04) & 0x20) ? "yes" : "no", 2266 (hdmi_read(sd, 0x04) & 0x10) ? "ERROR" : ""); 2267 if (!is_hdmi(sd)) 2268 return 0; 2269 2270 v4l2_info(sd, "Audio: pll %s, samples %s, %s\n", 2271 audio_pll_locked ? "locked" : "not locked", 2272 audio_sample_packet_detect ? "detected" : "not detected", 2273 audio_mute ? "muted" : "enabled"); 2274 if (audio_pll_locked && audio_sample_packet_detect) { 2275 v4l2_info(sd, "Audio format: %s\n", 2276 (hdmi_read(sd, 0x07) & 0x40) ? "multi-channel" : "stereo"); 2277 } 2278 v4l2_info(sd, "Audio CTS: %u\n", (hdmi_read(sd, 0x5b) << 12) + 2279 (hdmi_read(sd, 0x5c) << 8) + 2280 (hdmi_read(sd, 0x5d) & 0xf0)); 2281 v4l2_info(sd, "Audio N: %u\n", ((hdmi_read(sd, 0x5d) & 0x0f) << 16) + 2282 (hdmi_read(sd, 0x5e) << 8) + 2283 hdmi_read(sd, 0x5f)); 2284 v4l2_info(sd, "AV Mute: %s\n", 2285 (hdmi_read(sd, 0x04) & 0x40) ? "on" : "off"); 2286 v4l2_info(sd, "Deep color mode: %s\n", 2287 deep_color_mode_txt[hdmi_read(sd, 0x0b) >> 6]); 2288 2289 print_avi_infoframe(sd); 2290 return 0; 2291 } 2292 2293 static int adv7842_log_status(struct v4l2_subdev *sd) 2294 { 2295 struct adv7842_state *state = to_state(sd); 2296 2297 if (state->mode == ADV7842_MODE_SDP) 2298 return adv7842_sdp_log_status(sd); 2299 return adv7842_cp_log_status(sd); 2300 } 2301 2302 static int adv7842_querystd(struct v4l2_subdev *sd, v4l2_std_id *std) 2303 { 2304 struct adv7842_state *state = to_state(sd); 2305 2306 v4l2_dbg(1, debug, sd, "%s:\n", __func__); 2307 2308 if (state->mode != ADV7842_MODE_SDP) 2309 return -ENODATA; 2310 2311 if (!(sdp_read(sd, 0x5A) & 0x01)) { 2312 *std = 0; 2313 v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__); 2314 return 0; 2315 } 2316 2317 switch (sdp_read(sd, 0x52) & 0x0f) { 2318 case 0: 2319 /* NTSC-M/J */ 2320 *std &= V4L2_STD_NTSC; 2321 break; 2322 case 2: 2323 /* NTSC-443 */ 2324 *std &= V4L2_STD_NTSC_443; 2325 break; 2326 case 3: 2327 /* 60HzSECAM */ 2328 *std &= V4L2_STD_SECAM; 2329 break; 2330 case 4: 2331 /* PAL-M */ 2332 *std &= V4L2_STD_PAL_M; 2333 break; 2334 case 6: 2335 /* PAL-60 */ 2336 *std &= V4L2_STD_PAL_60; 2337 break; 2338 case 0xc: 2339 /* PAL-CombN */ 2340 *std &= V4L2_STD_PAL_Nc; 2341 break; 2342 case 0xe: 2343 /* PAL-BGHID */ 2344 *std &= V4L2_STD_PAL; 2345 break; 2346 case 0xf: 2347 /* SECAM */ 2348 *std &= V4L2_STD_SECAM; 2349 break; 2350 default: 2351 *std &= V4L2_STD_ALL; 2352 break; 2353 } 2354 return 0; 2355 } 2356 2357 static int adv7842_s_std(struct v4l2_subdev *sd, v4l2_std_id norm) 2358 { 2359 struct adv7842_state *state = to_state(sd); 2360 2361 v4l2_dbg(1, debug, sd, "%s:\n", __func__); 2362 2363 if (state->mode != ADV7842_MODE_SDP) 2364 return -ENODATA; 2365 2366 if (norm & V4L2_STD_ALL) { 2367 state->norm = norm; 2368 return 0; 2369 } 2370 return -EINVAL; 2371 } 2372 2373 static int adv7842_g_std(struct v4l2_subdev *sd, v4l2_std_id *norm) 2374 { 2375 struct adv7842_state *state = to_state(sd); 2376 2377 v4l2_dbg(1, debug, sd, "%s:\n", __func__); 2378 2379 if (state->mode != ADV7842_MODE_SDP) 2380 return -ENODATA; 2381 2382 *norm = state->norm; 2383 return 0; 2384 } 2385 2386 /* ----------------------------------------------------------------------- */ 2387 2388 static int adv7842_core_init(struct v4l2_subdev *sd, 2389 const struct adv7842_platform_data *pdata) 2390 { 2391 hdmi_write(sd, 0x48, 2392 (pdata->disable_pwrdnb ? 0x80 : 0) | 2393 (pdata->disable_cable_det_rst ? 0x40 : 0)); 2394 2395 disable_input(sd); 2396 2397 /* power */ 2398 io_write(sd, 0x0c, 0x42); /* Power up part and power down VDP */ 2399 io_write(sd, 0x15, 0x80); /* Power up pads */ 2400 2401 /* video format */ 2402 io_write(sd, 0x02, 2403 pdata->inp_color_space << 4 | 2404 pdata->alt_gamma << 3 | 2405 pdata->op_656_range << 2 | 2406 pdata->rgb_out << 1 | 2407 pdata->alt_data_sat << 0); 2408 io_write(sd, 0x03, pdata->op_format_sel); 2409 io_write_and_or(sd, 0x04, 0x1f, pdata->op_ch_sel << 5); 2410 io_write_and_or(sd, 0x05, 0xf0, pdata->blank_data << 3 | 2411 pdata->insert_av_codes << 2 | 2412 pdata->replicate_av_codes << 1 | 2413 pdata->invert_cbcr << 0); 2414 2415 /* Drive strength */ 2416 io_write_and_or(sd, 0x14, 0xc0, pdata->drive_strength.data<<4 | 2417 pdata->drive_strength.clock<<2 | 2418 pdata->drive_strength.sync); 2419 2420 /* HDMI free run */ 2421 cp_write(sd, 0xba, (pdata->hdmi_free_run_mode << 1) | 0x01); 2422 2423 /* TODO from platform data */ 2424 cp_write(sd, 0x69, 0x14); /* Enable CP CSC */ 2425 io_write(sd, 0x06, 0xa6); /* positive VS and HS and DE */ 2426 cp_write(sd, 0xf3, 0xdc); /* Low threshold to enter/exit free run mode */ 2427 afe_write(sd, 0xb5, 0x01); /* Setting MCLK to 256Fs */ 2428 2429 afe_write(sd, 0x02, pdata->ain_sel); /* Select analog input muxing mode */ 2430 io_write_and_or(sd, 0x30, ~(1 << 4), pdata->output_bus_lsb_to_msb << 4); 2431 2432 sdp_csc_coeff(sd, &pdata->sdp_csc_coeff); 2433 2434 if (pdata->sdp_io_sync.adjust) { 2435 const struct adv7842_sdp_io_sync_adjustment *s = &pdata->sdp_io_sync; 2436 sdp_io_write(sd, 0x94, (s->hs_beg>>8) & 0xf); 2437 sdp_io_write(sd, 0x95, s->hs_beg & 0xff); 2438 sdp_io_write(sd, 0x96, (s->hs_width>>8) & 0xf); 2439 sdp_io_write(sd, 0x97, s->hs_width & 0xff); 2440 sdp_io_write(sd, 0x98, (s->de_beg>>8) & 0xf); 2441 sdp_io_write(sd, 0x99, s->de_beg & 0xff); 2442 sdp_io_write(sd, 0x9a, (s->de_end>>8) & 0xf); 2443 sdp_io_write(sd, 0x9b, s->de_end & 0xff); 2444 } 2445 2446 /* todo, improve settings for sdram */ 2447 if (pdata->sd_ram_size >= 128) { 2448 sdp_write(sd, 0x12, 0x0d); /* Frame TBC,3D comb enabled */ 2449 if (pdata->sd_ram_ddr) { 2450 /* SDP setup for the AD eval board */ 2451 sdp_io_write(sd, 0x6f, 0x00); /* DDR mode */ 2452 sdp_io_write(sd, 0x75, 0x0a); /* 128 MB memory size */ 2453 sdp_io_write(sd, 0x7a, 0xa5); /* Timing Adjustment */ 2454 sdp_io_write(sd, 0x7b, 0x8f); /* Timing Adjustment */ 2455 sdp_io_write(sd, 0x60, 0x01); /* SDRAM reset */ 2456 } else { 2457 sdp_io_write(sd, 0x75, 0x0a); /* 64 MB memory size ?*/ 2458 sdp_io_write(sd, 0x74, 0x00); /* must be zero for sdr sdram */ 2459 sdp_io_write(sd, 0x79, 0x33); /* CAS latency to 3, 2460 depends on memory */ 2461 sdp_io_write(sd, 0x6f, 0x01); /* SDR mode */ 2462 sdp_io_write(sd, 0x7a, 0xa5); /* Timing Adjustment */ 2463 sdp_io_write(sd, 0x7b, 0x8f); /* Timing Adjustment */ 2464 sdp_io_write(sd, 0x60, 0x01); /* SDRAM reset */ 2465 } 2466 } else { 2467 /* 2468 * Manual UG-214, rev 0 is bit confusing on this bit 2469 * but a '1' disables any signal if the Ram is active. 2470 */ 2471 sdp_io_write(sd, 0x29, 0x10); /* Tristate memory interface */ 2472 } 2473 2474 select_input(sd, pdata->vid_std_select); 2475 2476 enable_input(sd); 2477 2478 /* disable I2C access to internal EDID ram from HDMI DDC ports */ 2479 rep_write_and_or(sd, 0x77, 0xf3, 0x00); 2480 2481 hdmi_write(sd, 0x69, 0xa3); /* HPA manual */ 2482 /* HPA disable on port A and B */ 2483 io_write_and_or(sd, 0x20, 0xcf, 0x00); 2484 2485 /* LLC */ 2486 /* Set phase to 16. TODO: get this from platform_data */ 2487 io_write(sd, 0x19, 0x90); 2488 io_write(sd, 0x33, 0x40); 2489 2490 /* interrupts */ 2491 io_write(sd, 0x40, 0xe2); /* Configure INT1 */ 2492 2493 adv7842_irq_enable(sd, true); 2494 2495 return v4l2_ctrl_handler_setup(sd->ctrl_handler); 2496 } 2497 2498 /* ----------------------------------------------------------------------- */ 2499 2500 static int adv7842_ddr_ram_test(struct v4l2_subdev *sd) 2501 { 2502 /* 2503 * From ADV784x external Memory test.pdf 2504 * 2505 * Reset must just been performed before running test. 2506 * Recommended to reset after test. 2507 */ 2508 int i; 2509 int pass = 0; 2510 int fail = 0; 2511 int complete = 0; 2512 2513 io_write(sd, 0x00, 0x01); /* Program SDP 4x1 */ 2514 io_write(sd, 0x01, 0x00); /* Program SDP mode */ 2515 afe_write(sd, 0x80, 0x92); /* SDP Recommeneded Write */ 2516 afe_write(sd, 0x9B, 0x01); /* SDP Recommeneded Write ADV7844ES1 */ 2517 afe_write(sd, 0x9C, 0x60); /* SDP Recommeneded Write ADV7844ES1 */ 2518 afe_write(sd, 0x9E, 0x02); /* SDP Recommeneded Write ADV7844ES1 */ 2519 afe_write(sd, 0xA0, 0x0B); /* SDP Recommeneded Write ADV7844ES1 */ 2520 afe_write(sd, 0xC3, 0x02); /* Memory BIST Initialisation */ 2521 io_write(sd, 0x0C, 0x40); /* Power up ADV7844 */ 2522 io_write(sd, 0x15, 0xBA); /* Enable outputs */ 2523 sdp_write(sd, 0x12, 0x00); /* Disable 3D comb, Frame TBC & 3DNR */ 2524 io_write(sd, 0xFF, 0x04); /* Reset memory controller */ 2525 2526 mdelay(5); 2527 2528 sdp_write(sd, 0x12, 0x00); /* Disable 3D Comb, Frame TBC & 3DNR */ 2529 sdp_io_write(sd, 0x2A, 0x01); /* Memory BIST Initialisation */ 2530 sdp_io_write(sd, 0x7c, 0x19); /* Memory BIST Initialisation */ 2531 sdp_io_write(sd, 0x80, 0x87); /* Memory BIST Initialisation */ 2532 sdp_io_write(sd, 0x81, 0x4a); /* Memory BIST Initialisation */ 2533 sdp_io_write(sd, 0x82, 0x2c); /* Memory BIST Initialisation */ 2534 sdp_io_write(sd, 0x83, 0x0e); /* Memory BIST Initialisation */ 2535 sdp_io_write(sd, 0x84, 0x94); /* Memory BIST Initialisation */ 2536 sdp_io_write(sd, 0x85, 0x62); /* Memory BIST Initialisation */ 2537 sdp_io_write(sd, 0x7d, 0x00); /* Memory BIST Initialisation */ 2538 sdp_io_write(sd, 0x7e, 0x1a); /* Memory BIST Initialisation */ 2539 2540 mdelay(5); 2541 2542 sdp_io_write(sd, 0xd9, 0xd5); /* Enable BIST Test */ 2543 sdp_write(sd, 0x12, 0x05); /* Enable FRAME TBC & 3D COMB */ 2544 2545 mdelay(20); 2546 2547 for (i = 0; i < 10; i++) { 2548 u8 result = sdp_io_read(sd, 0xdb); 2549 if (result & 0x10) { 2550 complete++; 2551 if (result & 0x20) 2552 fail++; 2553 else 2554 pass++; 2555 } 2556 mdelay(20); 2557 } 2558 2559 v4l2_dbg(1, debug, sd, 2560 "Ram Test: completed %d of %d: pass %d, fail %d\n", 2561 complete, i, pass, fail); 2562 2563 if (!complete || fail) 2564 return -EIO; 2565 return 0; 2566 } 2567 2568 static void adv7842_rewrite_i2c_addresses(struct v4l2_subdev *sd, 2569 struct adv7842_platform_data *pdata) 2570 { 2571 io_write(sd, 0xf1, pdata->i2c_sdp << 1); 2572 io_write(sd, 0xf2, pdata->i2c_sdp_io << 1); 2573 io_write(sd, 0xf3, pdata->i2c_avlink << 1); 2574 io_write(sd, 0xf4, pdata->i2c_cec << 1); 2575 io_write(sd, 0xf5, pdata->i2c_infoframe << 1); 2576 2577 io_write(sd, 0xf8, pdata->i2c_afe << 1); 2578 io_write(sd, 0xf9, pdata->i2c_repeater << 1); 2579 io_write(sd, 0xfa, pdata->i2c_edid << 1); 2580 io_write(sd, 0xfb, pdata->i2c_hdmi << 1); 2581 2582 io_write(sd, 0xfd, pdata->i2c_cp << 1); 2583 io_write(sd, 0xfe, pdata->i2c_vdp << 1); 2584 } 2585 2586 static int adv7842_command_ram_test(struct v4l2_subdev *sd) 2587 { 2588 struct i2c_client *client = v4l2_get_subdevdata(sd); 2589 struct adv7842_state *state = to_state(sd); 2590 struct adv7842_platform_data *pdata = client->dev.platform_data; 2591 int ret = 0; 2592 2593 if (!pdata) 2594 return -ENODEV; 2595 2596 if (!pdata->sd_ram_size || !pdata->sd_ram_ddr) { 2597 v4l2_info(sd, "no sdram or no ddr sdram\n"); 2598 return -EINVAL; 2599 } 2600 2601 main_reset(sd); 2602 2603 adv7842_rewrite_i2c_addresses(sd, pdata); 2604 2605 /* run ram test */ 2606 ret = adv7842_ddr_ram_test(sd); 2607 2608 main_reset(sd); 2609 2610 adv7842_rewrite_i2c_addresses(sd, pdata); 2611 2612 /* and re-init chip and state */ 2613 adv7842_core_init(sd, pdata); 2614 2615 disable_input(sd); 2616 2617 select_input(sd, state->vid_std_select); 2618 2619 enable_input(sd); 2620 2621 adv7842_s_dv_timings(sd, &state->timings); 2622 2623 edid_write_vga_segment(sd); 2624 edid_write_hdmi_segment(sd, 0); 2625 edid_write_hdmi_segment(sd, 1); 2626 2627 return ret; 2628 } 2629 2630 static long adv7842_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg) 2631 { 2632 switch (cmd) { 2633 case ADV7842_CMD_RAM_TEST: 2634 return adv7842_command_ram_test(sd); 2635 } 2636 return -ENOTTY; 2637 } 2638 2639 /* ----------------------------------------------------------------------- */ 2640 2641 static const struct v4l2_ctrl_ops adv7842_ctrl_ops = { 2642 .s_ctrl = adv7842_s_ctrl, 2643 }; 2644 2645 static const struct v4l2_subdev_core_ops adv7842_core_ops = { 2646 .log_status = adv7842_log_status, 2647 .g_std = adv7842_g_std, 2648 .s_std = adv7842_s_std, 2649 .ioctl = adv7842_ioctl, 2650 .interrupt_service_routine = adv7842_isr, 2651 #ifdef CONFIG_VIDEO_ADV_DEBUG 2652 .g_register = adv7842_g_register, 2653 .s_register = adv7842_s_register, 2654 #endif 2655 }; 2656 2657 static const struct v4l2_subdev_video_ops adv7842_video_ops = { 2658 .s_routing = adv7842_s_routing, 2659 .querystd = adv7842_querystd, 2660 .g_input_status = adv7842_g_input_status, 2661 .s_dv_timings = adv7842_s_dv_timings, 2662 .g_dv_timings = adv7842_g_dv_timings, 2663 .query_dv_timings = adv7842_query_dv_timings, 2664 .enum_dv_timings = adv7842_enum_dv_timings, 2665 .dv_timings_cap = adv7842_dv_timings_cap, 2666 .enum_mbus_fmt = adv7842_enum_mbus_fmt, 2667 .g_mbus_fmt = adv7842_g_mbus_fmt, 2668 .try_mbus_fmt = adv7842_g_mbus_fmt, 2669 .s_mbus_fmt = adv7842_g_mbus_fmt, 2670 }; 2671 2672 static const struct v4l2_subdev_pad_ops adv7842_pad_ops = { 2673 .set_edid = adv7842_set_edid, 2674 }; 2675 2676 static const struct v4l2_subdev_ops adv7842_ops = { 2677 .core = &adv7842_core_ops, 2678 .video = &adv7842_video_ops, 2679 .pad = &adv7842_pad_ops, 2680 }; 2681 2682 /* -------------------------- custom ctrls ---------------------------------- */ 2683 2684 static const struct v4l2_ctrl_config adv7842_ctrl_analog_sampling_phase = { 2685 .ops = &adv7842_ctrl_ops, 2686 .id = V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE, 2687 .name = "Analog Sampling Phase", 2688 .type = V4L2_CTRL_TYPE_INTEGER, 2689 .min = 0, 2690 .max = 0x1f, 2691 .step = 1, 2692 .def = 0, 2693 }; 2694 2695 static const struct v4l2_ctrl_config adv7842_ctrl_free_run_color_manual = { 2696 .ops = &adv7842_ctrl_ops, 2697 .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL, 2698 .name = "Free Running Color, Manual", 2699 .type = V4L2_CTRL_TYPE_BOOLEAN, 2700 .max = 1, 2701 .step = 1, 2702 .def = 1, 2703 }; 2704 2705 static const struct v4l2_ctrl_config adv7842_ctrl_free_run_color = { 2706 .ops = &adv7842_ctrl_ops, 2707 .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR, 2708 .name = "Free Running Color", 2709 .type = V4L2_CTRL_TYPE_INTEGER, 2710 .max = 0xffffff, 2711 .step = 0x1, 2712 }; 2713 2714 2715 static void adv7842_unregister_clients(struct adv7842_state *state) 2716 { 2717 if (state->i2c_avlink) 2718 i2c_unregister_device(state->i2c_avlink); 2719 if (state->i2c_cec) 2720 i2c_unregister_device(state->i2c_cec); 2721 if (state->i2c_infoframe) 2722 i2c_unregister_device(state->i2c_infoframe); 2723 if (state->i2c_sdp_io) 2724 i2c_unregister_device(state->i2c_sdp_io); 2725 if (state->i2c_sdp) 2726 i2c_unregister_device(state->i2c_sdp); 2727 if (state->i2c_afe) 2728 i2c_unregister_device(state->i2c_afe); 2729 if (state->i2c_repeater) 2730 i2c_unregister_device(state->i2c_repeater); 2731 if (state->i2c_edid) 2732 i2c_unregister_device(state->i2c_edid); 2733 if (state->i2c_hdmi) 2734 i2c_unregister_device(state->i2c_hdmi); 2735 if (state->i2c_cp) 2736 i2c_unregister_device(state->i2c_cp); 2737 if (state->i2c_vdp) 2738 i2c_unregister_device(state->i2c_vdp); 2739 } 2740 2741 static struct i2c_client *adv7842_dummy_client(struct v4l2_subdev *sd, 2742 u8 addr, u8 io_reg) 2743 { 2744 struct i2c_client *client = v4l2_get_subdevdata(sd); 2745 2746 io_write(sd, io_reg, addr << 1); 2747 return i2c_new_dummy(client->adapter, io_read(sd, io_reg) >> 1); 2748 } 2749 2750 static int adv7842_probe(struct i2c_client *client, 2751 const struct i2c_device_id *id) 2752 { 2753 struct adv7842_state *state; 2754 struct adv7842_platform_data *pdata = client->dev.platform_data; 2755 struct v4l2_ctrl_handler *hdl; 2756 struct v4l2_subdev *sd; 2757 u16 rev; 2758 int err; 2759 2760 /* Check if the adapter supports the needed features */ 2761 if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA)) 2762 return -EIO; 2763 2764 v4l_dbg(1, debug, client, "detecting adv7842 client on address 0x%x\n", 2765 client->addr << 1); 2766 2767 if (!pdata) { 2768 v4l_err(client, "No platform data!\n"); 2769 return -ENODEV; 2770 } 2771 2772 state = devm_kzalloc(&client->dev, sizeof(struct adv7842_state), GFP_KERNEL); 2773 if (!state) { 2774 v4l_err(client, "Could not allocate adv7842_state memory!\n"); 2775 return -ENOMEM; 2776 } 2777 2778 sd = &state->sd; 2779 v4l2_i2c_subdev_init(sd, client, &adv7842_ops); 2780 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; 2781 state->connector_hdmi = pdata->connector_hdmi; 2782 state->mode = pdata->mode; 2783 2784 state->hdmi_port_a = true; 2785 2786 /* i2c access to adv7842? */ 2787 rev = adv_smbus_read_byte_data_check(client, 0xea, false) << 8 | 2788 adv_smbus_read_byte_data_check(client, 0xeb, false); 2789 if (rev != 0x2012) { 2790 v4l2_info(sd, "got rev=0x%04x on first read attempt\n", rev); 2791 rev = adv_smbus_read_byte_data_check(client, 0xea, false) << 8 | 2792 adv_smbus_read_byte_data_check(client, 0xeb, false); 2793 } 2794 if (rev != 0x2012) { 2795 v4l2_info(sd, "not an adv7842 on address 0x%x (rev=0x%04x)\n", 2796 client->addr << 1, rev); 2797 return -ENODEV; 2798 } 2799 2800 if (pdata->chip_reset) 2801 main_reset(sd); 2802 2803 /* control handlers */ 2804 hdl = &state->hdl; 2805 v4l2_ctrl_handler_init(hdl, 6); 2806 2807 /* add in ascending ID order */ 2808 v4l2_ctrl_new_std(hdl, &adv7842_ctrl_ops, 2809 V4L2_CID_BRIGHTNESS, -128, 127, 1, 0); 2810 v4l2_ctrl_new_std(hdl, &adv7842_ctrl_ops, 2811 V4L2_CID_CONTRAST, 0, 255, 1, 128); 2812 v4l2_ctrl_new_std(hdl, &adv7842_ctrl_ops, 2813 V4L2_CID_SATURATION, 0, 255, 1, 128); 2814 v4l2_ctrl_new_std(hdl, &adv7842_ctrl_ops, 2815 V4L2_CID_HUE, 0, 128, 1, 0); 2816 2817 /* custom controls */ 2818 state->detect_tx_5v_ctrl = v4l2_ctrl_new_std(hdl, NULL, 2819 V4L2_CID_DV_RX_POWER_PRESENT, 0, 3, 0, 0); 2820 state->analog_sampling_phase_ctrl = v4l2_ctrl_new_custom(hdl, 2821 &adv7842_ctrl_analog_sampling_phase, NULL); 2822 state->free_run_color_ctrl_manual = v4l2_ctrl_new_custom(hdl, 2823 &adv7842_ctrl_free_run_color_manual, NULL); 2824 state->free_run_color_ctrl = v4l2_ctrl_new_custom(hdl, 2825 &adv7842_ctrl_free_run_color, NULL); 2826 state->rgb_quantization_range_ctrl = 2827 v4l2_ctrl_new_std_menu(hdl, &adv7842_ctrl_ops, 2828 V4L2_CID_DV_RX_RGB_RANGE, V4L2_DV_RGB_RANGE_FULL, 2829 0, V4L2_DV_RGB_RANGE_AUTO); 2830 sd->ctrl_handler = hdl; 2831 if (hdl->error) { 2832 err = hdl->error; 2833 goto err_hdl; 2834 } 2835 state->detect_tx_5v_ctrl->is_private = true; 2836 state->rgb_quantization_range_ctrl->is_private = true; 2837 state->analog_sampling_phase_ctrl->is_private = true; 2838 state->free_run_color_ctrl_manual->is_private = true; 2839 state->free_run_color_ctrl->is_private = true; 2840 2841 if (adv7842_s_detect_tx_5v_ctrl(sd)) { 2842 err = -ENODEV; 2843 goto err_hdl; 2844 } 2845 2846 state->i2c_avlink = adv7842_dummy_client(sd, pdata->i2c_avlink, 0xf3); 2847 state->i2c_cec = adv7842_dummy_client(sd, pdata->i2c_cec, 0xf4); 2848 state->i2c_infoframe = adv7842_dummy_client(sd, pdata->i2c_infoframe, 0xf5); 2849 state->i2c_sdp_io = adv7842_dummy_client(sd, pdata->i2c_sdp_io, 0xf2); 2850 state->i2c_sdp = adv7842_dummy_client(sd, pdata->i2c_sdp, 0xf1); 2851 state->i2c_afe = adv7842_dummy_client(sd, pdata->i2c_afe, 0xf8); 2852 state->i2c_repeater = adv7842_dummy_client(sd, pdata->i2c_repeater, 0xf9); 2853 state->i2c_edid = adv7842_dummy_client(sd, pdata->i2c_edid, 0xfa); 2854 state->i2c_hdmi = adv7842_dummy_client(sd, pdata->i2c_hdmi, 0xfb); 2855 state->i2c_cp = adv7842_dummy_client(sd, pdata->i2c_cp, 0xfd); 2856 state->i2c_vdp = adv7842_dummy_client(sd, pdata->i2c_vdp, 0xfe); 2857 if (!state->i2c_avlink || !state->i2c_cec || !state->i2c_infoframe || 2858 !state->i2c_sdp_io || !state->i2c_sdp || !state->i2c_afe || 2859 !state->i2c_repeater || !state->i2c_edid || !state->i2c_hdmi || 2860 !state->i2c_cp || !state->i2c_vdp) { 2861 err = -ENOMEM; 2862 v4l2_err(sd, "failed to create all i2c clients\n"); 2863 goto err_i2c; 2864 } 2865 2866 /* work queues */ 2867 state->work_queues = create_singlethread_workqueue(client->name); 2868 if (!state->work_queues) { 2869 v4l2_err(sd, "Could not create work queue\n"); 2870 err = -ENOMEM; 2871 goto err_i2c; 2872 } 2873 2874 INIT_DELAYED_WORK(&state->delayed_work_enable_hotplug, 2875 adv7842_delayed_work_enable_hotplug); 2876 2877 state->pad.flags = MEDIA_PAD_FL_SOURCE; 2878 err = media_entity_init(&sd->entity, 1, &state->pad, 0); 2879 if (err) 2880 goto err_work_queues; 2881 2882 err = adv7842_core_init(sd, pdata); 2883 if (err) 2884 goto err_entity; 2885 2886 v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name, 2887 client->addr << 1, client->adapter->name); 2888 return 0; 2889 2890 err_entity: 2891 media_entity_cleanup(&sd->entity); 2892 err_work_queues: 2893 cancel_delayed_work(&state->delayed_work_enable_hotplug); 2894 destroy_workqueue(state->work_queues); 2895 err_i2c: 2896 adv7842_unregister_clients(state); 2897 err_hdl: 2898 v4l2_ctrl_handler_free(hdl); 2899 return err; 2900 } 2901 2902 /* ----------------------------------------------------------------------- */ 2903 2904 static int adv7842_remove(struct i2c_client *client) 2905 { 2906 struct v4l2_subdev *sd = i2c_get_clientdata(client); 2907 struct adv7842_state *state = to_state(sd); 2908 2909 adv7842_irq_enable(sd, false); 2910 2911 cancel_delayed_work(&state->delayed_work_enable_hotplug); 2912 destroy_workqueue(state->work_queues); 2913 v4l2_device_unregister_subdev(sd); 2914 media_entity_cleanup(&sd->entity); 2915 adv7842_unregister_clients(to_state(sd)); 2916 v4l2_ctrl_handler_free(sd->ctrl_handler); 2917 return 0; 2918 } 2919 2920 /* ----------------------------------------------------------------------- */ 2921 2922 static struct i2c_device_id adv7842_id[] = { 2923 { "adv7842", 0 }, 2924 { } 2925 }; 2926 MODULE_DEVICE_TABLE(i2c, adv7842_id); 2927 2928 /* ----------------------------------------------------------------------- */ 2929 2930 static struct i2c_driver adv7842_driver = { 2931 .driver = { 2932 .owner = THIS_MODULE, 2933 .name = "adv7842", 2934 }, 2935 .probe = adv7842_probe, 2936 .remove = adv7842_remove, 2937 .id_table = adv7842_id, 2938 }; 2939 2940 module_i2c_driver(adv7842_driver); 2941