1 /* 2 * adv7842 - Analog Devices ADV7842 video decoder driver 3 * 4 * Copyright 2013 Cisco Systems, Inc. and/or its affiliates. All rights reserved. 5 * 6 * This program is free software; you may redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; version 2 of the License. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 11 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 12 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 13 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 14 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 15 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 16 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 17 * SOFTWARE. 18 * 19 */ 20 21 /* 22 * References (c = chapter, p = page): 23 * REF_01 - Analog devices, ADV7842, 24 * Register Settings Recommendations, Rev. 1.9, April 2011 25 * REF_02 - Analog devices, Software User Guide, UG-206, 26 * ADV7842 I2C Register Maps, Rev. 0, November 2010 27 * REF_03 - Analog devices, Hardware User Guide, UG-214, 28 * ADV7842 Fast Switching 2:1 HDMI 1.4 Receiver with 3D-Comb 29 * Decoder and Digitizer , Rev. 0, January 2011 30 */ 31 32 33 #include <linux/kernel.h> 34 #include <linux/module.h> 35 #include <linux/slab.h> 36 #include <linux/i2c.h> 37 #include <linux/delay.h> 38 #include <linux/videodev2.h> 39 #include <linux/workqueue.h> 40 #include <linux/v4l2-dv-timings.h> 41 #include <linux/hdmi.h> 42 #include <media/v4l2-device.h> 43 #include <media/v4l2-event.h> 44 #include <media/v4l2-ctrls.h> 45 #include <media/v4l2-dv-timings.h> 46 #include <media/i2c/adv7842.h> 47 48 static int debug; 49 module_param(debug, int, 0644); 50 MODULE_PARM_DESC(debug, "debug level (0-2)"); 51 52 MODULE_DESCRIPTION("Analog Devices ADV7842 video decoder driver"); 53 MODULE_AUTHOR("Hans Verkuil <hans.verkuil@cisco.com>"); 54 MODULE_AUTHOR("Martin Bugge <marbugge@cisco.com>"); 55 MODULE_LICENSE("GPL"); 56 57 /* ADV7842 system clock frequency */ 58 #define ADV7842_fsc (28636360) 59 60 #define ADV7842_RGB_OUT (1 << 1) 61 62 #define ADV7842_OP_FORMAT_SEL_8BIT (0 << 0) 63 #define ADV7842_OP_FORMAT_SEL_10BIT (1 << 0) 64 #define ADV7842_OP_FORMAT_SEL_12BIT (2 << 0) 65 66 #define ADV7842_OP_MODE_SEL_SDR_422 (0 << 5) 67 #define ADV7842_OP_MODE_SEL_DDR_422 (1 << 5) 68 #define ADV7842_OP_MODE_SEL_SDR_444 (2 << 5) 69 #define ADV7842_OP_MODE_SEL_DDR_444 (3 << 5) 70 #define ADV7842_OP_MODE_SEL_SDR_422_2X (4 << 5) 71 #define ADV7842_OP_MODE_SEL_ADI_CM (5 << 5) 72 73 #define ADV7842_OP_CH_SEL_GBR (0 << 5) 74 #define ADV7842_OP_CH_SEL_GRB (1 << 5) 75 #define ADV7842_OP_CH_SEL_BGR (2 << 5) 76 #define ADV7842_OP_CH_SEL_RGB (3 << 5) 77 #define ADV7842_OP_CH_SEL_BRG (4 << 5) 78 #define ADV7842_OP_CH_SEL_RBG (5 << 5) 79 80 #define ADV7842_OP_SWAP_CB_CR (1 << 0) 81 82 /* 83 ********************************************************************** 84 * 85 * Arrays with configuration parameters for the ADV7842 86 * 87 ********************************************************************** 88 */ 89 90 struct adv7842_format_info { 91 u32 code; 92 u8 op_ch_sel; 93 bool rgb_out; 94 bool swap_cb_cr; 95 u8 op_format_sel; 96 }; 97 98 struct adv7842_state { 99 struct adv7842_platform_data pdata; 100 struct v4l2_subdev sd; 101 struct media_pad pad; 102 struct v4l2_ctrl_handler hdl; 103 enum adv7842_mode mode; 104 struct v4l2_dv_timings timings; 105 enum adv7842_vid_std_select vid_std_select; 106 107 const struct adv7842_format_info *format; 108 109 v4l2_std_id norm; 110 struct { 111 u8 edid[256]; 112 u32 present; 113 } hdmi_edid; 114 struct { 115 u8 edid[256]; 116 u32 present; 117 } vga_edid; 118 struct v4l2_fract aspect_ratio; 119 u32 rgb_quantization_range; 120 bool is_cea_format; 121 struct workqueue_struct *work_queues; 122 struct delayed_work delayed_work_enable_hotplug; 123 bool restart_stdi_once; 124 bool hdmi_port_a; 125 126 /* i2c clients */ 127 struct i2c_client *i2c_sdp_io; 128 struct i2c_client *i2c_sdp; 129 struct i2c_client *i2c_cp; 130 struct i2c_client *i2c_vdp; 131 struct i2c_client *i2c_afe; 132 struct i2c_client *i2c_hdmi; 133 struct i2c_client *i2c_repeater; 134 struct i2c_client *i2c_edid; 135 struct i2c_client *i2c_infoframe; 136 struct i2c_client *i2c_cec; 137 struct i2c_client *i2c_avlink; 138 139 /* controls */ 140 struct v4l2_ctrl *detect_tx_5v_ctrl; 141 struct v4l2_ctrl *analog_sampling_phase_ctrl; 142 struct v4l2_ctrl *free_run_color_ctrl_manual; 143 struct v4l2_ctrl *free_run_color_ctrl; 144 struct v4l2_ctrl *rgb_quantization_range_ctrl; 145 }; 146 147 /* Unsupported timings. This device cannot support 720p30. */ 148 static const struct v4l2_dv_timings adv7842_timings_exceptions[] = { 149 V4L2_DV_BT_CEA_1280X720P30, 150 { } 151 }; 152 153 static bool adv7842_check_dv_timings(const struct v4l2_dv_timings *t, void *hdl) 154 { 155 int i; 156 157 for (i = 0; adv7842_timings_exceptions[i].bt.width; i++) 158 if (v4l2_match_dv_timings(t, adv7842_timings_exceptions + i, 0, false)) 159 return false; 160 return true; 161 } 162 163 struct adv7842_video_standards { 164 struct v4l2_dv_timings timings; 165 u8 vid_std; 166 u8 v_freq; 167 }; 168 169 /* sorted by number of lines */ 170 static const struct adv7842_video_standards adv7842_prim_mode_comp[] = { 171 /* { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 }, TODO flickering */ 172 { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 }, 173 { V4L2_DV_BT_CEA_1280X720P50, 0x19, 0x01 }, 174 { V4L2_DV_BT_CEA_1280X720P60, 0x19, 0x00 }, 175 { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 }, 176 { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 }, 177 { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 }, 178 { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 }, 179 { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 }, 180 /* TODO add 1920x1080P60_RB (CVT timing) */ 181 { }, 182 }; 183 184 /* sorted by number of lines */ 185 static const struct adv7842_video_standards adv7842_prim_mode_gr[] = { 186 { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 }, 187 { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 }, 188 { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 }, 189 { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 }, 190 { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 }, 191 { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 }, 192 { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 }, 193 { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 }, 194 { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 }, 195 { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 }, 196 { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 }, 197 { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 }, 198 { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 }, 199 { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 }, 200 { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 }, 201 { V4L2_DV_BT_DMT_1360X768P60, 0x12, 0x00 }, 202 { V4L2_DV_BT_DMT_1366X768P60, 0x13, 0x00 }, 203 { V4L2_DV_BT_DMT_1400X1050P60, 0x14, 0x00 }, 204 { V4L2_DV_BT_DMT_1400X1050P75, 0x15, 0x00 }, 205 { V4L2_DV_BT_DMT_1600X1200P60, 0x16, 0x00 }, /* TODO not tested */ 206 /* TODO add 1600X1200P60_RB (not a DMT timing) */ 207 { V4L2_DV_BT_DMT_1680X1050P60, 0x18, 0x00 }, 208 { V4L2_DV_BT_DMT_1920X1200P60_RB, 0x19, 0x00 }, /* TODO not tested */ 209 { }, 210 }; 211 212 /* sorted by number of lines */ 213 static const struct adv7842_video_standards adv7842_prim_mode_hdmi_comp[] = { 214 { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 }, 215 { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 }, 216 { V4L2_DV_BT_CEA_1280X720P50, 0x13, 0x01 }, 217 { V4L2_DV_BT_CEA_1280X720P60, 0x13, 0x00 }, 218 { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 }, 219 { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 }, 220 { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 }, 221 { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 }, 222 { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 }, 223 { }, 224 }; 225 226 /* sorted by number of lines */ 227 static const struct adv7842_video_standards adv7842_prim_mode_hdmi_gr[] = { 228 { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 }, 229 { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 }, 230 { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 }, 231 { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 }, 232 { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 }, 233 { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 }, 234 { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 }, 235 { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 }, 236 { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 }, 237 { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 }, 238 { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 }, 239 { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 }, 240 { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 }, 241 { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 }, 242 { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 }, 243 { }, 244 }; 245 246 static const struct v4l2_event adv7842_ev_fmt = { 247 .type = V4L2_EVENT_SOURCE_CHANGE, 248 .u.src_change.changes = V4L2_EVENT_SRC_CH_RESOLUTION, 249 }; 250 251 /* ----------------------------------------------------------------------- */ 252 253 static inline struct adv7842_state *to_state(struct v4l2_subdev *sd) 254 { 255 return container_of(sd, struct adv7842_state, sd); 256 } 257 258 static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl) 259 { 260 return &container_of(ctrl->handler, struct adv7842_state, hdl)->sd; 261 } 262 263 static inline unsigned hblanking(const struct v4l2_bt_timings *t) 264 { 265 return V4L2_DV_BT_BLANKING_WIDTH(t); 266 } 267 268 static inline unsigned htotal(const struct v4l2_bt_timings *t) 269 { 270 return V4L2_DV_BT_FRAME_WIDTH(t); 271 } 272 273 static inline unsigned vblanking(const struct v4l2_bt_timings *t) 274 { 275 return V4L2_DV_BT_BLANKING_HEIGHT(t); 276 } 277 278 static inline unsigned vtotal(const struct v4l2_bt_timings *t) 279 { 280 return V4L2_DV_BT_FRAME_HEIGHT(t); 281 } 282 283 284 /* ----------------------------------------------------------------------- */ 285 286 static s32 adv_smbus_read_byte_data_check(struct i2c_client *client, 287 u8 command, bool check) 288 { 289 union i2c_smbus_data data; 290 291 if (!i2c_smbus_xfer(client->adapter, client->addr, client->flags, 292 I2C_SMBUS_READ, command, 293 I2C_SMBUS_BYTE_DATA, &data)) 294 return data.byte; 295 if (check) 296 v4l_err(client, "error reading %02x, %02x\n", 297 client->addr, command); 298 return -EIO; 299 } 300 301 static s32 adv_smbus_read_byte_data(struct i2c_client *client, u8 command) 302 { 303 int i; 304 305 for (i = 0; i < 3; i++) { 306 int ret = adv_smbus_read_byte_data_check(client, command, true); 307 308 if (ret >= 0) { 309 if (i) 310 v4l_err(client, "read ok after %d retries\n", i); 311 return ret; 312 } 313 } 314 v4l_err(client, "read failed\n"); 315 return -EIO; 316 } 317 318 static s32 adv_smbus_write_byte_data(struct i2c_client *client, 319 u8 command, u8 value) 320 { 321 union i2c_smbus_data data; 322 int err; 323 int i; 324 325 data.byte = value; 326 for (i = 0; i < 3; i++) { 327 err = i2c_smbus_xfer(client->adapter, client->addr, 328 client->flags, 329 I2C_SMBUS_WRITE, command, 330 I2C_SMBUS_BYTE_DATA, &data); 331 if (!err) 332 break; 333 } 334 if (err < 0) 335 v4l_err(client, "error writing %02x, %02x, %02x\n", 336 client->addr, command, value); 337 return err; 338 } 339 340 static void adv_smbus_write_byte_no_check(struct i2c_client *client, 341 u8 command, u8 value) 342 { 343 union i2c_smbus_data data; 344 data.byte = value; 345 346 i2c_smbus_xfer(client->adapter, client->addr, 347 client->flags, 348 I2C_SMBUS_WRITE, command, 349 I2C_SMBUS_BYTE_DATA, &data); 350 } 351 352 static s32 adv_smbus_write_i2c_block_data(struct i2c_client *client, 353 u8 command, unsigned length, const u8 *values) 354 { 355 union i2c_smbus_data data; 356 357 if (length > I2C_SMBUS_BLOCK_MAX) 358 length = I2C_SMBUS_BLOCK_MAX; 359 data.block[0] = length; 360 memcpy(data.block + 1, values, length); 361 return i2c_smbus_xfer(client->adapter, client->addr, client->flags, 362 I2C_SMBUS_WRITE, command, 363 I2C_SMBUS_I2C_BLOCK_DATA, &data); 364 } 365 366 /* ----------------------------------------------------------------------- */ 367 368 static inline int io_read(struct v4l2_subdev *sd, u8 reg) 369 { 370 struct i2c_client *client = v4l2_get_subdevdata(sd); 371 372 return adv_smbus_read_byte_data(client, reg); 373 } 374 375 static inline int io_write(struct v4l2_subdev *sd, u8 reg, u8 val) 376 { 377 struct i2c_client *client = v4l2_get_subdevdata(sd); 378 379 return adv_smbus_write_byte_data(client, reg, val); 380 } 381 382 static inline int io_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) 383 { 384 return io_write(sd, reg, (io_read(sd, reg) & mask) | val); 385 } 386 387 static inline int io_write_clr_set(struct v4l2_subdev *sd, 388 u8 reg, u8 mask, u8 val) 389 { 390 return io_write(sd, reg, (io_read(sd, reg) & ~mask) | val); 391 } 392 393 static inline int avlink_read(struct v4l2_subdev *sd, u8 reg) 394 { 395 struct adv7842_state *state = to_state(sd); 396 397 return adv_smbus_read_byte_data(state->i2c_avlink, reg); 398 } 399 400 static inline int avlink_write(struct v4l2_subdev *sd, u8 reg, u8 val) 401 { 402 struct adv7842_state *state = to_state(sd); 403 404 return adv_smbus_write_byte_data(state->i2c_avlink, reg, val); 405 } 406 407 static inline int cec_read(struct v4l2_subdev *sd, u8 reg) 408 { 409 struct adv7842_state *state = to_state(sd); 410 411 return adv_smbus_read_byte_data(state->i2c_cec, reg); 412 } 413 414 static inline int cec_write(struct v4l2_subdev *sd, u8 reg, u8 val) 415 { 416 struct adv7842_state *state = to_state(sd); 417 418 return adv_smbus_write_byte_data(state->i2c_cec, reg, val); 419 } 420 421 static inline int cec_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) 422 { 423 return cec_write(sd, reg, (cec_read(sd, reg) & mask) | val); 424 } 425 426 static inline int infoframe_read(struct v4l2_subdev *sd, u8 reg) 427 { 428 struct adv7842_state *state = to_state(sd); 429 430 return adv_smbus_read_byte_data(state->i2c_infoframe, reg); 431 } 432 433 static inline int infoframe_write(struct v4l2_subdev *sd, u8 reg, u8 val) 434 { 435 struct adv7842_state *state = to_state(sd); 436 437 return adv_smbus_write_byte_data(state->i2c_infoframe, reg, val); 438 } 439 440 static inline int sdp_io_read(struct v4l2_subdev *sd, u8 reg) 441 { 442 struct adv7842_state *state = to_state(sd); 443 444 return adv_smbus_read_byte_data(state->i2c_sdp_io, reg); 445 } 446 447 static inline int sdp_io_write(struct v4l2_subdev *sd, u8 reg, u8 val) 448 { 449 struct adv7842_state *state = to_state(sd); 450 451 return adv_smbus_write_byte_data(state->i2c_sdp_io, reg, val); 452 } 453 454 static inline int sdp_io_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) 455 { 456 return sdp_io_write(sd, reg, (sdp_io_read(sd, reg) & mask) | val); 457 } 458 459 static inline int sdp_read(struct v4l2_subdev *sd, u8 reg) 460 { 461 struct adv7842_state *state = to_state(sd); 462 463 return adv_smbus_read_byte_data(state->i2c_sdp, reg); 464 } 465 466 static inline int sdp_write(struct v4l2_subdev *sd, u8 reg, u8 val) 467 { 468 struct adv7842_state *state = to_state(sd); 469 470 return adv_smbus_write_byte_data(state->i2c_sdp, reg, val); 471 } 472 473 static inline int sdp_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) 474 { 475 return sdp_write(sd, reg, (sdp_read(sd, reg) & mask) | val); 476 } 477 478 static inline int afe_read(struct v4l2_subdev *sd, u8 reg) 479 { 480 struct adv7842_state *state = to_state(sd); 481 482 return adv_smbus_read_byte_data(state->i2c_afe, reg); 483 } 484 485 static inline int afe_write(struct v4l2_subdev *sd, u8 reg, u8 val) 486 { 487 struct adv7842_state *state = to_state(sd); 488 489 return adv_smbus_write_byte_data(state->i2c_afe, reg, val); 490 } 491 492 static inline int afe_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) 493 { 494 return afe_write(sd, reg, (afe_read(sd, reg) & mask) | val); 495 } 496 497 static inline int rep_read(struct v4l2_subdev *sd, u8 reg) 498 { 499 struct adv7842_state *state = to_state(sd); 500 501 return adv_smbus_read_byte_data(state->i2c_repeater, reg); 502 } 503 504 static inline int rep_write(struct v4l2_subdev *sd, u8 reg, u8 val) 505 { 506 struct adv7842_state *state = to_state(sd); 507 508 return adv_smbus_write_byte_data(state->i2c_repeater, reg, val); 509 } 510 511 static inline int rep_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) 512 { 513 return rep_write(sd, reg, (rep_read(sd, reg) & mask) | val); 514 } 515 516 static inline int edid_read(struct v4l2_subdev *sd, u8 reg) 517 { 518 struct adv7842_state *state = to_state(sd); 519 520 return adv_smbus_read_byte_data(state->i2c_edid, reg); 521 } 522 523 static inline int edid_write(struct v4l2_subdev *sd, u8 reg, u8 val) 524 { 525 struct adv7842_state *state = to_state(sd); 526 527 return adv_smbus_write_byte_data(state->i2c_edid, reg, val); 528 } 529 530 static inline int hdmi_read(struct v4l2_subdev *sd, u8 reg) 531 { 532 struct adv7842_state *state = to_state(sd); 533 534 return adv_smbus_read_byte_data(state->i2c_hdmi, reg); 535 } 536 537 static inline int hdmi_write(struct v4l2_subdev *sd, u8 reg, u8 val) 538 { 539 struct adv7842_state *state = to_state(sd); 540 541 return adv_smbus_write_byte_data(state->i2c_hdmi, reg, val); 542 } 543 544 static inline int hdmi_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) 545 { 546 return hdmi_write(sd, reg, (hdmi_read(sd, reg) & mask) | val); 547 } 548 549 static inline int cp_read(struct v4l2_subdev *sd, u8 reg) 550 { 551 struct adv7842_state *state = to_state(sd); 552 553 return adv_smbus_read_byte_data(state->i2c_cp, reg); 554 } 555 556 static inline int cp_write(struct v4l2_subdev *sd, u8 reg, u8 val) 557 { 558 struct adv7842_state *state = to_state(sd); 559 560 return adv_smbus_write_byte_data(state->i2c_cp, reg, val); 561 } 562 563 static inline int cp_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) 564 { 565 return cp_write(sd, reg, (cp_read(sd, reg) & mask) | val); 566 } 567 568 static inline int vdp_read(struct v4l2_subdev *sd, u8 reg) 569 { 570 struct adv7842_state *state = to_state(sd); 571 572 return adv_smbus_read_byte_data(state->i2c_vdp, reg); 573 } 574 575 static inline int vdp_write(struct v4l2_subdev *sd, u8 reg, u8 val) 576 { 577 struct adv7842_state *state = to_state(sd); 578 579 return adv_smbus_write_byte_data(state->i2c_vdp, reg, val); 580 } 581 582 static void main_reset(struct v4l2_subdev *sd) 583 { 584 struct i2c_client *client = v4l2_get_subdevdata(sd); 585 586 v4l2_dbg(1, debug, sd, "%s:\n", __func__); 587 588 adv_smbus_write_byte_no_check(client, 0xff, 0x80); 589 590 mdelay(5); 591 } 592 593 /* ----------------------------------------------------------------------------- 594 * Format helpers 595 */ 596 597 static const struct adv7842_format_info adv7842_formats[] = { 598 { MEDIA_BUS_FMT_RGB888_1X24, ADV7842_OP_CH_SEL_RGB, true, false, 599 ADV7842_OP_MODE_SEL_SDR_444 | ADV7842_OP_FORMAT_SEL_8BIT }, 600 { MEDIA_BUS_FMT_YUYV8_2X8, ADV7842_OP_CH_SEL_RGB, false, false, 601 ADV7842_OP_MODE_SEL_SDR_422 | ADV7842_OP_FORMAT_SEL_8BIT }, 602 { MEDIA_BUS_FMT_YVYU8_2X8, ADV7842_OP_CH_SEL_RGB, false, true, 603 ADV7842_OP_MODE_SEL_SDR_422 | ADV7842_OP_FORMAT_SEL_8BIT }, 604 { MEDIA_BUS_FMT_YUYV10_2X10, ADV7842_OP_CH_SEL_RGB, false, false, 605 ADV7842_OP_MODE_SEL_SDR_422 | ADV7842_OP_FORMAT_SEL_10BIT }, 606 { MEDIA_BUS_FMT_YVYU10_2X10, ADV7842_OP_CH_SEL_RGB, false, true, 607 ADV7842_OP_MODE_SEL_SDR_422 | ADV7842_OP_FORMAT_SEL_10BIT }, 608 { MEDIA_BUS_FMT_YUYV12_2X12, ADV7842_OP_CH_SEL_RGB, false, false, 609 ADV7842_OP_MODE_SEL_SDR_422 | ADV7842_OP_FORMAT_SEL_12BIT }, 610 { MEDIA_BUS_FMT_YVYU12_2X12, ADV7842_OP_CH_SEL_RGB, false, true, 611 ADV7842_OP_MODE_SEL_SDR_422 | ADV7842_OP_FORMAT_SEL_12BIT }, 612 { MEDIA_BUS_FMT_UYVY8_1X16, ADV7842_OP_CH_SEL_RBG, false, false, 613 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_8BIT }, 614 { MEDIA_BUS_FMT_VYUY8_1X16, ADV7842_OP_CH_SEL_RBG, false, true, 615 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_8BIT }, 616 { MEDIA_BUS_FMT_YUYV8_1X16, ADV7842_OP_CH_SEL_RGB, false, false, 617 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_8BIT }, 618 { MEDIA_BUS_FMT_YVYU8_1X16, ADV7842_OP_CH_SEL_RGB, false, true, 619 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_8BIT }, 620 { MEDIA_BUS_FMT_UYVY10_1X20, ADV7842_OP_CH_SEL_RBG, false, false, 621 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_10BIT }, 622 { MEDIA_BUS_FMT_VYUY10_1X20, ADV7842_OP_CH_SEL_RBG, false, true, 623 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_10BIT }, 624 { MEDIA_BUS_FMT_YUYV10_1X20, ADV7842_OP_CH_SEL_RGB, false, false, 625 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_10BIT }, 626 { MEDIA_BUS_FMT_YVYU10_1X20, ADV7842_OP_CH_SEL_RGB, false, true, 627 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_10BIT }, 628 { MEDIA_BUS_FMT_UYVY12_1X24, ADV7842_OP_CH_SEL_RBG, false, false, 629 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_12BIT }, 630 { MEDIA_BUS_FMT_VYUY12_1X24, ADV7842_OP_CH_SEL_RBG, false, true, 631 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_12BIT }, 632 { MEDIA_BUS_FMT_YUYV12_1X24, ADV7842_OP_CH_SEL_RGB, false, false, 633 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_12BIT }, 634 { MEDIA_BUS_FMT_YVYU12_1X24, ADV7842_OP_CH_SEL_RGB, false, true, 635 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_12BIT }, 636 }; 637 638 static const struct adv7842_format_info * 639 adv7842_format_info(struct adv7842_state *state, u32 code) 640 { 641 unsigned int i; 642 643 for (i = 0; i < ARRAY_SIZE(adv7842_formats); ++i) { 644 if (adv7842_formats[i].code == code) 645 return &adv7842_formats[i]; 646 } 647 648 return NULL; 649 } 650 651 /* ----------------------------------------------------------------------- */ 652 653 static inline bool is_analog_input(struct v4l2_subdev *sd) 654 { 655 struct adv7842_state *state = to_state(sd); 656 657 return ((state->mode == ADV7842_MODE_RGB) || 658 (state->mode == ADV7842_MODE_COMP)); 659 } 660 661 static inline bool is_digital_input(struct v4l2_subdev *sd) 662 { 663 struct adv7842_state *state = to_state(sd); 664 665 return state->mode == ADV7842_MODE_HDMI; 666 } 667 668 static const struct v4l2_dv_timings_cap adv7842_timings_cap_analog = { 669 .type = V4L2_DV_BT_656_1120, 670 /* keep this initialization for compatibility with GCC < 4.4.6 */ 671 .reserved = { 0 }, 672 V4L2_INIT_BT_TIMINGS(0, 1920, 0, 1200, 25000000, 170000000, 673 V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT | 674 V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT, 675 V4L2_DV_BT_CAP_PROGRESSIVE | V4L2_DV_BT_CAP_REDUCED_BLANKING | 676 V4L2_DV_BT_CAP_CUSTOM) 677 }; 678 679 static const struct v4l2_dv_timings_cap adv7842_timings_cap_digital = { 680 .type = V4L2_DV_BT_656_1120, 681 /* keep this initialization for compatibility with GCC < 4.4.6 */ 682 .reserved = { 0 }, 683 V4L2_INIT_BT_TIMINGS(0, 1920, 0, 1200, 25000000, 225000000, 684 V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT | 685 V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT, 686 V4L2_DV_BT_CAP_PROGRESSIVE | V4L2_DV_BT_CAP_REDUCED_BLANKING | 687 V4L2_DV_BT_CAP_CUSTOM) 688 }; 689 690 static inline const struct v4l2_dv_timings_cap * 691 adv7842_get_dv_timings_cap(struct v4l2_subdev *sd) 692 { 693 return is_digital_input(sd) ? &adv7842_timings_cap_digital : 694 &adv7842_timings_cap_analog; 695 } 696 697 /* ----------------------------------------------------------------------- */ 698 699 static void adv7842_delayed_work_enable_hotplug(struct work_struct *work) 700 { 701 struct delayed_work *dwork = to_delayed_work(work); 702 struct adv7842_state *state = container_of(dwork, 703 struct adv7842_state, delayed_work_enable_hotplug); 704 struct v4l2_subdev *sd = &state->sd; 705 int present = state->hdmi_edid.present; 706 u8 mask = 0; 707 708 v4l2_dbg(2, debug, sd, "%s: enable hotplug on ports: 0x%x\n", 709 __func__, present); 710 711 if (present & (0x04 << ADV7842_EDID_PORT_A)) 712 mask |= 0x20; 713 if (present & (0x04 << ADV7842_EDID_PORT_B)) 714 mask |= 0x10; 715 io_write_and_or(sd, 0x20, 0xcf, mask); 716 } 717 718 static int edid_write_vga_segment(struct v4l2_subdev *sd) 719 { 720 struct i2c_client *client = v4l2_get_subdevdata(sd); 721 struct adv7842_state *state = to_state(sd); 722 const u8 *val = state->vga_edid.edid; 723 int err = 0; 724 int i; 725 726 v4l2_dbg(2, debug, sd, "%s: write EDID on VGA port\n", __func__); 727 728 /* HPA disable on port A and B */ 729 io_write_and_or(sd, 0x20, 0xcf, 0x00); 730 731 /* Disable I2C access to internal EDID ram from VGA DDC port */ 732 rep_write_and_or(sd, 0x7f, 0x7f, 0x00); 733 734 /* edid segment pointer '1' for VGA port */ 735 rep_write_and_or(sd, 0x77, 0xef, 0x10); 736 737 for (i = 0; !err && i < 256; i += I2C_SMBUS_BLOCK_MAX) 738 err = adv_smbus_write_i2c_block_data(state->i2c_edid, i, 739 I2C_SMBUS_BLOCK_MAX, val + i); 740 if (err) 741 return err; 742 743 /* Calculates the checksums and enables I2C access 744 * to internal EDID ram from VGA DDC port. 745 */ 746 rep_write_and_or(sd, 0x7f, 0x7f, 0x80); 747 748 for (i = 0; i < 1000; i++) { 749 if (rep_read(sd, 0x79) & 0x20) 750 break; 751 mdelay(1); 752 } 753 if (i == 1000) { 754 v4l_err(client, "error enabling edid on VGA port\n"); 755 return -EIO; 756 } 757 758 /* enable hotplug after 200 ms */ 759 queue_delayed_work(state->work_queues, 760 &state->delayed_work_enable_hotplug, HZ / 5); 761 762 return 0; 763 } 764 765 static int edid_spa_location(const u8 *edid) 766 { 767 u8 d; 768 769 /* 770 * TODO, improve and update for other CEA extensions 771 * currently only for 1 segment (256 bytes), 772 * i.e. 1 extension block and CEA revision 3. 773 */ 774 if ((edid[0x7e] != 1) || 775 (edid[0x80] != 0x02) || 776 (edid[0x81] != 0x03)) { 777 return -EINVAL; 778 } 779 /* 780 * search Vendor Specific Data Block (tag 3) 781 */ 782 d = edid[0x82] & 0x7f; 783 if (d > 4) { 784 int i = 0x84; 785 int end = 0x80 + d; 786 do { 787 u8 tag = edid[i]>>5; 788 u8 len = edid[i] & 0x1f; 789 790 if ((tag == 3) && (len >= 5)) 791 return i + 4; 792 i += len + 1; 793 } while (i < end); 794 } 795 return -EINVAL; 796 } 797 798 static int edid_write_hdmi_segment(struct v4l2_subdev *sd, u8 port) 799 { 800 struct i2c_client *client = v4l2_get_subdevdata(sd); 801 struct adv7842_state *state = to_state(sd); 802 const u8 *val = state->hdmi_edid.edid; 803 int spa_loc = edid_spa_location(val); 804 int err = 0; 805 int i; 806 807 v4l2_dbg(2, debug, sd, "%s: write EDID on port %c (spa at 0x%x)\n", 808 __func__, (port == ADV7842_EDID_PORT_A) ? 'A' : 'B', spa_loc); 809 810 /* HPA disable on port A and B */ 811 io_write_and_or(sd, 0x20, 0xcf, 0x00); 812 813 /* Disable I2C access to internal EDID ram from HDMI DDC ports */ 814 rep_write_and_or(sd, 0x77, 0xf3, 0x00); 815 816 if (!state->hdmi_edid.present) 817 return 0; 818 819 /* edid segment pointer '0' for HDMI ports */ 820 rep_write_and_or(sd, 0x77, 0xef, 0x00); 821 822 for (i = 0; !err && i < 256; i += I2C_SMBUS_BLOCK_MAX) 823 err = adv_smbus_write_i2c_block_data(state->i2c_edid, i, 824 I2C_SMBUS_BLOCK_MAX, val + i); 825 if (err) 826 return err; 827 828 if (spa_loc < 0) 829 spa_loc = 0xc0; /* Default value [REF_02, p. 199] */ 830 831 if (port == ADV7842_EDID_PORT_A) { 832 rep_write(sd, 0x72, val[spa_loc]); 833 rep_write(sd, 0x73, val[spa_loc + 1]); 834 } else { 835 rep_write(sd, 0x74, val[spa_loc]); 836 rep_write(sd, 0x75, val[spa_loc + 1]); 837 } 838 rep_write(sd, 0x76, spa_loc & 0xff); 839 rep_write_and_or(sd, 0x77, 0xbf, (spa_loc >> 2) & 0x40); 840 841 /* Calculates the checksums and enables I2C access to internal 842 * EDID ram from HDMI DDC ports 843 */ 844 rep_write_and_or(sd, 0x77, 0xf3, state->hdmi_edid.present); 845 846 for (i = 0; i < 1000; i++) { 847 if (rep_read(sd, 0x7d) & state->hdmi_edid.present) 848 break; 849 mdelay(1); 850 } 851 if (i == 1000) { 852 v4l_err(client, "error enabling edid on port %c\n", 853 (port == ADV7842_EDID_PORT_A) ? 'A' : 'B'); 854 return -EIO; 855 } 856 857 /* enable hotplug after 200 ms */ 858 queue_delayed_work(state->work_queues, 859 &state->delayed_work_enable_hotplug, HZ / 5); 860 861 return 0; 862 } 863 864 /* ----------------------------------------------------------------------- */ 865 866 #ifdef CONFIG_VIDEO_ADV_DEBUG 867 static void adv7842_inv_register(struct v4l2_subdev *sd) 868 { 869 v4l2_info(sd, "0x000-0x0ff: IO Map\n"); 870 v4l2_info(sd, "0x100-0x1ff: AVLink Map\n"); 871 v4l2_info(sd, "0x200-0x2ff: CEC Map\n"); 872 v4l2_info(sd, "0x300-0x3ff: InfoFrame Map\n"); 873 v4l2_info(sd, "0x400-0x4ff: SDP_IO Map\n"); 874 v4l2_info(sd, "0x500-0x5ff: SDP Map\n"); 875 v4l2_info(sd, "0x600-0x6ff: AFE Map\n"); 876 v4l2_info(sd, "0x700-0x7ff: Repeater Map\n"); 877 v4l2_info(sd, "0x800-0x8ff: EDID Map\n"); 878 v4l2_info(sd, "0x900-0x9ff: HDMI Map\n"); 879 v4l2_info(sd, "0xa00-0xaff: CP Map\n"); 880 v4l2_info(sd, "0xb00-0xbff: VDP Map\n"); 881 } 882 883 static int adv7842_g_register(struct v4l2_subdev *sd, 884 struct v4l2_dbg_register *reg) 885 { 886 reg->size = 1; 887 switch (reg->reg >> 8) { 888 case 0: 889 reg->val = io_read(sd, reg->reg & 0xff); 890 break; 891 case 1: 892 reg->val = avlink_read(sd, reg->reg & 0xff); 893 break; 894 case 2: 895 reg->val = cec_read(sd, reg->reg & 0xff); 896 break; 897 case 3: 898 reg->val = infoframe_read(sd, reg->reg & 0xff); 899 break; 900 case 4: 901 reg->val = sdp_io_read(sd, reg->reg & 0xff); 902 break; 903 case 5: 904 reg->val = sdp_read(sd, reg->reg & 0xff); 905 break; 906 case 6: 907 reg->val = afe_read(sd, reg->reg & 0xff); 908 break; 909 case 7: 910 reg->val = rep_read(sd, reg->reg & 0xff); 911 break; 912 case 8: 913 reg->val = edid_read(sd, reg->reg & 0xff); 914 break; 915 case 9: 916 reg->val = hdmi_read(sd, reg->reg & 0xff); 917 break; 918 case 0xa: 919 reg->val = cp_read(sd, reg->reg & 0xff); 920 break; 921 case 0xb: 922 reg->val = vdp_read(sd, reg->reg & 0xff); 923 break; 924 default: 925 v4l2_info(sd, "Register %03llx not supported\n", reg->reg); 926 adv7842_inv_register(sd); 927 break; 928 } 929 return 0; 930 } 931 932 static int adv7842_s_register(struct v4l2_subdev *sd, 933 const struct v4l2_dbg_register *reg) 934 { 935 u8 val = reg->val & 0xff; 936 937 switch (reg->reg >> 8) { 938 case 0: 939 io_write(sd, reg->reg & 0xff, val); 940 break; 941 case 1: 942 avlink_write(sd, reg->reg & 0xff, val); 943 break; 944 case 2: 945 cec_write(sd, reg->reg & 0xff, val); 946 break; 947 case 3: 948 infoframe_write(sd, reg->reg & 0xff, val); 949 break; 950 case 4: 951 sdp_io_write(sd, reg->reg & 0xff, val); 952 break; 953 case 5: 954 sdp_write(sd, reg->reg & 0xff, val); 955 break; 956 case 6: 957 afe_write(sd, reg->reg & 0xff, val); 958 break; 959 case 7: 960 rep_write(sd, reg->reg & 0xff, val); 961 break; 962 case 8: 963 edid_write(sd, reg->reg & 0xff, val); 964 break; 965 case 9: 966 hdmi_write(sd, reg->reg & 0xff, val); 967 break; 968 case 0xa: 969 cp_write(sd, reg->reg & 0xff, val); 970 break; 971 case 0xb: 972 vdp_write(sd, reg->reg & 0xff, val); 973 break; 974 default: 975 v4l2_info(sd, "Register %03llx not supported\n", reg->reg); 976 adv7842_inv_register(sd); 977 break; 978 } 979 return 0; 980 } 981 #endif 982 983 static int adv7842_s_detect_tx_5v_ctrl(struct v4l2_subdev *sd) 984 { 985 struct adv7842_state *state = to_state(sd); 986 int prev = v4l2_ctrl_g_ctrl(state->detect_tx_5v_ctrl); 987 u8 reg_io_6f = io_read(sd, 0x6f); 988 int val = 0; 989 990 if (reg_io_6f & 0x02) 991 val |= 1; /* port A */ 992 if (reg_io_6f & 0x01) 993 val |= 2; /* port B */ 994 995 v4l2_dbg(1, debug, sd, "%s: 0x%x -> 0x%x\n", __func__, prev, val); 996 997 if (val != prev) 998 return v4l2_ctrl_s_ctrl(state->detect_tx_5v_ctrl, val); 999 return 0; 1000 } 1001 1002 static int find_and_set_predefined_video_timings(struct v4l2_subdev *sd, 1003 u8 prim_mode, 1004 const struct adv7842_video_standards *predef_vid_timings, 1005 const struct v4l2_dv_timings *timings) 1006 { 1007 int i; 1008 1009 for (i = 0; predef_vid_timings[i].timings.bt.width; i++) { 1010 if (!v4l2_match_dv_timings(timings, &predef_vid_timings[i].timings, 1011 is_digital_input(sd) ? 250000 : 1000000, false)) 1012 continue; 1013 /* video std */ 1014 io_write(sd, 0x00, predef_vid_timings[i].vid_std); 1015 /* v_freq and prim mode */ 1016 io_write(sd, 0x01, (predef_vid_timings[i].v_freq << 4) + prim_mode); 1017 return 0; 1018 } 1019 1020 return -1; 1021 } 1022 1023 static int configure_predefined_video_timings(struct v4l2_subdev *sd, 1024 struct v4l2_dv_timings *timings) 1025 { 1026 struct adv7842_state *state = to_state(sd); 1027 int err; 1028 1029 v4l2_dbg(1, debug, sd, "%s\n", __func__); 1030 1031 /* reset to default values */ 1032 io_write(sd, 0x16, 0x43); 1033 io_write(sd, 0x17, 0x5a); 1034 /* disable embedded syncs for auto graphics mode */ 1035 cp_write_and_or(sd, 0x81, 0xef, 0x00); 1036 cp_write(sd, 0x26, 0x00); 1037 cp_write(sd, 0x27, 0x00); 1038 cp_write(sd, 0x28, 0x00); 1039 cp_write(sd, 0x29, 0x00); 1040 cp_write(sd, 0x8f, 0x40); 1041 cp_write(sd, 0x90, 0x00); 1042 cp_write(sd, 0xa5, 0x00); 1043 cp_write(sd, 0xa6, 0x00); 1044 cp_write(sd, 0xa7, 0x00); 1045 cp_write(sd, 0xab, 0x00); 1046 cp_write(sd, 0xac, 0x00); 1047 1048 switch (state->mode) { 1049 case ADV7842_MODE_COMP: 1050 case ADV7842_MODE_RGB: 1051 err = find_and_set_predefined_video_timings(sd, 1052 0x01, adv7842_prim_mode_comp, timings); 1053 if (err) 1054 err = find_and_set_predefined_video_timings(sd, 1055 0x02, adv7842_prim_mode_gr, timings); 1056 break; 1057 case ADV7842_MODE_HDMI: 1058 err = find_and_set_predefined_video_timings(sd, 1059 0x05, adv7842_prim_mode_hdmi_comp, timings); 1060 if (err) 1061 err = find_and_set_predefined_video_timings(sd, 1062 0x06, adv7842_prim_mode_hdmi_gr, timings); 1063 break; 1064 default: 1065 v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n", 1066 __func__, state->mode); 1067 err = -1; 1068 break; 1069 } 1070 1071 1072 return err; 1073 } 1074 1075 static void configure_custom_video_timings(struct v4l2_subdev *sd, 1076 const struct v4l2_bt_timings *bt) 1077 { 1078 struct adv7842_state *state = to_state(sd); 1079 struct i2c_client *client = v4l2_get_subdevdata(sd); 1080 u32 width = htotal(bt); 1081 u32 height = vtotal(bt); 1082 u16 cp_start_sav = bt->hsync + bt->hbackporch - 4; 1083 u16 cp_start_eav = width - bt->hfrontporch; 1084 u16 cp_start_vbi = height - bt->vfrontporch + 1; 1085 u16 cp_end_vbi = bt->vsync + bt->vbackporch + 1; 1086 u16 ch1_fr_ll = (((u32)bt->pixelclock / 100) > 0) ? 1087 ((width * (ADV7842_fsc / 100)) / ((u32)bt->pixelclock / 100)) : 0; 1088 const u8 pll[2] = { 1089 0xc0 | ((width >> 8) & 0x1f), 1090 width & 0xff 1091 }; 1092 1093 v4l2_dbg(2, debug, sd, "%s\n", __func__); 1094 1095 switch (state->mode) { 1096 case ADV7842_MODE_COMP: 1097 case ADV7842_MODE_RGB: 1098 /* auto graphics */ 1099 io_write(sd, 0x00, 0x07); /* video std */ 1100 io_write(sd, 0x01, 0x02); /* prim mode */ 1101 /* enable embedded syncs for auto graphics mode */ 1102 cp_write_and_or(sd, 0x81, 0xef, 0x10); 1103 1104 /* Should only be set in auto-graphics mode [REF_02, p. 91-92] */ 1105 /* setup PLL_DIV_MAN_EN and PLL_DIV_RATIO */ 1106 /* IO-map reg. 0x16 and 0x17 should be written in sequence */ 1107 if (adv_smbus_write_i2c_block_data(client, 0x16, 2, pll)) { 1108 v4l2_err(sd, "writing to reg 0x16 and 0x17 failed\n"); 1109 break; 1110 } 1111 1112 /* active video - horizontal timing */ 1113 cp_write(sd, 0x26, (cp_start_sav >> 8) & 0xf); 1114 cp_write(sd, 0x27, (cp_start_sav & 0xff)); 1115 cp_write(sd, 0x28, (cp_start_eav >> 8) & 0xf); 1116 cp_write(sd, 0x29, (cp_start_eav & 0xff)); 1117 1118 /* active video - vertical timing */ 1119 cp_write(sd, 0xa5, (cp_start_vbi >> 4) & 0xff); 1120 cp_write(sd, 0xa6, ((cp_start_vbi & 0xf) << 4) | 1121 ((cp_end_vbi >> 8) & 0xf)); 1122 cp_write(sd, 0xa7, cp_end_vbi & 0xff); 1123 break; 1124 case ADV7842_MODE_HDMI: 1125 /* set default prim_mode/vid_std for HDMI 1126 according to [REF_03, c. 4.2] */ 1127 io_write(sd, 0x00, 0x02); /* video std */ 1128 io_write(sd, 0x01, 0x06); /* prim mode */ 1129 break; 1130 default: 1131 v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n", 1132 __func__, state->mode); 1133 break; 1134 } 1135 1136 cp_write(sd, 0x8f, (ch1_fr_ll >> 8) & 0x7); 1137 cp_write(sd, 0x90, ch1_fr_ll & 0xff); 1138 cp_write(sd, 0xab, (height >> 4) & 0xff); 1139 cp_write(sd, 0xac, (height & 0x0f) << 4); 1140 } 1141 1142 static void adv7842_set_offset(struct v4l2_subdev *sd, bool auto_offset, u16 offset_a, u16 offset_b, u16 offset_c) 1143 { 1144 struct adv7842_state *state = to_state(sd); 1145 u8 offset_buf[4]; 1146 1147 if (auto_offset) { 1148 offset_a = 0x3ff; 1149 offset_b = 0x3ff; 1150 offset_c = 0x3ff; 1151 } 1152 1153 v4l2_dbg(2, debug, sd, "%s: %s offset: a = 0x%x, b = 0x%x, c = 0x%x\n", 1154 __func__, auto_offset ? "Auto" : "Manual", 1155 offset_a, offset_b, offset_c); 1156 1157 offset_buf[0]= (cp_read(sd, 0x77) & 0xc0) | ((offset_a & 0x3f0) >> 4); 1158 offset_buf[1] = ((offset_a & 0x00f) << 4) | ((offset_b & 0x3c0) >> 6); 1159 offset_buf[2] = ((offset_b & 0x03f) << 2) | ((offset_c & 0x300) >> 8); 1160 offset_buf[3] = offset_c & 0x0ff; 1161 1162 /* Registers must be written in this order with no i2c access in between */ 1163 if (adv_smbus_write_i2c_block_data(state->i2c_cp, 0x77, 4, offset_buf)) 1164 v4l2_err(sd, "%s: i2c error writing to CP reg 0x77, 0x78, 0x79, 0x7a\n", __func__); 1165 } 1166 1167 static void adv7842_set_gain(struct v4l2_subdev *sd, bool auto_gain, u16 gain_a, u16 gain_b, u16 gain_c) 1168 { 1169 struct adv7842_state *state = to_state(sd); 1170 u8 gain_buf[4]; 1171 u8 gain_man = 1; 1172 u8 agc_mode_man = 1; 1173 1174 if (auto_gain) { 1175 gain_man = 0; 1176 agc_mode_man = 0; 1177 gain_a = 0x100; 1178 gain_b = 0x100; 1179 gain_c = 0x100; 1180 } 1181 1182 v4l2_dbg(2, debug, sd, "%s: %s gain: a = 0x%x, b = 0x%x, c = 0x%x\n", 1183 __func__, auto_gain ? "Auto" : "Manual", 1184 gain_a, gain_b, gain_c); 1185 1186 gain_buf[0] = ((gain_man << 7) | (agc_mode_man << 6) | ((gain_a & 0x3f0) >> 4)); 1187 gain_buf[1] = (((gain_a & 0x00f) << 4) | ((gain_b & 0x3c0) >> 6)); 1188 gain_buf[2] = (((gain_b & 0x03f) << 2) | ((gain_c & 0x300) >> 8)); 1189 gain_buf[3] = ((gain_c & 0x0ff)); 1190 1191 /* Registers must be written in this order with no i2c access in between */ 1192 if (adv_smbus_write_i2c_block_data(state->i2c_cp, 0x73, 4, gain_buf)) 1193 v4l2_err(sd, "%s: i2c error writing to CP reg 0x73, 0x74, 0x75, 0x76\n", __func__); 1194 } 1195 1196 static void set_rgb_quantization_range(struct v4l2_subdev *sd) 1197 { 1198 struct adv7842_state *state = to_state(sd); 1199 bool rgb_output = io_read(sd, 0x02) & 0x02; 1200 bool hdmi_signal = hdmi_read(sd, 0x05) & 0x80; 1201 1202 v4l2_dbg(2, debug, sd, "%s: RGB quantization range: %d, RGB out: %d, HDMI: %d\n", 1203 __func__, state->rgb_quantization_range, 1204 rgb_output, hdmi_signal); 1205 1206 adv7842_set_gain(sd, true, 0x0, 0x0, 0x0); 1207 adv7842_set_offset(sd, true, 0x0, 0x0, 0x0); 1208 1209 switch (state->rgb_quantization_range) { 1210 case V4L2_DV_RGB_RANGE_AUTO: 1211 if (state->mode == ADV7842_MODE_RGB) { 1212 /* Receiving analog RGB signal 1213 * Set RGB full range (0-255) */ 1214 io_write_and_or(sd, 0x02, 0x0f, 0x10); 1215 break; 1216 } 1217 1218 if (state->mode == ADV7842_MODE_COMP) { 1219 /* Receiving analog YPbPr signal 1220 * Set automode */ 1221 io_write_and_or(sd, 0x02, 0x0f, 0xf0); 1222 break; 1223 } 1224 1225 if (hdmi_signal) { 1226 /* Receiving HDMI signal 1227 * Set automode */ 1228 io_write_and_or(sd, 0x02, 0x0f, 0xf0); 1229 break; 1230 } 1231 1232 /* Receiving DVI-D signal 1233 * ADV7842 selects RGB limited range regardless of 1234 * input format (CE/IT) in automatic mode */ 1235 if (state->timings.bt.flags & V4L2_DV_FL_IS_CE_VIDEO) { 1236 /* RGB limited range (16-235) */ 1237 io_write_and_or(sd, 0x02, 0x0f, 0x00); 1238 } else { 1239 /* RGB full range (0-255) */ 1240 io_write_and_or(sd, 0x02, 0x0f, 0x10); 1241 1242 if (is_digital_input(sd) && rgb_output) { 1243 adv7842_set_offset(sd, false, 0x40, 0x40, 0x40); 1244 } else { 1245 adv7842_set_gain(sd, false, 0xe0, 0xe0, 0xe0); 1246 adv7842_set_offset(sd, false, 0x70, 0x70, 0x70); 1247 } 1248 } 1249 break; 1250 case V4L2_DV_RGB_RANGE_LIMITED: 1251 if (state->mode == ADV7842_MODE_COMP) { 1252 /* YCrCb limited range (16-235) */ 1253 io_write_and_or(sd, 0x02, 0x0f, 0x20); 1254 break; 1255 } 1256 1257 /* RGB limited range (16-235) */ 1258 io_write_and_or(sd, 0x02, 0x0f, 0x00); 1259 1260 break; 1261 case V4L2_DV_RGB_RANGE_FULL: 1262 if (state->mode == ADV7842_MODE_COMP) { 1263 /* YCrCb full range (0-255) */ 1264 io_write_and_or(sd, 0x02, 0x0f, 0x60); 1265 break; 1266 } 1267 1268 /* RGB full range (0-255) */ 1269 io_write_and_or(sd, 0x02, 0x0f, 0x10); 1270 1271 if (is_analog_input(sd) || hdmi_signal) 1272 break; 1273 1274 /* Adjust gain/offset for DVI-D signals only */ 1275 if (rgb_output) { 1276 adv7842_set_offset(sd, false, 0x40, 0x40, 0x40); 1277 } else { 1278 adv7842_set_gain(sd, false, 0xe0, 0xe0, 0xe0); 1279 adv7842_set_offset(sd, false, 0x70, 0x70, 0x70); 1280 } 1281 break; 1282 } 1283 } 1284 1285 static int adv7842_s_ctrl(struct v4l2_ctrl *ctrl) 1286 { 1287 struct v4l2_subdev *sd = to_sd(ctrl); 1288 struct adv7842_state *state = to_state(sd); 1289 1290 /* TODO SDP ctrls 1291 contrast/brightness/hue/free run is acting a bit strange, 1292 not sure if sdp csc is correct. 1293 */ 1294 switch (ctrl->id) { 1295 /* standard ctrls */ 1296 case V4L2_CID_BRIGHTNESS: 1297 cp_write(sd, 0x3c, ctrl->val); 1298 sdp_write(sd, 0x14, ctrl->val); 1299 /* ignore lsb sdp 0x17[3:2] */ 1300 return 0; 1301 case V4L2_CID_CONTRAST: 1302 cp_write(sd, 0x3a, ctrl->val); 1303 sdp_write(sd, 0x13, ctrl->val); 1304 /* ignore lsb sdp 0x17[1:0] */ 1305 return 0; 1306 case V4L2_CID_SATURATION: 1307 cp_write(sd, 0x3b, ctrl->val); 1308 sdp_write(sd, 0x15, ctrl->val); 1309 /* ignore lsb sdp 0x17[5:4] */ 1310 return 0; 1311 case V4L2_CID_HUE: 1312 cp_write(sd, 0x3d, ctrl->val); 1313 sdp_write(sd, 0x16, ctrl->val); 1314 /* ignore lsb sdp 0x17[7:6] */ 1315 return 0; 1316 /* custom ctrls */ 1317 case V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE: 1318 afe_write(sd, 0xc8, ctrl->val); 1319 return 0; 1320 case V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL: 1321 cp_write_and_or(sd, 0xbf, ~0x04, (ctrl->val << 2)); 1322 sdp_write_and_or(sd, 0xdd, ~0x04, (ctrl->val << 2)); 1323 return 0; 1324 case V4L2_CID_ADV_RX_FREE_RUN_COLOR: { 1325 u8 R = (ctrl->val & 0xff0000) >> 16; 1326 u8 G = (ctrl->val & 0x00ff00) >> 8; 1327 u8 B = (ctrl->val & 0x0000ff); 1328 /* RGB -> YUV, numerical approximation */ 1329 int Y = 66 * R + 129 * G + 25 * B; 1330 int U = -38 * R - 74 * G + 112 * B; 1331 int V = 112 * R - 94 * G - 18 * B; 1332 1333 /* Scale down to 8 bits with rounding */ 1334 Y = (Y + 128) >> 8; 1335 U = (U + 128) >> 8; 1336 V = (V + 128) >> 8; 1337 /* make U,V positive */ 1338 Y += 16; 1339 U += 128; 1340 V += 128; 1341 1342 v4l2_dbg(1, debug, sd, "R %x, G %x, B %x\n", R, G, B); 1343 v4l2_dbg(1, debug, sd, "Y %x, U %x, V %x\n", Y, U, V); 1344 1345 /* CP */ 1346 cp_write(sd, 0xc1, R); 1347 cp_write(sd, 0xc0, G); 1348 cp_write(sd, 0xc2, B); 1349 /* SDP */ 1350 sdp_write(sd, 0xde, Y); 1351 sdp_write(sd, 0xdf, (V & 0xf0) | ((U >> 4) & 0x0f)); 1352 return 0; 1353 } 1354 case V4L2_CID_DV_RX_RGB_RANGE: 1355 state->rgb_quantization_range = ctrl->val; 1356 set_rgb_quantization_range(sd); 1357 return 0; 1358 } 1359 return -EINVAL; 1360 } 1361 1362 static int adv7842_g_volatile_ctrl(struct v4l2_ctrl *ctrl) 1363 { 1364 struct v4l2_subdev *sd = to_sd(ctrl); 1365 1366 if (ctrl->id == V4L2_CID_DV_RX_IT_CONTENT_TYPE) { 1367 ctrl->val = V4L2_DV_IT_CONTENT_TYPE_NO_ITC; 1368 if ((io_read(sd, 0x60) & 1) && (infoframe_read(sd, 0x03) & 0x80)) 1369 ctrl->val = (infoframe_read(sd, 0x05) >> 4) & 3; 1370 return 0; 1371 } 1372 return -EINVAL; 1373 } 1374 1375 static inline bool no_power(struct v4l2_subdev *sd) 1376 { 1377 return io_read(sd, 0x0c) & 0x24; 1378 } 1379 1380 static inline bool no_cp_signal(struct v4l2_subdev *sd) 1381 { 1382 return ((cp_read(sd, 0xb5) & 0xd0) != 0xd0) || !(cp_read(sd, 0xb1) & 0x80); 1383 } 1384 1385 static inline bool is_hdmi(struct v4l2_subdev *sd) 1386 { 1387 return hdmi_read(sd, 0x05) & 0x80; 1388 } 1389 1390 static int adv7842_g_input_status(struct v4l2_subdev *sd, u32 *status) 1391 { 1392 struct adv7842_state *state = to_state(sd); 1393 1394 *status = 0; 1395 1396 if (io_read(sd, 0x0c) & 0x24) 1397 *status |= V4L2_IN_ST_NO_POWER; 1398 1399 if (state->mode == ADV7842_MODE_SDP) { 1400 /* status from SDP block */ 1401 if (!(sdp_read(sd, 0x5A) & 0x01)) 1402 *status |= V4L2_IN_ST_NO_SIGNAL; 1403 1404 v4l2_dbg(1, debug, sd, "%s: SDP status = 0x%x\n", 1405 __func__, *status); 1406 return 0; 1407 } 1408 /* status from CP block */ 1409 if ((cp_read(sd, 0xb5) & 0xd0) != 0xd0 || 1410 !(cp_read(sd, 0xb1) & 0x80)) 1411 /* TODO channel 2 */ 1412 *status |= V4L2_IN_ST_NO_SIGNAL; 1413 1414 if (is_digital_input(sd) && ((io_read(sd, 0x74) & 0x03) != 0x03)) 1415 *status |= V4L2_IN_ST_NO_SIGNAL; 1416 1417 v4l2_dbg(1, debug, sd, "%s: CP status = 0x%x\n", 1418 __func__, *status); 1419 1420 return 0; 1421 } 1422 1423 struct stdi_readback { 1424 u16 bl, lcf, lcvs; 1425 u8 hs_pol, vs_pol; 1426 bool interlaced; 1427 }; 1428 1429 static int stdi2dv_timings(struct v4l2_subdev *sd, 1430 struct stdi_readback *stdi, 1431 struct v4l2_dv_timings *timings) 1432 { 1433 struct adv7842_state *state = to_state(sd); 1434 u32 hfreq = (ADV7842_fsc * 8) / stdi->bl; 1435 u32 pix_clk; 1436 int i; 1437 1438 for (i = 0; v4l2_dv_timings_presets[i].bt.width; i++) { 1439 const struct v4l2_bt_timings *bt = &v4l2_dv_timings_presets[i].bt; 1440 1441 if (!v4l2_valid_dv_timings(&v4l2_dv_timings_presets[i], 1442 adv7842_get_dv_timings_cap(sd), 1443 adv7842_check_dv_timings, NULL)) 1444 continue; 1445 if (vtotal(bt) != stdi->lcf + 1) 1446 continue; 1447 if (bt->vsync != stdi->lcvs) 1448 continue; 1449 1450 pix_clk = hfreq * htotal(bt); 1451 1452 if ((pix_clk < bt->pixelclock + 1000000) && 1453 (pix_clk > bt->pixelclock - 1000000)) { 1454 *timings = v4l2_dv_timings_presets[i]; 1455 return 0; 1456 } 1457 } 1458 1459 if (v4l2_detect_cvt(stdi->lcf + 1, hfreq, stdi->lcvs, 0, 1460 (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) | 1461 (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0), 1462 false, timings)) 1463 return 0; 1464 if (v4l2_detect_gtf(stdi->lcf + 1, hfreq, stdi->lcvs, 1465 (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) | 1466 (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0), 1467 false, state->aspect_ratio, timings)) 1468 return 0; 1469 1470 v4l2_dbg(2, debug, sd, 1471 "%s: No format candidate found for lcvs = %d, lcf=%d, bl = %d, %chsync, %cvsync\n", 1472 __func__, stdi->lcvs, stdi->lcf, stdi->bl, 1473 stdi->hs_pol, stdi->vs_pol); 1474 return -1; 1475 } 1476 1477 static int read_stdi(struct v4l2_subdev *sd, struct stdi_readback *stdi) 1478 { 1479 u32 status; 1480 1481 adv7842_g_input_status(sd, &status); 1482 if (status & V4L2_IN_ST_NO_SIGNAL) { 1483 v4l2_dbg(2, debug, sd, "%s: no signal\n", __func__); 1484 return -ENOLINK; 1485 } 1486 1487 stdi->bl = ((cp_read(sd, 0xb1) & 0x3f) << 8) | cp_read(sd, 0xb2); 1488 stdi->lcf = ((cp_read(sd, 0xb3) & 0x7) << 8) | cp_read(sd, 0xb4); 1489 stdi->lcvs = cp_read(sd, 0xb3) >> 3; 1490 1491 if ((cp_read(sd, 0xb5) & 0x80) && ((cp_read(sd, 0xb5) & 0x03) == 0x01)) { 1492 stdi->hs_pol = ((cp_read(sd, 0xb5) & 0x10) ? 1493 ((cp_read(sd, 0xb5) & 0x08) ? '+' : '-') : 'x'); 1494 stdi->vs_pol = ((cp_read(sd, 0xb5) & 0x40) ? 1495 ((cp_read(sd, 0xb5) & 0x20) ? '+' : '-') : 'x'); 1496 } else { 1497 stdi->hs_pol = 'x'; 1498 stdi->vs_pol = 'x'; 1499 } 1500 stdi->interlaced = (cp_read(sd, 0xb1) & 0x40) ? true : false; 1501 1502 if (stdi->lcf < 239 || stdi->bl < 8 || stdi->bl == 0x3fff) { 1503 v4l2_dbg(2, debug, sd, "%s: invalid signal\n", __func__); 1504 return -ENOLINK; 1505 } 1506 1507 v4l2_dbg(2, debug, sd, 1508 "%s: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %chsync, %cvsync, %s\n", 1509 __func__, stdi->lcf, stdi->bl, stdi->lcvs, 1510 stdi->hs_pol, stdi->vs_pol, 1511 stdi->interlaced ? "interlaced" : "progressive"); 1512 1513 return 0; 1514 } 1515 1516 static int adv7842_enum_dv_timings(struct v4l2_subdev *sd, 1517 struct v4l2_enum_dv_timings *timings) 1518 { 1519 if (timings->pad != 0) 1520 return -EINVAL; 1521 1522 return v4l2_enum_dv_timings_cap(timings, 1523 adv7842_get_dv_timings_cap(sd), adv7842_check_dv_timings, NULL); 1524 } 1525 1526 static int adv7842_dv_timings_cap(struct v4l2_subdev *sd, 1527 struct v4l2_dv_timings_cap *cap) 1528 { 1529 if (cap->pad != 0) 1530 return -EINVAL; 1531 1532 *cap = *adv7842_get_dv_timings_cap(sd); 1533 return 0; 1534 } 1535 1536 /* Fill the optional fields .standards and .flags in struct v4l2_dv_timings 1537 if the format is listed in adv7842_timings[] */ 1538 static void adv7842_fill_optional_dv_timings_fields(struct v4l2_subdev *sd, 1539 struct v4l2_dv_timings *timings) 1540 { 1541 v4l2_find_dv_timings_cap(timings, adv7842_get_dv_timings_cap(sd), 1542 is_digital_input(sd) ? 250000 : 1000000, 1543 adv7842_check_dv_timings, NULL); 1544 } 1545 1546 static int adv7842_query_dv_timings(struct v4l2_subdev *sd, 1547 struct v4l2_dv_timings *timings) 1548 { 1549 struct adv7842_state *state = to_state(sd); 1550 struct v4l2_bt_timings *bt = &timings->bt; 1551 struct stdi_readback stdi = { 0 }; 1552 1553 v4l2_dbg(1, debug, sd, "%s:\n", __func__); 1554 1555 memset(timings, 0, sizeof(struct v4l2_dv_timings)); 1556 1557 /* SDP block */ 1558 if (state->mode == ADV7842_MODE_SDP) 1559 return -ENODATA; 1560 1561 /* read STDI */ 1562 if (read_stdi(sd, &stdi)) { 1563 state->restart_stdi_once = true; 1564 v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__); 1565 return -ENOLINK; 1566 } 1567 bt->interlaced = stdi.interlaced ? 1568 V4L2_DV_INTERLACED : V4L2_DV_PROGRESSIVE; 1569 bt->standards = V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT | 1570 V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT; 1571 1572 if (is_digital_input(sd)) { 1573 u32 freq; 1574 1575 timings->type = V4L2_DV_BT_656_1120; 1576 1577 bt->width = (hdmi_read(sd, 0x07) & 0x0f) * 256 + hdmi_read(sd, 0x08); 1578 bt->height = (hdmi_read(sd, 0x09) & 0x0f) * 256 + hdmi_read(sd, 0x0a); 1579 freq = ((hdmi_read(sd, 0x51) << 1) + (hdmi_read(sd, 0x52) >> 7)) * 1000000; 1580 freq += ((hdmi_read(sd, 0x52) & 0x7f) * 7813); 1581 if (is_hdmi(sd)) { 1582 /* adjust for deep color mode */ 1583 freq = freq * 8 / (((hdmi_read(sd, 0x0b) & 0xc0) >> 6) * 2 + 8); 1584 } 1585 bt->pixelclock = freq; 1586 bt->hfrontporch = (hdmi_read(sd, 0x20) & 0x03) * 256 + 1587 hdmi_read(sd, 0x21); 1588 bt->hsync = (hdmi_read(sd, 0x22) & 0x03) * 256 + 1589 hdmi_read(sd, 0x23); 1590 bt->hbackporch = (hdmi_read(sd, 0x24) & 0x03) * 256 + 1591 hdmi_read(sd, 0x25); 1592 bt->vfrontporch = ((hdmi_read(sd, 0x2a) & 0x1f) * 256 + 1593 hdmi_read(sd, 0x2b)) / 2; 1594 bt->vsync = ((hdmi_read(sd, 0x2e) & 0x1f) * 256 + 1595 hdmi_read(sd, 0x2f)) / 2; 1596 bt->vbackporch = ((hdmi_read(sd, 0x32) & 0x1f) * 256 + 1597 hdmi_read(sd, 0x33)) / 2; 1598 bt->polarities = ((hdmi_read(sd, 0x05) & 0x10) ? V4L2_DV_VSYNC_POS_POL : 0) | 1599 ((hdmi_read(sd, 0x05) & 0x20) ? V4L2_DV_HSYNC_POS_POL : 0); 1600 if (bt->interlaced == V4L2_DV_INTERLACED) { 1601 bt->height += (hdmi_read(sd, 0x0b) & 0x0f) * 256 + 1602 hdmi_read(sd, 0x0c); 1603 bt->il_vfrontporch = ((hdmi_read(sd, 0x2c) & 0x1f) * 256 + 1604 hdmi_read(sd, 0x2d)) / 2; 1605 bt->il_vsync = ((hdmi_read(sd, 0x30) & 0x1f) * 256 + 1606 hdmi_read(sd, 0x31)) / 2; 1607 bt->il_vbackporch = ((hdmi_read(sd, 0x34) & 0x1f) * 256 + 1608 hdmi_read(sd, 0x35)) / 2; 1609 } else { 1610 bt->il_vfrontporch = 0; 1611 bt->il_vsync = 0; 1612 bt->il_vbackporch = 0; 1613 } 1614 adv7842_fill_optional_dv_timings_fields(sd, timings); 1615 } else { 1616 /* find format 1617 * Since LCVS values are inaccurate [REF_03, p. 339-340], 1618 * stdi2dv_timings() is called with lcvs +-1 if the first attempt fails. 1619 */ 1620 if (!stdi2dv_timings(sd, &stdi, timings)) 1621 goto found; 1622 stdi.lcvs += 1; 1623 v4l2_dbg(1, debug, sd, "%s: lcvs + 1 = %d\n", __func__, stdi.lcvs); 1624 if (!stdi2dv_timings(sd, &stdi, timings)) 1625 goto found; 1626 stdi.lcvs -= 2; 1627 v4l2_dbg(1, debug, sd, "%s: lcvs - 1 = %d\n", __func__, stdi.lcvs); 1628 if (stdi2dv_timings(sd, &stdi, timings)) { 1629 /* 1630 * The STDI block may measure wrong values, especially 1631 * for lcvs and lcf. If the driver can not find any 1632 * valid timing, the STDI block is restarted to measure 1633 * the video timings again. The function will return an 1634 * error, but the restart of STDI will generate a new 1635 * STDI interrupt and the format detection process will 1636 * restart. 1637 */ 1638 if (state->restart_stdi_once) { 1639 v4l2_dbg(1, debug, sd, "%s: restart STDI\n", __func__); 1640 /* TODO restart STDI for Sync Channel 2 */ 1641 /* enter one-shot mode */ 1642 cp_write_and_or(sd, 0x86, 0xf9, 0x00); 1643 /* trigger STDI restart */ 1644 cp_write_and_or(sd, 0x86, 0xf9, 0x04); 1645 /* reset to continuous mode */ 1646 cp_write_and_or(sd, 0x86, 0xf9, 0x02); 1647 state->restart_stdi_once = false; 1648 return -ENOLINK; 1649 } 1650 v4l2_dbg(1, debug, sd, "%s: format not supported\n", __func__); 1651 return -ERANGE; 1652 } 1653 state->restart_stdi_once = true; 1654 } 1655 found: 1656 1657 if (debug > 1) 1658 v4l2_print_dv_timings(sd->name, "adv7842_query_dv_timings:", 1659 timings, true); 1660 return 0; 1661 } 1662 1663 static int adv7842_s_dv_timings(struct v4l2_subdev *sd, 1664 struct v4l2_dv_timings *timings) 1665 { 1666 struct adv7842_state *state = to_state(sd); 1667 struct v4l2_bt_timings *bt; 1668 int err; 1669 1670 v4l2_dbg(1, debug, sd, "%s:\n", __func__); 1671 1672 if (state->mode == ADV7842_MODE_SDP) 1673 return -ENODATA; 1674 1675 if (v4l2_match_dv_timings(&state->timings, timings, 0, false)) { 1676 v4l2_dbg(1, debug, sd, "%s: no change\n", __func__); 1677 return 0; 1678 } 1679 1680 bt = &timings->bt; 1681 1682 if (!v4l2_valid_dv_timings(timings, adv7842_get_dv_timings_cap(sd), 1683 adv7842_check_dv_timings, NULL)) 1684 return -ERANGE; 1685 1686 adv7842_fill_optional_dv_timings_fields(sd, timings); 1687 1688 state->timings = *timings; 1689 1690 cp_write(sd, 0x91, bt->interlaced ? 0x40 : 0x00); 1691 1692 /* Use prim_mode and vid_std when available */ 1693 err = configure_predefined_video_timings(sd, timings); 1694 if (err) { 1695 /* custom settings when the video format 1696 does not have prim_mode/vid_std */ 1697 configure_custom_video_timings(sd, bt); 1698 } 1699 1700 set_rgb_quantization_range(sd); 1701 1702 1703 if (debug > 1) 1704 v4l2_print_dv_timings(sd->name, "adv7842_s_dv_timings: ", 1705 timings, true); 1706 return 0; 1707 } 1708 1709 static int adv7842_g_dv_timings(struct v4l2_subdev *sd, 1710 struct v4l2_dv_timings *timings) 1711 { 1712 struct adv7842_state *state = to_state(sd); 1713 1714 if (state->mode == ADV7842_MODE_SDP) 1715 return -ENODATA; 1716 *timings = state->timings; 1717 return 0; 1718 } 1719 1720 static void enable_input(struct v4l2_subdev *sd) 1721 { 1722 struct adv7842_state *state = to_state(sd); 1723 1724 set_rgb_quantization_range(sd); 1725 switch (state->mode) { 1726 case ADV7842_MODE_SDP: 1727 case ADV7842_MODE_COMP: 1728 case ADV7842_MODE_RGB: 1729 io_write(sd, 0x15, 0xb0); /* Disable Tristate of Pins (no audio) */ 1730 break; 1731 case ADV7842_MODE_HDMI: 1732 hdmi_write(sd, 0x01, 0x00); /* Enable HDMI clock terminators */ 1733 io_write(sd, 0x15, 0xa0); /* Disable Tristate of Pins */ 1734 hdmi_write_and_or(sd, 0x1a, 0xef, 0x00); /* Unmute audio */ 1735 break; 1736 default: 1737 v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n", 1738 __func__, state->mode); 1739 break; 1740 } 1741 } 1742 1743 static void disable_input(struct v4l2_subdev *sd) 1744 { 1745 hdmi_write_and_or(sd, 0x1a, 0xef, 0x10); /* Mute audio [REF_01, c. 2.2.2] */ 1746 msleep(16); /* 512 samples with >= 32 kHz sample rate [REF_03, c. 8.29] */ 1747 io_write(sd, 0x15, 0xbe); /* Tristate all outputs from video core */ 1748 hdmi_write(sd, 0x01, 0x78); /* Disable HDMI clock terminators */ 1749 } 1750 1751 static void sdp_csc_coeff(struct v4l2_subdev *sd, 1752 const struct adv7842_sdp_csc_coeff *c) 1753 { 1754 /* csc auto/manual */ 1755 sdp_io_write_and_or(sd, 0xe0, 0xbf, c->manual ? 0x00 : 0x40); 1756 1757 if (!c->manual) 1758 return; 1759 1760 /* csc scaling */ 1761 sdp_io_write_and_or(sd, 0xe0, 0x7f, c->scaling == 2 ? 0x80 : 0x00); 1762 1763 /* A coeff */ 1764 sdp_io_write_and_or(sd, 0xe0, 0xe0, c->A1 >> 8); 1765 sdp_io_write(sd, 0xe1, c->A1); 1766 sdp_io_write_and_or(sd, 0xe2, 0xe0, c->A2 >> 8); 1767 sdp_io_write(sd, 0xe3, c->A2); 1768 sdp_io_write_and_or(sd, 0xe4, 0xe0, c->A3 >> 8); 1769 sdp_io_write(sd, 0xe5, c->A3); 1770 1771 /* A scale */ 1772 sdp_io_write_and_or(sd, 0xe6, 0x80, c->A4 >> 8); 1773 sdp_io_write(sd, 0xe7, c->A4); 1774 1775 /* B coeff */ 1776 sdp_io_write_and_or(sd, 0xe8, 0xe0, c->B1 >> 8); 1777 sdp_io_write(sd, 0xe9, c->B1); 1778 sdp_io_write_and_or(sd, 0xea, 0xe0, c->B2 >> 8); 1779 sdp_io_write(sd, 0xeb, c->B2); 1780 sdp_io_write_and_or(sd, 0xec, 0xe0, c->B3 >> 8); 1781 sdp_io_write(sd, 0xed, c->B3); 1782 1783 /* B scale */ 1784 sdp_io_write_and_or(sd, 0xee, 0x80, c->B4 >> 8); 1785 sdp_io_write(sd, 0xef, c->B4); 1786 1787 /* C coeff */ 1788 sdp_io_write_and_or(sd, 0xf0, 0xe0, c->C1 >> 8); 1789 sdp_io_write(sd, 0xf1, c->C1); 1790 sdp_io_write_and_or(sd, 0xf2, 0xe0, c->C2 >> 8); 1791 sdp_io_write(sd, 0xf3, c->C2); 1792 sdp_io_write_and_or(sd, 0xf4, 0xe0, c->C3 >> 8); 1793 sdp_io_write(sd, 0xf5, c->C3); 1794 1795 /* C scale */ 1796 sdp_io_write_and_or(sd, 0xf6, 0x80, c->C4 >> 8); 1797 sdp_io_write(sd, 0xf7, c->C4); 1798 } 1799 1800 static void select_input(struct v4l2_subdev *sd, 1801 enum adv7842_vid_std_select vid_std_select) 1802 { 1803 struct adv7842_state *state = to_state(sd); 1804 1805 switch (state->mode) { 1806 case ADV7842_MODE_SDP: 1807 io_write(sd, 0x00, vid_std_select); /* video std: CVBS or YC mode */ 1808 io_write(sd, 0x01, 0); /* prim mode */ 1809 /* enable embedded syncs for auto graphics mode */ 1810 cp_write_and_or(sd, 0x81, 0xef, 0x10); 1811 1812 afe_write(sd, 0x00, 0x00); /* power up ADC */ 1813 afe_write(sd, 0xc8, 0x00); /* phase control */ 1814 1815 io_write(sd, 0xdd, 0x90); /* Manual 2x output clock */ 1816 /* script says register 0xde, which don't exist in manual */ 1817 1818 /* Manual analog input muxing mode, CVBS (6.4)*/ 1819 afe_write_and_or(sd, 0x02, 0x7f, 0x80); 1820 if (vid_std_select == ADV7842_SDP_VID_STD_CVBS_SD_4x1) { 1821 afe_write(sd, 0x03, 0xa0); /* ADC0 to AIN10 (CVBS), ADC1 N/C*/ 1822 afe_write(sd, 0x04, 0x00); /* ADC2 N/C,ADC3 N/C*/ 1823 } else { 1824 afe_write(sd, 0x03, 0xa0); /* ADC0 to AIN10 (CVBS), ADC1 N/C*/ 1825 afe_write(sd, 0x04, 0xc0); /* ADC2 to AIN12, ADC3 N/C*/ 1826 } 1827 afe_write(sd, 0x0c, 0x1f); /* ADI recommend write */ 1828 afe_write(sd, 0x12, 0x63); /* ADI recommend write */ 1829 1830 sdp_io_write(sd, 0xb2, 0x60); /* Disable AV codes */ 1831 sdp_io_write(sd, 0xc8, 0xe3); /* Disable Ancillary data */ 1832 1833 /* SDP recommended settings */ 1834 sdp_write(sd, 0x00, 0x3F); /* Autodetect PAL NTSC (not SECAM) */ 1835 sdp_write(sd, 0x01, 0x00); /* Pedestal Off */ 1836 1837 sdp_write(sd, 0x03, 0xE4); /* Manual VCR Gain Luma 0x40B */ 1838 sdp_write(sd, 0x04, 0x0B); /* Manual Luma setting */ 1839 sdp_write(sd, 0x05, 0xC3); /* Manual Chroma setting 0x3FE */ 1840 sdp_write(sd, 0x06, 0xFE); /* Manual Chroma setting */ 1841 sdp_write(sd, 0x12, 0x0D); /* Frame TBC,I_P, 3D comb enabled */ 1842 sdp_write(sd, 0xA7, 0x00); /* ADI Recommended Write */ 1843 sdp_io_write(sd, 0xB0, 0x00); /* Disable H and v blanking */ 1844 1845 /* deinterlacer enabled and 3D comb */ 1846 sdp_write_and_or(sd, 0x12, 0xf6, 0x09); 1847 1848 break; 1849 1850 case ADV7842_MODE_COMP: 1851 case ADV7842_MODE_RGB: 1852 /* Automatic analog input muxing mode */ 1853 afe_write_and_or(sd, 0x02, 0x7f, 0x00); 1854 /* set mode and select free run resolution */ 1855 io_write(sd, 0x00, vid_std_select); /* video std */ 1856 io_write(sd, 0x01, 0x02); /* prim mode */ 1857 cp_write_and_or(sd, 0x81, 0xef, 0x10); /* enable embedded syncs 1858 for auto graphics mode */ 1859 1860 afe_write(sd, 0x00, 0x00); /* power up ADC */ 1861 afe_write(sd, 0xc8, 0x00); /* phase control */ 1862 if (state->mode == ADV7842_MODE_COMP) { 1863 /* force to YCrCb */ 1864 io_write_and_or(sd, 0x02, 0x0f, 0x60); 1865 } else { 1866 /* force to RGB */ 1867 io_write_and_or(sd, 0x02, 0x0f, 0x10); 1868 } 1869 1870 /* set ADI recommended settings for digitizer */ 1871 /* "ADV7842 Register Settings Recommendations 1872 * (rev. 1.8, November 2010)" p. 9. */ 1873 afe_write(sd, 0x0c, 0x1f); /* ADC Range improvement */ 1874 afe_write(sd, 0x12, 0x63); /* ADC Range improvement */ 1875 1876 /* set to default gain for RGB */ 1877 cp_write(sd, 0x73, 0x10); 1878 cp_write(sd, 0x74, 0x04); 1879 cp_write(sd, 0x75, 0x01); 1880 cp_write(sd, 0x76, 0x00); 1881 1882 cp_write(sd, 0x3e, 0x04); /* CP core pre-gain control */ 1883 cp_write(sd, 0xc3, 0x39); /* CP coast control. Graphics mode */ 1884 cp_write(sd, 0x40, 0x5c); /* CP core pre-gain control. Graphics mode */ 1885 break; 1886 1887 case ADV7842_MODE_HDMI: 1888 /* Automatic analog input muxing mode */ 1889 afe_write_and_or(sd, 0x02, 0x7f, 0x00); 1890 /* set mode and select free run resolution */ 1891 if (state->hdmi_port_a) 1892 hdmi_write(sd, 0x00, 0x02); /* select port A */ 1893 else 1894 hdmi_write(sd, 0x00, 0x03); /* select port B */ 1895 io_write(sd, 0x00, vid_std_select); /* video std */ 1896 io_write(sd, 0x01, 5); /* prim mode */ 1897 cp_write_and_or(sd, 0x81, 0xef, 0x00); /* disable embedded syncs 1898 for auto graphics mode */ 1899 1900 /* set ADI recommended settings for HDMI: */ 1901 /* "ADV7842 Register Settings Recommendations 1902 * (rev. 1.8, November 2010)" p. 3. */ 1903 hdmi_write(sd, 0xc0, 0x00); 1904 hdmi_write(sd, 0x0d, 0x34); /* ADI recommended write */ 1905 hdmi_write(sd, 0x3d, 0x10); /* ADI recommended write */ 1906 hdmi_write(sd, 0x44, 0x85); /* TMDS PLL optimization */ 1907 hdmi_write(sd, 0x46, 0x1f); /* ADI recommended write */ 1908 hdmi_write(sd, 0x57, 0xb6); /* TMDS PLL optimization */ 1909 hdmi_write(sd, 0x58, 0x03); /* TMDS PLL optimization */ 1910 hdmi_write(sd, 0x60, 0x88); /* TMDS PLL optimization */ 1911 hdmi_write(sd, 0x61, 0x88); /* TMDS PLL optimization */ 1912 hdmi_write(sd, 0x6c, 0x18); /* Disable ISRC clearing bit, 1913 Improve robustness */ 1914 hdmi_write(sd, 0x75, 0x10); /* DDC drive strength */ 1915 hdmi_write(sd, 0x85, 0x1f); /* equaliser */ 1916 hdmi_write(sd, 0x87, 0x70); /* ADI recommended write */ 1917 hdmi_write(sd, 0x89, 0x04); /* equaliser */ 1918 hdmi_write(sd, 0x8a, 0x1e); /* equaliser */ 1919 hdmi_write(sd, 0x93, 0x04); /* equaliser */ 1920 hdmi_write(sd, 0x94, 0x1e); /* equaliser */ 1921 hdmi_write(sd, 0x99, 0xa1); /* ADI recommended write */ 1922 hdmi_write(sd, 0x9b, 0x09); /* ADI recommended write */ 1923 hdmi_write(sd, 0x9d, 0x02); /* equaliser */ 1924 1925 afe_write(sd, 0x00, 0xff); /* power down ADC */ 1926 afe_write(sd, 0xc8, 0x40); /* phase control */ 1927 1928 /* set to default gain for HDMI */ 1929 cp_write(sd, 0x73, 0x10); 1930 cp_write(sd, 0x74, 0x04); 1931 cp_write(sd, 0x75, 0x01); 1932 cp_write(sd, 0x76, 0x00); 1933 1934 /* reset ADI recommended settings for digitizer */ 1935 /* "ADV7842 Register Settings Recommendations 1936 * (rev. 2.5, June 2010)" p. 17. */ 1937 afe_write(sd, 0x12, 0xfb); /* ADC noise shaping filter controls */ 1938 afe_write(sd, 0x0c, 0x0d); /* CP core gain controls */ 1939 cp_write(sd, 0x3e, 0x00); /* CP core pre-gain control */ 1940 1941 /* CP coast control */ 1942 cp_write(sd, 0xc3, 0x33); /* Component mode */ 1943 1944 /* color space conversion, autodetect color space */ 1945 io_write_and_or(sd, 0x02, 0x0f, 0xf0); 1946 break; 1947 1948 default: 1949 v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n", 1950 __func__, state->mode); 1951 break; 1952 } 1953 } 1954 1955 static int adv7842_s_routing(struct v4l2_subdev *sd, 1956 u32 input, u32 output, u32 config) 1957 { 1958 struct adv7842_state *state = to_state(sd); 1959 1960 v4l2_dbg(2, debug, sd, "%s: input %d\n", __func__, input); 1961 1962 switch (input) { 1963 case ADV7842_SELECT_HDMI_PORT_A: 1964 state->mode = ADV7842_MODE_HDMI; 1965 state->vid_std_select = ADV7842_HDMI_COMP_VID_STD_HD_1250P; 1966 state->hdmi_port_a = true; 1967 break; 1968 case ADV7842_SELECT_HDMI_PORT_B: 1969 state->mode = ADV7842_MODE_HDMI; 1970 state->vid_std_select = ADV7842_HDMI_COMP_VID_STD_HD_1250P; 1971 state->hdmi_port_a = false; 1972 break; 1973 case ADV7842_SELECT_VGA_COMP: 1974 state->mode = ADV7842_MODE_COMP; 1975 state->vid_std_select = ADV7842_RGB_VID_STD_AUTO_GRAPH_MODE; 1976 break; 1977 case ADV7842_SELECT_VGA_RGB: 1978 state->mode = ADV7842_MODE_RGB; 1979 state->vid_std_select = ADV7842_RGB_VID_STD_AUTO_GRAPH_MODE; 1980 break; 1981 case ADV7842_SELECT_SDP_CVBS: 1982 state->mode = ADV7842_MODE_SDP; 1983 state->vid_std_select = ADV7842_SDP_VID_STD_CVBS_SD_4x1; 1984 break; 1985 case ADV7842_SELECT_SDP_YC: 1986 state->mode = ADV7842_MODE_SDP; 1987 state->vid_std_select = ADV7842_SDP_VID_STD_YC_SD4_x1; 1988 break; 1989 default: 1990 return -EINVAL; 1991 } 1992 1993 disable_input(sd); 1994 select_input(sd, state->vid_std_select); 1995 enable_input(sd); 1996 1997 v4l2_subdev_notify_event(sd, &adv7842_ev_fmt); 1998 1999 return 0; 2000 } 2001 2002 static int adv7842_enum_mbus_code(struct v4l2_subdev *sd, 2003 struct v4l2_subdev_pad_config *cfg, 2004 struct v4l2_subdev_mbus_code_enum *code) 2005 { 2006 if (code->index >= ARRAY_SIZE(adv7842_formats)) 2007 return -EINVAL; 2008 code->code = adv7842_formats[code->index].code; 2009 return 0; 2010 } 2011 2012 static void adv7842_fill_format(struct adv7842_state *state, 2013 struct v4l2_mbus_framefmt *format) 2014 { 2015 memset(format, 0, sizeof(*format)); 2016 2017 format->width = state->timings.bt.width; 2018 format->height = state->timings.bt.height; 2019 format->field = V4L2_FIELD_NONE; 2020 format->colorspace = V4L2_COLORSPACE_SRGB; 2021 2022 if (state->timings.bt.flags & V4L2_DV_FL_IS_CE_VIDEO) 2023 format->colorspace = (state->timings.bt.height <= 576) ? 2024 V4L2_COLORSPACE_SMPTE170M : V4L2_COLORSPACE_REC709; 2025 } 2026 2027 /* 2028 * Compute the op_ch_sel value required to obtain on the bus the component order 2029 * corresponding to the selected format taking into account bus reordering 2030 * applied by the board at the output of the device. 2031 * 2032 * The following table gives the op_ch_value from the format component order 2033 * (expressed as op_ch_sel value in column) and the bus reordering (expressed as 2034 * adv7842_bus_order value in row). 2035 * 2036 * | GBR(0) GRB(1) BGR(2) RGB(3) BRG(4) RBG(5) 2037 * ----------+------------------------------------------------- 2038 * RGB (NOP) | GBR GRB BGR RGB BRG RBG 2039 * GRB (1-2) | BGR RGB GBR GRB RBG BRG 2040 * RBG (2-3) | GRB GBR BRG RBG BGR RGB 2041 * BGR (1-3) | RBG BRG RGB BGR GRB GBR 2042 * BRG (ROR) | BRG RBG GRB GBR RGB BGR 2043 * GBR (ROL) | RGB BGR RBG BRG GBR GRB 2044 */ 2045 static unsigned int adv7842_op_ch_sel(struct adv7842_state *state) 2046 { 2047 #define _SEL(a, b, c, d, e, f) { \ 2048 ADV7842_OP_CH_SEL_##a, ADV7842_OP_CH_SEL_##b, ADV7842_OP_CH_SEL_##c, \ 2049 ADV7842_OP_CH_SEL_##d, ADV7842_OP_CH_SEL_##e, ADV7842_OP_CH_SEL_##f } 2050 #define _BUS(x) [ADV7842_BUS_ORDER_##x] 2051 2052 static const unsigned int op_ch_sel[6][6] = { 2053 _BUS(RGB) /* NOP */ = _SEL(GBR, GRB, BGR, RGB, BRG, RBG), 2054 _BUS(GRB) /* 1-2 */ = _SEL(BGR, RGB, GBR, GRB, RBG, BRG), 2055 _BUS(RBG) /* 2-3 */ = _SEL(GRB, GBR, BRG, RBG, BGR, RGB), 2056 _BUS(BGR) /* 1-3 */ = _SEL(RBG, BRG, RGB, BGR, GRB, GBR), 2057 _BUS(BRG) /* ROR */ = _SEL(BRG, RBG, GRB, GBR, RGB, BGR), 2058 _BUS(GBR) /* ROL */ = _SEL(RGB, BGR, RBG, BRG, GBR, GRB), 2059 }; 2060 2061 return op_ch_sel[state->pdata.bus_order][state->format->op_ch_sel >> 5]; 2062 } 2063 2064 static void adv7842_setup_format(struct adv7842_state *state) 2065 { 2066 struct v4l2_subdev *sd = &state->sd; 2067 2068 io_write_clr_set(sd, 0x02, 0x02, 2069 state->format->rgb_out ? ADV7842_RGB_OUT : 0); 2070 io_write(sd, 0x03, state->format->op_format_sel | 2071 state->pdata.op_format_mode_sel); 2072 io_write_clr_set(sd, 0x04, 0xe0, adv7842_op_ch_sel(state)); 2073 io_write_clr_set(sd, 0x05, 0x01, 2074 state->format->swap_cb_cr ? ADV7842_OP_SWAP_CB_CR : 0); 2075 } 2076 2077 static int adv7842_get_format(struct v4l2_subdev *sd, 2078 struct v4l2_subdev_pad_config *cfg, 2079 struct v4l2_subdev_format *format) 2080 { 2081 struct adv7842_state *state = to_state(sd); 2082 2083 if (format->pad != ADV7842_PAD_SOURCE) 2084 return -EINVAL; 2085 2086 if (state->mode == ADV7842_MODE_SDP) { 2087 /* SPD block */ 2088 if (!(sdp_read(sd, 0x5a) & 0x01)) 2089 return -EINVAL; 2090 format->format.code = MEDIA_BUS_FMT_YUYV8_2X8; 2091 format->format.width = 720; 2092 /* valid signal */ 2093 if (state->norm & V4L2_STD_525_60) 2094 format->format.height = 480; 2095 else 2096 format->format.height = 576; 2097 format->format.colorspace = V4L2_COLORSPACE_SMPTE170M; 2098 return 0; 2099 } 2100 2101 adv7842_fill_format(state, &format->format); 2102 2103 if (format->which == V4L2_SUBDEV_FORMAT_TRY) { 2104 struct v4l2_mbus_framefmt *fmt; 2105 2106 fmt = v4l2_subdev_get_try_format(sd, cfg, format->pad); 2107 format->format.code = fmt->code; 2108 } else { 2109 format->format.code = state->format->code; 2110 } 2111 2112 return 0; 2113 } 2114 2115 static int adv7842_set_format(struct v4l2_subdev *sd, 2116 struct v4l2_subdev_pad_config *cfg, 2117 struct v4l2_subdev_format *format) 2118 { 2119 struct adv7842_state *state = to_state(sd); 2120 const struct adv7842_format_info *info; 2121 2122 if (format->pad != ADV7842_PAD_SOURCE) 2123 return -EINVAL; 2124 2125 if (state->mode == ADV7842_MODE_SDP) 2126 return adv7842_get_format(sd, cfg, format); 2127 2128 info = adv7842_format_info(state, format->format.code); 2129 if (info == NULL) 2130 info = adv7842_format_info(state, MEDIA_BUS_FMT_YUYV8_2X8); 2131 2132 adv7842_fill_format(state, &format->format); 2133 format->format.code = info->code; 2134 2135 if (format->which == V4L2_SUBDEV_FORMAT_TRY) { 2136 struct v4l2_mbus_framefmt *fmt; 2137 2138 fmt = v4l2_subdev_get_try_format(sd, cfg, format->pad); 2139 fmt->code = format->format.code; 2140 } else { 2141 state->format = info; 2142 adv7842_setup_format(state); 2143 } 2144 2145 return 0; 2146 } 2147 2148 static void adv7842_irq_enable(struct v4l2_subdev *sd, bool enable) 2149 { 2150 if (enable) { 2151 /* Enable SSPD, STDI and CP locked/unlocked interrupts */ 2152 io_write(sd, 0x46, 0x9c); 2153 /* ESDP_50HZ_DET interrupt */ 2154 io_write(sd, 0x5a, 0x10); 2155 /* Enable CABLE_DET_A/B_ST (+5v) interrupt */ 2156 io_write(sd, 0x73, 0x03); 2157 /* Enable V_LOCKED and DE_REGEN_LCK interrupts */ 2158 io_write(sd, 0x78, 0x03); 2159 /* Enable SDP Standard Detection Change and SDP Video Detected */ 2160 io_write(sd, 0xa0, 0x09); 2161 /* Enable HDMI_MODE interrupt */ 2162 io_write(sd, 0x69, 0x08); 2163 } else { 2164 io_write(sd, 0x46, 0x0); 2165 io_write(sd, 0x5a, 0x0); 2166 io_write(sd, 0x73, 0x0); 2167 io_write(sd, 0x78, 0x0); 2168 io_write(sd, 0xa0, 0x0); 2169 io_write(sd, 0x69, 0x0); 2170 } 2171 } 2172 2173 static int adv7842_isr(struct v4l2_subdev *sd, u32 status, bool *handled) 2174 { 2175 struct adv7842_state *state = to_state(sd); 2176 u8 fmt_change_cp, fmt_change_digital, fmt_change_sdp; 2177 u8 irq_status[6]; 2178 2179 adv7842_irq_enable(sd, false); 2180 2181 /* read status */ 2182 irq_status[0] = io_read(sd, 0x43); 2183 irq_status[1] = io_read(sd, 0x57); 2184 irq_status[2] = io_read(sd, 0x70); 2185 irq_status[3] = io_read(sd, 0x75); 2186 irq_status[4] = io_read(sd, 0x9d); 2187 irq_status[5] = io_read(sd, 0x66); 2188 2189 /* and clear */ 2190 if (irq_status[0]) 2191 io_write(sd, 0x44, irq_status[0]); 2192 if (irq_status[1]) 2193 io_write(sd, 0x58, irq_status[1]); 2194 if (irq_status[2]) 2195 io_write(sd, 0x71, irq_status[2]); 2196 if (irq_status[3]) 2197 io_write(sd, 0x76, irq_status[3]); 2198 if (irq_status[4]) 2199 io_write(sd, 0x9e, irq_status[4]); 2200 if (irq_status[5]) 2201 io_write(sd, 0x67, irq_status[5]); 2202 2203 adv7842_irq_enable(sd, true); 2204 2205 v4l2_dbg(1, debug, sd, "%s: irq %x, %x, %x, %x, %x, %x\n", __func__, 2206 irq_status[0], irq_status[1], irq_status[2], 2207 irq_status[3], irq_status[4], irq_status[5]); 2208 2209 /* format change CP */ 2210 fmt_change_cp = irq_status[0] & 0x9c; 2211 2212 /* format change SDP */ 2213 if (state->mode == ADV7842_MODE_SDP) 2214 fmt_change_sdp = (irq_status[1] & 0x30) | (irq_status[4] & 0x09); 2215 else 2216 fmt_change_sdp = 0; 2217 2218 /* digital format CP */ 2219 if (is_digital_input(sd)) 2220 fmt_change_digital = irq_status[3] & 0x03; 2221 else 2222 fmt_change_digital = 0; 2223 2224 /* format change */ 2225 if (fmt_change_cp || fmt_change_digital || fmt_change_sdp) { 2226 v4l2_dbg(1, debug, sd, 2227 "%s: fmt_change_cp = 0x%x, fmt_change_digital = 0x%x, fmt_change_sdp = 0x%x\n", 2228 __func__, fmt_change_cp, fmt_change_digital, 2229 fmt_change_sdp); 2230 v4l2_subdev_notify_event(sd, &adv7842_ev_fmt); 2231 if (handled) 2232 *handled = true; 2233 } 2234 2235 /* HDMI/DVI mode */ 2236 if (irq_status[5] & 0x08) { 2237 v4l2_dbg(1, debug, sd, "%s: irq %s mode\n", __func__, 2238 (io_read(sd, 0x65) & 0x08) ? "HDMI" : "DVI"); 2239 set_rgb_quantization_range(sd); 2240 if (handled) 2241 *handled = true; 2242 } 2243 2244 /* tx 5v detect */ 2245 if (irq_status[2] & 0x3) { 2246 v4l2_dbg(1, debug, sd, "%s: irq tx_5v\n", __func__); 2247 adv7842_s_detect_tx_5v_ctrl(sd); 2248 if (handled) 2249 *handled = true; 2250 } 2251 return 0; 2252 } 2253 2254 static int adv7842_get_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid) 2255 { 2256 struct adv7842_state *state = to_state(sd); 2257 u8 *data = NULL; 2258 2259 memset(edid->reserved, 0, sizeof(edid->reserved)); 2260 2261 switch (edid->pad) { 2262 case ADV7842_EDID_PORT_A: 2263 case ADV7842_EDID_PORT_B: 2264 if (state->hdmi_edid.present & (0x04 << edid->pad)) 2265 data = state->hdmi_edid.edid; 2266 break; 2267 case ADV7842_EDID_PORT_VGA: 2268 if (state->vga_edid.present) 2269 data = state->vga_edid.edid; 2270 break; 2271 default: 2272 return -EINVAL; 2273 } 2274 2275 if (edid->start_block == 0 && edid->blocks == 0) { 2276 edid->blocks = data ? 2 : 0; 2277 return 0; 2278 } 2279 2280 if (!data) 2281 return -ENODATA; 2282 2283 if (edid->start_block >= 2) 2284 return -EINVAL; 2285 2286 if (edid->start_block + edid->blocks > 2) 2287 edid->blocks = 2 - edid->start_block; 2288 2289 memcpy(edid->edid, data + edid->start_block * 128, edid->blocks * 128); 2290 2291 return 0; 2292 } 2293 2294 static int adv7842_set_edid(struct v4l2_subdev *sd, struct v4l2_edid *e) 2295 { 2296 struct adv7842_state *state = to_state(sd); 2297 int err = 0; 2298 2299 memset(e->reserved, 0, sizeof(e->reserved)); 2300 2301 if (e->pad > ADV7842_EDID_PORT_VGA) 2302 return -EINVAL; 2303 if (e->start_block != 0) 2304 return -EINVAL; 2305 if (e->blocks > 2) { 2306 e->blocks = 2; 2307 return -E2BIG; 2308 } 2309 2310 /* todo, per edid */ 2311 state->aspect_ratio = v4l2_calc_aspect_ratio(e->edid[0x15], 2312 e->edid[0x16]); 2313 2314 switch (e->pad) { 2315 case ADV7842_EDID_PORT_VGA: 2316 memset(&state->vga_edid.edid, 0, 256); 2317 state->vga_edid.present = e->blocks ? 0x1 : 0x0; 2318 memcpy(&state->vga_edid.edid, e->edid, 128 * e->blocks); 2319 err = edid_write_vga_segment(sd); 2320 break; 2321 case ADV7842_EDID_PORT_A: 2322 case ADV7842_EDID_PORT_B: 2323 memset(&state->hdmi_edid.edid, 0, 256); 2324 if (e->blocks) 2325 state->hdmi_edid.present |= 0x04 << e->pad; 2326 else 2327 state->hdmi_edid.present &= ~(0x04 << e->pad); 2328 memcpy(&state->hdmi_edid.edid, e->edid, 128 * e->blocks); 2329 err = edid_write_hdmi_segment(sd, e->pad); 2330 break; 2331 default: 2332 return -EINVAL; 2333 } 2334 if (err < 0) 2335 v4l2_err(sd, "error %d writing edid on port %d\n", err, e->pad); 2336 return err; 2337 } 2338 2339 struct adv7842_cfg_read_infoframe { 2340 const char *desc; 2341 u8 present_mask; 2342 u8 head_addr; 2343 u8 payload_addr; 2344 }; 2345 2346 static void log_infoframe(struct v4l2_subdev *sd, struct adv7842_cfg_read_infoframe *cri) 2347 { 2348 int i; 2349 u8 buffer[32]; 2350 union hdmi_infoframe frame; 2351 u8 len; 2352 struct i2c_client *client = v4l2_get_subdevdata(sd); 2353 struct device *dev = &client->dev; 2354 2355 if (!(io_read(sd, 0x60) & cri->present_mask)) { 2356 v4l2_info(sd, "%s infoframe not received\n", cri->desc); 2357 return; 2358 } 2359 2360 for (i = 0; i < 3; i++) 2361 buffer[i] = infoframe_read(sd, cri->head_addr + i); 2362 2363 len = buffer[2] + 1; 2364 2365 if (len + 3 > sizeof(buffer)) { 2366 v4l2_err(sd, "%s: invalid %s infoframe length %d\n", __func__, cri->desc, len); 2367 return; 2368 } 2369 2370 for (i = 0; i < len; i++) 2371 buffer[i + 3] = infoframe_read(sd, cri->payload_addr + i); 2372 2373 if (hdmi_infoframe_unpack(&frame, buffer) < 0) { 2374 v4l2_err(sd, "%s: unpack of %s infoframe failed\n", __func__, cri->desc); 2375 return; 2376 } 2377 2378 hdmi_infoframe_log(KERN_INFO, dev, &frame); 2379 } 2380 2381 static void adv7842_log_infoframes(struct v4l2_subdev *sd) 2382 { 2383 int i; 2384 struct adv7842_cfg_read_infoframe cri[] = { 2385 { "AVI", 0x01, 0xe0, 0x00 }, 2386 { "Audio", 0x02, 0xe3, 0x1c }, 2387 { "SDP", 0x04, 0xe6, 0x2a }, 2388 { "Vendor", 0x10, 0xec, 0x54 } 2389 }; 2390 2391 if (!(hdmi_read(sd, 0x05) & 0x80)) { 2392 v4l2_info(sd, "receive DVI-D signal, no infoframes\n"); 2393 return; 2394 } 2395 2396 for (i = 0; i < ARRAY_SIZE(cri); i++) 2397 log_infoframe(sd, &cri[i]); 2398 } 2399 2400 static const char * const prim_mode_txt[] = { 2401 "SDP", 2402 "Component", 2403 "Graphics", 2404 "Reserved", 2405 "CVBS & HDMI AUDIO", 2406 "HDMI-Comp", 2407 "HDMI-GR", 2408 "Reserved", 2409 "Reserved", 2410 "Reserved", 2411 "Reserved", 2412 "Reserved", 2413 "Reserved", 2414 "Reserved", 2415 "Reserved", 2416 "Reserved", 2417 }; 2418 2419 static int adv7842_sdp_log_status(struct v4l2_subdev *sd) 2420 { 2421 /* SDP (Standard definition processor) block */ 2422 u8 sdp_signal_detected = sdp_read(sd, 0x5A) & 0x01; 2423 2424 v4l2_info(sd, "Chip powered %s\n", no_power(sd) ? "off" : "on"); 2425 v4l2_info(sd, "Prim-mode = 0x%x, video std = 0x%x\n", 2426 io_read(sd, 0x01) & 0x0f, io_read(sd, 0x00) & 0x3f); 2427 2428 v4l2_info(sd, "SDP: free run: %s\n", 2429 (sdp_read(sd, 0x56) & 0x01) ? "on" : "off"); 2430 v4l2_info(sd, "SDP: %s\n", sdp_signal_detected ? 2431 "valid SD/PR signal detected" : "invalid/no signal"); 2432 if (sdp_signal_detected) { 2433 static const char * const sdp_std_txt[] = { 2434 "NTSC-M/J", 2435 "1?", 2436 "NTSC-443", 2437 "60HzSECAM", 2438 "PAL-M", 2439 "5?", 2440 "PAL-60", 2441 "7?", "8?", "9?", "a?", "b?", 2442 "PAL-CombN", 2443 "d?", 2444 "PAL-BGHID", 2445 "SECAM" 2446 }; 2447 v4l2_info(sd, "SDP: standard %s\n", 2448 sdp_std_txt[sdp_read(sd, 0x52) & 0x0f]); 2449 v4l2_info(sd, "SDP: %s\n", 2450 (sdp_read(sd, 0x59) & 0x08) ? "50Hz" : "60Hz"); 2451 v4l2_info(sd, "SDP: %s\n", 2452 (sdp_read(sd, 0x57) & 0x08) ? "Interlaced" : "Progressive"); 2453 v4l2_info(sd, "SDP: deinterlacer %s\n", 2454 (sdp_read(sd, 0x12) & 0x08) ? "enabled" : "disabled"); 2455 v4l2_info(sd, "SDP: csc %s mode\n", 2456 (sdp_io_read(sd, 0xe0) & 0x40) ? "auto" : "manual"); 2457 } 2458 return 0; 2459 } 2460 2461 static int adv7842_cp_log_status(struct v4l2_subdev *sd) 2462 { 2463 /* CP block */ 2464 struct adv7842_state *state = to_state(sd); 2465 struct v4l2_dv_timings timings; 2466 u8 reg_io_0x02 = io_read(sd, 0x02); 2467 u8 reg_io_0x21 = io_read(sd, 0x21); 2468 u8 reg_rep_0x77 = rep_read(sd, 0x77); 2469 u8 reg_rep_0x7d = rep_read(sd, 0x7d); 2470 bool audio_pll_locked = hdmi_read(sd, 0x04) & 0x01; 2471 bool audio_sample_packet_detect = hdmi_read(sd, 0x18) & 0x01; 2472 bool audio_mute = io_read(sd, 0x65) & 0x40; 2473 2474 static const char * const csc_coeff_sel_rb[16] = { 2475 "bypassed", "YPbPr601 -> RGB", "reserved", "YPbPr709 -> RGB", 2476 "reserved", "RGB -> YPbPr601", "reserved", "RGB -> YPbPr709", 2477 "reserved", "YPbPr709 -> YPbPr601", "YPbPr601 -> YPbPr709", 2478 "reserved", "reserved", "reserved", "reserved", "manual" 2479 }; 2480 static const char * const input_color_space_txt[16] = { 2481 "RGB limited range (16-235)", "RGB full range (0-255)", 2482 "YCbCr Bt.601 (16-235)", "YCbCr Bt.709 (16-235)", 2483 "xvYCC Bt.601", "xvYCC Bt.709", 2484 "YCbCr Bt.601 (0-255)", "YCbCr Bt.709 (0-255)", 2485 "invalid", "invalid", "invalid", "invalid", "invalid", 2486 "invalid", "invalid", "automatic" 2487 }; 2488 static const char * const rgb_quantization_range_txt[] = { 2489 "Automatic", 2490 "RGB limited range (16-235)", 2491 "RGB full range (0-255)", 2492 }; 2493 static const char * const deep_color_mode_txt[4] = { 2494 "8-bits per channel", 2495 "10-bits per channel", 2496 "12-bits per channel", 2497 "16-bits per channel (not supported)" 2498 }; 2499 2500 v4l2_info(sd, "-----Chip status-----\n"); 2501 v4l2_info(sd, "Chip power: %s\n", no_power(sd) ? "off" : "on"); 2502 v4l2_info(sd, "HDMI/DVI-D port selected: %s\n", 2503 state->hdmi_port_a ? "A" : "B"); 2504 v4l2_info(sd, "EDID A %s, B %s\n", 2505 ((reg_rep_0x7d & 0x04) && (reg_rep_0x77 & 0x04)) ? 2506 "enabled" : "disabled", 2507 ((reg_rep_0x7d & 0x08) && (reg_rep_0x77 & 0x08)) ? 2508 "enabled" : "disabled"); 2509 v4l2_info(sd, "HPD A %s, B %s\n", 2510 reg_io_0x21 & 0x02 ? "enabled" : "disabled", 2511 reg_io_0x21 & 0x01 ? "enabled" : "disabled"); 2512 v4l2_info(sd, "CEC %s\n", !!(cec_read(sd, 0x2a) & 0x01) ? 2513 "enabled" : "disabled"); 2514 2515 v4l2_info(sd, "-----Signal status-----\n"); 2516 if (state->hdmi_port_a) { 2517 v4l2_info(sd, "Cable detected (+5V power): %s\n", 2518 io_read(sd, 0x6f) & 0x02 ? "true" : "false"); 2519 v4l2_info(sd, "TMDS signal detected: %s\n", 2520 (io_read(sd, 0x6a) & 0x02) ? "true" : "false"); 2521 v4l2_info(sd, "TMDS signal locked: %s\n", 2522 (io_read(sd, 0x6a) & 0x20) ? "true" : "false"); 2523 } else { 2524 v4l2_info(sd, "Cable detected (+5V power):%s\n", 2525 io_read(sd, 0x6f) & 0x01 ? "true" : "false"); 2526 v4l2_info(sd, "TMDS signal detected: %s\n", 2527 (io_read(sd, 0x6a) & 0x01) ? "true" : "false"); 2528 v4l2_info(sd, "TMDS signal locked: %s\n", 2529 (io_read(sd, 0x6a) & 0x10) ? "true" : "false"); 2530 } 2531 v4l2_info(sd, "CP free run: %s\n", 2532 (!!(cp_read(sd, 0xff) & 0x10) ? "on" : "off")); 2533 v4l2_info(sd, "Prim-mode = 0x%x, video std = 0x%x, v_freq = 0x%x\n", 2534 io_read(sd, 0x01) & 0x0f, io_read(sd, 0x00) & 0x3f, 2535 (io_read(sd, 0x01) & 0x70) >> 4); 2536 2537 v4l2_info(sd, "-----Video Timings-----\n"); 2538 if (no_cp_signal(sd)) { 2539 v4l2_info(sd, "STDI: not locked\n"); 2540 } else { 2541 u32 bl = ((cp_read(sd, 0xb1) & 0x3f) << 8) | cp_read(sd, 0xb2); 2542 u32 lcf = ((cp_read(sd, 0xb3) & 0x7) << 8) | cp_read(sd, 0xb4); 2543 u32 lcvs = cp_read(sd, 0xb3) >> 3; 2544 u32 fcl = ((cp_read(sd, 0xb8) & 0x1f) << 8) | cp_read(sd, 0xb9); 2545 char hs_pol = ((cp_read(sd, 0xb5) & 0x10) ? 2546 ((cp_read(sd, 0xb5) & 0x08) ? '+' : '-') : 'x'); 2547 char vs_pol = ((cp_read(sd, 0xb5) & 0x40) ? 2548 ((cp_read(sd, 0xb5) & 0x20) ? '+' : '-') : 'x'); 2549 v4l2_info(sd, 2550 "STDI: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, fcl = %d, %s, %chsync, %cvsync\n", 2551 lcf, bl, lcvs, fcl, 2552 (cp_read(sd, 0xb1) & 0x40) ? 2553 "interlaced" : "progressive", 2554 hs_pol, vs_pol); 2555 } 2556 if (adv7842_query_dv_timings(sd, &timings)) 2557 v4l2_info(sd, "No video detected\n"); 2558 else 2559 v4l2_print_dv_timings(sd->name, "Detected format: ", 2560 &timings, true); 2561 v4l2_print_dv_timings(sd->name, "Configured format: ", 2562 &state->timings, true); 2563 2564 if (no_cp_signal(sd)) 2565 return 0; 2566 2567 v4l2_info(sd, "-----Color space-----\n"); 2568 v4l2_info(sd, "RGB quantization range ctrl: %s\n", 2569 rgb_quantization_range_txt[state->rgb_quantization_range]); 2570 v4l2_info(sd, "Input color space: %s\n", 2571 input_color_space_txt[reg_io_0x02 >> 4]); 2572 v4l2_info(sd, "Output color space: %s %s, saturator %s\n", 2573 (reg_io_0x02 & 0x02) ? "RGB" : "YCbCr", 2574 (reg_io_0x02 & 0x04) ? "(16-235)" : "(0-255)", 2575 ((reg_io_0x02 & 0x04) ^ (reg_io_0x02 & 0x01)) ? 2576 "enabled" : "disabled"); 2577 v4l2_info(sd, "Color space conversion: %s\n", 2578 csc_coeff_sel_rb[cp_read(sd, 0xf4) >> 4]); 2579 2580 if (!is_digital_input(sd)) 2581 return 0; 2582 2583 v4l2_info(sd, "-----%s status-----\n", is_hdmi(sd) ? "HDMI" : "DVI-D"); 2584 v4l2_info(sd, "HDCP encrypted content: %s\n", 2585 (hdmi_read(sd, 0x05) & 0x40) ? "true" : "false"); 2586 v4l2_info(sd, "HDCP keys read: %s%s\n", 2587 (hdmi_read(sd, 0x04) & 0x20) ? "yes" : "no", 2588 (hdmi_read(sd, 0x04) & 0x10) ? "ERROR" : ""); 2589 if (!is_hdmi(sd)) 2590 return 0; 2591 2592 v4l2_info(sd, "Audio: pll %s, samples %s, %s\n", 2593 audio_pll_locked ? "locked" : "not locked", 2594 audio_sample_packet_detect ? "detected" : "not detected", 2595 audio_mute ? "muted" : "enabled"); 2596 if (audio_pll_locked && audio_sample_packet_detect) { 2597 v4l2_info(sd, "Audio format: %s\n", 2598 (hdmi_read(sd, 0x07) & 0x40) ? "multi-channel" : "stereo"); 2599 } 2600 v4l2_info(sd, "Audio CTS: %u\n", (hdmi_read(sd, 0x5b) << 12) + 2601 (hdmi_read(sd, 0x5c) << 8) + 2602 (hdmi_read(sd, 0x5d) & 0xf0)); 2603 v4l2_info(sd, "Audio N: %u\n", ((hdmi_read(sd, 0x5d) & 0x0f) << 16) + 2604 (hdmi_read(sd, 0x5e) << 8) + 2605 hdmi_read(sd, 0x5f)); 2606 v4l2_info(sd, "AV Mute: %s\n", 2607 (hdmi_read(sd, 0x04) & 0x40) ? "on" : "off"); 2608 v4l2_info(sd, "Deep color mode: %s\n", 2609 deep_color_mode_txt[hdmi_read(sd, 0x0b) >> 6]); 2610 2611 adv7842_log_infoframes(sd); 2612 2613 return 0; 2614 } 2615 2616 static int adv7842_log_status(struct v4l2_subdev *sd) 2617 { 2618 struct adv7842_state *state = to_state(sd); 2619 2620 if (state->mode == ADV7842_MODE_SDP) 2621 return adv7842_sdp_log_status(sd); 2622 return adv7842_cp_log_status(sd); 2623 } 2624 2625 static int adv7842_querystd(struct v4l2_subdev *sd, v4l2_std_id *std) 2626 { 2627 struct adv7842_state *state = to_state(sd); 2628 2629 v4l2_dbg(1, debug, sd, "%s:\n", __func__); 2630 2631 if (state->mode != ADV7842_MODE_SDP) 2632 return -ENODATA; 2633 2634 if (!(sdp_read(sd, 0x5A) & 0x01)) { 2635 *std = 0; 2636 v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__); 2637 return 0; 2638 } 2639 2640 switch (sdp_read(sd, 0x52) & 0x0f) { 2641 case 0: 2642 /* NTSC-M/J */ 2643 *std &= V4L2_STD_NTSC; 2644 break; 2645 case 2: 2646 /* NTSC-443 */ 2647 *std &= V4L2_STD_NTSC_443; 2648 break; 2649 case 3: 2650 /* 60HzSECAM */ 2651 *std &= V4L2_STD_SECAM; 2652 break; 2653 case 4: 2654 /* PAL-M */ 2655 *std &= V4L2_STD_PAL_M; 2656 break; 2657 case 6: 2658 /* PAL-60 */ 2659 *std &= V4L2_STD_PAL_60; 2660 break; 2661 case 0xc: 2662 /* PAL-CombN */ 2663 *std &= V4L2_STD_PAL_Nc; 2664 break; 2665 case 0xe: 2666 /* PAL-BGHID */ 2667 *std &= V4L2_STD_PAL; 2668 break; 2669 case 0xf: 2670 /* SECAM */ 2671 *std &= V4L2_STD_SECAM; 2672 break; 2673 default: 2674 *std &= V4L2_STD_ALL; 2675 break; 2676 } 2677 return 0; 2678 } 2679 2680 static void adv7842_s_sdp_io(struct v4l2_subdev *sd, struct adv7842_sdp_io_sync_adjustment *s) 2681 { 2682 if (s && s->adjust) { 2683 sdp_io_write(sd, 0x94, (s->hs_beg >> 8) & 0xf); 2684 sdp_io_write(sd, 0x95, s->hs_beg & 0xff); 2685 sdp_io_write(sd, 0x96, (s->hs_width >> 8) & 0xf); 2686 sdp_io_write(sd, 0x97, s->hs_width & 0xff); 2687 sdp_io_write(sd, 0x98, (s->de_beg >> 8) & 0xf); 2688 sdp_io_write(sd, 0x99, s->de_beg & 0xff); 2689 sdp_io_write(sd, 0x9a, (s->de_end >> 8) & 0xf); 2690 sdp_io_write(sd, 0x9b, s->de_end & 0xff); 2691 sdp_io_write(sd, 0xa8, s->vs_beg_o); 2692 sdp_io_write(sd, 0xa9, s->vs_beg_e); 2693 sdp_io_write(sd, 0xaa, s->vs_end_o); 2694 sdp_io_write(sd, 0xab, s->vs_end_e); 2695 sdp_io_write(sd, 0xac, s->de_v_beg_o); 2696 sdp_io_write(sd, 0xad, s->de_v_beg_e); 2697 sdp_io_write(sd, 0xae, s->de_v_end_o); 2698 sdp_io_write(sd, 0xaf, s->de_v_end_e); 2699 } else { 2700 /* set to default */ 2701 sdp_io_write(sd, 0x94, 0x00); 2702 sdp_io_write(sd, 0x95, 0x00); 2703 sdp_io_write(sd, 0x96, 0x00); 2704 sdp_io_write(sd, 0x97, 0x20); 2705 sdp_io_write(sd, 0x98, 0x00); 2706 sdp_io_write(sd, 0x99, 0x00); 2707 sdp_io_write(sd, 0x9a, 0x00); 2708 sdp_io_write(sd, 0x9b, 0x00); 2709 sdp_io_write(sd, 0xa8, 0x04); 2710 sdp_io_write(sd, 0xa9, 0x04); 2711 sdp_io_write(sd, 0xaa, 0x04); 2712 sdp_io_write(sd, 0xab, 0x04); 2713 sdp_io_write(sd, 0xac, 0x04); 2714 sdp_io_write(sd, 0xad, 0x04); 2715 sdp_io_write(sd, 0xae, 0x04); 2716 sdp_io_write(sd, 0xaf, 0x04); 2717 } 2718 } 2719 2720 static int adv7842_s_std(struct v4l2_subdev *sd, v4l2_std_id norm) 2721 { 2722 struct adv7842_state *state = to_state(sd); 2723 struct adv7842_platform_data *pdata = &state->pdata; 2724 2725 v4l2_dbg(1, debug, sd, "%s:\n", __func__); 2726 2727 if (state->mode != ADV7842_MODE_SDP) 2728 return -ENODATA; 2729 2730 if (norm & V4L2_STD_625_50) 2731 adv7842_s_sdp_io(sd, &pdata->sdp_io_sync_625); 2732 else if (norm & V4L2_STD_525_60) 2733 adv7842_s_sdp_io(sd, &pdata->sdp_io_sync_525); 2734 else 2735 adv7842_s_sdp_io(sd, NULL); 2736 2737 if (norm & V4L2_STD_ALL) { 2738 state->norm = norm; 2739 return 0; 2740 } 2741 return -EINVAL; 2742 } 2743 2744 static int adv7842_g_std(struct v4l2_subdev *sd, v4l2_std_id *norm) 2745 { 2746 struct adv7842_state *state = to_state(sd); 2747 2748 v4l2_dbg(1, debug, sd, "%s:\n", __func__); 2749 2750 if (state->mode != ADV7842_MODE_SDP) 2751 return -ENODATA; 2752 2753 *norm = state->norm; 2754 return 0; 2755 } 2756 2757 /* ----------------------------------------------------------------------- */ 2758 2759 static int adv7842_core_init(struct v4l2_subdev *sd) 2760 { 2761 struct adv7842_state *state = to_state(sd); 2762 struct adv7842_platform_data *pdata = &state->pdata; 2763 hdmi_write(sd, 0x48, 2764 (pdata->disable_pwrdnb ? 0x80 : 0) | 2765 (pdata->disable_cable_det_rst ? 0x40 : 0)); 2766 2767 disable_input(sd); 2768 2769 /* 2770 * Disable I2C access to internal EDID ram from HDMI DDC ports 2771 * Disable auto edid enable when leaving powerdown mode 2772 */ 2773 rep_write_and_or(sd, 0x77, 0xd3, 0x20); 2774 2775 /* power */ 2776 io_write(sd, 0x0c, 0x42); /* Power up part and power down VDP */ 2777 io_write(sd, 0x15, 0x80); /* Power up pads */ 2778 2779 /* video format */ 2780 io_write(sd, 0x02, 2781 0xf0 | 2782 pdata->alt_gamma << 3 | 2783 pdata->op_656_range << 2 | 2784 pdata->alt_data_sat << 0); 2785 io_write_and_or(sd, 0x05, 0xf0, pdata->blank_data << 3 | 2786 pdata->insert_av_codes << 2 | 2787 pdata->replicate_av_codes << 1); 2788 adv7842_setup_format(state); 2789 2790 /* HDMI audio */ 2791 hdmi_write_and_or(sd, 0x1a, 0xf1, 0x08); /* Wait 1 s before unmute */ 2792 2793 /* Drive strength */ 2794 io_write_and_or(sd, 0x14, 0xc0, 2795 pdata->dr_str_data << 4 | 2796 pdata->dr_str_clk << 2 | 2797 pdata->dr_str_sync); 2798 2799 /* HDMI free run */ 2800 cp_write_and_or(sd, 0xba, 0xfc, pdata->hdmi_free_run_enable | 2801 (pdata->hdmi_free_run_mode << 1)); 2802 2803 /* SPD free run */ 2804 sdp_write_and_or(sd, 0xdd, 0xf0, pdata->sdp_free_run_force | 2805 (pdata->sdp_free_run_cbar_en << 1) | 2806 (pdata->sdp_free_run_man_col_en << 2) | 2807 (pdata->sdp_free_run_auto << 3)); 2808 2809 /* TODO from platform data */ 2810 cp_write(sd, 0x69, 0x14); /* Enable CP CSC */ 2811 io_write(sd, 0x06, 0xa6); /* positive VS and HS and DE */ 2812 cp_write(sd, 0xf3, 0xdc); /* Low threshold to enter/exit free run mode */ 2813 afe_write(sd, 0xb5, 0x01); /* Setting MCLK to 256Fs */ 2814 2815 afe_write(sd, 0x02, pdata->ain_sel); /* Select analog input muxing mode */ 2816 io_write_and_or(sd, 0x30, ~(1 << 4), pdata->output_bus_lsb_to_msb << 4); 2817 2818 sdp_csc_coeff(sd, &pdata->sdp_csc_coeff); 2819 2820 /* todo, improve settings for sdram */ 2821 if (pdata->sd_ram_size >= 128) { 2822 sdp_write(sd, 0x12, 0x0d); /* Frame TBC,3D comb enabled */ 2823 if (pdata->sd_ram_ddr) { 2824 /* SDP setup for the AD eval board */ 2825 sdp_io_write(sd, 0x6f, 0x00); /* DDR mode */ 2826 sdp_io_write(sd, 0x75, 0x0a); /* 128 MB memory size */ 2827 sdp_io_write(sd, 0x7a, 0xa5); /* Timing Adjustment */ 2828 sdp_io_write(sd, 0x7b, 0x8f); /* Timing Adjustment */ 2829 sdp_io_write(sd, 0x60, 0x01); /* SDRAM reset */ 2830 } else { 2831 sdp_io_write(sd, 0x75, 0x0a); /* 64 MB memory size ?*/ 2832 sdp_io_write(sd, 0x74, 0x00); /* must be zero for sdr sdram */ 2833 sdp_io_write(sd, 0x79, 0x33); /* CAS latency to 3, 2834 depends on memory */ 2835 sdp_io_write(sd, 0x6f, 0x01); /* SDR mode */ 2836 sdp_io_write(sd, 0x7a, 0xa5); /* Timing Adjustment */ 2837 sdp_io_write(sd, 0x7b, 0x8f); /* Timing Adjustment */ 2838 sdp_io_write(sd, 0x60, 0x01); /* SDRAM reset */ 2839 } 2840 } else { 2841 /* 2842 * Manual UG-214, rev 0 is bit confusing on this bit 2843 * but a '1' disables any signal if the Ram is active. 2844 */ 2845 sdp_io_write(sd, 0x29, 0x10); /* Tristate memory interface */ 2846 } 2847 2848 select_input(sd, pdata->vid_std_select); 2849 2850 enable_input(sd); 2851 2852 if (pdata->hpa_auto) { 2853 /* HPA auto, HPA 0.5s after Edid set and Cable detect */ 2854 hdmi_write(sd, 0x69, 0x5c); 2855 } else { 2856 /* HPA manual */ 2857 hdmi_write(sd, 0x69, 0xa3); 2858 /* HPA disable on port A and B */ 2859 io_write_and_or(sd, 0x20, 0xcf, 0x00); 2860 } 2861 2862 /* LLC */ 2863 io_write(sd, 0x19, 0x80 | pdata->llc_dll_phase); 2864 io_write(sd, 0x33, 0x40); 2865 2866 /* interrupts */ 2867 io_write(sd, 0x40, 0xf2); /* Configure INT1 */ 2868 2869 adv7842_irq_enable(sd, true); 2870 2871 return v4l2_ctrl_handler_setup(sd->ctrl_handler); 2872 } 2873 2874 /* ----------------------------------------------------------------------- */ 2875 2876 static int adv7842_ddr_ram_test(struct v4l2_subdev *sd) 2877 { 2878 /* 2879 * From ADV784x external Memory test.pdf 2880 * 2881 * Reset must just been performed before running test. 2882 * Recommended to reset after test. 2883 */ 2884 int i; 2885 int pass = 0; 2886 int fail = 0; 2887 int complete = 0; 2888 2889 io_write(sd, 0x00, 0x01); /* Program SDP 4x1 */ 2890 io_write(sd, 0x01, 0x00); /* Program SDP mode */ 2891 afe_write(sd, 0x80, 0x92); /* SDP Recommeneded Write */ 2892 afe_write(sd, 0x9B, 0x01); /* SDP Recommeneded Write ADV7844ES1 */ 2893 afe_write(sd, 0x9C, 0x60); /* SDP Recommeneded Write ADV7844ES1 */ 2894 afe_write(sd, 0x9E, 0x02); /* SDP Recommeneded Write ADV7844ES1 */ 2895 afe_write(sd, 0xA0, 0x0B); /* SDP Recommeneded Write ADV7844ES1 */ 2896 afe_write(sd, 0xC3, 0x02); /* Memory BIST Initialisation */ 2897 io_write(sd, 0x0C, 0x40); /* Power up ADV7844 */ 2898 io_write(sd, 0x15, 0xBA); /* Enable outputs */ 2899 sdp_write(sd, 0x12, 0x00); /* Disable 3D comb, Frame TBC & 3DNR */ 2900 io_write(sd, 0xFF, 0x04); /* Reset memory controller */ 2901 2902 mdelay(5); 2903 2904 sdp_write(sd, 0x12, 0x00); /* Disable 3D Comb, Frame TBC & 3DNR */ 2905 sdp_io_write(sd, 0x2A, 0x01); /* Memory BIST Initialisation */ 2906 sdp_io_write(sd, 0x7c, 0x19); /* Memory BIST Initialisation */ 2907 sdp_io_write(sd, 0x80, 0x87); /* Memory BIST Initialisation */ 2908 sdp_io_write(sd, 0x81, 0x4a); /* Memory BIST Initialisation */ 2909 sdp_io_write(sd, 0x82, 0x2c); /* Memory BIST Initialisation */ 2910 sdp_io_write(sd, 0x83, 0x0e); /* Memory BIST Initialisation */ 2911 sdp_io_write(sd, 0x84, 0x94); /* Memory BIST Initialisation */ 2912 sdp_io_write(sd, 0x85, 0x62); /* Memory BIST Initialisation */ 2913 sdp_io_write(sd, 0x7d, 0x00); /* Memory BIST Initialisation */ 2914 sdp_io_write(sd, 0x7e, 0x1a); /* Memory BIST Initialisation */ 2915 2916 mdelay(5); 2917 2918 sdp_io_write(sd, 0xd9, 0xd5); /* Enable BIST Test */ 2919 sdp_write(sd, 0x12, 0x05); /* Enable FRAME TBC & 3D COMB */ 2920 2921 mdelay(20); 2922 2923 for (i = 0; i < 10; i++) { 2924 u8 result = sdp_io_read(sd, 0xdb); 2925 if (result & 0x10) { 2926 complete++; 2927 if (result & 0x20) 2928 fail++; 2929 else 2930 pass++; 2931 } 2932 mdelay(20); 2933 } 2934 2935 v4l2_dbg(1, debug, sd, 2936 "Ram Test: completed %d of %d: pass %d, fail %d\n", 2937 complete, i, pass, fail); 2938 2939 if (!complete || fail) 2940 return -EIO; 2941 return 0; 2942 } 2943 2944 static void adv7842_rewrite_i2c_addresses(struct v4l2_subdev *sd, 2945 struct adv7842_platform_data *pdata) 2946 { 2947 io_write(sd, 0xf1, pdata->i2c_sdp << 1); 2948 io_write(sd, 0xf2, pdata->i2c_sdp_io << 1); 2949 io_write(sd, 0xf3, pdata->i2c_avlink << 1); 2950 io_write(sd, 0xf4, pdata->i2c_cec << 1); 2951 io_write(sd, 0xf5, pdata->i2c_infoframe << 1); 2952 2953 io_write(sd, 0xf8, pdata->i2c_afe << 1); 2954 io_write(sd, 0xf9, pdata->i2c_repeater << 1); 2955 io_write(sd, 0xfa, pdata->i2c_edid << 1); 2956 io_write(sd, 0xfb, pdata->i2c_hdmi << 1); 2957 2958 io_write(sd, 0xfd, pdata->i2c_cp << 1); 2959 io_write(sd, 0xfe, pdata->i2c_vdp << 1); 2960 } 2961 2962 static int adv7842_command_ram_test(struct v4l2_subdev *sd) 2963 { 2964 struct i2c_client *client = v4l2_get_subdevdata(sd); 2965 struct adv7842_state *state = to_state(sd); 2966 struct adv7842_platform_data *pdata = client->dev.platform_data; 2967 struct v4l2_dv_timings timings; 2968 int ret = 0; 2969 2970 if (!pdata) 2971 return -ENODEV; 2972 2973 if (!pdata->sd_ram_size || !pdata->sd_ram_ddr) { 2974 v4l2_info(sd, "no sdram or no ddr sdram\n"); 2975 return -EINVAL; 2976 } 2977 2978 main_reset(sd); 2979 2980 adv7842_rewrite_i2c_addresses(sd, pdata); 2981 2982 /* run ram test */ 2983 ret = adv7842_ddr_ram_test(sd); 2984 2985 main_reset(sd); 2986 2987 adv7842_rewrite_i2c_addresses(sd, pdata); 2988 2989 /* and re-init chip and state */ 2990 adv7842_core_init(sd); 2991 2992 disable_input(sd); 2993 2994 select_input(sd, state->vid_std_select); 2995 2996 enable_input(sd); 2997 2998 edid_write_vga_segment(sd); 2999 edid_write_hdmi_segment(sd, ADV7842_EDID_PORT_A); 3000 edid_write_hdmi_segment(sd, ADV7842_EDID_PORT_B); 3001 3002 timings = state->timings; 3003 3004 memset(&state->timings, 0, sizeof(struct v4l2_dv_timings)); 3005 3006 adv7842_s_dv_timings(sd, &timings); 3007 3008 return ret; 3009 } 3010 3011 static long adv7842_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg) 3012 { 3013 switch (cmd) { 3014 case ADV7842_CMD_RAM_TEST: 3015 return adv7842_command_ram_test(sd); 3016 } 3017 return -ENOTTY; 3018 } 3019 3020 static int adv7842_subscribe_event(struct v4l2_subdev *sd, 3021 struct v4l2_fh *fh, 3022 struct v4l2_event_subscription *sub) 3023 { 3024 switch (sub->type) { 3025 case V4L2_EVENT_SOURCE_CHANGE: 3026 return v4l2_src_change_event_subdev_subscribe(sd, fh, sub); 3027 case V4L2_EVENT_CTRL: 3028 return v4l2_ctrl_subdev_subscribe_event(sd, fh, sub); 3029 default: 3030 return -EINVAL; 3031 } 3032 } 3033 3034 /* ----------------------------------------------------------------------- */ 3035 3036 static const struct v4l2_ctrl_ops adv7842_ctrl_ops = { 3037 .s_ctrl = adv7842_s_ctrl, 3038 .g_volatile_ctrl = adv7842_g_volatile_ctrl, 3039 }; 3040 3041 static const struct v4l2_subdev_core_ops adv7842_core_ops = { 3042 .log_status = adv7842_log_status, 3043 .ioctl = adv7842_ioctl, 3044 .interrupt_service_routine = adv7842_isr, 3045 .subscribe_event = adv7842_subscribe_event, 3046 .unsubscribe_event = v4l2_event_subdev_unsubscribe, 3047 #ifdef CONFIG_VIDEO_ADV_DEBUG 3048 .g_register = adv7842_g_register, 3049 .s_register = adv7842_s_register, 3050 #endif 3051 }; 3052 3053 static const struct v4l2_subdev_video_ops adv7842_video_ops = { 3054 .g_std = adv7842_g_std, 3055 .s_std = adv7842_s_std, 3056 .s_routing = adv7842_s_routing, 3057 .querystd = adv7842_querystd, 3058 .g_input_status = adv7842_g_input_status, 3059 .s_dv_timings = adv7842_s_dv_timings, 3060 .g_dv_timings = adv7842_g_dv_timings, 3061 .query_dv_timings = adv7842_query_dv_timings, 3062 }; 3063 3064 static const struct v4l2_subdev_pad_ops adv7842_pad_ops = { 3065 .enum_mbus_code = adv7842_enum_mbus_code, 3066 .get_fmt = adv7842_get_format, 3067 .set_fmt = adv7842_set_format, 3068 .get_edid = adv7842_get_edid, 3069 .set_edid = adv7842_set_edid, 3070 .enum_dv_timings = adv7842_enum_dv_timings, 3071 .dv_timings_cap = adv7842_dv_timings_cap, 3072 }; 3073 3074 static const struct v4l2_subdev_ops adv7842_ops = { 3075 .core = &adv7842_core_ops, 3076 .video = &adv7842_video_ops, 3077 .pad = &adv7842_pad_ops, 3078 }; 3079 3080 /* -------------------------- custom ctrls ---------------------------------- */ 3081 3082 static const struct v4l2_ctrl_config adv7842_ctrl_analog_sampling_phase = { 3083 .ops = &adv7842_ctrl_ops, 3084 .id = V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE, 3085 .name = "Analog Sampling Phase", 3086 .type = V4L2_CTRL_TYPE_INTEGER, 3087 .min = 0, 3088 .max = 0x1f, 3089 .step = 1, 3090 .def = 0, 3091 }; 3092 3093 static const struct v4l2_ctrl_config adv7842_ctrl_free_run_color_manual = { 3094 .ops = &adv7842_ctrl_ops, 3095 .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL, 3096 .name = "Free Running Color, Manual", 3097 .type = V4L2_CTRL_TYPE_BOOLEAN, 3098 .max = 1, 3099 .step = 1, 3100 .def = 1, 3101 }; 3102 3103 static const struct v4l2_ctrl_config adv7842_ctrl_free_run_color = { 3104 .ops = &adv7842_ctrl_ops, 3105 .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR, 3106 .name = "Free Running Color", 3107 .type = V4L2_CTRL_TYPE_INTEGER, 3108 .max = 0xffffff, 3109 .step = 0x1, 3110 }; 3111 3112 3113 static void adv7842_unregister_clients(struct v4l2_subdev *sd) 3114 { 3115 struct adv7842_state *state = to_state(sd); 3116 if (state->i2c_avlink) 3117 i2c_unregister_device(state->i2c_avlink); 3118 if (state->i2c_cec) 3119 i2c_unregister_device(state->i2c_cec); 3120 if (state->i2c_infoframe) 3121 i2c_unregister_device(state->i2c_infoframe); 3122 if (state->i2c_sdp_io) 3123 i2c_unregister_device(state->i2c_sdp_io); 3124 if (state->i2c_sdp) 3125 i2c_unregister_device(state->i2c_sdp); 3126 if (state->i2c_afe) 3127 i2c_unregister_device(state->i2c_afe); 3128 if (state->i2c_repeater) 3129 i2c_unregister_device(state->i2c_repeater); 3130 if (state->i2c_edid) 3131 i2c_unregister_device(state->i2c_edid); 3132 if (state->i2c_hdmi) 3133 i2c_unregister_device(state->i2c_hdmi); 3134 if (state->i2c_cp) 3135 i2c_unregister_device(state->i2c_cp); 3136 if (state->i2c_vdp) 3137 i2c_unregister_device(state->i2c_vdp); 3138 3139 state->i2c_avlink = NULL; 3140 state->i2c_cec = NULL; 3141 state->i2c_infoframe = NULL; 3142 state->i2c_sdp_io = NULL; 3143 state->i2c_sdp = NULL; 3144 state->i2c_afe = NULL; 3145 state->i2c_repeater = NULL; 3146 state->i2c_edid = NULL; 3147 state->i2c_hdmi = NULL; 3148 state->i2c_cp = NULL; 3149 state->i2c_vdp = NULL; 3150 } 3151 3152 static struct i2c_client *adv7842_dummy_client(struct v4l2_subdev *sd, const char *desc, 3153 u8 addr, u8 io_reg) 3154 { 3155 struct i2c_client *client = v4l2_get_subdevdata(sd); 3156 struct i2c_client *cp; 3157 3158 io_write(sd, io_reg, addr << 1); 3159 3160 if (addr == 0) { 3161 v4l2_err(sd, "no %s i2c addr configured\n", desc); 3162 return NULL; 3163 } 3164 3165 cp = i2c_new_dummy(client->adapter, io_read(sd, io_reg) >> 1); 3166 if (!cp) 3167 v4l2_err(sd, "register %s on i2c addr 0x%x failed\n", desc, addr); 3168 3169 return cp; 3170 } 3171 3172 static int adv7842_register_clients(struct v4l2_subdev *sd) 3173 { 3174 struct adv7842_state *state = to_state(sd); 3175 struct adv7842_platform_data *pdata = &state->pdata; 3176 3177 state->i2c_avlink = adv7842_dummy_client(sd, "avlink", pdata->i2c_avlink, 0xf3); 3178 state->i2c_cec = adv7842_dummy_client(sd, "cec", pdata->i2c_cec, 0xf4); 3179 state->i2c_infoframe = adv7842_dummy_client(sd, "infoframe", pdata->i2c_infoframe, 0xf5); 3180 state->i2c_sdp_io = adv7842_dummy_client(sd, "sdp_io", pdata->i2c_sdp_io, 0xf2); 3181 state->i2c_sdp = adv7842_dummy_client(sd, "sdp", pdata->i2c_sdp, 0xf1); 3182 state->i2c_afe = adv7842_dummy_client(sd, "afe", pdata->i2c_afe, 0xf8); 3183 state->i2c_repeater = adv7842_dummy_client(sd, "repeater", pdata->i2c_repeater, 0xf9); 3184 state->i2c_edid = adv7842_dummy_client(sd, "edid", pdata->i2c_edid, 0xfa); 3185 state->i2c_hdmi = adv7842_dummy_client(sd, "hdmi", pdata->i2c_hdmi, 0xfb); 3186 state->i2c_cp = adv7842_dummy_client(sd, "cp", pdata->i2c_cp, 0xfd); 3187 state->i2c_vdp = adv7842_dummy_client(sd, "vdp", pdata->i2c_vdp, 0xfe); 3188 3189 if (!state->i2c_avlink || 3190 !state->i2c_cec || 3191 !state->i2c_infoframe || 3192 !state->i2c_sdp_io || 3193 !state->i2c_sdp || 3194 !state->i2c_afe || 3195 !state->i2c_repeater || 3196 !state->i2c_edid || 3197 !state->i2c_hdmi || 3198 !state->i2c_cp || 3199 !state->i2c_vdp) 3200 return -1; 3201 3202 return 0; 3203 } 3204 3205 static int adv7842_probe(struct i2c_client *client, 3206 const struct i2c_device_id *id) 3207 { 3208 struct adv7842_state *state; 3209 static const struct v4l2_dv_timings cea640x480 = 3210 V4L2_DV_BT_CEA_640X480P59_94; 3211 struct adv7842_platform_data *pdata = client->dev.platform_data; 3212 struct v4l2_ctrl_handler *hdl; 3213 struct v4l2_ctrl *ctrl; 3214 struct v4l2_subdev *sd; 3215 u16 rev; 3216 int err; 3217 3218 /* Check if the adapter supports the needed features */ 3219 if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA)) 3220 return -EIO; 3221 3222 v4l_dbg(1, debug, client, "detecting adv7842 client on address 0x%x\n", 3223 client->addr << 1); 3224 3225 if (!pdata) { 3226 v4l_err(client, "No platform data!\n"); 3227 return -ENODEV; 3228 } 3229 3230 state = devm_kzalloc(&client->dev, sizeof(struct adv7842_state), GFP_KERNEL); 3231 if (!state) { 3232 v4l_err(client, "Could not allocate adv7842_state memory!\n"); 3233 return -ENOMEM; 3234 } 3235 3236 /* platform data */ 3237 state->pdata = *pdata; 3238 state->timings = cea640x480; 3239 state->format = adv7842_format_info(state, MEDIA_BUS_FMT_YUYV8_2X8); 3240 3241 sd = &state->sd; 3242 v4l2_i2c_subdev_init(sd, client, &adv7842_ops); 3243 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS; 3244 state->mode = pdata->mode; 3245 3246 state->hdmi_port_a = pdata->input == ADV7842_SELECT_HDMI_PORT_A; 3247 state->restart_stdi_once = true; 3248 3249 /* i2c access to adv7842? */ 3250 rev = adv_smbus_read_byte_data_check(client, 0xea, false) << 8 | 3251 adv_smbus_read_byte_data_check(client, 0xeb, false); 3252 if (rev != 0x2012) { 3253 v4l2_info(sd, "got rev=0x%04x on first read attempt\n", rev); 3254 rev = adv_smbus_read_byte_data_check(client, 0xea, false) << 8 | 3255 adv_smbus_read_byte_data_check(client, 0xeb, false); 3256 } 3257 if (rev != 0x2012) { 3258 v4l2_info(sd, "not an adv7842 on address 0x%x (rev=0x%04x)\n", 3259 client->addr << 1, rev); 3260 return -ENODEV; 3261 } 3262 3263 if (pdata->chip_reset) 3264 main_reset(sd); 3265 3266 /* control handlers */ 3267 hdl = &state->hdl; 3268 v4l2_ctrl_handler_init(hdl, 6); 3269 3270 /* add in ascending ID order */ 3271 v4l2_ctrl_new_std(hdl, &adv7842_ctrl_ops, 3272 V4L2_CID_BRIGHTNESS, -128, 127, 1, 0); 3273 v4l2_ctrl_new_std(hdl, &adv7842_ctrl_ops, 3274 V4L2_CID_CONTRAST, 0, 255, 1, 128); 3275 v4l2_ctrl_new_std(hdl, &adv7842_ctrl_ops, 3276 V4L2_CID_SATURATION, 0, 255, 1, 128); 3277 v4l2_ctrl_new_std(hdl, &adv7842_ctrl_ops, 3278 V4L2_CID_HUE, 0, 128, 1, 0); 3279 ctrl = v4l2_ctrl_new_std_menu(hdl, &adv7842_ctrl_ops, 3280 V4L2_CID_DV_RX_IT_CONTENT_TYPE, V4L2_DV_IT_CONTENT_TYPE_NO_ITC, 3281 0, V4L2_DV_IT_CONTENT_TYPE_NO_ITC); 3282 if (ctrl) 3283 ctrl->flags |= V4L2_CTRL_FLAG_VOLATILE; 3284 3285 /* custom controls */ 3286 state->detect_tx_5v_ctrl = v4l2_ctrl_new_std(hdl, NULL, 3287 V4L2_CID_DV_RX_POWER_PRESENT, 0, 3, 0, 0); 3288 state->analog_sampling_phase_ctrl = v4l2_ctrl_new_custom(hdl, 3289 &adv7842_ctrl_analog_sampling_phase, NULL); 3290 state->free_run_color_ctrl_manual = v4l2_ctrl_new_custom(hdl, 3291 &adv7842_ctrl_free_run_color_manual, NULL); 3292 state->free_run_color_ctrl = v4l2_ctrl_new_custom(hdl, 3293 &adv7842_ctrl_free_run_color, NULL); 3294 state->rgb_quantization_range_ctrl = 3295 v4l2_ctrl_new_std_menu(hdl, &adv7842_ctrl_ops, 3296 V4L2_CID_DV_RX_RGB_RANGE, V4L2_DV_RGB_RANGE_FULL, 3297 0, V4L2_DV_RGB_RANGE_AUTO); 3298 sd->ctrl_handler = hdl; 3299 if (hdl->error) { 3300 err = hdl->error; 3301 goto err_hdl; 3302 } 3303 state->detect_tx_5v_ctrl->is_private = true; 3304 state->rgb_quantization_range_ctrl->is_private = true; 3305 state->analog_sampling_phase_ctrl->is_private = true; 3306 state->free_run_color_ctrl_manual->is_private = true; 3307 state->free_run_color_ctrl->is_private = true; 3308 3309 if (adv7842_s_detect_tx_5v_ctrl(sd)) { 3310 err = -ENODEV; 3311 goto err_hdl; 3312 } 3313 3314 if (adv7842_register_clients(sd) < 0) { 3315 err = -ENOMEM; 3316 v4l2_err(sd, "failed to create all i2c clients\n"); 3317 goto err_i2c; 3318 } 3319 3320 /* work queues */ 3321 state->work_queues = create_singlethread_workqueue(client->name); 3322 if (!state->work_queues) { 3323 v4l2_err(sd, "Could not create work queue\n"); 3324 err = -ENOMEM; 3325 goto err_i2c; 3326 } 3327 3328 INIT_DELAYED_WORK(&state->delayed_work_enable_hotplug, 3329 adv7842_delayed_work_enable_hotplug); 3330 3331 state->pad.flags = MEDIA_PAD_FL_SOURCE; 3332 err = media_entity_pads_init(&sd->entity, 1, &state->pad); 3333 if (err) 3334 goto err_work_queues; 3335 3336 err = adv7842_core_init(sd); 3337 if (err) 3338 goto err_entity; 3339 3340 v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name, 3341 client->addr << 1, client->adapter->name); 3342 return 0; 3343 3344 err_entity: 3345 media_entity_cleanup(&sd->entity); 3346 err_work_queues: 3347 cancel_delayed_work(&state->delayed_work_enable_hotplug); 3348 destroy_workqueue(state->work_queues); 3349 err_i2c: 3350 adv7842_unregister_clients(sd); 3351 err_hdl: 3352 v4l2_ctrl_handler_free(hdl); 3353 return err; 3354 } 3355 3356 /* ----------------------------------------------------------------------- */ 3357 3358 static int adv7842_remove(struct i2c_client *client) 3359 { 3360 struct v4l2_subdev *sd = i2c_get_clientdata(client); 3361 struct adv7842_state *state = to_state(sd); 3362 3363 adv7842_irq_enable(sd, false); 3364 3365 cancel_delayed_work(&state->delayed_work_enable_hotplug); 3366 destroy_workqueue(state->work_queues); 3367 v4l2_device_unregister_subdev(sd); 3368 media_entity_cleanup(&sd->entity); 3369 adv7842_unregister_clients(sd); 3370 v4l2_ctrl_handler_free(sd->ctrl_handler); 3371 return 0; 3372 } 3373 3374 /* ----------------------------------------------------------------------- */ 3375 3376 static struct i2c_device_id adv7842_id[] = { 3377 { "adv7842", 0 }, 3378 { } 3379 }; 3380 MODULE_DEVICE_TABLE(i2c, adv7842_id); 3381 3382 /* ----------------------------------------------------------------------- */ 3383 3384 static struct i2c_driver adv7842_driver = { 3385 .driver = { 3386 .name = "adv7842", 3387 }, 3388 .probe = adv7842_probe, 3389 .remove = adv7842_remove, 3390 .id_table = adv7842_id, 3391 }; 3392 3393 module_i2c_driver(adv7842_driver); 3394