1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * adv7604 - Analog Devices ADV7604 video decoder driver 4 * 5 * Copyright 2012 Cisco Systems, Inc. and/or its affiliates. All rights reserved. 6 * 7 */ 8 9 /* 10 * References (c = chapter, p = page): 11 * REF_01 - Analog devices, ADV7604, Register Settings Recommendations, 12 * Revision 2.5, June 2010 13 * REF_02 - Analog devices, Register map documentation, Documentation of 14 * the register maps, Software manual, Rev. F, June 2010 15 * REF_03 - Analog devices, ADV7604, Hardware Manual, Rev. F, August 2010 16 */ 17 18 #include <linux/delay.h> 19 #include <linux/gpio/consumer.h> 20 #include <linux/hdmi.h> 21 #include <linux/i2c.h> 22 #include <linux/kernel.h> 23 #include <linux/module.h> 24 #include <linux/of_graph.h> 25 #include <linux/slab.h> 26 #include <linux/v4l2-dv-timings.h> 27 #include <linux/videodev2.h> 28 #include <linux/workqueue.h> 29 #include <linux/regmap.h> 30 31 #include <media/i2c/adv7604.h> 32 #include <media/cec.h> 33 #include <media/v4l2-ctrls.h> 34 #include <media/v4l2-device.h> 35 #include <media/v4l2-event.h> 36 #include <media/v4l2-dv-timings.h> 37 #include <media/v4l2-fwnode.h> 38 39 static int debug; 40 module_param(debug, int, 0644); 41 MODULE_PARM_DESC(debug, "debug level (0-2)"); 42 43 MODULE_DESCRIPTION("Analog Devices ADV7604 video decoder driver"); 44 MODULE_AUTHOR("Hans Verkuil <hans.verkuil@cisco.com>"); 45 MODULE_AUTHOR("Mats Randgaard <mats.randgaard@cisco.com>"); 46 MODULE_LICENSE("GPL"); 47 48 /* ADV7604 system clock frequency */ 49 #define ADV76XX_FSC (28636360) 50 51 #define ADV76XX_RGB_OUT (1 << 1) 52 53 #define ADV76XX_OP_FORMAT_SEL_8BIT (0 << 0) 54 #define ADV7604_OP_FORMAT_SEL_10BIT (1 << 0) 55 #define ADV76XX_OP_FORMAT_SEL_12BIT (2 << 0) 56 57 #define ADV76XX_OP_MODE_SEL_SDR_422 (0 << 5) 58 #define ADV7604_OP_MODE_SEL_DDR_422 (1 << 5) 59 #define ADV76XX_OP_MODE_SEL_SDR_444 (2 << 5) 60 #define ADV7604_OP_MODE_SEL_DDR_444 (3 << 5) 61 #define ADV76XX_OP_MODE_SEL_SDR_422_2X (4 << 5) 62 #define ADV7604_OP_MODE_SEL_ADI_CM (5 << 5) 63 64 #define ADV76XX_OP_CH_SEL_GBR (0 << 5) 65 #define ADV76XX_OP_CH_SEL_GRB (1 << 5) 66 #define ADV76XX_OP_CH_SEL_BGR (2 << 5) 67 #define ADV76XX_OP_CH_SEL_RGB (3 << 5) 68 #define ADV76XX_OP_CH_SEL_BRG (4 << 5) 69 #define ADV76XX_OP_CH_SEL_RBG (5 << 5) 70 71 #define ADV76XX_OP_SWAP_CB_CR (1 << 0) 72 73 #define ADV76XX_MAX_ADDRS (3) 74 75 enum adv76xx_type { 76 ADV7604, 77 ADV7611, 78 ADV7612, 79 }; 80 81 struct adv76xx_reg_seq { 82 unsigned int reg; 83 u8 val; 84 }; 85 86 struct adv76xx_format_info { 87 u32 code; 88 u8 op_ch_sel; 89 bool rgb_out; 90 bool swap_cb_cr; 91 u8 op_format_sel; 92 }; 93 94 struct adv76xx_cfg_read_infoframe { 95 const char *desc; 96 u8 present_mask; 97 u8 head_addr; 98 u8 payload_addr; 99 }; 100 101 struct adv76xx_chip_info { 102 enum adv76xx_type type; 103 104 bool has_afe; 105 unsigned int max_port; 106 unsigned int num_dv_ports; 107 108 unsigned int edid_enable_reg; 109 unsigned int edid_status_reg; 110 unsigned int lcf_reg; 111 112 unsigned int cable_det_mask; 113 unsigned int tdms_lock_mask; 114 unsigned int fmt_change_digital_mask; 115 unsigned int cp_csc; 116 117 const struct adv76xx_format_info *formats; 118 unsigned int nformats; 119 120 void (*set_termination)(struct v4l2_subdev *sd, bool enable); 121 void (*setup_irqs)(struct v4l2_subdev *sd); 122 unsigned int (*read_hdmi_pixelclock)(struct v4l2_subdev *sd); 123 unsigned int (*read_cable_det)(struct v4l2_subdev *sd); 124 125 /* 0 = AFE, 1 = HDMI */ 126 const struct adv76xx_reg_seq *recommended_settings[2]; 127 unsigned int num_recommended_settings[2]; 128 129 unsigned long page_mask; 130 131 /* Masks for timings */ 132 unsigned int linewidth_mask; 133 unsigned int field0_height_mask; 134 unsigned int field1_height_mask; 135 unsigned int hfrontporch_mask; 136 unsigned int hsync_mask; 137 unsigned int hbackporch_mask; 138 unsigned int field0_vfrontporch_mask; 139 unsigned int field1_vfrontporch_mask; 140 unsigned int field0_vsync_mask; 141 unsigned int field1_vsync_mask; 142 unsigned int field0_vbackporch_mask; 143 unsigned int field1_vbackporch_mask; 144 }; 145 146 /* 147 ********************************************************************** 148 * 149 * Arrays with configuration parameters for the ADV7604 150 * 151 ********************************************************************** 152 */ 153 154 struct adv76xx_state { 155 const struct adv76xx_chip_info *info; 156 struct adv76xx_platform_data pdata; 157 158 struct gpio_desc *hpd_gpio[4]; 159 struct gpio_desc *reset_gpio; 160 161 struct v4l2_subdev sd; 162 struct media_pad pads[ADV76XX_PAD_MAX]; 163 unsigned int source_pad; 164 165 struct v4l2_ctrl_handler hdl; 166 167 enum adv76xx_pad selected_input; 168 169 struct v4l2_dv_timings timings; 170 const struct adv76xx_format_info *format; 171 172 struct { 173 u8 edid[256]; 174 u32 present; 175 unsigned blocks; 176 } edid; 177 u16 spa_port_a[2]; 178 struct v4l2_fract aspect_ratio; 179 u32 rgb_quantization_range; 180 struct delayed_work delayed_work_enable_hotplug; 181 bool restart_stdi_once; 182 183 /* CEC */ 184 struct cec_adapter *cec_adap; 185 u8 cec_addr[ADV76XX_MAX_ADDRS]; 186 u8 cec_valid_addrs; 187 bool cec_enabled_adap; 188 189 /* i2c clients */ 190 struct i2c_client *i2c_clients[ADV76XX_PAGE_MAX]; 191 192 /* Regmaps */ 193 struct regmap *regmap[ADV76XX_PAGE_MAX]; 194 195 /* controls */ 196 struct v4l2_ctrl *detect_tx_5v_ctrl; 197 struct v4l2_ctrl *analog_sampling_phase_ctrl; 198 struct v4l2_ctrl *free_run_color_manual_ctrl; 199 struct v4l2_ctrl *free_run_color_ctrl; 200 struct v4l2_ctrl *rgb_quantization_range_ctrl; 201 }; 202 203 static bool adv76xx_has_afe(struct adv76xx_state *state) 204 { 205 return state->info->has_afe; 206 } 207 208 /* Unsupported timings. This device cannot support 720p30. */ 209 static const struct v4l2_dv_timings adv76xx_timings_exceptions[] = { 210 V4L2_DV_BT_CEA_1280X720P30, 211 { } 212 }; 213 214 static bool adv76xx_check_dv_timings(const struct v4l2_dv_timings *t, void *hdl) 215 { 216 int i; 217 218 for (i = 0; adv76xx_timings_exceptions[i].bt.width; i++) 219 if (v4l2_match_dv_timings(t, adv76xx_timings_exceptions + i, 0, false)) 220 return false; 221 return true; 222 } 223 224 struct adv76xx_video_standards { 225 struct v4l2_dv_timings timings; 226 u8 vid_std; 227 u8 v_freq; 228 }; 229 230 /* sorted by number of lines */ 231 static const struct adv76xx_video_standards adv7604_prim_mode_comp[] = { 232 /* { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 }, TODO flickering */ 233 { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 }, 234 { V4L2_DV_BT_CEA_1280X720P50, 0x19, 0x01 }, 235 { V4L2_DV_BT_CEA_1280X720P60, 0x19, 0x00 }, 236 { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 }, 237 { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 }, 238 { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 }, 239 { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 }, 240 { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 }, 241 /* TODO add 1920x1080P60_RB (CVT timing) */ 242 { }, 243 }; 244 245 /* sorted by number of lines */ 246 static const struct adv76xx_video_standards adv7604_prim_mode_gr[] = { 247 { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 }, 248 { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 }, 249 { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 }, 250 { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 }, 251 { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 }, 252 { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 }, 253 { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 }, 254 { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 }, 255 { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 }, 256 { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 }, 257 { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 }, 258 { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 }, 259 { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 }, 260 { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 }, 261 { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 }, 262 { V4L2_DV_BT_DMT_1360X768P60, 0x12, 0x00 }, 263 { V4L2_DV_BT_DMT_1366X768P60, 0x13, 0x00 }, 264 { V4L2_DV_BT_DMT_1400X1050P60, 0x14, 0x00 }, 265 { V4L2_DV_BT_DMT_1400X1050P75, 0x15, 0x00 }, 266 { V4L2_DV_BT_DMT_1600X1200P60, 0x16, 0x00 }, /* TODO not tested */ 267 /* TODO add 1600X1200P60_RB (not a DMT timing) */ 268 { V4L2_DV_BT_DMT_1680X1050P60, 0x18, 0x00 }, 269 { V4L2_DV_BT_DMT_1920X1200P60_RB, 0x19, 0x00 }, /* TODO not tested */ 270 { }, 271 }; 272 273 /* sorted by number of lines */ 274 static const struct adv76xx_video_standards adv76xx_prim_mode_hdmi_comp[] = { 275 { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 }, 276 { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 }, 277 { V4L2_DV_BT_CEA_1280X720P50, 0x13, 0x01 }, 278 { V4L2_DV_BT_CEA_1280X720P60, 0x13, 0x00 }, 279 { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 }, 280 { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 }, 281 { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 }, 282 { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 }, 283 { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 }, 284 { }, 285 }; 286 287 /* sorted by number of lines */ 288 static const struct adv76xx_video_standards adv76xx_prim_mode_hdmi_gr[] = { 289 { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 }, 290 { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 }, 291 { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 }, 292 { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 }, 293 { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 }, 294 { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 }, 295 { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 }, 296 { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 }, 297 { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 }, 298 { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 }, 299 { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 }, 300 { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 }, 301 { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 }, 302 { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 }, 303 { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 }, 304 { }, 305 }; 306 307 static const struct v4l2_event adv76xx_ev_fmt = { 308 .type = V4L2_EVENT_SOURCE_CHANGE, 309 .u.src_change.changes = V4L2_EVENT_SRC_CH_RESOLUTION, 310 }; 311 312 /* ----------------------------------------------------------------------- */ 313 314 static inline struct adv76xx_state *to_state(struct v4l2_subdev *sd) 315 { 316 return container_of(sd, struct adv76xx_state, sd); 317 } 318 319 static inline unsigned htotal(const struct v4l2_bt_timings *t) 320 { 321 return V4L2_DV_BT_FRAME_WIDTH(t); 322 } 323 324 static inline unsigned vtotal(const struct v4l2_bt_timings *t) 325 { 326 return V4L2_DV_BT_FRAME_HEIGHT(t); 327 } 328 329 /* ----------------------------------------------------------------------- */ 330 331 static int adv76xx_read_check(struct adv76xx_state *state, 332 int client_page, u8 reg) 333 { 334 struct i2c_client *client = state->i2c_clients[client_page]; 335 int err; 336 unsigned int val; 337 338 err = regmap_read(state->regmap[client_page], reg, &val); 339 340 if (err) { 341 v4l_err(client, "error reading %02x, %02x\n", 342 client->addr, reg); 343 return err; 344 } 345 return val; 346 } 347 348 /* adv76xx_write_block(): Write raw data with a maximum of I2C_SMBUS_BLOCK_MAX 349 * size to one or more registers. 350 * 351 * A value of zero will be returned on success, a negative errno will 352 * be returned in error cases. 353 */ 354 static int adv76xx_write_block(struct adv76xx_state *state, int client_page, 355 unsigned int init_reg, const void *val, 356 size_t val_len) 357 { 358 struct regmap *regmap = state->regmap[client_page]; 359 360 if (val_len > I2C_SMBUS_BLOCK_MAX) 361 val_len = I2C_SMBUS_BLOCK_MAX; 362 363 return regmap_raw_write(regmap, init_reg, val, val_len); 364 } 365 366 /* ----------------------------------------------------------------------- */ 367 368 static inline int io_read(struct v4l2_subdev *sd, u8 reg) 369 { 370 struct adv76xx_state *state = to_state(sd); 371 372 return adv76xx_read_check(state, ADV76XX_PAGE_IO, reg); 373 } 374 375 static inline int io_write(struct v4l2_subdev *sd, u8 reg, u8 val) 376 { 377 struct adv76xx_state *state = to_state(sd); 378 379 return regmap_write(state->regmap[ADV76XX_PAGE_IO], reg, val); 380 } 381 382 static inline int io_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, 383 u8 val) 384 { 385 return io_write(sd, reg, (io_read(sd, reg) & ~mask) | val); 386 } 387 388 static inline int avlink_read(struct v4l2_subdev *sd, u8 reg) 389 { 390 struct adv76xx_state *state = to_state(sd); 391 392 return adv76xx_read_check(state, ADV7604_PAGE_AVLINK, reg); 393 } 394 395 static inline int avlink_write(struct v4l2_subdev *sd, u8 reg, u8 val) 396 { 397 struct adv76xx_state *state = to_state(sd); 398 399 return regmap_write(state->regmap[ADV7604_PAGE_AVLINK], reg, val); 400 } 401 402 static inline int cec_read(struct v4l2_subdev *sd, u8 reg) 403 { 404 struct adv76xx_state *state = to_state(sd); 405 406 return adv76xx_read_check(state, ADV76XX_PAGE_CEC, reg); 407 } 408 409 static inline int cec_write(struct v4l2_subdev *sd, u8 reg, u8 val) 410 { 411 struct adv76xx_state *state = to_state(sd); 412 413 return regmap_write(state->regmap[ADV76XX_PAGE_CEC], reg, val); 414 } 415 416 static inline int cec_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, 417 u8 val) 418 { 419 return cec_write(sd, reg, (cec_read(sd, reg) & ~mask) | val); 420 } 421 422 static inline int infoframe_read(struct v4l2_subdev *sd, u8 reg) 423 { 424 struct adv76xx_state *state = to_state(sd); 425 426 return adv76xx_read_check(state, ADV76XX_PAGE_INFOFRAME, reg); 427 } 428 429 static inline int infoframe_write(struct v4l2_subdev *sd, u8 reg, u8 val) 430 { 431 struct adv76xx_state *state = to_state(sd); 432 433 return regmap_write(state->regmap[ADV76XX_PAGE_INFOFRAME], reg, val); 434 } 435 436 static inline int afe_read(struct v4l2_subdev *sd, u8 reg) 437 { 438 struct adv76xx_state *state = to_state(sd); 439 440 return adv76xx_read_check(state, ADV76XX_PAGE_AFE, reg); 441 } 442 443 static inline int afe_write(struct v4l2_subdev *sd, u8 reg, u8 val) 444 { 445 struct adv76xx_state *state = to_state(sd); 446 447 return regmap_write(state->regmap[ADV76XX_PAGE_AFE], reg, val); 448 } 449 450 static inline int rep_read(struct v4l2_subdev *sd, u8 reg) 451 { 452 struct adv76xx_state *state = to_state(sd); 453 454 return adv76xx_read_check(state, ADV76XX_PAGE_REP, reg); 455 } 456 457 static inline int rep_write(struct v4l2_subdev *sd, u8 reg, u8 val) 458 { 459 struct adv76xx_state *state = to_state(sd); 460 461 return regmap_write(state->regmap[ADV76XX_PAGE_REP], reg, val); 462 } 463 464 static inline int rep_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) 465 { 466 return rep_write(sd, reg, (rep_read(sd, reg) & ~mask) | val); 467 } 468 469 static inline int edid_read(struct v4l2_subdev *sd, u8 reg) 470 { 471 struct adv76xx_state *state = to_state(sd); 472 473 return adv76xx_read_check(state, ADV76XX_PAGE_EDID, reg); 474 } 475 476 static inline int edid_write(struct v4l2_subdev *sd, u8 reg, u8 val) 477 { 478 struct adv76xx_state *state = to_state(sd); 479 480 return regmap_write(state->regmap[ADV76XX_PAGE_EDID], reg, val); 481 } 482 483 static inline int edid_write_block(struct v4l2_subdev *sd, 484 unsigned int total_len, const u8 *val) 485 { 486 struct adv76xx_state *state = to_state(sd); 487 int err = 0; 488 int i = 0; 489 int len = 0; 490 491 v4l2_dbg(2, debug, sd, "%s: write EDID block (%d byte)\n", 492 __func__, total_len); 493 494 while (!err && i < total_len) { 495 len = (total_len - i) > I2C_SMBUS_BLOCK_MAX ? 496 I2C_SMBUS_BLOCK_MAX : 497 (total_len - i); 498 499 err = adv76xx_write_block(state, ADV76XX_PAGE_EDID, 500 i, val + i, len); 501 i += len; 502 } 503 504 return err; 505 } 506 507 static void adv76xx_set_hpd(struct adv76xx_state *state, unsigned int hpd) 508 { 509 unsigned int i; 510 511 for (i = 0; i < state->info->num_dv_ports; ++i) 512 gpiod_set_value_cansleep(state->hpd_gpio[i], hpd & BIT(i)); 513 514 v4l2_subdev_notify(&state->sd, ADV76XX_HOTPLUG, &hpd); 515 } 516 517 static void adv76xx_delayed_work_enable_hotplug(struct work_struct *work) 518 { 519 struct delayed_work *dwork = to_delayed_work(work); 520 struct adv76xx_state *state = container_of(dwork, struct adv76xx_state, 521 delayed_work_enable_hotplug); 522 struct v4l2_subdev *sd = &state->sd; 523 524 v4l2_dbg(2, debug, sd, "%s: enable hotplug\n", __func__); 525 526 adv76xx_set_hpd(state, state->edid.present); 527 } 528 529 static inline int hdmi_read(struct v4l2_subdev *sd, u8 reg) 530 { 531 struct adv76xx_state *state = to_state(sd); 532 533 return adv76xx_read_check(state, ADV76XX_PAGE_HDMI, reg); 534 } 535 536 static u16 hdmi_read16(struct v4l2_subdev *sd, u8 reg, u16 mask) 537 { 538 return ((hdmi_read(sd, reg) << 8) | hdmi_read(sd, reg + 1)) & mask; 539 } 540 541 static inline int hdmi_write(struct v4l2_subdev *sd, u8 reg, u8 val) 542 { 543 struct adv76xx_state *state = to_state(sd); 544 545 return regmap_write(state->regmap[ADV76XX_PAGE_HDMI], reg, val); 546 } 547 548 static inline int hdmi_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) 549 { 550 return hdmi_write(sd, reg, (hdmi_read(sd, reg) & ~mask) | val); 551 } 552 553 static inline int test_write(struct v4l2_subdev *sd, u8 reg, u8 val) 554 { 555 struct adv76xx_state *state = to_state(sd); 556 557 return regmap_write(state->regmap[ADV76XX_PAGE_TEST], reg, val); 558 } 559 560 static inline int cp_read(struct v4l2_subdev *sd, u8 reg) 561 { 562 struct adv76xx_state *state = to_state(sd); 563 564 return adv76xx_read_check(state, ADV76XX_PAGE_CP, reg); 565 } 566 567 static u16 cp_read16(struct v4l2_subdev *sd, u8 reg, u16 mask) 568 { 569 return ((cp_read(sd, reg) << 8) | cp_read(sd, reg + 1)) & mask; 570 } 571 572 static inline int cp_write(struct v4l2_subdev *sd, u8 reg, u8 val) 573 { 574 struct adv76xx_state *state = to_state(sd); 575 576 return regmap_write(state->regmap[ADV76XX_PAGE_CP], reg, val); 577 } 578 579 static inline int cp_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) 580 { 581 return cp_write(sd, reg, (cp_read(sd, reg) & ~mask) | val); 582 } 583 584 static inline int vdp_read(struct v4l2_subdev *sd, u8 reg) 585 { 586 struct adv76xx_state *state = to_state(sd); 587 588 return adv76xx_read_check(state, ADV7604_PAGE_VDP, reg); 589 } 590 591 static inline int vdp_write(struct v4l2_subdev *sd, u8 reg, u8 val) 592 { 593 struct adv76xx_state *state = to_state(sd); 594 595 return regmap_write(state->regmap[ADV7604_PAGE_VDP], reg, val); 596 } 597 598 #define ADV76XX_REG(page, offset) (((page) << 8) | (offset)) 599 #define ADV76XX_REG_SEQ_TERM 0xffff 600 601 #ifdef CONFIG_VIDEO_ADV_DEBUG 602 static int adv76xx_read_reg(struct v4l2_subdev *sd, unsigned int reg) 603 { 604 struct adv76xx_state *state = to_state(sd); 605 unsigned int page = reg >> 8; 606 unsigned int val; 607 int err; 608 609 if (page >= ADV76XX_PAGE_MAX || !(BIT(page) & state->info->page_mask)) 610 return -EINVAL; 611 612 reg &= 0xff; 613 err = regmap_read(state->regmap[page], reg, &val); 614 615 return err ? err : val; 616 } 617 #endif 618 619 static int adv76xx_write_reg(struct v4l2_subdev *sd, unsigned int reg, u8 val) 620 { 621 struct adv76xx_state *state = to_state(sd); 622 unsigned int page = reg >> 8; 623 624 if (page >= ADV76XX_PAGE_MAX || !(BIT(page) & state->info->page_mask)) 625 return -EINVAL; 626 627 reg &= 0xff; 628 629 return regmap_write(state->regmap[page], reg, val); 630 } 631 632 static void adv76xx_write_reg_seq(struct v4l2_subdev *sd, 633 const struct adv76xx_reg_seq *reg_seq) 634 { 635 unsigned int i; 636 637 for (i = 0; reg_seq[i].reg != ADV76XX_REG_SEQ_TERM; i++) 638 adv76xx_write_reg(sd, reg_seq[i].reg, reg_seq[i].val); 639 } 640 641 /* ----------------------------------------------------------------------------- 642 * Format helpers 643 */ 644 645 static const struct adv76xx_format_info adv7604_formats[] = { 646 { MEDIA_BUS_FMT_RGB888_1X24, ADV76XX_OP_CH_SEL_RGB, true, false, 647 ADV76XX_OP_MODE_SEL_SDR_444 | ADV76XX_OP_FORMAT_SEL_8BIT }, 648 { MEDIA_BUS_FMT_YUYV8_2X8, ADV76XX_OP_CH_SEL_RGB, false, false, 649 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT }, 650 { MEDIA_BUS_FMT_YVYU8_2X8, ADV76XX_OP_CH_SEL_RGB, false, true, 651 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT }, 652 { MEDIA_BUS_FMT_YUYV10_2X10, ADV76XX_OP_CH_SEL_RGB, false, false, 653 ADV76XX_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_10BIT }, 654 { MEDIA_BUS_FMT_YVYU10_2X10, ADV76XX_OP_CH_SEL_RGB, false, true, 655 ADV76XX_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_10BIT }, 656 { MEDIA_BUS_FMT_YUYV12_2X12, ADV76XX_OP_CH_SEL_RGB, false, false, 657 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_12BIT }, 658 { MEDIA_BUS_FMT_YVYU12_2X12, ADV76XX_OP_CH_SEL_RGB, false, true, 659 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_12BIT }, 660 { MEDIA_BUS_FMT_UYVY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, false, 661 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT }, 662 { MEDIA_BUS_FMT_VYUY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, true, 663 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT }, 664 { MEDIA_BUS_FMT_YUYV8_1X16, ADV76XX_OP_CH_SEL_RGB, false, false, 665 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT }, 666 { MEDIA_BUS_FMT_YVYU8_1X16, ADV76XX_OP_CH_SEL_RGB, false, true, 667 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT }, 668 { MEDIA_BUS_FMT_UYVY10_1X20, ADV76XX_OP_CH_SEL_RBG, false, false, 669 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT }, 670 { MEDIA_BUS_FMT_VYUY10_1X20, ADV76XX_OP_CH_SEL_RBG, false, true, 671 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT }, 672 { MEDIA_BUS_FMT_YUYV10_1X20, ADV76XX_OP_CH_SEL_RGB, false, false, 673 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT }, 674 { MEDIA_BUS_FMT_YVYU10_1X20, ADV76XX_OP_CH_SEL_RGB, false, true, 675 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT }, 676 { MEDIA_BUS_FMT_UYVY12_1X24, ADV76XX_OP_CH_SEL_RBG, false, false, 677 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT }, 678 { MEDIA_BUS_FMT_VYUY12_1X24, ADV76XX_OP_CH_SEL_RBG, false, true, 679 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT }, 680 { MEDIA_BUS_FMT_YUYV12_1X24, ADV76XX_OP_CH_SEL_RGB, false, false, 681 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT }, 682 { MEDIA_BUS_FMT_YVYU12_1X24, ADV76XX_OP_CH_SEL_RGB, false, true, 683 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT }, 684 }; 685 686 static const struct adv76xx_format_info adv7611_formats[] = { 687 { MEDIA_BUS_FMT_RGB888_1X24, ADV76XX_OP_CH_SEL_RGB, true, false, 688 ADV76XX_OP_MODE_SEL_SDR_444 | ADV76XX_OP_FORMAT_SEL_8BIT }, 689 { MEDIA_BUS_FMT_YUYV8_2X8, ADV76XX_OP_CH_SEL_RGB, false, false, 690 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT }, 691 { MEDIA_BUS_FMT_YVYU8_2X8, ADV76XX_OP_CH_SEL_RGB, false, true, 692 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT }, 693 { MEDIA_BUS_FMT_YUYV12_2X12, ADV76XX_OP_CH_SEL_RGB, false, false, 694 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_12BIT }, 695 { MEDIA_BUS_FMT_YVYU12_2X12, ADV76XX_OP_CH_SEL_RGB, false, true, 696 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_12BIT }, 697 { MEDIA_BUS_FMT_UYVY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, false, 698 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT }, 699 { MEDIA_BUS_FMT_VYUY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, true, 700 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT }, 701 { MEDIA_BUS_FMT_YUYV8_1X16, ADV76XX_OP_CH_SEL_RGB, false, false, 702 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT }, 703 { MEDIA_BUS_FMT_YVYU8_1X16, ADV76XX_OP_CH_SEL_RGB, false, true, 704 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT }, 705 { MEDIA_BUS_FMT_UYVY12_1X24, ADV76XX_OP_CH_SEL_RBG, false, false, 706 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT }, 707 { MEDIA_BUS_FMT_VYUY12_1X24, ADV76XX_OP_CH_SEL_RBG, false, true, 708 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT }, 709 { MEDIA_BUS_FMT_YUYV12_1X24, ADV76XX_OP_CH_SEL_RGB, false, false, 710 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT }, 711 { MEDIA_BUS_FMT_YVYU12_1X24, ADV76XX_OP_CH_SEL_RGB, false, true, 712 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT }, 713 }; 714 715 static const struct adv76xx_format_info adv7612_formats[] = { 716 { MEDIA_BUS_FMT_RGB888_1X24, ADV76XX_OP_CH_SEL_RGB, true, false, 717 ADV76XX_OP_MODE_SEL_SDR_444 | ADV76XX_OP_FORMAT_SEL_8BIT }, 718 { MEDIA_BUS_FMT_YUYV8_2X8, ADV76XX_OP_CH_SEL_RGB, false, false, 719 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT }, 720 { MEDIA_BUS_FMT_YVYU8_2X8, ADV76XX_OP_CH_SEL_RGB, false, true, 721 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT }, 722 { MEDIA_BUS_FMT_UYVY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, false, 723 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT }, 724 { MEDIA_BUS_FMT_VYUY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, true, 725 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT }, 726 { MEDIA_BUS_FMT_YUYV8_1X16, ADV76XX_OP_CH_SEL_RGB, false, false, 727 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT }, 728 { MEDIA_BUS_FMT_YVYU8_1X16, ADV76XX_OP_CH_SEL_RGB, false, true, 729 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT }, 730 }; 731 732 static const struct adv76xx_format_info * 733 adv76xx_format_info(struct adv76xx_state *state, u32 code) 734 { 735 unsigned int i; 736 737 for (i = 0; i < state->info->nformats; ++i) { 738 if (state->info->formats[i].code == code) 739 return &state->info->formats[i]; 740 } 741 742 return NULL; 743 } 744 745 /* ----------------------------------------------------------------------- */ 746 747 static inline bool is_analog_input(struct v4l2_subdev *sd) 748 { 749 struct adv76xx_state *state = to_state(sd); 750 751 return state->selected_input == ADV7604_PAD_VGA_RGB || 752 state->selected_input == ADV7604_PAD_VGA_COMP; 753 } 754 755 static inline bool is_digital_input(struct v4l2_subdev *sd) 756 { 757 struct adv76xx_state *state = to_state(sd); 758 759 return state->selected_input == ADV76XX_PAD_HDMI_PORT_A || 760 state->selected_input == ADV7604_PAD_HDMI_PORT_B || 761 state->selected_input == ADV7604_PAD_HDMI_PORT_C || 762 state->selected_input == ADV7604_PAD_HDMI_PORT_D; 763 } 764 765 static const struct v4l2_dv_timings_cap adv7604_timings_cap_analog = { 766 .type = V4L2_DV_BT_656_1120, 767 /* keep this initialization for compatibility with GCC < 4.4.6 */ 768 .reserved = { 0 }, 769 V4L2_INIT_BT_TIMINGS(0, 1920, 0, 1200, 25000000, 170000000, 770 V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT | 771 V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT, 772 V4L2_DV_BT_CAP_PROGRESSIVE | V4L2_DV_BT_CAP_REDUCED_BLANKING | 773 V4L2_DV_BT_CAP_CUSTOM) 774 }; 775 776 static const struct v4l2_dv_timings_cap adv76xx_timings_cap_digital = { 777 .type = V4L2_DV_BT_656_1120, 778 /* keep this initialization for compatibility with GCC < 4.4.6 */ 779 .reserved = { 0 }, 780 V4L2_INIT_BT_TIMINGS(0, 1920, 0, 1200, 25000000, 225000000, 781 V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT | 782 V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT, 783 V4L2_DV_BT_CAP_PROGRESSIVE | V4L2_DV_BT_CAP_REDUCED_BLANKING | 784 V4L2_DV_BT_CAP_CUSTOM) 785 }; 786 787 /* 788 * Return the DV timings capabilities for the requested sink pad. As a special 789 * case, pad value -1 returns the capabilities for the currently selected input. 790 */ 791 static const struct v4l2_dv_timings_cap * 792 adv76xx_get_dv_timings_cap(struct v4l2_subdev *sd, int pad) 793 { 794 if (pad == -1) { 795 struct adv76xx_state *state = to_state(sd); 796 797 pad = state->selected_input; 798 } 799 800 switch (pad) { 801 case ADV76XX_PAD_HDMI_PORT_A: 802 case ADV7604_PAD_HDMI_PORT_B: 803 case ADV7604_PAD_HDMI_PORT_C: 804 case ADV7604_PAD_HDMI_PORT_D: 805 return &adv76xx_timings_cap_digital; 806 807 case ADV7604_PAD_VGA_RGB: 808 case ADV7604_PAD_VGA_COMP: 809 default: 810 return &adv7604_timings_cap_analog; 811 } 812 } 813 814 815 /* ----------------------------------------------------------------------- */ 816 817 #ifdef CONFIG_VIDEO_ADV_DEBUG 818 static void adv76xx_inv_register(struct v4l2_subdev *sd) 819 { 820 v4l2_info(sd, "0x000-0x0ff: IO Map\n"); 821 v4l2_info(sd, "0x100-0x1ff: AVLink Map\n"); 822 v4l2_info(sd, "0x200-0x2ff: CEC Map\n"); 823 v4l2_info(sd, "0x300-0x3ff: InfoFrame Map\n"); 824 v4l2_info(sd, "0x400-0x4ff: ESDP Map\n"); 825 v4l2_info(sd, "0x500-0x5ff: DPP Map\n"); 826 v4l2_info(sd, "0x600-0x6ff: AFE Map\n"); 827 v4l2_info(sd, "0x700-0x7ff: Repeater Map\n"); 828 v4l2_info(sd, "0x800-0x8ff: EDID Map\n"); 829 v4l2_info(sd, "0x900-0x9ff: HDMI Map\n"); 830 v4l2_info(sd, "0xa00-0xaff: Test Map\n"); 831 v4l2_info(sd, "0xb00-0xbff: CP Map\n"); 832 v4l2_info(sd, "0xc00-0xcff: VDP Map\n"); 833 } 834 835 static int adv76xx_g_register(struct v4l2_subdev *sd, 836 struct v4l2_dbg_register *reg) 837 { 838 int ret; 839 840 ret = adv76xx_read_reg(sd, reg->reg); 841 if (ret < 0) { 842 v4l2_info(sd, "Register %03llx not supported\n", reg->reg); 843 adv76xx_inv_register(sd); 844 return ret; 845 } 846 847 reg->size = 1; 848 reg->val = ret; 849 850 return 0; 851 } 852 853 static int adv76xx_s_register(struct v4l2_subdev *sd, 854 const struct v4l2_dbg_register *reg) 855 { 856 int ret; 857 858 ret = adv76xx_write_reg(sd, reg->reg, reg->val); 859 if (ret < 0) { 860 v4l2_info(sd, "Register %03llx not supported\n", reg->reg); 861 adv76xx_inv_register(sd); 862 return ret; 863 } 864 865 return 0; 866 } 867 #endif 868 869 static unsigned int adv7604_read_cable_det(struct v4l2_subdev *sd) 870 { 871 u8 value = io_read(sd, 0x6f); 872 873 return ((value & 0x10) >> 4) 874 | ((value & 0x08) >> 2) 875 | ((value & 0x04) << 0) 876 | ((value & 0x02) << 2); 877 } 878 879 static unsigned int adv7611_read_cable_det(struct v4l2_subdev *sd) 880 { 881 u8 value = io_read(sd, 0x6f); 882 883 return value & 1; 884 } 885 886 static unsigned int adv7612_read_cable_det(struct v4l2_subdev *sd) 887 { 888 /* Reads CABLE_DET_A_RAW. For input B support, need to 889 * account for bit 7 [MSB] of 0x6a (ie. CABLE_DET_B_RAW) 890 */ 891 u8 value = io_read(sd, 0x6f); 892 893 return value & 1; 894 } 895 896 static int adv76xx_s_detect_tx_5v_ctrl(struct v4l2_subdev *sd) 897 { 898 struct adv76xx_state *state = to_state(sd); 899 const struct adv76xx_chip_info *info = state->info; 900 u16 cable_det = info->read_cable_det(sd); 901 902 return v4l2_ctrl_s_ctrl(state->detect_tx_5v_ctrl, cable_det); 903 } 904 905 static int find_and_set_predefined_video_timings(struct v4l2_subdev *sd, 906 u8 prim_mode, 907 const struct adv76xx_video_standards *predef_vid_timings, 908 const struct v4l2_dv_timings *timings) 909 { 910 int i; 911 912 for (i = 0; predef_vid_timings[i].timings.bt.width; i++) { 913 if (!v4l2_match_dv_timings(timings, &predef_vid_timings[i].timings, 914 is_digital_input(sd) ? 250000 : 1000000, false)) 915 continue; 916 io_write(sd, 0x00, predef_vid_timings[i].vid_std); /* video std */ 917 io_write(sd, 0x01, (predef_vid_timings[i].v_freq << 4) + 918 prim_mode); /* v_freq and prim mode */ 919 return 0; 920 } 921 922 return -1; 923 } 924 925 static int configure_predefined_video_timings(struct v4l2_subdev *sd, 926 struct v4l2_dv_timings *timings) 927 { 928 struct adv76xx_state *state = to_state(sd); 929 int err; 930 931 v4l2_dbg(1, debug, sd, "%s", __func__); 932 933 if (adv76xx_has_afe(state)) { 934 /* reset to default values */ 935 io_write(sd, 0x16, 0x43); 936 io_write(sd, 0x17, 0x5a); 937 } 938 /* disable embedded syncs for auto graphics mode */ 939 cp_write_clr_set(sd, 0x81, 0x10, 0x00); 940 cp_write(sd, 0x8f, 0x00); 941 cp_write(sd, 0x90, 0x00); 942 cp_write(sd, 0xa2, 0x00); 943 cp_write(sd, 0xa3, 0x00); 944 cp_write(sd, 0xa4, 0x00); 945 cp_write(sd, 0xa5, 0x00); 946 cp_write(sd, 0xa6, 0x00); 947 cp_write(sd, 0xa7, 0x00); 948 cp_write(sd, 0xab, 0x00); 949 cp_write(sd, 0xac, 0x00); 950 951 if (is_analog_input(sd)) { 952 err = find_and_set_predefined_video_timings(sd, 953 0x01, adv7604_prim_mode_comp, timings); 954 if (err) 955 err = find_and_set_predefined_video_timings(sd, 956 0x02, adv7604_prim_mode_gr, timings); 957 } else if (is_digital_input(sd)) { 958 err = find_and_set_predefined_video_timings(sd, 959 0x05, adv76xx_prim_mode_hdmi_comp, timings); 960 if (err) 961 err = find_and_set_predefined_video_timings(sd, 962 0x06, adv76xx_prim_mode_hdmi_gr, timings); 963 } else { 964 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n", 965 __func__, state->selected_input); 966 err = -1; 967 } 968 969 970 return err; 971 } 972 973 static void configure_custom_video_timings(struct v4l2_subdev *sd, 974 const struct v4l2_bt_timings *bt) 975 { 976 struct adv76xx_state *state = to_state(sd); 977 u32 width = htotal(bt); 978 u32 height = vtotal(bt); 979 u16 cp_start_sav = bt->hsync + bt->hbackporch - 4; 980 u16 cp_start_eav = width - bt->hfrontporch; 981 u16 cp_start_vbi = height - bt->vfrontporch; 982 u16 cp_end_vbi = bt->vsync + bt->vbackporch; 983 u16 ch1_fr_ll = (((u32)bt->pixelclock / 100) > 0) ? 984 ((width * (ADV76XX_FSC / 100)) / ((u32)bt->pixelclock / 100)) : 0; 985 const u8 pll[2] = { 986 0xc0 | ((width >> 8) & 0x1f), 987 width & 0xff 988 }; 989 990 v4l2_dbg(2, debug, sd, "%s\n", __func__); 991 992 if (is_analog_input(sd)) { 993 /* auto graphics */ 994 io_write(sd, 0x00, 0x07); /* video std */ 995 io_write(sd, 0x01, 0x02); /* prim mode */ 996 /* enable embedded syncs for auto graphics mode */ 997 cp_write_clr_set(sd, 0x81, 0x10, 0x10); 998 999 /* Should only be set in auto-graphics mode [REF_02, p. 91-92] */ 1000 /* setup PLL_DIV_MAN_EN and PLL_DIV_RATIO */ 1001 /* IO-map reg. 0x16 and 0x17 should be written in sequence */ 1002 if (regmap_raw_write(state->regmap[ADV76XX_PAGE_IO], 1003 0x16, pll, 2)) 1004 v4l2_err(sd, "writing to reg 0x16 and 0x17 failed\n"); 1005 1006 /* active video - horizontal timing */ 1007 cp_write(sd, 0xa2, (cp_start_sav >> 4) & 0xff); 1008 cp_write(sd, 0xa3, ((cp_start_sav & 0x0f) << 4) | 1009 ((cp_start_eav >> 8) & 0x0f)); 1010 cp_write(sd, 0xa4, cp_start_eav & 0xff); 1011 1012 /* active video - vertical timing */ 1013 cp_write(sd, 0xa5, (cp_start_vbi >> 4) & 0xff); 1014 cp_write(sd, 0xa6, ((cp_start_vbi & 0xf) << 4) | 1015 ((cp_end_vbi >> 8) & 0xf)); 1016 cp_write(sd, 0xa7, cp_end_vbi & 0xff); 1017 } else if (is_digital_input(sd)) { 1018 /* set default prim_mode/vid_std for HDMI 1019 according to [REF_03, c. 4.2] */ 1020 io_write(sd, 0x00, 0x02); /* video std */ 1021 io_write(sd, 0x01, 0x06); /* prim mode */ 1022 } else { 1023 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n", 1024 __func__, state->selected_input); 1025 } 1026 1027 cp_write(sd, 0x8f, (ch1_fr_ll >> 8) & 0x7); 1028 cp_write(sd, 0x90, ch1_fr_ll & 0xff); 1029 cp_write(sd, 0xab, (height >> 4) & 0xff); 1030 cp_write(sd, 0xac, (height & 0x0f) << 4); 1031 } 1032 1033 static void adv76xx_set_offset(struct v4l2_subdev *sd, bool auto_offset, u16 offset_a, u16 offset_b, u16 offset_c) 1034 { 1035 struct adv76xx_state *state = to_state(sd); 1036 u8 offset_buf[4]; 1037 1038 if (auto_offset) { 1039 offset_a = 0x3ff; 1040 offset_b = 0x3ff; 1041 offset_c = 0x3ff; 1042 } 1043 1044 v4l2_dbg(2, debug, sd, "%s: %s offset: a = 0x%x, b = 0x%x, c = 0x%x\n", 1045 __func__, auto_offset ? "Auto" : "Manual", 1046 offset_a, offset_b, offset_c); 1047 1048 offset_buf[0] = (cp_read(sd, 0x77) & 0xc0) | ((offset_a & 0x3f0) >> 4); 1049 offset_buf[1] = ((offset_a & 0x00f) << 4) | ((offset_b & 0x3c0) >> 6); 1050 offset_buf[2] = ((offset_b & 0x03f) << 2) | ((offset_c & 0x300) >> 8); 1051 offset_buf[3] = offset_c & 0x0ff; 1052 1053 /* Registers must be written in this order with no i2c access in between */ 1054 if (regmap_raw_write(state->regmap[ADV76XX_PAGE_CP], 1055 0x77, offset_buf, 4)) 1056 v4l2_err(sd, "%s: i2c error writing to CP reg 0x77, 0x78, 0x79, 0x7a\n", __func__); 1057 } 1058 1059 static void adv76xx_set_gain(struct v4l2_subdev *sd, bool auto_gain, u16 gain_a, u16 gain_b, u16 gain_c) 1060 { 1061 struct adv76xx_state *state = to_state(sd); 1062 u8 gain_buf[4]; 1063 u8 gain_man = 1; 1064 u8 agc_mode_man = 1; 1065 1066 if (auto_gain) { 1067 gain_man = 0; 1068 agc_mode_man = 0; 1069 gain_a = 0x100; 1070 gain_b = 0x100; 1071 gain_c = 0x100; 1072 } 1073 1074 v4l2_dbg(2, debug, sd, "%s: %s gain: a = 0x%x, b = 0x%x, c = 0x%x\n", 1075 __func__, auto_gain ? "Auto" : "Manual", 1076 gain_a, gain_b, gain_c); 1077 1078 gain_buf[0] = ((gain_man << 7) | (agc_mode_man << 6) | ((gain_a & 0x3f0) >> 4)); 1079 gain_buf[1] = (((gain_a & 0x00f) << 4) | ((gain_b & 0x3c0) >> 6)); 1080 gain_buf[2] = (((gain_b & 0x03f) << 2) | ((gain_c & 0x300) >> 8)); 1081 gain_buf[3] = ((gain_c & 0x0ff)); 1082 1083 /* Registers must be written in this order with no i2c access in between */ 1084 if (regmap_raw_write(state->regmap[ADV76XX_PAGE_CP], 1085 0x73, gain_buf, 4)) 1086 v4l2_err(sd, "%s: i2c error writing to CP reg 0x73, 0x74, 0x75, 0x76\n", __func__); 1087 } 1088 1089 static void set_rgb_quantization_range(struct v4l2_subdev *sd) 1090 { 1091 struct adv76xx_state *state = to_state(sd); 1092 bool rgb_output = io_read(sd, 0x02) & 0x02; 1093 bool hdmi_signal = hdmi_read(sd, 0x05) & 0x80; 1094 u8 y = HDMI_COLORSPACE_RGB; 1095 1096 if (hdmi_signal && (io_read(sd, 0x60) & 1)) 1097 y = infoframe_read(sd, 0x01) >> 5; 1098 1099 v4l2_dbg(2, debug, sd, "%s: RGB quantization range: %d, RGB out: %d, HDMI: %d\n", 1100 __func__, state->rgb_quantization_range, 1101 rgb_output, hdmi_signal); 1102 1103 adv76xx_set_gain(sd, true, 0x0, 0x0, 0x0); 1104 adv76xx_set_offset(sd, true, 0x0, 0x0, 0x0); 1105 io_write_clr_set(sd, 0x02, 0x04, rgb_output ? 0 : 4); 1106 1107 switch (state->rgb_quantization_range) { 1108 case V4L2_DV_RGB_RANGE_AUTO: 1109 if (state->selected_input == ADV7604_PAD_VGA_RGB) { 1110 /* Receiving analog RGB signal 1111 * Set RGB full range (0-255) */ 1112 io_write_clr_set(sd, 0x02, 0xf0, 0x10); 1113 break; 1114 } 1115 1116 if (state->selected_input == ADV7604_PAD_VGA_COMP) { 1117 /* Receiving analog YPbPr signal 1118 * Set automode */ 1119 io_write_clr_set(sd, 0x02, 0xf0, 0xf0); 1120 break; 1121 } 1122 1123 if (hdmi_signal) { 1124 /* Receiving HDMI signal 1125 * Set automode */ 1126 io_write_clr_set(sd, 0x02, 0xf0, 0xf0); 1127 break; 1128 } 1129 1130 /* Receiving DVI-D signal 1131 * ADV7604 selects RGB limited range regardless of 1132 * input format (CE/IT) in automatic mode */ 1133 if (state->timings.bt.flags & V4L2_DV_FL_IS_CE_VIDEO) { 1134 /* RGB limited range (16-235) */ 1135 io_write_clr_set(sd, 0x02, 0xf0, 0x00); 1136 } else { 1137 /* RGB full range (0-255) */ 1138 io_write_clr_set(sd, 0x02, 0xf0, 0x10); 1139 1140 if (is_digital_input(sd) && rgb_output) { 1141 adv76xx_set_offset(sd, false, 0x40, 0x40, 0x40); 1142 } else { 1143 adv76xx_set_gain(sd, false, 0xe0, 0xe0, 0xe0); 1144 adv76xx_set_offset(sd, false, 0x70, 0x70, 0x70); 1145 } 1146 } 1147 break; 1148 case V4L2_DV_RGB_RANGE_LIMITED: 1149 if (state->selected_input == ADV7604_PAD_VGA_COMP) { 1150 /* YCrCb limited range (16-235) */ 1151 io_write_clr_set(sd, 0x02, 0xf0, 0x20); 1152 break; 1153 } 1154 1155 if (y != HDMI_COLORSPACE_RGB) 1156 break; 1157 1158 /* RGB limited range (16-235) */ 1159 io_write_clr_set(sd, 0x02, 0xf0, 0x00); 1160 1161 break; 1162 case V4L2_DV_RGB_RANGE_FULL: 1163 if (state->selected_input == ADV7604_PAD_VGA_COMP) { 1164 /* YCrCb full range (0-255) */ 1165 io_write_clr_set(sd, 0x02, 0xf0, 0x60); 1166 break; 1167 } 1168 1169 if (y != HDMI_COLORSPACE_RGB) 1170 break; 1171 1172 /* RGB full range (0-255) */ 1173 io_write_clr_set(sd, 0x02, 0xf0, 0x10); 1174 1175 if (is_analog_input(sd) || hdmi_signal) 1176 break; 1177 1178 /* Adjust gain/offset for DVI-D signals only */ 1179 if (rgb_output) { 1180 adv76xx_set_offset(sd, false, 0x40, 0x40, 0x40); 1181 } else { 1182 adv76xx_set_gain(sd, false, 0xe0, 0xe0, 0xe0); 1183 adv76xx_set_offset(sd, false, 0x70, 0x70, 0x70); 1184 } 1185 break; 1186 } 1187 } 1188 1189 static int adv76xx_s_ctrl(struct v4l2_ctrl *ctrl) 1190 { 1191 struct v4l2_subdev *sd = 1192 &container_of(ctrl->handler, struct adv76xx_state, hdl)->sd; 1193 1194 struct adv76xx_state *state = to_state(sd); 1195 1196 switch (ctrl->id) { 1197 case V4L2_CID_BRIGHTNESS: 1198 cp_write(sd, 0x3c, ctrl->val); 1199 return 0; 1200 case V4L2_CID_CONTRAST: 1201 cp_write(sd, 0x3a, ctrl->val); 1202 return 0; 1203 case V4L2_CID_SATURATION: 1204 cp_write(sd, 0x3b, ctrl->val); 1205 return 0; 1206 case V4L2_CID_HUE: 1207 cp_write(sd, 0x3d, ctrl->val); 1208 return 0; 1209 case V4L2_CID_DV_RX_RGB_RANGE: 1210 state->rgb_quantization_range = ctrl->val; 1211 set_rgb_quantization_range(sd); 1212 return 0; 1213 case V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE: 1214 if (!adv76xx_has_afe(state)) 1215 return -EINVAL; 1216 /* Set the analog sampling phase. This is needed to find the 1217 best sampling phase for analog video: an application or 1218 driver has to try a number of phases and analyze the picture 1219 quality before settling on the best performing phase. */ 1220 afe_write(sd, 0xc8, ctrl->val); 1221 return 0; 1222 case V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL: 1223 /* Use the default blue color for free running mode, 1224 or supply your own. */ 1225 cp_write_clr_set(sd, 0xbf, 0x04, ctrl->val << 2); 1226 return 0; 1227 case V4L2_CID_ADV_RX_FREE_RUN_COLOR: 1228 cp_write(sd, 0xc0, (ctrl->val & 0xff0000) >> 16); 1229 cp_write(sd, 0xc1, (ctrl->val & 0x00ff00) >> 8); 1230 cp_write(sd, 0xc2, (u8)(ctrl->val & 0x0000ff)); 1231 return 0; 1232 } 1233 return -EINVAL; 1234 } 1235 1236 static int adv76xx_g_volatile_ctrl(struct v4l2_ctrl *ctrl) 1237 { 1238 struct v4l2_subdev *sd = 1239 &container_of(ctrl->handler, struct adv76xx_state, hdl)->sd; 1240 1241 if (ctrl->id == V4L2_CID_DV_RX_IT_CONTENT_TYPE) { 1242 ctrl->val = V4L2_DV_IT_CONTENT_TYPE_NO_ITC; 1243 if ((io_read(sd, 0x60) & 1) && (infoframe_read(sd, 0x03) & 0x80)) 1244 ctrl->val = (infoframe_read(sd, 0x05) >> 4) & 3; 1245 return 0; 1246 } 1247 return -EINVAL; 1248 } 1249 1250 /* ----------------------------------------------------------------------- */ 1251 1252 static inline bool no_power(struct v4l2_subdev *sd) 1253 { 1254 /* Entire chip or CP powered off */ 1255 return io_read(sd, 0x0c) & 0x24; 1256 } 1257 1258 static inline bool no_signal_tmds(struct v4l2_subdev *sd) 1259 { 1260 struct adv76xx_state *state = to_state(sd); 1261 1262 return !(io_read(sd, 0x6a) & (0x10 >> state->selected_input)); 1263 } 1264 1265 static inline bool no_lock_tmds(struct v4l2_subdev *sd) 1266 { 1267 struct adv76xx_state *state = to_state(sd); 1268 const struct adv76xx_chip_info *info = state->info; 1269 1270 return (io_read(sd, 0x6a) & info->tdms_lock_mask) != info->tdms_lock_mask; 1271 } 1272 1273 static inline bool is_hdmi(struct v4l2_subdev *sd) 1274 { 1275 return hdmi_read(sd, 0x05) & 0x80; 1276 } 1277 1278 static inline bool no_lock_sspd(struct v4l2_subdev *sd) 1279 { 1280 struct adv76xx_state *state = to_state(sd); 1281 1282 /* 1283 * Chips without a AFE don't expose registers for the SSPD, so just assume 1284 * that we have a lock. 1285 */ 1286 if (adv76xx_has_afe(state)) 1287 return false; 1288 1289 /* TODO channel 2 */ 1290 return ((cp_read(sd, 0xb5) & 0xd0) != 0xd0); 1291 } 1292 1293 static inline bool no_lock_stdi(struct v4l2_subdev *sd) 1294 { 1295 /* TODO channel 2 */ 1296 return !(cp_read(sd, 0xb1) & 0x80); 1297 } 1298 1299 static inline bool no_signal(struct v4l2_subdev *sd) 1300 { 1301 bool ret; 1302 1303 ret = no_power(sd); 1304 1305 ret |= no_lock_stdi(sd); 1306 ret |= no_lock_sspd(sd); 1307 1308 if (is_digital_input(sd)) { 1309 ret |= no_lock_tmds(sd); 1310 ret |= no_signal_tmds(sd); 1311 } 1312 1313 return ret; 1314 } 1315 1316 static inline bool no_lock_cp(struct v4l2_subdev *sd) 1317 { 1318 struct adv76xx_state *state = to_state(sd); 1319 1320 if (!adv76xx_has_afe(state)) 1321 return false; 1322 1323 /* CP has detected a non standard number of lines on the incoming 1324 video compared to what it is configured to receive by s_dv_timings */ 1325 return io_read(sd, 0x12) & 0x01; 1326 } 1327 1328 static inline bool in_free_run(struct v4l2_subdev *sd) 1329 { 1330 return cp_read(sd, 0xff) & 0x10; 1331 } 1332 1333 static int adv76xx_g_input_status(struct v4l2_subdev *sd, u32 *status) 1334 { 1335 *status = 0; 1336 *status |= no_power(sd) ? V4L2_IN_ST_NO_POWER : 0; 1337 *status |= no_signal(sd) ? V4L2_IN_ST_NO_SIGNAL : 0; 1338 if (!in_free_run(sd) && no_lock_cp(sd)) 1339 *status |= is_digital_input(sd) ? 1340 V4L2_IN_ST_NO_SYNC : V4L2_IN_ST_NO_H_LOCK; 1341 1342 v4l2_dbg(1, debug, sd, "%s: status = 0x%x\n", __func__, *status); 1343 1344 return 0; 1345 } 1346 1347 /* ----------------------------------------------------------------------- */ 1348 1349 struct stdi_readback { 1350 u16 bl, lcf, lcvs; 1351 u8 hs_pol, vs_pol; 1352 bool interlaced; 1353 }; 1354 1355 static int stdi2dv_timings(struct v4l2_subdev *sd, 1356 struct stdi_readback *stdi, 1357 struct v4l2_dv_timings *timings) 1358 { 1359 struct adv76xx_state *state = to_state(sd); 1360 u32 hfreq = (ADV76XX_FSC * 8) / stdi->bl; 1361 u32 pix_clk; 1362 int i; 1363 1364 for (i = 0; v4l2_dv_timings_presets[i].bt.width; i++) { 1365 const struct v4l2_bt_timings *bt = &v4l2_dv_timings_presets[i].bt; 1366 1367 if (!v4l2_valid_dv_timings(&v4l2_dv_timings_presets[i], 1368 adv76xx_get_dv_timings_cap(sd, -1), 1369 adv76xx_check_dv_timings, NULL)) 1370 continue; 1371 if (vtotal(bt) != stdi->lcf + 1) 1372 continue; 1373 if (bt->vsync != stdi->lcvs) 1374 continue; 1375 1376 pix_clk = hfreq * htotal(bt); 1377 1378 if ((pix_clk < bt->pixelclock + 1000000) && 1379 (pix_clk > bt->pixelclock - 1000000)) { 1380 *timings = v4l2_dv_timings_presets[i]; 1381 return 0; 1382 } 1383 } 1384 1385 if (v4l2_detect_cvt(stdi->lcf + 1, hfreq, stdi->lcvs, 0, 1386 (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) | 1387 (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0), 1388 false, timings)) 1389 return 0; 1390 if (v4l2_detect_gtf(stdi->lcf + 1, hfreq, stdi->lcvs, 1391 (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) | 1392 (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0), 1393 false, state->aspect_ratio, timings)) 1394 return 0; 1395 1396 v4l2_dbg(2, debug, sd, 1397 "%s: No format candidate found for lcvs = %d, lcf=%d, bl = %d, %chsync, %cvsync\n", 1398 __func__, stdi->lcvs, stdi->lcf, stdi->bl, 1399 stdi->hs_pol, stdi->vs_pol); 1400 return -1; 1401 } 1402 1403 1404 static int read_stdi(struct v4l2_subdev *sd, struct stdi_readback *stdi) 1405 { 1406 struct adv76xx_state *state = to_state(sd); 1407 const struct adv76xx_chip_info *info = state->info; 1408 u8 polarity; 1409 1410 if (no_lock_stdi(sd) || no_lock_sspd(sd)) { 1411 v4l2_dbg(2, debug, sd, "%s: STDI and/or SSPD not locked\n", __func__); 1412 return -1; 1413 } 1414 1415 /* read STDI */ 1416 stdi->bl = cp_read16(sd, 0xb1, 0x3fff); 1417 stdi->lcf = cp_read16(sd, info->lcf_reg, 0x7ff); 1418 stdi->lcvs = cp_read(sd, 0xb3) >> 3; 1419 stdi->interlaced = io_read(sd, 0x12) & 0x10; 1420 1421 if (adv76xx_has_afe(state)) { 1422 /* read SSPD */ 1423 polarity = cp_read(sd, 0xb5); 1424 if ((polarity & 0x03) == 0x01) { 1425 stdi->hs_pol = polarity & 0x10 1426 ? (polarity & 0x08 ? '+' : '-') : 'x'; 1427 stdi->vs_pol = polarity & 0x40 1428 ? (polarity & 0x20 ? '+' : '-') : 'x'; 1429 } else { 1430 stdi->hs_pol = 'x'; 1431 stdi->vs_pol = 'x'; 1432 } 1433 } else { 1434 polarity = hdmi_read(sd, 0x05); 1435 stdi->hs_pol = polarity & 0x20 ? '+' : '-'; 1436 stdi->vs_pol = polarity & 0x10 ? '+' : '-'; 1437 } 1438 1439 if (no_lock_stdi(sd) || no_lock_sspd(sd)) { 1440 v4l2_dbg(2, debug, sd, 1441 "%s: signal lost during readout of STDI/SSPD\n", __func__); 1442 return -1; 1443 } 1444 1445 if (stdi->lcf < 239 || stdi->bl < 8 || stdi->bl == 0x3fff) { 1446 v4l2_dbg(2, debug, sd, "%s: invalid signal\n", __func__); 1447 memset(stdi, 0, sizeof(struct stdi_readback)); 1448 return -1; 1449 } 1450 1451 v4l2_dbg(2, debug, sd, 1452 "%s: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %chsync, %cvsync, %s\n", 1453 __func__, stdi->lcf, stdi->bl, stdi->lcvs, 1454 stdi->hs_pol, stdi->vs_pol, 1455 stdi->interlaced ? "interlaced" : "progressive"); 1456 1457 return 0; 1458 } 1459 1460 static int adv76xx_enum_dv_timings(struct v4l2_subdev *sd, 1461 struct v4l2_enum_dv_timings *timings) 1462 { 1463 struct adv76xx_state *state = to_state(sd); 1464 1465 if (timings->pad >= state->source_pad) 1466 return -EINVAL; 1467 1468 return v4l2_enum_dv_timings_cap(timings, 1469 adv76xx_get_dv_timings_cap(sd, timings->pad), 1470 adv76xx_check_dv_timings, NULL); 1471 } 1472 1473 static int adv76xx_dv_timings_cap(struct v4l2_subdev *sd, 1474 struct v4l2_dv_timings_cap *cap) 1475 { 1476 struct adv76xx_state *state = to_state(sd); 1477 unsigned int pad = cap->pad; 1478 1479 if (cap->pad >= state->source_pad) 1480 return -EINVAL; 1481 1482 *cap = *adv76xx_get_dv_timings_cap(sd, pad); 1483 cap->pad = pad; 1484 1485 return 0; 1486 } 1487 1488 /* Fill the optional fields .standards and .flags in struct v4l2_dv_timings 1489 if the format is listed in adv76xx_timings[] */ 1490 static void adv76xx_fill_optional_dv_timings_fields(struct v4l2_subdev *sd, 1491 struct v4l2_dv_timings *timings) 1492 { 1493 v4l2_find_dv_timings_cap(timings, adv76xx_get_dv_timings_cap(sd, -1), 1494 is_digital_input(sd) ? 250000 : 1000000, 1495 adv76xx_check_dv_timings, NULL); 1496 } 1497 1498 static unsigned int adv7604_read_hdmi_pixelclock(struct v4l2_subdev *sd) 1499 { 1500 unsigned int freq; 1501 int a, b; 1502 1503 a = hdmi_read(sd, 0x06); 1504 b = hdmi_read(sd, 0x3b); 1505 if (a < 0 || b < 0) 1506 return 0; 1507 freq = a * 1000000 + ((b & 0x30) >> 4) * 250000; 1508 1509 if (is_hdmi(sd)) { 1510 /* adjust for deep color mode */ 1511 unsigned bits_per_channel = ((hdmi_read(sd, 0x0b) & 0x60) >> 4) + 8; 1512 1513 freq = freq * 8 / bits_per_channel; 1514 } 1515 1516 return freq; 1517 } 1518 1519 static unsigned int adv7611_read_hdmi_pixelclock(struct v4l2_subdev *sd) 1520 { 1521 int a, b; 1522 1523 a = hdmi_read(sd, 0x51); 1524 b = hdmi_read(sd, 0x52); 1525 if (a < 0 || b < 0) 1526 return 0; 1527 return ((a << 1) | (b >> 7)) * 1000000 + (b & 0x7f) * 1000000 / 128; 1528 } 1529 1530 static int adv76xx_query_dv_timings(struct v4l2_subdev *sd, 1531 struct v4l2_dv_timings *timings) 1532 { 1533 struct adv76xx_state *state = to_state(sd); 1534 const struct adv76xx_chip_info *info = state->info; 1535 struct v4l2_bt_timings *bt = &timings->bt; 1536 struct stdi_readback stdi; 1537 1538 if (!timings) 1539 return -EINVAL; 1540 1541 memset(timings, 0, sizeof(struct v4l2_dv_timings)); 1542 1543 if (no_signal(sd)) { 1544 state->restart_stdi_once = true; 1545 v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__); 1546 return -ENOLINK; 1547 } 1548 1549 /* read STDI */ 1550 if (read_stdi(sd, &stdi)) { 1551 v4l2_dbg(1, debug, sd, "%s: STDI/SSPD not locked\n", __func__); 1552 return -ENOLINK; 1553 } 1554 bt->interlaced = stdi.interlaced ? 1555 V4L2_DV_INTERLACED : V4L2_DV_PROGRESSIVE; 1556 1557 if (is_digital_input(sd)) { 1558 bool hdmi_signal = hdmi_read(sd, 0x05) & 0x80; 1559 u8 vic = 0; 1560 u32 w, h; 1561 1562 w = hdmi_read16(sd, 0x07, info->linewidth_mask); 1563 h = hdmi_read16(sd, 0x09, info->field0_height_mask); 1564 1565 if (hdmi_signal && (io_read(sd, 0x60) & 1)) 1566 vic = infoframe_read(sd, 0x04); 1567 1568 if (vic && v4l2_find_dv_timings_cea861_vic(timings, vic) && 1569 bt->width == w && bt->height == h) 1570 goto found; 1571 1572 timings->type = V4L2_DV_BT_656_1120; 1573 1574 bt->width = w; 1575 bt->height = h; 1576 bt->pixelclock = info->read_hdmi_pixelclock(sd); 1577 bt->hfrontporch = hdmi_read16(sd, 0x20, info->hfrontporch_mask); 1578 bt->hsync = hdmi_read16(sd, 0x22, info->hsync_mask); 1579 bt->hbackporch = hdmi_read16(sd, 0x24, info->hbackporch_mask); 1580 bt->vfrontporch = hdmi_read16(sd, 0x2a, 1581 info->field0_vfrontporch_mask) / 2; 1582 bt->vsync = hdmi_read16(sd, 0x2e, info->field0_vsync_mask) / 2; 1583 bt->vbackporch = hdmi_read16(sd, 0x32, 1584 info->field0_vbackporch_mask) / 2; 1585 bt->polarities = ((hdmi_read(sd, 0x05) & 0x10) ? V4L2_DV_VSYNC_POS_POL : 0) | 1586 ((hdmi_read(sd, 0x05) & 0x20) ? V4L2_DV_HSYNC_POS_POL : 0); 1587 if (bt->interlaced == V4L2_DV_INTERLACED) { 1588 bt->height += hdmi_read16(sd, 0x0b, 1589 info->field1_height_mask); 1590 bt->il_vfrontporch = hdmi_read16(sd, 0x2c, 1591 info->field1_vfrontporch_mask) / 2; 1592 bt->il_vsync = hdmi_read16(sd, 0x30, 1593 info->field1_vsync_mask) / 2; 1594 bt->il_vbackporch = hdmi_read16(sd, 0x34, 1595 info->field1_vbackporch_mask) / 2; 1596 } 1597 adv76xx_fill_optional_dv_timings_fields(sd, timings); 1598 } else { 1599 /* find format 1600 * Since LCVS values are inaccurate [REF_03, p. 275-276], 1601 * stdi2dv_timings() is called with lcvs +-1 if the first attempt fails. 1602 */ 1603 if (!stdi2dv_timings(sd, &stdi, timings)) 1604 goto found; 1605 stdi.lcvs += 1; 1606 v4l2_dbg(1, debug, sd, "%s: lcvs + 1 = %d\n", __func__, stdi.lcvs); 1607 if (!stdi2dv_timings(sd, &stdi, timings)) 1608 goto found; 1609 stdi.lcvs -= 2; 1610 v4l2_dbg(1, debug, sd, "%s: lcvs - 1 = %d\n", __func__, stdi.lcvs); 1611 if (stdi2dv_timings(sd, &stdi, timings)) { 1612 /* 1613 * The STDI block may measure wrong values, especially 1614 * for lcvs and lcf. If the driver can not find any 1615 * valid timing, the STDI block is restarted to measure 1616 * the video timings again. The function will return an 1617 * error, but the restart of STDI will generate a new 1618 * STDI interrupt and the format detection process will 1619 * restart. 1620 */ 1621 if (state->restart_stdi_once) { 1622 v4l2_dbg(1, debug, sd, "%s: restart STDI\n", __func__); 1623 /* TODO restart STDI for Sync Channel 2 */ 1624 /* enter one-shot mode */ 1625 cp_write_clr_set(sd, 0x86, 0x06, 0x00); 1626 /* trigger STDI restart */ 1627 cp_write_clr_set(sd, 0x86, 0x06, 0x04); 1628 /* reset to continuous mode */ 1629 cp_write_clr_set(sd, 0x86, 0x06, 0x02); 1630 state->restart_stdi_once = false; 1631 return -ENOLINK; 1632 } 1633 v4l2_dbg(1, debug, sd, "%s: format not supported\n", __func__); 1634 return -ERANGE; 1635 } 1636 state->restart_stdi_once = true; 1637 } 1638 found: 1639 1640 if (no_signal(sd)) { 1641 v4l2_dbg(1, debug, sd, "%s: signal lost during readout\n", __func__); 1642 memset(timings, 0, sizeof(struct v4l2_dv_timings)); 1643 return -ENOLINK; 1644 } 1645 1646 if ((is_analog_input(sd) && bt->pixelclock > 170000000) || 1647 (is_digital_input(sd) && bt->pixelclock > 225000000)) { 1648 v4l2_dbg(1, debug, sd, "%s: pixelclock out of range %d\n", 1649 __func__, (u32)bt->pixelclock); 1650 return -ERANGE; 1651 } 1652 1653 if (debug > 1) 1654 v4l2_print_dv_timings(sd->name, "adv76xx_query_dv_timings: ", 1655 timings, true); 1656 1657 return 0; 1658 } 1659 1660 static int adv76xx_s_dv_timings(struct v4l2_subdev *sd, 1661 struct v4l2_dv_timings *timings) 1662 { 1663 struct adv76xx_state *state = to_state(sd); 1664 struct v4l2_bt_timings *bt; 1665 int err; 1666 1667 if (!timings) 1668 return -EINVAL; 1669 1670 if (v4l2_match_dv_timings(&state->timings, timings, 0, false)) { 1671 v4l2_dbg(1, debug, sd, "%s: no change\n", __func__); 1672 return 0; 1673 } 1674 1675 bt = &timings->bt; 1676 1677 if (!v4l2_valid_dv_timings(timings, adv76xx_get_dv_timings_cap(sd, -1), 1678 adv76xx_check_dv_timings, NULL)) 1679 return -ERANGE; 1680 1681 adv76xx_fill_optional_dv_timings_fields(sd, timings); 1682 1683 state->timings = *timings; 1684 1685 cp_write_clr_set(sd, 0x91, 0x40, bt->interlaced ? 0x40 : 0x00); 1686 1687 /* Use prim_mode and vid_std when available */ 1688 err = configure_predefined_video_timings(sd, timings); 1689 if (err) { 1690 /* custom settings when the video format 1691 does not have prim_mode/vid_std */ 1692 configure_custom_video_timings(sd, bt); 1693 } 1694 1695 set_rgb_quantization_range(sd); 1696 1697 if (debug > 1) 1698 v4l2_print_dv_timings(sd->name, "adv76xx_s_dv_timings: ", 1699 timings, true); 1700 return 0; 1701 } 1702 1703 static int adv76xx_g_dv_timings(struct v4l2_subdev *sd, 1704 struct v4l2_dv_timings *timings) 1705 { 1706 struct adv76xx_state *state = to_state(sd); 1707 1708 *timings = state->timings; 1709 return 0; 1710 } 1711 1712 static void adv7604_set_termination(struct v4l2_subdev *sd, bool enable) 1713 { 1714 hdmi_write(sd, 0x01, enable ? 0x00 : 0x78); 1715 } 1716 1717 static void adv7611_set_termination(struct v4l2_subdev *sd, bool enable) 1718 { 1719 hdmi_write(sd, 0x83, enable ? 0xfe : 0xff); 1720 } 1721 1722 static void enable_input(struct v4l2_subdev *sd) 1723 { 1724 struct adv76xx_state *state = to_state(sd); 1725 1726 if (is_analog_input(sd)) { 1727 io_write(sd, 0x15, 0xb0); /* Disable Tristate of Pins (no audio) */ 1728 } else if (is_digital_input(sd)) { 1729 hdmi_write_clr_set(sd, 0x00, 0x03, state->selected_input); 1730 state->info->set_termination(sd, true); 1731 io_write(sd, 0x15, 0xa0); /* Disable Tristate of Pins */ 1732 hdmi_write_clr_set(sd, 0x1a, 0x10, 0x00); /* Unmute audio */ 1733 } else { 1734 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n", 1735 __func__, state->selected_input); 1736 } 1737 } 1738 1739 static void disable_input(struct v4l2_subdev *sd) 1740 { 1741 struct adv76xx_state *state = to_state(sd); 1742 1743 hdmi_write_clr_set(sd, 0x1a, 0x10, 0x10); /* Mute audio */ 1744 msleep(16); /* 512 samples with >= 32 kHz sample rate [REF_03, c. 7.16.10] */ 1745 io_write(sd, 0x15, 0xbe); /* Tristate all outputs from video core */ 1746 state->info->set_termination(sd, false); 1747 } 1748 1749 static void select_input(struct v4l2_subdev *sd) 1750 { 1751 struct adv76xx_state *state = to_state(sd); 1752 const struct adv76xx_chip_info *info = state->info; 1753 1754 if (is_analog_input(sd)) { 1755 adv76xx_write_reg_seq(sd, info->recommended_settings[0]); 1756 1757 afe_write(sd, 0x00, 0x08); /* power up ADC */ 1758 afe_write(sd, 0x01, 0x06); /* power up Analog Front End */ 1759 afe_write(sd, 0xc8, 0x00); /* phase control */ 1760 } else if (is_digital_input(sd)) { 1761 hdmi_write(sd, 0x00, state->selected_input & 0x03); 1762 1763 adv76xx_write_reg_seq(sd, info->recommended_settings[1]); 1764 1765 if (adv76xx_has_afe(state)) { 1766 afe_write(sd, 0x00, 0xff); /* power down ADC */ 1767 afe_write(sd, 0x01, 0xfe); /* power down Analog Front End */ 1768 afe_write(sd, 0xc8, 0x40); /* phase control */ 1769 } 1770 1771 cp_write(sd, 0x3e, 0x00); /* CP core pre-gain control */ 1772 cp_write(sd, 0xc3, 0x39); /* CP coast control. Graphics mode */ 1773 cp_write(sd, 0x40, 0x80); /* CP core pre-gain control. Graphics mode */ 1774 } else { 1775 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n", 1776 __func__, state->selected_input); 1777 } 1778 } 1779 1780 static int adv76xx_s_routing(struct v4l2_subdev *sd, 1781 u32 input, u32 output, u32 config) 1782 { 1783 struct adv76xx_state *state = to_state(sd); 1784 1785 v4l2_dbg(2, debug, sd, "%s: input %d, selected input %d", 1786 __func__, input, state->selected_input); 1787 1788 if (input == state->selected_input) 1789 return 0; 1790 1791 if (input > state->info->max_port) 1792 return -EINVAL; 1793 1794 state->selected_input = input; 1795 1796 disable_input(sd); 1797 select_input(sd); 1798 enable_input(sd); 1799 1800 v4l2_subdev_notify_event(sd, &adv76xx_ev_fmt); 1801 1802 return 0; 1803 } 1804 1805 static int adv76xx_enum_mbus_code(struct v4l2_subdev *sd, 1806 struct v4l2_subdev_pad_config *cfg, 1807 struct v4l2_subdev_mbus_code_enum *code) 1808 { 1809 struct adv76xx_state *state = to_state(sd); 1810 1811 if (code->index >= state->info->nformats) 1812 return -EINVAL; 1813 1814 code->code = state->info->formats[code->index].code; 1815 1816 return 0; 1817 } 1818 1819 static void adv76xx_fill_format(struct adv76xx_state *state, 1820 struct v4l2_mbus_framefmt *format) 1821 { 1822 memset(format, 0, sizeof(*format)); 1823 1824 format->width = state->timings.bt.width; 1825 format->height = state->timings.bt.height; 1826 format->field = V4L2_FIELD_NONE; 1827 format->colorspace = V4L2_COLORSPACE_SRGB; 1828 1829 if (state->timings.bt.flags & V4L2_DV_FL_IS_CE_VIDEO) 1830 format->colorspace = (state->timings.bt.height <= 576) ? 1831 V4L2_COLORSPACE_SMPTE170M : V4L2_COLORSPACE_REC709; 1832 } 1833 1834 /* 1835 * Compute the op_ch_sel value required to obtain on the bus the component order 1836 * corresponding to the selected format taking into account bus reordering 1837 * applied by the board at the output of the device. 1838 * 1839 * The following table gives the op_ch_value from the format component order 1840 * (expressed as op_ch_sel value in column) and the bus reordering (expressed as 1841 * adv76xx_bus_order value in row). 1842 * 1843 * | GBR(0) GRB(1) BGR(2) RGB(3) BRG(4) RBG(5) 1844 * ----------+------------------------------------------------- 1845 * RGB (NOP) | GBR GRB BGR RGB BRG RBG 1846 * GRB (1-2) | BGR RGB GBR GRB RBG BRG 1847 * RBG (2-3) | GRB GBR BRG RBG BGR RGB 1848 * BGR (1-3) | RBG BRG RGB BGR GRB GBR 1849 * BRG (ROR) | BRG RBG GRB GBR RGB BGR 1850 * GBR (ROL) | RGB BGR RBG BRG GBR GRB 1851 */ 1852 static unsigned int adv76xx_op_ch_sel(struct adv76xx_state *state) 1853 { 1854 #define _SEL(a,b,c,d,e,f) { \ 1855 ADV76XX_OP_CH_SEL_##a, ADV76XX_OP_CH_SEL_##b, ADV76XX_OP_CH_SEL_##c, \ 1856 ADV76XX_OP_CH_SEL_##d, ADV76XX_OP_CH_SEL_##e, ADV76XX_OP_CH_SEL_##f } 1857 #define _BUS(x) [ADV7604_BUS_ORDER_##x] 1858 1859 static const unsigned int op_ch_sel[6][6] = { 1860 _BUS(RGB) /* NOP */ = _SEL(GBR, GRB, BGR, RGB, BRG, RBG), 1861 _BUS(GRB) /* 1-2 */ = _SEL(BGR, RGB, GBR, GRB, RBG, BRG), 1862 _BUS(RBG) /* 2-3 */ = _SEL(GRB, GBR, BRG, RBG, BGR, RGB), 1863 _BUS(BGR) /* 1-3 */ = _SEL(RBG, BRG, RGB, BGR, GRB, GBR), 1864 _BUS(BRG) /* ROR */ = _SEL(BRG, RBG, GRB, GBR, RGB, BGR), 1865 _BUS(GBR) /* ROL */ = _SEL(RGB, BGR, RBG, BRG, GBR, GRB), 1866 }; 1867 1868 return op_ch_sel[state->pdata.bus_order][state->format->op_ch_sel >> 5]; 1869 } 1870 1871 static void adv76xx_setup_format(struct adv76xx_state *state) 1872 { 1873 struct v4l2_subdev *sd = &state->sd; 1874 1875 io_write_clr_set(sd, 0x02, 0x02, 1876 state->format->rgb_out ? ADV76XX_RGB_OUT : 0); 1877 io_write(sd, 0x03, state->format->op_format_sel | 1878 state->pdata.op_format_mode_sel); 1879 io_write_clr_set(sd, 0x04, 0xe0, adv76xx_op_ch_sel(state)); 1880 io_write_clr_set(sd, 0x05, 0x01, 1881 state->format->swap_cb_cr ? ADV76XX_OP_SWAP_CB_CR : 0); 1882 set_rgb_quantization_range(sd); 1883 } 1884 1885 static int adv76xx_get_format(struct v4l2_subdev *sd, 1886 struct v4l2_subdev_pad_config *cfg, 1887 struct v4l2_subdev_format *format) 1888 { 1889 struct adv76xx_state *state = to_state(sd); 1890 1891 if (format->pad != state->source_pad) 1892 return -EINVAL; 1893 1894 adv76xx_fill_format(state, &format->format); 1895 1896 if (format->which == V4L2_SUBDEV_FORMAT_TRY) { 1897 struct v4l2_mbus_framefmt *fmt; 1898 1899 fmt = v4l2_subdev_get_try_format(sd, cfg, format->pad); 1900 format->format.code = fmt->code; 1901 } else { 1902 format->format.code = state->format->code; 1903 } 1904 1905 return 0; 1906 } 1907 1908 static int adv76xx_get_selection(struct v4l2_subdev *sd, 1909 struct v4l2_subdev_pad_config *cfg, 1910 struct v4l2_subdev_selection *sel) 1911 { 1912 struct adv76xx_state *state = to_state(sd); 1913 1914 if (sel->which != V4L2_SUBDEV_FORMAT_ACTIVE) 1915 return -EINVAL; 1916 /* Only CROP, CROP_DEFAULT and CROP_BOUNDS are supported */ 1917 if (sel->target > V4L2_SEL_TGT_CROP_BOUNDS) 1918 return -EINVAL; 1919 1920 sel->r.left = 0; 1921 sel->r.top = 0; 1922 sel->r.width = state->timings.bt.width; 1923 sel->r.height = state->timings.bt.height; 1924 1925 return 0; 1926 } 1927 1928 static int adv76xx_set_format(struct v4l2_subdev *sd, 1929 struct v4l2_subdev_pad_config *cfg, 1930 struct v4l2_subdev_format *format) 1931 { 1932 struct adv76xx_state *state = to_state(sd); 1933 const struct adv76xx_format_info *info; 1934 1935 if (format->pad != state->source_pad) 1936 return -EINVAL; 1937 1938 info = adv76xx_format_info(state, format->format.code); 1939 if (!info) 1940 info = adv76xx_format_info(state, MEDIA_BUS_FMT_YUYV8_2X8); 1941 1942 adv76xx_fill_format(state, &format->format); 1943 format->format.code = info->code; 1944 1945 if (format->which == V4L2_SUBDEV_FORMAT_TRY) { 1946 struct v4l2_mbus_framefmt *fmt; 1947 1948 fmt = v4l2_subdev_get_try_format(sd, cfg, format->pad); 1949 fmt->code = format->format.code; 1950 } else { 1951 state->format = info; 1952 adv76xx_setup_format(state); 1953 } 1954 1955 return 0; 1956 } 1957 1958 #if IS_ENABLED(CONFIG_VIDEO_ADV7604_CEC) 1959 static void adv76xx_cec_tx_raw_status(struct v4l2_subdev *sd, u8 tx_raw_status) 1960 { 1961 struct adv76xx_state *state = to_state(sd); 1962 1963 if ((cec_read(sd, 0x11) & 0x01) == 0) { 1964 v4l2_dbg(1, debug, sd, "%s: tx raw: tx disabled\n", __func__); 1965 return; 1966 } 1967 1968 if (tx_raw_status & 0x02) { 1969 v4l2_dbg(1, debug, sd, "%s: tx raw: arbitration lost\n", 1970 __func__); 1971 cec_transmit_done(state->cec_adap, CEC_TX_STATUS_ARB_LOST, 1972 1, 0, 0, 0); 1973 return; 1974 } 1975 if (tx_raw_status & 0x04) { 1976 u8 status; 1977 u8 nack_cnt; 1978 u8 low_drive_cnt; 1979 1980 v4l2_dbg(1, debug, sd, "%s: tx raw: retry failed\n", __func__); 1981 /* 1982 * We set this status bit since this hardware performs 1983 * retransmissions. 1984 */ 1985 status = CEC_TX_STATUS_MAX_RETRIES; 1986 nack_cnt = cec_read(sd, 0x14) & 0xf; 1987 if (nack_cnt) 1988 status |= CEC_TX_STATUS_NACK; 1989 low_drive_cnt = cec_read(sd, 0x14) >> 4; 1990 if (low_drive_cnt) 1991 status |= CEC_TX_STATUS_LOW_DRIVE; 1992 cec_transmit_done(state->cec_adap, status, 1993 0, nack_cnt, low_drive_cnt, 0); 1994 return; 1995 } 1996 if (tx_raw_status & 0x01) { 1997 v4l2_dbg(1, debug, sd, "%s: tx raw: ready ok\n", __func__); 1998 cec_transmit_done(state->cec_adap, CEC_TX_STATUS_OK, 0, 0, 0, 0); 1999 return; 2000 } 2001 } 2002 2003 static void adv76xx_cec_isr(struct v4l2_subdev *sd, bool *handled) 2004 { 2005 struct adv76xx_state *state = to_state(sd); 2006 u8 cec_irq; 2007 2008 /* cec controller */ 2009 cec_irq = io_read(sd, 0x4d) & 0x0f; 2010 if (!cec_irq) 2011 return; 2012 2013 v4l2_dbg(1, debug, sd, "%s: cec: irq 0x%x\n", __func__, cec_irq); 2014 adv76xx_cec_tx_raw_status(sd, cec_irq); 2015 if (cec_irq & 0x08) { 2016 struct cec_msg msg; 2017 2018 msg.len = cec_read(sd, 0x25) & 0x1f; 2019 if (msg.len > 16) 2020 msg.len = 16; 2021 2022 if (msg.len) { 2023 u8 i; 2024 2025 for (i = 0; i < msg.len; i++) 2026 msg.msg[i] = cec_read(sd, i + 0x15); 2027 cec_write(sd, 0x26, 0x01); /* re-enable rx */ 2028 cec_received_msg(state->cec_adap, &msg); 2029 } 2030 } 2031 2032 /* note: the bit order is swapped between 0x4d and 0x4e */ 2033 cec_irq = ((cec_irq & 0x08) >> 3) | ((cec_irq & 0x04) >> 1) | 2034 ((cec_irq & 0x02) << 1) | ((cec_irq & 0x01) << 3); 2035 io_write(sd, 0x4e, cec_irq); 2036 2037 if (handled) 2038 *handled = true; 2039 } 2040 2041 static int adv76xx_cec_adap_enable(struct cec_adapter *adap, bool enable) 2042 { 2043 struct adv76xx_state *state = cec_get_drvdata(adap); 2044 struct v4l2_subdev *sd = &state->sd; 2045 2046 if (!state->cec_enabled_adap && enable) { 2047 cec_write_clr_set(sd, 0x2a, 0x01, 0x01); /* power up cec */ 2048 cec_write(sd, 0x2c, 0x01); /* cec soft reset */ 2049 cec_write_clr_set(sd, 0x11, 0x01, 0); /* initially disable tx */ 2050 /* enabled irqs: */ 2051 /* tx: ready */ 2052 /* tx: arbitration lost */ 2053 /* tx: retry timeout */ 2054 /* rx: ready */ 2055 io_write_clr_set(sd, 0x50, 0x0f, 0x0f); 2056 cec_write(sd, 0x26, 0x01); /* enable rx */ 2057 } else if (state->cec_enabled_adap && !enable) { 2058 /* disable cec interrupts */ 2059 io_write_clr_set(sd, 0x50, 0x0f, 0x00); 2060 /* disable address mask 1-3 */ 2061 cec_write_clr_set(sd, 0x27, 0x70, 0x00); 2062 /* power down cec section */ 2063 cec_write_clr_set(sd, 0x2a, 0x01, 0x00); 2064 state->cec_valid_addrs = 0; 2065 } 2066 state->cec_enabled_adap = enable; 2067 adv76xx_s_detect_tx_5v_ctrl(sd); 2068 return 0; 2069 } 2070 2071 static int adv76xx_cec_adap_log_addr(struct cec_adapter *adap, u8 addr) 2072 { 2073 struct adv76xx_state *state = cec_get_drvdata(adap); 2074 struct v4l2_subdev *sd = &state->sd; 2075 unsigned int i, free_idx = ADV76XX_MAX_ADDRS; 2076 2077 if (!state->cec_enabled_adap) 2078 return addr == CEC_LOG_ADDR_INVALID ? 0 : -EIO; 2079 2080 if (addr == CEC_LOG_ADDR_INVALID) { 2081 cec_write_clr_set(sd, 0x27, 0x70, 0); 2082 state->cec_valid_addrs = 0; 2083 return 0; 2084 } 2085 2086 for (i = 0; i < ADV76XX_MAX_ADDRS; i++) { 2087 bool is_valid = state->cec_valid_addrs & (1 << i); 2088 2089 if (free_idx == ADV76XX_MAX_ADDRS && !is_valid) 2090 free_idx = i; 2091 if (is_valid && state->cec_addr[i] == addr) 2092 return 0; 2093 } 2094 if (i == ADV76XX_MAX_ADDRS) { 2095 i = free_idx; 2096 if (i == ADV76XX_MAX_ADDRS) 2097 return -ENXIO; 2098 } 2099 state->cec_addr[i] = addr; 2100 state->cec_valid_addrs |= 1 << i; 2101 2102 switch (i) { 2103 case 0: 2104 /* enable address mask 0 */ 2105 cec_write_clr_set(sd, 0x27, 0x10, 0x10); 2106 /* set address for mask 0 */ 2107 cec_write_clr_set(sd, 0x28, 0x0f, addr); 2108 break; 2109 case 1: 2110 /* enable address mask 1 */ 2111 cec_write_clr_set(sd, 0x27, 0x20, 0x20); 2112 /* set address for mask 1 */ 2113 cec_write_clr_set(sd, 0x28, 0xf0, addr << 4); 2114 break; 2115 case 2: 2116 /* enable address mask 2 */ 2117 cec_write_clr_set(sd, 0x27, 0x40, 0x40); 2118 /* set address for mask 1 */ 2119 cec_write_clr_set(sd, 0x29, 0x0f, addr); 2120 break; 2121 } 2122 return 0; 2123 } 2124 2125 static int adv76xx_cec_adap_transmit(struct cec_adapter *adap, u8 attempts, 2126 u32 signal_free_time, struct cec_msg *msg) 2127 { 2128 struct adv76xx_state *state = cec_get_drvdata(adap); 2129 struct v4l2_subdev *sd = &state->sd; 2130 u8 len = msg->len; 2131 unsigned int i; 2132 2133 /* 2134 * The number of retries is the number of attempts - 1, but retry 2135 * at least once. It's not clear if a value of 0 is allowed, so 2136 * let's do at least one retry. 2137 */ 2138 cec_write_clr_set(sd, 0x12, 0x70, max(1, attempts - 1) << 4); 2139 2140 if (len > 16) { 2141 v4l2_err(sd, "%s: len exceeded 16 (%d)\n", __func__, len); 2142 return -EINVAL; 2143 } 2144 2145 /* write data */ 2146 for (i = 0; i < len; i++) 2147 cec_write(sd, i, msg->msg[i]); 2148 2149 /* set length (data + header) */ 2150 cec_write(sd, 0x10, len); 2151 /* start transmit, enable tx */ 2152 cec_write(sd, 0x11, 0x01); 2153 return 0; 2154 } 2155 2156 static const struct cec_adap_ops adv76xx_cec_adap_ops = { 2157 .adap_enable = adv76xx_cec_adap_enable, 2158 .adap_log_addr = adv76xx_cec_adap_log_addr, 2159 .adap_transmit = adv76xx_cec_adap_transmit, 2160 }; 2161 #endif 2162 2163 static int adv76xx_isr(struct v4l2_subdev *sd, u32 status, bool *handled) 2164 { 2165 struct adv76xx_state *state = to_state(sd); 2166 const struct adv76xx_chip_info *info = state->info; 2167 const u8 irq_reg_0x43 = io_read(sd, 0x43); 2168 const u8 irq_reg_0x6b = io_read(sd, 0x6b); 2169 const u8 irq_reg_0x70 = io_read(sd, 0x70); 2170 u8 fmt_change_digital; 2171 u8 fmt_change; 2172 u8 tx_5v; 2173 2174 if (irq_reg_0x43) 2175 io_write(sd, 0x44, irq_reg_0x43); 2176 if (irq_reg_0x70) 2177 io_write(sd, 0x71, irq_reg_0x70); 2178 if (irq_reg_0x6b) 2179 io_write(sd, 0x6c, irq_reg_0x6b); 2180 2181 v4l2_dbg(2, debug, sd, "%s: ", __func__); 2182 2183 /* format change */ 2184 fmt_change = irq_reg_0x43 & 0x98; 2185 fmt_change_digital = is_digital_input(sd) 2186 ? irq_reg_0x6b & info->fmt_change_digital_mask 2187 : 0; 2188 2189 if (fmt_change || fmt_change_digital) { 2190 v4l2_dbg(1, debug, sd, 2191 "%s: fmt_change = 0x%x, fmt_change_digital = 0x%x\n", 2192 __func__, fmt_change, fmt_change_digital); 2193 2194 v4l2_subdev_notify_event(sd, &adv76xx_ev_fmt); 2195 2196 if (handled) 2197 *handled = true; 2198 } 2199 /* HDMI/DVI mode */ 2200 if (irq_reg_0x6b & 0x01) { 2201 v4l2_dbg(1, debug, sd, "%s: irq %s mode\n", __func__, 2202 (io_read(sd, 0x6a) & 0x01) ? "HDMI" : "DVI"); 2203 set_rgb_quantization_range(sd); 2204 if (handled) 2205 *handled = true; 2206 } 2207 2208 #if IS_ENABLED(CONFIG_VIDEO_ADV7604_CEC) 2209 /* cec */ 2210 adv76xx_cec_isr(sd, handled); 2211 #endif 2212 2213 /* tx 5v detect */ 2214 tx_5v = irq_reg_0x70 & info->cable_det_mask; 2215 if (tx_5v) { 2216 v4l2_dbg(1, debug, sd, "%s: tx_5v: 0x%x\n", __func__, tx_5v); 2217 adv76xx_s_detect_tx_5v_ctrl(sd); 2218 if (handled) 2219 *handled = true; 2220 } 2221 return 0; 2222 } 2223 2224 static int adv76xx_get_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid) 2225 { 2226 struct adv76xx_state *state = to_state(sd); 2227 u8 *data = NULL; 2228 2229 memset(edid->reserved, 0, sizeof(edid->reserved)); 2230 2231 switch (edid->pad) { 2232 case ADV76XX_PAD_HDMI_PORT_A: 2233 case ADV7604_PAD_HDMI_PORT_B: 2234 case ADV7604_PAD_HDMI_PORT_C: 2235 case ADV7604_PAD_HDMI_PORT_D: 2236 if (state->edid.present & (1 << edid->pad)) 2237 data = state->edid.edid; 2238 break; 2239 default: 2240 return -EINVAL; 2241 } 2242 2243 if (edid->start_block == 0 && edid->blocks == 0) { 2244 edid->blocks = data ? state->edid.blocks : 0; 2245 return 0; 2246 } 2247 2248 if (!data) 2249 return -ENODATA; 2250 2251 if (edid->start_block >= state->edid.blocks) 2252 return -EINVAL; 2253 2254 if (edid->start_block + edid->blocks > state->edid.blocks) 2255 edid->blocks = state->edid.blocks - edid->start_block; 2256 2257 memcpy(edid->edid, data + edid->start_block * 128, edid->blocks * 128); 2258 2259 return 0; 2260 } 2261 2262 static int adv76xx_set_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid) 2263 { 2264 struct adv76xx_state *state = to_state(sd); 2265 const struct adv76xx_chip_info *info = state->info; 2266 unsigned int spa_loc; 2267 u16 pa; 2268 int err; 2269 int i; 2270 2271 memset(edid->reserved, 0, sizeof(edid->reserved)); 2272 2273 if (edid->pad > ADV7604_PAD_HDMI_PORT_D) 2274 return -EINVAL; 2275 if (edid->start_block != 0) 2276 return -EINVAL; 2277 if (edid->blocks == 0) { 2278 /* Disable hotplug and I2C access to EDID RAM from DDC port */ 2279 state->edid.present &= ~(1 << edid->pad); 2280 adv76xx_set_hpd(state, state->edid.present); 2281 rep_write_clr_set(sd, info->edid_enable_reg, 0x0f, state->edid.present); 2282 2283 /* Fall back to a 16:9 aspect ratio */ 2284 state->aspect_ratio.numerator = 16; 2285 state->aspect_ratio.denominator = 9; 2286 2287 if (!state->edid.present) 2288 state->edid.blocks = 0; 2289 2290 v4l2_dbg(2, debug, sd, "%s: clear EDID pad %d, edid.present = 0x%x\n", 2291 __func__, edid->pad, state->edid.present); 2292 return 0; 2293 } 2294 if (edid->blocks > 2) { 2295 edid->blocks = 2; 2296 return -E2BIG; 2297 } 2298 pa = cec_get_edid_phys_addr(edid->edid, edid->blocks * 128, &spa_loc); 2299 err = cec_phys_addr_validate(pa, &pa, NULL); 2300 if (err) 2301 return err; 2302 2303 v4l2_dbg(2, debug, sd, "%s: write EDID pad %d, edid.present = 0x%x\n", 2304 __func__, edid->pad, state->edid.present); 2305 2306 /* Disable hotplug and I2C access to EDID RAM from DDC port */ 2307 cancel_delayed_work_sync(&state->delayed_work_enable_hotplug); 2308 adv76xx_set_hpd(state, 0); 2309 rep_write_clr_set(sd, info->edid_enable_reg, 0x0f, 0x00); 2310 2311 /* 2312 * Return an error if no location of the source physical address 2313 * was found. 2314 */ 2315 if (spa_loc == 0) 2316 return -EINVAL; 2317 2318 switch (edid->pad) { 2319 case ADV76XX_PAD_HDMI_PORT_A: 2320 state->spa_port_a[0] = edid->edid[spa_loc]; 2321 state->spa_port_a[1] = edid->edid[spa_loc + 1]; 2322 break; 2323 case ADV7604_PAD_HDMI_PORT_B: 2324 rep_write(sd, 0x70, edid->edid[spa_loc]); 2325 rep_write(sd, 0x71, edid->edid[spa_loc + 1]); 2326 break; 2327 case ADV7604_PAD_HDMI_PORT_C: 2328 rep_write(sd, 0x72, edid->edid[spa_loc]); 2329 rep_write(sd, 0x73, edid->edid[spa_loc + 1]); 2330 break; 2331 case ADV7604_PAD_HDMI_PORT_D: 2332 rep_write(sd, 0x74, edid->edid[spa_loc]); 2333 rep_write(sd, 0x75, edid->edid[spa_loc + 1]); 2334 break; 2335 default: 2336 return -EINVAL; 2337 } 2338 2339 if (info->type == ADV7604) { 2340 rep_write(sd, 0x76, spa_loc & 0xff); 2341 rep_write_clr_set(sd, 0x77, 0x40, (spa_loc & 0x100) >> 2); 2342 } else { 2343 /* ADV7612 Software Manual Rev. A, p. 15 */ 2344 rep_write(sd, 0x70, spa_loc & 0xff); 2345 rep_write_clr_set(sd, 0x71, 0x01, (spa_loc & 0x100) >> 8); 2346 } 2347 2348 edid->edid[spa_loc] = state->spa_port_a[0]; 2349 edid->edid[spa_loc + 1] = state->spa_port_a[1]; 2350 2351 memcpy(state->edid.edid, edid->edid, 128 * edid->blocks); 2352 state->edid.blocks = edid->blocks; 2353 state->aspect_ratio = v4l2_calc_aspect_ratio(edid->edid[0x15], 2354 edid->edid[0x16]); 2355 state->edid.present |= 1 << edid->pad; 2356 2357 err = edid_write_block(sd, 128 * edid->blocks, state->edid.edid); 2358 if (err < 0) { 2359 v4l2_err(sd, "error %d writing edid pad %d\n", err, edid->pad); 2360 return err; 2361 } 2362 2363 /* adv76xx calculates the checksums and enables I2C access to internal 2364 EDID RAM from DDC port. */ 2365 rep_write_clr_set(sd, info->edid_enable_reg, 0x0f, state->edid.present); 2366 2367 for (i = 0; i < 1000; i++) { 2368 if (rep_read(sd, info->edid_status_reg) & state->edid.present) 2369 break; 2370 mdelay(1); 2371 } 2372 if (i == 1000) { 2373 v4l2_err(sd, "error enabling edid (0x%x)\n", state->edid.present); 2374 return -EIO; 2375 } 2376 cec_s_phys_addr(state->cec_adap, pa, false); 2377 2378 /* enable hotplug after 100 ms */ 2379 schedule_delayed_work(&state->delayed_work_enable_hotplug, HZ / 10); 2380 return 0; 2381 } 2382 2383 /*********** avi info frame CEA-861-E **************/ 2384 2385 static const struct adv76xx_cfg_read_infoframe adv76xx_cri[] = { 2386 { "AVI", 0x01, 0xe0, 0x00 }, 2387 { "Audio", 0x02, 0xe3, 0x1c }, 2388 { "SDP", 0x04, 0xe6, 0x2a }, 2389 { "Vendor", 0x10, 0xec, 0x54 } 2390 }; 2391 2392 static int adv76xx_read_infoframe(struct v4l2_subdev *sd, int index, 2393 union hdmi_infoframe *frame) 2394 { 2395 uint8_t buffer[32]; 2396 u8 len; 2397 int i; 2398 2399 if (!(io_read(sd, 0x60) & adv76xx_cri[index].present_mask)) { 2400 v4l2_info(sd, "%s infoframe not received\n", 2401 adv76xx_cri[index].desc); 2402 return -ENOENT; 2403 } 2404 2405 for (i = 0; i < 3; i++) 2406 buffer[i] = infoframe_read(sd, 2407 adv76xx_cri[index].head_addr + i); 2408 2409 len = buffer[2] + 1; 2410 2411 if (len + 3 > sizeof(buffer)) { 2412 v4l2_err(sd, "%s: invalid %s infoframe length %d\n", __func__, 2413 adv76xx_cri[index].desc, len); 2414 return -ENOENT; 2415 } 2416 2417 for (i = 0; i < len; i++) 2418 buffer[i + 3] = infoframe_read(sd, 2419 adv76xx_cri[index].payload_addr + i); 2420 2421 if (hdmi_infoframe_unpack(frame, buffer) < 0) { 2422 v4l2_err(sd, "%s: unpack of %s infoframe failed\n", __func__, 2423 adv76xx_cri[index].desc); 2424 return -ENOENT; 2425 } 2426 return 0; 2427 } 2428 2429 static void adv76xx_log_infoframes(struct v4l2_subdev *sd) 2430 { 2431 int i; 2432 2433 if (!is_hdmi(sd)) { 2434 v4l2_info(sd, "receive DVI-D signal, no infoframes\n"); 2435 return; 2436 } 2437 2438 for (i = 0; i < ARRAY_SIZE(adv76xx_cri); i++) { 2439 union hdmi_infoframe frame; 2440 struct i2c_client *client = v4l2_get_subdevdata(sd); 2441 2442 if (adv76xx_read_infoframe(sd, i, &frame)) 2443 return; 2444 hdmi_infoframe_log(KERN_INFO, &client->dev, &frame); 2445 } 2446 } 2447 2448 static int adv76xx_log_status(struct v4l2_subdev *sd) 2449 { 2450 struct adv76xx_state *state = to_state(sd); 2451 const struct adv76xx_chip_info *info = state->info; 2452 struct v4l2_dv_timings timings; 2453 struct stdi_readback stdi; 2454 u8 reg_io_0x02 = io_read(sd, 0x02); 2455 u8 edid_enabled; 2456 u8 cable_det; 2457 2458 static const char * const csc_coeff_sel_rb[16] = { 2459 "bypassed", "YPbPr601 -> RGB", "reserved", "YPbPr709 -> RGB", 2460 "reserved", "RGB -> YPbPr601", "reserved", "RGB -> YPbPr709", 2461 "reserved", "YPbPr709 -> YPbPr601", "YPbPr601 -> YPbPr709", 2462 "reserved", "reserved", "reserved", "reserved", "manual" 2463 }; 2464 static const char * const input_color_space_txt[16] = { 2465 "RGB limited range (16-235)", "RGB full range (0-255)", 2466 "YCbCr Bt.601 (16-235)", "YCbCr Bt.709 (16-235)", 2467 "xvYCC Bt.601", "xvYCC Bt.709", 2468 "YCbCr Bt.601 (0-255)", "YCbCr Bt.709 (0-255)", 2469 "invalid", "invalid", "invalid", "invalid", "invalid", 2470 "invalid", "invalid", "automatic" 2471 }; 2472 static const char * const hdmi_color_space_txt[16] = { 2473 "RGB limited range (16-235)", "RGB full range (0-255)", 2474 "YCbCr Bt.601 (16-235)", "YCbCr Bt.709 (16-235)", 2475 "xvYCC Bt.601", "xvYCC Bt.709", 2476 "YCbCr Bt.601 (0-255)", "YCbCr Bt.709 (0-255)", 2477 "sYCC", "Adobe YCC 601", "AdobeRGB", "invalid", "invalid", 2478 "invalid", "invalid", "invalid" 2479 }; 2480 static const char * const rgb_quantization_range_txt[] = { 2481 "Automatic", 2482 "RGB limited range (16-235)", 2483 "RGB full range (0-255)", 2484 }; 2485 static const char * const deep_color_mode_txt[4] = { 2486 "8-bits per channel", 2487 "10-bits per channel", 2488 "12-bits per channel", 2489 "16-bits per channel (not supported)" 2490 }; 2491 2492 v4l2_info(sd, "-----Chip status-----\n"); 2493 v4l2_info(sd, "Chip power: %s\n", no_power(sd) ? "off" : "on"); 2494 edid_enabled = rep_read(sd, info->edid_status_reg); 2495 v4l2_info(sd, "EDID enabled port A: %s, B: %s, C: %s, D: %s\n", 2496 ((edid_enabled & 0x01) ? "Yes" : "No"), 2497 ((edid_enabled & 0x02) ? "Yes" : "No"), 2498 ((edid_enabled & 0x04) ? "Yes" : "No"), 2499 ((edid_enabled & 0x08) ? "Yes" : "No")); 2500 v4l2_info(sd, "CEC: %s\n", state->cec_enabled_adap ? 2501 "enabled" : "disabled"); 2502 if (state->cec_enabled_adap) { 2503 int i; 2504 2505 for (i = 0; i < ADV76XX_MAX_ADDRS; i++) { 2506 bool is_valid = state->cec_valid_addrs & (1 << i); 2507 2508 if (is_valid) 2509 v4l2_info(sd, "CEC Logical Address: 0x%x\n", 2510 state->cec_addr[i]); 2511 } 2512 } 2513 2514 v4l2_info(sd, "-----Signal status-----\n"); 2515 cable_det = info->read_cable_det(sd); 2516 v4l2_info(sd, "Cable detected (+5V power) port A: %s, B: %s, C: %s, D: %s\n", 2517 ((cable_det & 0x01) ? "Yes" : "No"), 2518 ((cable_det & 0x02) ? "Yes" : "No"), 2519 ((cable_det & 0x04) ? "Yes" : "No"), 2520 ((cable_det & 0x08) ? "Yes" : "No")); 2521 v4l2_info(sd, "TMDS signal detected: %s\n", 2522 no_signal_tmds(sd) ? "false" : "true"); 2523 v4l2_info(sd, "TMDS signal locked: %s\n", 2524 no_lock_tmds(sd) ? "false" : "true"); 2525 v4l2_info(sd, "SSPD locked: %s\n", no_lock_sspd(sd) ? "false" : "true"); 2526 v4l2_info(sd, "STDI locked: %s\n", no_lock_stdi(sd) ? "false" : "true"); 2527 v4l2_info(sd, "CP locked: %s\n", no_lock_cp(sd) ? "false" : "true"); 2528 v4l2_info(sd, "CP free run: %s\n", 2529 (in_free_run(sd)) ? "on" : "off"); 2530 v4l2_info(sd, "Prim-mode = 0x%x, video std = 0x%x, v_freq = 0x%x\n", 2531 io_read(sd, 0x01) & 0x0f, io_read(sd, 0x00) & 0x3f, 2532 (io_read(sd, 0x01) & 0x70) >> 4); 2533 2534 v4l2_info(sd, "-----Video Timings-----\n"); 2535 if (read_stdi(sd, &stdi)) 2536 v4l2_info(sd, "STDI: not locked\n"); 2537 else 2538 v4l2_info(sd, "STDI: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %s, %chsync, %cvsync\n", 2539 stdi.lcf, stdi.bl, stdi.lcvs, 2540 stdi.interlaced ? "interlaced" : "progressive", 2541 stdi.hs_pol, stdi.vs_pol); 2542 if (adv76xx_query_dv_timings(sd, &timings)) 2543 v4l2_info(sd, "No video detected\n"); 2544 else 2545 v4l2_print_dv_timings(sd->name, "Detected format: ", 2546 &timings, true); 2547 v4l2_print_dv_timings(sd->name, "Configured format: ", 2548 &state->timings, true); 2549 2550 if (no_signal(sd)) 2551 return 0; 2552 2553 v4l2_info(sd, "-----Color space-----\n"); 2554 v4l2_info(sd, "RGB quantization range ctrl: %s\n", 2555 rgb_quantization_range_txt[state->rgb_quantization_range]); 2556 v4l2_info(sd, "Input color space: %s\n", 2557 input_color_space_txt[reg_io_0x02 >> 4]); 2558 v4l2_info(sd, "Output color space: %s %s, alt-gamma %s\n", 2559 (reg_io_0x02 & 0x02) ? "RGB" : "YCbCr", 2560 (((reg_io_0x02 >> 2) & 0x01) ^ (reg_io_0x02 & 0x01)) ? 2561 "(16-235)" : "(0-255)", 2562 (reg_io_0x02 & 0x08) ? "enabled" : "disabled"); 2563 v4l2_info(sd, "Color space conversion: %s\n", 2564 csc_coeff_sel_rb[cp_read(sd, info->cp_csc) >> 4]); 2565 2566 if (!is_digital_input(sd)) 2567 return 0; 2568 2569 v4l2_info(sd, "-----%s status-----\n", is_hdmi(sd) ? "HDMI" : "DVI-D"); 2570 v4l2_info(sd, "Digital video port selected: %c\n", 2571 (hdmi_read(sd, 0x00) & 0x03) + 'A'); 2572 v4l2_info(sd, "HDCP encrypted content: %s\n", 2573 (hdmi_read(sd, 0x05) & 0x40) ? "true" : "false"); 2574 v4l2_info(sd, "HDCP keys read: %s%s\n", 2575 (hdmi_read(sd, 0x04) & 0x20) ? "yes" : "no", 2576 (hdmi_read(sd, 0x04) & 0x10) ? "ERROR" : ""); 2577 if (is_hdmi(sd)) { 2578 bool audio_pll_locked = hdmi_read(sd, 0x04) & 0x01; 2579 bool audio_sample_packet_detect = hdmi_read(sd, 0x18) & 0x01; 2580 bool audio_mute = io_read(sd, 0x65) & 0x40; 2581 2582 v4l2_info(sd, "Audio: pll %s, samples %s, %s\n", 2583 audio_pll_locked ? "locked" : "not locked", 2584 audio_sample_packet_detect ? "detected" : "not detected", 2585 audio_mute ? "muted" : "enabled"); 2586 if (audio_pll_locked && audio_sample_packet_detect) { 2587 v4l2_info(sd, "Audio format: %s\n", 2588 (hdmi_read(sd, 0x07) & 0x20) ? "multi-channel" : "stereo"); 2589 } 2590 v4l2_info(sd, "Audio CTS: %u\n", (hdmi_read(sd, 0x5b) << 12) + 2591 (hdmi_read(sd, 0x5c) << 8) + 2592 (hdmi_read(sd, 0x5d) & 0xf0)); 2593 v4l2_info(sd, "Audio N: %u\n", ((hdmi_read(sd, 0x5d) & 0x0f) << 16) + 2594 (hdmi_read(sd, 0x5e) << 8) + 2595 hdmi_read(sd, 0x5f)); 2596 v4l2_info(sd, "AV Mute: %s\n", (hdmi_read(sd, 0x04) & 0x40) ? "on" : "off"); 2597 2598 v4l2_info(sd, "Deep color mode: %s\n", deep_color_mode_txt[(hdmi_read(sd, 0x0b) & 0x60) >> 5]); 2599 v4l2_info(sd, "HDMI colorspace: %s\n", hdmi_color_space_txt[hdmi_read(sd, 0x53) & 0xf]); 2600 2601 adv76xx_log_infoframes(sd); 2602 } 2603 2604 return 0; 2605 } 2606 2607 static int adv76xx_subscribe_event(struct v4l2_subdev *sd, 2608 struct v4l2_fh *fh, 2609 struct v4l2_event_subscription *sub) 2610 { 2611 switch (sub->type) { 2612 case V4L2_EVENT_SOURCE_CHANGE: 2613 return v4l2_src_change_event_subdev_subscribe(sd, fh, sub); 2614 case V4L2_EVENT_CTRL: 2615 return v4l2_ctrl_subdev_subscribe_event(sd, fh, sub); 2616 default: 2617 return -EINVAL; 2618 } 2619 } 2620 2621 static int adv76xx_registered(struct v4l2_subdev *sd) 2622 { 2623 struct adv76xx_state *state = to_state(sd); 2624 struct i2c_client *client = v4l2_get_subdevdata(sd); 2625 int err; 2626 2627 err = cec_register_adapter(state->cec_adap, &client->dev); 2628 if (err) 2629 cec_delete_adapter(state->cec_adap); 2630 return err; 2631 } 2632 2633 static void adv76xx_unregistered(struct v4l2_subdev *sd) 2634 { 2635 struct adv76xx_state *state = to_state(sd); 2636 2637 cec_unregister_adapter(state->cec_adap); 2638 } 2639 2640 /* ----------------------------------------------------------------------- */ 2641 2642 static const struct v4l2_ctrl_ops adv76xx_ctrl_ops = { 2643 .s_ctrl = adv76xx_s_ctrl, 2644 .g_volatile_ctrl = adv76xx_g_volatile_ctrl, 2645 }; 2646 2647 static const struct v4l2_subdev_core_ops adv76xx_core_ops = { 2648 .log_status = adv76xx_log_status, 2649 .interrupt_service_routine = adv76xx_isr, 2650 .subscribe_event = adv76xx_subscribe_event, 2651 .unsubscribe_event = v4l2_event_subdev_unsubscribe, 2652 #ifdef CONFIG_VIDEO_ADV_DEBUG 2653 .g_register = adv76xx_g_register, 2654 .s_register = adv76xx_s_register, 2655 #endif 2656 }; 2657 2658 static const struct v4l2_subdev_video_ops adv76xx_video_ops = { 2659 .s_routing = adv76xx_s_routing, 2660 .g_input_status = adv76xx_g_input_status, 2661 .s_dv_timings = adv76xx_s_dv_timings, 2662 .g_dv_timings = adv76xx_g_dv_timings, 2663 .query_dv_timings = adv76xx_query_dv_timings, 2664 }; 2665 2666 static const struct v4l2_subdev_pad_ops adv76xx_pad_ops = { 2667 .enum_mbus_code = adv76xx_enum_mbus_code, 2668 .get_selection = adv76xx_get_selection, 2669 .get_fmt = adv76xx_get_format, 2670 .set_fmt = adv76xx_set_format, 2671 .get_edid = adv76xx_get_edid, 2672 .set_edid = adv76xx_set_edid, 2673 .dv_timings_cap = adv76xx_dv_timings_cap, 2674 .enum_dv_timings = adv76xx_enum_dv_timings, 2675 }; 2676 2677 static const struct v4l2_subdev_ops adv76xx_ops = { 2678 .core = &adv76xx_core_ops, 2679 .video = &adv76xx_video_ops, 2680 .pad = &adv76xx_pad_ops, 2681 }; 2682 2683 static const struct v4l2_subdev_internal_ops adv76xx_int_ops = { 2684 .registered = adv76xx_registered, 2685 .unregistered = adv76xx_unregistered, 2686 }; 2687 2688 /* -------------------------- custom ctrls ---------------------------------- */ 2689 2690 static const struct v4l2_ctrl_config adv7604_ctrl_analog_sampling_phase = { 2691 .ops = &adv76xx_ctrl_ops, 2692 .id = V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE, 2693 .name = "Analog Sampling Phase", 2694 .type = V4L2_CTRL_TYPE_INTEGER, 2695 .min = 0, 2696 .max = 0x1f, 2697 .step = 1, 2698 .def = 0, 2699 }; 2700 2701 static const struct v4l2_ctrl_config adv76xx_ctrl_free_run_color_manual = { 2702 .ops = &adv76xx_ctrl_ops, 2703 .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL, 2704 .name = "Free Running Color, Manual", 2705 .type = V4L2_CTRL_TYPE_BOOLEAN, 2706 .min = false, 2707 .max = true, 2708 .step = 1, 2709 .def = false, 2710 }; 2711 2712 static const struct v4l2_ctrl_config adv76xx_ctrl_free_run_color = { 2713 .ops = &adv76xx_ctrl_ops, 2714 .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR, 2715 .name = "Free Running Color", 2716 .type = V4L2_CTRL_TYPE_INTEGER, 2717 .min = 0x0, 2718 .max = 0xffffff, 2719 .step = 0x1, 2720 .def = 0x0, 2721 }; 2722 2723 /* ----------------------------------------------------------------------- */ 2724 2725 struct adv76xx_register_map { 2726 const char *name; 2727 u8 default_addr; 2728 }; 2729 2730 static const struct adv76xx_register_map adv76xx_default_addresses[] = { 2731 [ADV76XX_PAGE_IO] = { "main", 0x4c }, 2732 [ADV7604_PAGE_AVLINK] = { "avlink", 0x42 }, 2733 [ADV76XX_PAGE_CEC] = { "cec", 0x40 }, 2734 [ADV76XX_PAGE_INFOFRAME] = { "infoframe", 0x3e }, 2735 [ADV7604_PAGE_ESDP] = { "esdp", 0x38 }, 2736 [ADV7604_PAGE_DPP] = { "dpp", 0x3c }, 2737 [ADV76XX_PAGE_AFE] = { "afe", 0x26 }, 2738 [ADV76XX_PAGE_REP] = { "rep", 0x32 }, 2739 [ADV76XX_PAGE_EDID] = { "edid", 0x36 }, 2740 [ADV76XX_PAGE_HDMI] = { "hdmi", 0x34 }, 2741 [ADV76XX_PAGE_TEST] = { "test", 0x30 }, 2742 [ADV76XX_PAGE_CP] = { "cp", 0x22 }, 2743 [ADV7604_PAGE_VDP] = { "vdp", 0x24 }, 2744 }; 2745 2746 static int adv76xx_core_init(struct v4l2_subdev *sd) 2747 { 2748 struct adv76xx_state *state = to_state(sd); 2749 const struct adv76xx_chip_info *info = state->info; 2750 struct adv76xx_platform_data *pdata = &state->pdata; 2751 2752 hdmi_write(sd, 0x48, 2753 (pdata->disable_pwrdnb ? 0x80 : 0) | 2754 (pdata->disable_cable_det_rst ? 0x40 : 0)); 2755 2756 disable_input(sd); 2757 2758 if (pdata->default_input >= 0 && 2759 pdata->default_input < state->source_pad) { 2760 state->selected_input = pdata->default_input; 2761 select_input(sd); 2762 enable_input(sd); 2763 } 2764 2765 /* power */ 2766 io_write(sd, 0x0c, 0x42); /* Power up part and power down VDP */ 2767 io_write(sd, 0x0b, 0x44); /* Power down ESDP block */ 2768 cp_write(sd, 0xcf, 0x01); /* Power down macrovision */ 2769 2770 /* video format */ 2771 io_write_clr_set(sd, 0x02, 0x0f, pdata->alt_gamma << 3); 2772 io_write_clr_set(sd, 0x05, 0x0e, pdata->blank_data << 3 | 2773 pdata->insert_av_codes << 2 | 2774 pdata->replicate_av_codes << 1); 2775 adv76xx_setup_format(state); 2776 2777 cp_write(sd, 0x69, 0x30); /* Enable CP CSC */ 2778 2779 /* VS, HS polarities */ 2780 io_write(sd, 0x06, 0xa0 | pdata->inv_vs_pol << 2 | 2781 pdata->inv_hs_pol << 1 | pdata->inv_llc_pol); 2782 2783 /* Adjust drive strength */ 2784 io_write(sd, 0x14, 0x40 | pdata->dr_str_data << 4 | 2785 pdata->dr_str_clk << 2 | 2786 pdata->dr_str_sync); 2787 2788 cp_write(sd, 0xba, (pdata->hdmi_free_run_mode << 1) | 0x01); /* HDMI free run */ 2789 cp_write(sd, 0xf3, 0xdc); /* Low threshold to enter/exit free run mode */ 2790 cp_write(sd, 0xf9, 0x23); /* STDI ch. 1 - LCVS change threshold - 2791 ADI recommended setting [REF_01, c. 2.3.3] */ 2792 cp_write(sd, 0x45, 0x23); /* STDI ch. 2 - LCVS change threshold - 2793 ADI recommended setting [REF_01, c. 2.3.3] */ 2794 cp_write(sd, 0xc9, 0x2d); /* use prim_mode and vid_std as free run resolution 2795 for digital formats */ 2796 2797 /* HDMI audio */ 2798 hdmi_write_clr_set(sd, 0x15, 0x03, 0x03); /* Mute on FIFO over-/underflow [REF_01, c. 1.2.18] */ 2799 hdmi_write_clr_set(sd, 0x1a, 0x0e, 0x08); /* Wait 1 s before unmute */ 2800 hdmi_write_clr_set(sd, 0x68, 0x06, 0x06); /* FIFO reset on over-/underflow [REF_01, c. 1.2.19] */ 2801 2802 /* TODO from platform data */ 2803 afe_write(sd, 0xb5, 0x01); /* Setting MCLK to 256Fs */ 2804 2805 if (adv76xx_has_afe(state)) { 2806 afe_write(sd, 0x02, pdata->ain_sel); /* Select analog input muxing mode */ 2807 io_write_clr_set(sd, 0x30, 1 << 4, pdata->output_bus_lsb_to_msb << 4); 2808 } 2809 2810 /* interrupts */ 2811 io_write(sd, 0x40, 0xc0 | pdata->int1_config); /* Configure INT1 */ 2812 io_write(sd, 0x46, 0x98); /* Enable SSPD, STDI and CP unlocked interrupts */ 2813 io_write(sd, 0x6e, info->fmt_change_digital_mask); /* Enable V_LOCKED and DE_REGEN_LCK interrupts */ 2814 io_write(sd, 0x73, info->cable_det_mask); /* Enable cable detection (+5v) interrupts */ 2815 info->setup_irqs(sd); 2816 2817 return v4l2_ctrl_handler_setup(sd->ctrl_handler); 2818 } 2819 2820 static void adv7604_setup_irqs(struct v4l2_subdev *sd) 2821 { 2822 io_write(sd, 0x41, 0xd7); /* STDI irq for any change, disable INT2 */ 2823 } 2824 2825 static void adv7611_setup_irqs(struct v4l2_subdev *sd) 2826 { 2827 io_write(sd, 0x41, 0xd0); /* STDI irq for any change, disable INT2 */ 2828 } 2829 2830 static void adv7612_setup_irqs(struct v4l2_subdev *sd) 2831 { 2832 io_write(sd, 0x41, 0xd0); /* disable INT2 */ 2833 } 2834 2835 static void adv76xx_unregister_clients(struct adv76xx_state *state) 2836 { 2837 unsigned int i; 2838 2839 for (i = 1; i < ARRAY_SIZE(state->i2c_clients); ++i) { 2840 if (state->i2c_clients[i]) 2841 i2c_unregister_device(state->i2c_clients[i]); 2842 } 2843 } 2844 2845 static struct i2c_client *adv76xx_dummy_client(struct v4l2_subdev *sd, 2846 unsigned int page) 2847 { 2848 struct i2c_client *client = v4l2_get_subdevdata(sd); 2849 struct adv76xx_state *state = to_state(sd); 2850 struct adv76xx_platform_data *pdata = &state->pdata; 2851 unsigned int io_reg = 0xf2 + page; 2852 struct i2c_client *new_client; 2853 2854 if (pdata && pdata->i2c_addresses[page]) 2855 new_client = i2c_new_dummy(client->adapter, 2856 pdata->i2c_addresses[page]); 2857 else 2858 new_client = i2c_new_secondary_device(client, 2859 adv76xx_default_addresses[page].name, 2860 adv76xx_default_addresses[page].default_addr); 2861 2862 if (new_client) 2863 io_write(sd, io_reg, new_client->addr << 1); 2864 2865 return new_client; 2866 } 2867 2868 static const struct adv76xx_reg_seq adv7604_recommended_settings_afe[] = { 2869 /* reset ADI recommended settings for HDMI: */ 2870 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 4. */ 2871 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x0d), 0x04 }, /* HDMI filter optimization */ 2872 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x0d), 0x04 }, /* HDMI filter optimization */ 2873 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x3d), 0x00 }, /* DDC bus active pull-up control */ 2874 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x3e), 0x74 }, /* TMDS PLL optimization */ 2875 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x4e), 0x3b }, /* TMDS PLL optimization */ 2876 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x57), 0x74 }, /* TMDS PLL optimization */ 2877 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x58), 0x63 }, /* TMDS PLL optimization */ 2878 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8d), 0x18 }, /* equaliser */ 2879 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8e), 0x34 }, /* equaliser */ 2880 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x93), 0x88 }, /* equaliser */ 2881 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x94), 0x2e }, /* equaliser */ 2882 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x96), 0x00 }, /* enable automatic EQ changing */ 2883 2884 /* set ADI recommended settings for digitizer */ 2885 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 17. */ 2886 { ADV76XX_REG(ADV76XX_PAGE_AFE, 0x12), 0x7b }, /* ADC noise shaping filter controls */ 2887 { ADV76XX_REG(ADV76XX_PAGE_AFE, 0x0c), 0x1f }, /* CP core gain controls */ 2888 { ADV76XX_REG(ADV76XX_PAGE_CP, 0x3e), 0x04 }, /* CP core pre-gain control */ 2889 { ADV76XX_REG(ADV76XX_PAGE_CP, 0xc3), 0x39 }, /* CP coast control. Graphics mode */ 2890 { ADV76XX_REG(ADV76XX_PAGE_CP, 0x40), 0x5c }, /* CP core pre-gain control. Graphics mode */ 2891 2892 { ADV76XX_REG_SEQ_TERM, 0 }, 2893 }; 2894 2895 static const struct adv76xx_reg_seq adv7604_recommended_settings_hdmi[] = { 2896 /* set ADI recommended settings for HDMI: */ 2897 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 4. */ 2898 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x0d), 0x84 }, /* HDMI filter optimization */ 2899 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x3d), 0x10 }, /* DDC bus active pull-up control */ 2900 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x3e), 0x39 }, /* TMDS PLL optimization */ 2901 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x4e), 0x3b }, /* TMDS PLL optimization */ 2902 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x57), 0xb6 }, /* TMDS PLL optimization */ 2903 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x58), 0x03 }, /* TMDS PLL optimization */ 2904 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8d), 0x18 }, /* equaliser */ 2905 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8e), 0x34 }, /* equaliser */ 2906 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x93), 0x8b }, /* equaliser */ 2907 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x94), 0x2d }, /* equaliser */ 2908 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x96), 0x01 }, /* enable automatic EQ changing */ 2909 2910 /* reset ADI recommended settings for digitizer */ 2911 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 17. */ 2912 { ADV76XX_REG(ADV76XX_PAGE_AFE, 0x12), 0xfb }, /* ADC noise shaping filter controls */ 2913 { ADV76XX_REG(ADV76XX_PAGE_AFE, 0x0c), 0x0d }, /* CP core gain controls */ 2914 2915 { ADV76XX_REG_SEQ_TERM, 0 }, 2916 }; 2917 2918 static const struct adv76xx_reg_seq adv7611_recommended_settings_hdmi[] = { 2919 /* ADV7611 Register Settings Recommendations Rev 1.5, May 2014 */ 2920 { ADV76XX_REG(ADV76XX_PAGE_CP, 0x6c), 0x00 }, 2921 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x9b), 0x03 }, 2922 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x6f), 0x08 }, 2923 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x85), 0x1f }, 2924 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x87), 0x70 }, 2925 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x57), 0xda }, 2926 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x58), 0x01 }, 2927 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x03), 0x98 }, 2928 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x4c), 0x44 }, 2929 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8d), 0x04 }, 2930 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8e), 0x1e }, 2931 2932 { ADV76XX_REG_SEQ_TERM, 0 }, 2933 }; 2934 2935 static const struct adv76xx_reg_seq adv7612_recommended_settings_hdmi[] = { 2936 { ADV76XX_REG(ADV76XX_PAGE_CP, 0x6c), 0x00 }, 2937 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x9b), 0x03 }, 2938 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x6f), 0x08 }, 2939 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x85), 0x1f }, 2940 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x87), 0x70 }, 2941 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x57), 0xda }, 2942 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x58), 0x01 }, 2943 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x03), 0x98 }, 2944 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x4c), 0x44 }, 2945 { ADV76XX_REG_SEQ_TERM, 0 }, 2946 }; 2947 2948 static const struct adv76xx_chip_info adv76xx_chip_info[] = { 2949 [ADV7604] = { 2950 .type = ADV7604, 2951 .has_afe = true, 2952 .max_port = ADV7604_PAD_VGA_COMP, 2953 .num_dv_ports = 4, 2954 .edid_enable_reg = 0x77, 2955 .edid_status_reg = 0x7d, 2956 .lcf_reg = 0xb3, 2957 .tdms_lock_mask = 0xe0, 2958 .cable_det_mask = 0x1e, 2959 .fmt_change_digital_mask = 0xc1, 2960 .cp_csc = 0xfc, 2961 .formats = adv7604_formats, 2962 .nformats = ARRAY_SIZE(adv7604_formats), 2963 .set_termination = adv7604_set_termination, 2964 .setup_irqs = adv7604_setup_irqs, 2965 .read_hdmi_pixelclock = adv7604_read_hdmi_pixelclock, 2966 .read_cable_det = adv7604_read_cable_det, 2967 .recommended_settings = { 2968 [0] = adv7604_recommended_settings_afe, 2969 [1] = adv7604_recommended_settings_hdmi, 2970 }, 2971 .num_recommended_settings = { 2972 [0] = ARRAY_SIZE(adv7604_recommended_settings_afe), 2973 [1] = ARRAY_SIZE(adv7604_recommended_settings_hdmi), 2974 }, 2975 .page_mask = BIT(ADV76XX_PAGE_IO) | BIT(ADV7604_PAGE_AVLINK) | 2976 BIT(ADV76XX_PAGE_CEC) | BIT(ADV76XX_PAGE_INFOFRAME) | 2977 BIT(ADV7604_PAGE_ESDP) | BIT(ADV7604_PAGE_DPP) | 2978 BIT(ADV76XX_PAGE_AFE) | BIT(ADV76XX_PAGE_REP) | 2979 BIT(ADV76XX_PAGE_EDID) | BIT(ADV76XX_PAGE_HDMI) | 2980 BIT(ADV76XX_PAGE_TEST) | BIT(ADV76XX_PAGE_CP) | 2981 BIT(ADV7604_PAGE_VDP), 2982 .linewidth_mask = 0xfff, 2983 .field0_height_mask = 0xfff, 2984 .field1_height_mask = 0xfff, 2985 .hfrontporch_mask = 0x3ff, 2986 .hsync_mask = 0x3ff, 2987 .hbackporch_mask = 0x3ff, 2988 .field0_vfrontporch_mask = 0x1fff, 2989 .field0_vsync_mask = 0x1fff, 2990 .field0_vbackporch_mask = 0x1fff, 2991 .field1_vfrontporch_mask = 0x1fff, 2992 .field1_vsync_mask = 0x1fff, 2993 .field1_vbackporch_mask = 0x1fff, 2994 }, 2995 [ADV7611] = { 2996 .type = ADV7611, 2997 .has_afe = false, 2998 .max_port = ADV76XX_PAD_HDMI_PORT_A, 2999 .num_dv_ports = 1, 3000 .edid_enable_reg = 0x74, 3001 .edid_status_reg = 0x76, 3002 .lcf_reg = 0xa3, 3003 .tdms_lock_mask = 0x43, 3004 .cable_det_mask = 0x01, 3005 .fmt_change_digital_mask = 0x03, 3006 .cp_csc = 0xf4, 3007 .formats = adv7611_formats, 3008 .nformats = ARRAY_SIZE(adv7611_formats), 3009 .set_termination = adv7611_set_termination, 3010 .setup_irqs = adv7611_setup_irqs, 3011 .read_hdmi_pixelclock = adv7611_read_hdmi_pixelclock, 3012 .read_cable_det = adv7611_read_cable_det, 3013 .recommended_settings = { 3014 [1] = adv7611_recommended_settings_hdmi, 3015 }, 3016 .num_recommended_settings = { 3017 [1] = ARRAY_SIZE(adv7611_recommended_settings_hdmi), 3018 }, 3019 .page_mask = BIT(ADV76XX_PAGE_IO) | BIT(ADV76XX_PAGE_CEC) | 3020 BIT(ADV76XX_PAGE_INFOFRAME) | BIT(ADV76XX_PAGE_AFE) | 3021 BIT(ADV76XX_PAGE_REP) | BIT(ADV76XX_PAGE_EDID) | 3022 BIT(ADV76XX_PAGE_HDMI) | BIT(ADV76XX_PAGE_CP), 3023 .linewidth_mask = 0x1fff, 3024 .field0_height_mask = 0x1fff, 3025 .field1_height_mask = 0x1fff, 3026 .hfrontporch_mask = 0x1fff, 3027 .hsync_mask = 0x1fff, 3028 .hbackporch_mask = 0x1fff, 3029 .field0_vfrontporch_mask = 0x3fff, 3030 .field0_vsync_mask = 0x3fff, 3031 .field0_vbackporch_mask = 0x3fff, 3032 .field1_vfrontporch_mask = 0x3fff, 3033 .field1_vsync_mask = 0x3fff, 3034 .field1_vbackporch_mask = 0x3fff, 3035 }, 3036 [ADV7612] = { 3037 .type = ADV7612, 3038 .has_afe = false, 3039 .max_port = ADV76XX_PAD_HDMI_PORT_A, /* B not supported */ 3040 .num_dv_ports = 1, /* normally 2 */ 3041 .edid_enable_reg = 0x74, 3042 .edid_status_reg = 0x76, 3043 .lcf_reg = 0xa3, 3044 .tdms_lock_mask = 0x43, 3045 .cable_det_mask = 0x01, 3046 .fmt_change_digital_mask = 0x03, 3047 .cp_csc = 0xf4, 3048 .formats = adv7612_formats, 3049 .nformats = ARRAY_SIZE(adv7612_formats), 3050 .set_termination = adv7611_set_termination, 3051 .setup_irqs = adv7612_setup_irqs, 3052 .read_hdmi_pixelclock = adv7611_read_hdmi_pixelclock, 3053 .read_cable_det = adv7612_read_cable_det, 3054 .recommended_settings = { 3055 [1] = adv7612_recommended_settings_hdmi, 3056 }, 3057 .num_recommended_settings = { 3058 [1] = ARRAY_SIZE(adv7612_recommended_settings_hdmi), 3059 }, 3060 .page_mask = BIT(ADV76XX_PAGE_IO) | BIT(ADV76XX_PAGE_CEC) | 3061 BIT(ADV76XX_PAGE_INFOFRAME) | BIT(ADV76XX_PAGE_AFE) | 3062 BIT(ADV76XX_PAGE_REP) | BIT(ADV76XX_PAGE_EDID) | 3063 BIT(ADV76XX_PAGE_HDMI) | BIT(ADV76XX_PAGE_CP), 3064 .linewidth_mask = 0x1fff, 3065 .field0_height_mask = 0x1fff, 3066 .field1_height_mask = 0x1fff, 3067 .hfrontporch_mask = 0x1fff, 3068 .hsync_mask = 0x1fff, 3069 .hbackporch_mask = 0x1fff, 3070 .field0_vfrontporch_mask = 0x3fff, 3071 .field0_vsync_mask = 0x3fff, 3072 .field0_vbackporch_mask = 0x3fff, 3073 .field1_vfrontporch_mask = 0x3fff, 3074 .field1_vsync_mask = 0x3fff, 3075 .field1_vbackporch_mask = 0x3fff, 3076 }, 3077 }; 3078 3079 static const struct i2c_device_id adv76xx_i2c_id[] = { 3080 { "adv7604", (kernel_ulong_t)&adv76xx_chip_info[ADV7604] }, 3081 { "adv7611", (kernel_ulong_t)&adv76xx_chip_info[ADV7611] }, 3082 { "adv7612", (kernel_ulong_t)&adv76xx_chip_info[ADV7612] }, 3083 { } 3084 }; 3085 MODULE_DEVICE_TABLE(i2c, adv76xx_i2c_id); 3086 3087 static const struct of_device_id adv76xx_of_id[] __maybe_unused = { 3088 { .compatible = "adi,adv7611", .data = &adv76xx_chip_info[ADV7611] }, 3089 { .compatible = "adi,adv7612", .data = &adv76xx_chip_info[ADV7612] }, 3090 { } 3091 }; 3092 MODULE_DEVICE_TABLE(of, adv76xx_of_id); 3093 3094 static int adv76xx_parse_dt(struct adv76xx_state *state) 3095 { 3096 struct v4l2_fwnode_endpoint bus_cfg; 3097 struct device_node *endpoint; 3098 struct device_node *np; 3099 unsigned int flags; 3100 int ret; 3101 u32 v; 3102 3103 np = state->i2c_clients[ADV76XX_PAGE_IO]->dev.of_node; 3104 3105 /* Parse the endpoint. */ 3106 endpoint = of_graph_get_next_endpoint(np, NULL); 3107 if (!endpoint) 3108 return -EINVAL; 3109 3110 ret = v4l2_fwnode_endpoint_parse(of_fwnode_handle(endpoint), &bus_cfg); 3111 if (ret) { 3112 of_node_put(endpoint); 3113 return ret; 3114 } 3115 3116 of_node_put(endpoint); 3117 3118 if (!of_property_read_u32(np, "default-input", &v)) 3119 state->pdata.default_input = v; 3120 else 3121 state->pdata.default_input = -1; 3122 3123 flags = bus_cfg.bus.parallel.flags; 3124 3125 if (flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH) 3126 state->pdata.inv_hs_pol = 1; 3127 3128 if (flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH) 3129 state->pdata.inv_vs_pol = 1; 3130 3131 if (flags & V4L2_MBUS_PCLK_SAMPLE_RISING) 3132 state->pdata.inv_llc_pol = 1; 3133 3134 if (bus_cfg.bus_type == V4L2_MBUS_BT656) 3135 state->pdata.insert_av_codes = 1; 3136 3137 /* Disable the interrupt for now as no DT-based board uses it. */ 3138 state->pdata.int1_config = ADV76XX_INT1_CONFIG_DISABLED; 3139 3140 /* Hardcode the remaining platform data fields. */ 3141 state->pdata.disable_pwrdnb = 0; 3142 state->pdata.disable_cable_det_rst = 0; 3143 state->pdata.blank_data = 1; 3144 state->pdata.op_format_mode_sel = ADV7604_OP_FORMAT_MODE0; 3145 state->pdata.bus_order = ADV7604_BUS_ORDER_RGB; 3146 state->pdata.dr_str_data = ADV76XX_DR_STR_MEDIUM_HIGH; 3147 state->pdata.dr_str_clk = ADV76XX_DR_STR_MEDIUM_HIGH; 3148 state->pdata.dr_str_sync = ADV76XX_DR_STR_MEDIUM_HIGH; 3149 3150 return 0; 3151 } 3152 3153 static const struct regmap_config adv76xx_regmap_cnf[] = { 3154 { 3155 .name = "io", 3156 .reg_bits = 8, 3157 .val_bits = 8, 3158 3159 .max_register = 0xff, 3160 .cache_type = REGCACHE_NONE, 3161 }, 3162 { 3163 .name = "avlink", 3164 .reg_bits = 8, 3165 .val_bits = 8, 3166 3167 .max_register = 0xff, 3168 .cache_type = REGCACHE_NONE, 3169 }, 3170 { 3171 .name = "cec", 3172 .reg_bits = 8, 3173 .val_bits = 8, 3174 3175 .max_register = 0xff, 3176 .cache_type = REGCACHE_NONE, 3177 }, 3178 { 3179 .name = "infoframe", 3180 .reg_bits = 8, 3181 .val_bits = 8, 3182 3183 .max_register = 0xff, 3184 .cache_type = REGCACHE_NONE, 3185 }, 3186 { 3187 .name = "esdp", 3188 .reg_bits = 8, 3189 .val_bits = 8, 3190 3191 .max_register = 0xff, 3192 .cache_type = REGCACHE_NONE, 3193 }, 3194 { 3195 .name = "epp", 3196 .reg_bits = 8, 3197 .val_bits = 8, 3198 3199 .max_register = 0xff, 3200 .cache_type = REGCACHE_NONE, 3201 }, 3202 { 3203 .name = "afe", 3204 .reg_bits = 8, 3205 .val_bits = 8, 3206 3207 .max_register = 0xff, 3208 .cache_type = REGCACHE_NONE, 3209 }, 3210 { 3211 .name = "rep", 3212 .reg_bits = 8, 3213 .val_bits = 8, 3214 3215 .max_register = 0xff, 3216 .cache_type = REGCACHE_NONE, 3217 }, 3218 { 3219 .name = "edid", 3220 .reg_bits = 8, 3221 .val_bits = 8, 3222 3223 .max_register = 0xff, 3224 .cache_type = REGCACHE_NONE, 3225 }, 3226 3227 { 3228 .name = "hdmi", 3229 .reg_bits = 8, 3230 .val_bits = 8, 3231 3232 .max_register = 0xff, 3233 .cache_type = REGCACHE_NONE, 3234 }, 3235 { 3236 .name = "test", 3237 .reg_bits = 8, 3238 .val_bits = 8, 3239 3240 .max_register = 0xff, 3241 .cache_type = REGCACHE_NONE, 3242 }, 3243 { 3244 .name = "cp", 3245 .reg_bits = 8, 3246 .val_bits = 8, 3247 3248 .max_register = 0xff, 3249 .cache_type = REGCACHE_NONE, 3250 }, 3251 { 3252 .name = "vdp", 3253 .reg_bits = 8, 3254 .val_bits = 8, 3255 3256 .max_register = 0xff, 3257 .cache_type = REGCACHE_NONE, 3258 }, 3259 }; 3260 3261 static int configure_regmap(struct adv76xx_state *state, int region) 3262 { 3263 int err; 3264 3265 if (!state->i2c_clients[region]) 3266 return -ENODEV; 3267 3268 state->regmap[region] = 3269 devm_regmap_init_i2c(state->i2c_clients[region], 3270 &adv76xx_regmap_cnf[region]); 3271 3272 if (IS_ERR(state->regmap[region])) { 3273 err = PTR_ERR(state->regmap[region]); 3274 v4l_err(state->i2c_clients[region], 3275 "Error initializing regmap %d with error %d\n", 3276 region, err); 3277 return -EINVAL; 3278 } 3279 3280 return 0; 3281 } 3282 3283 static int configure_regmaps(struct adv76xx_state *state) 3284 { 3285 int i, err; 3286 3287 for (i = ADV7604_PAGE_AVLINK ; i < ADV76XX_PAGE_MAX; i++) { 3288 err = configure_regmap(state, i); 3289 if (err && (err != -ENODEV)) 3290 return err; 3291 } 3292 return 0; 3293 } 3294 3295 static void adv76xx_reset(struct adv76xx_state *state) 3296 { 3297 if (state->reset_gpio) { 3298 /* ADV76XX can be reset by a low reset pulse of minimum 5 ms. */ 3299 gpiod_set_value_cansleep(state->reset_gpio, 0); 3300 usleep_range(5000, 10000); 3301 gpiod_set_value_cansleep(state->reset_gpio, 1); 3302 /* It is recommended to wait 5 ms after the low pulse before */ 3303 /* an I2C write is performed to the ADV76XX. */ 3304 usleep_range(5000, 10000); 3305 } 3306 } 3307 3308 static int adv76xx_probe(struct i2c_client *client, 3309 const struct i2c_device_id *id) 3310 { 3311 static const struct v4l2_dv_timings cea640x480 = 3312 V4L2_DV_BT_CEA_640X480P59_94; 3313 struct adv76xx_state *state; 3314 struct v4l2_ctrl_handler *hdl; 3315 struct v4l2_ctrl *ctrl; 3316 struct v4l2_subdev *sd; 3317 unsigned int i; 3318 unsigned int val, val2; 3319 int err; 3320 3321 /* Check if the adapter supports the needed features */ 3322 if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA)) 3323 return -EIO; 3324 v4l_dbg(1, debug, client, "detecting adv76xx client on address 0x%x\n", 3325 client->addr << 1); 3326 3327 state = devm_kzalloc(&client->dev, sizeof(*state), GFP_KERNEL); 3328 if (!state) 3329 return -ENOMEM; 3330 3331 state->i2c_clients[ADV76XX_PAGE_IO] = client; 3332 3333 /* initialize variables */ 3334 state->restart_stdi_once = true; 3335 state->selected_input = ~0; 3336 3337 if (IS_ENABLED(CONFIG_OF) && client->dev.of_node) { 3338 const struct of_device_id *oid; 3339 3340 oid = of_match_node(adv76xx_of_id, client->dev.of_node); 3341 state->info = oid->data; 3342 3343 err = adv76xx_parse_dt(state); 3344 if (err < 0) { 3345 v4l_err(client, "DT parsing error\n"); 3346 return err; 3347 } 3348 } else if (client->dev.platform_data) { 3349 struct adv76xx_platform_data *pdata = client->dev.platform_data; 3350 3351 state->info = (const struct adv76xx_chip_info *)id->driver_data; 3352 state->pdata = *pdata; 3353 } else { 3354 v4l_err(client, "No platform data!\n"); 3355 return -ENODEV; 3356 } 3357 3358 /* Request GPIOs. */ 3359 for (i = 0; i < state->info->num_dv_ports; ++i) { 3360 state->hpd_gpio[i] = 3361 devm_gpiod_get_index_optional(&client->dev, "hpd", i, 3362 GPIOD_OUT_LOW); 3363 if (IS_ERR(state->hpd_gpio[i])) 3364 return PTR_ERR(state->hpd_gpio[i]); 3365 3366 if (state->hpd_gpio[i]) 3367 v4l_info(client, "Handling HPD %u GPIO\n", i); 3368 } 3369 state->reset_gpio = devm_gpiod_get_optional(&client->dev, "reset", 3370 GPIOD_OUT_HIGH); 3371 if (IS_ERR(state->reset_gpio)) 3372 return PTR_ERR(state->reset_gpio); 3373 3374 adv76xx_reset(state); 3375 3376 state->timings = cea640x480; 3377 state->format = adv76xx_format_info(state, MEDIA_BUS_FMT_YUYV8_2X8); 3378 3379 sd = &state->sd; 3380 v4l2_i2c_subdev_init(sd, client, &adv76xx_ops); 3381 snprintf(sd->name, sizeof(sd->name), "%s %d-%04x", 3382 id->name, i2c_adapter_id(client->adapter), 3383 client->addr); 3384 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS; 3385 sd->internal_ops = &adv76xx_int_ops; 3386 3387 /* Configure IO Regmap region */ 3388 err = configure_regmap(state, ADV76XX_PAGE_IO); 3389 3390 if (err) { 3391 v4l2_err(sd, "Error configuring IO regmap region\n"); 3392 return -ENODEV; 3393 } 3394 3395 /* 3396 * Verify that the chip is present. On ADV7604 the RD_INFO register only 3397 * identifies the revision, while on ADV7611 it identifies the model as 3398 * well. Use the HDMI slave address on ADV7604 and RD_INFO on ADV7611. 3399 */ 3400 switch (state->info->type) { 3401 case ADV7604: 3402 err = regmap_read(state->regmap[ADV76XX_PAGE_IO], 0xfb, &val); 3403 if (err) { 3404 v4l2_err(sd, "Error %d reading IO Regmap\n", err); 3405 return -ENODEV; 3406 } 3407 if (val != 0x68) { 3408 v4l2_err(sd, "not an adv7604 on address 0x%x\n", 3409 client->addr << 1); 3410 return -ENODEV; 3411 } 3412 break; 3413 case ADV7611: 3414 case ADV7612: 3415 err = regmap_read(state->regmap[ADV76XX_PAGE_IO], 3416 0xea, 3417 &val); 3418 if (err) { 3419 v4l2_err(sd, "Error %d reading IO Regmap\n", err); 3420 return -ENODEV; 3421 } 3422 val2 = val << 8; 3423 err = regmap_read(state->regmap[ADV76XX_PAGE_IO], 3424 0xeb, 3425 &val); 3426 if (err) { 3427 v4l2_err(sd, "Error %d reading IO Regmap\n", err); 3428 return -ENODEV; 3429 } 3430 val |= val2; 3431 if ((state->info->type == ADV7611 && val != 0x2051) || 3432 (state->info->type == ADV7612 && val != 0x2041)) { 3433 v4l2_err(sd, "not an adv761x on address 0x%x\n", 3434 client->addr << 1); 3435 return -ENODEV; 3436 } 3437 break; 3438 } 3439 3440 /* control handlers */ 3441 hdl = &state->hdl; 3442 v4l2_ctrl_handler_init(hdl, adv76xx_has_afe(state) ? 9 : 8); 3443 3444 v4l2_ctrl_new_std(hdl, &adv76xx_ctrl_ops, 3445 V4L2_CID_BRIGHTNESS, -128, 127, 1, 0); 3446 v4l2_ctrl_new_std(hdl, &adv76xx_ctrl_ops, 3447 V4L2_CID_CONTRAST, 0, 255, 1, 128); 3448 v4l2_ctrl_new_std(hdl, &adv76xx_ctrl_ops, 3449 V4L2_CID_SATURATION, 0, 255, 1, 128); 3450 v4l2_ctrl_new_std(hdl, &adv76xx_ctrl_ops, 3451 V4L2_CID_HUE, 0, 128, 1, 0); 3452 ctrl = v4l2_ctrl_new_std_menu(hdl, &adv76xx_ctrl_ops, 3453 V4L2_CID_DV_RX_IT_CONTENT_TYPE, V4L2_DV_IT_CONTENT_TYPE_NO_ITC, 3454 0, V4L2_DV_IT_CONTENT_TYPE_NO_ITC); 3455 if (ctrl) 3456 ctrl->flags |= V4L2_CTRL_FLAG_VOLATILE; 3457 3458 state->detect_tx_5v_ctrl = v4l2_ctrl_new_std(hdl, NULL, 3459 V4L2_CID_DV_RX_POWER_PRESENT, 0, 3460 (1 << state->info->num_dv_ports) - 1, 0, 0); 3461 state->rgb_quantization_range_ctrl = 3462 v4l2_ctrl_new_std_menu(hdl, &adv76xx_ctrl_ops, 3463 V4L2_CID_DV_RX_RGB_RANGE, V4L2_DV_RGB_RANGE_FULL, 3464 0, V4L2_DV_RGB_RANGE_AUTO); 3465 3466 /* custom controls */ 3467 if (adv76xx_has_afe(state)) 3468 state->analog_sampling_phase_ctrl = 3469 v4l2_ctrl_new_custom(hdl, &adv7604_ctrl_analog_sampling_phase, NULL); 3470 state->free_run_color_manual_ctrl = 3471 v4l2_ctrl_new_custom(hdl, &adv76xx_ctrl_free_run_color_manual, NULL); 3472 state->free_run_color_ctrl = 3473 v4l2_ctrl_new_custom(hdl, &adv76xx_ctrl_free_run_color, NULL); 3474 3475 sd->ctrl_handler = hdl; 3476 if (hdl->error) { 3477 err = hdl->error; 3478 goto err_hdl; 3479 } 3480 if (adv76xx_s_detect_tx_5v_ctrl(sd)) { 3481 err = -ENODEV; 3482 goto err_hdl; 3483 } 3484 3485 for (i = 1; i < ADV76XX_PAGE_MAX; ++i) { 3486 if (!(BIT(i) & state->info->page_mask)) 3487 continue; 3488 3489 state->i2c_clients[i] = adv76xx_dummy_client(sd, i); 3490 if (!state->i2c_clients[i]) { 3491 err = -EINVAL; 3492 v4l2_err(sd, "failed to create i2c client %u\n", i); 3493 goto err_i2c; 3494 } 3495 } 3496 3497 INIT_DELAYED_WORK(&state->delayed_work_enable_hotplug, 3498 adv76xx_delayed_work_enable_hotplug); 3499 3500 state->source_pad = state->info->num_dv_ports 3501 + (state->info->has_afe ? 2 : 0); 3502 for (i = 0; i < state->source_pad; ++i) 3503 state->pads[i].flags = MEDIA_PAD_FL_SINK; 3504 state->pads[state->source_pad].flags = MEDIA_PAD_FL_SOURCE; 3505 3506 err = media_entity_pads_init(&sd->entity, state->source_pad + 1, 3507 state->pads); 3508 if (err) 3509 goto err_work_queues; 3510 3511 /* Configure regmaps */ 3512 err = configure_regmaps(state); 3513 if (err) 3514 goto err_entity; 3515 3516 err = adv76xx_core_init(sd); 3517 if (err) 3518 goto err_entity; 3519 3520 #if IS_ENABLED(CONFIG_VIDEO_ADV7604_CEC) 3521 state->cec_adap = cec_allocate_adapter(&adv76xx_cec_adap_ops, 3522 state, dev_name(&client->dev), 3523 CEC_CAP_DEFAULTS, ADV76XX_MAX_ADDRS); 3524 err = PTR_ERR_OR_ZERO(state->cec_adap); 3525 if (err) 3526 goto err_entity; 3527 #endif 3528 3529 v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name, 3530 client->addr << 1, client->adapter->name); 3531 3532 err = v4l2_async_register_subdev(sd); 3533 if (err) 3534 goto err_entity; 3535 3536 return 0; 3537 3538 err_entity: 3539 media_entity_cleanup(&sd->entity); 3540 err_work_queues: 3541 cancel_delayed_work(&state->delayed_work_enable_hotplug); 3542 err_i2c: 3543 adv76xx_unregister_clients(state); 3544 err_hdl: 3545 v4l2_ctrl_handler_free(hdl); 3546 return err; 3547 } 3548 3549 /* ----------------------------------------------------------------------- */ 3550 3551 static int adv76xx_remove(struct i2c_client *client) 3552 { 3553 struct v4l2_subdev *sd = i2c_get_clientdata(client); 3554 struct adv76xx_state *state = to_state(sd); 3555 3556 /* disable interrupts */ 3557 io_write(sd, 0x40, 0); 3558 io_write(sd, 0x41, 0); 3559 io_write(sd, 0x46, 0); 3560 io_write(sd, 0x6e, 0); 3561 io_write(sd, 0x73, 0); 3562 3563 cancel_delayed_work(&state->delayed_work_enable_hotplug); 3564 v4l2_async_unregister_subdev(sd); 3565 media_entity_cleanup(&sd->entity); 3566 adv76xx_unregister_clients(to_state(sd)); 3567 v4l2_ctrl_handler_free(sd->ctrl_handler); 3568 return 0; 3569 } 3570 3571 /* ----------------------------------------------------------------------- */ 3572 3573 static struct i2c_driver adv76xx_driver = { 3574 .driver = { 3575 .name = "adv7604", 3576 .of_match_table = of_match_ptr(adv76xx_of_id), 3577 }, 3578 .probe = adv76xx_probe, 3579 .remove = adv76xx_remove, 3580 .id_table = adv76xx_i2c_id, 3581 }; 3582 3583 module_i2c_driver(adv76xx_driver); 3584