1 /* 2 * adv7604 - Analog Devices ADV7604 video decoder driver 3 * 4 * Copyright 2012 Cisco Systems, Inc. and/or its affiliates. All rights reserved. 5 * 6 * This program is free software; you may redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; version 2 of the License. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 11 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 12 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 13 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 14 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 15 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 16 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 17 * SOFTWARE. 18 * 19 */ 20 21 /* 22 * References (c = chapter, p = page): 23 * REF_01 - Analog devices, ADV7604, Register Settings Recommendations, 24 * Revision 2.5, June 2010 25 * REF_02 - Analog devices, Register map documentation, Documentation of 26 * the register maps, Software manual, Rev. F, June 2010 27 * REF_03 - Analog devices, ADV7604, Hardware Manual, Rev. F, August 2010 28 */ 29 30 #include <linux/delay.h> 31 #include <linux/gpio/consumer.h> 32 #include <linux/hdmi.h> 33 #include <linux/i2c.h> 34 #include <linux/kernel.h> 35 #include <linux/module.h> 36 #include <linux/slab.h> 37 #include <linux/v4l2-dv-timings.h> 38 #include <linux/videodev2.h> 39 #include <linux/workqueue.h> 40 #include <linux/regmap.h> 41 42 #include <media/i2c/adv7604.h> 43 #include <media/v4l2-ctrls.h> 44 #include <media/v4l2-device.h> 45 #include <media/v4l2-event.h> 46 #include <media/v4l2-dv-timings.h> 47 #include <media/v4l2-of.h> 48 49 static int debug; 50 module_param(debug, int, 0644); 51 MODULE_PARM_DESC(debug, "debug level (0-2)"); 52 53 MODULE_DESCRIPTION("Analog Devices ADV7604 video decoder driver"); 54 MODULE_AUTHOR("Hans Verkuil <hans.verkuil@cisco.com>"); 55 MODULE_AUTHOR("Mats Randgaard <mats.randgaard@cisco.com>"); 56 MODULE_LICENSE("GPL"); 57 58 /* ADV7604 system clock frequency */ 59 #define ADV76XX_FSC (28636360) 60 61 #define ADV76XX_RGB_OUT (1 << 1) 62 63 #define ADV76XX_OP_FORMAT_SEL_8BIT (0 << 0) 64 #define ADV7604_OP_FORMAT_SEL_10BIT (1 << 0) 65 #define ADV76XX_OP_FORMAT_SEL_12BIT (2 << 0) 66 67 #define ADV76XX_OP_MODE_SEL_SDR_422 (0 << 5) 68 #define ADV7604_OP_MODE_SEL_DDR_422 (1 << 5) 69 #define ADV76XX_OP_MODE_SEL_SDR_444 (2 << 5) 70 #define ADV7604_OP_MODE_SEL_DDR_444 (3 << 5) 71 #define ADV76XX_OP_MODE_SEL_SDR_422_2X (4 << 5) 72 #define ADV7604_OP_MODE_SEL_ADI_CM (5 << 5) 73 74 #define ADV76XX_OP_CH_SEL_GBR (0 << 5) 75 #define ADV76XX_OP_CH_SEL_GRB (1 << 5) 76 #define ADV76XX_OP_CH_SEL_BGR (2 << 5) 77 #define ADV76XX_OP_CH_SEL_RGB (3 << 5) 78 #define ADV76XX_OP_CH_SEL_BRG (4 << 5) 79 #define ADV76XX_OP_CH_SEL_RBG (5 << 5) 80 81 #define ADV76XX_OP_SWAP_CB_CR (1 << 0) 82 83 enum adv76xx_type { 84 ADV7604, 85 ADV7611, 86 ADV7612, 87 }; 88 89 struct adv76xx_reg_seq { 90 unsigned int reg; 91 u8 val; 92 }; 93 94 struct adv76xx_format_info { 95 u32 code; 96 u8 op_ch_sel; 97 bool rgb_out; 98 bool swap_cb_cr; 99 u8 op_format_sel; 100 }; 101 102 struct adv76xx_cfg_read_infoframe { 103 const char *desc; 104 u8 present_mask; 105 u8 head_addr; 106 u8 payload_addr; 107 }; 108 109 struct adv76xx_chip_info { 110 enum adv76xx_type type; 111 112 bool has_afe; 113 unsigned int max_port; 114 unsigned int num_dv_ports; 115 116 unsigned int edid_enable_reg; 117 unsigned int edid_status_reg; 118 unsigned int lcf_reg; 119 120 unsigned int cable_det_mask; 121 unsigned int tdms_lock_mask; 122 unsigned int fmt_change_digital_mask; 123 unsigned int cp_csc; 124 125 const struct adv76xx_format_info *formats; 126 unsigned int nformats; 127 128 void (*set_termination)(struct v4l2_subdev *sd, bool enable); 129 void (*setup_irqs)(struct v4l2_subdev *sd); 130 unsigned int (*read_hdmi_pixelclock)(struct v4l2_subdev *sd); 131 unsigned int (*read_cable_det)(struct v4l2_subdev *sd); 132 133 /* 0 = AFE, 1 = HDMI */ 134 const struct adv76xx_reg_seq *recommended_settings[2]; 135 unsigned int num_recommended_settings[2]; 136 137 unsigned long page_mask; 138 139 /* Masks for timings */ 140 unsigned int linewidth_mask; 141 unsigned int field0_height_mask; 142 unsigned int field1_height_mask; 143 unsigned int hfrontporch_mask; 144 unsigned int hsync_mask; 145 unsigned int hbackporch_mask; 146 unsigned int field0_vfrontporch_mask; 147 unsigned int field1_vfrontporch_mask; 148 unsigned int field0_vsync_mask; 149 unsigned int field1_vsync_mask; 150 unsigned int field0_vbackporch_mask; 151 unsigned int field1_vbackporch_mask; 152 }; 153 154 /* 155 ********************************************************************** 156 * 157 * Arrays with configuration parameters for the ADV7604 158 * 159 ********************************************************************** 160 */ 161 162 struct adv76xx_state { 163 const struct adv76xx_chip_info *info; 164 struct adv76xx_platform_data pdata; 165 166 struct gpio_desc *hpd_gpio[4]; 167 168 struct v4l2_subdev sd; 169 struct media_pad pads[ADV76XX_PAD_MAX]; 170 unsigned int source_pad; 171 172 struct v4l2_ctrl_handler hdl; 173 174 enum adv76xx_pad selected_input; 175 176 struct v4l2_dv_timings timings; 177 const struct adv76xx_format_info *format; 178 179 struct { 180 u8 edid[256]; 181 u32 present; 182 unsigned blocks; 183 } edid; 184 u16 spa_port_a[2]; 185 struct v4l2_fract aspect_ratio; 186 u32 rgb_quantization_range; 187 struct workqueue_struct *work_queues; 188 struct delayed_work delayed_work_enable_hotplug; 189 bool restart_stdi_once; 190 191 /* i2c clients */ 192 struct i2c_client *i2c_clients[ADV76XX_PAGE_MAX]; 193 194 /* Regmaps */ 195 struct regmap *regmap[ADV76XX_PAGE_MAX]; 196 197 /* controls */ 198 struct v4l2_ctrl *detect_tx_5v_ctrl; 199 struct v4l2_ctrl *analog_sampling_phase_ctrl; 200 struct v4l2_ctrl *free_run_color_manual_ctrl; 201 struct v4l2_ctrl *free_run_color_ctrl; 202 struct v4l2_ctrl *rgb_quantization_range_ctrl; 203 }; 204 205 static bool adv76xx_has_afe(struct adv76xx_state *state) 206 { 207 return state->info->has_afe; 208 } 209 210 /* Unsupported timings. This device cannot support 720p30. */ 211 static const struct v4l2_dv_timings adv76xx_timings_exceptions[] = { 212 V4L2_DV_BT_CEA_1280X720P30, 213 { } 214 }; 215 216 static bool adv76xx_check_dv_timings(const struct v4l2_dv_timings *t, void *hdl) 217 { 218 int i; 219 220 for (i = 0; adv76xx_timings_exceptions[i].bt.width; i++) 221 if (v4l2_match_dv_timings(t, adv76xx_timings_exceptions + i, 0, false)) 222 return false; 223 return true; 224 } 225 226 struct adv76xx_video_standards { 227 struct v4l2_dv_timings timings; 228 u8 vid_std; 229 u8 v_freq; 230 }; 231 232 /* sorted by number of lines */ 233 static const struct adv76xx_video_standards adv7604_prim_mode_comp[] = { 234 /* { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 }, TODO flickering */ 235 { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 }, 236 { V4L2_DV_BT_CEA_1280X720P50, 0x19, 0x01 }, 237 { V4L2_DV_BT_CEA_1280X720P60, 0x19, 0x00 }, 238 { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 }, 239 { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 }, 240 { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 }, 241 { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 }, 242 { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 }, 243 /* TODO add 1920x1080P60_RB (CVT timing) */ 244 { }, 245 }; 246 247 /* sorted by number of lines */ 248 static const struct adv76xx_video_standards adv7604_prim_mode_gr[] = { 249 { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 }, 250 { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 }, 251 { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 }, 252 { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 }, 253 { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 }, 254 { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 }, 255 { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 }, 256 { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 }, 257 { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 }, 258 { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 }, 259 { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 }, 260 { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 }, 261 { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 }, 262 { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 }, 263 { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 }, 264 { V4L2_DV_BT_DMT_1360X768P60, 0x12, 0x00 }, 265 { V4L2_DV_BT_DMT_1366X768P60, 0x13, 0x00 }, 266 { V4L2_DV_BT_DMT_1400X1050P60, 0x14, 0x00 }, 267 { V4L2_DV_BT_DMT_1400X1050P75, 0x15, 0x00 }, 268 { V4L2_DV_BT_DMT_1600X1200P60, 0x16, 0x00 }, /* TODO not tested */ 269 /* TODO add 1600X1200P60_RB (not a DMT timing) */ 270 { V4L2_DV_BT_DMT_1680X1050P60, 0x18, 0x00 }, 271 { V4L2_DV_BT_DMT_1920X1200P60_RB, 0x19, 0x00 }, /* TODO not tested */ 272 { }, 273 }; 274 275 /* sorted by number of lines */ 276 static const struct adv76xx_video_standards adv76xx_prim_mode_hdmi_comp[] = { 277 { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 }, 278 { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 }, 279 { V4L2_DV_BT_CEA_1280X720P50, 0x13, 0x01 }, 280 { V4L2_DV_BT_CEA_1280X720P60, 0x13, 0x00 }, 281 { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 }, 282 { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 }, 283 { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 }, 284 { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 }, 285 { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 }, 286 { }, 287 }; 288 289 /* sorted by number of lines */ 290 static const struct adv76xx_video_standards adv76xx_prim_mode_hdmi_gr[] = { 291 { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 }, 292 { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 }, 293 { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 }, 294 { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 }, 295 { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 }, 296 { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 }, 297 { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 }, 298 { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 }, 299 { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 }, 300 { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 }, 301 { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 }, 302 { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 }, 303 { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 }, 304 { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 }, 305 { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 }, 306 { }, 307 }; 308 309 static const struct v4l2_event adv76xx_ev_fmt = { 310 .type = V4L2_EVENT_SOURCE_CHANGE, 311 .u.src_change.changes = V4L2_EVENT_SRC_CH_RESOLUTION, 312 }; 313 314 /* ----------------------------------------------------------------------- */ 315 316 static inline struct adv76xx_state *to_state(struct v4l2_subdev *sd) 317 { 318 return container_of(sd, struct adv76xx_state, sd); 319 } 320 321 static inline unsigned htotal(const struct v4l2_bt_timings *t) 322 { 323 return V4L2_DV_BT_FRAME_WIDTH(t); 324 } 325 326 static inline unsigned vtotal(const struct v4l2_bt_timings *t) 327 { 328 return V4L2_DV_BT_FRAME_HEIGHT(t); 329 } 330 331 /* ----------------------------------------------------------------------- */ 332 333 static int adv76xx_read_check(struct adv76xx_state *state, 334 int client_page, u8 reg) 335 { 336 struct i2c_client *client = state->i2c_clients[client_page]; 337 int err; 338 unsigned int val; 339 340 err = regmap_read(state->regmap[client_page], reg, &val); 341 342 if (err) { 343 v4l_err(client, "error reading %02x, %02x\n", 344 client->addr, reg); 345 return err; 346 } 347 return val; 348 } 349 350 /* adv76xx_write_block(): Write raw data with a maximum of I2C_SMBUS_BLOCK_MAX 351 * size to one or more registers. 352 * 353 * A value of zero will be returned on success, a negative errno will 354 * be returned in error cases. 355 */ 356 static int adv76xx_write_block(struct adv76xx_state *state, int client_page, 357 unsigned int init_reg, const void *val, 358 size_t val_len) 359 { 360 struct regmap *regmap = state->regmap[client_page]; 361 362 if (val_len > I2C_SMBUS_BLOCK_MAX) 363 val_len = I2C_SMBUS_BLOCK_MAX; 364 365 return regmap_raw_write(regmap, init_reg, val, val_len); 366 } 367 368 /* ----------------------------------------------------------------------- */ 369 370 static inline int io_read(struct v4l2_subdev *sd, u8 reg) 371 { 372 struct adv76xx_state *state = to_state(sd); 373 374 return adv76xx_read_check(state, ADV76XX_PAGE_IO, reg); 375 } 376 377 static inline int io_write(struct v4l2_subdev *sd, u8 reg, u8 val) 378 { 379 struct adv76xx_state *state = to_state(sd); 380 381 return regmap_write(state->regmap[ADV76XX_PAGE_IO], reg, val); 382 } 383 384 static inline int io_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) 385 { 386 return io_write(sd, reg, (io_read(sd, reg) & ~mask) | val); 387 } 388 389 static inline int avlink_read(struct v4l2_subdev *sd, u8 reg) 390 { 391 struct adv76xx_state *state = to_state(sd); 392 393 return adv76xx_read_check(state, ADV7604_PAGE_AVLINK, reg); 394 } 395 396 static inline int avlink_write(struct v4l2_subdev *sd, u8 reg, u8 val) 397 { 398 struct adv76xx_state *state = to_state(sd); 399 400 return regmap_write(state->regmap[ADV7604_PAGE_AVLINK], reg, val); 401 } 402 403 static inline int cec_read(struct v4l2_subdev *sd, u8 reg) 404 { 405 struct adv76xx_state *state = to_state(sd); 406 407 return adv76xx_read_check(state, ADV76XX_PAGE_CEC, reg); 408 } 409 410 static inline int cec_write(struct v4l2_subdev *sd, u8 reg, u8 val) 411 { 412 struct adv76xx_state *state = to_state(sd); 413 414 return regmap_write(state->regmap[ADV76XX_PAGE_CEC], reg, val); 415 } 416 417 static inline int infoframe_read(struct v4l2_subdev *sd, u8 reg) 418 { 419 struct adv76xx_state *state = to_state(sd); 420 421 return adv76xx_read_check(state, ADV76XX_PAGE_INFOFRAME, reg); 422 } 423 424 static inline int infoframe_write(struct v4l2_subdev *sd, u8 reg, u8 val) 425 { 426 struct adv76xx_state *state = to_state(sd); 427 428 return regmap_write(state->regmap[ADV76XX_PAGE_INFOFRAME], reg, val); 429 } 430 431 static inline int afe_read(struct v4l2_subdev *sd, u8 reg) 432 { 433 struct adv76xx_state *state = to_state(sd); 434 435 return adv76xx_read_check(state, ADV76XX_PAGE_AFE, reg); 436 } 437 438 static inline int afe_write(struct v4l2_subdev *sd, u8 reg, u8 val) 439 { 440 struct adv76xx_state *state = to_state(sd); 441 442 return regmap_write(state->regmap[ADV76XX_PAGE_AFE], reg, val); 443 } 444 445 static inline int rep_read(struct v4l2_subdev *sd, u8 reg) 446 { 447 struct adv76xx_state *state = to_state(sd); 448 449 return adv76xx_read_check(state, ADV76XX_PAGE_REP, reg); 450 } 451 452 static inline int rep_write(struct v4l2_subdev *sd, u8 reg, u8 val) 453 { 454 struct adv76xx_state *state = to_state(sd); 455 456 return regmap_write(state->regmap[ADV76XX_PAGE_REP], reg, val); 457 } 458 459 static inline int rep_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) 460 { 461 return rep_write(sd, reg, (rep_read(sd, reg) & ~mask) | val); 462 } 463 464 static inline int edid_read(struct v4l2_subdev *sd, u8 reg) 465 { 466 struct adv76xx_state *state = to_state(sd); 467 468 return adv76xx_read_check(state, ADV76XX_PAGE_EDID, reg); 469 } 470 471 static inline int edid_write(struct v4l2_subdev *sd, u8 reg, u8 val) 472 { 473 struct adv76xx_state *state = to_state(sd); 474 475 return regmap_write(state->regmap[ADV76XX_PAGE_EDID], reg, val); 476 } 477 478 static inline int edid_write_block(struct v4l2_subdev *sd, 479 unsigned int total_len, const u8 *val) 480 { 481 struct adv76xx_state *state = to_state(sd); 482 int err = 0; 483 int i = 0; 484 int len = 0; 485 486 v4l2_dbg(2, debug, sd, "%s: write EDID block (%d byte)\n", 487 __func__, total_len); 488 489 while (!err && i < total_len) { 490 len = (total_len - i) > I2C_SMBUS_BLOCK_MAX ? 491 I2C_SMBUS_BLOCK_MAX : 492 (total_len - i); 493 494 err = adv76xx_write_block(state, ADV76XX_PAGE_EDID, 495 i, val + i, len); 496 i += len; 497 } 498 499 return err; 500 } 501 502 static void adv76xx_set_hpd(struct adv76xx_state *state, unsigned int hpd) 503 { 504 unsigned int i; 505 506 for (i = 0; i < state->info->num_dv_ports; ++i) 507 gpiod_set_value_cansleep(state->hpd_gpio[i], hpd & BIT(i)); 508 509 v4l2_subdev_notify(&state->sd, ADV76XX_HOTPLUG, &hpd); 510 } 511 512 static void adv76xx_delayed_work_enable_hotplug(struct work_struct *work) 513 { 514 struct delayed_work *dwork = to_delayed_work(work); 515 struct adv76xx_state *state = container_of(dwork, struct adv76xx_state, 516 delayed_work_enable_hotplug); 517 struct v4l2_subdev *sd = &state->sd; 518 519 v4l2_dbg(2, debug, sd, "%s: enable hotplug\n", __func__); 520 521 adv76xx_set_hpd(state, state->edid.present); 522 } 523 524 static inline int hdmi_read(struct v4l2_subdev *sd, u8 reg) 525 { 526 struct adv76xx_state *state = to_state(sd); 527 528 return adv76xx_read_check(state, ADV76XX_PAGE_HDMI, reg); 529 } 530 531 static u16 hdmi_read16(struct v4l2_subdev *sd, u8 reg, u16 mask) 532 { 533 return ((hdmi_read(sd, reg) << 8) | hdmi_read(sd, reg + 1)) & mask; 534 } 535 536 static inline int hdmi_write(struct v4l2_subdev *sd, u8 reg, u8 val) 537 { 538 struct adv76xx_state *state = to_state(sd); 539 540 return regmap_write(state->regmap[ADV76XX_PAGE_HDMI], reg, val); 541 } 542 543 static inline int hdmi_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) 544 { 545 return hdmi_write(sd, reg, (hdmi_read(sd, reg) & ~mask) | val); 546 } 547 548 static inline int test_write(struct v4l2_subdev *sd, u8 reg, u8 val) 549 { 550 struct adv76xx_state *state = to_state(sd); 551 552 return regmap_write(state->regmap[ADV76XX_PAGE_TEST], reg, val); 553 } 554 555 static inline int cp_read(struct v4l2_subdev *sd, u8 reg) 556 { 557 struct adv76xx_state *state = to_state(sd); 558 559 return adv76xx_read_check(state, ADV76XX_PAGE_CP, reg); 560 } 561 562 static u16 cp_read16(struct v4l2_subdev *sd, u8 reg, u16 mask) 563 { 564 return ((cp_read(sd, reg) << 8) | cp_read(sd, reg + 1)) & mask; 565 } 566 567 static inline int cp_write(struct v4l2_subdev *sd, u8 reg, u8 val) 568 { 569 struct adv76xx_state *state = to_state(sd); 570 571 return regmap_write(state->regmap[ADV76XX_PAGE_CP], reg, val); 572 } 573 574 static inline int cp_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) 575 { 576 return cp_write(sd, reg, (cp_read(sd, reg) & ~mask) | val); 577 } 578 579 static inline int vdp_read(struct v4l2_subdev *sd, u8 reg) 580 { 581 struct adv76xx_state *state = to_state(sd); 582 583 return adv76xx_read_check(state, ADV7604_PAGE_VDP, reg); 584 } 585 586 static inline int vdp_write(struct v4l2_subdev *sd, u8 reg, u8 val) 587 { 588 struct adv76xx_state *state = to_state(sd); 589 590 return regmap_write(state->regmap[ADV7604_PAGE_VDP], reg, val); 591 } 592 593 #define ADV76XX_REG(page, offset) (((page) << 8) | (offset)) 594 #define ADV76XX_REG_SEQ_TERM 0xffff 595 596 #ifdef CONFIG_VIDEO_ADV_DEBUG 597 static int adv76xx_read_reg(struct v4l2_subdev *sd, unsigned int reg) 598 { 599 struct adv76xx_state *state = to_state(sd); 600 unsigned int page = reg >> 8; 601 unsigned int val; 602 int err; 603 604 if (!(BIT(page) & state->info->page_mask)) 605 return -EINVAL; 606 607 reg &= 0xff; 608 err = regmap_read(state->regmap[page], reg, &val); 609 610 return err ? err : val; 611 } 612 #endif 613 614 static int adv76xx_write_reg(struct v4l2_subdev *sd, unsigned int reg, u8 val) 615 { 616 struct adv76xx_state *state = to_state(sd); 617 unsigned int page = reg >> 8; 618 619 if (!(BIT(page) & state->info->page_mask)) 620 return -EINVAL; 621 622 reg &= 0xff; 623 624 return regmap_write(state->regmap[page], reg, val); 625 } 626 627 static void adv76xx_write_reg_seq(struct v4l2_subdev *sd, 628 const struct adv76xx_reg_seq *reg_seq) 629 { 630 unsigned int i; 631 632 for (i = 0; reg_seq[i].reg != ADV76XX_REG_SEQ_TERM; i++) 633 adv76xx_write_reg(sd, reg_seq[i].reg, reg_seq[i].val); 634 } 635 636 /* ----------------------------------------------------------------------------- 637 * Format helpers 638 */ 639 640 static const struct adv76xx_format_info adv7604_formats[] = { 641 { MEDIA_BUS_FMT_RGB888_1X24, ADV76XX_OP_CH_SEL_RGB, true, false, 642 ADV76XX_OP_MODE_SEL_SDR_444 | ADV76XX_OP_FORMAT_SEL_8BIT }, 643 { MEDIA_BUS_FMT_YUYV8_2X8, ADV76XX_OP_CH_SEL_RGB, false, false, 644 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT }, 645 { MEDIA_BUS_FMT_YVYU8_2X8, ADV76XX_OP_CH_SEL_RGB, false, true, 646 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT }, 647 { MEDIA_BUS_FMT_YUYV10_2X10, ADV76XX_OP_CH_SEL_RGB, false, false, 648 ADV76XX_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_10BIT }, 649 { MEDIA_BUS_FMT_YVYU10_2X10, ADV76XX_OP_CH_SEL_RGB, false, true, 650 ADV76XX_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_10BIT }, 651 { MEDIA_BUS_FMT_YUYV12_2X12, ADV76XX_OP_CH_SEL_RGB, false, false, 652 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_12BIT }, 653 { MEDIA_BUS_FMT_YVYU12_2X12, ADV76XX_OP_CH_SEL_RGB, false, true, 654 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_12BIT }, 655 { MEDIA_BUS_FMT_UYVY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, false, 656 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT }, 657 { MEDIA_BUS_FMT_VYUY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, true, 658 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT }, 659 { MEDIA_BUS_FMT_YUYV8_1X16, ADV76XX_OP_CH_SEL_RGB, false, false, 660 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT }, 661 { MEDIA_BUS_FMT_YVYU8_1X16, ADV76XX_OP_CH_SEL_RGB, false, true, 662 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT }, 663 { MEDIA_BUS_FMT_UYVY10_1X20, ADV76XX_OP_CH_SEL_RBG, false, false, 664 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT }, 665 { MEDIA_BUS_FMT_VYUY10_1X20, ADV76XX_OP_CH_SEL_RBG, false, true, 666 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT }, 667 { MEDIA_BUS_FMT_YUYV10_1X20, ADV76XX_OP_CH_SEL_RGB, false, false, 668 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT }, 669 { MEDIA_BUS_FMT_YVYU10_1X20, ADV76XX_OP_CH_SEL_RGB, false, true, 670 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT }, 671 { MEDIA_BUS_FMT_UYVY12_1X24, ADV76XX_OP_CH_SEL_RBG, false, false, 672 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT }, 673 { MEDIA_BUS_FMT_VYUY12_1X24, ADV76XX_OP_CH_SEL_RBG, false, true, 674 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT }, 675 { MEDIA_BUS_FMT_YUYV12_1X24, ADV76XX_OP_CH_SEL_RGB, false, false, 676 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT }, 677 { MEDIA_BUS_FMT_YVYU12_1X24, ADV76XX_OP_CH_SEL_RGB, false, true, 678 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT }, 679 }; 680 681 static const struct adv76xx_format_info adv7611_formats[] = { 682 { MEDIA_BUS_FMT_RGB888_1X24, ADV76XX_OP_CH_SEL_RGB, true, false, 683 ADV76XX_OP_MODE_SEL_SDR_444 | ADV76XX_OP_FORMAT_SEL_8BIT }, 684 { MEDIA_BUS_FMT_YUYV8_2X8, ADV76XX_OP_CH_SEL_RGB, false, false, 685 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT }, 686 { MEDIA_BUS_FMT_YVYU8_2X8, ADV76XX_OP_CH_SEL_RGB, false, true, 687 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT }, 688 { MEDIA_BUS_FMT_YUYV12_2X12, ADV76XX_OP_CH_SEL_RGB, false, false, 689 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_12BIT }, 690 { MEDIA_BUS_FMT_YVYU12_2X12, ADV76XX_OP_CH_SEL_RGB, false, true, 691 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_12BIT }, 692 { MEDIA_BUS_FMT_UYVY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, false, 693 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT }, 694 { MEDIA_BUS_FMT_VYUY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, true, 695 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT }, 696 { MEDIA_BUS_FMT_YUYV8_1X16, ADV76XX_OP_CH_SEL_RGB, false, false, 697 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT }, 698 { MEDIA_BUS_FMT_YVYU8_1X16, ADV76XX_OP_CH_SEL_RGB, false, true, 699 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT }, 700 { MEDIA_BUS_FMT_UYVY12_1X24, ADV76XX_OP_CH_SEL_RBG, false, false, 701 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT }, 702 { MEDIA_BUS_FMT_VYUY12_1X24, ADV76XX_OP_CH_SEL_RBG, false, true, 703 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT }, 704 { MEDIA_BUS_FMT_YUYV12_1X24, ADV76XX_OP_CH_SEL_RGB, false, false, 705 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT }, 706 { MEDIA_BUS_FMT_YVYU12_1X24, ADV76XX_OP_CH_SEL_RGB, false, true, 707 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT }, 708 }; 709 710 static const struct adv76xx_format_info adv7612_formats[] = { 711 { MEDIA_BUS_FMT_RGB888_1X24, ADV76XX_OP_CH_SEL_RGB, true, false, 712 ADV76XX_OP_MODE_SEL_SDR_444 | ADV76XX_OP_FORMAT_SEL_8BIT }, 713 { MEDIA_BUS_FMT_YUYV8_2X8, ADV76XX_OP_CH_SEL_RGB, false, false, 714 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT }, 715 { MEDIA_BUS_FMT_YVYU8_2X8, ADV76XX_OP_CH_SEL_RGB, false, true, 716 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT }, 717 { MEDIA_BUS_FMT_UYVY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, false, 718 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT }, 719 { MEDIA_BUS_FMT_VYUY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, true, 720 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT }, 721 { MEDIA_BUS_FMT_YUYV8_1X16, ADV76XX_OP_CH_SEL_RGB, false, false, 722 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT }, 723 { MEDIA_BUS_FMT_YVYU8_1X16, ADV76XX_OP_CH_SEL_RGB, false, true, 724 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT }, 725 }; 726 727 static const struct adv76xx_format_info * 728 adv76xx_format_info(struct adv76xx_state *state, u32 code) 729 { 730 unsigned int i; 731 732 for (i = 0; i < state->info->nformats; ++i) { 733 if (state->info->formats[i].code == code) 734 return &state->info->formats[i]; 735 } 736 737 return NULL; 738 } 739 740 /* ----------------------------------------------------------------------- */ 741 742 static inline bool is_analog_input(struct v4l2_subdev *sd) 743 { 744 struct adv76xx_state *state = to_state(sd); 745 746 return state->selected_input == ADV7604_PAD_VGA_RGB || 747 state->selected_input == ADV7604_PAD_VGA_COMP; 748 } 749 750 static inline bool is_digital_input(struct v4l2_subdev *sd) 751 { 752 struct adv76xx_state *state = to_state(sd); 753 754 return state->selected_input == ADV76XX_PAD_HDMI_PORT_A || 755 state->selected_input == ADV7604_PAD_HDMI_PORT_B || 756 state->selected_input == ADV7604_PAD_HDMI_PORT_C || 757 state->selected_input == ADV7604_PAD_HDMI_PORT_D; 758 } 759 760 static const struct v4l2_dv_timings_cap adv7604_timings_cap_analog = { 761 .type = V4L2_DV_BT_656_1120, 762 /* keep this initialization for compatibility with GCC < 4.4.6 */ 763 .reserved = { 0 }, 764 V4L2_INIT_BT_TIMINGS(0, 1920, 0, 1200, 25000000, 170000000, 765 V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT | 766 V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT, 767 V4L2_DV_BT_CAP_PROGRESSIVE | V4L2_DV_BT_CAP_REDUCED_BLANKING | 768 V4L2_DV_BT_CAP_CUSTOM) 769 }; 770 771 static const struct v4l2_dv_timings_cap adv76xx_timings_cap_digital = { 772 .type = V4L2_DV_BT_656_1120, 773 /* keep this initialization for compatibility with GCC < 4.4.6 */ 774 .reserved = { 0 }, 775 V4L2_INIT_BT_TIMINGS(0, 1920, 0, 1200, 25000000, 225000000, 776 V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT | 777 V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT, 778 V4L2_DV_BT_CAP_PROGRESSIVE | V4L2_DV_BT_CAP_REDUCED_BLANKING | 779 V4L2_DV_BT_CAP_CUSTOM) 780 }; 781 782 /* 783 * Return the DV timings capabilities for the requested sink pad. As a special 784 * case, pad value -1 returns the capabilities for the currently selected input. 785 */ 786 static const struct v4l2_dv_timings_cap * 787 adv76xx_get_dv_timings_cap(struct v4l2_subdev *sd, int pad) 788 { 789 if (pad == -1) { 790 struct adv76xx_state *state = to_state(sd); 791 792 pad = state->selected_input; 793 } 794 795 switch (pad) { 796 case ADV76XX_PAD_HDMI_PORT_A: 797 case ADV7604_PAD_HDMI_PORT_B: 798 case ADV7604_PAD_HDMI_PORT_C: 799 case ADV7604_PAD_HDMI_PORT_D: 800 return &adv76xx_timings_cap_digital; 801 802 case ADV7604_PAD_VGA_RGB: 803 case ADV7604_PAD_VGA_COMP: 804 default: 805 return &adv7604_timings_cap_analog; 806 } 807 } 808 809 810 /* ----------------------------------------------------------------------- */ 811 812 #ifdef CONFIG_VIDEO_ADV_DEBUG 813 static void adv76xx_inv_register(struct v4l2_subdev *sd) 814 { 815 v4l2_info(sd, "0x000-0x0ff: IO Map\n"); 816 v4l2_info(sd, "0x100-0x1ff: AVLink Map\n"); 817 v4l2_info(sd, "0x200-0x2ff: CEC Map\n"); 818 v4l2_info(sd, "0x300-0x3ff: InfoFrame Map\n"); 819 v4l2_info(sd, "0x400-0x4ff: ESDP Map\n"); 820 v4l2_info(sd, "0x500-0x5ff: DPP Map\n"); 821 v4l2_info(sd, "0x600-0x6ff: AFE Map\n"); 822 v4l2_info(sd, "0x700-0x7ff: Repeater Map\n"); 823 v4l2_info(sd, "0x800-0x8ff: EDID Map\n"); 824 v4l2_info(sd, "0x900-0x9ff: HDMI Map\n"); 825 v4l2_info(sd, "0xa00-0xaff: Test Map\n"); 826 v4l2_info(sd, "0xb00-0xbff: CP Map\n"); 827 v4l2_info(sd, "0xc00-0xcff: VDP Map\n"); 828 } 829 830 static int adv76xx_g_register(struct v4l2_subdev *sd, 831 struct v4l2_dbg_register *reg) 832 { 833 int ret; 834 835 ret = adv76xx_read_reg(sd, reg->reg); 836 if (ret < 0) { 837 v4l2_info(sd, "Register %03llx not supported\n", reg->reg); 838 adv76xx_inv_register(sd); 839 return ret; 840 } 841 842 reg->size = 1; 843 reg->val = ret; 844 845 return 0; 846 } 847 848 static int adv76xx_s_register(struct v4l2_subdev *sd, 849 const struct v4l2_dbg_register *reg) 850 { 851 int ret; 852 853 ret = adv76xx_write_reg(sd, reg->reg, reg->val); 854 if (ret < 0) { 855 v4l2_info(sd, "Register %03llx not supported\n", reg->reg); 856 adv76xx_inv_register(sd); 857 return ret; 858 } 859 860 return 0; 861 } 862 #endif 863 864 static unsigned int adv7604_read_cable_det(struct v4l2_subdev *sd) 865 { 866 u8 value = io_read(sd, 0x6f); 867 868 return ((value & 0x10) >> 4) 869 | ((value & 0x08) >> 2) 870 | ((value & 0x04) << 0) 871 | ((value & 0x02) << 2); 872 } 873 874 static unsigned int adv7611_read_cable_det(struct v4l2_subdev *sd) 875 { 876 u8 value = io_read(sd, 0x6f); 877 878 return value & 1; 879 } 880 881 static unsigned int adv7612_read_cable_det(struct v4l2_subdev *sd) 882 { 883 /* Reads CABLE_DET_A_RAW. For input B support, need to 884 * account for bit 7 [MSB] of 0x6a (ie. CABLE_DET_B_RAW) 885 */ 886 u8 value = io_read(sd, 0x6f); 887 888 return value & 1; 889 } 890 891 static int adv76xx_s_detect_tx_5v_ctrl(struct v4l2_subdev *sd) 892 { 893 struct adv76xx_state *state = to_state(sd); 894 const struct adv76xx_chip_info *info = state->info; 895 896 return v4l2_ctrl_s_ctrl(state->detect_tx_5v_ctrl, 897 info->read_cable_det(sd)); 898 } 899 900 static int find_and_set_predefined_video_timings(struct v4l2_subdev *sd, 901 u8 prim_mode, 902 const struct adv76xx_video_standards *predef_vid_timings, 903 const struct v4l2_dv_timings *timings) 904 { 905 int i; 906 907 for (i = 0; predef_vid_timings[i].timings.bt.width; i++) { 908 if (!v4l2_match_dv_timings(timings, &predef_vid_timings[i].timings, 909 is_digital_input(sd) ? 250000 : 1000000, false)) 910 continue; 911 io_write(sd, 0x00, predef_vid_timings[i].vid_std); /* video std */ 912 io_write(sd, 0x01, (predef_vid_timings[i].v_freq << 4) + 913 prim_mode); /* v_freq and prim mode */ 914 return 0; 915 } 916 917 return -1; 918 } 919 920 static int configure_predefined_video_timings(struct v4l2_subdev *sd, 921 struct v4l2_dv_timings *timings) 922 { 923 struct adv76xx_state *state = to_state(sd); 924 int err; 925 926 v4l2_dbg(1, debug, sd, "%s", __func__); 927 928 if (adv76xx_has_afe(state)) { 929 /* reset to default values */ 930 io_write(sd, 0x16, 0x43); 931 io_write(sd, 0x17, 0x5a); 932 } 933 /* disable embedded syncs for auto graphics mode */ 934 cp_write_clr_set(sd, 0x81, 0x10, 0x00); 935 cp_write(sd, 0x8f, 0x00); 936 cp_write(sd, 0x90, 0x00); 937 cp_write(sd, 0xa2, 0x00); 938 cp_write(sd, 0xa3, 0x00); 939 cp_write(sd, 0xa4, 0x00); 940 cp_write(sd, 0xa5, 0x00); 941 cp_write(sd, 0xa6, 0x00); 942 cp_write(sd, 0xa7, 0x00); 943 cp_write(sd, 0xab, 0x00); 944 cp_write(sd, 0xac, 0x00); 945 946 if (is_analog_input(sd)) { 947 err = find_and_set_predefined_video_timings(sd, 948 0x01, adv7604_prim_mode_comp, timings); 949 if (err) 950 err = find_and_set_predefined_video_timings(sd, 951 0x02, adv7604_prim_mode_gr, timings); 952 } else if (is_digital_input(sd)) { 953 err = find_and_set_predefined_video_timings(sd, 954 0x05, adv76xx_prim_mode_hdmi_comp, timings); 955 if (err) 956 err = find_and_set_predefined_video_timings(sd, 957 0x06, adv76xx_prim_mode_hdmi_gr, timings); 958 } else { 959 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n", 960 __func__, state->selected_input); 961 err = -1; 962 } 963 964 965 return err; 966 } 967 968 static void configure_custom_video_timings(struct v4l2_subdev *sd, 969 const struct v4l2_bt_timings *bt) 970 { 971 struct adv76xx_state *state = to_state(sd); 972 u32 width = htotal(bt); 973 u32 height = vtotal(bt); 974 u16 cp_start_sav = bt->hsync + bt->hbackporch - 4; 975 u16 cp_start_eav = width - bt->hfrontporch; 976 u16 cp_start_vbi = height - bt->vfrontporch; 977 u16 cp_end_vbi = bt->vsync + bt->vbackporch; 978 u16 ch1_fr_ll = (((u32)bt->pixelclock / 100) > 0) ? 979 ((width * (ADV76XX_FSC / 100)) / ((u32)bt->pixelclock / 100)) : 0; 980 const u8 pll[2] = { 981 0xc0 | ((width >> 8) & 0x1f), 982 width & 0xff 983 }; 984 985 v4l2_dbg(2, debug, sd, "%s\n", __func__); 986 987 if (is_analog_input(sd)) { 988 /* auto graphics */ 989 io_write(sd, 0x00, 0x07); /* video std */ 990 io_write(sd, 0x01, 0x02); /* prim mode */ 991 /* enable embedded syncs for auto graphics mode */ 992 cp_write_clr_set(sd, 0x81, 0x10, 0x10); 993 994 /* Should only be set in auto-graphics mode [REF_02, p. 91-92] */ 995 /* setup PLL_DIV_MAN_EN and PLL_DIV_RATIO */ 996 /* IO-map reg. 0x16 and 0x17 should be written in sequence */ 997 if (regmap_raw_write(state->regmap[ADV76XX_PAGE_IO], 998 0x16, pll, 2)) 999 v4l2_err(sd, "writing to reg 0x16 and 0x17 failed\n"); 1000 1001 /* active video - horizontal timing */ 1002 cp_write(sd, 0xa2, (cp_start_sav >> 4) & 0xff); 1003 cp_write(sd, 0xa3, ((cp_start_sav & 0x0f) << 4) | 1004 ((cp_start_eav >> 8) & 0x0f)); 1005 cp_write(sd, 0xa4, cp_start_eav & 0xff); 1006 1007 /* active video - vertical timing */ 1008 cp_write(sd, 0xa5, (cp_start_vbi >> 4) & 0xff); 1009 cp_write(sd, 0xa6, ((cp_start_vbi & 0xf) << 4) | 1010 ((cp_end_vbi >> 8) & 0xf)); 1011 cp_write(sd, 0xa7, cp_end_vbi & 0xff); 1012 } else if (is_digital_input(sd)) { 1013 /* set default prim_mode/vid_std for HDMI 1014 according to [REF_03, c. 4.2] */ 1015 io_write(sd, 0x00, 0x02); /* video std */ 1016 io_write(sd, 0x01, 0x06); /* prim mode */ 1017 } else { 1018 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n", 1019 __func__, state->selected_input); 1020 } 1021 1022 cp_write(sd, 0x8f, (ch1_fr_ll >> 8) & 0x7); 1023 cp_write(sd, 0x90, ch1_fr_ll & 0xff); 1024 cp_write(sd, 0xab, (height >> 4) & 0xff); 1025 cp_write(sd, 0xac, (height & 0x0f) << 4); 1026 } 1027 1028 static void adv76xx_set_offset(struct v4l2_subdev *sd, bool auto_offset, u16 offset_a, u16 offset_b, u16 offset_c) 1029 { 1030 struct adv76xx_state *state = to_state(sd); 1031 u8 offset_buf[4]; 1032 1033 if (auto_offset) { 1034 offset_a = 0x3ff; 1035 offset_b = 0x3ff; 1036 offset_c = 0x3ff; 1037 } 1038 1039 v4l2_dbg(2, debug, sd, "%s: %s offset: a = 0x%x, b = 0x%x, c = 0x%x\n", 1040 __func__, auto_offset ? "Auto" : "Manual", 1041 offset_a, offset_b, offset_c); 1042 1043 offset_buf[0] = (cp_read(sd, 0x77) & 0xc0) | ((offset_a & 0x3f0) >> 4); 1044 offset_buf[1] = ((offset_a & 0x00f) << 4) | ((offset_b & 0x3c0) >> 6); 1045 offset_buf[2] = ((offset_b & 0x03f) << 2) | ((offset_c & 0x300) >> 8); 1046 offset_buf[3] = offset_c & 0x0ff; 1047 1048 /* Registers must be written in this order with no i2c access in between */ 1049 if (regmap_raw_write(state->regmap[ADV76XX_PAGE_CP], 1050 0x77, offset_buf, 4)) 1051 v4l2_err(sd, "%s: i2c error writing to CP reg 0x77, 0x78, 0x79, 0x7a\n", __func__); 1052 } 1053 1054 static void adv76xx_set_gain(struct v4l2_subdev *sd, bool auto_gain, u16 gain_a, u16 gain_b, u16 gain_c) 1055 { 1056 struct adv76xx_state *state = to_state(sd); 1057 u8 gain_buf[4]; 1058 u8 gain_man = 1; 1059 u8 agc_mode_man = 1; 1060 1061 if (auto_gain) { 1062 gain_man = 0; 1063 agc_mode_man = 0; 1064 gain_a = 0x100; 1065 gain_b = 0x100; 1066 gain_c = 0x100; 1067 } 1068 1069 v4l2_dbg(2, debug, sd, "%s: %s gain: a = 0x%x, b = 0x%x, c = 0x%x\n", 1070 __func__, auto_gain ? "Auto" : "Manual", 1071 gain_a, gain_b, gain_c); 1072 1073 gain_buf[0] = ((gain_man << 7) | (agc_mode_man << 6) | ((gain_a & 0x3f0) >> 4)); 1074 gain_buf[1] = (((gain_a & 0x00f) << 4) | ((gain_b & 0x3c0) >> 6)); 1075 gain_buf[2] = (((gain_b & 0x03f) << 2) | ((gain_c & 0x300) >> 8)); 1076 gain_buf[3] = ((gain_c & 0x0ff)); 1077 1078 /* Registers must be written in this order with no i2c access in between */ 1079 if (regmap_raw_write(state->regmap[ADV76XX_PAGE_CP], 1080 0x73, gain_buf, 4)) 1081 v4l2_err(sd, "%s: i2c error writing to CP reg 0x73, 0x74, 0x75, 0x76\n", __func__); 1082 } 1083 1084 static void set_rgb_quantization_range(struct v4l2_subdev *sd) 1085 { 1086 struct adv76xx_state *state = to_state(sd); 1087 bool rgb_output = io_read(sd, 0x02) & 0x02; 1088 bool hdmi_signal = hdmi_read(sd, 0x05) & 0x80; 1089 1090 v4l2_dbg(2, debug, sd, "%s: RGB quantization range: %d, RGB out: %d, HDMI: %d\n", 1091 __func__, state->rgb_quantization_range, 1092 rgb_output, hdmi_signal); 1093 1094 adv76xx_set_gain(sd, true, 0x0, 0x0, 0x0); 1095 adv76xx_set_offset(sd, true, 0x0, 0x0, 0x0); 1096 1097 switch (state->rgb_quantization_range) { 1098 case V4L2_DV_RGB_RANGE_AUTO: 1099 if (state->selected_input == ADV7604_PAD_VGA_RGB) { 1100 /* Receiving analog RGB signal 1101 * Set RGB full range (0-255) */ 1102 io_write_clr_set(sd, 0x02, 0xf0, 0x10); 1103 break; 1104 } 1105 1106 if (state->selected_input == ADV7604_PAD_VGA_COMP) { 1107 /* Receiving analog YPbPr signal 1108 * Set automode */ 1109 io_write_clr_set(sd, 0x02, 0xf0, 0xf0); 1110 break; 1111 } 1112 1113 if (hdmi_signal) { 1114 /* Receiving HDMI signal 1115 * Set automode */ 1116 io_write_clr_set(sd, 0x02, 0xf0, 0xf0); 1117 break; 1118 } 1119 1120 /* Receiving DVI-D signal 1121 * ADV7604 selects RGB limited range regardless of 1122 * input format (CE/IT) in automatic mode */ 1123 if (state->timings.bt.flags & V4L2_DV_FL_IS_CE_VIDEO) { 1124 /* RGB limited range (16-235) */ 1125 io_write_clr_set(sd, 0x02, 0xf0, 0x00); 1126 } else { 1127 /* RGB full range (0-255) */ 1128 io_write_clr_set(sd, 0x02, 0xf0, 0x10); 1129 1130 if (is_digital_input(sd) && rgb_output) { 1131 adv76xx_set_offset(sd, false, 0x40, 0x40, 0x40); 1132 } else { 1133 adv76xx_set_gain(sd, false, 0xe0, 0xe0, 0xe0); 1134 adv76xx_set_offset(sd, false, 0x70, 0x70, 0x70); 1135 } 1136 } 1137 break; 1138 case V4L2_DV_RGB_RANGE_LIMITED: 1139 if (state->selected_input == ADV7604_PAD_VGA_COMP) { 1140 /* YCrCb limited range (16-235) */ 1141 io_write_clr_set(sd, 0x02, 0xf0, 0x20); 1142 break; 1143 } 1144 1145 /* RGB limited range (16-235) */ 1146 io_write_clr_set(sd, 0x02, 0xf0, 0x00); 1147 1148 break; 1149 case V4L2_DV_RGB_RANGE_FULL: 1150 if (state->selected_input == ADV7604_PAD_VGA_COMP) { 1151 /* YCrCb full range (0-255) */ 1152 io_write_clr_set(sd, 0x02, 0xf0, 0x60); 1153 break; 1154 } 1155 1156 /* RGB full range (0-255) */ 1157 io_write_clr_set(sd, 0x02, 0xf0, 0x10); 1158 1159 if (is_analog_input(sd) || hdmi_signal) 1160 break; 1161 1162 /* Adjust gain/offset for DVI-D signals only */ 1163 if (rgb_output) { 1164 adv76xx_set_offset(sd, false, 0x40, 0x40, 0x40); 1165 } else { 1166 adv76xx_set_gain(sd, false, 0xe0, 0xe0, 0xe0); 1167 adv76xx_set_offset(sd, false, 0x70, 0x70, 0x70); 1168 } 1169 break; 1170 } 1171 } 1172 1173 static int adv76xx_s_ctrl(struct v4l2_ctrl *ctrl) 1174 { 1175 struct v4l2_subdev *sd = 1176 &container_of(ctrl->handler, struct adv76xx_state, hdl)->sd; 1177 1178 struct adv76xx_state *state = to_state(sd); 1179 1180 switch (ctrl->id) { 1181 case V4L2_CID_BRIGHTNESS: 1182 cp_write(sd, 0x3c, ctrl->val); 1183 return 0; 1184 case V4L2_CID_CONTRAST: 1185 cp_write(sd, 0x3a, ctrl->val); 1186 return 0; 1187 case V4L2_CID_SATURATION: 1188 cp_write(sd, 0x3b, ctrl->val); 1189 return 0; 1190 case V4L2_CID_HUE: 1191 cp_write(sd, 0x3d, ctrl->val); 1192 return 0; 1193 case V4L2_CID_DV_RX_RGB_RANGE: 1194 state->rgb_quantization_range = ctrl->val; 1195 set_rgb_quantization_range(sd); 1196 return 0; 1197 case V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE: 1198 if (!adv76xx_has_afe(state)) 1199 return -EINVAL; 1200 /* Set the analog sampling phase. This is needed to find the 1201 best sampling phase for analog video: an application or 1202 driver has to try a number of phases and analyze the picture 1203 quality before settling on the best performing phase. */ 1204 afe_write(sd, 0xc8, ctrl->val); 1205 return 0; 1206 case V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL: 1207 /* Use the default blue color for free running mode, 1208 or supply your own. */ 1209 cp_write_clr_set(sd, 0xbf, 0x04, ctrl->val << 2); 1210 return 0; 1211 case V4L2_CID_ADV_RX_FREE_RUN_COLOR: 1212 cp_write(sd, 0xc0, (ctrl->val & 0xff0000) >> 16); 1213 cp_write(sd, 0xc1, (ctrl->val & 0x00ff00) >> 8); 1214 cp_write(sd, 0xc2, (u8)(ctrl->val & 0x0000ff)); 1215 return 0; 1216 } 1217 return -EINVAL; 1218 } 1219 1220 static int adv76xx_g_volatile_ctrl(struct v4l2_ctrl *ctrl) 1221 { 1222 struct v4l2_subdev *sd = 1223 &container_of(ctrl->handler, struct adv76xx_state, hdl)->sd; 1224 1225 if (ctrl->id == V4L2_CID_DV_RX_IT_CONTENT_TYPE) { 1226 ctrl->val = V4L2_DV_IT_CONTENT_TYPE_NO_ITC; 1227 if ((io_read(sd, 0x60) & 1) && (infoframe_read(sd, 0x03) & 0x80)) 1228 ctrl->val = (infoframe_read(sd, 0x05) >> 4) & 3; 1229 return 0; 1230 } 1231 return -EINVAL; 1232 } 1233 1234 /* ----------------------------------------------------------------------- */ 1235 1236 static inline bool no_power(struct v4l2_subdev *sd) 1237 { 1238 /* Entire chip or CP powered off */ 1239 return io_read(sd, 0x0c) & 0x24; 1240 } 1241 1242 static inline bool no_signal_tmds(struct v4l2_subdev *sd) 1243 { 1244 struct adv76xx_state *state = to_state(sd); 1245 1246 return !(io_read(sd, 0x6a) & (0x10 >> state->selected_input)); 1247 } 1248 1249 static inline bool no_lock_tmds(struct v4l2_subdev *sd) 1250 { 1251 struct adv76xx_state *state = to_state(sd); 1252 const struct adv76xx_chip_info *info = state->info; 1253 1254 return (io_read(sd, 0x6a) & info->tdms_lock_mask) != info->tdms_lock_mask; 1255 } 1256 1257 static inline bool is_hdmi(struct v4l2_subdev *sd) 1258 { 1259 return hdmi_read(sd, 0x05) & 0x80; 1260 } 1261 1262 static inline bool no_lock_sspd(struct v4l2_subdev *sd) 1263 { 1264 struct adv76xx_state *state = to_state(sd); 1265 1266 /* 1267 * Chips without a AFE don't expose registers for the SSPD, so just assume 1268 * that we have a lock. 1269 */ 1270 if (adv76xx_has_afe(state)) 1271 return false; 1272 1273 /* TODO channel 2 */ 1274 return ((cp_read(sd, 0xb5) & 0xd0) != 0xd0); 1275 } 1276 1277 static inline bool no_lock_stdi(struct v4l2_subdev *sd) 1278 { 1279 /* TODO channel 2 */ 1280 return !(cp_read(sd, 0xb1) & 0x80); 1281 } 1282 1283 static inline bool no_signal(struct v4l2_subdev *sd) 1284 { 1285 bool ret; 1286 1287 ret = no_power(sd); 1288 1289 ret |= no_lock_stdi(sd); 1290 ret |= no_lock_sspd(sd); 1291 1292 if (is_digital_input(sd)) { 1293 ret |= no_lock_tmds(sd); 1294 ret |= no_signal_tmds(sd); 1295 } 1296 1297 return ret; 1298 } 1299 1300 static inline bool no_lock_cp(struct v4l2_subdev *sd) 1301 { 1302 struct adv76xx_state *state = to_state(sd); 1303 1304 if (!adv76xx_has_afe(state)) 1305 return false; 1306 1307 /* CP has detected a non standard number of lines on the incoming 1308 video compared to what it is configured to receive by s_dv_timings */ 1309 return io_read(sd, 0x12) & 0x01; 1310 } 1311 1312 static inline bool in_free_run(struct v4l2_subdev *sd) 1313 { 1314 return cp_read(sd, 0xff) & 0x10; 1315 } 1316 1317 static int adv76xx_g_input_status(struct v4l2_subdev *sd, u32 *status) 1318 { 1319 *status = 0; 1320 *status |= no_power(sd) ? V4L2_IN_ST_NO_POWER : 0; 1321 *status |= no_signal(sd) ? V4L2_IN_ST_NO_SIGNAL : 0; 1322 if (!in_free_run(sd) && no_lock_cp(sd)) 1323 *status |= is_digital_input(sd) ? 1324 V4L2_IN_ST_NO_SYNC : V4L2_IN_ST_NO_H_LOCK; 1325 1326 v4l2_dbg(1, debug, sd, "%s: status = 0x%x\n", __func__, *status); 1327 1328 return 0; 1329 } 1330 1331 /* ----------------------------------------------------------------------- */ 1332 1333 struct stdi_readback { 1334 u16 bl, lcf, lcvs; 1335 u8 hs_pol, vs_pol; 1336 bool interlaced; 1337 }; 1338 1339 static int stdi2dv_timings(struct v4l2_subdev *sd, 1340 struct stdi_readback *stdi, 1341 struct v4l2_dv_timings *timings) 1342 { 1343 struct adv76xx_state *state = to_state(sd); 1344 u32 hfreq = (ADV76XX_FSC * 8) / stdi->bl; 1345 u32 pix_clk; 1346 int i; 1347 1348 for (i = 0; v4l2_dv_timings_presets[i].bt.width; i++) { 1349 const struct v4l2_bt_timings *bt = &v4l2_dv_timings_presets[i].bt; 1350 1351 if (!v4l2_valid_dv_timings(&v4l2_dv_timings_presets[i], 1352 adv76xx_get_dv_timings_cap(sd, -1), 1353 adv76xx_check_dv_timings, NULL)) 1354 continue; 1355 if (vtotal(bt) != stdi->lcf + 1) 1356 continue; 1357 if (bt->vsync != stdi->lcvs) 1358 continue; 1359 1360 pix_clk = hfreq * htotal(bt); 1361 1362 if ((pix_clk < bt->pixelclock + 1000000) && 1363 (pix_clk > bt->pixelclock - 1000000)) { 1364 *timings = v4l2_dv_timings_presets[i]; 1365 return 0; 1366 } 1367 } 1368 1369 if (v4l2_detect_cvt(stdi->lcf + 1, hfreq, stdi->lcvs, 0, 1370 (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) | 1371 (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0), 1372 false, timings)) 1373 return 0; 1374 if (v4l2_detect_gtf(stdi->lcf + 1, hfreq, stdi->lcvs, 1375 (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) | 1376 (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0), 1377 false, state->aspect_ratio, timings)) 1378 return 0; 1379 1380 v4l2_dbg(2, debug, sd, 1381 "%s: No format candidate found for lcvs = %d, lcf=%d, bl = %d, %chsync, %cvsync\n", 1382 __func__, stdi->lcvs, stdi->lcf, stdi->bl, 1383 stdi->hs_pol, stdi->vs_pol); 1384 return -1; 1385 } 1386 1387 1388 static int read_stdi(struct v4l2_subdev *sd, struct stdi_readback *stdi) 1389 { 1390 struct adv76xx_state *state = to_state(sd); 1391 const struct adv76xx_chip_info *info = state->info; 1392 u8 polarity; 1393 1394 if (no_lock_stdi(sd) || no_lock_sspd(sd)) { 1395 v4l2_dbg(2, debug, sd, "%s: STDI and/or SSPD not locked\n", __func__); 1396 return -1; 1397 } 1398 1399 /* read STDI */ 1400 stdi->bl = cp_read16(sd, 0xb1, 0x3fff); 1401 stdi->lcf = cp_read16(sd, info->lcf_reg, 0x7ff); 1402 stdi->lcvs = cp_read(sd, 0xb3) >> 3; 1403 stdi->interlaced = io_read(sd, 0x12) & 0x10; 1404 1405 if (adv76xx_has_afe(state)) { 1406 /* read SSPD */ 1407 polarity = cp_read(sd, 0xb5); 1408 if ((polarity & 0x03) == 0x01) { 1409 stdi->hs_pol = polarity & 0x10 1410 ? (polarity & 0x08 ? '+' : '-') : 'x'; 1411 stdi->vs_pol = polarity & 0x40 1412 ? (polarity & 0x20 ? '+' : '-') : 'x'; 1413 } else { 1414 stdi->hs_pol = 'x'; 1415 stdi->vs_pol = 'x'; 1416 } 1417 } else { 1418 polarity = hdmi_read(sd, 0x05); 1419 stdi->hs_pol = polarity & 0x20 ? '+' : '-'; 1420 stdi->vs_pol = polarity & 0x10 ? '+' : '-'; 1421 } 1422 1423 if (no_lock_stdi(sd) || no_lock_sspd(sd)) { 1424 v4l2_dbg(2, debug, sd, 1425 "%s: signal lost during readout of STDI/SSPD\n", __func__); 1426 return -1; 1427 } 1428 1429 if (stdi->lcf < 239 || stdi->bl < 8 || stdi->bl == 0x3fff) { 1430 v4l2_dbg(2, debug, sd, "%s: invalid signal\n", __func__); 1431 memset(stdi, 0, sizeof(struct stdi_readback)); 1432 return -1; 1433 } 1434 1435 v4l2_dbg(2, debug, sd, 1436 "%s: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %chsync, %cvsync, %s\n", 1437 __func__, stdi->lcf, stdi->bl, stdi->lcvs, 1438 stdi->hs_pol, stdi->vs_pol, 1439 stdi->interlaced ? "interlaced" : "progressive"); 1440 1441 return 0; 1442 } 1443 1444 static int adv76xx_enum_dv_timings(struct v4l2_subdev *sd, 1445 struct v4l2_enum_dv_timings *timings) 1446 { 1447 struct adv76xx_state *state = to_state(sd); 1448 1449 if (timings->pad >= state->source_pad) 1450 return -EINVAL; 1451 1452 return v4l2_enum_dv_timings_cap(timings, 1453 adv76xx_get_dv_timings_cap(sd, timings->pad), 1454 adv76xx_check_dv_timings, NULL); 1455 } 1456 1457 static int adv76xx_dv_timings_cap(struct v4l2_subdev *sd, 1458 struct v4l2_dv_timings_cap *cap) 1459 { 1460 struct adv76xx_state *state = to_state(sd); 1461 unsigned int pad = cap->pad; 1462 1463 if (cap->pad >= state->source_pad) 1464 return -EINVAL; 1465 1466 *cap = *adv76xx_get_dv_timings_cap(sd, pad); 1467 cap->pad = pad; 1468 1469 return 0; 1470 } 1471 1472 /* Fill the optional fields .standards and .flags in struct v4l2_dv_timings 1473 if the format is listed in adv76xx_timings[] */ 1474 static void adv76xx_fill_optional_dv_timings_fields(struct v4l2_subdev *sd, 1475 struct v4l2_dv_timings *timings) 1476 { 1477 v4l2_find_dv_timings_cap(timings, adv76xx_get_dv_timings_cap(sd, -1), 1478 is_digital_input(sd) ? 250000 : 1000000, 1479 adv76xx_check_dv_timings, NULL); 1480 } 1481 1482 static unsigned int adv7604_read_hdmi_pixelclock(struct v4l2_subdev *sd) 1483 { 1484 unsigned int freq; 1485 int a, b; 1486 1487 a = hdmi_read(sd, 0x06); 1488 b = hdmi_read(sd, 0x3b); 1489 if (a < 0 || b < 0) 1490 return 0; 1491 freq = a * 1000000 + ((b & 0x30) >> 4) * 250000; 1492 1493 if (is_hdmi(sd)) { 1494 /* adjust for deep color mode */ 1495 unsigned bits_per_channel = ((hdmi_read(sd, 0x0b) & 0x60) >> 4) + 8; 1496 1497 freq = freq * 8 / bits_per_channel; 1498 } 1499 1500 return freq; 1501 } 1502 1503 static unsigned int adv7611_read_hdmi_pixelclock(struct v4l2_subdev *sd) 1504 { 1505 int a, b; 1506 1507 a = hdmi_read(sd, 0x51); 1508 b = hdmi_read(sd, 0x52); 1509 if (a < 0 || b < 0) 1510 return 0; 1511 return ((a << 1) | (b >> 7)) * 1000000 + (b & 0x7f) * 1000000 / 128; 1512 } 1513 1514 static int adv76xx_query_dv_timings(struct v4l2_subdev *sd, 1515 struct v4l2_dv_timings *timings) 1516 { 1517 struct adv76xx_state *state = to_state(sd); 1518 const struct adv76xx_chip_info *info = state->info; 1519 struct v4l2_bt_timings *bt = &timings->bt; 1520 struct stdi_readback stdi; 1521 1522 if (!timings) 1523 return -EINVAL; 1524 1525 memset(timings, 0, sizeof(struct v4l2_dv_timings)); 1526 1527 if (no_signal(sd)) { 1528 state->restart_stdi_once = true; 1529 v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__); 1530 return -ENOLINK; 1531 } 1532 1533 /* read STDI */ 1534 if (read_stdi(sd, &stdi)) { 1535 v4l2_dbg(1, debug, sd, "%s: STDI/SSPD not locked\n", __func__); 1536 return -ENOLINK; 1537 } 1538 bt->interlaced = stdi.interlaced ? 1539 V4L2_DV_INTERLACED : V4L2_DV_PROGRESSIVE; 1540 1541 if (is_digital_input(sd)) { 1542 timings->type = V4L2_DV_BT_656_1120; 1543 1544 bt->width = hdmi_read16(sd, 0x07, info->linewidth_mask); 1545 bt->height = hdmi_read16(sd, 0x09, info->field0_height_mask); 1546 bt->pixelclock = info->read_hdmi_pixelclock(sd); 1547 bt->hfrontporch = hdmi_read16(sd, 0x20, info->hfrontporch_mask); 1548 bt->hsync = hdmi_read16(sd, 0x22, info->hsync_mask); 1549 bt->hbackporch = hdmi_read16(sd, 0x24, info->hbackporch_mask); 1550 bt->vfrontporch = hdmi_read16(sd, 0x2a, 1551 info->field0_vfrontporch_mask) / 2; 1552 bt->vsync = hdmi_read16(sd, 0x2e, info->field0_vsync_mask) / 2; 1553 bt->vbackporch = hdmi_read16(sd, 0x32, 1554 info->field0_vbackporch_mask) / 2; 1555 bt->polarities = ((hdmi_read(sd, 0x05) & 0x10) ? V4L2_DV_VSYNC_POS_POL : 0) | 1556 ((hdmi_read(sd, 0x05) & 0x20) ? V4L2_DV_HSYNC_POS_POL : 0); 1557 if (bt->interlaced == V4L2_DV_INTERLACED) { 1558 bt->height += hdmi_read16(sd, 0x0b, 1559 info->field1_height_mask); 1560 bt->il_vfrontporch = hdmi_read16(sd, 0x2c, 1561 info->field1_vfrontporch_mask) / 2; 1562 bt->il_vsync = hdmi_read16(sd, 0x30, 1563 info->field1_vsync_mask) / 2; 1564 bt->il_vbackporch = hdmi_read16(sd, 0x34, 1565 info->field1_vbackporch_mask) / 2; 1566 } 1567 adv76xx_fill_optional_dv_timings_fields(sd, timings); 1568 } else { 1569 /* find format 1570 * Since LCVS values are inaccurate [REF_03, p. 275-276], 1571 * stdi2dv_timings() is called with lcvs +-1 if the first attempt fails. 1572 */ 1573 if (!stdi2dv_timings(sd, &stdi, timings)) 1574 goto found; 1575 stdi.lcvs += 1; 1576 v4l2_dbg(1, debug, sd, "%s: lcvs + 1 = %d\n", __func__, stdi.lcvs); 1577 if (!stdi2dv_timings(sd, &stdi, timings)) 1578 goto found; 1579 stdi.lcvs -= 2; 1580 v4l2_dbg(1, debug, sd, "%s: lcvs - 1 = %d\n", __func__, stdi.lcvs); 1581 if (stdi2dv_timings(sd, &stdi, timings)) { 1582 /* 1583 * The STDI block may measure wrong values, especially 1584 * for lcvs and lcf. If the driver can not find any 1585 * valid timing, the STDI block is restarted to measure 1586 * the video timings again. The function will return an 1587 * error, but the restart of STDI will generate a new 1588 * STDI interrupt and the format detection process will 1589 * restart. 1590 */ 1591 if (state->restart_stdi_once) { 1592 v4l2_dbg(1, debug, sd, "%s: restart STDI\n", __func__); 1593 /* TODO restart STDI for Sync Channel 2 */ 1594 /* enter one-shot mode */ 1595 cp_write_clr_set(sd, 0x86, 0x06, 0x00); 1596 /* trigger STDI restart */ 1597 cp_write_clr_set(sd, 0x86, 0x06, 0x04); 1598 /* reset to continuous mode */ 1599 cp_write_clr_set(sd, 0x86, 0x06, 0x02); 1600 state->restart_stdi_once = false; 1601 return -ENOLINK; 1602 } 1603 v4l2_dbg(1, debug, sd, "%s: format not supported\n", __func__); 1604 return -ERANGE; 1605 } 1606 state->restart_stdi_once = true; 1607 } 1608 found: 1609 1610 if (no_signal(sd)) { 1611 v4l2_dbg(1, debug, sd, "%s: signal lost during readout\n", __func__); 1612 memset(timings, 0, sizeof(struct v4l2_dv_timings)); 1613 return -ENOLINK; 1614 } 1615 1616 if ((is_analog_input(sd) && bt->pixelclock > 170000000) || 1617 (is_digital_input(sd) && bt->pixelclock > 225000000)) { 1618 v4l2_dbg(1, debug, sd, "%s: pixelclock out of range %d\n", 1619 __func__, (u32)bt->pixelclock); 1620 return -ERANGE; 1621 } 1622 1623 if (debug > 1) 1624 v4l2_print_dv_timings(sd->name, "adv76xx_query_dv_timings: ", 1625 timings, true); 1626 1627 return 0; 1628 } 1629 1630 static int adv76xx_s_dv_timings(struct v4l2_subdev *sd, 1631 struct v4l2_dv_timings *timings) 1632 { 1633 struct adv76xx_state *state = to_state(sd); 1634 struct v4l2_bt_timings *bt; 1635 int err; 1636 1637 if (!timings) 1638 return -EINVAL; 1639 1640 if (v4l2_match_dv_timings(&state->timings, timings, 0, false)) { 1641 v4l2_dbg(1, debug, sd, "%s: no change\n", __func__); 1642 return 0; 1643 } 1644 1645 bt = &timings->bt; 1646 1647 if (!v4l2_valid_dv_timings(timings, adv76xx_get_dv_timings_cap(sd, -1), 1648 adv76xx_check_dv_timings, NULL)) 1649 return -ERANGE; 1650 1651 adv76xx_fill_optional_dv_timings_fields(sd, timings); 1652 1653 state->timings = *timings; 1654 1655 cp_write_clr_set(sd, 0x91, 0x40, bt->interlaced ? 0x40 : 0x00); 1656 1657 /* Use prim_mode and vid_std when available */ 1658 err = configure_predefined_video_timings(sd, timings); 1659 if (err) { 1660 /* custom settings when the video format 1661 does not have prim_mode/vid_std */ 1662 configure_custom_video_timings(sd, bt); 1663 } 1664 1665 set_rgb_quantization_range(sd); 1666 1667 if (debug > 1) 1668 v4l2_print_dv_timings(sd->name, "adv76xx_s_dv_timings: ", 1669 timings, true); 1670 return 0; 1671 } 1672 1673 static int adv76xx_g_dv_timings(struct v4l2_subdev *sd, 1674 struct v4l2_dv_timings *timings) 1675 { 1676 struct adv76xx_state *state = to_state(sd); 1677 1678 *timings = state->timings; 1679 return 0; 1680 } 1681 1682 static void adv7604_set_termination(struct v4l2_subdev *sd, bool enable) 1683 { 1684 hdmi_write(sd, 0x01, enable ? 0x00 : 0x78); 1685 } 1686 1687 static void adv7611_set_termination(struct v4l2_subdev *sd, bool enable) 1688 { 1689 hdmi_write(sd, 0x83, enable ? 0xfe : 0xff); 1690 } 1691 1692 static void enable_input(struct v4l2_subdev *sd) 1693 { 1694 struct adv76xx_state *state = to_state(sd); 1695 1696 if (is_analog_input(sd)) { 1697 io_write(sd, 0x15, 0xb0); /* Disable Tristate of Pins (no audio) */ 1698 } else if (is_digital_input(sd)) { 1699 hdmi_write_clr_set(sd, 0x00, 0x03, state->selected_input); 1700 state->info->set_termination(sd, true); 1701 io_write(sd, 0x15, 0xa0); /* Disable Tristate of Pins */ 1702 hdmi_write_clr_set(sd, 0x1a, 0x10, 0x00); /* Unmute audio */ 1703 } else { 1704 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n", 1705 __func__, state->selected_input); 1706 } 1707 } 1708 1709 static void disable_input(struct v4l2_subdev *sd) 1710 { 1711 struct adv76xx_state *state = to_state(sd); 1712 1713 hdmi_write_clr_set(sd, 0x1a, 0x10, 0x10); /* Mute audio */ 1714 msleep(16); /* 512 samples with >= 32 kHz sample rate [REF_03, c. 7.16.10] */ 1715 io_write(sd, 0x15, 0xbe); /* Tristate all outputs from video core */ 1716 state->info->set_termination(sd, false); 1717 } 1718 1719 static void select_input(struct v4l2_subdev *sd) 1720 { 1721 struct adv76xx_state *state = to_state(sd); 1722 const struct adv76xx_chip_info *info = state->info; 1723 1724 if (is_analog_input(sd)) { 1725 adv76xx_write_reg_seq(sd, info->recommended_settings[0]); 1726 1727 afe_write(sd, 0x00, 0x08); /* power up ADC */ 1728 afe_write(sd, 0x01, 0x06); /* power up Analog Front End */ 1729 afe_write(sd, 0xc8, 0x00); /* phase control */ 1730 } else if (is_digital_input(sd)) { 1731 hdmi_write(sd, 0x00, state->selected_input & 0x03); 1732 1733 adv76xx_write_reg_seq(sd, info->recommended_settings[1]); 1734 1735 if (adv76xx_has_afe(state)) { 1736 afe_write(sd, 0x00, 0xff); /* power down ADC */ 1737 afe_write(sd, 0x01, 0xfe); /* power down Analog Front End */ 1738 afe_write(sd, 0xc8, 0x40); /* phase control */ 1739 } 1740 1741 cp_write(sd, 0x3e, 0x00); /* CP core pre-gain control */ 1742 cp_write(sd, 0xc3, 0x39); /* CP coast control. Graphics mode */ 1743 cp_write(sd, 0x40, 0x80); /* CP core pre-gain control. Graphics mode */ 1744 } else { 1745 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n", 1746 __func__, state->selected_input); 1747 } 1748 } 1749 1750 static int adv76xx_s_routing(struct v4l2_subdev *sd, 1751 u32 input, u32 output, u32 config) 1752 { 1753 struct adv76xx_state *state = to_state(sd); 1754 1755 v4l2_dbg(2, debug, sd, "%s: input %d, selected input %d", 1756 __func__, input, state->selected_input); 1757 1758 if (input == state->selected_input) 1759 return 0; 1760 1761 if (input > state->info->max_port) 1762 return -EINVAL; 1763 1764 state->selected_input = input; 1765 1766 disable_input(sd); 1767 select_input(sd); 1768 enable_input(sd); 1769 1770 v4l2_subdev_notify_event(sd, &adv76xx_ev_fmt); 1771 1772 return 0; 1773 } 1774 1775 static int adv76xx_enum_mbus_code(struct v4l2_subdev *sd, 1776 struct v4l2_subdev_pad_config *cfg, 1777 struct v4l2_subdev_mbus_code_enum *code) 1778 { 1779 struct adv76xx_state *state = to_state(sd); 1780 1781 if (code->index >= state->info->nformats) 1782 return -EINVAL; 1783 1784 code->code = state->info->formats[code->index].code; 1785 1786 return 0; 1787 } 1788 1789 static void adv76xx_fill_format(struct adv76xx_state *state, 1790 struct v4l2_mbus_framefmt *format) 1791 { 1792 memset(format, 0, sizeof(*format)); 1793 1794 format->width = state->timings.bt.width; 1795 format->height = state->timings.bt.height; 1796 format->field = V4L2_FIELD_NONE; 1797 format->colorspace = V4L2_COLORSPACE_SRGB; 1798 1799 if (state->timings.bt.flags & V4L2_DV_FL_IS_CE_VIDEO) 1800 format->colorspace = (state->timings.bt.height <= 576) ? 1801 V4L2_COLORSPACE_SMPTE170M : V4L2_COLORSPACE_REC709; 1802 } 1803 1804 /* 1805 * Compute the op_ch_sel value required to obtain on the bus the component order 1806 * corresponding to the selected format taking into account bus reordering 1807 * applied by the board at the output of the device. 1808 * 1809 * The following table gives the op_ch_value from the format component order 1810 * (expressed as op_ch_sel value in column) and the bus reordering (expressed as 1811 * adv76xx_bus_order value in row). 1812 * 1813 * | GBR(0) GRB(1) BGR(2) RGB(3) BRG(4) RBG(5) 1814 * ----------+------------------------------------------------- 1815 * RGB (NOP) | GBR GRB BGR RGB BRG RBG 1816 * GRB (1-2) | BGR RGB GBR GRB RBG BRG 1817 * RBG (2-3) | GRB GBR BRG RBG BGR RGB 1818 * BGR (1-3) | RBG BRG RGB BGR GRB GBR 1819 * BRG (ROR) | BRG RBG GRB GBR RGB BGR 1820 * GBR (ROL) | RGB BGR RBG BRG GBR GRB 1821 */ 1822 static unsigned int adv76xx_op_ch_sel(struct adv76xx_state *state) 1823 { 1824 #define _SEL(a,b,c,d,e,f) { \ 1825 ADV76XX_OP_CH_SEL_##a, ADV76XX_OP_CH_SEL_##b, ADV76XX_OP_CH_SEL_##c, \ 1826 ADV76XX_OP_CH_SEL_##d, ADV76XX_OP_CH_SEL_##e, ADV76XX_OP_CH_SEL_##f } 1827 #define _BUS(x) [ADV7604_BUS_ORDER_##x] 1828 1829 static const unsigned int op_ch_sel[6][6] = { 1830 _BUS(RGB) /* NOP */ = _SEL(GBR, GRB, BGR, RGB, BRG, RBG), 1831 _BUS(GRB) /* 1-2 */ = _SEL(BGR, RGB, GBR, GRB, RBG, BRG), 1832 _BUS(RBG) /* 2-3 */ = _SEL(GRB, GBR, BRG, RBG, BGR, RGB), 1833 _BUS(BGR) /* 1-3 */ = _SEL(RBG, BRG, RGB, BGR, GRB, GBR), 1834 _BUS(BRG) /* ROR */ = _SEL(BRG, RBG, GRB, GBR, RGB, BGR), 1835 _BUS(GBR) /* ROL */ = _SEL(RGB, BGR, RBG, BRG, GBR, GRB), 1836 }; 1837 1838 return op_ch_sel[state->pdata.bus_order][state->format->op_ch_sel >> 5]; 1839 } 1840 1841 static void adv76xx_setup_format(struct adv76xx_state *state) 1842 { 1843 struct v4l2_subdev *sd = &state->sd; 1844 1845 io_write_clr_set(sd, 0x02, 0x02, 1846 state->format->rgb_out ? ADV76XX_RGB_OUT : 0); 1847 io_write(sd, 0x03, state->format->op_format_sel | 1848 state->pdata.op_format_mode_sel); 1849 io_write_clr_set(sd, 0x04, 0xe0, adv76xx_op_ch_sel(state)); 1850 io_write_clr_set(sd, 0x05, 0x01, 1851 state->format->swap_cb_cr ? ADV76XX_OP_SWAP_CB_CR : 0); 1852 } 1853 1854 static int adv76xx_get_format(struct v4l2_subdev *sd, 1855 struct v4l2_subdev_pad_config *cfg, 1856 struct v4l2_subdev_format *format) 1857 { 1858 struct adv76xx_state *state = to_state(sd); 1859 1860 if (format->pad != state->source_pad) 1861 return -EINVAL; 1862 1863 adv76xx_fill_format(state, &format->format); 1864 1865 if (format->which == V4L2_SUBDEV_FORMAT_TRY) { 1866 struct v4l2_mbus_framefmt *fmt; 1867 1868 fmt = v4l2_subdev_get_try_format(sd, cfg, format->pad); 1869 format->format.code = fmt->code; 1870 } else { 1871 format->format.code = state->format->code; 1872 } 1873 1874 return 0; 1875 } 1876 1877 static int adv76xx_get_selection(struct v4l2_subdev *sd, 1878 struct v4l2_subdev_pad_config *cfg, 1879 struct v4l2_subdev_selection *sel) 1880 { 1881 struct adv76xx_state *state = to_state(sd); 1882 1883 if (sel->which != V4L2_SUBDEV_FORMAT_ACTIVE) 1884 return -EINVAL; 1885 /* Only CROP, CROP_DEFAULT and CROP_BOUNDS are supported */ 1886 if (sel->target > V4L2_SEL_TGT_CROP_BOUNDS) 1887 return -EINVAL; 1888 1889 sel->r.left = 0; 1890 sel->r.top = 0; 1891 sel->r.width = state->timings.bt.width; 1892 sel->r.height = state->timings.bt.height; 1893 1894 return 0; 1895 } 1896 1897 static int adv76xx_set_format(struct v4l2_subdev *sd, 1898 struct v4l2_subdev_pad_config *cfg, 1899 struct v4l2_subdev_format *format) 1900 { 1901 struct adv76xx_state *state = to_state(sd); 1902 const struct adv76xx_format_info *info; 1903 1904 if (format->pad != state->source_pad) 1905 return -EINVAL; 1906 1907 info = adv76xx_format_info(state, format->format.code); 1908 if (info == NULL) 1909 info = adv76xx_format_info(state, MEDIA_BUS_FMT_YUYV8_2X8); 1910 1911 adv76xx_fill_format(state, &format->format); 1912 format->format.code = info->code; 1913 1914 if (format->which == V4L2_SUBDEV_FORMAT_TRY) { 1915 struct v4l2_mbus_framefmt *fmt; 1916 1917 fmt = v4l2_subdev_get_try_format(sd, cfg, format->pad); 1918 fmt->code = format->format.code; 1919 } else { 1920 state->format = info; 1921 adv76xx_setup_format(state); 1922 } 1923 1924 return 0; 1925 } 1926 1927 static int adv76xx_isr(struct v4l2_subdev *sd, u32 status, bool *handled) 1928 { 1929 struct adv76xx_state *state = to_state(sd); 1930 const struct adv76xx_chip_info *info = state->info; 1931 const u8 irq_reg_0x43 = io_read(sd, 0x43); 1932 const u8 irq_reg_0x6b = io_read(sd, 0x6b); 1933 const u8 irq_reg_0x70 = io_read(sd, 0x70); 1934 u8 fmt_change_digital; 1935 u8 fmt_change; 1936 u8 tx_5v; 1937 1938 if (irq_reg_0x43) 1939 io_write(sd, 0x44, irq_reg_0x43); 1940 if (irq_reg_0x70) 1941 io_write(sd, 0x71, irq_reg_0x70); 1942 if (irq_reg_0x6b) 1943 io_write(sd, 0x6c, irq_reg_0x6b); 1944 1945 v4l2_dbg(2, debug, sd, "%s: ", __func__); 1946 1947 /* format change */ 1948 fmt_change = irq_reg_0x43 & 0x98; 1949 fmt_change_digital = is_digital_input(sd) 1950 ? irq_reg_0x6b & info->fmt_change_digital_mask 1951 : 0; 1952 1953 if (fmt_change || fmt_change_digital) { 1954 v4l2_dbg(1, debug, sd, 1955 "%s: fmt_change = 0x%x, fmt_change_digital = 0x%x\n", 1956 __func__, fmt_change, fmt_change_digital); 1957 1958 v4l2_subdev_notify_event(sd, &adv76xx_ev_fmt); 1959 1960 if (handled) 1961 *handled = true; 1962 } 1963 /* HDMI/DVI mode */ 1964 if (irq_reg_0x6b & 0x01) { 1965 v4l2_dbg(1, debug, sd, "%s: irq %s mode\n", __func__, 1966 (io_read(sd, 0x6a) & 0x01) ? "HDMI" : "DVI"); 1967 set_rgb_quantization_range(sd); 1968 if (handled) 1969 *handled = true; 1970 } 1971 1972 /* tx 5v detect */ 1973 tx_5v = irq_reg_0x70 & info->cable_det_mask; 1974 if (tx_5v) { 1975 v4l2_dbg(1, debug, sd, "%s: tx_5v: 0x%x\n", __func__, tx_5v); 1976 adv76xx_s_detect_tx_5v_ctrl(sd); 1977 if (handled) 1978 *handled = true; 1979 } 1980 return 0; 1981 } 1982 1983 static int adv76xx_get_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid) 1984 { 1985 struct adv76xx_state *state = to_state(sd); 1986 u8 *data = NULL; 1987 1988 memset(edid->reserved, 0, sizeof(edid->reserved)); 1989 1990 switch (edid->pad) { 1991 case ADV76XX_PAD_HDMI_PORT_A: 1992 case ADV7604_PAD_HDMI_PORT_B: 1993 case ADV7604_PAD_HDMI_PORT_C: 1994 case ADV7604_PAD_HDMI_PORT_D: 1995 if (state->edid.present & (1 << edid->pad)) 1996 data = state->edid.edid; 1997 break; 1998 default: 1999 return -EINVAL; 2000 } 2001 2002 if (edid->start_block == 0 && edid->blocks == 0) { 2003 edid->blocks = data ? state->edid.blocks : 0; 2004 return 0; 2005 } 2006 2007 if (data == NULL) 2008 return -ENODATA; 2009 2010 if (edid->start_block >= state->edid.blocks) 2011 return -EINVAL; 2012 2013 if (edid->start_block + edid->blocks > state->edid.blocks) 2014 edid->blocks = state->edid.blocks - edid->start_block; 2015 2016 memcpy(edid->edid, data + edid->start_block * 128, edid->blocks * 128); 2017 2018 return 0; 2019 } 2020 2021 static int get_edid_spa_location(const u8 *edid) 2022 { 2023 u8 d; 2024 2025 if ((edid[0x7e] != 1) || 2026 (edid[0x80] != 0x02) || 2027 (edid[0x81] != 0x03)) { 2028 return -1; 2029 } 2030 2031 /* search Vendor Specific Data Block (tag 3) */ 2032 d = edid[0x82] & 0x7f; 2033 if (d > 4) { 2034 int i = 0x84; 2035 int end = 0x80 + d; 2036 2037 do { 2038 u8 tag = edid[i] >> 5; 2039 u8 len = edid[i] & 0x1f; 2040 2041 if ((tag == 3) && (len >= 5)) 2042 return i + 4; 2043 i += len + 1; 2044 } while (i < end); 2045 } 2046 return -1; 2047 } 2048 2049 static int adv76xx_set_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid) 2050 { 2051 struct adv76xx_state *state = to_state(sd); 2052 const struct adv76xx_chip_info *info = state->info; 2053 int spa_loc; 2054 int err; 2055 int i; 2056 2057 memset(edid->reserved, 0, sizeof(edid->reserved)); 2058 2059 if (edid->pad > ADV7604_PAD_HDMI_PORT_D) 2060 return -EINVAL; 2061 if (edid->start_block != 0) 2062 return -EINVAL; 2063 if (edid->blocks == 0) { 2064 /* Disable hotplug and I2C access to EDID RAM from DDC port */ 2065 state->edid.present &= ~(1 << edid->pad); 2066 adv76xx_set_hpd(state, state->edid.present); 2067 rep_write_clr_set(sd, info->edid_enable_reg, 0x0f, state->edid.present); 2068 2069 /* Fall back to a 16:9 aspect ratio */ 2070 state->aspect_ratio.numerator = 16; 2071 state->aspect_ratio.denominator = 9; 2072 2073 if (!state->edid.present) 2074 state->edid.blocks = 0; 2075 2076 v4l2_dbg(2, debug, sd, "%s: clear EDID pad %d, edid.present = 0x%x\n", 2077 __func__, edid->pad, state->edid.present); 2078 return 0; 2079 } 2080 if (edid->blocks > 2) { 2081 edid->blocks = 2; 2082 return -E2BIG; 2083 } 2084 2085 v4l2_dbg(2, debug, sd, "%s: write EDID pad %d, edid.present = 0x%x\n", 2086 __func__, edid->pad, state->edid.present); 2087 2088 /* Disable hotplug and I2C access to EDID RAM from DDC port */ 2089 cancel_delayed_work_sync(&state->delayed_work_enable_hotplug); 2090 adv76xx_set_hpd(state, 0); 2091 rep_write_clr_set(sd, info->edid_enable_reg, 0x0f, 0x00); 2092 2093 spa_loc = get_edid_spa_location(edid->edid); 2094 if (spa_loc < 0) 2095 spa_loc = 0xc0; /* Default value [REF_02, p. 116] */ 2096 2097 switch (edid->pad) { 2098 case ADV76XX_PAD_HDMI_PORT_A: 2099 state->spa_port_a[0] = edid->edid[spa_loc]; 2100 state->spa_port_a[1] = edid->edid[spa_loc + 1]; 2101 break; 2102 case ADV7604_PAD_HDMI_PORT_B: 2103 rep_write(sd, 0x70, edid->edid[spa_loc]); 2104 rep_write(sd, 0x71, edid->edid[spa_loc + 1]); 2105 break; 2106 case ADV7604_PAD_HDMI_PORT_C: 2107 rep_write(sd, 0x72, edid->edid[spa_loc]); 2108 rep_write(sd, 0x73, edid->edid[spa_loc + 1]); 2109 break; 2110 case ADV7604_PAD_HDMI_PORT_D: 2111 rep_write(sd, 0x74, edid->edid[spa_loc]); 2112 rep_write(sd, 0x75, edid->edid[spa_loc + 1]); 2113 break; 2114 default: 2115 return -EINVAL; 2116 } 2117 2118 if (info->type == ADV7604) { 2119 rep_write(sd, 0x76, spa_loc & 0xff); 2120 rep_write_clr_set(sd, 0x77, 0x40, (spa_loc & 0x100) >> 2); 2121 } else { 2122 /* ADV7612 Software Manual Rev. A, p. 15 */ 2123 rep_write(sd, 0x70, spa_loc & 0xff); 2124 rep_write_clr_set(sd, 0x71, 0x01, (spa_loc & 0x100) >> 8); 2125 } 2126 2127 edid->edid[spa_loc] = state->spa_port_a[0]; 2128 edid->edid[spa_loc + 1] = state->spa_port_a[1]; 2129 2130 memcpy(state->edid.edid, edid->edid, 128 * edid->blocks); 2131 state->edid.blocks = edid->blocks; 2132 state->aspect_ratio = v4l2_calc_aspect_ratio(edid->edid[0x15], 2133 edid->edid[0x16]); 2134 state->edid.present |= 1 << edid->pad; 2135 2136 err = edid_write_block(sd, 128 * edid->blocks, state->edid.edid); 2137 if (err < 0) { 2138 v4l2_err(sd, "error %d writing edid pad %d\n", err, edid->pad); 2139 return err; 2140 } 2141 2142 /* adv76xx calculates the checksums and enables I2C access to internal 2143 EDID RAM from DDC port. */ 2144 rep_write_clr_set(sd, info->edid_enable_reg, 0x0f, state->edid.present); 2145 2146 for (i = 0; i < 1000; i++) { 2147 if (rep_read(sd, info->edid_status_reg) & state->edid.present) 2148 break; 2149 mdelay(1); 2150 } 2151 if (i == 1000) { 2152 v4l2_err(sd, "error enabling edid (0x%x)\n", state->edid.present); 2153 return -EIO; 2154 } 2155 2156 /* enable hotplug after 100 ms */ 2157 queue_delayed_work(state->work_queues, 2158 &state->delayed_work_enable_hotplug, HZ / 10); 2159 return 0; 2160 } 2161 2162 /*********** avi info frame CEA-861-E **************/ 2163 2164 static const struct adv76xx_cfg_read_infoframe adv76xx_cri[] = { 2165 { "AVI", 0x01, 0xe0, 0x00 }, 2166 { "Audio", 0x02, 0xe3, 0x1c }, 2167 { "SDP", 0x04, 0xe6, 0x2a }, 2168 { "Vendor", 0x10, 0xec, 0x54 } 2169 }; 2170 2171 static int adv76xx_read_infoframe(struct v4l2_subdev *sd, int index, 2172 union hdmi_infoframe *frame) 2173 { 2174 uint8_t buffer[32]; 2175 u8 len; 2176 int i; 2177 2178 if (!(io_read(sd, 0x60) & adv76xx_cri[index].present_mask)) { 2179 v4l2_info(sd, "%s infoframe not received\n", 2180 adv76xx_cri[index].desc); 2181 return -ENOENT; 2182 } 2183 2184 for (i = 0; i < 3; i++) 2185 buffer[i] = infoframe_read(sd, 2186 adv76xx_cri[index].head_addr + i); 2187 2188 len = buffer[2] + 1; 2189 2190 if (len + 3 > sizeof(buffer)) { 2191 v4l2_err(sd, "%s: invalid %s infoframe length %d\n", __func__, 2192 adv76xx_cri[index].desc, len); 2193 return -ENOENT; 2194 } 2195 2196 for (i = 0; i < len; i++) 2197 buffer[i + 3] = infoframe_read(sd, 2198 adv76xx_cri[index].payload_addr + i); 2199 2200 if (hdmi_infoframe_unpack(frame, buffer) < 0) { 2201 v4l2_err(sd, "%s: unpack of %s infoframe failed\n", __func__, 2202 adv76xx_cri[index].desc); 2203 return -ENOENT; 2204 } 2205 return 0; 2206 } 2207 2208 static void adv76xx_log_infoframes(struct v4l2_subdev *sd) 2209 { 2210 int i; 2211 2212 if (!is_hdmi(sd)) { 2213 v4l2_info(sd, "receive DVI-D signal, no infoframes\n"); 2214 return; 2215 } 2216 2217 for (i = 0; i < ARRAY_SIZE(adv76xx_cri); i++) { 2218 union hdmi_infoframe frame; 2219 struct i2c_client *client = v4l2_get_subdevdata(sd); 2220 2221 if (adv76xx_read_infoframe(sd, i, &frame)) 2222 return; 2223 hdmi_infoframe_log(KERN_INFO, &client->dev, &frame); 2224 } 2225 } 2226 2227 static int adv76xx_log_status(struct v4l2_subdev *sd) 2228 { 2229 struct adv76xx_state *state = to_state(sd); 2230 const struct adv76xx_chip_info *info = state->info; 2231 struct v4l2_dv_timings timings; 2232 struct stdi_readback stdi; 2233 u8 reg_io_0x02 = io_read(sd, 0x02); 2234 u8 edid_enabled; 2235 u8 cable_det; 2236 2237 static const char * const csc_coeff_sel_rb[16] = { 2238 "bypassed", "YPbPr601 -> RGB", "reserved", "YPbPr709 -> RGB", 2239 "reserved", "RGB -> YPbPr601", "reserved", "RGB -> YPbPr709", 2240 "reserved", "YPbPr709 -> YPbPr601", "YPbPr601 -> YPbPr709", 2241 "reserved", "reserved", "reserved", "reserved", "manual" 2242 }; 2243 static const char * const input_color_space_txt[16] = { 2244 "RGB limited range (16-235)", "RGB full range (0-255)", 2245 "YCbCr Bt.601 (16-235)", "YCbCr Bt.709 (16-235)", 2246 "xvYCC Bt.601", "xvYCC Bt.709", 2247 "YCbCr Bt.601 (0-255)", "YCbCr Bt.709 (0-255)", 2248 "invalid", "invalid", "invalid", "invalid", "invalid", 2249 "invalid", "invalid", "automatic" 2250 }; 2251 static const char * const hdmi_color_space_txt[16] = { 2252 "RGB limited range (16-235)", "RGB full range (0-255)", 2253 "YCbCr Bt.601 (16-235)", "YCbCr Bt.709 (16-235)", 2254 "xvYCC Bt.601", "xvYCC Bt.709", 2255 "YCbCr Bt.601 (0-255)", "YCbCr Bt.709 (0-255)", 2256 "sYCC", "Adobe YCC 601", "AdobeRGB", "invalid", "invalid", 2257 "invalid", "invalid", "invalid" 2258 }; 2259 static const char * const rgb_quantization_range_txt[] = { 2260 "Automatic", 2261 "RGB limited range (16-235)", 2262 "RGB full range (0-255)", 2263 }; 2264 static const char * const deep_color_mode_txt[4] = { 2265 "8-bits per channel", 2266 "10-bits per channel", 2267 "12-bits per channel", 2268 "16-bits per channel (not supported)" 2269 }; 2270 2271 v4l2_info(sd, "-----Chip status-----\n"); 2272 v4l2_info(sd, "Chip power: %s\n", no_power(sd) ? "off" : "on"); 2273 edid_enabled = rep_read(sd, info->edid_status_reg); 2274 v4l2_info(sd, "EDID enabled port A: %s, B: %s, C: %s, D: %s\n", 2275 ((edid_enabled & 0x01) ? "Yes" : "No"), 2276 ((edid_enabled & 0x02) ? "Yes" : "No"), 2277 ((edid_enabled & 0x04) ? "Yes" : "No"), 2278 ((edid_enabled & 0x08) ? "Yes" : "No")); 2279 v4l2_info(sd, "CEC: %s\n", !!(cec_read(sd, 0x2a) & 0x01) ? 2280 "enabled" : "disabled"); 2281 2282 v4l2_info(sd, "-----Signal status-----\n"); 2283 cable_det = info->read_cable_det(sd); 2284 v4l2_info(sd, "Cable detected (+5V power) port A: %s, B: %s, C: %s, D: %s\n", 2285 ((cable_det & 0x01) ? "Yes" : "No"), 2286 ((cable_det & 0x02) ? "Yes" : "No"), 2287 ((cable_det & 0x04) ? "Yes" : "No"), 2288 ((cable_det & 0x08) ? "Yes" : "No")); 2289 v4l2_info(sd, "TMDS signal detected: %s\n", 2290 no_signal_tmds(sd) ? "false" : "true"); 2291 v4l2_info(sd, "TMDS signal locked: %s\n", 2292 no_lock_tmds(sd) ? "false" : "true"); 2293 v4l2_info(sd, "SSPD locked: %s\n", no_lock_sspd(sd) ? "false" : "true"); 2294 v4l2_info(sd, "STDI locked: %s\n", no_lock_stdi(sd) ? "false" : "true"); 2295 v4l2_info(sd, "CP locked: %s\n", no_lock_cp(sd) ? "false" : "true"); 2296 v4l2_info(sd, "CP free run: %s\n", 2297 (in_free_run(sd)) ? "on" : "off"); 2298 v4l2_info(sd, "Prim-mode = 0x%x, video std = 0x%x, v_freq = 0x%x\n", 2299 io_read(sd, 0x01) & 0x0f, io_read(sd, 0x00) & 0x3f, 2300 (io_read(sd, 0x01) & 0x70) >> 4); 2301 2302 v4l2_info(sd, "-----Video Timings-----\n"); 2303 if (read_stdi(sd, &stdi)) 2304 v4l2_info(sd, "STDI: not locked\n"); 2305 else 2306 v4l2_info(sd, "STDI: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %s, %chsync, %cvsync\n", 2307 stdi.lcf, stdi.bl, stdi.lcvs, 2308 stdi.interlaced ? "interlaced" : "progressive", 2309 stdi.hs_pol, stdi.vs_pol); 2310 if (adv76xx_query_dv_timings(sd, &timings)) 2311 v4l2_info(sd, "No video detected\n"); 2312 else 2313 v4l2_print_dv_timings(sd->name, "Detected format: ", 2314 &timings, true); 2315 v4l2_print_dv_timings(sd->name, "Configured format: ", 2316 &state->timings, true); 2317 2318 if (no_signal(sd)) 2319 return 0; 2320 2321 v4l2_info(sd, "-----Color space-----\n"); 2322 v4l2_info(sd, "RGB quantization range ctrl: %s\n", 2323 rgb_quantization_range_txt[state->rgb_quantization_range]); 2324 v4l2_info(sd, "Input color space: %s\n", 2325 input_color_space_txt[reg_io_0x02 >> 4]); 2326 v4l2_info(sd, "Output color space: %s %s, saturator %s, alt-gamma %s\n", 2327 (reg_io_0x02 & 0x02) ? "RGB" : "YCbCr", 2328 (reg_io_0x02 & 0x04) ? "(16-235)" : "(0-255)", 2329 (((reg_io_0x02 >> 2) & 0x01) ^ (reg_io_0x02 & 0x01)) ? 2330 "enabled" : "disabled", 2331 (reg_io_0x02 & 0x08) ? "enabled" : "disabled"); 2332 v4l2_info(sd, "Color space conversion: %s\n", 2333 csc_coeff_sel_rb[cp_read(sd, info->cp_csc) >> 4]); 2334 2335 if (!is_digital_input(sd)) 2336 return 0; 2337 2338 v4l2_info(sd, "-----%s status-----\n", is_hdmi(sd) ? "HDMI" : "DVI-D"); 2339 v4l2_info(sd, "Digital video port selected: %c\n", 2340 (hdmi_read(sd, 0x00) & 0x03) + 'A'); 2341 v4l2_info(sd, "HDCP encrypted content: %s\n", 2342 (hdmi_read(sd, 0x05) & 0x40) ? "true" : "false"); 2343 v4l2_info(sd, "HDCP keys read: %s%s\n", 2344 (hdmi_read(sd, 0x04) & 0x20) ? "yes" : "no", 2345 (hdmi_read(sd, 0x04) & 0x10) ? "ERROR" : ""); 2346 if (is_hdmi(sd)) { 2347 bool audio_pll_locked = hdmi_read(sd, 0x04) & 0x01; 2348 bool audio_sample_packet_detect = hdmi_read(sd, 0x18) & 0x01; 2349 bool audio_mute = io_read(sd, 0x65) & 0x40; 2350 2351 v4l2_info(sd, "Audio: pll %s, samples %s, %s\n", 2352 audio_pll_locked ? "locked" : "not locked", 2353 audio_sample_packet_detect ? "detected" : "not detected", 2354 audio_mute ? "muted" : "enabled"); 2355 if (audio_pll_locked && audio_sample_packet_detect) { 2356 v4l2_info(sd, "Audio format: %s\n", 2357 (hdmi_read(sd, 0x07) & 0x20) ? "multi-channel" : "stereo"); 2358 } 2359 v4l2_info(sd, "Audio CTS: %u\n", (hdmi_read(sd, 0x5b) << 12) + 2360 (hdmi_read(sd, 0x5c) << 8) + 2361 (hdmi_read(sd, 0x5d) & 0xf0)); 2362 v4l2_info(sd, "Audio N: %u\n", ((hdmi_read(sd, 0x5d) & 0x0f) << 16) + 2363 (hdmi_read(sd, 0x5e) << 8) + 2364 hdmi_read(sd, 0x5f)); 2365 v4l2_info(sd, "AV Mute: %s\n", (hdmi_read(sd, 0x04) & 0x40) ? "on" : "off"); 2366 2367 v4l2_info(sd, "Deep color mode: %s\n", deep_color_mode_txt[(hdmi_read(sd, 0x0b) & 0x60) >> 5]); 2368 v4l2_info(sd, "HDMI colorspace: %s\n", hdmi_color_space_txt[hdmi_read(sd, 0x53) & 0xf]); 2369 2370 adv76xx_log_infoframes(sd); 2371 } 2372 2373 return 0; 2374 } 2375 2376 static int adv76xx_subscribe_event(struct v4l2_subdev *sd, 2377 struct v4l2_fh *fh, 2378 struct v4l2_event_subscription *sub) 2379 { 2380 switch (sub->type) { 2381 case V4L2_EVENT_SOURCE_CHANGE: 2382 return v4l2_src_change_event_subdev_subscribe(sd, fh, sub); 2383 case V4L2_EVENT_CTRL: 2384 return v4l2_ctrl_subdev_subscribe_event(sd, fh, sub); 2385 default: 2386 return -EINVAL; 2387 } 2388 } 2389 2390 /* ----------------------------------------------------------------------- */ 2391 2392 static const struct v4l2_ctrl_ops adv76xx_ctrl_ops = { 2393 .s_ctrl = adv76xx_s_ctrl, 2394 .g_volatile_ctrl = adv76xx_g_volatile_ctrl, 2395 }; 2396 2397 static const struct v4l2_subdev_core_ops adv76xx_core_ops = { 2398 .log_status = adv76xx_log_status, 2399 .interrupt_service_routine = adv76xx_isr, 2400 .subscribe_event = adv76xx_subscribe_event, 2401 .unsubscribe_event = v4l2_event_subdev_unsubscribe, 2402 #ifdef CONFIG_VIDEO_ADV_DEBUG 2403 .g_register = adv76xx_g_register, 2404 .s_register = adv76xx_s_register, 2405 #endif 2406 }; 2407 2408 static const struct v4l2_subdev_video_ops adv76xx_video_ops = { 2409 .s_routing = adv76xx_s_routing, 2410 .g_input_status = adv76xx_g_input_status, 2411 .s_dv_timings = adv76xx_s_dv_timings, 2412 .g_dv_timings = adv76xx_g_dv_timings, 2413 .query_dv_timings = adv76xx_query_dv_timings, 2414 }; 2415 2416 static const struct v4l2_subdev_pad_ops adv76xx_pad_ops = { 2417 .enum_mbus_code = adv76xx_enum_mbus_code, 2418 .get_selection = adv76xx_get_selection, 2419 .get_fmt = adv76xx_get_format, 2420 .set_fmt = adv76xx_set_format, 2421 .get_edid = adv76xx_get_edid, 2422 .set_edid = adv76xx_set_edid, 2423 .dv_timings_cap = adv76xx_dv_timings_cap, 2424 .enum_dv_timings = adv76xx_enum_dv_timings, 2425 }; 2426 2427 static const struct v4l2_subdev_ops adv76xx_ops = { 2428 .core = &adv76xx_core_ops, 2429 .video = &adv76xx_video_ops, 2430 .pad = &adv76xx_pad_ops, 2431 }; 2432 2433 /* -------------------------- custom ctrls ---------------------------------- */ 2434 2435 static const struct v4l2_ctrl_config adv7604_ctrl_analog_sampling_phase = { 2436 .ops = &adv76xx_ctrl_ops, 2437 .id = V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE, 2438 .name = "Analog Sampling Phase", 2439 .type = V4L2_CTRL_TYPE_INTEGER, 2440 .min = 0, 2441 .max = 0x1f, 2442 .step = 1, 2443 .def = 0, 2444 }; 2445 2446 static const struct v4l2_ctrl_config adv76xx_ctrl_free_run_color_manual = { 2447 .ops = &adv76xx_ctrl_ops, 2448 .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL, 2449 .name = "Free Running Color, Manual", 2450 .type = V4L2_CTRL_TYPE_BOOLEAN, 2451 .min = false, 2452 .max = true, 2453 .step = 1, 2454 .def = false, 2455 }; 2456 2457 static const struct v4l2_ctrl_config adv76xx_ctrl_free_run_color = { 2458 .ops = &adv76xx_ctrl_ops, 2459 .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR, 2460 .name = "Free Running Color", 2461 .type = V4L2_CTRL_TYPE_INTEGER, 2462 .min = 0x0, 2463 .max = 0xffffff, 2464 .step = 0x1, 2465 .def = 0x0, 2466 }; 2467 2468 /* ----------------------------------------------------------------------- */ 2469 2470 static int adv76xx_core_init(struct v4l2_subdev *sd) 2471 { 2472 struct adv76xx_state *state = to_state(sd); 2473 const struct adv76xx_chip_info *info = state->info; 2474 struct adv76xx_platform_data *pdata = &state->pdata; 2475 2476 hdmi_write(sd, 0x48, 2477 (pdata->disable_pwrdnb ? 0x80 : 0) | 2478 (pdata->disable_cable_det_rst ? 0x40 : 0)); 2479 2480 disable_input(sd); 2481 2482 if (pdata->default_input >= 0 && 2483 pdata->default_input < state->source_pad) { 2484 state->selected_input = pdata->default_input; 2485 select_input(sd); 2486 enable_input(sd); 2487 } 2488 2489 /* power */ 2490 io_write(sd, 0x0c, 0x42); /* Power up part and power down VDP */ 2491 io_write(sd, 0x0b, 0x44); /* Power down ESDP block */ 2492 cp_write(sd, 0xcf, 0x01); /* Power down macrovision */ 2493 2494 /* video format */ 2495 io_write_clr_set(sd, 0x02, 0x0f, 2496 pdata->alt_gamma << 3 | 2497 pdata->op_656_range << 2 | 2498 pdata->alt_data_sat << 0); 2499 io_write_clr_set(sd, 0x05, 0x0e, pdata->blank_data << 3 | 2500 pdata->insert_av_codes << 2 | 2501 pdata->replicate_av_codes << 1); 2502 adv76xx_setup_format(state); 2503 2504 cp_write(sd, 0x69, 0x30); /* Enable CP CSC */ 2505 2506 /* VS, HS polarities */ 2507 io_write(sd, 0x06, 0xa0 | pdata->inv_vs_pol << 2 | 2508 pdata->inv_hs_pol << 1 | pdata->inv_llc_pol); 2509 2510 /* Adjust drive strength */ 2511 io_write(sd, 0x14, 0x40 | pdata->dr_str_data << 4 | 2512 pdata->dr_str_clk << 2 | 2513 pdata->dr_str_sync); 2514 2515 cp_write(sd, 0xba, (pdata->hdmi_free_run_mode << 1) | 0x01); /* HDMI free run */ 2516 cp_write(sd, 0xf3, 0xdc); /* Low threshold to enter/exit free run mode */ 2517 cp_write(sd, 0xf9, 0x23); /* STDI ch. 1 - LCVS change threshold - 2518 ADI recommended setting [REF_01, c. 2.3.3] */ 2519 cp_write(sd, 0x45, 0x23); /* STDI ch. 2 - LCVS change threshold - 2520 ADI recommended setting [REF_01, c. 2.3.3] */ 2521 cp_write(sd, 0xc9, 0x2d); /* use prim_mode and vid_std as free run resolution 2522 for digital formats */ 2523 2524 /* HDMI audio */ 2525 hdmi_write_clr_set(sd, 0x15, 0x03, 0x03); /* Mute on FIFO over-/underflow [REF_01, c. 1.2.18] */ 2526 hdmi_write_clr_set(sd, 0x1a, 0x0e, 0x08); /* Wait 1 s before unmute */ 2527 hdmi_write_clr_set(sd, 0x68, 0x06, 0x06); /* FIFO reset on over-/underflow [REF_01, c. 1.2.19] */ 2528 2529 /* TODO from platform data */ 2530 afe_write(sd, 0xb5, 0x01); /* Setting MCLK to 256Fs */ 2531 2532 if (adv76xx_has_afe(state)) { 2533 afe_write(sd, 0x02, pdata->ain_sel); /* Select analog input muxing mode */ 2534 io_write_clr_set(sd, 0x30, 1 << 4, pdata->output_bus_lsb_to_msb << 4); 2535 } 2536 2537 /* interrupts */ 2538 io_write(sd, 0x40, 0xc0 | pdata->int1_config); /* Configure INT1 */ 2539 io_write(sd, 0x46, 0x98); /* Enable SSPD, STDI and CP unlocked interrupts */ 2540 io_write(sd, 0x6e, info->fmt_change_digital_mask); /* Enable V_LOCKED and DE_REGEN_LCK interrupts */ 2541 io_write(sd, 0x73, info->cable_det_mask); /* Enable cable detection (+5v) interrupts */ 2542 info->setup_irqs(sd); 2543 2544 return v4l2_ctrl_handler_setup(sd->ctrl_handler); 2545 } 2546 2547 static void adv7604_setup_irqs(struct v4l2_subdev *sd) 2548 { 2549 io_write(sd, 0x41, 0xd7); /* STDI irq for any change, disable INT2 */ 2550 } 2551 2552 static void adv7611_setup_irqs(struct v4l2_subdev *sd) 2553 { 2554 io_write(sd, 0x41, 0xd0); /* STDI irq for any change, disable INT2 */ 2555 } 2556 2557 static void adv7612_setup_irqs(struct v4l2_subdev *sd) 2558 { 2559 io_write(sd, 0x41, 0xd0); /* disable INT2 */ 2560 } 2561 2562 static void adv76xx_unregister_clients(struct adv76xx_state *state) 2563 { 2564 unsigned int i; 2565 2566 for (i = 1; i < ARRAY_SIZE(state->i2c_clients); ++i) { 2567 if (state->i2c_clients[i]) 2568 i2c_unregister_device(state->i2c_clients[i]); 2569 } 2570 } 2571 2572 static struct i2c_client *adv76xx_dummy_client(struct v4l2_subdev *sd, 2573 u8 addr, u8 io_reg) 2574 { 2575 struct i2c_client *client = v4l2_get_subdevdata(sd); 2576 2577 if (addr) 2578 io_write(sd, io_reg, addr << 1); 2579 return i2c_new_dummy(client->adapter, io_read(sd, io_reg) >> 1); 2580 } 2581 2582 static const struct adv76xx_reg_seq adv7604_recommended_settings_afe[] = { 2583 /* reset ADI recommended settings for HDMI: */ 2584 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 4. */ 2585 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x0d), 0x04 }, /* HDMI filter optimization */ 2586 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x0d), 0x04 }, /* HDMI filter optimization */ 2587 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x3d), 0x00 }, /* DDC bus active pull-up control */ 2588 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x3e), 0x74 }, /* TMDS PLL optimization */ 2589 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x4e), 0x3b }, /* TMDS PLL optimization */ 2590 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x57), 0x74 }, /* TMDS PLL optimization */ 2591 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x58), 0x63 }, /* TMDS PLL optimization */ 2592 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8d), 0x18 }, /* equaliser */ 2593 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8e), 0x34 }, /* equaliser */ 2594 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x93), 0x88 }, /* equaliser */ 2595 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x94), 0x2e }, /* equaliser */ 2596 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x96), 0x00 }, /* enable automatic EQ changing */ 2597 2598 /* set ADI recommended settings for digitizer */ 2599 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 17. */ 2600 { ADV76XX_REG(ADV76XX_PAGE_AFE, 0x12), 0x7b }, /* ADC noise shaping filter controls */ 2601 { ADV76XX_REG(ADV76XX_PAGE_AFE, 0x0c), 0x1f }, /* CP core gain controls */ 2602 { ADV76XX_REG(ADV76XX_PAGE_CP, 0x3e), 0x04 }, /* CP core pre-gain control */ 2603 { ADV76XX_REG(ADV76XX_PAGE_CP, 0xc3), 0x39 }, /* CP coast control. Graphics mode */ 2604 { ADV76XX_REG(ADV76XX_PAGE_CP, 0x40), 0x5c }, /* CP core pre-gain control. Graphics mode */ 2605 2606 { ADV76XX_REG_SEQ_TERM, 0 }, 2607 }; 2608 2609 static const struct adv76xx_reg_seq adv7604_recommended_settings_hdmi[] = { 2610 /* set ADI recommended settings for HDMI: */ 2611 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 4. */ 2612 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x0d), 0x84 }, /* HDMI filter optimization */ 2613 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x3d), 0x10 }, /* DDC bus active pull-up control */ 2614 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x3e), 0x39 }, /* TMDS PLL optimization */ 2615 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x4e), 0x3b }, /* TMDS PLL optimization */ 2616 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x57), 0xb6 }, /* TMDS PLL optimization */ 2617 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x58), 0x03 }, /* TMDS PLL optimization */ 2618 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8d), 0x18 }, /* equaliser */ 2619 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8e), 0x34 }, /* equaliser */ 2620 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x93), 0x8b }, /* equaliser */ 2621 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x94), 0x2d }, /* equaliser */ 2622 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x96), 0x01 }, /* enable automatic EQ changing */ 2623 2624 /* reset ADI recommended settings for digitizer */ 2625 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 17. */ 2626 { ADV76XX_REG(ADV76XX_PAGE_AFE, 0x12), 0xfb }, /* ADC noise shaping filter controls */ 2627 { ADV76XX_REG(ADV76XX_PAGE_AFE, 0x0c), 0x0d }, /* CP core gain controls */ 2628 2629 { ADV76XX_REG_SEQ_TERM, 0 }, 2630 }; 2631 2632 static const struct adv76xx_reg_seq adv7611_recommended_settings_hdmi[] = { 2633 /* ADV7611 Register Settings Recommendations Rev 1.5, May 2014 */ 2634 { ADV76XX_REG(ADV76XX_PAGE_CP, 0x6c), 0x00 }, 2635 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x9b), 0x03 }, 2636 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x6f), 0x08 }, 2637 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x85), 0x1f }, 2638 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x87), 0x70 }, 2639 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x57), 0xda }, 2640 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x58), 0x01 }, 2641 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x03), 0x98 }, 2642 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x4c), 0x44 }, 2643 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8d), 0x04 }, 2644 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8e), 0x1e }, 2645 2646 { ADV76XX_REG_SEQ_TERM, 0 }, 2647 }; 2648 2649 static const struct adv76xx_reg_seq adv7612_recommended_settings_hdmi[] = { 2650 { ADV76XX_REG(ADV76XX_PAGE_CP, 0x6c), 0x00 }, 2651 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x9b), 0x03 }, 2652 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x6f), 0x08 }, 2653 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x85), 0x1f }, 2654 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x87), 0x70 }, 2655 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x57), 0xda }, 2656 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x58), 0x01 }, 2657 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x03), 0x98 }, 2658 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x4c), 0x44 }, 2659 { ADV76XX_REG_SEQ_TERM, 0 }, 2660 }; 2661 2662 static const struct adv76xx_chip_info adv76xx_chip_info[] = { 2663 [ADV7604] = { 2664 .type = ADV7604, 2665 .has_afe = true, 2666 .max_port = ADV7604_PAD_VGA_COMP, 2667 .num_dv_ports = 4, 2668 .edid_enable_reg = 0x77, 2669 .edid_status_reg = 0x7d, 2670 .lcf_reg = 0xb3, 2671 .tdms_lock_mask = 0xe0, 2672 .cable_det_mask = 0x1e, 2673 .fmt_change_digital_mask = 0xc1, 2674 .cp_csc = 0xfc, 2675 .formats = adv7604_formats, 2676 .nformats = ARRAY_SIZE(adv7604_formats), 2677 .set_termination = adv7604_set_termination, 2678 .setup_irqs = adv7604_setup_irqs, 2679 .read_hdmi_pixelclock = adv7604_read_hdmi_pixelclock, 2680 .read_cable_det = adv7604_read_cable_det, 2681 .recommended_settings = { 2682 [0] = adv7604_recommended_settings_afe, 2683 [1] = adv7604_recommended_settings_hdmi, 2684 }, 2685 .num_recommended_settings = { 2686 [0] = ARRAY_SIZE(adv7604_recommended_settings_afe), 2687 [1] = ARRAY_SIZE(adv7604_recommended_settings_hdmi), 2688 }, 2689 .page_mask = BIT(ADV76XX_PAGE_IO) | BIT(ADV7604_PAGE_AVLINK) | 2690 BIT(ADV76XX_PAGE_CEC) | BIT(ADV76XX_PAGE_INFOFRAME) | 2691 BIT(ADV7604_PAGE_ESDP) | BIT(ADV7604_PAGE_DPP) | 2692 BIT(ADV76XX_PAGE_AFE) | BIT(ADV76XX_PAGE_REP) | 2693 BIT(ADV76XX_PAGE_EDID) | BIT(ADV76XX_PAGE_HDMI) | 2694 BIT(ADV76XX_PAGE_TEST) | BIT(ADV76XX_PAGE_CP) | 2695 BIT(ADV7604_PAGE_VDP), 2696 .linewidth_mask = 0xfff, 2697 .field0_height_mask = 0xfff, 2698 .field1_height_mask = 0xfff, 2699 .hfrontporch_mask = 0x3ff, 2700 .hsync_mask = 0x3ff, 2701 .hbackporch_mask = 0x3ff, 2702 .field0_vfrontporch_mask = 0x1fff, 2703 .field0_vsync_mask = 0x1fff, 2704 .field0_vbackporch_mask = 0x1fff, 2705 .field1_vfrontporch_mask = 0x1fff, 2706 .field1_vsync_mask = 0x1fff, 2707 .field1_vbackporch_mask = 0x1fff, 2708 }, 2709 [ADV7611] = { 2710 .type = ADV7611, 2711 .has_afe = false, 2712 .max_port = ADV76XX_PAD_HDMI_PORT_A, 2713 .num_dv_ports = 1, 2714 .edid_enable_reg = 0x74, 2715 .edid_status_reg = 0x76, 2716 .lcf_reg = 0xa3, 2717 .tdms_lock_mask = 0x43, 2718 .cable_det_mask = 0x01, 2719 .fmt_change_digital_mask = 0x03, 2720 .cp_csc = 0xf4, 2721 .formats = adv7611_formats, 2722 .nformats = ARRAY_SIZE(adv7611_formats), 2723 .set_termination = adv7611_set_termination, 2724 .setup_irqs = adv7611_setup_irqs, 2725 .read_hdmi_pixelclock = adv7611_read_hdmi_pixelclock, 2726 .read_cable_det = adv7611_read_cable_det, 2727 .recommended_settings = { 2728 [1] = adv7611_recommended_settings_hdmi, 2729 }, 2730 .num_recommended_settings = { 2731 [1] = ARRAY_SIZE(adv7611_recommended_settings_hdmi), 2732 }, 2733 .page_mask = BIT(ADV76XX_PAGE_IO) | BIT(ADV76XX_PAGE_CEC) | 2734 BIT(ADV76XX_PAGE_INFOFRAME) | BIT(ADV76XX_PAGE_AFE) | 2735 BIT(ADV76XX_PAGE_REP) | BIT(ADV76XX_PAGE_EDID) | 2736 BIT(ADV76XX_PAGE_HDMI) | BIT(ADV76XX_PAGE_CP), 2737 .linewidth_mask = 0x1fff, 2738 .field0_height_mask = 0x1fff, 2739 .field1_height_mask = 0x1fff, 2740 .hfrontporch_mask = 0x1fff, 2741 .hsync_mask = 0x1fff, 2742 .hbackporch_mask = 0x1fff, 2743 .field0_vfrontporch_mask = 0x3fff, 2744 .field0_vsync_mask = 0x3fff, 2745 .field0_vbackporch_mask = 0x3fff, 2746 .field1_vfrontporch_mask = 0x3fff, 2747 .field1_vsync_mask = 0x3fff, 2748 .field1_vbackporch_mask = 0x3fff, 2749 }, 2750 [ADV7612] = { 2751 .type = ADV7612, 2752 .has_afe = false, 2753 .max_port = ADV76XX_PAD_HDMI_PORT_A, /* B not supported */ 2754 .num_dv_ports = 1, /* normally 2 */ 2755 .edid_enable_reg = 0x74, 2756 .edid_status_reg = 0x76, 2757 .lcf_reg = 0xa3, 2758 .tdms_lock_mask = 0x43, 2759 .cable_det_mask = 0x01, 2760 .fmt_change_digital_mask = 0x03, 2761 .cp_csc = 0xf4, 2762 .formats = adv7612_formats, 2763 .nformats = ARRAY_SIZE(adv7612_formats), 2764 .set_termination = adv7611_set_termination, 2765 .setup_irqs = adv7612_setup_irqs, 2766 .read_hdmi_pixelclock = adv7611_read_hdmi_pixelclock, 2767 .read_cable_det = adv7612_read_cable_det, 2768 .recommended_settings = { 2769 [1] = adv7612_recommended_settings_hdmi, 2770 }, 2771 .num_recommended_settings = { 2772 [1] = ARRAY_SIZE(adv7612_recommended_settings_hdmi), 2773 }, 2774 .page_mask = BIT(ADV76XX_PAGE_IO) | BIT(ADV76XX_PAGE_CEC) | 2775 BIT(ADV76XX_PAGE_INFOFRAME) | BIT(ADV76XX_PAGE_AFE) | 2776 BIT(ADV76XX_PAGE_REP) | BIT(ADV76XX_PAGE_EDID) | 2777 BIT(ADV76XX_PAGE_HDMI) | BIT(ADV76XX_PAGE_CP), 2778 .linewidth_mask = 0x1fff, 2779 .field0_height_mask = 0x1fff, 2780 .field1_height_mask = 0x1fff, 2781 .hfrontporch_mask = 0x1fff, 2782 .hsync_mask = 0x1fff, 2783 .hbackporch_mask = 0x1fff, 2784 .field0_vfrontporch_mask = 0x3fff, 2785 .field0_vsync_mask = 0x3fff, 2786 .field0_vbackporch_mask = 0x3fff, 2787 .field1_vfrontporch_mask = 0x3fff, 2788 .field1_vsync_mask = 0x3fff, 2789 .field1_vbackporch_mask = 0x3fff, 2790 }, 2791 }; 2792 2793 static const struct i2c_device_id adv76xx_i2c_id[] = { 2794 { "adv7604", (kernel_ulong_t)&adv76xx_chip_info[ADV7604] }, 2795 { "adv7611", (kernel_ulong_t)&adv76xx_chip_info[ADV7611] }, 2796 { "adv7612", (kernel_ulong_t)&adv76xx_chip_info[ADV7612] }, 2797 { } 2798 }; 2799 MODULE_DEVICE_TABLE(i2c, adv76xx_i2c_id); 2800 2801 static const struct of_device_id adv76xx_of_id[] __maybe_unused = { 2802 { .compatible = "adi,adv7611", .data = &adv76xx_chip_info[ADV7611] }, 2803 { .compatible = "adi,adv7612", .data = &adv76xx_chip_info[ADV7612] }, 2804 { } 2805 }; 2806 MODULE_DEVICE_TABLE(of, adv76xx_of_id); 2807 2808 static int adv76xx_parse_dt(struct adv76xx_state *state) 2809 { 2810 struct v4l2_of_endpoint bus_cfg; 2811 struct device_node *endpoint; 2812 struct device_node *np; 2813 unsigned int flags; 2814 int ret; 2815 u32 v; 2816 2817 np = state->i2c_clients[ADV76XX_PAGE_IO]->dev.of_node; 2818 2819 /* Parse the endpoint. */ 2820 endpoint = of_graph_get_next_endpoint(np, NULL); 2821 if (!endpoint) 2822 return -EINVAL; 2823 2824 ret = v4l2_of_parse_endpoint(endpoint, &bus_cfg); 2825 if (ret) { 2826 of_node_put(endpoint); 2827 return ret; 2828 } 2829 2830 if (!of_property_read_u32(endpoint, "default-input", &v)) 2831 state->pdata.default_input = v; 2832 else 2833 state->pdata.default_input = -1; 2834 2835 of_node_put(endpoint); 2836 2837 flags = bus_cfg.bus.parallel.flags; 2838 2839 if (flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH) 2840 state->pdata.inv_hs_pol = 1; 2841 2842 if (flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH) 2843 state->pdata.inv_vs_pol = 1; 2844 2845 if (flags & V4L2_MBUS_PCLK_SAMPLE_RISING) 2846 state->pdata.inv_llc_pol = 1; 2847 2848 if (bus_cfg.bus_type == V4L2_MBUS_BT656) { 2849 state->pdata.insert_av_codes = 1; 2850 state->pdata.op_656_range = 1; 2851 } 2852 2853 /* Disable the interrupt for now as no DT-based board uses it. */ 2854 state->pdata.int1_config = ADV76XX_INT1_CONFIG_DISABLED; 2855 2856 /* Use the default I2C addresses. */ 2857 state->pdata.i2c_addresses[ADV7604_PAGE_AVLINK] = 0x42; 2858 state->pdata.i2c_addresses[ADV76XX_PAGE_CEC] = 0x40; 2859 state->pdata.i2c_addresses[ADV76XX_PAGE_INFOFRAME] = 0x3e; 2860 state->pdata.i2c_addresses[ADV7604_PAGE_ESDP] = 0x38; 2861 state->pdata.i2c_addresses[ADV7604_PAGE_DPP] = 0x3c; 2862 state->pdata.i2c_addresses[ADV76XX_PAGE_AFE] = 0x26; 2863 state->pdata.i2c_addresses[ADV76XX_PAGE_REP] = 0x32; 2864 state->pdata.i2c_addresses[ADV76XX_PAGE_EDID] = 0x36; 2865 state->pdata.i2c_addresses[ADV76XX_PAGE_HDMI] = 0x34; 2866 state->pdata.i2c_addresses[ADV76XX_PAGE_TEST] = 0x30; 2867 state->pdata.i2c_addresses[ADV76XX_PAGE_CP] = 0x22; 2868 state->pdata.i2c_addresses[ADV7604_PAGE_VDP] = 0x24; 2869 2870 /* Hardcode the remaining platform data fields. */ 2871 state->pdata.disable_pwrdnb = 0; 2872 state->pdata.disable_cable_det_rst = 0; 2873 state->pdata.blank_data = 1; 2874 state->pdata.alt_data_sat = 1; 2875 state->pdata.op_format_mode_sel = ADV7604_OP_FORMAT_MODE0; 2876 state->pdata.bus_order = ADV7604_BUS_ORDER_RGB; 2877 2878 return 0; 2879 } 2880 2881 static const struct regmap_config adv76xx_regmap_cnf[] = { 2882 { 2883 .name = "io", 2884 .reg_bits = 8, 2885 .val_bits = 8, 2886 2887 .max_register = 0xff, 2888 .cache_type = REGCACHE_NONE, 2889 }, 2890 { 2891 .name = "avlink", 2892 .reg_bits = 8, 2893 .val_bits = 8, 2894 2895 .max_register = 0xff, 2896 .cache_type = REGCACHE_NONE, 2897 }, 2898 { 2899 .name = "cec", 2900 .reg_bits = 8, 2901 .val_bits = 8, 2902 2903 .max_register = 0xff, 2904 .cache_type = REGCACHE_NONE, 2905 }, 2906 { 2907 .name = "infoframe", 2908 .reg_bits = 8, 2909 .val_bits = 8, 2910 2911 .max_register = 0xff, 2912 .cache_type = REGCACHE_NONE, 2913 }, 2914 { 2915 .name = "esdp", 2916 .reg_bits = 8, 2917 .val_bits = 8, 2918 2919 .max_register = 0xff, 2920 .cache_type = REGCACHE_NONE, 2921 }, 2922 { 2923 .name = "epp", 2924 .reg_bits = 8, 2925 .val_bits = 8, 2926 2927 .max_register = 0xff, 2928 .cache_type = REGCACHE_NONE, 2929 }, 2930 { 2931 .name = "afe", 2932 .reg_bits = 8, 2933 .val_bits = 8, 2934 2935 .max_register = 0xff, 2936 .cache_type = REGCACHE_NONE, 2937 }, 2938 { 2939 .name = "rep", 2940 .reg_bits = 8, 2941 .val_bits = 8, 2942 2943 .max_register = 0xff, 2944 .cache_type = REGCACHE_NONE, 2945 }, 2946 { 2947 .name = "edid", 2948 .reg_bits = 8, 2949 .val_bits = 8, 2950 2951 .max_register = 0xff, 2952 .cache_type = REGCACHE_NONE, 2953 }, 2954 2955 { 2956 .name = "hdmi", 2957 .reg_bits = 8, 2958 .val_bits = 8, 2959 2960 .max_register = 0xff, 2961 .cache_type = REGCACHE_NONE, 2962 }, 2963 { 2964 .name = "test", 2965 .reg_bits = 8, 2966 .val_bits = 8, 2967 2968 .max_register = 0xff, 2969 .cache_type = REGCACHE_NONE, 2970 }, 2971 { 2972 .name = "cp", 2973 .reg_bits = 8, 2974 .val_bits = 8, 2975 2976 .max_register = 0xff, 2977 .cache_type = REGCACHE_NONE, 2978 }, 2979 { 2980 .name = "vdp", 2981 .reg_bits = 8, 2982 .val_bits = 8, 2983 2984 .max_register = 0xff, 2985 .cache_type = REGCACHE_NONE, 2986 }, 2987 }; 2988 2989 static int configure_regmap(struct adv76xx_state *state, int region) 2990 { 2991 int err; 2992 2993 if (!state->i2c_clients[region]) 2994 return -ENODEV; 2995 2996 state->regmap[region] = 2997 devm_regmap_init_i2c(state->i2c_clients[region], 2998 &adv76xx_regmap_cnf[region]); 2999 3000 if (IS_ERR(state->regmap[region])) { 3001 err = PTR_ERR(state->regmap[region]); 3002 v4l_err(state->i2c_clients[region], 3003 "Error initializing regmap %d with error %d\n", 3004 region, err); 3005 return -EINVAL; 3006 } 3007 3008 return 0; 3009 } 3010 3011 static int configure_regmaps(struct adv76xx_state *state) 3012 { 3013 int i, err; 3014 3015 for (i = ADV7604_PAGE_AVLINK ; i < ADV76XX_PAGE_MAX; i++) { 3016 err = configure_regmap(state, i); 3017 if (err && (err != -ENODEV)) 3018 return err; 3019 } 3020 return 0; 3021 } 3022 3023 static int adv76xx_probe(struct i2c_client *client, 3024 const struct i2c_device_id *id) 3025 { 3026 static const struct v4l2_dv_timings cea640x480 = 3027 V4L2_DV_BT_CEA_640X480P59_94; 3028 struct adv76xx_state *state; 3029 struct v4l2_ctrl_handler *hdl; 3030 struct v4l2_ctrl *ctrl; 3031 struct v4l2_subdev *sd; 3032 unsigned int i; 3033 unsigned int val, val2; 3034 int err; 3035 3036 /* Check if the adapter supports the needed features */ 3037 if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA)) 3038 return -EIO; 3039 v4l_dbg(1, debug, client, "detecting adv76xx client on address 0x%x\n", 3040 client->addr << 1); 3041 3042 state = devm_kzalloc(&client->dev, sizeof(*state), GFP_KERNEL); 3043 if (!state) { 3044 v4l_err(client, "Could not allocate adv76xx_state memory!\n"); 3045 return -ENOMEM; 3046 } 3047 3048 state->i2c_clients[ADV76XX_PAGE_IO] = client; 3049 3050 /* initialize variables */ 3051 state->restart_stdi_once = true; 3052 state->selected_input = ~0; 3053 3054 if (IS_ENABLED(CONFIG_OF) && client->dev.of_node) { 3055 const struct of_device_id *oid; 3056 3057 oid = of_match_node(adv76xx_of_id, client->dev.of_node); 3058 state->info = oid->data; 3059 3060 err = adv76xx_parse_dt(state); 3061 if (err < 0) { 3062 v4l_err(client, "DT parsing error\n"); 3063 return err; 3064 } 3065 } else if (client->dev.platform_data) { 3066 struct adv76xx_platform_data *pdata = client->dev.platform_data; 3067 3068 state->info = (const struct adv76xx_chip_info *)id->driver_data; 3069 state->pdata = *pdata; 3070 } else { 3071 v4l_err(client, "No platform data!\n"); 3072 return -ENODEV; 3073 } 3074 3075 /* Request GPIOs. */ 3076 for (i = 0; i < state->info->num_dv_ports; ++i) { 3077 state->hpd_gpio[i] = 3078 devm_gpiod_get_index_optional(&client->dev, "hpd", i, 3079 GPIOD_OUT_LOW); 3080 if (IS_ERR(state->hpd_gpio[i])) 3081 return PTR_ERR(state->hpd_gpio[i]); 3082 3083 if (state->hpd_gpio[i]) 3084 v4l_info(client, "Handling HPD %u GPIO\n", i); 3085 } 3086 3087 state->timings = cea640x480; 3088 state->format = adv76xx_format_info(state, MEDIA_BUS_FMT_YUYV8_2X8); 3089 3090 sd = &state->sd; 3091 v4l2_i2c_subdev_init(sd, client, &adv76xx_ops); 3092 snprintf(sd->name, sizeof(sd->name), "%s %d-%04x", 3093 id->name, i2c_adapter_id(client->adapter), 3094 client->addr); 3095 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS; 3096 3097 /* Configure IO Regmap region */ 3098 err = configure_regmap(state, ADV76XX_PAGE_IO); 3099 3100 if (err) { 3101 v4l2_err(sd, "Error configuring IO regmap region\n"); 3102 return -ENODEV; 3103 } 3104 3105 /* 3106 * Verify that the chip is present. On ADV7604 the RD_INFO register only 3107 * identifies the revision, while on ADV7611 it identifies the model as 3108 * well. Use the HDMI slave address on ADV7604 and RD_INFO on ADV7611. 3109 */ 3110 switch (state->info->type) { 3111 case ADV7604: 3112 err = regmap_read(state->regmap[ADV76XX_PAGE_IO], 0xfb, &val); 3113 if (err) { 3114 v4l2_err(sd, "Error %d reading IO Regmap\n", err); 3115 return -ENODEV; 3116 } 3117 if (val != 0x68) { 3118 v4l2_err(sd, "not an adv7604 on address 0x%x\n", 3119 client->addr << 1); 3120 return -ENODEV; 3121 } 3122 break; 3123 case ADV7611: 3124 case ADV7612: 3125 err = regmap_read(state->regmap[ADV76XX_PAGE_IO], 3126 0xea, 3127 &val); 3128 if (err) { 3129 v4l2_err(sd, "Error %d reading IO Regmap\n", err); 3130 return -ENODEV; 3131 } 3132 val2 = val << 8; 3133 err = regmap_read(state->regmap[ADV76XX_PAGE_IO], 3134 0xeb, 3135 &val); 3136 if (err) { 3137 v4l2_err(sd, "Error %d reading IO Regmap\n", err); 3138 return -ENODEV; 3139 } 3140 val |= val2; 3141 if ((state->info->type == ADV7611 && val != 0x2051) || 3142 (state->info->type == ADV7612 && val != 0x2041)) { 3143 v4l2_err(sd, "not an adv761x on address 0x%x\n", 3144 client->addr << 1); 3145 return -ENODEV; 3146 } 3147 break; 3148 } 3149 3150 /* control handlers */ 3151 hdl = &state->hdl; 3152 v4l2_ctrl_handler_init(hdl, adv76xx_has_afe(state) ? 9 : 8); 3153 3154 v4l2_ctrl_new_std(hdl, &adv76xx_ctrl_ops, 3155 V4L2_CID_BRIGHTNESS, -128, 127, 1, 0); 3156 v4l2_ctrl_new_std(hdl, &adv76xx_ctrl_ops, 3157 V4L2_CID_CONTRAST, 0, 255, 1, 128); 3158 v4l2_ctrl_new_std(hdl, &adv76xx_ctrl_ops, 3159 V4L2_CID_SATURATION, 0, 255, 1, 128); 3160 v4l2_ctrl_new_std(hdl, &adv76xx_ctrl_ops, 3161 V4L2_CID_HUE, 0, 128, 1, 0); 3162 ctrl = v4l2_ctrl_new_std_menu(hdl, &adv76xx_ctrl_ops, 3163 V4L2_CID_DV_RX_IT_CONTENT_TYPE, V4L2_DV_IT_CONTENT_TYPE_NO_ITC, 3164 0, V4L2_DV_IT_CONTENT_TYPE_NO_ITC); 3165 if (ctrl) 3166 ctrl->flags |= V4L2_CTRL_FLAG_VOLATILE; 3167 3168 state->detect_tx_5v_ctrl = v4l2_ctrl_new_std(hdl, NULL, 3169 V4L2_CID_DV_RX_POWER_PRESENT, 0, 3170 (1 << state->info->num_dv_ports) - 1, 0, 0); 3171 state->rgb_quantization_range_ctrl = 3172 v4l2_ctrl_new_std_menu(hdl, &adv76xx_ctrl_ops, 3173 V4L2_CID_DV_RX_RGB_RANGE, V4L2_DV_RGB_RANGE_FULL, 3174 0, V4L2_DV_RGB_RANGE_AUTO); 3175 3176 /* custom controls */ 3177 if (adv76xx_has_afe(state)) 3178 state->analog_sampling_phase_ctrl = 3179 v4l2_ctrl_new_custom(hdl, &adv7604_ctrl_analog_sampling_phase, NULL); 3180 state->free_run_color_manual_ctrl = 3181 v4l2_ctrl_new_custom(hdl, &adv76xx_ctrl_free_run_color_manual, NULL); 3182 state->free_run_color_ctrl = 3183 v4l2_ctrl_new_custom(hdl, &adv76xx_ctrl_free_run_color, NULL); 3184 3185 sd->ctrl_handler = hdl; 3186 if (hdl->error) { 3187 err = hdl->error; 3188 goto err_hdl; 3189 } 3190 if (adv76xx_s_detect_tx_5v_ctrl(sd)) { 3191 err = -ENODEV; 3192 goto err_hdl; 3193 } 3194 3195 for (i = 1; i < ADV76XX_PAGE_MAX; ++i) { 3196 if (!(BIT(i) & state->info->page_mask)) 3197 continue; 3198 3199 state->i2c_clients[i] = 3200 adv76xx_dummy_client(sd, state->pdata.i2c_addresses[i], 3201 0xf2 + i); 3202 if (state->i2c_clients[i] == NULL) { 3203 err = -ENOMEM; 3204 v4l2_err(sd, "failed to create i2c client %u\n", i); 3205 goto err_i2c; 3206 } 3207 } 3208 3209 /* work queues */ 3210 state->work_queues = create_singlethread_workqueue(client->name); 3211 if (!state->work_queues) { 3212 v4l2_err(sd, "Could not create work queue\n"); 3213 err = -ENOMEM; 3214 goto err_i2c; 3215 } 3216 3217 INIT_DELAYED_WORK(&state->delayed_work_enable_hotplug, 3218 adv76xx_delayed_work_enable_hotplug); 3219 3220 state->source_pad = state->info->num_dv_ports 3221 + (state->info->has_afe ? 2 : 0); 3222 for (i = 0; i < state->source_pad; ++i) 3223 state->pads[i].flags = MEDIA_PAD_FL_SINK; 3224 state->pads[state->source_pad].flags = MEDIA_PAD_FL_SOURCE; 3225 3226 err = media_entity_pads_init(&sd->entity, state->source_pad + 1, 3227 state->pads); 3228 if (err) 3229 goto err_work_queues; 3230 3231 /* Configure regmaps */ 3232 err = configure_regmaps(state); 3233 if (err) 3234 goto err_entity; 3235 3236 err = adv76xx_core_init(sd); 3237 if (err) 3238 goto err_entity; 3239 v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name, 3240 client->addr << 1, client->adapter->name); 3241 3242 err = v4l2_async_register_subdev(sd); 3243 if (err) 3244 goto err_entity; 3245 3246 return 0; 3247 3248 err_entity: 3249 media_entity_cleanup(&sd->entity); 3250 err_work_queues: 3251 cancel_delayed_work(&state->delayed_work_enable_hotplug); 3252 destroy_workqueue(state->work_queues); 3253 err_i2c: 3254 adv76xx_unregister_clients(state); 3255 err_hdl: 3256 v4l2_ctrl_handler_free(hdl); 3257 return err; 3258 } 3259 3260 /* ----------------------------------------------------------------------- */ 3261 3262 static int adv76xx_remove(struct i2c_client *client) 3263 { 3264 struct v4l2_subdev *sd = i2c_get_clientdata(client); 3265 struct adv76xx_state *state = to_state(sd); 3266 3267 cancel_delayed_work(&state->delayed_work_enable_hotplug); 3268 destroy_workqueue(state->work_queues); 3269 v4l2_async_unregister_subdev(sd); 3270 media_entity_cleanup(&sd->entity); 3271 adv76xx_unregister_clients(to_state(sd)); 3272 v4l2_ctrl_handler_free(sd->ctrl_handler); 3273 return 0; 3274 } 3275 3276 /* ----------------------------------------------------------------------- */ 3277 3278 static struct i2c_driver adv76xx_driver = { 3279 .driver = { 3280 .name = "adv7604", 3281 .of_match_table = of_match_ptr(adv76xx_of_id), 3282 }, 3283 .probe = adv76xx_probe, 3284 .remove = adv76xx_remove, 3285 .id_table = adv76xx_i2c_id, 3286 }; 3287 3288 module_i2c_driver(adv76xx_driver); 3289