1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * adv7604 - Analog Devices ADV7604 video decoder driver 4 * 5 * Copyright 2012 Cisco Systems, Inc. and/or its affiliates. All rights reserved. 6 * 7 */ 8 9 /* 10 * References (c = chapter, p = page): 11 * REF_01 - Analog devices, ADV7604, Register Settings Recommendations, 12 * Revision 2.5, June 2010 13 * REF_02 - Analog devices, Register map documentation, Documentation of 14 * the register maps, Software manual, Rev. F, June 2010 15 * REF_03 - Analog devices, ADV7604, Hardware Manual, Rev. F, August 2010 16 */ 17 18 #include <linux/delay.h> 19 #include <linux/gpio/consumer.h> 20 #include <linux/hdmi.h> 21 #include <linux/i2c.h> 22 #include <linux/kernel.h> 23 #include <linux/module.h> 24 #include <linux/of_graph.h> 25 #include <linux/slab.h> 26 #include <linux/v4l2-dv-timings.h> 27 #include <linux/videodev2.h> 28 #include <linux/workqueue.h> 29 #include <linux/regmap.h> 30 #include <linux/interrupt.h> 31 32 #include <media/i2c/adv7604.h> 33 #include <media/cec.h> 34 #include <media/v4l2-ctrls.h> 35 #include <media/v4l2-device.h> 36 #include <media/v4l2-event.h> 37 #include <media/v4l2-dv-timings.h> 38 #include <media/v4l2-fwnode.h> 39 40 static int debug; 41 module_param(debug, int, 0644); 42 MODULE_PARM_DESC(debug, "debug level (0-2)"); 43 44 MODULE_DESCRIPTION("Analog Devices ADV7604 video decoder driver"); 45 MODULE_AUTHOR("Hans Verkuil <hans.verkuil@cisco.com>"); 46 MODULE_AUTHOR("Mats Randgaard <mats.randgaard@cisco.com>"); 47 MODULE_LICENSE("GPL"); 48 49 /* ADV7604 system clock frequency */ 50 #define ADV76XX_FSC (28636360) 51 52 #define ADV76XX_RGB_OUT (1 << 1) 53 54 #define ADV76XX_OP_FORMAT_SEL_8BIT (0 << 0) 55 #define ADV7604_OP_FORMAT_SEL_10BIT (1 << 0) 56 #define ADV76XX_OP_FORMAT_SEL_12BIT (2 << 0) 57 58 #define ADV76XX_OP_MODE_SEL_SDR_422 (0 << 5) 59 #define ADV7604_OP_MODE_SEL_DDR_422 (1 << 5) 60 #define ADV76XX_OP_MODE_SEL_SDR_444 (2 << 5) 61 #define ADV7604_OP_MODE_SEL_DDR_444 (3 << 5) 62 #define ADV76XX_OP_MODE_SEL_SDR_422_2X (4 << 5) 63 #define ADV7604_OP_MODE_SEL_ADI_CM (5 << 5) 64 65 #define ADV76XX_OP_CH_SEL_GBR (0 << 5) 66 #define ADV76XX_OP_CH_SEL_GRB (1 << 5) 67 #define ADV76XX_OP_CH_SEL_BGR (2 << 5) 68 #define ADV76XX_OP_CH_SEL_RGB (3 << 5) 69 #define ADV76XX_OP_CH_SEL_BRG (4 << 5) 70 #define ADV76XX_OP_CH_SEL_RBG (5 << 5) 71 72 #define ADV76XX_OP_SWAP_CB_CR (1 << 0) 73 74 #define ADV76XX_MAX_ADDRS (3) 75 76 enum adv76xx_type { 77 ADV7604, 78 ADV7611, 79 ADV7612, 80 }; 81 82 struct adv76xx_reg_seq { 83 unsigned int reg; 84 u8 val; 85 }; 86 87 struct adv76xx_format_info { 88 u32 code; 89 u8 op_ch_sel; 90 bool rgb_out; 91 bool swap_cb_cr; 92 u8 op_format_sel; 93 }; 94 95 struct adv76xx_cfg_read_infoframe { 96 const char *desc; 97 u8 present_mask; 98 u8 head_addr; 99 u8 payload_addr; 100 }; 101 102 struct adv76xx_chip_info { 103 enum adv76xx_type type; 104 105 bool has_afe; 106 unsigned int max_port; 107 unsigned int num_dv_ports; 108 109 unsigned int edid_enable_reg; 110 unsigned int edid_status_reg; 111 unsigned int lcf_reg; 112 113 unsigned int cable_det_mask; 114 unsigned int tdms_lock_mask; 115 unsigned int fmt_change_digital_mask; 116 unsigned int cp_csc; 117 118 unsigned int cec_irq_status; 119 unsigned int cec_rx_enable; 120 unsigned int cec_rx_enable_mask; 121 bool cec_irq_swap; 122 123 const struct adv76xx_format_info *formats; 124 unsigned int nformats; 125 126 void (*set_termination)(struct v4l2_subdev *sd, bool enable); 127 void (*setup_irqs)(struct v4l2_subdev *sd); 128 unsigned int (*read_hdmi_pixelclock)(struct v4l2_subdev *sd); 129 unsigned int (*read_cable_det)(struct v4l2_subdev *sd); 130 131 /* 0 = AFE, 1 = HDMI */ 132 const struct adv76xx_reg_seq *recommended_settings[2]; 133 unsigned int num_recommended_settings[2]; 134 135 unsigned long page_mask; 136 137 /* Masks for timings */ 138 unsigned int linewidth_mask; 139 unsigned int field0_height_mask; 140 unsigned int field1_height_mask; 141 unsigned int hfrontporch_mask; 142 unsigned int hsync_mask; 143 unsigned int hbackporch_mask; 144 unsigned int field0_vfrontporch_mask; 145 unsigned int field1_vfrontporch_mask; 146 unsigned int field0_vsync_mask; 147 unsigned int field1_vsync_mask; 148 unsigned int field0_vbackporch_mask; 149 unsigned int field1_vbackporch_mask; 150 }; 151 152 /* 153 ********************************************************************** 154 * 155 * Arrays with configuration parameters for the ADV7604 156 * 157 ********************************************************************** 158 */ 159 160 struct adv76xx_state { 161 const struct adv76xx_chip_info *info; 162 struct adv76xx_platform_data pdata; 163 164 struct gpio_desc *hpd_gpio[4]; 165 struct gpio_desc *reset_gpio; 166 167 struct v4l2_subdev sd; 168 struct media_pad pads[ADV76XX_PAD_MAX]; 169 unsigned int source_pad; 170 171 struct v4l2_ctrl_handler hdl; 172 173 enum adv76xx_pad selected_input; 174 175 struct v4l2_dv_timings timings; 176 const struct adv76xx_format_info *format; 177 178 struct { 179 u8 edid[256]; 180 u32 present; 181 unsigned blocks; 182 } edid; 183 u16 spa_port_a[2]; 184 struct v4l2_fract aspect_ratio; 185 u32 rgb_quantization_range; 186 struct delayed_work delayed_work_enable_hotplug; 187 bool restart_stdi_once; 188 189 /* CEC */ 190 struct cec_adapter *cec_adap; 191 u8 cec_addr[ADV76XX_MAX_ADDRS]; 192 u8 cec_valid_addrs; 193 bool cec_enabled_adap; 194 195 /* i2c clients */ 196 struct i2c_client *i2c_clients[ADV76XX_PAGE_MAX]; 197 198 /* Regmaps */ 199 struct regmap *regmap[ADV76XX_PAGE_MAX]; 200 201 /* controls */ 202 struct v4l2_ctrl *detect_tx_5v_ctrl; 203 struct v4l2_ctrl *analog_sampling_phase_ctrl; 204 struct v4l2_ctrl *free_run_color_manual_ctrl; 205 struct v4l2_ctrl *free_run_color_ctrl; 206 struct v4l2_ctrl *rgb_quantization_range_ctrl; 207 }; 208 209 static bool adv76xx_has_afe(struct adv76xx_state *state) 210 { 211 return state->info->has_afe; 212 } 213 214 /* Unsupported timings. This device cannot support 720p30. */ 215 static const struct v4l2_dv_timings adv76xx_timings_exceptions[] = { 216 V4L2_DV_BT_CEA_1280X720P30, 217 { } 218 }; 219 220 static bool adv76xx_check_dv_timings(const struct v4l2_dv_timings *t, void *hdl) 221 { 222 int i; 223 224 for (i = 0; adv76xx_timings_exceptions[i].bt.width; i++) 225 if (v4l2_match_dv_timings(t, adv76xx_timings_exceptions + i, 0, false)) 226 return false; 227 return true; 228 } 229 230 struct adv76xx_video_standards { 231 struct v4l2_dv_timings timings; 232 u8 vid_std; 233 u8 v_freq; 234 }; 235 236 /* sorted by number of lines */ 237 static const struct adv76xx_video_standards adv7604_prim_mode_comp[] = { 238 /* { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 }, TODO flickering */ 239 { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 }, 240 { V4L2_DV_BT_CEA_1280X720P50, 0x19, 0x01 }, 241 { V4L2_DV_BT_CEA_1280X720P60, 0x19, 0x00 }, 242 { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 }, 243 { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 }, 244 { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 }, 245 { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 }, 246 { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 }, 247 /* TODO add 1920x1080P60_RB (CVT timing) */ 248 { }, 249 }; 250 251 /* sorted by number of lines */ 252 static const struct adv76xx_video_standards adv7604_prim_mode_gr[] = { 253 { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 }, 254 { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 }, 255 { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 }, 256 { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 }, 257 { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 }, 258 { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 }, 259 { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 }, 260 { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 }, 261 { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 }, 262 { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 }, 263 { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 }, 264 { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 }, 265 { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 }, 266 { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 }, 267 { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 }, 268 { V4L2_DV_BT_DMT_1360X768P60, 0x12, 0x00 }, 269 { V4L2_DV_BT_DMT_1366X768P60, 0x13, 0x00 }, 270 { V4L2_DV_BT_DMT_1400X1050P60, 0x14, 0x00 }, 271 { V4L2_DV_BT_DMT_1400X1050P75, 0x15, 0x00 }, 272 { V4L2_DV_BT_DMT_1600X1200P60, 0x16, 0x00 }, /* TODO not tested */ 273 /* TODO add 1600X1200P60_RB (not a DMT timing) */ 274 { V4L2_DV_BT_DMT_1680X1050P60, 0x18, 0x00 }, 275 { V4L2_DV_BT_DMT_1920X1200P60_RB, 0x19, 0x00 }, /* TODO not tested */ 276 { }, 277 }; 278 279 /* sorted by number of lines */ 280 static const struct adv76xx_video_standards adv76xx_prim_mode_hdmi_comp[] = { 281 { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 }, 282 { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 }, 283 { V4L2_DV_BT_CEA_1280X720P50, 0x13, 0x01 }, 284 { V4L2_DV_BT_CEA_1280X720P60, 0x13, 0x00 }, 285 { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 }, 286 { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 }, 287 { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 }, 288 { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 }, 289 { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 }, 290 { }, 291 }; 292 293 /* sorted by number of lines */ 294 static const struct adv76xx_video_standards adv76xx_prim_mode_hdmi_gr[] = { 295 { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 }, 296 { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 }, 297 { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 }, 298 { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 }, 299 { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 }, 300 { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 }, 301 { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 }, 302 { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 }, 303 { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 }, 304 { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 }, 305 { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 }, 306 { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 }, 307 { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 }, 308 { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 }, 309 { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 }, 310 { }, 311 }; 312 313 static const struct v4l2_event adv76xx_ev_fmt = { 314 .type = V4L2_EVENT_SOURCE_CHANGE, 315 .u.src_change.changes = V4L2_EVENT_SRC_CH_RESOLUTION, 316 }; 317 318 /* ----------------------------------------------------------------------- */ 319 320 static inline struct adv76xx_state *to_state(struct v4l2_subdev *sd) 321 { 322 return container_of(sd, struct adv76xx_state, sd); 323 } 324 325 static inline unsigned htotal(const struct v4l2_bt_timings *t) 326 { 327 return V4L2_DV_BT_FRAME_WIDTH(t); 328 } 329 330 static inline unsigned vtotal(const struct v4l2_bt_timings *t) 331 { 332 return V4L2_DV_BT_FRAME_HEIGHT(t); 333 } 334 335 /* ----------------------------------------------------------------------- */ 336 337 static int adv76xx_read_check(struct adv76xx_state *state, 338 int client_page, u8 reg) 339 { 340 struct i2c_client *client = state->i2c_clients[client_page]; 341 int err; 342 unsigned int val; 343 344 err = regmap_read(state->regmap[client_page], reg, &val); 345 346 if (err) { 347 v4l_err(client, "error reading %02x, %02x\n", 348 client->addr, reg); 349 return err; 350 } 351 return val; 352 } 353 354 /* adv76xx_write_block(): Write raw data with a maximum of I2C_SMBUS_BLOCK_MAX 355 * size to one or more registers. 356 * 357 * A value of zero will be returned on success, a negative errno will 358 * be returned in error cases. 359 */ 360 static int adv76xx_write_block(struct adv76xx_state *state, int client_page, 361 unsigned int init_reg, const void *val, 362 size_t val_len) 363 { 364 struct regmap *regmap = state->regmap[client_page]; 365 366 if (val_len > I2C_SMBUS_BLOCK_MAX) 367 val_len = I2C_SMBUS_BLOCK_MAX; 368 369 return regmap_raw_write(regmap, init_reg, val, val_len); 370 } 371 372 /* ----------------------------------------------------------------------- */ 373 374 static inline int io_read(struct v4l2_subdev *sd, u8 reg) 375 { 376 struct adv76xx_state *state = to_state(sd); 377 378 return adv76xx_read_check(state, ADV76XX_PAGE_IO, reg); 379 } 380 381 static inline int io_write(struct v4l2_subdev *sd, u8 reg, u8 val) 382 { 383 struct adv76xx_state *state = to_state(sd); 384 385 return regmap_write(state->regmap[ADV76XX_PAGE_IO], reg, val); 386 } 387 388 static inline int io_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, 389 u8 val) 390 { 391 return io_write(sd, reg, (io_read(sd, reg) & ~mask) | val); 392 } 393 394 static inline int avlink_read(struct v4l2_subdev *sd, u8 reg) 395 { 396 struct adv76xx_state *state = to_state(sd); 397 398 return adv76xx_read_check(state, ADV7604_PAGE_AVLINK, reg); 399 } 400 401 static inline int avlink_write(struct v4l2_subdev *sd, u8 reg, u8 val) 402 { 403 struct adv76xx_state *state = to_state(sd); 404 405 return regmap_write(state->regmap[ADV7604_PAGE_AVLINK], reg, val); 406 } 407 408 static inline int cec_read(struct v4l2_subdev *sd, u8 reg) 409 { 410 struct adv76xx_state *state = to_state(sd); 411 412 return adv76xx_read_check(state, ADV76XX_PAGE_CEC, reg); 413 } 414 415 static inline int cec_write(struct v4l2_subdev *sd, u8 reg, u8 val) 416 { 417 struct adv76xx_state *state = to_state(sd); 418 419 return regmap_write(state->regmap[ADV76XX_PAGE_CEC], reg, val); 420 } 421 422 static inline int cec_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, 423 u8 val) 424 { 425 return cec_write(sd, reg, (cec_read(sd, reg) & ~mask) | val); 426 } 427 428 static inline int infoframe_read(struct v4l2_subdev *sd, u8 reg) 429 { 430 struct adv76xx_state *state = to_state(sd); 431 432 return adv76xx_read_check(state, ADV76XX_PAGE_INFOFRAME, reg); 433 } 434 435 static inline int infoframe_write(struct v4l2_subdev *sd, u8 reg, u8 val) 436 { 437 struct adv76xx_state *state = to_state(sd); 438 439 return regmap_write(state->regmap[ADV76XX_PAGE_INFOFRAME], reg, val); 440 } 441 442 static inline int afe_read(struct v4l2_subdev *sd, u8 reg) 443 { 444 struct adv76xx_state *state = to_state(sd); 445 446 return adv76xx_read_check(state, ADV76XX_PAGE_AFE, reg); 447 } 448 449 static inline int afe_write(struct v4l2_subdev *sd, u8 reg, u8 val) 450 { 451 struct adv76xx_state *state = to_state(sd); 452 453 return regmap_write(state->regmap[ADV76XX_PAGE_AFE], reg, val); 454 } 455 456 static inline int rep_read(struct v4l2_subdev *sd, u8 reg) 457 { 458 struct adv76xx_state *state = to_state(sd); 459 460 return adv76xx_read_check(state, ADV76XX_PAGE_REP, reg); 461 } 462 463 static inline int rep_write(struct v4l2_subdev *sd, u8 reg, u8 val) 464 { 465 struct adv76xx_state *state = to_state(sd); 466 467 return regmap_write(state->regmap[ADV76XX_PAGE_REP], reg, val); 468 } 469 470 static inline int rep_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) 471 { 472 return rep_write(sd, reg, (rep_read(sd, reg) & ~mask) | val); 473 } 474 475 static inline int edid_read(struct v4l2_subdev *sd, u8 reg) 476 { 477 struct adv76xx_state *state = to_state(sd); 478 479 return adv76xx_read_check(state, ADV76XX_PAGE_EDID, reg); 480 } 481 482 static inline int edid_write(struct v4l2_subdev *sd, u8 reg, u8 val) 483 { 484 struct adv76xx_state *state = to_state(sd); 485 486 return regmap_write(state->regmap[ADV76XX_PAGE_EDID], reg, val); 487 } 488 489 static inline int edid_write_block(struct v4l2_subdev *sd, 490 unsigned int total_len, const u8 *val) 491 { 492 struct adv76xx_state *state = to_state(sd); 493 int err = 0; 494 int i = 0; 495 int len = 0; 496 497 v4l2_dbg(2, debug, sd, "%s: write EDID block (%d byte)\n", 498 __func__, total_len); 499 500 while (!err && i < total_len) { 501 len = (total_len - i) > I2C_SMBUS_BLOCK_MAX ? 502 I2C_SMBUS_BLOCK_MAX : 503 (total_len - i); 504 505 err = adv76xx_write_block(state, ADV76XX_PAGE_EDID, 506 i, val + i, len); 507 i += len; 508 } 509 510 return err; 511 } 512 513 static void adv76xx_set_hpd(struct adv76xx_state *state, unsigned int hpd) 514 { 515 const struct adv76xx_chip_info *info = state->info; 516 unsigned int i; 517 518 if (info->type == ADV7604) { 519 for (i = 0; i < state->info->num_dv_ports; ++i) 520 gpiod_set_value_cansleep(state->hpd_gpio[i], hpd & BIT(i)); 521 } else { 522 for (i = 0; i < state->info->num_dv_ports; ++i) 523 io_write_clr_set(&state->sd, 0x20, 0x80 >> i, 524 (!!(hpd & BIT(i))) << (7 - i)); 525 } 526 527 v4l2_subdev_notify(&state->sd, ADV76XX_HOTPLUG, &hpd); 528 } 529 530 static void adv76xx_delayed_work_enable_hotplug(struct work_struct *work) 531 { 532 struct delayed_work *dwork = to_delayed_work(work); 533 struct adv76xx_state *state = container_of(dwork, struct adv76xx_state, 534 delayed_work_enable_hotplug); 535 struct v4l2_subdev *sd = &state->sd; 536 537 v4l2_dbg(2, debug, sd, "%s: enable hotplug\n", __func__); 538 539 adv76xx_set_hpd(state, state->edid.present); 540 } 541 542 static inline int hdmi_read(struct v4l2_subdev *sd, u8 reg) 543 { 544 struct adv76xx_state *state = to_state(sd); 545 546 return adv76xx_read_check(state, ADV76XX_PAGE_HDMI, reg); 547 } 548 549 static u16 hdmi_read16(struct v4l2_subdev *sd, u8 reg, u16 mask) 550 { 551 return ((hdmi_read(sd, reg) << 8) | hdmi_read(sd, reg + 1)) & mask; 552 } 553 554 static inline int hdmi_write(struct v4l2_subdev *sd, u8 reg, u8 val) 555 { 556 struct adv76xx_state *state = to_state(sd); 557 558 return regmap_write(state->regmap[ADV76XX_PAGE_HDMI], reg, val); 559 } 560 561 static inline int hdmi_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) 562 { 563 return hdmi_write(sd, reg, (hdmi_read(sd, reg) & ~mask) | val); 564 } 565 566 static inline int test_write(struct v4l2_subdev *sd, u8 reg, u8 val) 567 { 568 struct adv76xx_state *state = to_state(sd); 569 570 return regmap_write(state->regmap[ADV76XX_PAGE_TEST], reg, val); 571 } 572 573 static inline int cp_read(struct v4l2_subdev *sd, u8 reg) 574 { 575 struct adv76xx_state *state = to_state(sd); 576 577 return adv76xx_read_check(state, ADV76XX_PAGE_CP, reg); 578 } 579 580 static u16 cp_read16(struct v4l2_subdev *sd, u8 reg, u16 mask) 581 { 582 return ((cp_read(sd, reg) << 8) | cp_read(sd, reg + 1)) & mask; 583 } 584 585 static inline int cp_write(struct v4l2_subdev *sd, u8 reg, u8 val) 586 { 587 struct adv76xx_state *state = to_state(sd); 588 589 return regmap_write(state->regmap[ADV76XX_PAGE_CP], reg, val); 590 } 591 592 static inline int cp_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) 593 { 594 return cp_write(sd, reg, (cp_read(sd, reg) & ~mask) | val); 595 } 596 597 static inline int vdp_read(struct v4l2_subdev *sd, u8 reg) 598 { 599 struct adv76xx_state *state = to_state(sd); 600 601 return adv76xx_read_check(state, ADV7604_PAGE_VDP, reg); 602 } 603 604 static inline int vdp_write(struct v4l2_subdev *sd, u8 reg, u8 val) 605 { 606 struct adv76xx_state *state = to_state(sd); 607 608 return regmap_write(state->regmap[ADV7604_PAGE_VDP], reg, val); 609 } 610 611 #define ADV76XX_REG(page, offset) (((page) << 8) | (offset)) 612 #define ADV76XX_REG_SEQ_TERM 0xffff 613 614 #ifdef CONFIG_VIDEO_ADV_DEBUG 615 static int adv76xx_read_reg(struct v4l2_subdev *sd, unsigned int reg) 616 { 617 struct adv76xx_state *state = to_state(sd); 618 unsigned int page = reg >> 8; 619 unsigned int val; 620 int err; 621 622 if (page >= ADV76XX_PAGE_MAX || !(BIT(page) & state->info->page_mask)) 623 return -EINVAL; 624 625 reg &= 0xff; 626 err = regmap_read(state->regmap[page], reg, &val); 627 628 return err ? err : val; 629 } 630 #endif 631 632 static int adv76xx_write_reg(struct v4l2_subdev *sd, unsigned int reg, u8 val) 633 { 634 struct adv76xx_state *state = to_state(sd); 635 unsigned int page = reg >> 8; 636 637 if (page >= ADV76XX_PAGE_MAX || !(BIT(page) & state->info->page_mask)) 638 return -EINVAL; 639 640 reg &= 0xff; 641 642 return regmap_write(state->regmap[page], reg, val); 643 } 644 645 static void adv76xx_write_reg_seq(struct v4l2_subdev *sd, 646 const struct adv76xx_reg_seq *reg_seq) 647 { 648 unsigned int i; 649 650 for (i = 0; reg_seq[i].reg != ADV76XX_REG_SEQ_TERM; i++) 651 adv76xx_write_reg(sd, reg_seq[i].reg, reg_seq[i].val); 652 } 653 654 /* ----------------------------------------------------------------------------- 655 * Format helpers 656 */ 657 658 static const struct adv76xx_format_info adv7604_formats[] = { 659 { MEDIA_BUS_FMT_RGB888_1X24, ADV76XX_OP_CH_SEL_RGB, true, false, 660 ADV76XX_OP_MODE_SEL_SDR_444 | ADV76XX_OP_FORMAT_SEL_8BIT }, 661 { MEDIA_BUS_FMT_YUYV8_2X8, ADV76XX_OP_CH_SEL_RGB, false, false, 662 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT }, 663 { MEDIA_BUS_FMT_YVYU8_2X8, ADV76XX_OP_CH_SEL_RGB, false, true, 664 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT }, 665 { MEDIA_BUS_FMT_YUYV10_2X10, ADV76XX_OP_CH_SEL_RGB, false, false, 666 ADV76XX_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_10BIT }, 667 { MEDIA_BUS_FMT_YVYU10_2X10, ADV76XX_OP_CH_SEL_RGB, false, true, 668 ADV76XX_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_10BIT }, 669 { MEDIA_BUS_FMT_YUYV12_2X12, ADV76XX_OP_CH_SEL_RGB, false, false, 670 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_12BIT }, 671 { MEDIA_BUS_FMT_YVYU12_2X12, ADV76XX_OP_CH_SEL_RGB, false, true, 672 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_12BIT }, 673 { MEDIA_BUS_FMT_UYVY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, false, 674 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT }, 675 { MEDIA_BUS_FMT_VYUY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, true, 676 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT }, 677 { MEDIA_BUS_FMT_YUYV8_1X16, ADV76XX_OP_CH_SEL_RGB, false, false, 678 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT }, 679 { MEDIA_BUS_FMT_YVYU8_1X16, ADV76XX_OP_CH_SEL_RGB, false, true, 680 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT }, 681 { MEDIA_BUS_FMT_UYVY10_1X20, ADV76XX_OP_CH_SEL_RBG, false, false, 682 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT }, 683 { MEDIA_BUS_FMT_VYUY10_1X20, ADV76XX_OP_CH_SEL_RBG, false, true, 684 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT }, 685 { MEDIA_BUS_FMT_YUYV10_1X20, ADV76XX_OP_CH_SEL_RGB, false, false, 686 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT }, 687 { MEDIA_BUS_FMT_YVYU10_1X20, ADV76XX_OP_CH_SEL_RGB, false, true, 688 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT }, 689 { MEDIA_BUS_FMT_UYVY12_1X24, ADV76XX_OP_CH_SEL_RBG, false, false, 690 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT }, 691 { MEDIA_BUS_FMT_VYUY12_1X24, ADV76XX_OP_CH_SEL_RBG, false, true, 692 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT }, 693 { MEDIA_BUS_FMT_YUYV12_1X24, ADV76XX_OP_CH_SEL_RGB, false, false, 694 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT }, 695 { MEDIA_BUS_FMT_YVYU12_1X24, ADV76XX_OP_CH_SEL_RGB, false, true, 696 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT }, 697 }; 698 699 static const struct adv76xx_format_info adv7611_formats[] = { 700 { MEDIA_BUS_FMT_RGB888_1X24, ADV76XX_OP_CH_SEL_RGB, true, false, 701 ADV76XX_OP_MODE_SEL_SDR_444 | ADV76XX_OP_FORMAT_SEL_8BIT }, 702 { MEDIA_BUS_FMT_YUYV8_2X8, ADV76XX_OP_CH_SEL_RGB, false, false, 703 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT }, 704 { MEDIA_BUS_FMT_YVYU8_2X8, ADV76XX_OP_CH_SEL_RGB, false, true, 705 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT }, 706 { MEDIA_BUS_FMT_YUYV12_2X12, ADV76XX_OP_CH_SEL_RGB, false, false, 707 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_12BIT }, 708 { MEDIA_BUS_FMT_YVYU12_2X12, ADV76XX_OP_CH_SEL_RGB, false, true, 709 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_12BIT }, 710 { MEDIA_BUS_FMT_UYVY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, false, 711 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT }, 712 { MEDIA_BUS_FMT_VYUY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, true, 713 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT }, 714 { MEDIA_BUS_FMT_YUYV8_1X16, ADV76XX_OP_CH_SEL_RGB, false, false, 715 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT }, 716 { MEDIA_BUS_FMT_YVYU8_1X16, ADV76XX_OP_CH_SEL_RGB, false, true, 717 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT }, 718 { MEDIA_BUS_FMT_UYVY12_1X24, ADV76XX_OP_CH_SEL_RBG, false, false, 719 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT }, 720 { MEDIA_BUS_FMT_VYUY12_1X24, ADV76XX_OP_CH_SEL_RBG, false, true, 721 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT }, 722 { MEDIA_BUS_FMT_YUYV12_1X24, ADV76XX_OP_CH_SEL_RGB, false, false, 723 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT }, 724 { MEDIA_BUS_FMT_YVYU12_1X24, ADV76XX_OP_CH_SEL_RGB, false, true, 725 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT }, 726 }; 727 728 static const struct adv76xx_format_info adv7612_formats[] = { 729 { MEDIA_BUS_FMT_RGB888_1X24, ADV76XX_OP_CH_SEL_RGB, true, false, 730 ADV76XX_OP_MODE_SEL_SDR_444 | ADV76XX_OP_FORMAT_SEL_8BIT }, 731 { MEDIA_BUS_FMT_YUYV8_2X8, ADV76XX_OP_CH_SEL_RGB, false, false, 732 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT }, 733 { MEDIA_BUS_FMT_YVYU8_2X8, ADV76XX_OP_CH_SEL_RGB, false, true, 734 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT }, 735 { MEDIA_BUS_FMT_UYVY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, false, 736 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT }, 737 { MEDIA_BUS_FMT_VYUY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, true, 738 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT }, 739 { MEDIA_BUS_FMT_YUYV8_1X16, ADV76XX_OP_CH_SEL_RGB, false, false, 740 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT }, 741 { MEDIA_BUS_FMT_YVYU8_1X16, ADV76XX_OP_CH_SEL_RGB, false, true, 742 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT }, 743 }; 744 745 static const struct adv76xx_format_info * 746 adv76xx_format_info(struct adv76xx_state *state, u32 code) 747 { 748 unsigned int i; 749 750 for (i = 0; i < state->info->nformats; ++i) { 751 if (state->info->formats[i].code == code) 752 return &state->info->formats[i]; 753 } 754 755 return NULL; 756 } 757 758 /* ----------------------------------------------------------------------- */ 759 760 static inline bool is_analog_input(struct v4l2_subdev *sd) 761 { 762 struct adv76xx_state *state = to_state(sd); 763 764 return state->selected_input == ADV7604_PAD_VGA_RGB || 765 state->selected_input == ADV7604_PAD_VGA_COMP; 766 } 767 768 static inline bool is_digital_input(struct v4l2_subdev *sd) 769 { 770 struct adv76xx_state *state = to_state(sd); 771 772 return state->selected_input == ADV76XX_PAD_HDMI_PORT_A || 773 state->selected_input == ADV7604_PAD_HDMI_PORT_B || 774 state->selected_input == ADV7604_PAD_HDMI_PORT_C || 775 state->selected_input == ADV7604_PAD_HDMI_PORT_D; 776 } 777 778 static const struct v4l2_dv_timings_cap adv7604_timings_cap_analog = { 779 .type = V4L2_DV_BT_656_1120, 780 /* keep this initialization for compatibility with GCC < 4.4.6 */ 781 .reserved = { 0 }, 782 V4L2_INIT_BT_TIMINGS(640, 1920, 350, 1200, 25000000, 170000000, 783 V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT | 784 V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT, 785 V4L2_DV_BT_CAP_PROGRESSIVE | V4L2_DV_BT_CAP_REDUCED_BLANKING | 786 V4L2_DV_BT_CAP_CUSTOM) 787 }; 788 789 static const struct v4l2_dv_timings_cap adv76xx_timings_cap_digital = { 790 .type = V4L2_DV_BT_656_1120, 791 /* keep this initialization for compatibility with GCC < 4.4.6 */ 792 .reserved = { 0 }, 793 V4L2_INIT_BT_TIMINGS(640, 1920, 350, 1200, 25000000, 225000000, 794 V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT | 795 V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT, 796 V4L2_DV_BT_CAP_PROGRESSIVE | V4L2_DV_BT_CAP_REDUCED_BLANKING | 797 V4L2_DV_BT_CAP_CUSTOM) 798 }; 799 800 /* 801 * Return the DV timings capabilities for the requested sink pad. As a special 802 * case, pad value -1 returns the capabilities for the currently selected input. 803 */ 804 static const struct v4l2_dv_timings_cap * 805 adv76xx_get_dv_timings_cap(struct v4l2_subdev *sd, int pad) 806 { 807 if (pad == -1) { 808 struct adv76xx_state *state = to_state(sd); 809 810 pad = state->selected_input; 811 } 812 813 switch (pad) { 814 case ADV76XX_PAD_HDMI_PORT_A: 815 case ADV7604_PAD_HDMI_PORT_B: 816 case ADV7604_PAD_HDMI_PORT_C: 817 case ADV7604_PAD_HDMI_PORT_D: 818 return &adv76xx_timings_cap_digital; 819 820 case ADV7604_PAD_VGA_RGB: 821 case ADV7604_PAD_VGA_COMP: 822 default: 823 return &adv7604_timings_cap_analog; 824 } 825 } 826 827 828 /* ----------------------------------------------------------------------- */ 829 830 #ifdef CONFIG_VIDEO_ADV_DEBUG 831 static void adv76xx_inv_register(struct v4l2_subdev *sd) 832 { 833 v4l2_info(sd, "0x000-0x0ff: IO Map\n"); 834 v4l2_info(sd, "0x100-0x1ff: AVLink Map\n"); 835 v4l2_info(sd, "0x200-0x2ff: CEC Map\n"); 836 v4l2_info(sd, "0x300-0x3ff: InfoFrame Map\n"); 837 v4l2_info(sd, "0x400-0x4ff: ESDP Map\n"); 838 v4l2_info(sd, "0x500-0x5ff: DPP Map\n"); 839 v4l2_info(sd, "0x600-0x6ff: AFE Map\n"); 840 v4l2_info(sd, "0x700-0x7ff: Repeater Map\n"); 841 v4l2_info(sd, "0x800-0x8ff: EDID Map\n"); 842 v4l2_info(sd, "0x900-0x9ff: HDMI Map\n"); 843 v4l2_info(sd, "0xa00-0xaff: Test Map\n"); 844 v4l2_info(sd, "0xb00-0xbff: CP Map\n"); 845 v4l2_info(sd, "0xc00-0xcff: VDP Map\n"); 846 } 847 848 static int adv76xx_g_register(struct v4l2_subdev *sd, 849 struct v4l2_dbg_register *reg) 850 { 851 int ret; 852 853 ret = adv76xx_read_reg(sd, reg->reg); 854 if (ret < 0) { 855 v4l2_info(sd, "Register %03llx not supported\n", reg->reg); 856 adv76xx_inv_register(sd); 857 return ret; 858 } 859 860 reg->size = 1; 861 reg->val = ret; 862 863 return 0; 864 } 865 866 static int adv76xx_s_register(struct v4l2_subdev *sd, 867 const struct v4l2_dbg_register *reg) 868 { 869 int ret; 870 871 ret = adv76xx_write_reg(sd, reg->reg, reg->val); 872 if (ret < 0) { 873 v4l2_info(sd, "Register %03llx not supported\n", reg->reg); 874 adv76xx_inv_register(sd); 875 return ret; 876 } 877 878 return 0; 879 } 880 #endif 881 882 static unsigned int adv7604_read_cable_det(struct v4l2_subdev *sd) 883 { 884 u8 value = io_read(sd, 0x6f); 885 886 return ((value & 0x10) >> 4) 887 | ((value & 0x08) >> 2) 888 | ((value & 0x04) << 0) 889 | ((value & 0x02) << 2); 890 } 891 892 static unsigned int adv7611_read_cable_det(struct v4l2_subdev *sd) 893 { 894 u8 value = io_read(sd, 0x6f); 895 896 return value & 1; 897 } 898 899 static unsigned int adv7612_read_cable_det(struct v4l2_subdev *sd) 900 { 901 /* Reads CABLE_DET_A_RAW. For input B support, need to 902 * account for bit 7 [MSB] of 0x6a (ie. CABLE_DET_B_RAW) 903 */ 904 u8 value = io_read(sd, 0x6f); 905 906 return value & 1; 907 } 908 909 static int adv76xx_s_detect_tx_5v_ctrl(struct v4l2_subdev *sd) 910 { 911 struct adv76xx_state *state = to_state(sd); 912 const struct adv76xx_chip_info *info = state->info; 913 u16 cable_det = info->read_cable_det(sd); 914 915 return v4l2_ctrl_s_ctrl(state->detect_tx_5v_ctrl, cable_det); 916 } 917 918 static int find_and_set_predefined_video_timings(struct v4l2_subdev *sd, 919 u8 prim_mode, 920 const struct adv76xx_video_standards *predef_vid_timings, 921 const struct v4l2_dv_timings *timings) 922 { 923 int i; 924 925 for (i = 0; predef_vid_timings[i].timings.bt.width; i++) { 926 if (!v4l2_match_dv_timings(timings, &predef_vid_timings[i].timings, 927 is_digital_input(sd) ? 250000 : 1000000, false)) 928 continue; 929 io_write(sd, 0x00, predef_vid_timings[i].vid_std); /* video std */ 930 io_write(sd, 0x01, (predef_vid_timings[i].v_freq << 4) + 931 prim_mode); /* v_freq and prim mode */ 932 return 0; 933 } 934 935 return -1; 936 } 937 938 static int configure_predefined_video_timings(struct v4l2_subdev *sd, 939 struct v4l2_dv_timings *timings) 940 { 941 struct adv76xx_state *state = to_state(sd); 942 int err; 943 944 v4l2_dbg(1, debug, sd, "%s", __func__); 945 946 if (adv76xx_has_afe(state)) { 947 /* reset to default values */ 948 io_write(sd, 0x16, 0x43); 949 io_write(sd, 0x17, 0x5a); 950 } 951 /* disable embedded syncs for auto graphics mode */ 952 cp_write_clr_set(sd, 0x81, 0x10, 0x00); 953 cp_write(sd, 0x8f, 0x00); 954 cp_write(sd, 0x90, 0x00); 955 cp_write(sd, 0xa2, 0x00); 956 cp_write(sd, 0xa3, 0x00); 957 cp_write(sd, 0xa4, 0x00); 958 cp_write(sd, 0xa5, 0x00); 959 cp_write(sd, 0xa6, 0x00); 960 cp_write(sd, 0xa7, 0x00); 961 cp_write(sd, 0xab, 0x00); 962 cp_write(sd, 0xac, 0x00); 963 964 if (is_analog_input(sd)) { 965 err = find_and_set_predefined_video_timings(sd, 966 0x01, adv7604_prim_mode_comp, timings); 967 if (err) 968 err = find_and_set_predefined_video_timings(sd, 969 0x02, adv7604_prim_mode_gr, timings); 970 } else if (is_digital_input(sd)) { 971 err = find_and_set_predefined_video_timings(sd, 972 0x05, adv76xx_prim_mode_hdmi_comp, timings); 973 if (err) 974 err = find_and_set_predefined_video_timings(sd, 975 0x06, adv76xx_prim_mode_hdmi_gr, timings); 976 } else { 977 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n", 978 __func__, state->selected_input); 979 err = -1; 980 } 981 982 983 return err; 984 } 985 986 static void configure_custom_video_timings(struct v4l2_subdev *sd, 987 const struct v4l2_bt_timings *bt) 988 { 989 struct adv76xx_state *state = to_state(sd); 990 u32 width = htotal(bt); 991 u32 height = vtotal(bt); 992 u16 cp_start_sav = bt->hsync + bt->hbackporch - 4; 993 u16 cp_start_eav = width - bt->hfrontporch; 994 u16 cp_start_vbi = height - bt->vfrontporch; 995 u16 cp_end_vbi = bt->vsync + bt->vbackporch; 996 u16 ch1_fr_ll = (((u32)bt->pixelclock / 100) > 0) ? 997 ((width * (ADV76XX_FSC / 100)) / ((u32)bt->pixelclock / 100)) : 0; 998 const u8 pll[2] = { 999 0xc0 | ((width >> 8) & 0x1f), 1000 width & 0xff 1001 }; 1002 1003 v4l2_dbg(2, debug, sd, "%s\n", __func__); 1004 1005 if (is_analog_input(sd)) { 1006 /* auto graphics */ 1007 io_write(sd, 0x00, 0x07); /* video std */ 1008 io_write(sd, 0x01, 0x02); /* prim mode */ 1009 /* enable embedded syncs for auto graphics mode */ 1010 cp_write_clr_set(sd, 0x81, 0x10, 0x10); 1011 1012 /* Should only be set in auto-graphics mode [REF_02, p. 91-92] */ 1013 /* setup PLL_DIV_MAN_EN and PLL_DIV_RATIO */ 1014 /* IO-map reg. 0x16 and 0x17 should be written in sequence */ 1015 if (regmap_raw_write(state->regmap[ADV76XX_PAGE_IO], 1016 0x16, pll, 2)) 1017 v4l2_err(sd, "writing to reg 0x16 and 0x17 failed\n"); 1018 1019 /* active video - horizontal timing */ 1020 cp_write(sd, 0xa2, (cp_start_sav >> 4) & 0xff); 1021 cp_write(sd, 0xa3, ((cp_start_sav & 0x0f) << 4) | 1022 ((cp_start_eav >> 8) & 0x0f)); 1023 cp_write(sd, 0xa4, cp_start_eav & 0xff); 1024 1025 /* active video - vertical timing */ 1026 cp_write(sd, 0xa5, (cp_start_vbi >> 4) & 0xff); 1027 cp_write(sd, 0xa6, ((cp_start_vbi & 0xf) << 4) | 1028 ((cp_end_vbi >> 8) & 0xf)); 1029 cp_write(sd, 0xa7, cp_end_vbi & 0xff); 1030 } else if (is_digital_input(sd)) { 1031 /* set default prim_mode/vid_std for HDMI 1032 according to [REF_03, c. 4.2] */ 1033 io_write(sd, 0x00, 0x02); /* video std */ 1034 io_write(sd, 0x01, 0x06); /* prim mode */ 1035 } else { 1036 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n", 1037 __func__, state->selected_input); 1038 } 1039 1040 cp_write(sd, 0x8f, (ch1_fr_ll >> 8) & 0x7); 1041 cp_write(sd, 0x90, ch1_fr_ll & 0xff); 1042 cp_write(sd, 0xab, (height >> 4) & 0xff); 1043 cp_write(sd, 0xac, (height & 0x0f) << 4); 1044 } 1045 1046 static void adv76xx_set_offset(struct v4l2_subdev *sd, bool auto_offset, u16 offset_a, u16 offset_b, u16 offset_c) 1047 { 1048 struct adv76xx_state *state = to_state(sd); 1049 u8 offset_buf[4]; 1050 1051 if (auto_offset) { 1052 offset_a = 0x3ff; 1053 offset_b = 0x3ff; 1054 offset_c = 0x3ff; 1055 } 1056 1057 v4l2_dbg(2, debug, sd, "%s: %s offset: a = 0x%x, b = 0x%x, c = 0x%x\n", 1058 __func__, auto_offset ? "Auto" : "Manual", 1059 offset_a, offset_b, offset_c); 1060 1061 offset_buf[0] = (cp_read(sd, 0x77) & 0xc0) | ((offset_a & 0x3f0) >> 4); 1062 offset_buf[1] = ((offset_a & 0x00f) << 4) | ((offset_b & 0x3c0) >> 6); 1063 offset_buf[2] = ((offset_b & 0x03f) << 2) | ((offset_c & 0x300) >> 8); 1064 offset_buf[3] = offset_c & 0x0ff; 1065 1066 /* Registers must be written in this order with no i2c access in between */ 1067 if (regmap_raw_write(state->regmap[ADV76XX_PAGE_CP], 1068 0x77, offset_buf, 4)) 1069 v4l2_err(sd, "%s: i2c error writing to CP reg 0x77, 0x78, 0x79, 0x7a\n", __func__); 1070 } 1071 1072 static void adv76xx_set_gain(struct v4l2_subdev *sd, bool auto_gain, u16 gain_a, u16 gain_b, u16 gain_c) 1073 { 1074 struct adv76xx_state *state = to_state(sd); 1075 u8 gain_buf[4]; 1076 u8 gain_man = 1; 1077 u8 agc_mode_man = 1; 1078 1079 if (auto_gain) { 1080 gain_man = 0; 1081 agc_mode_man = 0; 1082 gain_a = 0x100; 1083 gain_b = 0x100; 1084 gain_c = 0x100; 1085 } 1086 1087 v4l2_dbg(2, debug, sd, "%s: %s gain: a = 0x%x, b = 0x%x, c = 0x%x\n", 1088 __func__, auto_gain ? "Auto" : "Manual", 1089 gain_a, gain_b, gain_c); 1090 1091 gain_buf[0] = ((gain_man << 7) | (agc_mode_man << 6) | ((gain_a & 0x3f0) >> 4)); 1092 gain_buf[1] = (((gain_a & 0x00f) << 4) | ((gain_b & 0x3c0) >> 6)); 1093 gain_buf[2] = (((gain_b & 0x03f) << 2) | ((gain_c & 0x300) >> 8)); 1094 gain_buf[3] = ((gain_c & 0x0ff)); 1095 1096 /* Registers must be written in this order with no i2c access in between */ 1097 if (regmap_raw_write(state->regmap[ADV76XX_PAGE_CP], 1098 0x73, gain_buf, 4)) 1099 v4l2_err(sd, "%s: i2c error writing to CP reg 0x73, 0x74, 0x75, 0x76\n", __func__); 1100 } 1101 1102 static void set_rgb_quantization_range(struct v4l2_subdev *sd) 1103 { 1104 struct adv76xx_state *state = to_state(sd); 1105 bool rgb_output = io_read(sd, 0x02) & 0x02; 1106 bool hdmi_signal = hdmi_read(sd, 0x05) & 0x80; 1107 u8 y = HDMI_COLORSPACE_RGB; 1108 1109 if (hdmi_signal && (io_read(sd, 0x60) & 1)) 1110 y = infoframe_read(sd, 0x01) >> 5; 1111 1112 v4l2_dbg(2, debug, sd, "%s: RGB quantization range: %d, RGB out: %d, HDMI: %d\n", 1113 __func__, state->rgb_quantization_range, 1114 rgb_output, hdmi_signal); 1115 1116 adv76xx_set_gain(sd, true, 0x0, 0x0, 0x0); 1117 adv76xx_set_offset(sd, true, 0x0, 0x0, 0x0); 1118 io_write_clr_set(sd, 0x02, 0x04, rgb_output ? 0 : 4); 1119 1120 switch (state->rgb_quantization_range) { 1121 case V4L2_DV_RGB_RANGE_AUTO: 1122 if (state->selected_input == ADV7604_PAD_VGA_RGB) { 1123 /* Receiving analog RGB signal 1124 * Set RGB full range (0-255) */ 1125 io_write_clr_set(sd, 0x02, 0xf0, 0x10); 1126 break; 1127 } 1128 1129 if (state->selected_input == ADV7604_PAD_VGA_COMP) { 1130 /* Receiving analog YPbPr signal 1131 * Set automode */ 1132 io_write_clr_set(sd, 0x02, 0xf0, 0xf0); 1133 break; 1134 } 1135 1136 if (hdmi_signal) { 1137 /* Receiving HDMI signal 1138 * Set automode */ 1139 io_write_clr_set(sd, 0x02, 0xf0, 0xf0); 1140 break; 1141 } 1142 1143 /* Receiving DVI-D signal 1144 * ADV7604 selects RGB limited range regardless of 1145 * input format (CE/IT) in automatic mode */ 1146 if (state->timings.bt.flags & V4L2_DV_FL_IS_CE_VIDEO) { 1147 /* RGB limited range (16-235) */ 1148 io_write_clr_set(sd, 0x02, 0xf0, 0x00); 1149 } else { 1150 /* RGB full range (0-255) */ 1151 io_write_clr_set(sd, 0x02, 0xf0, 0x10); 1152 1153 if (is_digital_input(sd) && rgb_output) { 1154 adv76xx_set_offset(sd, false, 0x40, 0x40, 0x40); 1155 } else { 1156 adv76xx_set_gain(sd, false, 0xe0, 0xe0, 0xe0); 1157 adv76xx_set_offset(sd, false, 0x70, 0x70, 0x70); 1158 } 1159 } 1160 break; 1161 case V4L2_DV_RGB_RANGE_LIMITED: 1162 if (state->selected_input == ADV7604_PAD_VGA_COMP) { 1163 /* YCrCb limited range (16-235) */ 1164 io_write_clr_set(sd, 0x02, 0xf0, 0x20); 1165 break; 1166 } 1167 1168 if (y != HDMI_COLORSPACE_RGB) 1169 break; 1170 1171 /* RGB limited range (16-235) */ 1172 io_write_clr_set(sd, 0x02, 0xf0, 0x00); 1173 1174 break; 1175 case V4L2_DV_RGB_RANGE_FULL: 1176 if (state->selected_input == ADV7604_PAD_VGA_COMP) { 1177 /* YCrCb full range (0-255) */ 1178 io_write_clr_set(sd, 0x02, 0xf0, 0x60); 1179 break; 1180 } 1181 1182 if (y != HDMI_COLORSPACE_RGB) 1183 break; 1184 1185 /* RGB full range (0-255) */ 1186 io_write_clr_set(sd, 0x02, 0xf0, 0x10); 1187 1188 if (is_analog_input(sd) || hdmi_signal) 1189 break; 1190 1191 /* Adjust gain/offset for DVI-D signals only */ 1192 if (rgb_output) { 1193 adv76xx_set_offset(sd, false, 0x40, 0x40, 0x40); 1194 } else { 1195 adv76xx_set_gain(sd, false, 0xe0, 0xe0, 0xe0); 1196 adv76xx_set_offset(sd, false, 0x70, 0x70, 0x70); 1197 } 1198 break; 1199 } 1200 } 1201 1202 static int adv76xx_s_ctrl(struct v4l2_ctrl *ctrl) 1203 { 1204 struct v4l2_subdev *sd = 1205 &container_of(ctrl->handler, struct adv76xx_state, hdl)->sd; 1206 1207 struct adv76xx_state *state = to_state(sd); 1208 1209 switch (ctrl->id) { 1210 case V4L2_CID_BRIGHTNESS: 1211 cp_write(sd, 0x3c, ctrl->val); 1212 return 0; 1213 case V4L2_CID_CONTRAST: 1214 cp_write(sd, 0x3a, ctrl->val); 1215 return 0; 1216 case V4L2_CID_SATURATION: 1217 cp_write(sd, 0x3b, ctrl->val); 1218 return 0; 1219 case V4L2_CID_HUE: 1220 cp_write(sd, 0x3d, ctrl->val); 1221 return 0; 1222 case V4L2_CID_DV_RX_RGB_RANGE: 1223 state->rgb_quantization_range = ctrl->val; 1224 set_rgb_quantization_range(sd); 1225 return 0; 1226 case V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE: 1227 if (!adv76xx_has_afe(state)) 1228 return -EINVAL; 1229 /* Set the analog sampling phase. This is needed to find the 1230 best sampling phase for analog video: an application or 1231 driver has to try a number of phases and analyze the picture 1232 quality before settling on the best performing phase. */ 1233 afe_write(sd, 0xc8, ctrl->val); 1234 return 0; 1235 case V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL: 1236 /* Use the default blue color for free running mode, 1237 or supply your own. */ 1238 cp_write_clr_set(sd, 0xbf, 0x04, ctrl->val << 2); 1239 return 0; 1240 case V4L2_CID_ADV_RX_FREE_RUN_COLOR: 1241 cp_write(sd, 0xc0, (ctrl->val & 0xff0000) >> 16); 1242 cp_write(sd, 0xc1, (ctrl->val & 0x00ff00) >> 8); 1243 cp_write(sd, 0xc2, (u8)(ctrl->val & 0x0000ff)); 1244 return 0; 1245 } 1246 return -EINVAL; 1247 } 1248 1249 static int adv76xx_g_volatile_ctrl(struct v4l2_ctrl *ctrl) 1250 { 1251 struct v4l2_subdev *sd = 1252 &container_of(ctrl->handler, struct adv76xx_state, hdl)->sd; 1253 1254 if (ctrl->id == V4L2_CID_DV_RX_IT_CONTENT_TYPE) { 1255 ctrl->val = V4L2_DV_IT_CONTENT_TYPE_NO_ITC; 1256 if ((io_read(sd, 0x60) & 1) && (infoframe_read(sd, 0x03) & 0x80)) 1257 ctrl->val = (infoframe_read(sd, 0x05) >> 4) & 3; 1258 return 0; 1259 } 1260 return -EINVAL; 1261 } 1262 1263 /* ----------------------------------------------------------------------- */ 1264 1265 static inline bool no_power(struct v4l2_subdev *sd) 1266 { 1267 /* Entire chip or CP powered off */ 1268 return io_read(sd, 0x0c) & 0x24; 1269 } 1270 1271 static inline bool no_signal_tmds(struct v4l2_subdev *sd) 1272 { 1273 struct adv76xx_state *state = to_state(sd); 1274 1275 return !(io_read(sd, 0x6a) & (0x10 >> state->selected_input)); 1276 } 1277 1278 static inline bool no_lock_tmds(struct v4l2_subdev *sd) 1279 { 1280 struct adv76xx_state *state = to_state(sd); 1281 const struct adv76xx_chip_info *info = state->info; 1282 1283 return (io_read(sd, 0x6a) & info->tdms_lock_mask) != info->tdms_lock_mask; 1284 } 1285 1286 static inline bool is_hdmi(struct v4l2_subdev *sd) 1287 { 1288 return hdmi_read(sd, 0x05) & 0x80; 1289 } 1290 1291 static inline bool no_lock_sspd(struct v4l2_subdev *sd) 1292 { 1293 struct adv76xx_state *state = to_state(sd); 1294 1295 /* 1296 * Chips without a AFE don't expose registers for the SSPD, so just assume 1297 * that we have a lock. 1298 */ 1299 if (adv76xx_has_afe(state)) 1300 return false; 1301 1302 /* TODO channel 2 */ 1303 return ((cp_read(sd, 0xb5) & 0xd0) != 0xd0); 1304 } 1305 1306 static inline bool no_lock_stdi(struct v4l2_subdev *sd) 1307 { 1308 /* TODO channel 2 */ 1309 return !(cp_read(sd, 0xb1) & 0x80); 1310 } 1311 1312 static inline bool no_signal(struct v4l2_subdev *sd) 1313 { 1314 bool ret; 1315 1316 ret = no_power(sd); 1317 1318 ret |= no_lock_stdi(sd); 1319 ret |= no_lock_sspd(sd); 1320 1321 if (is_digital_input(sd)) { 1322 ret |= no_lock_tmds(sd); 1323 ret |= no_signal_tmds(sd); 1324 } 1325 1326 return ret; 1327 } 1328 1329 static inline bool no_lock_cp(struct v4l2_subdev *sd) 1330 { 1331 struct adv76xx_state *state = to_state(sd); 1332 1333 if (!adv76xx_has_afe(state)) 1334 return false; 1335 1336 /* CP has detected a non standard number of lines on the incoming 1337 video compared to what it is configured to receive by s_dv_timings */ 1338 return io_read(sd, 0x12) & 0x01; 1339 } 1340 1341 static inline bool in_free_run(struct v4l2_subdev *sd) 1342 { 1343 return cp_read(sd, 0xff) & 0x10; 1344 } 1345 1346 static int adv76xx_g_input_status(struct v4l2_subdev *sd, u32 *status) 1347 { 1348 *status = 0; 1349 *status |= no_power(sd) ? V4L2_IN_ST_NO_POWER : 0; 1350 *status |= no_signal(sd) ? V4L2_IN_ST_NO_SIGNAL : 0; 1351 if (!in_free_run(sd) && no_lock_cp(sd)) 1352 *status |= is_digital_input(sd) ? 1353 V4L2_IN_ST_NO_SYNC : V4L2_IN_ST_NO_H_LOCK; 1354 1355 v4l2_dbg(1, debug, sd, "%s: status = 0x%x\n", __func__, *status); 1356 1357 return 0; 1358 } 1359 1360 /* ----------------------------------------------------------------------- */ 1361 1362 struct stdi_readback { 1363 u16 bl, lcf, lcvs; 1364 u8 hs_pol, vs_pol; 1365 bool interlaced; 1366 }; 1367 1368 static int stdi2dv_timings(struct v4l2_subdev *sd, 1369 struct stdi_readback *stdi, 1370 struct v4l2_dv_timings *timings) 1371 { 1372 struct adv76xx_state *state = to_state(sd); 1373 u32 hfreq = (ADV76XX_FSC * 8) / stdi->bl; 1374 u32 pix_clk; 1375 int i; 1376 1377 for (i = 0; v4l2_dv_timings_presets[i].bt.width; i++) { 1378 const struct v4l2_bt_timings *bt = &v4l2_dv_timings_presets[i].bt; 1379 1380 if (!v4l2_valid_dv_timings(&v4l2_dv_timings_presets[i], 1381 adv76xx_get_dv_timings_cap(sd, -1), 1382 adv76xx_check_dv_timings, NULL)) 1383 continue; 1384 if (vtotal(bt) != stdi->lcf + 1) 1385 continue; 1386 if (bt->vsync != stdi->lcvs) 1387 continue; 1388 1389 pix_clk = hfreq * htotal(bt); 1390 1391 if ((pix_clk < bt->pixelclock + 1000000) && 1392 (pix_clk > bt->pixelclock - 1000000)) { 1393 *timings = v4l2_dv_timings_presets[i]; 1394 return 0; 1395 } 1396 } 1397 1398 if (v4l2_detect_cvt(stdi->lcf + 1, hfreq, stdi->lcvs, 0, 1399 (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) | 1400 (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0), 1401 false, timings)) 1402 return 0; 1403 if (v4l2_detect_gtf(stdi->lcf + 1, hfreq, stdi->lcvs, 1404 (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) | 1405 (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0), 1406 false, state->aspect_ratio, timings)) 1407 return 0; 1408 1409 v4l2_dbg(2, debug, sd, 1410 "%s: No format candidate found for lcvs = %d, lcf=%d, bl = %d, %chsync, %cvsync\n", 1411 __func__, stdi->lcvs, stdi->lcf, stdi->bl, 1412 stdi->hs_pol, stdi->vs_pol); 1413 return -1; 1414 } 1415 1416 1417 static int read_stdi(struct v4l2_subdev *sd, struct stdi_readback *stdi) 1418 { 1419 struct adv76xx_state *state = to_state(sd); 1420 const struct adv76xx_chip_info *info = state->info; 1421 u8 polarity; 1422 1423 if (no_lock_stdi(sd) || no_lock_sspd(sd)) { 1424 v4l2_dbg(2, debug, sd, "%s: STDI and/or SSPD not locked\n", __func__); 1425 return -1; 1426 } 1427 1428 /* read STDI */ 1429 stdi->bl = cp_read16(sd, 0xb1, 0x3fff); 1430 stdi->lcf = cp_read16(sd, info->lcf_reg, 0x7ff); 1431 stdi->lcvs = cp_read(sd, 0xb3) >> 3; 1432 stdi->interlaced = io_read(sd, 0x12) & 0x10; 1433 1434 if (adv76xx_has_afe(state)) { 1435 /* read SSPD */ 1436 polarity = cp_read(sd, 0xb5); 1437 if ((polarity & 0x03) == 0x01) { 1438 stdi->hs_pol = polarity & 0x10 1439 ? (polarity & 0x08 ? '+' : '-') : 'x'; 1440 stdi->vs_pol = polarity & 0x40 1441 ? (polarity & 0x20 ? '+' : '-') : 'x'; 1442 } else { 1443 stdi->hs_pol = 'x'; 1444 stdi->vs_pol = 'x'; 1445 } 1446 } else { 1447 polarity = hdmi_read(sd, 0x05); 1448 stdi->hs_pol = polarity & 0x20 ? '+' : '-'; 1449 stdi->vs_pol = polarity & 0x10 ? '+' : '-'; 1450 } 1451 1452 if (no_lock_stdi(sd) || no_lock_sspd(sd)) { 1453 v4l2_dbg(2, debug, sd, 1454 "%s: signal lost during readout of STDI/SSPD\n", __func__); 1455 return -1; 1456 } 1457 1458 if (stdi->lcf < 239 || stdi->bl < 8 || stdi->bl == 0x3fff) { 1459 v4l2_dbg(2, debug, sd, "%s: invalid signal\n", __func__); 1460 memset(stdi, 0, sizeof(struct stdi_readback)); 1461 return -1; 1462 } 1463 1464 v4l2_dbg(2, debug, sd, 1465 "%s: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %chsync, %cvsync, %s\n", 1466 __func__, stdi->lcf, stdi->bl, stdi->lcvs, 1467 stdi->hs_pol, stdi->vs_pol, 1468 stdi->interlaced ? "interlaced" : "progressive"); 1469 1470 return 0; 1471 } 1472 1473 static int adv76xx_enum_dv_timings(struct v4l2_subdev *sd, 1474 struct v4l2_enum_dv_timings *timings) 1475 { 1476 struct adv76xx_state *state = to_state(sd); 1477 1478 if (timings->pad >= state->source_pad) 1479 return -EINVAL; 1480 1481 return v4l2_enum_dv_timings_cap(timings, 1482 adv76xx_get_dv_timings_cap(sd, timings->pad), 1483 adv76xx_check_dv_timings, NULL); 1484 } 1485 1486 static int adv76xx_dv_timings_cap(struct v4l2_subdev *sd, 1487 struct v4l2_dv_timings_cap *cap) 1488 { 1489 struct adv76xx_state *state = to_state(sd); 1490 unsigned int pad = cap->pad; 1491 1492 if (cap->pad >= state->source_pad) 1493 return -EINVAL; 1494 1495 *cap = *adv76xx_get_dv_timings_cap(sd, pad); 1496 cap->pad = pad; 1497 1498 return 0; 1499 } 1500 1501 /* Fill the optional fields .standards and .flags in struct v4l2_dv_timings 1502 if the format is listed in adv76xx_timings[] */ 1503 static void adv76xx_fill_optional_dv_timings_fields(struct v4l2_subdev *sd, 1504 struct v4l2_dv_timings *timings) 1505 { 1506 v4l2_find_dv_timings_cap(timings, adv76xx_get_dv_timings_cap(sd, -1), 1507 is_digital_input(sd) ? 250000 : 1000000, 1508 adv76xx_check_dv_timings, NULL); 1509 } 1510 1511 static unsigned int adv7604_read_hdmi_pixelclock(struct v4l2_subdev *sd) 1512 { 1513 int a, b; 1514 1515 a = hdmi_read(sd, 0x06); 1516 b = hdmi_read(sd, 0x3b); 1517 if (a < 0 || b < 0) 1518 return 0; 1519 1520 return a * 1000000 + ((b & 0x30) >> 4) * 250000; 1521 } 1522 1523 static unsigned int adv7611_read_hdmi_pixelclock(struct v4l2_subdev *sd) 1524 { 1525 int a, b; 1526 1527 a = hdmi_read(sd, 0x51); 1528 b = hdmi_read(sd, 0x52); 1529 if (a < 0 || b < 0) 1530 return 0; 1531 1532 return ((a << 1) | (b >> 7)) * 1000000 + (b & 0x7f) * 1000000 / 128; 1533 } 1534 1535 static unsigned int adv76xx_read_hdmi_pixelclock(struct v4l2_subdev *sd) 1536 { 1537 struct adv76xx_state *state = to_state(sd); 1538 const struct adv76xx_chip_info *info = state->info; 1539 unsigned int freq, bits_per_channel, pixelrepetition; 1540 1541 freq = info->read_hdmi_pixelclock(sd); 1542 if (is_hdmi(sd)) { 1543 /* adjust for deep color mode and pixel repetition */ 1544 bits_per_channel = ((hdmi_read(sd, 0x0b) & 0x60) >> 4) + 8; 1545 pixelrepetition = (hdmi_read(sd, 0x05) & 0x0f) + 1; 1546 1547 freq = freq * 8 / bits_per_channel / pixelrepetition; 1548 } 1549 1550 return freq; 1551 } 1552 1553 static int adv76xx_query_dv_timings(struct v4l2_subdev *sd, 1554 struct v4l2_dv_timings *timings) 1555 { 1556 struct adv76xx_state *state = to_state(sd); 1557 const struct adv76xx_chip_info *info = state->info; 1558 struct v4l2_bt_timings *bt = &timings->bt; 1559 struct stdi_readback stdi; 1560 1561 if (!timings) 1562 return -EINVAL; 1563 1564 memset(timings, 0, sizeof(struct v4l2_dv_timings)); 1565 1566 if (no_signal(sd)) { 1567 state->restart_stdi_once = true; 1568 v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__); 1569 return -ENOLINK; 1570 } 1571 1572 /* read STDI */ 1573 if (read_stdi(sd, &stdi)) { 1574 v4l2_dbg(1, debug, sd, "%s: STDI/SSPD not locked\n", __func__); 1575 return -ENOLINK; 1576 } 1577 bt->interlaced = stdi.interlaced ? 1578 V4L2_DV_INTERLACED : V4L2_DV_PROGRESSIVE; 1579 1580 if (is_digital_input(sd)) { 1581 bool hdmi_signal = hdmi_read(sd, 0x05) & 0x80; 1582 u8 vic = 0; 1583 u32 w, h; 1584 1585 w = hdmi_read16(sd, 0x07, info->linewidth_mask); 1586 h = hdmi_read16(sd, 0x09, info->field0_height_mask); 1587 1588 if (hdmi_signal && (io_read(sd, 0x60) & 1)) 1589 vic = infoframe_read(sd, 0x04); 1590 1591 if (vic && v4l2_find_dv_timings_cea861_vic(timings, vic) && 1592 bt->width == w && bt->height == h) 1593 goto found; 1594 1595 timings->type = V4L2_DV_BT_656_1120; 1596 1597 bt->width = w; 1598 bt->height = h; 1599 bt->pixelclock = adv76xx_read_hdmi_pixelclock(sd); 1600 bt->hfrontporch = hdmi_read16(sd, 0x20, info->hfrontporch_mask); 1601 bt->hsync = hdmi_read16(sd, 0x22, info->hsync_mask); 1602 bt->hbackporch = hdmi_read16(sd, 0x24, info->hbackporch_mask); 1603 bt->vfrontporch = hdmi_read16(sd, 0x2a, 1604 info->field0_vfrontporch_mask) / 2; 1605 bt->vsync = hdmi_read16(sd, 0x2e, info->field0_vsync_mask) / 2; 1606 bt->vbackporch = hdmi_read16(sd, 0x32, 1607 info->field0_vbackporch_mask) / 2; 1608 bt->polarities = ((hdmi_read(sd, 0x05) & 0x10) ? V4L2_DV_VSYNC_POS_POL : 0) | 1609 ((hdmi_read(sd, 0x05) & 0x20) ? V4L2_DV_HSYNC_POS_POL : 0); 1610 if (bt->interlaced == V4L2_DV_INTERLACED) { 1611 bt->height += hdmi_read16(sd, 0x0b, 1612 info->field1_height_mask); 1613 bt->il_vfrontporch = hdmi_read16(sd, 0x2c, 1614 info->field1_vfrontporch_mask) / 2; 1615 bt->il_vsync = hdmi_read16(sd, 0x30, 1616 info->field1_vsync_mask) / 2; 1617 bt->il_vbackporch = hdmi_read16(sd, 0x34, 1618 info->field1_vbackporch_mask) / 2; 1619 } 1620 adv76xx_fill_optional_dv_timings_fields(sd, timings); 1621 } else { 1622 /* find format 1623 * Since LCVS values are inaccurate [REF_03, p. 275-276], 1624 * stdi2dv_timings() is called with lcvs +-1 if the first attempt fails. 1625 */ 1626 if (!stdi2dv_timings(sd, &stdi, timings)) 1627 goto found; 1628 stdi.lcvs += 1; 1629 v4l2_dbg(1, debug, sd, "%s: lcvs + 1 = %d\n", __func__, stdi.lcvs); 1630 if (!stdi2dv_timings(sd, &stdi, timings)) 1631 goto found; 1632 stdi.lcvs -= 2; 1633 v4l2_dbg(1, debug, sd, "%s: lcvs - 1 = %d\n", __func__, stdi.lcvs); 1634 if (stdi2dv_timings(sd, &stdi, timings)) { 1635 /* 1636 * The STDI block may measure wrong values, especially 1637 * for lcvs and lcf. If the driver can not find any 1638 * valid timing, the STDI block is restarted to measure 1639 * the video timings again. The function will return an 1640 * error, but the restart of STDI will generate a new 1641 * STDI interrupt and the format detection process will 1642 * restart. 1643 */ 1644 if (state->restart_stdi_once) { 1645 v4l2_dbg(1, debug, sd, "%s: restart STDI\n", __func__); 1646 /* TODO restart STDI for Sync Channel 2 */ 1647 /* enter one-shot mode */ 1648 cp_write_clr_set(sd, 0x86, 0x06, 0x00); 1649 /* trigger STDI restart */ 1650 cp_write_clr_set(sd, 0x86, 0x06, 0x04); 1651 /* reset to continuous mode */ 1652 cp_write_clr_set(sd, 0x86, 0x06, 0x02); 1653 state->restart_stdi_once = false; 1654 return -ENOLINK; 1655 } 1656 v4l2_dbg(1, debug, sd, "%s: format not supported\n", __func__); 1657 return -ERANGE; 1658 } 1659 state->restart_stdi_once = true; 1660 } 1661 found: 1662 1663 if (no_signal(sd)) { 1664 v4l2_dbg(1, debug, sd, "%s: signal lost during readout\n", __func__); 1665 memset(timings, 0, sizeof(struct v4l2_dv_timings)); 1666 return -ENOLINK; 1667 } 1668 1669 if ((is_analog_input(sd) && bt->pixelclock > 170000000) || 1670 (is_digital_input(sd) && bt->pixelclock > 225000000)) { 1671 v4l2_dbg(1, debug, sd, "%s: pixelclock out of range %d\n", 1672 __func__, (u32)bt->pixelclock); 1673 return -ERANGE; 1674 } 1675 1676 if (debug > 1) 1677 v4l2_print_dv_timings(sd->name, "adv76xx_query_dv_timings: ", 1678 timings, true); 1679 1680 return 0; 1681 } 1682 1683 static int adv76xx_s_dv_timings(struct v4l2_subdev *sd, 1684 struct v4l2_dv_timings *timings) 1685 { 1686 struct adv76xx_state *state = to_state(sd); 1687 struct v4l2_bt_timings *bt; 1688 int err; 1689 1690 if (!timings) 1691 return -EINVAL; 1692 1693 if (v4l2_match_dv_timings(&state->timings, timings, 0, false)) { 1694 v4l2_dbg(1, debug, sd, "%s: no change\n", __func__); 1695 return 0; 1696 } 1697 1698 bt = &timings->bt; 1699 1700 if (!v4l2_valid_dv_timings(timings, adv76xx_get_dv_timings_cap(sd, -1), 1701 adv76xx_check_dv_timings, NULL)) 1702 return -ERANGE; 1703 1704 adv76xx_fill_optional_dv_timings_fields(sd, timings); 1705 1706 state->timings = *timings; 1707 1708 cp_write_clr_set(sd, 0x91, 0x40, bt->interlaced ? 0x40 : 0x00); 1709 1710 /* Use prim_mode and vid_std when available */ 1711 err = configure_predefined_video_timings(sd, timings); 1712 if (err) { 1713 /* custom settings when the video format 1714 does not have prim_mode/vid_std */ 1715 configure_custom_video_timings(sd, bt); 1716 } 1717 1718 set_rgb_quantization_range(sd); 1719 1720 if (debug > 1) 1721 v4l2_print_dv_timings(sd->name, "adv76xx_s_dv_timings: ", 1722 timings, true); 1723 return 0; 1724 } 1725 1726 static int adv76xx_g_dv_timings(struct v4l2_subdev *sd, 1727 struct v4l2_dv_timings *timings) 1728 { 1729 struct adv76xx_state *state = to_state(sd); 1730 1731 *timings = state->timings; 1732 return 0; 1733 } 1734 1735 static void adv7604_set_termination(struct v4l2_subdev *sd, bool enable) 1736 { 1737 hdmi_write(sd, 0x01, enable ? 0x00 : 0x78); 1738 } 1739 1740 static void adv7611_set_termination(struct v4l2_subdev *sd, bool enable) 1741 { 1742 hdmi_write(sd, 0x83, enable ? 0xfe : 0xff); 1743 } 1744 1745 static void enable_input(struct v4l2_subdev *sd) 1746 { 1747 struct adv76xx_state *state = to_state(sd); 1748 1749 if (is_analog_input(sd)) { 1750 io_write(sd, 0x15, 0xb0); /* Disable Tristate of Pins (no audio) */ 1751 } else if (is_digital_input(sd)) { 1752 hdmi_write_clr_set(sd, 0x00, 0x03, state->selected_input); 1753 state->info->set_termination(sd, true); 1754 io_write(sd, 0x15, 0xa0); /* Disable Tristate of Pins */ 1755 hdmi_write_clr_set(sd, 0x1a, 0x10, 0x00); /* Unmute audio */ 1756 } else { 1757 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n", 1758 __func__, state->selected_input); 1759 } 1760 } 1761 1762 static void disable_input(struct v4l2_subdev *sd) 1763 { 1764 struct adv76xx_state *state = to_state(sd); 1765 1766 hdmi_write_clr_set(sd, 0x1a, 0x10, 0x10); /* Mute audio */ 1767 msleep(16); /* 512 samples with >= 32 kHz sample rate [REF_03, c. 7.16.10] */ 1768 io_write(sd, 0x15, 0xbe); /* Tristate all outputs from video core */ 1769 state->info->set_termination(sd, false); 1770 } 1771 1772 static void select_input(struct v4l2_subdev *sd) 1773 { 1774 struct adv76xx_state *state = to_state(sd); 1775 const struct adv76xx_chip_info *info = state->info; 1776 1777 if (is_analog_input(sd)) { 1778 adv76xx_write_reg_seq(sd, info->recommended_settings[0]); 1779 1780 afe_write(sd, 0x00, 0x08); /* power up ADC */ 1781 afe_write(sd, 0x01, 0x06); /* power up Analog Front End */ 1782 afe_write(sd, 0xc8, 0x00); /* phase control */ 1783 } else if (is_digital_input(sd)) { 1784 hdmi_write(sd, 0x00, state->selected_input & 0x03); 1785 1786 adv76xx_write_reg_seq(sd, info->recommended_settings[1]); 1787 1788 if (adv76xx_has_afe(state)) { 1789 afe_write(sd, 0x00, 0xff); /* power down ADC */ 1790 afe_write(sd, 0x01, 0xfe); /* power down Analog Front End */ 1791 afe_write(sd, 0xc8, 0x40); /* phase control */ 1792 } 1793 1794 cp_write(sd, 0x3e, 0x00); /* CP core pre-gain control */ 1795 cp_write(sd, 0xc3, 0x39); /* CP coast control. Graphics mode */ 1796 cp_write(sd, 0x40, 0x80); /* CP core pre-gain control. Graphics mode */ 1797 } else { 1798 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n", 1799 __func__, state->selected_input); 1800 } 1801 } 1802 1803 static int adv76xx_s_routing(struct v4l2_subdev *sd, 1804 u32 input, u32 output, u32 config) 1805 { 1806 struct adv76xx_state *state = to_state(sd); 1807 1808 v4l2_dbg(2, debug, sd, "%s: input %d, selected input %d", 1809 __func__, input, state->selected_input); 1810 1811 if (input == state->selected_input) 1812 return 0; 1813 1814 if (input > state->info->max_port) 1815 return -EINVAL; 1816 1817 state->selected_input = input; 1818 1819 disable_input(sd); 1820 select_input(sd); 1821 enable_input(sd); 1822 1823 v4l2_subdev_notify_event(sd, &adv76xx_ev_fmt); 1824 1825 return 0; 1826 } 1827 1828 static int adv76xx_enum_mbus_code(struct v4l2_subdev *sd, 1829 struct v4l2_subdev_pad_config *cfg, 1830 struct v4l2_subdev_mbus_code_enum *code) 1831 { 1832 struct adv76xx_state *state = to_state(sd); 1833 1834 if (code->index >= state->info->nformats) 1835 return -EINVAL; 1836 1837 code->code = state->info->formats[code->index].code; 1838 1839 return 0; 1840 } 1841 1842 static void adv76xx_fill_format(struct adv76xx_state *state, 1843 struct v4l2_mbus_framefmt *format) 1844 { 1845 memset(format, 0, sizeof(*format)); 1846 1847 format->width = state->timings.bt.width; 1848 format->height = state->timings.bt.height; 1849 format->field = V4L2_FIELD_NONE; 1850 format->colorspace = V4L2_COLORSPACE_SRGB; 1851 1852 if (state->timings.bt.flags & V4L2_DV_FL_IS_CE_VIDEO) 1853 format->colorspace = (state->timings.bt.height <= 576) ? 1854 V4L2_COLORSPACE_SMPTE170M : V4L2_COLORSPACE_REC709; 1855 } 1856 1857 /* 1858 * Compute the op_ch_sel value required to obtain on the bus the component order 1859 * corresponding to the selected format taking into account bus reordering 1860 * applied by the board at the output of the device. 1861 * 1862 * The following table gives the op_ch_value from the format component order 1863 * (expressed as op_ch_sel value in column) and the bus reordering (expressed as 1864 * adv76xx_bus_order value in row). 1865 * 1866 * | GBR(0) GRB(1) BGR(2) RGB(3) BRG(4) RBG(5) 1867 * ----------+------------------------------------------------- 1868 * RGB (NOP) | GBR GRB BGR RGB BRG RBG 1869 * GRB (1-2) | BGR RGB GBR GRB RBG BRG 1870 * RBG (2-3) | GRB GBR BRG RBG BGR RGB 1871 * BGR (1-3) | RBG BRG RGB BGR GRB GBR 1872 * BRG (ROR) | BRG RBG GRB GBR RGB BGR 1873 * GBR (ROL) | RGB BGR RBG BRG GBR GRB 1874 */ 1875 static unsigned int adv76xx_op_ch_sel(struct adv76xx_state *state) 1876 { 1877 #define _SEL(a,b,c,d,e,f) { \ 1878 ADV76XX_OP_CH_SEL_##a, ADV76XX_OP_CH_SEL_##b, ADV76XX_OP_CH_SEL_##c, \ 1879 ADV76XX_OP_CH_SEL_##d, ADV76XX_OP_CH_SEL_##e, ADV76XX_OP_CH_SEL_##f } 1880 #define _BUS(x) [ADV7604_BUS_ORDER_##x] 1881 1882 static const unsigned int op_ch_sel[6][6] = { 1883 _BUS(RGB) /* NOP */ = _SEL(GBR, GRB, BGR, RGB, BRG, RBG), 1884 _BUS(GRB) /* 1-2 */ = _SEL(BGR, RGB, GBR, GRB, RBG, BRG), 1885 _BUS(RBG) /* 2-3 */ = _SEL(GRB, GBR, BRG, RBG, BGR, RGB), 1886 _BUS(BGR) /* 1-3 */ = _SEL(RBG, BRG, RGB, BGR, GRB, GBR), 1887 _BUS(BRG) /* ROR */ = _SEL(BRG, RBG, GRB, GBR, RGB, BGR), 1888 _BUS(GBR) /* ROL */ = _SEL(RGB, BGR, RBG, BRG, GBR, GRB), 1889 }; 1890 1891 return op_ch_sel[state->pdata.bus_order][state->format->op_ch_sel >> 5]; 1892 } 1893 1894 static void adv76xx_setup_format(struct adv76xx_state *state) 1895 { 1896 struct v4l2_subdev *sd = &state->sd; 1897 1898 io_write_clr_set(sd, 0x02, 0x02, 1899 state->format->rgb_out ? ADV76XX_RGB_OUT : 0); 1900 io_write(sd, 0x03, state->format->op_format_sel | 1901 state->pdata.op_format_mode_sel); 1902 io_write_clr_set(sd, 0x04, 0xe0, adv76xx_op_ch_sel(state)); 1903 io_write_clr_set(sd, 0x05, 0x01, 1904 state->format->swap_cb_cr ? ADV76XX_OP_SWAP_CB_CR : 0); 1905 set_rgb_quantization_range(sd); 1906 } 1907 1908 static int adv76xx_get_format(struct v4l2_subdev *sd, 1909 struct v4l2_subdev_pad_config *cfg, 1910 struct v4l2_subdev_format *format) 1911 { 1912 struct adv76xx_state *state = to_state(sd); 1913 1914 if (format->pad != state->source_pad) 1915 return -EINVAL; 1916 1917 adv76xx_fill_format(state, &format->format); 1918 1919 if (format->which == V4L2_SUBDEV_FORMAT_TRY) { 1920 struct v4l2_mbus_framefmt *fmt; 1921 1922 fmt = v4l2_subdev_get_try_format(sd, cfg, format->pad); 1923 format->format.code = fmt->code; 1924 } else { 1925 format->format.code = state->format->code; 1926 } 1927 1928 return 0; 1929 } 1930 1931 static int adv76xx_get_selection(struct v4l2_subdev *sd, 1932 struct v4l2_subdev_pad_config *cfg, 1933 struct v4l2_subdev_selection *sel) 1934 { 1935 struct adv76xx_state *state = to_state(sd); 1936 1937 if (sel->which != V4L2_SUBDEV_FORMAT_ACTIVE) 1938 return -EINVAL; 1939 /* Only CROP, CROP_DEFAULT and CROP_BOUNDS are supported */ 1940 if (sel->target > V4L2_SEL_TGT_CROP_BOUNDS) 1941 return -EINVAL; 1942 1943 sel->r.left = 0; 1944 sel->r.top = 0; 1945 sel->r.width = state->timings.bt.width; 1946 sel->r.height = state->timings.bt.height; 1947 1948 return 0; 1949 } 1950 1951 static int adv76xx_set_format(struct v4l2_subdev *sd, 1952 struct v4l2_subdev_pad_config *cfg, 1953 struct v4l2_subdev_format *format) 1954 { 1955 struct adv76xx_state *state = to_state(sd); 1956 const struct adv76xx_format_info *info; 1957 1958 if (format->pad != state->source_pad) 1959 return -EINVAL; 1960 1961 info = adv76xx_format_info(state, format->format.code); 1962 if (!info) 1963 info = adv76xx_format_info(state, MEDIA_BUS_FMT_YUYV8_2X8); 1964 1965 adv76xx_fill_format(state, &format->format); 1966 format->format.code = info->code; 1967 1968 if (format->which == V4L2_SUBDEV_FORMAT_TRY) { 1969 struct v4l2_mbus_framefmt *fmt; 1970 1971 fmt = v4l2_subdev_get_try_format(sd, cfg, format->pad); 1972 fmt->code = format->format.code; 1973 } else { 1974 state->format = info; 1975 adv76xx_setup_format(state); 1976 } 1977 1978 return 0; 1979 } 1980 1981 #if IS_ENABLED(CONFIG_VIDEO_ADV7604_CEC) 1982 static void adv76xx_cec_tx_raw_status(struct v4l2_subdev *sd, u8 tx_raw_status) 1983 { 1984 struct adv76xx_state *state = to_state(sd); 1985 1986 if ((cec_read(sd, 0x11) & 0x01) == 0) { 1987 v4l2_dbg(1, debug, sd, "%s: tx raw: tx disabled\n", __func__); 1988 return; 1989 } 1990 1991 if (tx_raw_status & 0x02) { 1992 v4l2_dbg(1, debug, sd, "%s: tx raw: arbitration lost\n", 1993 __func__); 1994 cec_transmit_done(state->cec_adap, CEC_TX_STATUS_ARB_LOST, 1995 1, 0, 0, 0); 1996 return; 1997 } 1998 if (tx_raw_status & 0x04) { 1999 u8 status; 2000 u8 nack_cnt; 2001 u8 low_drive_cnt; 2002 2003 v4l2_dbg(1, debug, sd, "%s: tx raw: retry failed\n", __func__); 2004 /* 2005 * We set this status bit since this hardware performs 2006 * retransmissions. 2007 */ 2008 status = CEC_TX_STATUS_MAX_RETRIES; 2009 nack_cnt = cec_read(sd, 0x14) & 0xf; 2010 if (nack_cnt) 2011 status |= CEC_TX_STATUS_NACK; 2012 low_drive_cnt = cec_read(sd, 0x14) >> 4; 2013 if (low_drive_cnt) 2014 status |= CEC_TX_STATUS_LOW_DRIVE; 2015 cec_transmit_done(state->cec_adap, status, 2016 0, nack_cnt, low_drive_cnt, 0); 2017 return; 2018 } 2019 if (tx_raw_status & 0x01) { 2020 v4l2_dbg(1, debug, sd, "%s: tx raw: ready ok\n", __func__); 2021 cec_transmit_done(state->cec_adap, CEC_TX_STATUS_OK, 0, 0, 0, 0); 2022 return; 2023 } 2024 } 2025 2026 static void adv76xx_cec_isr(struct v4l2_subdev *sd, bool *handled) 2027 { 2028 struct adv76xx_state *state = to_state(sd); 2029 const struct adv76xx_chip_info *info = state->info; 2030 u8 cec_irq; 2031 2032 /* cec controller */ 2033 cec_irq = io_read(sd, info->cec_irq_status) & 0x0f; 2034 if (!cec_irq) 2035 return; 2036 2037 v4l2_dbg(1, debug, sd, "%s: cec: irq 0x%x\n", __func__, cec_irq); 2038 adv76xx_cec_tx_raw_status(sd, cec_irq); 2039 if (cec_irq & 0x08) { 2040 struct cec_msg msg; 2041 2042 msg.len = cec_read(sd, 0x25) & 0x1f; 2043 if (msg.len > 16) 2044 msg.len = 16; 2045 2046 if (msg.len) { 2047 u8 i; 2048 2049 for (i = 0; i < msg.len; i++) 2050 msg.msg[i] = cec_read(sd, i + 0x15); 2051 cec_write(sd, info->cec_rx_enable, 2052 info->cec_rx_enable_mask); /* re-enable rx */ 2053 cec_received_msg(state->cec_adap, &msg); 2054 } 2055 } 2056 2057 if (info->cec_irq_swap) { 2058 /* 2059 * Note: the bit order is swapped between 0x4d and 0x4e 2060 * on adv7604 2061 */ 2062 cec_irq = ((cec_irq & 0x08) >> 3) | ((cec_irq & 0x04) >> 1) | 2063 ((cec_irq & 0x02) << 1) | ((cec_irq & 0x01) << 3); 2064 } 2065 io_write(sd, info->cec_irq_status + 1, cec_irq); 2066 2067 if (handled) 2068 *handled = true; 2069 } 2070 2071 static int adv76xx_cec_adap_enable(struct cec_adapter *adap, bool enable) 2072 { 2073 struct adv76xx_state *state = cec_get_drvdata(adap); 2074 const struct adv76xx_chip_info *info = state->info; 2075 struct v4l2_subdev *sd = &state->sd; 2076 2077 if (!state->cec_enabled_adap && enable) { 2078 cec_write_clr_set(sd, 0x2a, 0x01, 0x01); /* power up cec */ 2079 cec_write(sd, 0x2c, 0x01); /* cec soft reset */ 2080 cec_write_clr_set(sd, 0x11, 0x01, 0); /* initially disable tx */ 2081 /* enabled irqs: */ 2082 /* tx: ready */ 2083 /* tx: arbitration lost */ 2084 /* tx: retry timeout */ 2085 /* rx: ready */ 2086 io_write_clr_set(sd, info->cec_irq_status + 3, 0x0f, 0x0f); 2087 cec_write(sd, info->cec_rx_enable, info->cec_rx_enable_mask); 2088 } else if (state->cec_enabled_adap && !enable) { 2089 /* disable cec interrupts */ 2090 io_write_clr_set(sd, info->cec_irq_status + 3, 0x0f, 0x00); 2091 /* disable address mask 1-3 */ 2092 cec_write_clr_set(sd, 0x27, 0x70, 0x00); 2093 /* power down cec section */ 2094 cec_write_clr_set(sd, 0x2a, 0x01, 0x00); 2095 state->cec_valid_addrs = 0; 2096 } 2097 state->cec_enabled_adap = enable; 2098 adv76xx_s_detect_tx_5v_ctrl(sd); 2099 return 0; 2100 } 2101 2102 static int adv76xx_cec_adap_log_addr(struct cec_adapter *adap, u8 addr) 2103 { 2104 struct adv76xx_state *state = cec_get_drvdata(adap); 2105 struct v4l2_subdev *sd = &state->sd; 2106 unsigned int i, free_idx = ADV76XX_MAX_ADDRS; 2107 2108 if (!state->cec_enabled_adap) 2109 return addr == CEC_LOG_ADDR_INVALID ? 0 : -EIO; 2110 2111 if (addr == CEC_LOG_ADDR_INVALID) { 2112 cec_write_clr_set(sd, 0x27, 0x70, 0); 2113 state->cec_valid_addrs = 0; 2114 return 0; 2115 } 2116 2117 for (i = 0; i < ADV76XX_MAX_ADDRS; i++) { 2118 bool is_valid = state->cec_valid_addrs & (1 << i); 2119 2120 if (free_idx == ADV76XX_MAX_ADDRS && !is_valid) 2121 free_idx = i; 2122 if (is_valid && state->cec_addr[i] == addr) 2123 return 0; 2124 } 2125 if (i == ADV76XX_MAX_ADDRS) { 2126 i = free_idx; 2127 if (i == ADV76XX_MAX_ADDRS) 2128 return -ENXIO; 2129 } 2130 state->cec_addr[i] = addr; 2131 state->cec_valid_addrs |= 1 << i; 2132 2133 switch (i) { 2134 case 0: 2135 /* enable address mask 0 */ 2136 cec_write_clr_set(sd, 0x27, 0x10, 0x10); 2137 /* set address for mask 0 */ 2138 cec_write_clr_set(sd, 0x28, 0x0f, addr); 2139 break; 2140 case 1: 2141 /* enable address mask 1 */ 2142 cec_write_clr_set(sd, 0x27, 0x20, 0x20); 2143 /* set address for mask 1 */ 2144 cec_write_clr_set(sd, 0x28, 0xf0, addr << 4); 2145 break; 2146 case 2: 2147 /* enable address mask 2 */ 2148 cec_write_clr_set(sd, 0x27, 0x40, 0x40); 2149 /* set address for mask 1 */ 2150 cec_write_clr_set(sd, 0x29, 0x0f, addr); 2151 break; 2152 } 2153 return 0; 2154 } 2155 2156 static int adv76xx_cec_adap_transmit(struct cec_adapter *adap, u8 attempts, 2157 u32 signal_free_time, struct cec_msg *msg) 2158 { 2159 struct adv76xx_state *state = cec_get_drvdata(adap); 2160 struct v4l2_subdev *sd = &state->sd; 2161 u8 len = msg->len; 2162 unsigned int i; 2163 2164 /* 2165 * The number of retries is the number of attempts - 1, but retry 2166 * at least once. It's not clear if a value of 0 is allowed, so 2167 * let's do at least one retry. 2168 */ 2169 cec_write_clr_set(sd, 0x12, 0x70, max(1, attempts - 1) << 4); 2170 2171 if (len > 16) { 2172 v4l2_err(sd, "%s: len exceeded 16 (%d)\n", __func__, len); 2173 return -EINVAL; 2174 } 2175 2176 /* write data */ 2177 for (i = 0; i < len; i++) 2178 cec_write(sd, i, msg->msg[i]); 2179 2180 /* set length (data + header) */ 2181 cec_write(sd, 0x10, len); 2182 /* start transmit, enable tx */ 2183 cec_write(sd, 0x11, 0x01); 2184 return 0; 2185 } 2186 2187 static const struct cec_adap_ops adv76xx_cec_adap_ops = { 2188 .adap_enable = adv76xx_cec_adap_enable, 2189 .adap_log_addr = adv76xx_cec_adap_log_addr, 2190 .adap_transmit = adv76xx_cec_adap_transmit, 2191 }; 2192 #endif 2193 2194 static int adv76xx_isr(struct v4l2_subdev *sd, u32 status, bool *handled) 2195 { 2196 struct adv76xx_state *state = to_state(sd); 2197 const struct adv76xx_chip_info *info = state->info; 2198 const u8 irq_reg_0x43 = io_read(sd, 0x43); 2199 const u8 irq_reg_0x6b = io_read(sd, 0x6b); 2200 const u8 irq_reg_0x70 = io_read(sd, 0x70); 2201 u8 fmt_change_digital; 2202 u8 fmt_change; 2203 u8 tx_5v; 2204 2205 if (irq_reg_0x43) 2206 io_write(sd, 0x44, irq_reg_0x43); 2207 if (irq_reg_0x70) 2208 io_write(sd, 0x71, irq_reg_0x70); 2209 if (irq_reg_0x6b) 2210 io_write(sd, 0x6c, irq_reg_0x6b); 2211 2212 v4l2_dbg(2, debug, sd, "%s: ", __func__); 2213 2214 /* format change */ 2215 fmt_change = irq_reg_0x43 & 0x98; 2216 fmt_change_digital = is_digital_input(sd) 2217 ? irq_reg_0x6b & info->fmt_change_digital_mask 2218 : 0; 2219 2220 if (fmt_change || fmt_change_digital) { 2221 v4l2_dbg(1, debug, sd, 2222 "%s: fmt_change = 0x%x, fmt_change_digital = 0x%x\n", 2223 __func__, fmt_change, fmt_change_digital); 2224 2225 v4l2_subdev_notify_event(sd, &adv76xx_ev_fmt); 2226 2227 if (handled) 2228 *handled = true; 2229 } 2230 /* HDMI/DVI mode */ 2231 if (irq_reg_0x6b & 0x01) { 2232 v4l2_dbg(1, debug, sd, "%s: irq %s mode\n", __func__, 2233 (io_read(sd, 0x6a) & 0x01) ? "HDMI" : "DVI"); 2234 set_rgb_quantization_range(sd); 2235 if (handled) 2236 *handled = true; 2237 } 2238 2239 #if IS_ENABLED(CONFIG_VIDEO_ADV7604_CEC) 2240 /* cec */ 2241 adv76xx_cec_isr(sd, handled); 2242 #endif 2243 2244 /* tx 5v detect */ 2245 tx_5v = irq_reg_0x70 & info->cable_det_mask; 2246 if (tx_5v) { 2247 v4l2_dbg(1, debug, sd, "%s: tx_5v: 0x%x\n", __func__, tx_5v); 2248 adv76xx_s_detect_tx_5v_ctrl(sd); 2249 if (handled) 2250 *handled = true; 2251 } 2252 return 0; 2253 } 2254 2255 static irqreturn_t adv76xx_irq_handler(int irq, void *dev_id) 2256 { 2257 struct adv76xx_state *state = dev_id; 2258 bool handled = false; 2259 2260 adv76xx_isr(&state->sd, 0, &handled); 2261 2262 return handled ? IRQ_HANDLED : IRQ_NONE; 2263 } 2264 2265 static int adv76xx_get_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid) 2266 { 2267 struct adv76xx_state *state = to_state(sd); 2268 u8 *data = NULL; 2269 2270 memset(edid->reserved, 0, sizeof(edid->reserved)); 2271 2272 switch (edid->pad) { 2273 case ADV76XX_PAD_HDMI_PORT_A: 2274 case ADV7604_PAD_HDMI_PORT_B: 2275 case ADV7604_PAD_HDMI_PORT_C: 2276 case ADV7604_PAD_HDMI_PORT_D: 2277 if (state->edid.present & (1 << edid->pad)) 2278 data = state->edid.edid; 2279 break; 2280 default: 2281 return -EINVAL; 2282 } 2283 2284 if (edid->start_block == 0 && edid->blocks == 0) { 2285 edid->blocks = data ? state->edid.blocks : 0; 2286 return 0; 2287 } 2288 2289 if (!data) 2290 return -ENODATA; 2291 2292 if (edid->start_block >= state->edid.blocks) 2293 return -EINVAL; 2294 2295 if (edid->start_block + edid->blocks > state->edid.blocks) 2296 edid->blocks = state->edid.blocks - edid->start_block; 2297 2298 memcpy(edid->edid, data + edid->start_block * 128, edid->blocks * 128); 2299 2300 return 0; 2301 } 2302 2303 static int adv76xx_set_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid) 2304 { 2305 struct adv76xx_state *state = to_state(sd); 2306 const struct adv76xx_chip_info *info = state->info; 2307 unsigned int spa_loc; 2308 u16 pa, parent_pa; 2309 int err; 2310 int i; 2311 2312 memset(edid->reserved, 0, sizeof(edid->reserved)); 2313 2314 if (edid->pad > ADV7604_PAD_HDMI_PORT_D) 2315 return -EINVAL; 2316 if (edid->start_block != 0) 2317 return -EINVAL; 2318 if (edid->blocks == 0) { 2319 /* Disable hotplug and I2C access to EDID RAM from DDC port */ 2320 state->edid.present &= ~(1 << edid->pad); 2321 adv76xx_set_hpd(state, state->edid.present); 2322 rep_write_clr_set(sd, info->edid_enable_reg, 0x0f, state->edid.present); 2323 2324 /* Fall back to a 16:9 aspect ratio */ 2325 state->aspect_ratio.numerator = 16; 2326 state->aspect_ratio.denominator = 9; 2327 2328 if (!state->edid.present) { 2329 state->edid.blocks = 0; 2330 cec_phys_addr_invalidate(state->cec_adap); 2331 } 2332 2333 v4l2_dbg(2, debug, sd, "%s: clear EDID pad %d, edid.present = 0x%x\n", 2334 __func__, edid->pad, state->edid.present); 2335 return 0; 2336 } 2337 if (edid->blocks > 2) { 2338 edid->blocks = 2; 2339 return -E2BIG; 2340 } 2341 pa = v4l2_get_edid_phys_addr(edid->edid, edid->blocks * 128, &spa_loc); 2342 err = v4l2_phys_addr_validate(pa, &parent_pa, NULL); 2343 if (err) 2344 return err; 2345 2346 v4l2_dbg(2, debug, sd, "%s: write EDID pad %d, edid.present = 0x%x\n", 2347 __func__, edid->pad, state->edid.present); 2348 2349 /* Disable hotplug and I2C access to EDID RAM from DDC port */ 2350 cancel_delayed_work_sync(&state->delayed_work_enable_hotplug); 2351 adv76xx_set_hpd(state, 0); 2352 rep_write_clr_set(sd, info->edid_enable_reg, 0x0f, 0x00); 2353 2354 /* 2355 * Return an error if no location of the source physical address 2356 * was found. 2357 */ 2358 if (edid->blocks > 1 && spa_loc == 0) 2359 return -EINVAL; 2360 2361 switch (edid->pad) { 2362 case ADV76XX_PAD_HDMI_PORT_A: 2363 state->spa_port_a[0] = pa >> 8; 2364 state->spa_port_a[1] = pa & 0xff; 2365 break; 2366 case ADV7604_PAD_HDMI_PORT_B: 2367 rep_write(sd, 0x70, pa >> 8); 2368 rep_write(sd, 0x71, pa & 0xff); 2369 break; 2370 case ADV7604_PAD_HDMI_PORT_C: 2371 rep_write(sd, 0x72, pa >> 8); 2372 rep_write(sd, 0x73, pa & 0xff); 2373 break; 2374 case ADV7604_PAD_HDMI_PORT_D: 2375 rep_write(sd, 0x74, pa >> 8); 2376 rep_write(sd, 0x75, pa & 0xff); 2377 break; 2378 default: 2379 return -EINVAL; 2380 } 2381 2382 if (info->type == ADV7604) { 2383 rep_write(sd, 0x76, spa_loc & 0xff); 2384 rep_write_clr_set(sd, 0x77, 0x40, (spa_loc & 0x100) >> 2); 2385 } else { 2386 /* ADV7612 Software Manual Rev. A, p. 15 */ 2387 rep_write(sd, 0x70, spa_loc & 0xff); 2388 rep_write_clr_set(sd, 0x71, 0x01, (spa_loc & 0x100) >> 8); 2389 } 2390 2391 if (spa_loc) { 2392 edid->edid[spa_loc] = state->spa_port_a[0]; 2393 edid->edid[spa_loc + 1] = state->spa_port_a[1]; 2394 } 2395 2396 memcpy(state->edid.edid, edid->edid, 128 * edid->blocks); 2397 state->edid.blocks = edid->blocks; 2398 state->aspect_ratio = v4l2_calc_aspect_ratio(edid->edid[0x15], 2399 edid->edid[0x16]); 2400 state->edid.present |= 1 << edid->pad; 2401 2402 err = edid_write_block(sd, 128 * edid->blocks, state->edid.edid); 2403 if (err < 0) { 2404 v4l2_err(sd, "error %d writing edid pad %d\n", err, edid->pad); 2405 return err; 2406 } 2407 2408 /* adv76xx calculates the checksums and enables I2C access to internal 2409 EDID RAM from DDC port. */ 2410 rep_write_clr_set(sd, info->edid_enable_reg, 0x0f, state->edid.present); 2411 2412 for (i = 0; i < 1000; i++) { 2413 if (rep_read(sd, info->edid_status_reg) & state->edid.present) 2414 break; 2415 mdelay(1); 2416 } 2417 if (i == 1000) { 2418 v4l2_err(sd, "error enabling edid (0x%x)\n", state->edid.present); 2419 return -EIO; 2420 } 2421 cec_s_phys_addr(state->cec_adap, parent_pa, false); 2422 2423 /* enable hotplug after 100 ms */ 2424 schedule_delayed_work(&state->delayed_work_enable_hotplug, HZ / 10); 2425 return 0; 2426 } 2427 2428 /*********** avi info frame CEA-861-E **************/ 2429 2430 static const struct adv76xx_cfg_read_infoframe adv76xx_cri[] = { 2431 { "AVI", 0x01, 0xe0, 0x00 }, 2432 { "Audio", 0x02, 0xe3, 0x1c }, 2433 { "SDP", 0x04, 0xe6, 0x2a }, 2434 { "Vendor", 0x10, 0xec, 0x54 } 2435 }; 2436 2437 static int adv76xx_read_infoframe(struct v4l2_subdev *sd, int index, 2438 union hdmi_infoframe *frame) 2439 { 2440 uint8_t buffer[32]; 2441 u8 len; 2442 int i; 2443 2444 if (!(io_read(sd, 0x60) & adv76xx_cri[index].present_mask)) { 2445 v4l2_info(sd, "%s infoframe not received\n", 2446 adv76xx_cri[index].desc); 2447 return -ENOENT; 2448 } 2449 2450 for (i = 0; i < 3; i++) 2451 buffer[i] = infoframe_read(sd, 2452 adv76xx_cri[index].head_addr + i); 2453 2454 len = buffer[2] + 1; 2455 2456 if (len + 3 > sizeof(buffer)) { 2457 v4l2_err(sd, "%s: invalid %s infoframe length %d\n", __func__, 2458 adv76xx_cri[index].desc, len); 2459 return -ENOENT; 2460 } 2461 2462 for (i = 0; i < len; i++) 2463 buffer[i + 3] = infoframe_read(sd, 2464 adv76xx_cri[index].payload_addr + i); 2465 2466 if (hdmi_infoframe_unpack(frame, buffer, sizeof(buffer)) < 0) { 2467 v4l2_err(sd, "%s: unpack of %s infoframe failed\n", __func__, 2468 adv76xx_cri[index].desc); 2469 return -ENOENT; 2470 } 2471 return 0; 2472 } 2473 2474 static void adv76xx_log_infoframes(struct v4l2_subdev *sd) 2475 { 2476 int i; 2477 2478 if (!is_hdmi(sd)) { 2479 v4l2_info(sd, "receive DVI-D signal, no infoframes\n"); 2480 return; 2481 } 2482 2483 for (i = 0; i < ARRAY_SIZE(adv76xx_cri); i++) { 2484 union hdmi_infoframe frame; 2485 struct i2c_client *client = v4l2_get_subdevdata(sd); 2486 2487 if (adv76xx_read_infoframe(sd, i, &frame)) 2488 return; 2489 hdmi_infoframe_log(KERN_INFO, &client->dev, &frame); 2490 } 2491 } 2492 2493 static int adv76xx_log_status(struct v4l2_subdev *sd) 2494 { 2495 struct adv76xx_state *state = to_state(sd); 2496 const struct adv76xx_chip_info *info = state->info; 2497 struct v4l2_dv_timings timings; 2498 struct stdi_readback stdi; 2499 u8 reg_io_0x02 = io_read(sd, 0x02); 2500 u8 edid_enabled; 2501 u8 cable_det; 2502 2503 static const char * const csc_coeff_sel_rb[16] = { 2504 "bypassed", "YPbPr601 -> RGB", "reserved", "YPbPr709 -> RGB", 2505 "reserved", "RGB -> YPbPr601", "reserved", "RGB -> YPbPr709", 2506 "reserved", "YPbPr709 -> YPbPr601", "YPbPr601 -> YPbPr709", 2507 "reserved", "reserved", "reserved", "reserved", "manual" 2508 }; 2509 static const char * const input_color_space_txt[16] = { 2510 "RGB limited range (16-235)", "RGB full range (0-255)", 2511 "YCbCr Bt.601 (16-235)", "YCbCr Bt.709 (16-235)", 2512 "xvYCC Bt.601", "xvYCC Bt.709", 2513 "YCbCr Bt.601 (0-255)", "YCbCr Bt.709 (0-255)", 2514 "invalid", "invalid", "invalid", "invalid", "invalid", 2515 "invalid", "invalid", "automatic" 2516 }; 2517 static const char * const hdmi_color_space_txt[16] = { 2518 "RGB limited range (16-235)", "RGB full range (0-255)", 2519 "YCbCr Bt.601 (16-235)", "YCbCr Bt.709 (16-235)", 2520 "xvYCC Bt.601", "xvYCC Bt.709", 2521 "YCbCr Bt.601 (0-255)", "YCbCr Bt.709 (0-255)", 2522 "sYCC", "opYCC 601", "opRGB", "invalid", "invalid", 2523 "invalid", "invalid", "invalid" 2524 }; 2525 static const char * const rgb_quantization_range_txt[] = { 2526 "Automatic", 2527 "RGB limited range (16-235)", 2528 "RGB full range (0-255)", 2529 }; 2530 static const char * const deep_color_mode_txt[4] = { 2531 "8-bits per channel", 2532 "10-bits per channel", 2533 "12-bits per channel", 2534 "16-bits per channel (not supported)" 2535 }; 2536 2537 v4l2_info(sd, "-----Chip status-----\n"); 2538 v4l2_info(sd, "Chip power: %s\n", no_power(sd) ? "off" : "on"); 2539 edid_enabled = rep_read(sd, info->edid_status_reg); 2540 v4l2_info(sd, "EDID enabled port A: %s, B: %s, C: %s, D: %s\n", 2541 ((edid_enabled & 0x01) ? "Yes" : "No"), 2542 ((edid_enabled & 0x02) ? "Yes" : "No"), 2543 ((edid_enabled & 0x04) ? "Yes" : "No"), 2544 ((edid_enabled & 0x08) ? "Yes" : "No")); 2545 v4l2_info(sd, "CEC: %s\n", state->cec_enabled_adap ? 2546 "enabled" : "disabled"); 2547 if (state->cec_enabled_adap) { 2548 int i; 2549 2550 for (i = 0; i < ADV76XX_MAX_ADDRS; i++) { 2551 bool is_valid = state->cec_valid_addrs & (1 << i); 2552 2553 if (is_valid) 2554 v4l2_info(sd, "CEC Logical Address: 0x%x\n", 2555 state->cec_addr[i]); 2556 } 2557 } 2558 2559 v4l2_info(sd, "-----Signal status-----\n"); 2560 cable_det = info->read_cable_det(sd); 2561 v4l2_info(sd, "Cable detected (+5V power) port A: %s, B: %s, C: %s, D: %s\n", 2562 ((cable_det & 0x01) ? "Yes" : "No"), 2563 ((cable_det & 0x02) ? "Yes" : "No"), 2564 ((cable_det & 0x04) ? "Yes" : "No"), 2565 ((cable_det & 0x08) ? "Yes" : "No")); 2566 v4l2_info(sd, "TMDS signal detected: %s\n", 2567 no_signal_tmds(sd) ? "false" : "true"); 2568 v4l2_info(sd, "TMDS signal locked: %s\n", 2569 no_lock_tmds(sd) ? "false" : "true"); 2570 v4l2_info(sd, "SSPD locked: %s\n", no_lock_sspd(sd) ? "false" : "true"); 2571 v4l2_info(sd, "STDI locked: %s\n", no_lock_stdi(sd) ? "false" : "true"); 2572 v4l2_info(sd, "CP locked: %s\n", no_lock_cp(sd) ? "false" : "true"); 2573 v4l2_info(sd, "CP free run: %s\n", 2574 (in_free_run(sd)) ? "on" : "off"); 2575 v4l2_info(sd, "Prim-mode = 0x%x, video std = 0x%x, v_freq = 0x%x\n", 2576 io_read(sd, 0x01) & 0x0f, io_read(sd, 0x00) & 0x3f, 2577 (io_read(sd, 0x01) & 0x70) >> 4); 2578 2579 v4l2_info(sd, "-----Video Timings-----\n"); 2580 if (read_stdi(sd, &stdi)) 2581 v4l2_info(sd, "STDI: not locked\n"); 2582 else 2583 v4l2_info(sd, "STDI: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %s, %chsync, %cvsync\n", 2584 stdi.lcf, stdi.bl, stdi.lcvs, 2585 stdi.interlaced ? "interlaced" : "progressive", 2586 stdi.hs_pol, stdi.vs_pol); 2587 if (adv76xx_query_dv_timings(sd, &timings)) 2588 v4l2_info(sd, "No video detected\n"); 2589 else 2590 v4l2_print_dv_timings(sd->name, "Detected format: ", 2591 &timings, true); 2592 v4l2_print_dv_timings(sd->name, "Configured format: ", 2593 &state->timings, true); 2594 2595 if (no_signal(sd)) 2596 return 0; 2597 2598 v4l2_info(sd, "-----Color space-----\n"); 2599 v4l2_info(sd, "RGB quantization range ctrl: %s\n", 2600 rgb_quantization_range_txt[state->rgb_quantization_range]); 2601 v4l2_info(sd, "Input color space: %s\n", 2602 input_color_space_txt[reg_io_0x02 >> 4]); 2603 v4l2_info(sd, "Output color space: %s %s, alt-gamma %s\n", 2604 (reg_io_0x02 & 0x02) ? "RGB" : "YCbCr", 2605 (((reg_io_0x02 >> 2) & 0x01) ^ (reg_io_0x02 & 0x01)) ? 2606 "(16-235)" : "(0-255)", 2607 (reg_io_0x02 & 0x08) ? "enabled" : "disabled"); 2608 v4l2_info(sd, "Color space conversion: %s\n", 2609 csc_coeff_sel_rb[cp_read(sd, info->cp_csc) >> 4]); 2610 2611 if (!is_digital_input(sd)) 2612 return 0; 2613 2614 v4l2_info(sd, "-----%s status-----\n", is_hdmi(sd) ? "HDMI" : "DVI-D"); 2615 v4l2_info(sd, "Digital video port selected: %c\n", 2616 (hdmi_read(sd, 0x00) & 0x03) + 'A'); 2617 v4l2_info(sd, "HDCP encrypted content: %s\n", 2618 (hdmi_read(sd, 0x05) & 0x40) ? "true" : "false"); 2619 v4l2_info(sd, "HDCP keys read: %s%s\n", 2620 (hdmi_read(sd, 0x04) & 0x20) ? "yes" : "no", 2621 (hdmi_read(sd, 0x04) & 0x10) ? "ERROR" : ""); 2622 if (is_hdmi(sd)) { 2623 bool audio_pll_locked = hdmi_read(sd, 0x04) & 0x01; 2624 bool audio_sample_packet_detect = hdmi_read(sd, 0x18) & 0x01; 2625 bool audio_mute = io_read(sd, 0x65) & 0x40; 2626 2627 v4l2_info(sd, "Audio: pll %s, samples %s, %s\n", 2628 audio_pll_locked ? "locked" : "not locked", 2629 audio_sample_packet_detect ? "detected" : "not detected", 2630 audio_mute ? "muted" : "enabled"); 2631 if (audio_pll_locked && audio_sample_packet_detect) { 2632 v4l2_info(sd, "Audio format: %s\n", 2633 (hdmi_read(sd, 0x07) & 0x20) ? "multi-channel" : "stereo"); 2634 } 2635 v4l2_info(sd, "Audio CTS: %u\n", (hdmi_read(sd, 0x5b) << 12) + 2636 (hdmi_read(sd, 0x5c) << 8) + 2637 (hdmi_read(sd, 0x5d) & 0xf0)); 2638 v4l2_info(sd, "Audio N: %u\n", ((hdmi_read(sd, 0x5d) & 0x0f) << 16) + 2639 (hdmi_read(sd, 0x5e) << 8) + 2640 hdmi_read(sd, 0x5f)); 2641 v4l2_info(sd, "AV Mute: %s\n", (hdmi_read(sd, 0x04) & 0x40) ? "on" : "off"); 2642 2643 v4l2_info(sd, "Deep color mode: %s\n", deep_color_mode_txt[(hdmi_read(sd, 0x0b) & 0x60) >> 5]); 2644 v4l2_info(sd, "HDMI colorspace: %s\n", hdmi_color_space_txt[hdmi_read(sd, 0x53) & 0xf]); 2645 2646 adv76xx_log_infoframes(sd); 2647 } 2648 2649 return 0; 2650 } 2651 2652 static int adv76xx_subscribe_event(struct v4l2_subdev *sd, 2653 struct v4l2_fh *fh, 2654 struct v4l2_event_subscription *sub) 2655 { 2656 switch (sub->type) { 2657 case V4L2_EVENT_SOURCE_CHANGE: 2658 return v4l2_src_change_event_subdev_subscribe(sd, fh, sub); 2659 case V4L2_EVENT_CTRL: 2660 return v4l2_ctrl_subdev_subscribe_event(sd, fh, sub); 2661 default: 2662 return -EINVAL; 2663 } 2664 } 2665 2666 static int adv76xx_registered(struct v4l2_subdev *sd) 2667 { 2668 struct adv76xx_state *state = to_state(sd); 2669 struct i2c_client *client = v4l2_get_subdevdata(sd); 2670 int err; 2671 2672 err = cec_register_adapter(state->cec_adap, &client->dev); 2673 if (err) 2674 cec_delete_adapter(state->cec_adap); 2675 return err; 2676 } 2677 2678 static void adv76xx_unregistered(struct v4l2_subdev *sd) 2679 { 2680 struct adv76xx_state *state = to_state(sd); 2681 2682 cec_unregister_adapter(state->cec_adap); 2683 } 2684 2685 /* ----------------------------------------------------------------------- */ 2686 2687 static const struct v4l2_ctrl_ops adv76xx_ctrl_ops = { 2688 .s_ctrl = adv76xx_s_ctrl, 2689 .g_volatile_ctrl = adv76xx_g_volatile_ctrl, 2690 }; 2691 2692 static const struct v4l2_subdev_core_ops adv76xx_core_ops = { 2693 .log_status = adv76xx_log_status, 2694 .interrupt_service_routine = adv76xx_isr, 2695 .subscribe_event = adv76xx_subscribe_event, 2696 .unsubscribe_event = v4l2_event_subdev_unsubscribe, 2697 #ifdef CONFIG_VIDEO_ADV_DEBUG 2698 .g_register = adv76xx_g_register, 2699 .s_register = adv76xx_s_register, 2700 #endif 2701 }; 2702 2703 static const struct v4l2_subdev_video_ops adv76xx_video_ops = { 2704 .s_routing = adv76xx_s_routing, 2705 .g_input_status = adv76xx_g_input_status, 2706 .s_dv_timings = adv76xx_s_dv_timings, 2707 .g_dv_timings = adv76xx_g_dv_timings, 2708 .query_dv_timings = adv76xx_query_dv_timings, 2709 }; 2710 2711 static const struct v4l2_subdev_pad_ops adv76xx_pad_ops = { 2712 .enum_mbus_code = adv76xx_enum_mbus_code, 2713 .get_selection = adv76xx_get_selection, 2714 .get_fmt = adv76xx_get_format, 2715 .set_fmt = adv76xx_set_format, 2716 .get_edid = adv76xx_get_edid, 2717 .set_edid = adv76xx_set_edid, 2718 .dv_timings_cap = adv76xx_dv_timings_cap, 2719 .enum_dv_timings = adv76xx_enum_dv_timings, 2720 }; 2721 2722 static const struct v4l2_subdev_ops adv76xx_ops = { 2723 .core = &adv76xx_core_ops, 2724 .video = &adv76xx_video_ops, 2725 .pad = &adv76xx_pad_ops, 2726 }; 2727 2728 static const struct v4l2_subdev_internal_ops adv76xx_int_ops = { 2729 .registered = adv76xx_registered, 2730 .unregistered = adv76xx_unregistered, 2731 }; 2732 2733 /* -------------------------- custom ctrls ---------------------------------- */ 2734 2735 static const struct v4l2_ctrl_config adv7604_ctrl_analog_sampling_phase = { 2736 .ops = &adv76xx_ctrl_ops, 2737 .id = V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE, 2738 .name = "Analog Sampling Phase", 2739 .type = V4L2_CTRL_TYPE_INTEGER, 2740 .min = 0, 2741 .max = 0x1f, 2742 .step = 1, 2743 .def = 0, 2744 }; 2745 2746 static const struct v4l2_ctrl_config adv76xx_ctrl_free_run_color_manual = { 2747 .ops = &adv76xx_ctrl_ops, 2748 .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL, 2749 .name = "Free Running Color, Manual", 2750 .type = V4L2_CTRL_TYPE_BOOLEAN, 2751 .min = false, 2752 .max = true, 2753 .step = 1, 2754 .def = false, 2755 }; 2756 2757 static const struct v4l2_ctrl_config adv76xx_ctrl_free_run_color = { 2758 .ops = &adv76xx_ctrl_ops, 2759 .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR, 2760 .name = "Free Running Color", 2761 .type = V4L2_CTRL_TYPE_INTEGER, 2762 .min = 0x0, 2763 .max = 0xffffff, 2764 .step = 0x1, 2765 .def = 0x0, 2766 }; 2767 2768 /* ----------------------------------------------------------------------- */ 2769 2770 struct adv76xx_register_map { 2771 const char *name; 2772 u8 default_addr; 2773 }; 2774 2775 static const struct adv76xx_register_map adv76xx_default_addresses[] = { 2776 [ADV76XX_PAGE_IO] = { "main", 0x4c }, 2777 [ADV7604_PAGE_AVLINK] = { "avlink", 0x42 }, 2778 [ADV76XX_PAGE_CEC] = { "cec", 0x40 }, 2779 [ADV76XX_PAGE_INFOFRAME] = { "infoframe", 0x3e }, 2780 [ADV7604_PAGE_ESDP] = { "esdp", 0x38 }, 2781 [ADV7604_PAGE_DPP] = { "dpp", 0x3c }, 2782 [ADV76XX_PAGE_AFE] = { "afe", 0x26 }, 2783 [ADV76XX_PAGE_REP] = { "rep", 0x32 }, 2784 [ADV76XX_PAGE_EDID] = { "edid", 0x36 }, 2785 [ADV76XX_PAGE_HDMI] = { "hdmi", 0x34 }, 2786 [ADV76XX_PAGE_TEST] = { "test", 0x30 }, 2787 [ADV76XX_PAGE_CP] = { "cp", 0x22 }, 2788 [ADV7604_PAGE_VDP] = { "vdp", 0x24 }, 2789 }; 2790 2791 static int adv76xx_core_init(struct v4l2_subdev *sd) 2792 { 2793 struct adv76xx_state *state = to_state(sd); 2794 const struct adv76xx_chip_info *info = state->info; 2795 struct adv76xx_platform_data *pdata = &state->pdata; 2796 2797 hdmi_write(sd, 0x48, 2798 (pdata->disable_pwrdnb ? 0x80 : 0) | 2799 (pdata->disable_cable_det_rst ? 0x40 : 0)); 2800 2801 disable_input(sd); 2802 2803 if (pdata->default_input >= 0 && 2804 pdata->default_input < state->source_pad) { 2805 state->selected_input = pdata->default_input; 2806 select_input(sd); 2807 enable_input(sd); 2808 } 2809 2810 /* power */ 2811 io_write(sd, 0x0c, 0x42); /* Power up part and power down VDP */ 2812 io_write(sd, 0x0b, 0x44); /* Power down ESDP block */ 2813 cp_write(sd, 0xcf, 0x01); /* Power down macrovision */ 2814 2815 /* HPD */ 2816 if (info->type != ADV7604) { 2817 /* Set manual HPD values to 0 */ 2818 io_write_clr_set(sd, 0x20, 0xc0, 0); 2819 /* 2820 * Set HPA_DELAY to 200 ms and set automatic HPD control 2821 * to: internal EDID is active AND a cable is detected 2822 * AND the manual HPD control is set to 1. 2823 */ 2824 hdmi_write_clr_set(sd, 0x6c, 0xf6, 0x26); 2825 } 2826 2827 /* video format */ 2828 io_write_clr_set(sd, 0x02, 0x0f, pdata->alt_gamma << 3); 2829 io_write_clr_set(sd, 0x05, 0x0e, pdata->blank_data << 3 | 2830 pdata->insert_av_codes << 2 | 2831 pdata->replicate_av_codes << 1); 2832 adv76xx_setup_format(state); 2833 2834 cp_write(sd, 0x69, 0x30); /* Enable CP CSC */ 2835 2836 /* VS, HS polarities */ 2837 io_write(sd, 0x06, 0xa0 | pdata->inv_vs_pol << 2 | 2838 pdata->inv_hs_pol << 1 | pdata->inv_llc_pol); 2839 2840 /* Adjust drive strength */ 2841 io_write(sd, 0x14, 0x40 | pdata->dr_str_data << 4 | 2842 pdata->dr_str_clk << 2 | 2843 pdata->dr_str_sync); 2844 2845 cp_write(sd, 0xba, (pdata->hdmi_free_run_mode << 1) | 0x01); /* HDMI free run */ 2846 cp_write(sd, 0xf3, 0xdc); /* Low threshold to enter/exit free run mode */ 2847 cp_write(sd, 0xf9, 0x23); /* STDI ch. 1 - LCVS change threshold - 2848 ADI recommended setting [REF_01, c. 2.3.3] */ 2849 cp_write(sd, 0x45, 0x23); /* STDI ch. 2 - LCVS change threshold - 2850 ADI recommended setting [REF_01, c. 2.3.3] */ 2851 cp_write(sd, 0xc9, 0x2d); /* use prim_mode and vid_std as free run resolution 2852 for digital formats */ 2853 2854 /* HDMI audio */ 2855 hdmi_write_clr_set(sd, 0x15, 0x03, 0x03); /* Mute on FIFO over-/underflow [REF_01, c. 1.2.18] */ 2856 hdmi_write_clr_set(sd, 0x1a, 0x0e, 0x08); /* Wait 1 s before unmute */ 2857 hdmi_write_clr_set(sd, 0x68, 0x06, 0x06); /* FIFO reset on over-/underflow [REF_01, c. 1.2.19] */ 2858 2859 /* TODO from platform data */ 2860 afe_write(sd, 0xb5, 0x01); /* Setting MCLK to 256Fs */ 2861 2862 if (adv76xx_has_afe(state)) { 2863 afe_write(sd, 0x02, pdata->ain_sel); /* Select analog input muxing mode */ 2864 io_write_clr_set(sd, 0x30, 1 << 4, pdata->output_bus_lsb_to_msb << 4); 2865 } 2866 2867 /* interrupts */ 2868 io_write(sd, 0x40, 0xc0 | pdata->int1_config); /* Configure INT1 */ 2869 io_write(sd, 0x46, 0x98); /* Enable SSPD, STDI and CP unlocked interrupts */ 2870 io_write(sd, 0x6e, info->fmt_change_digital_mask); /* Enable V_LOCKED and DE_REGEN_LCK interrupts */ 2871 io_write(sd, 0x73, info->cable_det_mask); /* Enable cable detection (+5v) interrupts */ 2872 info->setup_irqs(sd); 2873 2874 return v4l2_ctrl_handler_setup(sd->ctrl_handler); 2875 } 2876 2877 static void adv7604_setup_irqs(struct v4l2_subdev *sd) 2878 { 2879 io_write(sd, 0x41, 0xd7); /* STDI irq for any change, disable INT2 */ 2880 } 2881 2882 static void adv7611_setup_irqs(struct v4l2_subdev *sd) 2883 { 2884 io_write(sd, 0x41, 0xd0); /* STDI irq for any change, disable INT2 */ 2885 } 2886 2887 static void adv7612_setup_irqs(struct v4l2_subdev *sd) 2888 { 2889 io_write(sd, 0x41, 0xd0); /* disable INT2 */ 2890 } 2891 2892 static void adv76xx_unregister_clients(struct adv76xx_state *state) 2893 { 2894 unsigned int i; 2895 2896 for (i = 1; i < ARRAY_SIZE(state->i2c_clients); ++i) 2897 i2c_unregister_device(state->i2c_clients[i]); 2898 } 2899 2900 static struct i2c_client *adv76xx_dummy_client(struct v4l2_subdev *sd, 2901 unsigned int page) 2902 { 2903 struct i2c_client *client = v4l2_get_subdevdata(sd); 2904 struct adv76xx_state *state = to_state(sd); 2905 struct adv76xx_platform_data *pdata = &state->pdata; 2906 unsigned int io_reg = 0xf2 + page; 2907 struct i2c_client *new_client; 2908 2909 if (pdata && pdata->i2c_addresses[page]) 2910 new_client = i2c_new_dummy_device(client->adapter, 2911 pdata->i2c_addresses[page]); 2912 else 2913 new_client = i2c_new_ancillary_device(client, 2914 adv76xx_default_addresses[page].name, 2915 adv76xx_default_addresses[page].default_addr); 2916 2917 if (!IS_ERR(new_client)) 2918 io_write(sd, io_reg, new_client->addr << 1); 2919 2920 return new_client; 2921 } 2922 2923 static const struct adv76xx_reg_seq adv7604_recommended_settings_afe[] = { 2924 /* reset ADI recommended settings for HDMI: */ 2925 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 4. */ 2926 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x0d), 0x04 }, /* HDMI filter optimization */ 2927 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x0d), 0x04 }, /* HDMI filter optimization */ 2928 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x3d), 0x00 }, /* DDC bus active pull-up control */ 2929 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x3e), 0x74 }, /* TMDS PLL optimization */ 2930 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x4e), 0x3b }, /* TMDS PLL optimization */ 2931 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x57), 0x74 }, /* TMDS PLL optimization */ 2932 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x58), 0x63 }, /* TMDS PLL optimization */ 2933 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8d), 0x18 }, /* equaliser */ 2934 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8e), 0x34 }, /* equaliser */ 2935 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x93), 0x88 }, /* equaliser */ 2936 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x94), 0x2e }, /* equaliser */ 2937 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x96), 0x00 }, /* enable automatic EQ changing */ 2938 2939 /* set ADI recommended settings for digitizer */ 2940 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 17. */ 2941 { ADV76XX_REG(ADV76XX_PAGE_AFE, 0x12), 0x7b }, /* ADC noise shaping filter controls */ 2942 { ADV76XX_REG(ADV76XX_PAGE_AFE, 0x0c), 0x1f }, /* CP core gain controls */ 2943 { ADV76XX_REG(ADV76XX_PAGE_CP, 0x3e), 0x04 }, /* CP core pre-gain control */ 2944 { ADV76XX_REG(ADV76XX_PAGE_CP, 0xc3), 0x39 }, /* CP coast control. Graphics mode */ 2945 { ADV76XX_REG(ADV76XX_PAGE_CP, 0x40), 0x5c }, /* CP core pre-gain control. Graphics mode */ 2946 2947 { ADV76XX_REG_SEQ_TERM, 0 }, 2948 }; 2949 2950 static const struct adv76xx_reg_seq adv7604_recommended_settings_hdmi[] = { 2951 /* set ADI recommended settings for HDMI: */ 2952 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 4. */ 2953 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x0d), 0x84 }, /* HDMI filter optimization */ 2954 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x3d), 0x10 }, /* DDC bus active pull-up control */ 2955 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x3e), 0x39 }, /* TMDS PLL optimization */ 2956 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x4e), 0x3b }, /* TMDS PLL optimization */ 2957 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x57), 0xb6 }, /* TMDS PLL optimization */ 2958 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x58), 0x03 }, /* TMDS PLL optimization */ 2959 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8d), 0x18 }, /* equaliser */ 2960 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8e), 0x34 }, /* equaliser */ 2961 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x93), 0x8b }, /* equaliser */ 2962 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x94), 0x2d }, /* equaliser */ 2963 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x96), 0x01 }, /* enable automatic EQ changing */ 2964 2965 /* reset ADI recommended settings for digitizer */ 2966 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 17. */ 2967 { ADV76XX_REG(ADV76XX_PAGE_AFE, 0x12), 0xfb }, /* ADC noise shaping filter controls */ 2968 { ADV76XX_REG(ADV76XX_PAGE_AFE, 0x0c), 0x0d }, /* CP core gain controls */ 2969 2970 { ADV76XX_REG_SEQ_TERM, 0 }, 2971 }; 2972 2973 static const struct adv76xx_reg_seq adv7611_recommended_settings_hdmi[] = { 2974 /* ADV7611 Register Settings Recommendations Rev 1.5, May 2014 */ 2975 { ADV76XX_REG(ADV76XX_PAGE_CP, 0x6c), 0x00 }, 2976 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x9b), 0x03 }, 2977 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x6f), 0x08 }, 2978 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x85), 0x1f }, 2979 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x87), 0x70 }, 2980 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x57), 0xda }, 2981 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x58), 0x01 }, 2982 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x03), 0x98 }, 2983 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x4c), 0x44 }, 2984 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8d), 0x04 }, 2985 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8e), 0x1e }, 2986 2987 { ADV76XX_REG_SEQ_TERM, 0 }, 2988 }; 2989 2990 static const struct adv76xx_reg_seq adv7612_recommended_settings_hdmi[] = { 2991 { ADV76XX_REG(ADV76XX_PAGE_CP, 0x6c), 0x00 }, 2992 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x9b), 0x03 }, 2993 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x6f), 0x08 }, 2994 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x85), 0x1f }, 2995 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x87), 0x70 }, 2996 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x57), 0xda }, 2997 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x58), 0x01 }, 2998 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x03), 0x98 }, 2999 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x4c), 0x44 }, 3000 { ADV76XX_REG_SEQ_TERM, 0 }, 3001 }; 3002 3003 static const struct adv76xx_chip_info adv76xx_chip_info[] = { 3004 [ADV7604] = { 3005 .type = ADV7604, 3006 .has_afe = true, 3007 .max_port = ADV7604_PAD_VGA_COMP, 3008 .num_dv_ports = 4, 3009 .edid_enable_reg = 0x77, 3010 .edid_status_reg = 0x7d, 3011 .lcf_reg = 0xb3, 3012 .tdms_lock_mask = 0xe0, 3013 .cable_det_mask = 0x1e, 3014 .fmt_change_digital_mask = 0xc1, 3015 .cp_csc = 0xfc, 3016 .cec_irq_status = 0x4d, 3017 .cec_rx_enable = 0x26, 3018 .cec_rx_enable_mask = 0x01, 3019 .cec_irq_swap = true, 3020 .formats = adv7604_formats, 3021 .nformats = ARRAY_SIZE(adv7604_formats), 3022 .set_termination = adv7604_set_termination, 3023 .setup_irqs = adv7604_setup_irqs, 3024 .read_hdmi_pixelclock = adv7604_read_hdmi_pixelclock, 3025 .read_cable_det = adv7604_read_cable_det, 3026 .recommended_settings = { 3027 [0] = adv7604_recommended_settings_afe, 3028 [1] = adv7604_recommended_settings_hdmi, 3029 }, 3030 .num_recommended_settings = { 3031 [0] = ARRAY_SIZE(adv7604_recommended_settings_afe), 3032 [1] = ARRAY_SIZE(adv7604_recommended_settings_hdmi), 3033 }, 3034 .page_mask = BIT(ADV76XX_PAGE_IO) | BIT(ADV7604_PAGE_AVLINK) | 3035 BIT(ADV76XX_PAGE_CEC) | BIT(ADV76XX_PAGE_INFOFRAME) | 3036 BIT(ADV7604_PAGE_ESDP) | BIT(ADV7604_PAGE_DPP) | 3037 BIT(ADV76XX_PAGE_AFE) | BIT(ADV76XX_PAGE_REP) | 3038 BIT(ADV76XX_PAGE_EDID) | BIT(ADV76XX_PAGE_HDMI) | 3039 BIT(ADV76XX_PAGE_TEST) | BIT(ADV76XX_PAGE_CP) | 3040 BIT(ADV7604_PAGE_VDP), 3041 .linewidth_mask = 0xfff, 3042 .field0_height_mask = 0xfff, 3043 .field1_height_mask = 0xfff, 3044 .hfrontporch_mask = 0x3ff, 3045 .hsync_mask = 0x3ff, 3046 .hbackporch_mask = 0x3ff, 3047 .field0_vfrontporch_mask = 0x1fff, 3048 .field0_vsync_mask = 0x1fff, 3049 .field0_vbackporch_mask = 0x1fff, 3050 .field1_vfrontporch_mask = 0x1fff, 3051 .field1_vsync_mask = 0x1fff, 3052 .field1_vbackporch_mask = 0x1fff, 3053 }, 3054 [ADV7611] = { 3055 .type = ADV7611, 3056 .has_afe = false, 3057 .max_port = ADV76XX_PAD_HDMI_PORT_A, 3058 .num_dv_ports = 1, 3059 .edid_enable_reg = 0x74, 3060 .edid_status_reg = 0x76, 3061 .lcf_reg = 0xa3, 3062 .tdms_lock_mask = 0x43, 3063 .cable_det_mask = 0x01, 3064 .fmt_change_digital_mask = 0x03, 3065 .cp_csc = 0xf4, 3066 .cec_irq_status = 0x93, 3067 .cec_rx_enable = 0x2c, 3068 .cec_rx_enable_mask = 0x02, 3069 .formats = adv7611_formats, 3070 .nformats = ARRAY_SIZE(adv7611_formats), 3071 .set_termination = adv7611_set_termination, 3072 .setup_irqs = adv7611_setup_irqs, 3073 .read_hdmi_pixelclock = adv7611_read_hdmi_pixelclock, 3074 .read_cable_det = adv7611_read_cable_det, 3075 .recommended_settings = { 3076 [1] = adv7611_recommended_settings_hdmi, 3077 }, 3078 .num_recommended_settings = { 3079 [1] = ARRAY_SIZE(adv7611_recommended_settings_hdmi), 3080 }, 3081 .page_mask = BIT(ADV76XX_PAGE_IO) | BIT(ADV76XX_PAGE_CEC) | 3082 BIT(ADV76XX_PAGE_INFOFRAME) | BIT(ADV76XX_PAGE_AFE) | 3083 BIT(ADV76XX_PAGE_REP) | BIT(ADV76XX_PAGE_EDID) | 3084 BIT(ADV76XX_PAGE_HDMI) | BIT(ADV76XX_PAGE_CP), 3085 .linewidth_mask = 0x1fff, 3086 .field0_height_mask = 0x1fff, 3087 .field1_height_mask = 0x1fff, 3088 .hfrontporch_mask = 0x1fff, 3089 .hsync_mask = 0x1fff, 3090 .hbackporch_mask = 0x1fff, 3091 .field0_vfrontporch_mask = 0x3fff, 3092 .field0_vsync_mask = 0x3fff, 3093 .field0_vbackporch_mask = 0x3fff, 3094 .field1_vfrontporch_mask = 0x3fff, 3095 .field1_vsync_mask = 0x3fff, 3096 .field1_vbackporch_mask = 0x3fff, 3097 }, 3098 [ADV7612] = { 3099 .type = ADV7612, 3100 .has_afe = false, 3101 .max_port = ADV76XX_PAD_HDMI_PORT_A, /* B not supported */ 3102 .num_dv_ports = 1, /* normally 2 */ 3103 .edid_enable_reg = 0x74, 3104 .edid_status_reg = 0x76, 3105 .lcf_reg = 0xa3, 3106 .tdms_lock_mask = 0x43, 3107 .cable_det_mask = 0x01, 3108 .fmt_change_digital_mask = 0x03, 3109 .cp_csc = 0xf4, 3110 .cec_irq_status = 0x93, 3111 .cec_rx_enable = 0x2c, 3112 .cec_rx_enable_mask = 0x02, 3113 .formats = adv7612_formats, 3114 .nformats = ARRAY_SIZE(adv7612_formats), 3115 .set_termination = adv7611_set_termination, 3116 .setup_irqs = adv7612_setup_irqs, 3117 .read_hdmi_pixelclock = adv7611_read_hdmi_pixelclock, 3118 .read_cable_det = adv7612_read_cable_det, 3119 .recommended_settings = { 3120 [1] = adv7612_recommended_settings_hdmi, 3121 }, 3122 .num_recommended_settings = { 3123 [1] = ARRAY_SIZE(adv7612_recommended_settings_hdmi), 3124 }, 3125 .page_mask = BIT(ADV76XX_PAGE_IO) | BIT(ADV76XX_PAGE_CEC) | 3126 BIT(ADV76XX_PAGE_INFOFRAME) | BIT(ADV76XX_PAGE_AFE) | 3127 BIT(ADV76XX_PAGE_REP) | BIT(ADV76XX_PAGE_EDID) | 3128 BIT(ADV76XX_PAGE_HDMI) | BIT(ADV76XX_PAGE_CP), 3129 .linewidth_mask = 0x1fff, 3130 .field0_height_mask = 0x1fff, 3131 .field1_height_mask = 0x1fff, 3132 .hfrontporch_mask = 0x1fff, 3133 .hsync_mask = 0x1fff, 3134 .hbackporch_mask = 0x1fff, 3135 .field0_vfrontporch_mask = 0x3fff, 3136 .field0_vsync_mask = 0x3fff, 3137 .field0_vbackporch_mask = 0x3fff, 3138 .field1_vfrontporch_mask = 0x3fff, 3139 .field1_vsync_mask = 0x3fff, 3140 .field1_vbackporch_mask = 0x3fff, 3141 }, 3142 }; 3143 3144 static const struct i2c_device_id adv76xx_i2c_id[] = { 3145 { "adv7604", (kernel_ulong_t)&adv76xx_chip_info[ADV7604] }, 3146 { "adv7611", (kernel_ulong_t)&adv76xx_chip_info[ADV7611] }, 3147 { "adv7612", (kernel_ulong_t)&adv76xx_chip_info[ADV7612] }, 3148 { } 3149 }; 3150 MODULE_DEVICE_TABLE(i2c, adv76xx_i2c_id); 3151 3152 static const struct of_device_id adv76xx_of_id[] __maybe_unused = { 3153 { .compatible = "adi,adv7611", .data = &adv76xx_chip_info[ADV7611] }, 3154 { .compatible = "adi,adv7612", .data = &adv76xx_chip_info[ADV7612] }, 3155 { } 3156 }; 3157 MODULE_DEVICE_TABLE(of, adv76xx_of_id); 3158 3159 static int adv76xx_parse_dt(struct adv76xx_state *state) 3160 { 3161 struct v4l2_fwnode_endpoint bus_cfg = { .bus_type = 0 }; 3162 struct device_node *endpoint; 3163 struct device_node *np; 3164 unsigned int flags; 3165 int ret; 3166 u32 v; 3167 3168 np = state->i2c_clients[ADV76XX_PAGE_IO]->dev.of_node; 3169 3170 /* Parse the endpoint. */ 3171 endpoint = of_graph_get_next_endpoint(np, NULL); 3172 if (!endpoint) 3173 return -EINVAL; 3174 3175 ret = v4l2_fwnode_endpoint_parse(of_fwnode_handle(endpoint), &bus_cfg); 3176 of_node_put(endpoint); 3177 if (ret) 3178 return ret; 3179 3180 if (!of_property_read_u32(np, "default-input", &v)) 3181 state->pdata.default_input = v; 3182 else 3183 state->pdata.default_input = -1; 3184 3185 flags = bus_cfg.bus.parallel.flags; 3186 3187 if (flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH) 3188 state->pdata.inv_hs_pol = 1; 3189 3190 if (flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH) 3191 state->pdata.inv_vs_pol = 1; 3192 3193 if (flags & V4L2_MBUS_PCLK_SAMPLE_RISING) 3194 state->pdata.inv_llc_pol = 1; 3195 3196 if (bus_cfg.bus_type == V4L2_MBUS_BT656) 3197 state->pdata.insert_av_codes = 1; 3198 3199 /* Disable the interrupt for now as no DT-based board uses it. */ 3200 state->pdata.int1_config = ADV76XX_INT1_CONFIG_ACTIVE_HIGH; 3201 3202 /* Hardcode the remaining platform data fields. */ 3203 state->pdata.disable_pwrdnb = 0; 3204 state->pdata.disable_cable_det_rst = 0; 3205 state->pdata.blank_data = 1; 3206 state->pdata.op_format_mode_sel = ADV7604_OP_FORMAT_MODE0; 3207 state->pdata.bus_order = ADV7604_BUS_ORDER_RGB; 3208 state->pdata.dr_str_data = ADV76XX_DR_STR_MEDIUM_HIGH; 3209 state->pdata.dr_str_clk = ADV76XX_DR_STR_MEDIUM_HIGH; 3210 state->pdata.dr_str_sync = ADV76XX_DR_STR_MEDIUM_HIGH; 3211 3212 return 0; 3213 } 3214 3215 static const struct regmap_config adv76xx_regmap_cnf[] = { 3216 { 3217 .name = "io", 3218 .reg_bits = 8, 3219 .val_bits = 8, 3220 3221 .max_register = 0xff, 3222 .cache_type = REGCACHE_NONE, 3223 }, 3224 { 3225 .name = "avlink", 3226 .reg_bits = 8, 3227 .val_bits = 8, 3228 3229 .max_register = 0xff, 3230 .cache_type = REGCACHE_NONE, 3231 }, 3232 { 3233 .name = "cec", 3234 .reg_bits = 8, 3235 .val_bits = 8, 3236 3237 .max_register = 0xff, 3238 .cache_type = REGCACHE_NONE, 3239 }, 3240 { 3241 .name = "infoframe", 3242 .reg_bits = 8, 3243 .val_bits = 8, 3244 3245 .max_register = 0xff, 3246 .cache_type = REGCACHE_NONE, 3247 }, 3248 { 3249 .name = "esdp", 3250 .reg_bits = 8, 3251 .val_bits = 8, 3252 3253 .max_register = 0xff, 3254 .cache_type = REGCACHE_NONE, 3255 }, 3256 { 3257 .name = "epp", 3258 .reg_bits = 8, 3259 .val_bits = 8, 3260 3261 .max_register = 0xff, 3262 .cache_type = REGCACHE_NONE, 3263 }, 3264 { 3265 .name = "afe", 3266 .reg_bits = 8, 3267 .val_bits = 8, 3268 3269 .max_register = 0xff, 3270 .cache_type = REGCACHE_NONE, 3271 }, 3272 { 3273 .name = "rep", 3274 .reg_bits = 8, 3275 .val_bits = 8, 3276 3277 .max_register = 0xff, 3278 .cache_type = REGCACHE_NONE, 3279 }, 3280 { 3281 .name = "edid", 3282 .reg_bits = 8, 3283 .val_bits = 8, 3284 3285 .max_register = 0xff, 3286 .cache_type = REGCACHE_NONE, 3287 }, 3288 3289 { 3290 .name = "hdmi", 3291 .reg_bits = 8, 3292 .val_bits = 8, 3293 3294 .max_register = 0xff, 3295 .cache_type = REGCACHE_NONE, 3296 }, 3297 { 3298 .name = "test", 3299 .reg_bits = 8, 3300 .val_bits = 8, 3301 3302 .max_register = 0xff, 3303 .cache_type = REGCACHE_NONE, 3304 }, 3305 { 3306 .name = "cp", 3307 .reg_bits = 8, 3308 .val_bits = 8, 3309 3310 .max_register = 0xff, 3311 .cache_type = REGCACHE_NONE, 3312 }, 3313 { 3314 .name = "vdp", 3315 .reg_bits = 8, 3316 .val_bits = 8, 3317 3318 .max_register = 0xff, 3319 .cache_type = REGCACHE_NONE, 3320 }, 3321 }; 3322 3323 static int configure_regmap(struct adv76xx_state *state, int region) 3324 { 3325 int err; 3326 3327 if (!state->i2c_clients[region]) 3328 return -ENODEV; 3329 3330 state->regmap[region] = 3331 devm_regmap_init_i2c(state->i2c_clients[region], 3332 &adv76xx_regmap_cnf[region]); 3333 3334 if (IS_ERR(state->regmap[region])) { 3335 err = PTR_ERR(state->regmap[region]); 3336 v4l_err(state->i2c_clients[region], 3337 "Error initializing regmap %d with error %d\n", 3338 region, err); 3339 return -EINVAL; 3340 } 3341 3342 return 0; 3343 } 3344 3345 static int configure_regmaps(struct adv76xx_state *state) 3346 { 3347 int i, err; 3348 3349 for (i = ADV7604_PAGE_AVLINK ; i < ADV76XX_PAGE_MAX; i++) { 3350 err = configure_regmap(state, i); 3351 if (err && (err != -ENODEV)) 3352 return err; 3353 } 3354 return 0; 3355 } 3356 3357 static void adv76xx_reset(struct adv76xx_state *state) 3358 { 3359 if (state->reset_gpio) { 3360 /* ADV76XX can be reset by a low reset pulse of minimum 5 ms. */ 3361 gpiod_set_value_cansleep(state->reset_gpio, 0); 3362 usleep_range(5000, 10000); 3363 gpiod_set_value_cansleep(state->reset_gpio, 1); 3364 /* It is recommended to wait 5 ms after the low pulse before */ 3365 /* an I2C write is performed to the ADV76XX. */ 3366 usleep_range(5000, 10000); 3367 } 3368 } 3369 3370 static int adv76xx_probe(struct i2c_client *client, 3371 const struct i2c_device_id *id) 3372 { 3373 static const struct v4l2_dv_timings cea640x480 = 3374 V4L2_DV_BT_CEA_640X480P59_94; 3375 struct adv76xx_state *state; 3376 struct v4l2_ctrl_handler *hdl; 3377 struct v4l2_ctrl *ctrl; 3378 struct v4l2_subdev *sd; 3379 unsigned int i; 3380 unsigned int val, val2; 3381 int err; 3382 3383 /* Check if the adapter supports the needed features */ 3384 if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA)) 3385 return -EIO; 3386 v4l_dbg(1, debug, client, "detecting adv76xx client on address 0x%x\n", 3387 client->addr << 1); 3388 3389 state = devm_kzalloc(&client->dev, sizeof(*state), GFP_KERNEL); 3390 if (!state) 3391 return -ENOMEM; 3392 3393 state->i2c_clients[ADV76XX_PAGE_IO] = client; 3394 3395 /* initialize variables */ 3396 state->restart_stdi_once = true; 3397 state->selected_input = ~0; 3398 3399 if (IS_ENABLED(CONFIG_OF) && client->dev.of_node) { 3400 const struct of_device_id *oid; 3401 3402 oid = of_match_node(adv76xx_of_id, client->dev.of_node); 3403 state->info = oid->data; 3404 3405 err = adv76xx_parse_dt(state); 3406 if (err < 0) { 3407 v4l_err(client, "DT parsing error\n"); 3408 return err; 3409 } 3410 } else if (client->dev.platform_data) { 3411 struct adv76xx_platform_data *pdata = client->dev.platform_data; 3412 3413 state->info = (const struct adv76xx_chip_info *)id->driver_data; 3414 state->pdata = *pdata; 3415 } else { 3416 v4l_err(client, "No platform data!\n"); 3417 return -ENODEV; 3418 } 3419 3420 /* Request GPIOs. */ 3421 for (i = 0; i < state->info->num_dv_ports; ++i) { 3422 state->hpd_gpio[i] = 3423 devm_gpiod_get_index_optional(&client->dev, "hpd", i, 3424 GPIOD_OUT_LOW); 3425 if (IS_ERR(state->hpd_gpio[i])) 3426 return PTR_ERR(state->hpd_gpio[i]); 3427 3428 if (state->hpd_gpio[i]) 3429 v4l_info(client, "Handling HPD %u GPIO\n", i); 3430 } 3431 state->reset_gpio = devm_gpiod_get_optional(&client->dev, "reset", 3432 GPIOD_OUT_HIGH); 3433 if (IS_ERR(state->reset_gpio)) 3434 return PTR_ERR(state->reset_gpio); 3435 3436 adv76xx_reset(state); 3437 3438 state->timings = cea640x480; 3439 state->format = adv76xx_format_info(state, MEDIA_BUS_FMT_YUYV8_2X8); 3440 3441 sd = &state->sd; 3442 v4l2_i2c_subdev_init(sd, client, &adv76xx_ops); 3443 snprintf(sd->name, sizeof(sd->name), "%s %d-%04x", 3444 id->name, i2c_adapter_id(client->adapter), 3445 client->addr); 3446 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS; 3447 sd->internal_ops = &adv76xx_int_ops; 3448 3449 /* Configure IO Regmap region */ 3450 err = configure_regmap(state, ADV76XX_PAGE_IO); 3451 3452 if (err) { 3453 v4l2_err(sd, "Error configuring IO regmap region\n"); 3454 return -ENODEV; 3455 } 3456 3457 /* 3458 * Verify that the chip is present. On ADV7604 the RD_INFO register only 3459 * identifies the revision, while on ADV7611 it identifies the model as 3460 * well. Use the HDMI slave address on ADV7604 and RD_INFO on ADV7611. 3461 */ 3462 switch (state->info->type) { 3463 case ADV7604: 3464 err = regmap_read(state->regmap[ADV76XX_PAGE_IO], 0xfb, &val); 3465 if (err) { 3466 v4l2_err(sd, "Error %d reading IO Regmap\n", err); 3467 return -ENODEV; 3468 } 3469 if (val != 0x68) { 3470 v4l2_err(sd, "not an adv7604 on address 0x%x\n", 3471 client->addr << 1); 3472 return -ENODEV; 3473 } 3474 break; 3475 case ADV7611: 3476 case ADV7612: 3477 err = regmap_read(state->regmap[ADV76XX_PAGE_IO], 3478 0xea, 3479 &val); 3480 if (err) { 3481 v4l2_err(sd, "Error %d reading IO Regmap\n", err); 3482 return -ENODEV; 3483 } 3484 val2 = val << 8; 3485 err = regmap_read(state->regmap[ADV76XX_PAGE_IO], 3486 0xeb, 3487 &val); 3488 if (err) { 3489 v4l2_err(sd, "Error %d reading IO Regmap\n", err); 3490 return -ENODEV; 3491 } 3492 val |= val2; 3493 if ((state->info->type == ADV7611 && val != 0x2051) || 3494 (state->info->type == ADV7612 && val != 0x2041)) { 3495 v4l2_err(sd, "not an adv761x on address 0x%x\n", 3496 client->addr << 1); 3497 return -ENODEV; 3498 } 3499 break; 3500 } 3501 3502 /* control handlers */ 3503 hdl = &state->hdl; 3504 v4l2_ctrl_handler_init(hdl, adv76xx_has_afe(state) ? 9 : 8); 3505 3506 v4l2_ctrl_new_std(hdl, &adv76xx_ctrl_ops, 3507 V4L2_CID_BRIGHTNESS, -128, 127, 1, 0); 3508 v4l2_ctrl_new_std(hdl, &adv76xx_ctrl_ops, 3509 V4L2_CID_CONTRAST, 0, 255, 1, 128); 3510 v4l2_ctrl_new_std(hdl, &adv76xx_ctrl_ops, 3511 V4L2_CID_SATURATION, 0, 255, 1, 128); 3512 v4l2_ctrl_new_std(hdl, &adv76xx_ctrl_ops, 3513 V4L2_CID_HUE, 0, 128, 1, 0); 3514 ctrl = v4l2_ctrl_new_std_menu(hdl, &adv76xx_ctrl_ops, 3515 V4L2_CID_DV_RX_IT_CONTENT_TYPE, V4L2_DV_IT_CONTENT_TYPE_NO_ITC, 3516 0, V4L2_DV_IT_CONTENT_TYPE_NO_ITC); 3517 if (ctrl) 3518 ctrl->flags |= V4L2_CTRL_FLAG_VOLATILE; 3519 3520 state->detect_tx_5v_ctrl = v4l2_ctrl_new_std(hdl, NULL, 3521 V4L2_CID_DV_RX_POWER_PRESENT, 0, 3522 (1 << state->info->num_dv_ports) - 1, 0, 0); 3523 state->rgb_quantization_range_ctrl = 3524 v4l2_ctrl_new_std_menu(hdl, &adv76xx_ctrl_ops, 3525 V4L2_CID_DV_RX_RGB_RANGE, V4L2_DV_RGB_RANGE_FULL, 3526 0, V4L2_DV_RGB_RANGE_AUTO); 3527 3528 /* custom controls */ 3529 if (adv76xx_has_afe(state)) 3530 state->analog_sampling_phase_ctrl = 3531 v4l2_ctrl_new_custom(hdl, &adv7604_ctrl_analog_sampling_phase, NULL); 3532 state->free_run_color_manual_ctrl = 3533 v4l2_ctrl_new_custom(hdl, &adv76xx_ctrl_free_run_color_manual, NULL); 3534 state->free_run_color_ctrl = 3535 v4l2_ctrl_new_custom(hdl, &adv76xx_ctrl_free_run_color, NULL); 3536 3537 sd->ctrl_handler = hdl; 3538 if (hdl->error) { 3539 err = hdl->error; 3540 goto err_hdl; 3541 } 3542 if (adv76xx_s_detect_tx_5v_ctrl(sd)) { 3543 err = -ENODEV; 3544 goto err_hdl; 3545 } 3546 3547 for (i = 1; i < ADV76XX_PAGE_MAX; ++i) { 3548 struct i2c_client *dummy_client; 3549 3550 if (!(BIT(i) & state->info->page_mask)) 3551 continue; 3552 3553 dummy_client = adv76xx_dummy_client(sd, i); 3554 if (IS_ERR(dummy_client)) { 3555 err = PTR_ERR(dummy_client); 3556 v4l2_err(sd, "failed to create i2c client %u\n", i); 3557 goto err_i2c; 3558 } 3559 3560 state->i2c_clients[i] = dummy_client; 3561 } 3562 3563 INIT_DELAYED_WORK(&state->delayed_work_enable_hotplug, 3564 adv76xx_delayed_work_enable_hotplug); 3565 3566 state->source_pad = state->info->num_dv_ports 3567 + (state->info->has_afe ? 2 : 0); 3568 for (i = 0; i < state->source_pad; ++i) 3569 state->pads[i].flags = MEDIA_PAD_FL_SINK; 3570 state->pads[state->source_pad].flags = MEDIA_PAD_FL_SOURCE; 3571 sd->entity.function = MEDIA_ENT_F_DV_DECODER; 3572 3573 err = media_entity_pads_init(&sd->entity, state->source_pad + 1, 3574 state->pads); 3575 if (err) 3576 goto err_work_queues; 3577 3578 /* Configure regmaps */ 3579 err = configure_regmaps(state); 3580 if (err) 3581 goto err_entity; 3582 3583 err = adv76xx_core_init(sd); 3584 if (err) 3585 goto err_entity; 3586 3587 if (client->irq) { 3588 err = devm_request_threaded_irq(&client->dev, 3589 client->irq, 3590 NULL, adv76xx_irq_handler, 3591 IRQF_TRIGGER_HIGH | IRQF_ONESHOT, 3592 client->name, state); 3593 if (err) 3594 goto err_entity; 3595 } 3596 3597 #if IS_ENABLED(CONFIG_VIDEO_ADV7604_CEC) 3598 state->cec_adap = cec_allocate_adapter(&adv76xx_cec_adap_ops, 3599 state, dev_name(&client->dev), 3600 CEC_CAP_DEFAULTS, ADV76XX_MAX_ADDRS); 3601 err = PTR_ERR_OR_ZERO(state->cec_adap); 3602 if (err) 3603 goto err_entity; 3604 #endif 3605 3606 v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name, 3607 client->addr << 1, client->adapter->name); 3608 3609 err = v4l2_async_register_subdev(sd); 3610 if (err) 3611 goto err_entity; 3612 3613 return 0; 3614 3615 err_entity: 3616 media_entity_cleanup(&sd->entity); 3617 err_work_queues: 3618 cancel_delayed_work(&state->delayed_work_enable_hotplug); 3619 err_i2c: 3620 adv76xx_unregister_clients(state); 3621 err_hdl: 3622 v4l2_ctrl_handler_free(hdl); 3623 return err; 3624 } 3625 3626 /* ----------------------------------------------------------------------- */ 3627 3628 static int adv76xx_remove(struct i2c_client *client) 3629 { 3630 struct v4l2_subdev *sd = i2c_get_clientdata(client); 3631 struct adv76xx_state *state = to_state(sd); 3632 3633 /* disable interrupts */ 3634 io_write(sd, 0x40, 0); 3635 io_write(sd, 0x41, 0); 3636 io_write(sd, 0x46, 0); 3637 io_write(sd, 0x6e, 0); 3638 io_write(sd, 0x73, 0); 3639 3640 cancel_delayed_work(&state->delayed_work_enable_hotplug); 3641 v4l2_async_unregister_subdev(sd); 3642 media_entity_cleanup(&sd->entity); 3643 adv76xx_unregister_clients(to_state(sd)); 3644 v4l2_ctrl_handler_free(sd->ctrl_handler); 3645 return 0; 3646 } 3647 3648 /* ----------------------------------------------------------------------- */ 3649 3650 static struct i2c_driver adv76xx_driver = { 3651 .driver = { 3652 .name = "adv7604", 3653 .of_match_table = of_match_ptr(adv76xx_of_id), 3654 }, 3655 .probe = adv76xx_probe, 3656 .remove = adv76xx_remove, 3657 .id_table = adv76xx_i2c_id, 3658 }; 3659 3660 module_i2c_driver(adv76xx_driver); 3661