1 /* 2 * adv7604 - Analog Devices ADV7604 video decoder driver 3 * 4 * Copyright 2012 Cisco Systems, Inc. and/or its affiliates. All rights reserved. 5 * 6 * This program is free software; you may redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; version 2 of the License. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 11 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 12 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 13 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 14 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 15 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 16 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 17 * SOFTWARE. 18 * 19 */ 20 21 /* 22 * References (c = chapter, p = page): 23 * REF_01 - Analog devices, ADV7604, Register Settings Recommendations, 24 * Revision 2.5, June 2010 25 * REF_02 - Analog devices, Register map documentation, Documentation of 26 * the register maps, Software manual, Rev. F, June 2010 27 * REF_03 - Analog devices, ADV7604, Hardware Manual, Rev. F, August 2010 28 */ 29 30 31 #include <linux/kernel.h> 32 #include <linux/module.h> 33 #include <linux/slab.h> 34 #include <linux/i2c.h> 35 #include <linux/delay.h> 36 #include <linux/videodev2.h> 37 #include <linux/workqueue.h> 38 #include <linux/v4l2-dv-timings.h> 39 #include <media/v4l2-device.h> 40 #include <media/v4l2-ctrls.h> 41 #include <media/v4l2-dv-timings.h> 42 #include <media/adv7604.h> 43 44 static int debug; 45 module_param(debug, int, 0644); 46 MODULE_PARM_DESC(debug, "debug level (0-2)"); 47 48 MODULE_DESCRIPTION("Analog Devices ADV7604 video decoder driver"); 49 MODULE_AUTHOR("Hans Verkuil <hans.verkuil@cisco.com>"); 50 MODULE_AUTHOR("Mats Randgaard <mats.randgaard@cisco.com>"); 51 MODULE_LICENSE("GPL"); 52 53 /* ADV7604 system clock frequency */ 54 #define ADV7604_fsc (28636360) 55 56 /* 57 ********************************************************************** 58 * 59 * Arrays with configuration parameters for the ADV7604 60 * 61 ********************************************************************** 62 */ 63 struct adv7604_state { 64 struct adv7604_platform_data pdata; 65 struct v4l2_subdev sd; 66 struct media_pad pad; 67 struct v4l2_ctrl_handler hdl; 68 enum adv7604_input_port selected_input; 69 struct v4l2_dv_timings timings; 70 struct { 71 u8 edid[256]; 72 u32 present; 73 unsigned blocks; 74 } edid; 75 struct v4l2_fract aspect_ratio; 76 u32 rgb_quantization_range; 77 struct workqueue_struct *work_queues; 78 struct delayed_work delayed_work_enable_hotplug; 79 bool connector_hdmi; 80 bool restart_stdi_once; 81 u32 prev_input_status; 82 83 /* i2c clients */ 84 struct i2c_client *i2c_avlink; 85 struct i2c_client *i2c_cec; 86 struct i2c_client *i2c_infoframe; 87 struct i2c_client *i2c_esdp; 88 struct i2c_client *i2c_dpp; 89 struct i2c_client *i2c_afe; 90 struct i2c_client *i2c_repeater; 91 struct i2c_client *i2c_edid; 92 struct i2c_client *i2c_hdmi; 93 struct i2c_client *i2c_test; 94 struct i2c_client *i2c_cp; 95 struct i2c_client *i2c_vdp; 96 97 /* controls */ 98 struct v4l2_ctrl *detect_tx_5v_ctrl; 99 struct v4l2_ctrl *analog_sampling_phase_ctrl; 100 struct v4l2_ctrl *free_run_color_manual_ctrl; 101 struct v4l2_ctrl *free_run_color_ctrl; 102 struct v4l2_ctrl *rgb_quantization_range_ctrl; 103 }; 104 105 /* Supported CEA and DMT timings */ 106 static const struct v4l2_dv_timings adv7604_timings[] = { 107 V4L2_DV_BT_CEA_720X480P59_94, 108 V4L2_DV_BT_CEA_720X576P50, 109 V4L2_DV_BT_CEA_1280X720P24, 110 V4L2_DV_BT_CEA_1280X720P25, 111 V4L2_DV_BT_CEA_1280X720P50, 112 V4L2_DV_BT_CEA_1280X720P60, 113 V4L2_DV_BT_CEA_1920X1080P24, 114 V4L2_DV_BT_CEA_1920X1080P25, 115 V4L2_DV_BT_CEA_1920X1080P30, 116 V4L2_DV_BT_CEA_1920X1080P50, 117 V4L2_DV_BT_CEA_1920X1080P60, 118 119 /* sorted by DMT ID */ 120 V4L2_DV_BT_DMT_640X350P85, 121 V4L2_DV_BT_DMT_640X400P85, 122 V4L2_DV_BT_DMT_720X400P85, 123 V4L2_DV_BT_DMT_640X480P60, 124 V4L2_DV_BT_DMT_640X480P72, 125 V4L2_DV_BT_DMT_640X480P75, 126 V4L2_DV_BT_DMT_640X480P85, 127 V4L2_DV_BT_DMT_800X600P56, 128 V4L2_DV_BT_DMT_800X600P60, 129 V4L2_DV_BT_DMT_800X600P72, 130 V4L2_DV_BT_DMT_800X600P75, 131 V4L2_DV_BT_DMT_800X600P85, 132 V4L2_DV_BT_DMT_848X480P60, 133 V4L2_DV_BT_DMT_1024X768P60, 134 V4L2_DV_BT_DMT_1024X768P70, 135 V4L2_DV_BT_DMT_1024X768P75, 136 V4L2_DV_BT_DMT_1024X768P85, 137 V4L2_DV_BT_DMT_1152X864P75, 138 V4L2_DV_BT_DMT_1280X768P60_RB, 139 V4L2_DV_BT_DMT_1280X768P60, 140 V4L2_DV_BT_DMT_1280X768P75, 141 V4L2_DV_BT_DMT_1280X768P85, 142 V4L2_DV_BT_DMT_1280X800P60_RB, 143 V4L2_DV_BT_DMT_1280X800P60, 144 V4L2_DV_BT_DMT_1280X800P75, 145 V4L2_DV_BT_DMT_1280X800P85, 146 V4L2_DV_BT_DMT_1280X960P60, 147 V4L2_DV_BT_DMT_1280X960P85, 148 V4L2_DV_BT_DMT_1280X1024P60, 149 V4L2_DV_BT_DMT_1280X1024P75, 150 V4L2_DV_BT_DMT_1280X1024P85, 151 V4L2_DV_BT_DMT_1360X768P60, 152 V4L2_DV_BT_DMT_1400X1050P60_RB, 153 V4L2_DV_BT_DMT_1400X1050P60, 154 V4L2_DV_BT_DMT_1400X1050P75, 155 V4L2_DV_BT_DMT_1400X1050P85, 156 V4L2_DV_BT_DMT_1440X900P60_RB, 157 V4L2_DV_BT_DMT_1440X900P60, 158 V4L2_DV_BT_DMT_1600X1200P60, 159 V4L2_DV_BT_DMT_1680X1050P60_RB, 160 V4L2_DV_BT_DMT_1680X1050P60, 161 V4L2_DV_BT_DMT_1792X1344P60, 162 V4L2_DV_BT_DMT_1856X1392P60, 163 V4L2_DV_BT_DMT_1920X1200P60_RB, 164 V4L2_DV_BT_DMT_1366X768P60_RB, 165 V4L2_DV_BT_DMT_1366X768P60, 166 V4L2_DV_BT_DMT_1920X1080P60, 167 { }, 168 }; 169 170 struct adv7604_video_standards { 171 struct v4l2_dv_timings timings; 172 u8 vid_std; 173 u8 v_freq; 174 }; 175 176 /* sorted by number of lines */ 177 static const struct adv7604_video_standards adv7604_prim_mode_comp[] = { 178 /* { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 }, TODO flickering */ 179 { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 }, 180 { V4L2_DV_BT_CEA_1280X720P50, 0x19, 0x01 }, 181 { V4L2_DV_BT_CEA_1280X720P60, 0x19, 0x00 }, 182 { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 }, 183 { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 }, 184 { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 }, 185 { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 }, 186 { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 }, 187 /* TODO add 1920x1080P60_RB (CVT timing) */ 188 { }, 189 }; 190 191 /* sorted by number of lines */ 192 static const struct adv7604_video_standards adv7604_prim_mode_gr[] = { 193 { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 }, 194 { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 }, 195 { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 }, 196 { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 }, 197 { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 }, 198 { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 }, 199 { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 }, 200 { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 }, 201 { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 }, 202 { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 }, 203 { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 }, 204 { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 }, 205 { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 }, 206 { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 }, 207 { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 }, 208 { V4L2_DV_BT_DMT_1360X768P60, 0x12, 0x00 }, 209 { V4L2_DV_BT_DMT_1366X768P60, 0x13, 0x00 }, 210 { V4L2_DV_BT_DMT_1400X1050P60, 0x14, 0x00 }, 211 { V4L2_DV_BT_DMT_1400X1050P75, 0x15, 0x00 }, 212 { V4L2_DV_BT_DMT_1600X1200P60, 0x16, 0x00 }, /* TODO not tested */ 213 /* TODO add 1600X1200P60_RB (not a DMT timing) */ 214 { V4L2_DV_BT_DMT_1680X1050P60, 0x18, 0x00 }, 215 { V4L2_DV_BT_DMT_1920X1200P60_RB, 0x19, 0x00 }, /* TODO not tested */ 216 { }, 217 }; 218 219 /* sorted by number of lines */ 220 static const struct adv7604_video_standards adv7604_prim_mode_hdmi_comp[] = { 221 { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 }, 222 { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 }, 223 { V4L2_DV_BT_CEA_1280X720P50, 0x13, 0x01 }, 224 { V4L2_DV_BT_CEA_1280X720P60, 0x13, 0x00 }, 225 { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 }, 226 { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 }, 227 { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 }, 228 { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 }, 229 { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 }, 230 { }, 231 }; 232 233 /* sorted by number of lines */ 234 static const struct adv7604_video_standards adv7604_prim_mode_hdmi_gr[] = { 235 { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 }, 236 { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 }, 237 { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 }, 238 { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 }, 239 { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 }, 240 { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 }, 241 { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 }, 242 { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 }, 243 { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 }, 244 { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 }, 245 { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 }, 246 { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 }, 247 { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 }, 248 { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 }, 249 { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 }, 250 { }, 251 }; 252 253 /* ----------------------------------------------------------------------- */ 254 255 static inline struct adv7604_state *to_state(struct v4l2_subdev *sd) 256 { 257 return container_of(sd, struct adv7604_state, sd); 258 } 259 260 static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl) 261 { 262 return &container_of(ctrl->handler, struct adv7604_state, hdl)->sd; 263 } 264 265 static inline unsigned hblanking(const struct v4l2_bt_timings *t) 266 { 267 return V4L2_DV_BT_BLANKING_WIDTH(t); 268 } 269 270 static inline unsigned htotal(const struct v4l2_bt_timings *t) 271 { 272 return V4L2_DV_BT_FRAME_WIDTH(t); 273 } 274 275 static inline unsigned vblanking(const struct v4l2_bt_timings *t) 276 { 277 return V4L2_DV_BT_BLANKING_HEIGHT(t); 278 } 279 280 static inline unsigned vtotal(const struct v4l2_bt_timings *t) 281 { 282 return V4L2_DV_BT_FRAME_HEIGHT(t); 283 } 284 285 /* ----------------------------------------------------------------------- */ 286 287 static s32 adv_smbus_read_byte_data_check(struct i2c_client *client, 288 u8 command, bool check) 289 { 290 union i2c_smbus_data data; 291 292 if (!i2c_smbus_xfer(client->adapter, client->addr, client->flags, 293 I2C_SMBUS_READ, command, 294 I2C_SMBUS_BYTE_DATA, &data)) 295 return data.byte; 296 if (check) 297 v4l_err(client, "error reading %02x, %02x\n", 298 client->addr, command); 299 return -EIO; 300 } 301 302 static s32 adv_smbus_read_byte_data(struct i2c_client *client, u8 command) 303 { 304 return adv_smbus_read_byte_data_check(client, command, true); 305 } 306 307 static s32 adv_smbus_write_byte_data(struct i2c_client *client, 308 u8 command, u8 value) 309 { 310 union i2c_smbus_data data; 311 int err; 312 int i; 313 314 data.byte = value; 315 for (i = 0; i < 3; i++) { 316 err = i2c_smbus_xfer(client->adapter, client->addr, 317 client->flags, 318 I2C_SMBUS_WRITE, command, 319 I2C_SMBUS_BYTE_DATA, &data); 320 if (!err) 321 break; 322 } 323 if (err < 0) 324 v4l_err(client, "error writing %02x, %02x, %02x\n", 325 client->addr, command, value); 326 return err; 327 } 328 329 static s32 adv_smbus_write_i2c_block_data(struct i2c_client *client, 330 u8 command, unsigned length, const u8 *values) 331 { 332 union i2c_smbus_data data; 333 334 if (length > I2C_SMBUS_BLOCK_MAX) 335 length = I2C_SMBUS_BLOCK_MAX; 336 data.block[0] = length; 337 memcpy(data.block + 1, values, length); 338 return i2c_smbus_xfer(client->adapter, client->addr, client->flags, 339 I2C_SMBUS_WRITE, command, 340 I2C_SMBUS_I2C_BLOCK_DATA, &data); 341 } 342 343 /* ----------------------------------------------------------------------- */ 344 345 static inline int io_read(struct v4l2_subdev *sd, u8 reg) 346 { 347 struct i2c_client *client = v4l2_get_subdevdata(sd); 348 349 return adv_smbus_read_byte_data(client, reg); 350 } 351 352 static inline int io_write(struct v4l2_subdev *sd, u8 reg, u8 val) 353 { 354 struct i2c_client *client = v4l2_get_subdevdata(sd); 355 356 return adv_smbus_write_byte_data(client, reg, val); 357 } 358 359 static inline int io_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) 360 { 361 return io_write(sd, reg, (io_read(sd, reg) & mask) | val); 362 } 363 364 static inline int avlink_read(struct v4l2_subdev *sd, u8 reg) 365 { 366 struct adv7604_state *state = to_state(sd); 367 368 return adv_smbus_read_byte_data(state->i2c_avlink, reg); 369 } 370 371 static inline int avlink_write(struct v4l2_subdev *sd, u8 reg, u8 val) 372 { 373 struct adv7604_state *state = to_state(sd); 374 375 return adv_smbus_write_byte_data(state->i2c_avlink, reg, val); 376 } 377 378 static inline int cec_read(struct v4l2_subdev *sd, u8 reg) 379 { 380 struct adv7604_state *state = to_state(sd); 381 382 return adv_smbus_read_byte_data(state->i2c_cec, reg); 383 } 384 385 static inline int cec_write(struct v4l2_subdev *sd, u8 reg, u8 val) 386 { 387 struct adv7604_state *state = to_state(sd); 388 389 return adv_smbus_write_byte_data(state->i2c_cec, reg, val); 390 } 391 392 static inline int cec_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) 393 { 394 return cec_write(sd, reg, (cec_read(sd, reg) & mask) | val); 395 } 396 397 static inline int infoframe_read(struct v4l2_subdev *sd, u8 reg) 398 { 399 struct adv7604_state *state = to_state(sd); 400 401 return adv_smbus_read_byte_data(state->i2c_infoframe, reg); 402 } 403 404 static inline int infoframe_write(struct v4l2_subdev *sd, u8 reg, u8 val) 405 { 406 struct adv7604_state *state = to_state(sd); 407 408 return adv_smbus_write_byte_data(state->i2c_infoframe, reg, val); 409 } 410 411 static inline int esdp_read(struct v4l2_subdev *sd, u8 reg) 412 { 413 struct adv7604_state *state = to_state(sd); 414 415 return adv_smbus_read_byte_data(state->i2c_esdp, reg); 416 } 417 418 static inline int esdp_write(struct v4l2_subdev *sd, u8 reg, u8 val) 419 { 420 struct adv7604_state *state = to_state(sd); 421 422 return adv_smbus_write_byte_data(state->i2c_esdp, reg, val); 423 } 424 425 static inline int dpp_read(struct v4l2_subdev *sd, u8 reg) 426 { 427 struct adv7604_state *state = to_state(sd); 428 429 return adv_smbus_read_byte_data(state->i2c_dpp, reg); 430 } 431 432 static inline int dpp_write(struct v4l2_subdev *sd, u8 reg, u8 val) 433 { 434 struct adv7604_state *state = to_state(sd); 435 436 return adv_smbus_write_byte_data(state->i2c_dpp, reg, val); 437 } 438 439 static inline int afe_read(struct v4l2_subdev *sd, u8 reg) 440 { 441 struct adv7604_state *state = to_state(sd); 442 443 return adv_smbus_read_byte_data(state->i2c_afe, reg); 444 } 445 446 static inline int afe_write(struct v4l2_subdev *sd, u8 reg, u8 val) 447 { 448 struct adv7604_state *state = to_state(sd); 449 450 return adv_smbus_write_byte_data(state->i2c_afe, reg, val); 451 } 452 453 static inline int rep_read(struct v4l2_subdev *sd, u8 reg) 454 { 455 struct adv7604_state *state = to_state(sd); 456 457 return adv_smbus_read_byte_data(state->i2c_repeater, reg); 458 } 459 460 static inline int rep_write(struct v4l2_subdev *sd, u8 reg, u8 val) 461 { 462 struct adv7604_state *state = to_state(sd); 463 464 return adv_smbus_write_byte_data(state->i2c_repeater, reg, val); 465 } 466 467 static inline int rep_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) 468 { 469 return rep_write(sd, reg, (rep_read(sd, reg) & mask) | val); 470 } 471 472 static inline int edid_read(struct v4l2_subdev *sd, u8 reg) 473 { 474 struct adv7604_state *state = to_state(sd); 475 476 return adv_smbus_read_byte_data(state->i2c_edid, reg); 477 } 478 479 static inline int edid_write(struct v4l2_subdev *sd, u8 reg, u8 val) 480 { 481 struct adv7604_state *state = to_state(sd); 482 483 return adv_smbus_write_byte_data(state->i2c_edid, reg, val); 484 } 485 486 static inline int edid_read_block(struct v4l2_subdev *sd, unsigned len, u8 *val) 487 { 488 struct adv7604_state *state = to_state(sd); 489 struct i2c_client *client = state->i2c_edid; 490 u8 msgbuf0[1] = { 0 }; 491 u8 msgbuf1[256]; 492 struct i2c_msg msg[2] = { 493 { 494 .addr = client->addr, 495 .len = 1, 496 .buf = msgbuf0 497 }, 498 { 499 .addr = client->addr, 500 .flags = I2C_M_RD, 501 .len = len, 502 .buf = msgbuf1 503 }, 504 }; 505 506 if (i2c_transfer(client->adapter, msg, 2) < 0) 507 return -EIO; 508 memcpy(val, msgbuf1, len); 509 return 0; 510 } 511 512 static void adv7604_delayed_work_enable_hotplug(struct work_struct *work) 513 { 514 struct delayed_work *dwork = to_delayed_work(work); 515 struct adv7604_state *state = container_of(dwork, struct adv7604_state, 516 delayed_work_enable_hotplug); 517 struct v4l2_subdev *sd = &state->sd; 518 519 v4l2_dbg(2, debug, sd, "%s: enable hotplug\n", __func__); 520 521 v4l2_subdev_notify(sd, ADV7604_HOTPLUG, (void *)&state->edid.present); 522 } 523 524 static inline int edid_write_block(struct v4l2_subdev *sd, 525 unsigned len, const u8 *val) 526 { 527 struct i2c_client *client = v4l2_get_subdevdata(sd); 528 struct adv7604_state *state = to_state(sd); 529 int err = 0; 530 int i; 531 532 v4l2_dbg(2, debug, sd, "%s: write EDID block (%d byte)\n", __func__, len); 533 534 /* Disables I2C access to internal EDID ram from DDC port */ 535 rep_write_and_or(sd, 0x77, 0xf0, 0x0); 536 537 for (i = 0; !err && i < len; i += I2C_SMBUS_BLOCK_MAX) 538 err = adv_smbus_write_i2c_block_data(state->i2c_edid, i, 539 I2C_SMBUS_BLOCK_MAX, val + i); 540 if (err) 541 return err; 542 543 /* adv7604 calculates the checksums and enables I2C access to internal 544 EDID RAM from DDC port. */ 545 rep_write_and_or(sd, 0x77, 0xf0, state->edid.present); 546 547 for (i = 0; i < 1000; i++) { 548 if (rep_read(sd, 0x7d) & state->edid.present) 549 break; 550 mdelay(1); 551 } 552 if (i == 1000) { 553 v4l_err(client, "error enabling edid (0x%x)\n", state->edid.present); 554 return -EIO; 555 } 556 557 return 0; 558 } 559 560 static inline int hdmi_read(struct v4l2_subdev *sd, u8 reg) 561 { 562 struct adv7604_state *state = to_state(sd); 563 564 return adv_smbus_read_byte_data(state->i2c_hdmi, reg); 565 } 566 567 static inline int hdmi_write(struct v4l2_subdev *sd, u8 reg, u8 val) 568 { 569 struct adv7604_state *state = to_state(sd); 570 571 return adv_smbus_write_byte_data(state->i2c_hdmi, reg, val); 572 } 573 574 static inline int hdmi_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) 575 { 576 return hdmi_write(sd, reg, (hdmi_read(sd, reg) & mask) | val); 577 } 578 579 static inline int test_read(struct v4l2_subdev *sd, u8 reg) 580 { 581 struct adv7604_state *state = to_state(sd); 582 583 return adv_smbus_read_byte_data(state->i2c_test, reg); 584 } 585 586 static inline int test_write(struct v4l2_subdev *sd, u8 reg, u8 val) 587 { 588 struct adv7604_state *state = to_state(sd); 589 590 return adv_smbus_write_byte_data(state->i2c_test, reg, val); 591 } 592 593 static inline int cp_read(struct v4l2_subdev *sd, u8 reg) 594 { 595 struct adv7604_state *state = to_state(sd); 596 597 return adv_smbus_read_byte_data(state->i2c_cp, reg); 598 } 599 600 static inline int cp_write(struct v4l2_subdev *sd, u8 reg, u8 val) 601 { 602 struct adv7604_state *state = to_state(sd); 603 604 return adv_smbus_write_byte_data(state->i2c_cp, reg, val); 605 } 606 607 static inline int cp_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) 608 { 609 return cp_write(sd, reg, (cp_read(sd, reg) & mask) | val); 610 } 611 612 static inline int vdp_read(struct v4l2_subdev *sd, u8 reg) 613 { 614 struct adv7604_state *state = to_state(sd); 615 616 return adv_smbus_read_byte_data(state->i2c_vdp, reg); 617 } 618 619 static inline int vdp_write(struct v4l2_subdev *sd, u8 reg, u8 val) 620 { 621 struct adv7604_state *state = to_state(sd); 622 623 return adv_smbus_write_byte_data(state->i2c_vdp, reg, val); 624 } 625 626 /* ----------------------------------------------------------------------- */ 627 628 static inline bool is_analog_input(struct v4l2_subdev *sd) 629 { 630 struct adv7604_state *state = to_state(sd); 631 632 return state->selected_input == ADV7604_INPUT_VGA_RGB || 633 state->selected_input == ADV7604_INPUT_VGA_COMP; 634 } 635 636 static inline bool is_digital_input(struct v4l2_subdev *sd) 637 { 638 struct adv7604_state *state = to_state(sd); 639 640 return state->selected_input == ADV7604_INPUT_HDMI_PORT_A || 641 state->selected_input == ADV7604_INPUT_HDMI_PORT_B || 642 state->selected_input == ADV7604_INPUT_HDMI_PORT_C || 643 state->selected_input == ADV7604_INPUT_HDMI_PORT_D; 644 } 645 646 /* ----------------------------------------------------------------------- */ 647 648 #ifdef CONFIG_VIDEO_ADV_DEBUG 649 static void adv7604_inv_register(struct v4l2_subdev *sd) 650 { 651 v4l2_info(sd, "0x000-0x0ff: IO Map\n"); 652 v4l2_info(sd, "0x100-0x1ff: AVLink Map\n"); 653 v4l2_info(sd, "0x200-0x2ff: CEC Map\n"); 654 v4l2_info(sd, "0x300-0x3ff: InfoFrame Map\n"); 655 v4l2_info(sd, "0x400-0x4ff: ESDP Map\n"); 656 v4l2_info(sd, "0x500-0x5ff: DPP Map\n"); 657 v4l2_info(sd, "0x600-0x6ff: AFE Map\n"); 658 v4l2_info(sd, "0x700-0x7ff: Repeater Map\n"); 659 v4l2_info(sd, "0x800-0x8ff: EDID Map\n"); 660 v4l2_info(sd, "0x900-0x9ff: HDMI Map\n"); 661 v4l2_info(sd, "0xa00-0xaff: Test Map\n"); 662 v4l2_info(sd, "0xb00-0xbff: CP Map\n"); 663 v4l2_info(sd, "0xc00-0xcff: VDP Map\n"); 664 } 665 666 static int adv7604_g_register(struct v4l2_subdev *sd, 667 struct v4l2_dbg_register *reg) 668 { 669 reg->size = 1; 670 switch (reg->reg >> 8) { 671 case 0: 672 reg->val = io_read(sd, reg->reg & 0xff); 673 break; 674 case 1: 675 reg->val = avlink_read(sd, reg->reg & 0xff); 676 break; 677 case 2: 678 reg->val = cec_read(sd, reg->reg & 0xff); 679 break; 680 case 3: 681 reg->val = infoframe_read(sd, reg->reg & 0xff); 682 break; 683 case 4: 684 reg->val = esdp_read(sd, reg->reg & 0xff); 685 break; 686 case 5: 687 reg->val = dpp_read(sd, reg->reg & 0xff); 688 break; 689 case 6: 690 reg->val = afe_read(sd, reg->reg & 0xff); 691 break; 692 case 7: 693 reg->val = rep_read(sd, reg->reg & 0xff); 694 break; 695 case 8: 696 reg->val = edid_read(sd, reg->reg & 0xff); 697 break; 698 case 9: 699 reg->val = hdmi_read(sd, reg->reg & 0xff); 700 break; 701 case 0xa: 702 reg->val = test_read(sd, reg->reg & 0xff); 703 break; 704 case 0xb: 705 reg->val = cp_read(sd, reg->reg & 0xff); 706 break; 707 case 0xc: 708 reg->val = vdp_read(sd, reg->reg & 0xff); 709 break; 710 default: 711 v4l2_info(sd, "Register %03llx not supported\n", reg->reg); 712 adv7604_inv_register(sd); 713 break; 714 } 715 return 0; 716 } 717 718 static int adv7604_s_register(struct v4l2_subdev *sd, 719 const struct v4l2_dbg_register *reg) 720 { 721 u8 val = reg->val & 0xff; 722 723 switch (reg->reg >> 8) { 724 case 0: 725 io_write(sd, reg->reg & 0xff, val); 726 break; 727 case 1: 728 avlink_write(sd, reg->reg & 0xff, val); 729 break; 730 case 2: 731 cec_write(sd, reg->reg & 0xff, val); 732 break; 733 case 3: 734 infoframe_write(sd, reg->reg & 0xff, val); 735 break; 736 case 4: 737 esdp_write(sd, reg->reg & 0xff, val); 738 break; 739 case 5: 740 dpp_write(sd, reg->reg & 0xff, val); 741 break; 742 case 6: 743 afe_write(sd, reg->reg & 0xff, val); 744 break; 745 case 7: 746 rep_write(sd, reg->reg & 0xff, val); 747 break; 748 case 8: 749 edid_write(sd, reg->reg & 0xff, val); 750 break; 751 case 9: 752 hdmi_write(sd, reg->reg & 0xff, val); 753 break; 754 case 0xa: 755 test_write(sd, reg->reg & 0xff, val); 756 break; 757 case 0xb: 758 cp_write(sd, reg->reg & 0xff, val); 759 break; 760 case 0xc: 761 vdp_write(sd, reg->reg & 0xff, val); 762 break; 763 default: 764 v4l2_info(sd, "Register %03llx not supported\n", reg->reg); 765 adv7604_inv_register(sd); 766 break; 767 } 768 return 0; 769 } 770 #endif 771 772 static int adv7604_s_detect_tx_5v_ctrl(struct v4l2_subdev *sd) 773 { 774 struct adv7604_state *state = to_state(sd); 775 u8 reg_io_6f = io_read(sd, 0x6f); 776 777 return v4l2_ctrl_s_ctrl(state->detect_tx_5v_ctrl, 778 ((reg_io_6f & 0x10) >> 4) | 779 ((reg_io_6f & 0x08) >> 2) | 780 (reg_io_6f & 0x04) | 781 ((reg_io_6f & 0x02) << 2)); 782 } 783 784 static int find_and_set_predefined_video_timings(struct v4l2_subdev *sd, 785 u8 prim_mode, 786 const struct adv7604_video_standards *predef_vid_timings, 787 const struct v4l2_dv_timings *timings) 788 { 789 int i; 790 791 for (i = 0; predef_vid_timings[i].timings.bt.width; i++) { 792 if (!v4l2_match_dv_timings(timings, &predef_vid_timings[i].timings, 793 is_digital_input(sd) ? 250000 : 1000000)) 794 continue; 795 io_write(sd, 0x00, predef_vid_timings[i].vid_std); /* video std */ 796 io_write(sd, 0x01, (predef_vid_timings[i].v_freq << 4) + 797 prim_mode); /* v_freq and prim mode */ 798 return 0; 799 } 800 801 return -1; 802 } 803 804 static int configure_predefined_video_timings(struct v4l2_subdev *sd, 805 struct v4l2_dv_timings *timings) 806 { 807 struct adv7604_state *state = to_state(sd); 808 int err; 809 810 v4l2_dbg(1, debug, sd, "%s", __func__); 811 812 /* reset to default values */ 813 io_write(sd, 0x16, 0x43); 814 io_write(sd, 0x17, 0x5a); 815 /* disable embedded syncs for auto graphics mode */ 816 cp_write_and_or(sd, 0x81, 0xef, 0x00); 817 cp_write(sd, 0x8f, 0x00); 818 cp_write(sd, 0x90, 0x00); 819 cp_write(sd, 0xa2, 0x00); 820 cp_write(sd, 0xa3, 0x00); 821 cp_write(sd, 0xa4, 0x00); 822 cp_write(sd, 0xa5, 0x00); 823 cp_write(sd, 0xa6, 0x00); 824 cp_write(sd, 0xa7, 0x00); 825 cp_write(sd, 0xab, 0x00); 826 cp_write(sd, 0xac, 0x00); 827 828 if (is_analog_input(sd)) { 829 err = find_and_set_predefined_video_timings(sd, 830 0x01, adv7604_prim_mode_comp, timings); 831 if (err) 832 err = find_and_set_predefined_video_timings(sd, 833 0x02, adv7604_prim_mode_gr, timings); 834 } else if (is_digital_input(sd)) { 835 err = find_and_set_predefined_video_timings(sd, 836 0x05, adv7604_prim_mode_hdmi_comp, timings); 837 if (err) 838 err = find_and_set_predefined_video_timings(sd, 839 0x06, adv7604_prim_mode_hdmi_gr, timings); 840 } else { 841 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n", 842 __func__, state->selected_input); 843 err = -1; 844 } 845 846 847 return err; 848 } 849 850 static void configure_custom_video_timings(struct v4l2_subdev *sd, 851 const struct v4l2_bt_timings *bt) 852 { 853 struct adv7604_state *state = to_state(sd); 854 struct i2c_client *client = v4l2_get_subdevdata(sd); 855 u32 width = htotal(bt); 856 u32 height = vtotal(bt); 857 u16 cp_start_sav = bt->hsync + bt->hbackporch - 4; 858 u16 cp_start_eav = width - bt->hfrontporch; 859 u16 cp_start_vbi = height - bt->vfrontporch; 860 u16 cp_end_vbi = bt->vsync + bt->vbackporch; 861 u16 ch1_fr_ll = (((u32)bt->pixelclock / 100) > 0) ? 862 ((width * (ADV7604_fsc / 100)) / ((u32)bt->pixelclock / 100)) : 0; 863 const u8 pll[2] = { 864 0xc0 | ((width >> 8) & 0x1f), 865 width & 0xff 866 }; 867 868 v4l2_dbg(2, debug, sd, "%s\n", __func__); 869 870 if (is_analog_input(sd)) { 871 /* auto graphics */ 872 io_write(sd, 0x00, 0x07); /* video std */ 873 io_write(sd, 0x01, 0x02); /* prim mode */ 874 /* enable embedded syncs for auto graphics mode */ 875 cp_write_and_or(sd, 0x81, 0xef, 0x10); 876 877 /* Should only be set in auto-graphics mode [REF_02, p. 91-92] */ 878 /* setup PLL_DIV_MAN_EN and PLL_DIV_RATIO */ 879 /* IO-map reg. 0x16 and 0x17 should be written in sequence */ 880 if (adv_smbus_write_i2c_block_data(client, 0x16, 2, pll)) 881 v4l2_err(sd, "writing to reg 0x16 and 0x17 failed\n"); 882 883 /* active video - horizontal timing */ 884 cp_write(sd, 0xa2, (cp_start_sav >> 4) & 0xff); 885 cp_write(sd, 0xa3, ((cp_start_sav & 0x0f) << 4) | 886 ((cp_start_eav >> 8) & 0x0f)); 887 cp_write(sd, 0xa4, cp_start_eav & 0xff); 888 889 /* active video - vertical timing */ 890 cp_write(sd, 0xa5, (cp_start_vbi >> 4) & 0xff); 891 cp_write(sd, 0xa6, ((cp_start_vbi & 0xf) << 4) | 892 ((cp_end_vbi >> 8) & 0xf)); 893 cp_write(sd, 0xa7, cp_end_vbi & 0xff); 894 } else if (is_digital_input(sd)) { 895 /* set default prim_mode/vid_std for HDMI 896 according to [REF_03, c. 4.2] */ 897 io_write(sd, 0x00, 0x02); /* video std */ 898 io_write(sd, 0x01, 0x06); /* prim mode */ 899 } else { 900 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n", 901 __func__, state->selected_input); 902 } 903 904 cp_write(sd, 0x8f, (ch1_fr_ll >> 8) & 0x7); 905 cp_write(sd, 0x90, ch1_fr_ll & 0xff); 906 cp_write(sd, 0xab, (height >> 4) & 0xff); 907 cp_write(sd, 0xac, (height & 0x0f) << 4); 908 } 909 910 static void set_rgb_quantization_range(struct v4l2_subdev *sd) 911 { 912 struct adv7604_state *state = to_state(sd); 913 914 switch (state->rgb_quantization_range) { 915 case V4L2_DV_RGB_RANGE_AUTO: 916 /* automatic */ 917 if (is_digital_input(sd) && !(hdmi_read(sd, 0x05) & 0x80)) { 918 /* receiving DVI-D signal */ 919 920 /* ADV7604 selects RGB limited range regardless of 921 input format (CE/IT) in automatic mode */ 922 if (state->timings.bt.standards & V4L2_DV_BT_STD_CEA861) { 923 /* RGB limited range (16-235) */ 924 io_write_and_or(sd, 0x02, 0x0f, 0x00); 925 926 } else { 927 /* RGB full range (0-255) */ 928 io_write_and_or(sd, 0x02, 0x0f, 0x10); 929 } 930 } else { 931 /* receiving HDMI or analog signal, set automode */ 932 io_write_and_or(sd, 0x02, 0x0f, 0xf0); 933 } 934 break; 935 case V4L2_DV_RGB_RANGE_LIMITED: 936 /* RGB limited range (16-235) */ 937 io_write_and_or(sd, 0x02, 0x0f, 0x00); 938 break; 939 case V4L2_DV_RGB_RANGE_FULL: 940 /* RGB full range (0-255) */ 941 io_write_and_or(sd, 0x02, 0x0f, 0x10); 942 break; 943 } 944 } 945 946 947 static int adv7604_s_ctrl(struct v4l2_ctrl *ctrl) 948 { 949 struct v4l2_subdev *sd = to_sd(ctrl); 950 struct adv7604_state *state = to_state(sd); 951 952 switch (ctrl->id) { 953 case V4L2_CID_BRIGHTNESS: 954 cp_write(sd, 0x3c, ctrl->val); 955 return 0; 956 case V4L2_CID_CONTRAST: 957 cp_write(sd, 0x3a, ctrl->val); 958 return 0; 959 case V4L2_CID_SATURATION: 960 cp_write(sd, 0x3b, ctrl->val); 961 return 0; 962 case V4L2_CID_HUE: 963 cp_write(sd, 0x3d, ctrl->val); 964 return 0; 965 case V4L2_CID_DV_RX_RGB_RANGE: 966 state->rgb_quantization_range = ctrl->val; 967 set_rgb_quantization_range(sd); 968 return 0; 969 case V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE: 970 /* Set the analog sampling phase. This is needed to find the 971 best sampling phase for analog video: an application or 972 driver has to try a number of phases and analyze the picture 973 quality before settling on the best performing phase. */ 974 afe_write(sd, 0xc8, ctrl->val); 975 return 0; 976 case V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL: 977 /* Use the default blue color for free running mode, 978 or supply your own. */ 979 cp_write_and_or(sd, 0xbf, ~0x04, (ctrl->val << 2)); 980 return 0; 981 case V4L2_CID_ADV_RX_FREE_RUN_COLOR: 982 cp_write(sd, 0xc0, (ctrl->val & 0xff0000) >> 16); 983 cp_write(sd, 0xc1, (ctrl->val & 0x00ff00) >> 8); 984 cp_write(sd, 0xc2, (u8)(ctrl->val & 0x0000ff)); 985 return 0; 986 } 987 return -EINVAL; 988 } 989 990 /* ----------------------------------------------------------------------- */ 991 992 static inline bool no_power(struct v4l2_subdev *sd) 993 { 994 /* Entire chip or CP powered off */ 995 return io_read(sd, 0x0c) & 0x24; 996 } 997 998 static inline bool no_signal_tmds(struct v4l2_subdev *sd) 999 { 1000 struct adv7604_state *state = to_state(sd); 1001 1002 return !(io_read(sd, 0x6a) & (0x10 >> state->selected_input)); 1003 } 1004 1005 static inline bool no_lock_tmds(struct v4l2_subdev *sd) 1006 { 1007 return (io_read(sd, 0x6a) & 0xe0) != 0xe0; 1008 } 1009 1010 static inline bool is_hdmi(struct v4l2_subdev *sd) 1011 { 1012 return hdmi_read(sd, 0x05) & 0x80; 1013 } 1014 1015 static inline bool no_lock_sspd(struct v4l2_subdev *sd) 1016 { 1017 /* TODO channel 2 */ 1018 return ((cp_read(sd, 0xb5) & 0xd0) != 0xd0); 1019 } 1020 1021 static inline bool no_lock_stdi(struct v4l2_subdev *sd) 1022 { 1023 /* TODO channel 2 */ 1024 return !(cp_read(sd, 0xb1) & 0x80); 1025 } 1026 1027 static inline bool no_signal(struct v4l2_subdev *sd) 1028 { 1029 bool ret; 1030 1031 ret = no_power(sd); 1032 1033 ret |= no_lock_stdi(sd); 1034 ret |= no_lock_sspd(sd); 1035 1036 if (is_digital_input(sd)) { 1037 ret |= no_lock_tmds(sd); 1038 ret |= no_signal_tmds(sd); 1039 } 1040 1041 return ret; 1042 } 1043 1044 static inline bool no_lock_cp(struct v4l2_subdev *sd) 1045 { 1046 /* CP has detected a non standard number of lines on the incoming 1047 video compared to what it is configured to receive by s_dv_timings */ 1048 return io_read(sd, 0x12) & 0x01; 1049 } 1050 1051 static int adv7604_g_input_status(struct v4l2_subdev *sd, u32 *status) 1052 { 1053 *status = 0; 1054 *status |= no_power(sd) ? V4L2_IN_ST_NO_POWER : 0; 1055 *status |= no_signal(sd) ? V4L2_IN_ST_NO_SIGNAL : 0; 1056 if (no_lock_cp(sd)) 1057 *status |= is_digital_input(sd) ? V4L2_IN_ST_NO_SYNC : V4L2_IN_ST_NO_H_LOCK; 1058 1059 v4l2_dbg(1, debug, sd, "%s: status = 0x%x\n", __func__, *status); 1060 1061 return 0; 1062 } 1063 1064 /* ----------------------------------------------------------------------- */ 1065 1066 struct stdi_readback { 1067 u16 bl, lcf, lcvs; 1068 u8 hs_pol, vs_pol; 1069 bool interlaced; 1070 }; 1071 1072 static int stdi2dv_timings(struct v4l2_subdev *sd, 1073 struct stdi_readback *stdi, 1074 struct v4l2_dv_timings *timings) 1075 { 1076 struct adv7604_state *state = to_state(sd); 1077 u32 hfreq = (ADV7604_fsc * 8) / stdi->bl; 1078 u32 pix_clk; 1079 int i; 1080 1081 for (i = 0; adv7604_timings[i].bt.height; i++) { 1082 if (vtotal(&adv7604_timings[i].bt) != stdi->lcf + 1) 1083 continue; 1084 if (adv7604_timings[i].bt.vsync != stdi->lcvs) 1085 continue; 1086 1087 pix_clk = hfreq * htotal(&adv7604_timings[i].bt); 1088 1089 if ((pix_clk < adv7604_timings[i].bt.pixelclock + 1000000) && 1090 (pix_clk > adv7604_timings[i].bt.pixelclock - 1000000)) { 1091 *timings = adv7604_timings[i]; 1092 return 0; 1093 } 1094 } 1095 1096 if (v4l2_detect_cvt(stdi->lcf + 1, hfreq, stdi->lcvs, 1097 (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) | 1098 (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0), 1099 timings)) 1100 return 0; 1101 if (v4l2_detect_gtf(stdi->lcf + 1, hfreq, stdi->lcvs, 1102 (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) | 1103 (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0), 1104 state->aspect_ratio, timings)) 1105 return 0; 1106 1107 v4l2_dbg(2, debug, sd, 1108 "%s: No format candidate found for lcvs = %d, lcf=%d, bl = %d, %chsync, %cvsync\n", 1109 __func__, stdi->lcvs, stdi->lcf, stdi->bl, 1110 stdi->hs_pol, stdi->vs_pol); 1111 return -1; 1112 } 1113 1114 static int read_stdi(struct v4l2_subdev *sd, struct stdi_readback *stdi) 1115 { 1116 if (no_lock_stdi(sd) || no_lock_sspd(sd)) { 1117 v4l2_dbg(2, debug, sd, "%s: STDI and/or SSPD not locked\n", __func__); 1118 return -1; 1119 } 1120 1121 /* read STDI */ 1122 stdi->bl = ((cp_read(sd, 0xb1) & 0x3f) << 8) | cp_read(sd, 0xb2); 1123 stdi->lcf = ((cp_read(sd, 0xb3) & 0x7) << 8) | cp_read(sd, 0xb4); 1124 stdi->lcvs = cp_read(sd, 0xb3) >> 3; 1125 stdi->interlaced = io_read(sd, 0x12) & 0x10; 1126 1127 /* read SSPD */ 1128 if ((cp_read(sd, 0xb5) & 0x03) == 0x01) { 1129 stdi->hs_pol = ((cp_read(sd, 0xb5) & 0x10) ? 1130 ((cp_read(sd, 0xb5) & 0x08) ? '+' : '-') : 'x'); 1131 stdi->vs_pol = ((cp_read(sd, 0xb5) & 0x40) ? 1132 ((cp_read(sd, 0xb5) & 0x20) ? '+' : '-') : 'x'); 1133 } else { 1134 stdi->hs_pol = 'x'; 1135 stdi->vs_pol = 'x'; 1136 } 1137 1138 if (no_lock_stdi(sd) || no_lock_sspd(sd)) { 1139 v4l2_dbg(2, debug, sd, 1140 "%s: signal lost during readout of STDI/SSPD\n", __func__); 1141 return -1; 1142 } 1143 1144 if (stdi->lcf < 239 || stdi->bl < 8 || stdi->bl == 0x3fff) { 1145 v4l2_dbg(2, debug, sd, "%s: invalid signal\n", __func__); 1146 memset(stdi, 0, sizeof(struct stdi_readback)); 1147 return -1; 1148 } 1149 1150 v4l2_dbg(2, debug, sd, 1151 "%s: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %chsync, %cvsync, %s\n", 1152 __func__, stdi->lcf, stdi->bl, stdi->lcvs, 1153 stdi->hs_pol, stdi->vs_pol, 1154 stdi->interlaced ? "interlaced" : "progressive"); 1155 1156 return 0; 1157 } 1158 1159 static int adv7604_enum_dv_timings(struct v4l2_subdev *sd, 1160 struct v4l2_enum_dv_timings *timings) 1161 { 1162 if (timings->index >= ARRAY_SIZE(adv7604_timings) - 1) 1163 return -EINVAL; 1164 memset(timings->reserved, 0, sizeof(timings->reserved)); 1165 timings->timings = adv7604_timings[timings->index]; 1166 return 0; 1167 } 1168 1169 static int adv7604_dv_timings_cap(struct v4l2_subdev *sd, 1170 struct v4l2_dv_timings_cap *cap) 1171 { 1172 cap->type = V4L2_DV_BT_656_1120; 1173 cap->bt.max_width = 1920; 1174 cap->bt.max_height = 1200; 1175 cap->bt.min_pixelclock = 25000000; 1176 if (is_digital_input(sd)) 1177 cap->bt.max_pixelclock = 225000000; 1178 else 1179 cap->bt.max_pixelclock = 170000000; 1180 cap->bt.standards = V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT | 1181 V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT; 1182 cap->bt.capabilities = V4L2_DV_BT_CAP_PROGRESSIVE | 1183 V4L2_DV_BT_CAP_REDUCED_BLANKING | V4L2_DV_BT_CAP_CUSTOM; 1184 return 0; 1185 } 1186 1187 /* Fill the optional fields .standards and .flags in struct v4l2_dv_timings 1188 if the format is listed in adv7604_timings[] */ 1189 static void adv7604_fill_optional_dv_timings_fields(struct v4l2_subdev *sd, 1190 struct v4l2_dv_timings *timings) 1191 { 1192 int i; 1193 1194 for (i = 0; adv7604_timings[i].bt.width; i++) { 1195 if (v4l2_match_dv_timings(timings, &adv7604_timings[i], 1196 is_digital_input(sd) ? 250000 : 1000000)) { 1197 *timings = adv7604_timings[i]; 1198 break; 1199 } 1200 } 1201 } 1202 1203 static int adv7604_query_dv_timings(struct v4l2_subdev *sd, 1204 struct v4l2_dv_timings *timings) 1205 { 1206 struct adv7604_state *state = to_state(sd); 1207 struct v4l2_bt_timings *bt = &timings->bt; 1208 struct stdi_readback stdi; 1209 1210 if (!timings) 1211 return -EINVAL; 1212 1213 memset(timings, 0, sizeof(struct v4l2_dv_timings)); 1214 1215 if (no_signal(sd)) { 1216 v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__); 1217 return -ENOLINK; 1218 } 1219 1220 /* read STDI */ 1221 if (read_stdi(sd, &stdi)) { 1222 v4l2_dbg(1, debug, sd, "%s: STDI/SSPD not locked\n", __func__); 1223 return -ENOLINK; 1224 } 1225 bt->interlaced = stdi.interlaced ? 1226 V4L2_DV_INTERLACED : V4L2_DV_PROGRESSIVE; 1227 1228 if (is_digital_input(sd)) { 1229 uint32_t freq; 1230 1231 timings->type = V4L2_DV_BT_656_1120; 1232 1233 bt->width = (hdmi_read(sd, 0x07) & 0x0f) * 256 + hdmi_read(sd, 0x08); 1234 bt->height = (hdmi_read(sd, 0x09) & 0x0f) * 256 + hdmi_read(sd, 0x0a); 1235 freq = (hdmi_read(sd, 0x06) * 1000000) + 1236 ((hdmi_read(sd, 0x3b) & 0x30) >> 4) * 250000; 1237 if (is_hdmi(sd)) { 1238 /* adjust for deep color mode */ 1239 unsigned bits_per_channel = ((hdmi_read(sd, 0x0b) & 0x60) >> 4) + 8; 1240 1241 freq = freq * 8 / bits_per_channel; 1242 } 1243 bt->pixelclock = freq; 1244 bt->hfrontporch = (hdmi_read(sd, 0x20) & 0x03) * 256 + 1245 hdmi_read(sd, 0x21); 1246 bt->hsync = (hdmi_read(sd, 0x22) & 0x03) * 256 + 1247 hdmi_read(sd, 0x23); 1248 bt->hbackporch = (hdmi_read(sd, 0x24) & 0x03) * 256 + 1249 hdmi_read(sd, 0x25); 1250 bt->vfrontporch = ((hdmi_read(sd, 0x2a) & 0x1f) * 256 + 1251 hdmi_read(sd, 0x2b)) / 2; 1252 bt->vsync = ((hdmi_read(sd, 0x2e) & 0x1f) * 256 + 1253 hdmi_read(sd, 0x2f)) / 2; 1254 bt->vbackporch = ((hdmi_read(sd, 0x32) & 0x1f) * 256 + 1255 hdmi_read(sd, 0x33)) / 2; 1256 bt->polarities = ((hdmi_read(sd, 0x05) & 0x10) ? V4L2_DV_VSYNC_POS_POL : 0) | 1257 ((hdmi_read(sd, 0x05) & 0x20) ? V4L2_DV_HSYNC_POS_POL : 0); 1258 if (bt->interlaced == V4L2_DV_INTERLACED) { 1259 bt->height += (hdmi_read(sd, 0x0b) & 0x0f) * 256 + 1260 hdmi_read(sd, 0x0c); 1261 bt->il_vfrontporch = ((hdmi_read(sd, 0x2c) & 0x1f) * 256 + 1262 hdmi_read(sd, 0x2d)) / 2; 1263 bt->il_vsync = ((hdmi_read(sd, 0x30) & 0x1f) * 256 + 1264 hdmi_read(sd, 0x31)) / 2; 1265 bt->vbackporch = ((hdmi_read(sd, 0x34) & 0x1f) * 256 + 1266 hdmi_read(sd, 0x35)) / 2; 1267 } 1268 adv7604_fill_optional_dv_timings_fields(sd, timings); 1269 } else { 1270 /* find format 1271 * Since LCVS values are inaccurate [REF_03, p. 275-276], 1272 * stdi2dv_timings() is called with lcvs +-1 if the first attempt fails. 1273 */ 1274 if (!stdi2dv_timings(sd, &stdi, timings)) 1275 goto found; 1276 stdi.lcvs += 1; 1277 v4l2_dbg(1, debug, sd, "%s: lcvs + 1 = %d\n", __func__, stdi.lcvs); 1278 if (!stdi2dv_timings(sd, &stdi, timings)) 1279 goto found; 1280 stdi.lcvs -= 2; 1281 v4l2_dbg(1, debug, sd, "%s: lcvs - 1 = %d\n", __func__, stdi.lcvs); 1282 if (stdi2dv_timings(sd, &stdi, timings)) { 1283 /* 1284 * The STDI block may measure wrong values, especially 1285 * for lcvs and lcf. If the driver can not find any 1286 * valid timing, the STDI block is restarted to measure 1287 * the video timings again. The function will return an 1288 * error, but the restart of STDI will generate a new 1289 * STDI interrupt and the format detection process will 1290 * restart. 1291 */ 1292 if (state->restart_stdi_once) { 1293 v4l2_dbg(1, debug, sd, "%s: restart STDI\n", __func__); 1294 /* TODO restart STDI for Sync Channel 2 */ 1295 /* enter one-shot mode */ 1296 cp_write_and_or(sd, 0x86, 0xf9, 0x00); 1297 /* trigger STDI restart */ 1298 cp_write_and_or(sd, 0x86, 0xf9, 0x04); 1299 /* reset to continuous mode */ 1300 cp_write_and_or(sd, 0x86, 0xf9, 0x02); 1301 state->restart_stdi_once = false; 1302 return -ENOLINK; 1303 } 1304 v4l2_dbg(1, debug, sd, "%s: format not supported\n", __func__); 1305 return -ERANGE; 1306 } 1307 state->restart_stdi_once = true; 1308 } 1309 found: 1310 1311 if (no_signal(sd)) { 1312 v4l2_dbg(1, debug, sd, "%s: signal lost during readout\n", __func__); 1313 memset(timings, 0, sizeof(struct v4l2_dv_timings)); 1314 return -ENOLINK; 1315 } 1316 1317 if ((is_analog_input(sd) && bt->pixelclock > 170000000) || 1318 (is_digital_input(sd) && bt->pixelclock > 225000000)) { 1319 v4l2_dbg(1, debug, sd, "%s: pixelclock out of range %d\n", 1320 __func__, (u32)bt->pixelclock); 1321 return -ERANGE; 1322 } 1323 1324 if (debug > 1) 1325 v4l2_print_dv_timings(sd->name, "adv7604_query_dv_timings: ", 1326 timings, true); 1327 1328 return 0; 1329 } 1330 1331 static int adv7604_s_dv_timings(struct v4l2_subdev *sd, 1332 struct v4l2_dv_timings *timings) 1333 { 1334 struct adv7604_state *state = to_state(sd); 1335 struct v4l2_bt_timings *bt; 1336 int err; 1337 1338 if (!timings) 1339 return -EINVAL; 1340 1341 bt = &timings->bt; 1342 1343 if ((is_analog_input(sd) && bt->pixelclock > 170000000) || 1344 (is_digital_input(sd) && bt->pixelclock > 225000000)) { 1345 v4l2_dbg(1, debug, sd, "%s: pixelclock out of range %d\n", 1346 __func__, (u32)bt->pixelclock); 1347 return -ERANGE; 1348 } 1349 1350 adv7604_fill_optional_dv_timings_fields(sd, timings); 1351 1352 state->timings = *timings; 1353 1354 cp_write(sd, 0x91, bt->interlaced ? 0x50 : 0x10); 1355 1356 /* Use prim_mode and vid_std when available */ 1357 err = configure_predefined_video_timings(sd, timings); 1358 if (err) { 1359 /* custom settings when the video format 1360 does not have prim_mode/vid_std */ 1361 configure_custom_video_timings(sd, bt); 1362 } 1363 1364 set_rgb_quantization_range(sd); 1365 1366 1367 if (debug > 1) 1368 v4l2_print_dv_timings(sd->name, "adv7604_s_dv_timings: ", 1369 timings, true); 1370 return 0; 1371 } 1372 1373 static int adv7604_g_dv_timings(struct v4l2_subdev *sd, 1374 struct v4l2_dv_timings *timings) 1375 { 1376 struct adv7604_state *state = to_state(sd); 1377 1378 *timings = state->timings; 1379 return 0; 1380 } 1381 1382 static void enable_input(struct v4l2_subdev *sd) 1383 { 1384 struct adv7604_state *state = to_state(sd); 1385 1386 if (is_analog_input(sd)) { 1387 /* enable */ 1388 io_write(sd, 0x15, 0xb0); /* Disable Tristate of Pins (no audio) */ 1389 } else if (is_digital_input(sd)) { 1390 /* enable */ 1391 hdmi_write_and_or(sd, 0x00, 0xfc, state->selected_input); 1392 hdmi_write(sd, 0x1a, 0x0a); /* Unmute audio */ 1393 hdmi_write(sd, 0x01, 0x00); /* Enable HDMI clock terminators */ 1394 io_write(sd, 0x15, 0xa0); /* Disable Tristate of Pins */ 1395 } else { 1396 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n", 1397 __func__, state->selected_input); 1398 } 1399 } 1400 1401 static void disable_input(struct v4l2_subdev *sd) 1402 { 1403 /* disable */ 1404 io_write(sd, 0x15, 0xbe); /* Tristate all outputs from video core */ 1405 hdmi_write(sd, 0x1a, 0x1a); /* Mute audio */ 1406 hdmi_write(sd, 0x01, 0x78); /* Disable HDMI clock terminators */ 1407 } 1408 1409 static void select_input(struct v4l2_subdev *sd) 1410 { 1411 struct adv7604_state *state = to_state(sd); 1412 1413 if (is_analog_input(sd)) { 1414 /* reset ADI recommended settings for HDMI: */ 1415 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 4. */ 1416 hdmi_write(sd, 0x0d, 0x04); /* HDMI filter optimization */ 1417 hdmi_write(sd, 0x3d, 0x00); /* DDC bus active pull-up control */ 1418 hdmi_write(sd, 0x3e, 0x74); /* TMDS PLL optimization */ 1419 hdmi_write(sd, 0x4e, 0x3b); /* TMDS PLL optimization */ 1420 hdmi_write(sd, 0x57, 0x74); /* TMDS PLL optimization */ 1421 hdmi_write(sd, 0x58, 0x63); /* TMDS PLL optimization */ 1422 hdmi_write(sd, 0x8d, 0x18); /* equaliser */ 1423 hdmi_write(sd, 0x8e, 0x34); /* equaliser */ 1424 hdmi_write(sd, 0x93, 0x88); /* equaliser */ 1425 hdmi_write(sd, 0x94, 0x2e); /* equaliser */ 1426 hdmi_write(sd, 0x96, 0x00); /* enable automatic EQ changing */ 1427 1428 afe_write(sd, 0x00, 0x08); /* power up ADC */ 1429 afe_write(sd, 0x01, 0x06); /* power up Analog Front End */ 1430 afe_write(sd, 0xc8, 0x00); /* phase control */ 1431 1432 /* set ADI recommended settings for digitizer */ 1433 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 17. */ 1434 afe_write(sd, 0x12, 0x7b); /* ADC noise shaping filter controls */ 1435 afe_write(sd, 0x0c, 0x1f); /* CP core gain controls */ 1436 cp_write(sd, 0x3e, 0x04); /* CP core pre-gain control */ 1437 cp_write(sd, 0xc3, 0x39); /* CP coast control. Graphics mode */ 1438 cp_write(sd, 0x40, 0x5c); /* CP core pre-gain control. Graphics mode */ 1439 } else if (is_digital_input(sd)) { 1440 hdmi_write(sd, 0x00, state->selected_input & 0x03); 1441 1442 /* set ADI recommended settings for HDMI: */ 1443 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 4. */ 1444 hdmi_write(sd, 0x0d, 0x84); /* HDMI filter optimization */ 1445 hdmi_write(sd, 0x3d, 0x10); /* DDC bus active pull-up control */ 1446 hdmi_write(sd, 0x3e, 0x39); /* TMDS PLL optimization */ 1447 hdmi_write(sd, 0x4e, 0x3b); /* TMDS PLL optimization */ 1448 hdmi_write(sd, 0x57, 0xb6); /* TMDS PLL optimization */ 1449 hdmi_write(sd, 0x58, 0x03); /* TMDS PLL optimization */ 1450 hdmi_write(sd, 0x8d, 0x18); /* equaliser */ 1451 hdmi_write(sd, 0x8e, 0x34); /* equaliser */ 1452 hdmi_write(sd, 0x93, 0x8b); /* equaliser */ 1453 hdmi_write(sd, 0x94, 0x2d); /* equaliser */ 1454 hdmi_write(sd, 0x96, 0x01); /* enable automatic EQ changing */ 1455 1456 afe_write(sd, 0x00, 0xff); /* power down ADC */ 1457 afe_write(sd, 0x01, 0xfe); /* power down Analog Front End */ 1458 afe_write(sd, 0xc8, 0x40); /* phase control */ 1459 1460 /* reset ADI recommended settings for digitizer */ 1461 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 17. */ 1462 afe_write(sd, 0x12, 0xfb); /* ADC noise shaping filter controls */ 1463 afe_write(sd, 0x0c, 0x0d); /* CP core gain controls */ 1464 cp_write(sd, 0x3e, 0x00); /* CP core pre-gain control */ 1465 cp_write(sd, 0xc3, 0x39); /* CP coast control. Graphics mode */ 1466 cp_write(sd, 0x40, 0x80); /* CP core pre-gain control. Graphics mode */ 1467 } else { 1468 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n", 1469 __func__, state->selected_input); 1470 } 1471 } 1472 1473 static int adv7604_s_routing(struct v4l2_subdev *sd, 1474 u32 input, u32 output, u32 config) 1475 { 1476 struct adv7604_state *state = to_state(sd); 1477 1478 v4l2_dbg(2, debug, sd, "%s: input %d", __func__, input); 1479 1480 state->selected_input = input; 1481 1482 disable_input(sd); 1483 1484 select_input(sd); 1485 1486 enable_input(sd); 1487 1488 return 0; 1489 } 1490 1491 static int adv7604_enum_mbus_fmt(struct v4l2_subdev *sd, unsigned int index, 1492 enum v4l2_mbus_pixelcode *code) 1493 { 1494 if (index) 1495 return -EINVAL; 1496 /* Good enough for now */ 1497 *code = V4L2_MBUS_FMT_FIXED; 1498 return 0; 1499 } 1500 1501 static int adv7604_g_mbus_fmt(struct v4l2_subdev *sd, 1502 struct v4l2_mbus_framefmt *fmt) 1503 { 1504 struct adv7604_state *state = to_state(sd); 1505 1506 fmt->width = state->timings.bt.width; 1507 fmt->height = state->timings.bt.height; 1508 fmt->code = V4L2_MBUS_FMT_FIXED; 1509 fmt->field = V4L2_FIELD_NONE; 1510 if (state->timings.bt.standards & V4L2_DV_BT_STD_CEA861) { 1511 fmt->colorspace = (state->timings.bt.height <= 576) ? 1512 V4L2_COLORSPACE_SMPTE170M : V4L2_COLORSPACE_REC709; 1513 } 1514 return 0; 1515 } 1516 1517 static int adv7604_isr(struct v4l2_subdev *sd, u32 status, bool *handled) 1518 { 1519 struct adv7604_state *state = to_state(sd); 1520 u8 fmt_change, fmt_change_digital, tx_5v; 1521 u32 input_status; 1522 1523 /* format change */ 1524 fmt_change = io_read(sd, 0x43) & 0x98; 1525 if (fmt_change) 1526 io_write(sd, 0x44, fmt_change); 1527 fmt_change_digital = is_digital_input(sd) ? (io_read(sd, 0x6b) & 0xc0) : 0; 1528 if (fmt_change_digital) 1529 io_write(sd, 0x6c, fmt_change_digital); 1530 if (fmt_change || fmt_change_digital) { 1531 v4l2_dbg(1, debug, sd, 1532 "%s: fmt_change = 0x%x, fmt_change_digital = 0x%x\n", 1533 __func__, fmt_change, fmt_change_digital); 1534 1535 adv7604_g_input_status(sd, &input_status); 1536 if (input_status != state->prev_input_status) { 1537 v4l2_dbg(1, debug, sd, 1538 "%s: input_status = 0x%x, prev_input_status = 0x%x\n", 1539 __func__, input_status, state->prev_input_status); 1540 state->prev_input_status = input_status; 1541 v4l2_subdev_notify(sd, ADV7604_FMT_CHANGE, NULL); 1542 } 1543 1544 if (handled) 1545 *handled = true; 1546 } 1547 /* tx 5v detect */ 1548 tx_5v = io_read(sd, 0x70) & 0x1e; 1549 if (tx_5v) { 1550 v4l2_dbg(1, debug, sd, "%s: tx_5v: 0x%x\n", __func__, tx_5v); 1551 io_write(sd, 0x71, tx_5v); 1552 adv7604_s_detect_tx_5v_ctrl(sd); 1553 if (handled) 1554 *handled = true; 1555 } 1556 return 0; 1557 } 1558 1559 static int adv7604_get_edid(struct v4l2_subdev *sd, struct v4l2_subdev_edid *edid) 1560 { 1561 struct adv7604_state *state = to_state(sd); 1562 u8 *data = NULL; 1563 1564 if (edid->pad > ADV7604_EDID_PORT_D) 1565 return -EINVAL; 1566 if (edid->blocks == 0) 1567 return -EINVAL; 1568 if (edid->blocks > 2) 1569 return -EINVAL; 1570 if (edid->start_block > 1) 1571 return -EINVAL; 1572 if (edid->start_block == 1) 1573 edid->blocks = 1; 1574 if (!edid->edid) 1575 return -EINVAL; 1576 1577 if (edid->blocks > state->edid.blocks) 1578 edid->blocks = state->edid.blocks; 1579 1580 switch (edid->pad) { 1581 case ADV7604_EDID_PORT_A: 1582 case ADV7604_EDID_PORT_B: 1583 case ADV7604_EDID_PORT_C: 1584 case ADV7604_EDID_PORT_D: 1585 if (state->edid.present & (1 << edid->pad)) 1586 data = state->edid.edid; 1587 break; 1588 default: 1589 return -EINVAL; 1590 break; 1591 } 1592 if (!data) 1593 return -ENODATA; 1594 1595 memcpy(edid->edid, 1596 data + edid->start_block * 128, 1597 edid->blocks * 128); 1598 return 0; 1599 } 1600 1601 static int adv7604_set_edid(struct v4l2_subdev *sd, struct v4l2_subdev_edid *edid) 1602 { 1603 struct adv7604_state *state = to_state(sd); 1604 int err; 1605 1606 if (edid->pad > ADV7604_EDID_PORT_D) 1607 return -EINVAL; 1608 if (edid->start_block != 0) 1609 return -EINVAL; 1610 if (edid->blocks == 0) { 1611 /* Pull down the hotplug pin */ 1612 state->edid.present &= ~(1 << edid->pad); 1613 v4l2_subdev_notify(sd, ADV7604_HOTPLUG, (void *)&state->edid.present); 1614 /* Disables I2C access to internal EDID ram from DDC port */ 1615 rep_write_and_or(sd, 0x77, 0xf0, 0x0); 1616 state->edid.blocks = 0; 1617 /* Fall back to a 16:9 aspect ratio */ 1618 state->aspect_ratio.numerator = 16; 1619 state->aspect_ratio.denominator = 9; 1620 v4l2_dbg(2, debug, sd, "%s: clear edid\n", __func__); 1621 return 0; 1622 } 1623 if (edid->blocks > 2) { 1624 edid->blocks = 2; 1625 return -E2BIG; 1626 } 1627 if (!edid->edid) 1628 return -EINVAL; 1629 1630 cancel_delayed_work_sync(&state->delayed_work_enable_hotplug); 1631 state->edid.present &= ~(1 << edid->pad); 1632 v4l2_subdev_notify(sd, ADV7604_HOTPLUG, (void *)&state->edid.present); 1633 1634 memcpy(state->edid.edid, edid->edid, 128 * edid->blocks); 1635 state->edid.blocks = edid->blocks; 1636 state->aspect_ratio = v4l2_calc_aspect_ratio(edid->edid[0x15], 1637 edid->edid[0x16]); 1638 state->edid.present |= edid->pad; 1639 1640 err = edid_write_block(sd, 128 * edid->blocks, state->edid.edid); 1641 if (err < 0) { 1642 v4l2_err(sd, "error %d writing edid\n", err); 1643 return err; 1644 } 1645 1646 /* enable hotplug after 100 ms */ 1647 queue_delayed_work(state->work_queues, 1648 &state->delayed_work_enable_hotplug, HZ / 10); 1649 return 0; 1650 } 1651 1652 /*********** avi info frame CEA-861-E **************/ 1653 1654 static void print_avi_infoframe(struct v4l2_subdev *sd) 1655 { 1656 int i; 1657 u8 buf[14]; 1658 u8 avi_len; 1659 u8 avi_ver; 1660 1661 if (!is_hdmi(sd)) { 1662 v4l2_info(sd, "receive DVI-D signal (AVI infoframe not supported)\n"); 1663 return; 1664 } 1665 if (!(io_read(sd, 0x60) & 0x01)) { 1666 v4l2_info(sd, "AVI infoframe not received\n"); 1667 return; 1668 } 1669 1670 if (io_read(sd, 0x83) & 0x01) { 1671 v4l2_info(sd, "AVI infoframe checksum error has occurred earlier\n"); 1672 io_write(sd, 0x85, 0x01); /* clear AVI_INF_CKS_ERR_RAW */ 1673 if (io_read(sd, 0x83) & 0x01) { 1674 v4l2_info(sd, "AVI infoframe checksum error still present\n"); 1675 io_write(sd, 0x85, 0x01); /* clear AVI_INF_CKS_ERR_RAW */ 1676 } 1677 } 1678 1679 avi_len = infoframe_read(sd, 0xe2); 1680 avi_ver = infoframe_read(sd, 0xe1); 1681 v4l2_info(sd, "AVI infoframe version %d (%d byte)\n", 1682 avi_ver, avi_len); 1683 1684 if (avi_ver != 0x02) 1685 return; 1686 1687 for (i = 0; i < 14; i++) 1688 buf[i] = infoframe_read(sd, i); 1689 1690 v4l2_info(sd, 1691 "\t%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n", 1692 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6], buf[7], 1693 buf[8], buf[9], buf[10], buf[11], buf[12], buf[13]); 1694 } 1695 1696 static int adv7604_log_status(struct v4l2_subdev *sd) 1697 { 1698 struct adv7604_state *state = to_state(sd); 1699 struct v4l2_dv_timings timings; 1700 struct stdi_readback stdi; 1701 u8 reg_io_0x02 = io_read(sd, 0x02); 1702 1703 char *csc_coeff_sel_rb[16] = { 1704 "bypassed", "YPbPr601 -> RGB", "reserved", "YPbPr709 -> RGB", 1705 "reserved", "RGB -> YPbPr601", "reserved", "RGB -> YPbPr709", 1706 "reserved", "YPbPr709 -> YPbPr601", "YPbPr601 -> YPbPr709", 1707 "reserved", "reserved", "reserved", "reserved", "manual" 1708 }; 1709 char *input_color_space_txt[16] = { 1710 "RGB limited range (16-235)", "RGB full range (0-255)", 1711 "YCbCr Bt.601 (16-235)", "YCbCr Bt.709 (16-235)", 1712 "XvYCC Bt.601", "XvYCC Bt.709", 1713 "YCbCr Bt.601 (0-255)", "YCbCr Bt.709 (0-255)", 1714 "invalid", "invalid", "invalid", "invalid", "invalid", 1715 "invalid", "invalid", "automatic" 1716 }; 1717 char *rgb_quantization_range_txt[] = { 1718 "Automatic", 1719 "RGB limited range (16-235)", 1720 "RGB full range (0-255)", 1721 }; 1722 char *deep_color_mode_txt[4] = { 1723 "8-bits per channel", 1724 "10-bits per channel", 1725 "12-bits per channel", 1726 "16-bits per channel (not supported)" 1727 }; 1728 1729 v4l2_info(sd, "-----Chip status-----\n"); 1730 v4l2_info(sd, "Chip power: %s\n", no_power(sd) ? "off" : "on"); 1731 v4l2_info(sd, "Connector type: %s\n", state->connector_hdmi ? 1732 "HDMI" : (is_digital_input(sd) ? "DVI-D" : "DVI-A")); 1733 v4l2_info(sd, "EDID enabled port A: %s, B: %s, C: %s, D: %s\n", 1734 ((rep_read(sd, 0x7d) & 0x01) ? "Yes" : "No"), 1735 ((rep_read(sd, 0x7d) & 0x02) ? "Yes" : "No"), 1736 ((rep_read(sd, 0x7d) & 0x04) ? "Yes" : "No"), 1737 ((rep_read(sd, 0x7d) & 0x08) ? "Yes" : "No")); 1738 v4l2_info(sd, "CEC: %s\n", !!(cec_read(sd, 0x2a) & 0x01) ? 1739 "enabled" : "disabled"); 1740 1741 v4l2_info(sd, "-----Signal status-----\n"); 1742 v4l2_info(sd, "Cable detected (+5V power) port A: %s, B: %s, C: %s, D: %s\n", 1743 ((io_read(sd, 0x6f) & 0x10) ? "Yes" : "No"), 1744 ((io_read(sd, 0x6f) & 0x08) ? "Yes" : "No"), 1745 ((io_read(sd, 0x6f) & 0x04) ? "Yes" : "No"), 1746 ((io_read(sd, 0x6f) & 0x02) ? "Yes" : "No")); 1747 v4l2_info(sd, "TMDS signal detected: %s\n", 1748 no_signal_tmds(sd) ? "false" : "true"); 1749 v4l2_info(sd, "TMDS signal locked: %s\n", 1750 no_lock_tmds(sd) ? "false" : "true"); 1751 v4l2_info(sd, "SSPD locked: %s\n", no_lock_sspd(sd) ? "false" : "true"); 1752 v4l2_info(sd, "STDI locked: %s\n", no_lock_stdi(sd) ? "false" : "true"); 1753 v4l2_info(sd, "CP locked: %s\n", no_lock_cp(sd) ? "false" : "true"); 1754 v4l2_info(sd, "CP free run: %s\n", 1755 (!!(cp_read(sd, 0xff) & 0x10) ? "on" : "off")); 1756 v4l2_info(sd, "Prim-mode = 0x%x, video std = 0x%x, v_freq = 0x%x\n", 1757 io_read(sd, 0x01) & 0x0f, io_read(sd, 0x00) & 0x3f, 1758 (io_read(sd, 0x01) & 0x70) >> 4); 1759 1760 v4l2_info(sd, "-----Video Timings-----\n"); 1761 if (read_stdi(sd, &stdi)) 1762 v4l2_info(sd, "STDI: not locked\n"); 1763 else 1764 v4l2_info(sd, "STDI: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %s, %chsync, %cvsync\n", 1765 stdi.lcf, stdi.bl, stdi.lcvs, 1766 stdi.interlaced ? "interlaced" : "progressive", 1767 stdi.hs_pol, stdi.vs_pol); 1768 if (adv7604_query_dv_timings(sd, &timings)) 1769 v4l2_info(sd, "No video detected\n"); 1770 else 1771 v4l2_print_dv_timings(sd->name, "Detected format: ", 1772 &timings, true); 1773 v4l2_print_dv_timings(sd->name, "Configured format: ", 1774 &state->timings, true); 1775 1776 if (no_signal(sd)) 1777 return 0; 1778 1779 v4l2_info(sd, "-----Color space-----\n"); 1780 v4l2_info(sd, "RGB quantization range ctrl: %s\n", 1781 rgb_quantization_range_txt[state->rgb_quantization_range]); 1782 v4l2_info(sd, "Input color space: %s\n", 1783 input_color_space_txt[reg_io_0x02 >> 4]); 1784 v4l2_info(sd, "Output color space: %s %s, saturator %s\n", 1785 (reg_io_0x02 & 0x02) ? "RGB" : "YCbCr", 1786 (reg_io_0x02 & 0x04) ? "(16-235)" : "(0-255)", 1787 ((reg_io_0x02 & 0x04) ^ (reg_io_0x02 & 0x01)) ? 1788 "enabled" : "disabled"); 1789 v4l2_info(sd, "Color space conversion: %s\n", 1790 csc_coeff_sel_rb[cp_read(sd, 0xfc) >> 4]); 1791 1792 if (!is_digital_input(sd)) 1793 return 0; 1794 1795 v4l2_info(sd, "-----%s status-----\n", is_hdmi(sd) ? "HDMI" : "DVI-D"); 1796 v4l2_info(sd, "Digital video port selected: %c\n", 1797 (hdmi_read(sd, 0x00) & 0x03) + 'A'); 1798 v4l2_info(sd, "HDCP encrypted content: %s\n", 1799 (hdmi_read(sd, 0x05) & 0x40) ? "true" : "false"); 1800 v4l2_info(sd, "HDCP keys read: %s%s\n", 1801 (hdmi_read(sd, 0x04) & 0x20) ? "yes" : "no", 1802 (hdmi_read(sd, 0x04) & 0x10) ? "ERROR" : ""); 1803 if (!is_hdmi(sd)) { 1804 bool audio_pll_locked = hdmi_read(sd, 0x04) & 0x01; 1805 bool audio_sample_packet_detect = hdmi_read(sd, 0x18) & 0x01; 1806 bool audio_mute = io_read(sd, 0x65) & 0x40; 1807 1808 v4l2_info(sd, "Audio: pll %s, samples %s, %s\n", 1809 audio_pll_locked ? "locked" : "not locked", 1810 audio_sample_packet_detect ? "detected" : "not detected", 1811 audio_mute ? "muted" : "enabled"); 1812 if (audio_pll_locked && audio_sample_packet_detect) { 1813 v4l2_info(sd, "Audio format: %s\n", 1814 (hdmi_read(sd, 0x07) & 0x20) ? "multi-channel" : "stereo"); 1815 } 1816 v4l2_info(sd, "Audio CTS: %u\n", (hdmi_read(sd, 0x5b) << 12) + 1817 (hdmi_read(sd, 0x5c) << 8) + 1818 (hdmi_read(sd, 0x5d) & 0xf0)); 1819 v4l2_info(sd, "Audio N: %u\n", ((hdmi_read(sd, 0x5d) & 0x0f) << 16) + 1820 (hdmi_read(sd, 0x5e) << 8) + 1821 hdmi_read(sd, 0x5f)); 1822 v4l2_info(sd, "AV Mute: %s\n", (hdmi_read(sd, 0x04) & 0x40) ? "on" : "off"); 1823 1824 v4l2_info(sd, "Deep color mode: %s\n", deep_color_mode_txt[(hdmi_read(sd, 0x0b) & 0x60) >> 5]); 1825 1826 print_avi_infoframe(sd); 1827 } 1828 1829 return 0; 1830 } 1831 1832 /* ----------------------------------------------------------------------- */ 1833 1834 static const struct v4l2_ctrl_ops adv7604_ctrl_ops = { 1835 .s_ctrl = adv7604_s_ctrl, 1836 }; 1837 1838 static const struct v4l2_subdev_core_ops adv7604_core_ops = { 1839 .log_status = adv7604_log_status, 1840 .g_ext_ctrls = v4l2_subdev_g_ext_ctrls, 1841 .try_ext_ctrls = v4l2_subdev_try_ext_ctrls, 1842 .s_ext_ctrls = v4l2_subdev_s_ext_ctrls, 1843 .g_ctrl = v4l2_subdev_g_ctrl, 1844 .s_ctrl = v4l2_subdev_s_ctrl, 1845 .queryctrl = v4l2_subdev_queryctrl, 1846 .querymenu = v4l2_subdev_querymenu, 1847 .interrupt_service_routine = adv7604_isr, 1848 #ifdef CONFIG_VIDEO_ADV_DEBUG 1849 .g_register = adv7604_g_register, 1850 .s_register = adv7604_s_register, 1851 #endif 1852 }; 1853 1854 static const struct v4l2_subdev_video_ops adv7604_video_ops = { 1855 .s_routing = adv7604_s_routing, 1856 .g_input_status = adv7604_g_input_status, 1857 .s_dv_timings = adv7604_s_dv_timings, 1858 .g_dv_timings = adv7604_g_dv_timings, 1859 .query_dv_timings = adv7604_query_dv_timings, 1860 .enum_dv_timings = adv7604_enum_dv_timings, 1861 .dv_timings_cap = adv7604_dv_timings_cap, 1862 .enum_mbus_fmt = adv7604_enum_mbus_fmt, 1863 .g_mbus_fmt = adv7604_g_mbus_fmt, 1864 .try_mbus_fmt = adv7604_g_mbus_fmt, 1865 .s_mbus_fmt = adv7604_g_mbus_fmt, 1866 }; 1867 1868 static const struct v4l2_subdev_pad_ops adv7604_pad_ops = { 1869 .get_edid = adv7604_get_edid, 1870 .set_edid = adv7604_set_edid, 1871 }; 1872 1873 static const struct v4l2_subdev_ops adv7604_ops = { 1874 .core = &adv7604_core_ops, 1875 .video = &adv7604_video_ops, 1876 .pad = &adv7604_pad_ops, 1877 }; 1878 1879 /* -------------------------- custom ctrls ---------------------------------- */ 1880 1881 static const struct v4l2_ctrl_config adv7604_ctrl_analog_sampling_phase = { 1882 .ops = &adv7604_ctrl_ops, 1883 .id = V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE, 1884 .name = "Analog Sampling Phase", 1885 .type = V4L2_CTRL_TYPE_INTEGER, 1886 .min = 0, 1887 .max = 0x1f, 1888 .step = 1, 1889 .def = 0, 1890 }; 1891 1892 static const struct v4l2_ctrl_config adv7604_ctrl_free_run_color_manual = { 1893 .ops = &adv7604_ctrl_ops, 1894 .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL, 1895 .name = "Free Running Color, Manual", 1896 .type = V4L2_CTRL_TYPE_BOOLEAN, 1897 .min = false, 1898 .max = true, 1899 .step = 1, 1900 .def = false, 1901 }; 1902 1903 static const struct v4l2_ctrl_config adv7604_ctrl_free_run_color = { 1904 .ops = &adv7604_ctrl_ops, 1905 .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR, 1906 .name = "Free Running Color", 1907 .type = V4L2_CTRL_TYPE_INTEGER, 1908 .min = 0x0, 1909 .max = 0xffffff, 1910 .step = 0x1, 1911 .def = 0x0, 1912 }; 1913 1914 /* ----------------------------------------------------------------------- */ 1915 1916 static int adv7604_core_init(struct v4l2_subdev *sd) 1917 { 1918 struct adv7604_state *state = to_state(sd); 1919 struct adv7604_platform_data *pdata = &state->pdata; 1920 1921 hdmi_write(sd, 0x48, 1922 (pdata->disable_pwrdnb ? 0x80 : 0) | 1923 (pdata->disable_cable_det_rst ? 0x40 : 0)); 1924 1925 disable_input(sd); 1926 1927 /* power */ 1928 io_write(sd, 0x0c, 0x42); /* Power up part and power down VDP */ 1929 io_write(sd, 0x0b, 0x44); /* Power down ESDP block */ 1930 cp_write(sd, 0xcf, 0x01); /* Power down macrovision */ 1931 1932 /* video format */ 1933 io_write_and_or(sd, 0x02, 0xf0, 1934 pdata->alt_gamma << 3 | 1935 pdata->op_656_range << 2 | 1936 pdata->rgb_out << 1 | 1937 pdata->alt_data_sat << 0); 1938 io_write(sd, 0x03, pdata->op_format_sel); 1939 io_write_and_or(sd, 0x04, 0x1f, pdata->op_ch_sel << 5); 1940 io_write_and_or(sd, 0x05, 0xf0, pdata->blank_data << 3 | 1941 pdata->insert_av_codes << 2 | 1942 pdata->replicate_av_codes << 1 | 1943 pdata->invert_cbcr << 0); 1944 1945 /* TODO from platform data */ 1946 cp_write(sd, 0x69, 0x30); /* Enable CP CSC */ 1947 io_write(sd, 0x06, 0xa6); /* positive VS and HS */ 1948 1949 /* Adjust drive strength */ 1950 io_write(sd, 0x14, 0x40 | pdata->dr_str_data << 4 | 1951 pdata->dr_str_clk << 2 | 1952 pdata->dr_str_sync); 1953 1954 cp_write(sd, 0xba, (pdata->hdmi_free_run_mode << 1) | 0x01); /* HDMI free run */ 1955 cp_write(sd, 0xf3, 0xdc); /* Low threshold to enter/exit free run mode */ 1956 cp_write(sd, 0xf9, 0x23); /* STDI ch. 1 - LCVS change threshold - 1957 ADI recommended setting [REF_01, c. 2.3.3] */ 1958 cp_write(sd, 0x45, 0x23); /* STDI ch. 2 - LCVS change threshold - 1959 ADI recommended setting [REF_01, c. 2.3.3] */ 1960 cp_write(sd, 0xc9, 0x2d); /* use prim_mode and vid_std as free run resolution 1961 for digital formats */ 1962 rep_write(sd, 0x76, 0xc0); /* SPA location for port B, C and D */ 1963 1964 /* TODO from platform data */ 1965 afe_write(sd, 0xb5, 0x01); /* Setting MCLK to 256Fs */ 1966 1967 afe_write(sd, 0x02, pdata->ain_sel); /* Select analog input muxing mode */ 1968 io_write_and_or(sd, 0x30, ~(1 << 4), pdata->output_bus_lsb_to_msb << 4); 1969 1970 /* interrupts */ 1971 io_write(sd, 0x40, 0xc2); /* Configure INT1 */ 1972 io_write(sd, 0x41, 0xd7); /* STDI irq for any change, disable INT2 */ 1973 io_write(sd, 0x46, 0x98); /* Enable SSPD, STDI and CP unlocked interrupts */ 1974 io_write(sd, 0x6e, 0xc0); /* Enable V_LOCKED and DE_REGEN_LCK interrupts */ 1975 io_write(sd, 0x73, 0x1e); /* Enable CABLE_DET_A_ST (+5v) interrupts */ 1976 1977 return v4l2_ctrl_handler_setup(sd->ctrl_handler); 1978 } 1979 1980 static void adv7604_unregister_clients(struct adv7604_state *state) 1981 { 1982 if (state->i2c_avlink) 1983 i2c_unregister_device(state->i2c_avlink); 1984 if (state->i2c_cec) 1985 i2c_unregister_device(state->i2c_cec); 1986 if (state->i2c_infoframe) 1987 i2c_unregister_device(state->i2c_infoframe); 1988 if (state->i2c_esdp) 1989 i2c_unregister_device(state->i2c_esdp); 1990 if (state->i2c_dpp) 1991 i2c_unregister_device(state->i2c_dpp); 1992 if (state->i2c_afe) 1993 i2c_unregister_device(state->i2c_afe); 1994 if (state->i2c_repeater) 1995 i2c_unregister_device(state->i2c_repeater); 1996 if (state->i2c_edid) 1997 i2c_unregister_device(state->i2c_edid); 1998 if (state->i2c_hdmi) 1999 i2c_unregister_device(state->i2c_hdmi); 2000 if (state->i2c_test) 2001 i2c_unregister_device(state->i2c_test); 2002 if (state->i2c_cp) 2003 i2c_unregister_device(state->i2c_cp); 2004 if (state->i2c_vdp) 2005 i2c_unregister_device(state->i2c_vdp); 2006 } 2007 2008 static struct i2c_client *adv7604_dummy_client(struct v4l2_subdev *sd, 2009 u8 addr, u8 io_reg) 2010 { 2011 struct i2c_client *client = v4l2_get_subdevdata(sd); 2012 2013 if (addr) 2014 io_write(sd, io_reg, addr << 1); 2015 return i2c_new_dummy(client->adapter, io_read(sd, io_reg) >> 1); 2016 } 2017 2018 static int adv7604_probe(struct i2c_client *client, 2019 const struct i2c_device_id *id) 2020 { 2021 struct adv7604_state *state; 2022 struct adv7604_platform_data *pdata = client->dev.platform_data; 2023 struct v4l2_ctrl_handler *hdl; 2024 struct v4l2_subdev *sd; 2025 int err; 2026 2027 /* Check if the adapter supports the needed features */ 2028 if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA)) 2029 return -EIO; 2030 v4l_dbg(1, debug, client, "detecting adv7604 client on address 0x%x\n", 2031 client->addr << 1); 2032 2033 state = devm_kzalloc(&client->dev, sizeof(*state), GFP_KERNEL); 2034 if (!state) { 2035 v4l_err(client, "Could not allocate adv7604_state memory!\n"); 2036 return -ENOMEM; 2037 } 2038 2039 /* initialize variables */ 2040 state->restart_stdi_once = true; 2041 state->prev_input_status = ~0; 2042 2043 /* platform data */ 2044 if (!pdata) { 2045 v4l_err(client, "No platform data!\n"); 2046 return -ENODEV; 2047 } 2048 memcpy(&state->pdata, pdata, sizeof(state->pdata)); 2049 2050 sd = &state->sd; 2051 v4l2_i2c_subdev_init(sd, client, &adv7604_ops); 2052 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; 2053 state->connector_hdmi = pdata->connector_hdmi; 2054 2055 /* i2c access to adv7604? */ 2056 if (adv_smbus_read_byte_data_check(client, 0xfb, false) != 0x68) { 2057 v4l2_info(sd, "not an adv7604 on address 0x%x\n", 2058 client->addr << 1); 2059 return -ENODEV; 2060 } 2061 2062 /* control handlers */ 2063 hdl = &state->hdl; 2064 v4l2_ctrl_handler_init(hdl, 9); 2065 2066 v4l2_ctrl_new_std(hdl, &adv7604_ctrl_ops, 2067 V4L2_CID_BRIGHTNESS, -128, 127, 1, 0); 2068 v4l2_ctrl_new_std(hdl, &adv7604_ctrl_ops, 2069 V4L2_CID_CONTRAST, 0, 255, 1, 128); 2070 v4l2_ctrl_new_std(hdl, &adv7604_ctrl_ops, 2071 V4L2_CID_SATURATION, 0, 255, 1, 128); 2072 v4l2_ctrl_new_std(hdl, &adv7604_ctrl_ops, 2073 V4L2_CID_HUE, 0, 128, 1, 0); 2074 2075 /* private controls */ 2076 state->detect_tx_5v_ctrl = v4l2_ctrl_new_std(hdl, NULL, 2077 V4L2_CID_DV_RX_POWER_PRESENT, 0, 0x0f, 0, 0); 2078 state->rgb_quantization_range_ctrl = 2079 v4l2_ctrl_new_std_menu(hdl, &adv7604_ctrl_ops, 2080 V4L2_CID_DV_RX_RGB_RANGE, V4L2_DV_RGB_RANGE_FULL, 2081 0, V4L2_DV_RGB_RANGE_AUTO); 2082 2083 /* custom controls */ 2084 state->analog_sampling_phase_ctrl = 2085 v4l2_ctrl_new_custom(hdl, &adv7604_ctrl_analog_sampling_phase, NULL); 2086 state->free_run_color_manual_ctrl = 2087 v4l2_ctrl_new_custom(hdl, &adv7604_ctrl_free_run_color_manual, NULL); 2088 state->free_run_color_ctrl = 2089 v4l2_ctrl_new_custom(hdl, &adv7604_ctrl_free_run_color, NULL); 2090 2091 sd->ctrl_handler = hdl; 2092 if (hdl->error) { 2093 err = hdl->error; 2094 goto err_hdl; 2095 } 2096 state->detect_tx_5v_ctrl->is_private = true; 2097 state->rgb_quantization_range_ctrl->is_private = true; 2098 state->analog_sampling_phase_ctrl->is_private = true; 2099 state->free_run_color_manual_ctrl->is_private = true; 2100 state->free_run_color_ctrl->is_private = true; 2101 2102 if (adv7604_s_detect_tx_5v_ctrl(sd)) { 2103 err = -ENODEV; 2104 goto err_hdl; 2105 } 2106 2107 state->i2c_avlink = adv7604_dummy_client(sd, pdata->i2c_avlink, 0xf3); 2108 state->i2c_cec = adv7604_dummy_client(sd, pdata->i2c_cec, 0xf4); 2109 state->i2c_infoframe = adv7604_dummy_client(sd, pdata->i2c_infoframe, 0xf5); 2110 state->i2c_esdp = adv7604_dummy_client(sd, pdata->i2c_esdp, 0xf6); 2111 state->i2c_dpp = adv7604_dummy_client(sd, pdata->i2c_dpp, 0xf7); 2112 state->i2c_afe = adv7604_dummy_client(sd, pdata->i2c_afe, 0xf8); 2113 state->i2c_repeater = adv7604_dummy_client(sd, pdata->i2c_repeater, 0xf9); 2114 state->i2c_edid = adv7604_dummy_client(sd, pdata->i2c_edid, 0xfa); 2115 state->i2c_hdmi = adv7604_dummy_client(sd, pdata->i2c_hdmi, 0xfb); 2116 state->i2c_test = adv7604_dummy_client(sd, pdata->i2c_test, 0xfc); 2117 state->i2c_cp = adv7604_dummy_client(sd, pdata->i2c_cp, 0xfd); 2118 state->i2c_vdp = adv7604_dummy_client(sd, pdata->i2c_vdp, 0xfe); 2119 if (!state->i2c_avlink || !state->i2c_cec || !state->i2c_infoframe || 2120 !state->i2c_esdp || !state->i2c_dpp || !state->i2c_afe || 2121 !state->i2c_repeater || !state->i2c_edid || !state->i2c_hdmi || 2122 !state->i2c_test || !state->i2c_cp || !state->i2c_vdp) { 2123 err = -ENOMEM; 2124 v4l2_err(sd, "failed to create all i2c clients\n"); 2125 goto err_i2c; 2126 } 2127 2128 /* work queues */ 2129 state->work_queues = create_singlethread_workqueue(client->name); 2130 if (!state->work_queues) { 2131 v4l2_err(sd, "Could not create work queue\n"); 2132 err = -ENOMEM; 2133 goto err_i2c; 2134 } 2135 2136 INIT_DELAYED_WORK(&state->delayed_work_enable_hotplug, 2137 adv7604_delayed_work_enable_hotplug); 2138 2139 state->pad.flags = MEDIA_PAD_FL_SOURCE; 2140 err = media_entity_init(&sd->entity, 1, &state->pad, 0); 2141 if (err) 2142 goto err_work_queues; 2143 2144 err = adv7604_core_init(sd); 2145 if (err) 2146 goto err_entity; 2147 v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name, 2148 client->addr << 1, client->adapter->name); 2149 return 0; 2150 2151 err_entity: 2152 media_entity_cleanup(&sd->entity); 2153 err_work_queues: 2154 cancel_delayed_work(&state->delayed_work_enable_hotplug); 2155 destroy_workqueue(state->work_queues); 2156 err_i2c: 2157 adv7604_unregister_clients(state); 2158 err_hdl: 2159 v4l2_ctrl_handler_free(hdl); 2160 return err; 2161 } 2162 2163 /* ----------------------------------------------------------------------- */ 2164 2165 static int adv7604_remove(struct i2c_client *client) 2166 { 2167 struct v4l2_subdev *sd = i2c_get_clientdata(client); 2168 struct adv7604_state *state = to_state(sd); 2169 2170 cancel_delayed_work(&state->delayed_work_enable_hotplug); 2171 destroy_workqueue(state->work_queues); 2172 v4l2_device_unregister_subdev(sd); 2173 media_entity_cleanup(&sd->entity); 2174 adv7604_unregister_clients(to_state(sd)); 2175 v4l2_ctrl_handler_free(sd->ctrl_handler); 2176 return 0; 2177 } 2178 2179 /* ----------------------------------------------------------------------- */ 2180 2181 static struct i2c_device_id adv7604_id[] = { 2182 { "adv7604", 0 }, 2183 { } 2184 }; 2185 MODULE_DEVICE_TABLE(i2c, adv7604_id); 2186 2187 static struct i2c_driver adv7604_driver = { 2188 .driver = { 2189 .owner = THIS_MODULE, 2190 .name = "adv7604", 2191 }, 2192 .probe = adv7604_probe, 2193 .remove = adv7604_remove, 2194 .id_table = adv7604_id, 2195 }; 2196 2197 module_i2c_driver(adv7604_driver); 2198