154450f59SHans Verkuil /* 254450f59SHans Verkuil * adv7604 - Analog Devices ADV7604 video decoder driver 354450f59SHans Verkuil * 454450f59SHans Verkuil * Copyright 2012 Cisco Systems, Inc. and/or its affiliates. All rights reserved. 554450f59SHans Verkuil * 654450f59SHans Verkuil * This program is free software; you may redistribute it and/or modify 754450f59SHans Verkuil * it under the terms of the GNU General Public License as published by 854450f59SHans Verkuil * the Free Software Foundation; version 2 of the License. 954450f59SHans Verkuil * 1054450f59SHans Verkuil * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 1154450f59SHans Verkuil * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 1254450f59SHans Verkuil * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 1354450f59SHans Verkuil * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 1454450f59SHans Verkuil * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 1554450f59SHans Verkuil * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 1654450f59SHans Verkuil * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 1754450f59SHans Verkuil * SOFTWARE. 1854450f59SHans Verkuil * 1954450f59SHans Verkuil */ 2054450f59SHans Verkuil 2154450f59SHans Verkuil /* 2254450f59SHans Verkuil * References (c = chapter, p = page): 2354450f59SHans Verkuil * REF_01 - Analog devices, ADV7604, Register Settings Recommendations, 2454450f59SHans Verkuil * Revision 2.5, June 2010 2554450f59SHans Verkuil * REF_02 - Analog devices, Register map documentation, Documentation of 2654450f59SHans Verkuil * the register maps, Software manual, Rev. F, June 2010 2754450f59SHans Verkuil * REF_03 - Analog devices, ADV7604, Hardware Manual, Rev. F, August 2010 2854450f59SHans Verkuil */ 2954450f59SHans Verkuil 30c72a53ceSLaurent Pinchart #include <linux/delay.h> 31e9d50e9eSLaurent Pinchart #include <linux/gpio/consumer.h> 32c72a53ceSLaurent Pinchart #include <linux/i2c.h> 3354450f59SHans Verkuil #include <linux/kernel.h> 3454450f59SHans Verkuil #include <linux/module.h> 3554450f59SHans Verkuil #include <linux/slab.h> 36c72a53ceSLaurent Pinchart #include <linux/v4l2-dv-timings.h> 3754450f59SHans Verkuil #include <linux/videodev2.h> 3854450f59SHans Verkuil #include <linux/workqueue.h> 39c72a53ceSLaurent Pinchart 4054450f59SHans Verkuil #include <media/adv7604.h> 41c72a53ceSLaurent Pinchart #include <media/v4l2-ctrls.h> 42c72a53ceSLaurent Pinchart #include <media/v4l2-device.h> 43c72a53ceSLaurent Pinchart #include <media/v4l2-dv-timings.h> 4454450f59SHans Verkuil 4554450f59SHans Verkuil static int debug; 4654450f59SHans Verkuil module_param(debug, int, 0644); 4754450f59SHans Verkuil MODULE_PARM_DESC(debug, "debug level (0-2)"); 4854450f59SHans Verkuil 4954450f59SHans Verkuil MODULE_DESCRIPTION("Analog Devices ADV7604 video decoder driver"); 5054450f59SHans Verkuil MODULE_AUTHOR("Hans Verkuil <hans.verkuil@cisco.com>"); 5154450f59SHans Verkuil MODULE_AUTHOR("Mats Randgaard <mats.randgaard@cisco.com>"); 5254450f59SHans Verkuil MODULE_LICENSE("GPL"); 5354450f59SHans Verkuil 5454450f59SHans Verkuil /* ADV7604 system clock frequency */ 5554450f59SHans Verkuil #define ADV7604_fsc (28636360) 5654450f59SHans Verkuil 57539b33b0SLaurent Pinchart #define ADV7604_RGB_OUT (1 << 1) 58539b33b0SLaurent Pinchart 59539b33b0SLaurent Pinchart #define ADV7604_OP_FORMAT_SEL_8BIT (0 << 0) 60539b33b0SLaurent Pinchart #define ADV7604_OP_FORMAT_SEL_10BIT (1 << 0) 61539b33b0SLaurent Pinchart #define ADV7604_OP_FORMAT_SEL_12BIT (2 << 0) 62539b33b0SLaurent Pinchart 63539b33b0SLaurent Pinchart #define ADV7604_OP_MODE_SEL_SDR_422 (0 << 5) 64539b33b0SLaurent Pinchart #define ADV7604_OP_MODE_SEL_DDR_422 (1 << 5) 65539b33b0SLaurent Pinchart #define ADV7604_OP_MODE_SEL_SDR_444 (2 << 5) 66539b33b0SLaurent Pinchart #define ADV7604_OP_MODE_SEL_DDR_444 (3 << 5) 67539b33b0SLaurent Pinchart #define ADV7604_OP_MODE_SEL_SDR_422_2X (4 << 5) 68539b33b0SLaurent Pinchart #define ADV7604_OP_MODE_SEL_ADI_CM (5 << 5) 69539b33b0SLaurent Pinchart 70539b33b0SLaurent Pinchart #define ADV7604_OP_CH_SEL_GBR (0 << 5) 71539b33b0SLaurent Pinchart #define ADV7604_OP_CH_SEL_GRB (1 << 5) 72539b33b0SLaurent Pinchart #define ADV7604_OP_CH_SEL_BGR (2 << 5) 73539b33b0SLaurent Pinchart #define ADV7604_OP_CH_SEL_RGB (3 << 5) 74539b33b0SLaurent Pinchart #define ADV7604_OP_CH_SEL_BRG (4 << 5) 75539b33b0SLaurent Pinchart #define ADV7604_OP_CH_SEL_RBG (5 << 5) 76539b33b0SLaurent Pinchart 77539b33b0SLaurent Pinchart #define ADV7604_OP_SWAP_CB_CR (1 << 0) 78539b33b0SLaurent Pinchart 79d42010a1SLars-Peter Clausen enum adv7604_type { 80d42010a1SLars-Peter Clausen ADV7604, 81d42010a1SLars-Peter Clausen ADV7611, 82d42010a1SLars-Peter Clausen }; 83d42010a1SLars-Peter Clausen 84d42010a1SLars-Peter Clausen struct adv7604_reg_seq { 85d42010a1SLars-Peter Clausen unsigned int reg; 86d42010a1SLars-Peter Clausen u8 val; 87d42010a1SLars-Peter Clausen }; 88d42010a1SLars-Peter Clausen 89539b33b0SLaurent Pinchart struct adv7604_format_info { 90539b33b0SLaurent Pinchart enum v4l2_mbus_pixelcode code; 91539b33b0SLaurent Pinchart u8 op_ch_sel; 92539b33b0SLaurent Pinchart bool rgb_out; 93539b33b0SLaurent Pinchart bool swap_cb_cr; 94539b33b0SLaurent Pinchart u8 op_format_sel; 95539b33b0SLaurent Pinchart }; 96539b33b0SLaurent Pinchart 97d42010a1SLars-Peter Clausen struct adv7604_chip_info { 98d42010a1SLars-Peter Clausen enum adv7604_type type; 99d42010a1SLars-Peter Clausen 100d42010a1SLars-Peter Clausen bool has_afe; 101d42010a1SLars-Peter Clausen unsigned int max_port; 102d42010a1SLars-Peter Clausen unsigned int num_dv_ports; 103d42010a1SLars-Peter Clausen 104d42010a1SLars-Peter Clausen unsigned int edid_enable_reg; 105d42010a1SLars-Peter Clausen unsigned int edid_status_reg; 106d42010a1SLars-Peter Clausen unsigned int lcf_reg; 107d42010a1SLars-Peter Clausen 108d42010a1SLars-Peter Clausen unsigned int cable_det_mask; 109d42010a1SLars-Peter Clausen unsigned int tdms_lock_mask; 110d42010a1SLars-Peter Clausen unsigned int fmt_change_digital_mask; 111d42010a1SLars-Peter Clausen 112539b33b0SLaurent Pinchart const struct adv7604_format_info *formats; 113539b33b0SLaurent Pinchart unsigned int nformats; 114539b33b0SLaurent Pinchart 115d42010a1SLars-Peter Clausen void (*set_termination)(struct v4l2_subdev *sd, bool enable); 116d42010a1SLars-Peter Clausen void (*setup_irqs)(struct v4l2_subdev *sd); 117d42010a1SLars-Peter Clausen unsigned int (*read_hdmi_pixelclock)(struct v4l2_subdev *sd); 118d42010a1SLars-Peter Clausen unsigned int (*read_cable_det)(struct v4l2_subdev *sd); 119d42010a1SLars-Peter Clausen 120d42010a1SLars-Peter Clausen /* 0 = AFE, 1 = HDMI */ 121d42010a1SLars-Peter Clausen const struct adv7604_reg_seq *recommended_settings[2]; 122d42010a1SLars-Peter Clausen unsigned int num_recommended_settings[2]; 123d42010a1SLars-Peter Clausen 124d42010a1SLars-Peter Clausen unsigned long page_mask; 125d42010a1SLars-Peter Clausen }; 126d42010a1SLars-Peter Clausen 12754450f59SHans Verkuil /* 12854450f59SHans Verkuil ********************************************************************** 12954450f59SHans Verkuil * 13054450f59SHans Verkuil * Arrays with configuration parameters for the ADV7604 13154450f59SHans Verkuil * 13254450f59SHans Verkuil ********************************************************************** 13354450f59SHans Verkuil */ 134c784b1e2SLaurent Pinchart 13554450f59SHans Verkuil struct adv7604_state { 136d42010a1SLars-Peter Clausen const struct adv7604_chip_info *info; 13754450f59SHans Verkuil struct adv7604_platform_data pdata; 138539b33b0SLaurent Pinchart 139e9d50e9eSLaurent Pinchart struct gpio_desc *hpd_gpio[4]; 140e9d50e9eSLaurent Pinchart 14154450f59SHans Verkuil struct v4l2_subdev sd; 142c784b1e2SLaurent Pinchart struct media_pad pads[ADV7604_PAD_MAX]; 143c784b1e2SLaurent Pinchart unsigned int source_pad; 144539b33b0SLaurent Pinchart 14554450f59SHans Verkuil struct v4l2_ctrl_handler hdl; 146539b33b0SLaurent Pinchart 147c784b1e2SLaurent Pinchart enum adv7604_pad selected_input; 148539b33b0SLaurent Pinchart 14954450f59SHans Verkuil struct v4l2_dv_timings timings; 150539b33b0SLaurent Pinchart const struct adv7604_format_info *format; 151539b33b0SLaurent Pinchart 1524a31a93aSMats Randgaard struct { 15354450f59SHans Verkuil u8 edid[256]; 1544a31a93aSMats Randgaard u32 present; 1554a31a93aSMats Randgaard unsigned blocks; 1564a31a93aSMats Randgaard } edid; 157dd08beb9SMats Randgaard u16 spa_port_a[2]; 15854450f59SHans Verkuil struct v4l2_fract aspect_ratio; 15954450f59SHans Verkuil u32 rgb_quantization_range; 16054450f59SHans Verkuil struct workqueue_struct *work_queues; 16154450f59SHans Verkuil struct delayed_work delayed_work_enable_hotplug; 162cf9afb1dSHans Verkuil bool restart_stdi_once; 16354450f59SHans Verkuil 16454450f59SHans Verkuil /* i2c clients */ 16505cacb17SLaurent Pinchart struct i2c_client *i2c_clients[ADV7604_PAGE_MAX]; 16654450f59SHans Verkuil 16754450f59SHans Verkuil /* controls */ 16854450f59SHans Verkuil struct v4l2_ctrl *detect_tx_5v_ctrl; 16954450f59SHans Verkuil struct v4l2_ctrl *analog_sampling_phase_ctrl; 17054450f59SHans Verkuil struct v4l2_ctrl *free_run_color_manual_ctrl; 17154450f59SHans Verkuil struct v4l2_ctrl *free_run_color_ctrl; 17254450f59SHans Verkuil struct v4l2_ctrl *rgb_quantization_range_ctrl; 17354450f59SHans Verkuil }; 17454450f59SHans Verkuil 175d42010a1SLars-Peter Clausen static bool adv7604_has_afe(struct adv7604_state *state) 176d42010a1SLars-Peter Clausen { 177d42010a1SLars-Peter Clausen return state->info->has_afe; 178d42010a1SLars-Peter Clausen } 179d42010a1SLars-Peter Clausen 18054450f59SHans Verkuil /* Supported CEA and DMT timings */ 18154450f59SHans Verkuil static const struct v4l2_dv_timings adv7604_timings[] = { 18254450f59SHans Verkuil V4L2_DV_BT_CEA_720X480P59_94, 18354450f59SHans Verkuil V4L2_DV_BT_CEA_720X576P50, 18454450f59SHans Verkuil V4L2_DV_BT_CEA_1280X720P24, 18554450f59SHans Verkuil V4L2_DV_BT_CEA_1280X720P25, 18654450f59SHans Verkuil V4L2_DV_BT_CEA_1280X720P50, 18754450f59SHans Verkuil V4L2_DV_BT_CEA_1280X720P60, 18854450f59SHans Verkuil V4L2_DV_BT_CEA_1920X1080P24, 18954450f59SHans Verkuil V4L2_DV_BT_CEA_1920X1080P25, 19054450f59SHans Verkuil V4L2_DV_BT_CEA_1920X1080P30, 19154450f59SHans Verkuil V4L2_DV_BT_CEA_1920X1080P50, 19254450f59SHans Verkuil V4L2_DV_BT_CEA_1920X1080P60, 19354450f59SHans Verkuil 194ccbd5bc4SHans Verkuil /* sorted by DMT ID */ 19554450f59SHans Verkuil V4L2_DV_BT_DMT_640X350P85, 19654450f59SHans Verkuil V4L2_DV_BT_DMT_640X400P85, 19754450f59SHans Verkuil V4L2_DV_BT_DMT_720X400P85, 19854450f59SHans Verkuil V4L2_DV_BT_DMT_640X480P60, 19954450f59SHans Verkuil V4L2_DV_BT_DMT_640X480P72, 20054450f59SHans Verkuil V4L2_DV_BT_DMT_640X480P75, 20154450f59SHans Verkuil V4L2_DV_BT_DMT_640X480P85, 20254450f59SHans Verkuil V4L2_DV_BT_DMT_800X600P56, 20354450f59SHans Verkuil V4L2_DV_BT_DMT_800X600P60, 20454450f59SHans Verkuil V4L2_DV_BT_DMT_800X600P72, 20554450f59SHans Verkuil V4L2_DV_BT_DMT_800X600P75, 20654450f59SHans Verkuil V4L2_DV_BT_DMT_800X600P85, 20754450f59SHans Verkuil V4L2_DV_BT_DMT_848X480P60, 20854450f59SHans Verkuil V4L2_DV_BT_DMT_1024X768P60, 20954450f59SHans Verkuil V4L2_DV_BT_DMT_1024X768P70, 21054450f59SHans Verkuil V4L2_DV_BT_DMT_1024X768P75, 21154450f59SHans Verkuil V4L2_DV_BT_DMT_1024X768P85, 21254450f59SHans Verkuil V4L2_DV_BT_DMT_1152X864P75, 21354450f59SHans Verkuil V4L2_DV_BT_DMT_1280X768P60_RB, 21454450f59SHans Verkuil V4L2_DV_BT_DMT_1280X768P60, 21554450f59SHans Verkuil V4L2_DV_BT_DMT_1280X768P75, 21654450f59SHans Verkuil V4L2_DV_BT_DMT_1280X768P85, 21754450f59SHans Verkuil V4L2_DV_BT_DMT_1280X800P60_RB, 21854450f59SHans Verkuil V4L2_DV_BT_DMT_1280X800P60, 21954450f59SHans Verkuil V4L2_DV_BT_DMT_1280X800P75, 22054450f59SHans Verkuil V4L2_DV_BT_DMT_1280X800P85, 22154450f59SHans Verkuil V4L2_DV_BT_DMT_1280X960P60, 22254450f59SHans Verkuil V4L2_DV_BT_DMT_1280X960P85, 22354450f59SHans Verkuil V4L2_DV_BT_DMT_1280X1024P60, 22454450f59SHans Verkuil V4L2_DV_BT_DMT_1280X1024P75, 22554450f59SHans Verkuil V4L2_DV_BT_DMT_1280X1024P85, 22654450f59SHans Verkuil V4L2_DV_BT_DMT_1360X768P60, 22754450f59SHans Verkuil V4L2_DV_BT_DMT_1400X1050P60_RB, 22854450f59SHans Verkuil V4L2_DV_BT_DMT_1400X1050P60, 22954450f59SHans Verkuil V4L2_DV_BT_DMT_1400X1050P75, 23054450f59SHans Verkuil V4L2_DV_BT_DMT_1400X1050P85, 23154450f59SHans Verkuil V4L2_DV_BT_DMT_1440X900P60_RB, 23254450f59SHans Verkuil V4L2_DV_BT_DMT_1440X900P60, 23354450f59SHans Verkuil V4L2_DV_BT_DMT_1600X1200P60, 23454450f59SHans Verkuil V4L2_DV_BT_DMT_1680X1050P60_RB, 23554450f59SHans Verkuil V4L2_DV_BT_DMT_1680X1050P60, 23654450f59SHans Verkuil V4L2_DV_BT_DMT_1792X1344P60, 23754450f59SHans Verkuil V4L2_DV_BT_DMT_1856X1392P60, 23854450f59SHans Verkuil V4L2_DV_BT_DMT_1920X1200P60_RB, 239547ed542SMartin Bugge V4L2_DV_BT_DMT_1366X768P60_RB, 24054450f59SHans Verkuil V4L2_DV_BT_DMT_1366X768P60, 24154450f59SHans Verkuil V4L2_DV_BT_DMT_1920X1080P60, 24254450f59SHans Verkuil { }, 24354450f59SHans Verkuil }; 24454450f59SHans Verkuil 245ccbd5bc4SHans Verkuil struct adv7604_video_standards { 246ccbd5bc4SHans Verkuil struct v4l2_dv_timings timings; 247ccbd5bc4SHans Verkuil u8 vid_std; 248ccbd5bc4SHans Verkuil u8 v_freq; 249ccbd5bc4SHans Verkuil }; 250ccbd5bc4SHans Verkuil 251ccbd5bc4SHans Verkuil /* sorted by number of lines */ 252ccbd5bc4SHans Verkuil static const struct adv7604_video_standards adv7604_prim_mode_comp[] = { 253ccbd5bc4SHans Verkuil /* { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 }, TODO flickering */ 254ccbd5bc4SHans Verkuil { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 }, 255ccbd5bc4SHans Verkuil { V4L2_DV_BT_CEA_1280X720P50, 0x19, 0x01 }, 256ccbd5bc4SHans Verkuil { V4L2_DV_BT_CEA_1280X720P60, 0x19, 0x00 }, 257ccbd5bc4SHans Verkuil { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 }, 258ccbd5bc4SHans Verkuil { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 }, 259ccbd5bc4SHans Verkuil { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 }, 260ccbd5bc4SHans Verkuil { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 }, 261ccbd5bc4SHans Verkuil { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 }, 262ccbd5bc4SHans Verkuil /* TODO add 1920x1080P60_RB (CVT timing) */ 263ccbd5bc4SHans Verkuil { }, 264ccbd5bc4SHans Verkuil }; 265ccbd5bc4SHans Verkuil 266ccbd5bc4SHans Verkuil /* sorted by number of lines */ 267ccbd5bc4SHans Verkuil static const struct adv7604_video_standards adv7604_prim_mode_gr[] = { 268ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 }, 269ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 }, 270ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 }, 271ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 }, 272ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 }, 273ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 }, 274ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 }, 275ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 }, 276ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 }, 277ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 }, 278ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 }, 279ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 }, 280ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 }, 281ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 }, 282ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 }, 283ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_1360X768P60, 0x12, 0x00 }, 284ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_1366X768P60, 0x13, 0x00 }, 285ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_1400X1050P60, 0x14, 0x00 }, 286ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_1400X1050P75, 0x15, 0x00 }, 287ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_1600X1200P60, 0x16, 0x00 }, /* TODO not tested */ 288ccbd5bc4SHans Verkuil /* TODO add 1600X1200P60_RB (not a DMT timing) */ 289ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_1680X1050P60, 0x18, 0x00 }, 290ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_1920X1200P60_RB, 0x19, 0x00 }, /* TODO not tested */ 291ccbd5bc4SHans Verkuil { }, 292ccbd5bc4SHans Verkuil }; 293ccbd5bc4SHans Verkuil 294ccbd5bc4SHans Verkuil /* sorted by number of lines */ 295ccbd5bc4SHans Verkuil static const struct adv7604_video_standards adv7604_prim_mode_hdmi_comp[] = { 296ccbd5bc4SHans Verkuil { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 }, 297ccbd5bc4SHans Verkuil { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 }, 298ccbd5bc4SHans Verkuil { V4L2_DV_BT_CEA_1280X720P50, 0x13, 0x01 }, 299ccbd5bc4SHans Verkuil { V4L2_DV_BT_CEA_1280X720P60, 0x13, 0x00 }, 300ccbd5bc4SHans Verkuil { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 }, 301ccbd5bc4SHans Verkuil { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 }, 302ccbd5bc4SHans Verkuil { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 }, 303ccbd5bc4SHans Verkuil { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 }, 304ccbd5bc4SHans Verkuil { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 }, 305ccbd5bc4SHans Verkuil { }, 306ccbd5bc4SHans Verkuil }; 307ccbd5bc4SHans Verkuil 308ccbd5bc4SHans Verkuil /* sorted by number of lines */ 309ccbd5bc4SHans Verkuil static const struct adv7604_video_standards adv7604_prim_mode_hdmi_gr[] = { 310ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 }, 311ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 }, 312ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 }, 313ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 }, 314ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 }, 315ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 }, 316ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 }, 317ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 }, 318ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 }, 319ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 }, 320ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 }, 321ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 }, 322ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 }, 323ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 }, 324ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 }, 325ccbd5bc4SHans Verkuil { }, 326ccbd5bc4SHans Verkuil }; 327ccbd5bc4SHans Verkuil 32854450f59SHans Verkuil /* ----------------------------------------------------------------------- */ 32954450f59SHans Verkuil 33054450f59SHans Verkuil static inline struct adv7604_state *to_state(struct v4l2_subdev *sd) 33154450f59SHans Verkuil { 33254450f59SHans Verkuil return container_of(sd, struct adv7604_state, sd); 33354450f59SHans Verkuil } 33454450f59SHans Verkuil 33554450f59SHans Verkuil static inline unsigned hblanking(const struct v4l2_bt_timings *t) 33654450f59SHans Verkuil { 337eacf8f9aSHans Verkuil return V4L2_DV_BT_BLANKING_WIDTH(t); 33854450f59SHans Verkuil } 33954450f59SHans Verkuil 34054450f59SHans Verkuil static inline unsigned htotal(const struct v4l2_bt_timings *t) 34154450f59SHans Verkuil { 342eacf8f9aSHans Verkuil return V4L2_DV_BT_FRAME_WIDTH(t); 34354450f59SHans Verkuil } 34454450f59SHans Verkuil 34554450f59SHans Verkuil static inline unsigned vblanking(const struct v4l2_bt_timings *t) 34654450f59SHans Verkuil { 347eacf8f9aSHans Verkuil return V4L2_DV_BT_BLANKING_HEIGHT(t); 34854450f59SHans Verkuil } 34954450f59SHans Verkuil 35054450f59SHans Verkuil static inline unsigned vtotal(const struct v4l2_bt_timings *t) 35154450f59SHans Verkuil { 352eacf8f9aSHans Verkuil return V4L2_DV_BT_FRAME_HEIGHT(t); 35354450f59SHans Verkuil } 35454450f59SHans Verkuil 35554450f59SHans Verkuil /* ----------------------------------------------------------------------- */ 35654450f59SHans Verkuil 35754450f59SHans Verkuil static s32 adv_smbus_read_byte_data_check(struct i2c_client *client, 35854450f59SHans Verkuil u8 command, bool check) 35954450f59SHans Verkuil { 36054450f59SHans Verkuil union i2c_smbus_data data; 36154450f59SHans Verkuil 36254450f59SHans Verkuil if (!i2c_smbus_xfer(client->adapter, client->addr, client->flags, 36354450f59SHans Verkuil I2C_SMBUS_READ, command, 36454450f59SHans Verkuil I2C_SMBUS_BYTE_DATA, &data)) 36554450f59SHans Verkuil return data.byte; 36654450f59SHans Verkuil if (check) 36754450f59SHans Verkuil v4l_err(client, "error reading %02x, %02x\n", 36854450f59SHans Verkuil client->addr, command); 36954450f59SHans Verkuil return -EIO; 37054450f59SHans Verkuil } 37154450f59SHans Verkuil 37205cacb17SLaurent Pinchart static s32 adv_smbus_read_byte_data(struct adv7604_state *state, 37305cacb17SLaurent Pinchart enum adv7604_page page, u8 command) 37454450f59SHans Verkuil { 37505cacb17SLaurent Pinchart return adv_smbus_read_byte_data_check(state->i2c_clients[page], 37605cacb17SLaurent Pinchart command, true); 37754450f59SHans Verkuil } 37854450f59SHans Verkuil 37905cacb17SLaurent Pinchart static s32 adv_smbus_write_byte_data(struct adv7604_state *state, 38005cacb17SLaurent Pinchart enum adv7604_page page, u8 command, 38105cacb17SLaurent Pinchart u8 value) 38254450f59SHans Verkuil { 38305cacb17SLaurent Pinchart struct i2c_client *client = state->i2c_clients[page]; 38454450f59SHans Verkuil union i2c_smbus_data data; 38554450f59SHans Verkuil int err; 38654450f59SHans Verkuil int i; 38754450f59SHans Verkuil 38854450f59SHans Verkuil data.byte = value; 38954450f59SHans Verkuil for (i = 0; i < 3; i++) { 39054450f59SHans Verkuil err = i2c_smbus_xfer(client->adapter, client->addr, 39154450f59SHans Verkuil client->flags, 39254450f59SHans Verkuil I2C_SMBUS_WRITE, command, 39354450f59SHans Verkuil I2C_SMBUS_BYTE_DATA, &data); 39454450f59SHans Verkuil if (!err) 39554450f59SHans Verkuil break; 39654450f59SHans Verkuil } 39754450f59SHans Verkuil if (err < 0) 39854450f59SHans Verkuil v4l_err(client, "error writing %02x, %02x, %02x\n", 39954450f59SHans Verkuil client->addr, command, value); 40054450f59SHans Verkuil return err; 40154450f59SHans Verkuil } 40254450f59SHans Verkuil 40305cacb17SLaurent Pinchart static s32 adv_smbus_write_i2c_block_data(struct adv7604_state *state, 40405cacb17SLaurent Pinchart enum adv7604_page page, u8 command, 40505cacb17SLaurent Pinchart unsigned length, const u8 *values) 40654450f59SHans Verkuil { 40705cacb17SLaurent Pinchart struct i2c_client *client = state->i2c_clients[page]; 40854450f59SHans Verkuil union i2c_smbus_data data; 40954450f59SHans Verkuil 41054450f59SHans Verkuil if (length > I2C_SMBUS_BLOCK_MAX) 41154450f59SHans Verkuil length = I2C_SMBUS_BLOCK_MAX; 41254450f59SHans Verkuil data.block[0] = length; 41354450f59SHans Verkuil memcpy(data.block + 1, values, length); 41454450f59SHans Verkuil return i2c_smbus_xfer(client->adapter, client->addr, client->flags, 41554450f59SHans Verkuil I2C_SMBUS_WRITE, command, 41654450f59SHans Verkuil I2C_SMBUS_I2C_BLOCK_DATA, &data); 41754450f59SHans Verkuil } 41854450f59SHans Verkuil 41954450f59SHans Verkuil /* ----------------------------------------------------------------------- */ 42054450f59SHans Verkuil 42154450f59SHans Verkuil static inline int io_read(struct v4l2_subdev *sd, u8 reg) 42254450f59SHans Verkuil { 42305cacb17SLaurent Pinchart struct adv7604_state *state = to_state(sd); 42454450f59SHans Verkuil 42505cacb17SLaurent Pinchart return adv_smbus_read_byte_data(state, ADV7604_PAGE_IO, reg); 42654450f59SHans Verkuil } 42754450f59SHans Verkuil 42854450f59SHans Verkuil static inline int io_write(struct v4l2_subdev *sd, u8 reg, u8 val) 42954450f59SHans Verkuil { 43005cacb17SLaurent Pinchart struct adv7604_state *state = to_state(sd); 43154450f59SHans Verkuil 43205cacb17SLaurent Pinchart return adv_smbus_write_byte_data(state, ADV7604_PAGE_IO, reg, val); 43354450f59SHans Verkuil } 43454450f59SHans Verkuil 43522d97e56SLaurent Pinchart static inline int io_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) 43654450f59SHans Verkuil { 43722d97e56SLaurent Pinchart return io_write(sd, reg, (io_read(sd, reg) & ~mask) | val); 43854450f59SHans Verkuil } 43954450f59SHans Verkuil 44054450f59SHans Verkuil static inline int avlink_read(struct v4l2_subdev *sd, u8 reg) 44154450f59SHans Verkuil { 44254450f59SHans Verkuil struct adv7604_state *state = to_state(sd); 44354450f59SHans Verkuil 44405cacb17SLaurent Pinchart return adv_smbus_read_byte_data(state, ADV7604_PAGE_AVLINK, reg); 44554450f59SHans Verkuil } 44654450f59SHans Verkuil 44754450f59SHans Verkuil static inline int avlink_write(struct v4l2_subdev *sd, u8 reg, u8 val) 44854450f59SHans Verkuil { 44954450f59SHans Verkuil struct adv7604_state *state = to_state(sd); 45054450f59SHans Verkuil 45105cacb17SLaurent Pinchart return adv_smbus_write_byte_data(state, ADV7604_PAGE_AVLINK, reg, val); 45254450f59SHans Verkuil } 45354450f59SHans Verkuil 45454450f59SHans Verkuil static inline int cec_read(struct v4l2_subdev *sd, u8 reg) 45554450f59SHans Verkuil { 45654450f59SHans Verkuil struct adv7604_state *state = to_state(sd); 45754450f59SHans Verkuil 45805cacb17SLaurent Pinchart return adv_smbus_read_byte_data(state, ADV7604_PAGE_CEC, reg); 45954450f59SHans Verkuil } 46054450f59SHans Verkuil 46154450f59SHans Verkuil static inline int cec_write(struct v4l2_subdev *sd, u8 reg, u8 val) 46254450f59SHans Verkuil { 46354450f59SHans Verkuil struct adv7604_state *state = to_state(sd); 46454450f59SHans Verkuil 46505cacb17SLaurent Pinchart return adv_smbus_write_byte_data(state, ADV7604_PAGE_CEC, reg, val); 46654450f59SHans Verkuil } 46754450f59SHans Verkuil 46822d97e56SLaurent Pinchart static inline int cec_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) 46954450f59SHans Verkuil { 47022d97e56SLaurent Pinchart return cec_write(sd, reg, (cec_read(sd, reg) & ~mask) | val); 47154450f59SHans Verkuil } 47254450f59SHans Verkuil 47354450f59SHans Verkuil static inline int infoframe_read(struct v4l2_subdev *sd, u8 reg) 47454450f59SHans Verkuil { 47554450f59SHans Verkuil struct adv7604_state *state = to_state(sd); 47654450f59SHans Verkuil 47705cacb17SLaurent Pinchart return adv_smbus_read_byte_data(state, ADV7604_PAGE_INFOFRAME, reg); 47854450f59SHans Verkuil } 47954450f59SHans Verkuil 48054450f59SHans Verkuil static inline int infoframe_write(struct v4l2_subdev *sd, u8 reg, u8 val) 48154450f59SHans Verkuil { 48254450f59SHans Verkuil struct adv7604_state *state = to_state(sd); 48354450f59SHans Verkuil 48405cacb17SLaurent Pinchart return adv_smbus_write_byte_data(state, ADV7604_PAGE_INFOFRAME, 48505cacb17SLaurent Pinchart reg, val); 48654450f59SHans Verkuil } 48754450f59SHans Verkuil 48854450f59SHans Verkuil static inline int esdp_read(struct v4l2_subdev *sd, u8 reg) 48954450f59SHans Verkuil { 49054450f59SHans Verkuil struct adv7604_state *state = to_state(sd); 49154450f59SHans Verkuil 49205cacb17SLaurent Pinchart return adv_smbus_read_byte_data(state, ADV7604_PAGE_ESDP, reg); 49354450f59SHans Verkuil } 49454450f59SHans Verkuil 49554450f59SHans Verkuil static inline int esdp_write(struct v4l2_subdev *sd, u8 reg, u8 val) 49654450f59SHans Verkuil { 49754450f59SHans Verkuil struct adv7604_state *state = to_state(sd); 49854450f59SHans Verkuil 49905cacb17SLaurent Pinchart return adv_smbus_write_byte_data(state, ADV7604_PAGE_ESDP, reg, val); 50054450f59SHans Verkuil } 50154450f59SHans Verkuil 50254450f59SHans Verkuil static inline int dpp_read(struct v4l2_subdev *sd, u8 reg) 50354450f59SHans Verkuil { 50454450f59SHans Verkuil struct adv7604_state *state = to_state(sd); 50554450f59SHans Verkuil 50605cacb17SLaurent Pinchart return adv_smbus_read_byte_data(state, ADV7604_PAGE_DPP, reg); 50754450f59SHans Verkuil } 50854450f59SHans Verkuil 50954450f59SHans Verkuil static inline int dpp_write(struct v4l2_subdev *sd, u8 reg, u8 val) 51054450f59SHans Verkuil { 51154450f59SHans Verkuil struct adv7604_state *state = to_state(sd); 51254450f59SHans Verkuil 51305cacb17SLaurent Pinchart return adv_smbus_write_byte_data(state, ADV7604_PAGE_DPP, reg, val); 51454450f59SHans Verkuil } 51554450f59SHans Verkuil 51654450f59SHans Verkuil static inline int afe_read(struct v4l2_subdev *sd, u8 reg) 51754450f59SHans Verkuil { 51854450f59SHans Verkuil struct adv7604_state *state = to_state(sd); 51954450f59SHans Verkuil 52005cacb17SLaurent Pinchart return adv_smbus_read_byte_data(state, ADV7604_PAGE_AFE, reg); 52154450f59SHans Verkuil } 52254450f59SHans Verkuil 52354450f59SHans Verkuil static inline int afe_write(struct v4l2_subdev *sd, u8 reg, u8 val) 52454450f59SHans Verkuil { 52554450f59SHans Verkuil struct adv7604_state *state = to_state(sd); 52654450f59SHans Verkuil 52705cacb17SLaurent Pinchart return adv_smbus_write_byte_data(state, ADV7604_PAGE_AFE, reg, val); 52854450f59SHans Verkuil } 52954450f59SHans Verkuil 53054450f59SHans Verkuil static inline int rep_read(struct v4l2_subdev *sd, u8 reg) 53154450f59SHans Verkuil { 53254450f59SHans Verkuil struct adv7604_state *state = to_state(sd); 53354450f59SHans Verkuil 53405cacb17SLaurent Pinchart return adv_smbus_read_byte_data(state, ADV7604_PAGE_REP, reg); 53554450f59SHans Verkuil } 53654450f59SHans Verkuil 53754450f59SHans Verkuil static inline int rep_write(struct v4l2_subdev *sd, u8 reg, u8 val) 53854450f59SHans Verkuil { 53954450f59SHans Verkuil struct adv7604_state *state = to_state(sd); 54054450f59SHans Verkuil 54105cacb17SLaurent Pinchart return adv_smbus_write_byte_data(state, ADV7604_PAGE_REP, reg, val); 54254450f59SHans Verkuil } 54354450f59SHans Verkuil 54422d97e56SLaurent Pinchart static inline int rep_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) 54554450f59SHans Verkuil { 54622d97e56SLaurent Pinchart return rep_write(sd, reg, (rep_read(sd, reg) & ~mask) | val); 54754450f59SHans Verkuil } 54854450f59SHans Verkuil 54954450f59SHans Verkuil static inline int edid_read(struct v4l2_subdev *sd, u8 reg) 55054450f59SHans Verkuil { 55154450f59SHans Verkuil struct adv7604_state *state = to_state(sd); 55254450f59SHans Verkuil 55305cacb17SLaurent Pinchart return adv_smbus_read_byte_data(state, ADV7604_PAGE_EDID, reg); 55454450f59SHans Verkuil } 55554450f59SHans Verkuil 55654450f59SHans Verkuil static inline int edid_write(struct v4l2_subdev *sd, u8 reg, u8 val) 55754450f59SHans Verkuil { 55854450f59SHans Verkuil struct adv7604_state *state = to_state(sd); 55954450f59SHans Verkuil 56005cacb17SLaurent Pinchart return adv_smbus_write_byte_data(state, ADV7604_PAGE_EDID, reg, val); 56154450f59SHans Verkuil } 56254450f59SHans Verkuil 56354450f59SHans Verkuil static inline int edid_read_block(struct v4l2_subdev *sd, unsigned len, u8 *val) 56454450f59SHans Verkuil { 56554450f59SHans Verkuil struct adv7604_state *state = to_state(sd); 56605cacb17SLaurent Pinchart struct i2c_client *client = state->i2c_clients[ADV7604_PAGE_EDID]; 56754450f59SHans Verkuil u8 msgbuf0[1] = { 0 }; 56854450f59SHans Verkuil u8 msgbuf1[256]; 56909f29673SShubhrajyoti D struct i2c_msg msg[2] = { 57009f29673SShubhrajyoti D { 57109f29673SShubhrajyoti D .addr = client->addr, 57209f29673SShubhrajyoti D .len = 1, 57309f29673SShubhrajyoti D .buf = msgbuf0 57409f29673SShubhrajyoti D }, 57509f29673SShubhrajyoti D { 57609f29673SShubhrajyoti D .addr = client->addr, 57709f29673SShubhrajyoti D .flags = I2C_M_RD, 57809f29673SShubhrajyoti D .len = len, 57909f29673SShubhrajyoti D .buf = msgbuf1 58009f29673SShubhrajyoti D }, 58154450f59SHans Verkuil }; 58254450f59SHans Verkuil 58354450f59SHans Verkuil if (i2c_transfer(client->adapter, msg, 2) < 0) 58454450f59SHans Verkuil return -EIO; 58554450f59SHans Verkuil memcpy(val, msgbuf1, len); 58654450f59SHans Verkuil return 0; 58754450f59SHans Verkuil } 58854450f59SHans Verkuil 589dd08beb9SMats Randgaard static inline int edid_write_block(struct v4l2_subdev *sd, 590dd08beb9SMats Randgaard unsigned len, const u8 *val) 591dd08beb9SMats Randgaard { 592dd08beb9SMats Randgaard struct adv7604_state *state = to_state(sd); 593dd08beb9SMats Randgaard int err = 0; 594dd08beb9SMats Randgaard int i; 595dd08beb9SMats Randgaard 596dd08beb9SMats Randgaard v4l2_dbg(2, debug, sd, "%s: write EDID block (%d byte)\n", __func__, len); 597dd08beb9SMats Randgaard 598dd08beb9SMats Randgaard for (i = 0; !err && i < len; i += I2C_SMBUS_BLOCK_MAX) 59905cacb17SLaurent Pinchart err = adv_smbus_write_i2c_block_data(state, ADV7604_PAGE_EDID, 60005cacb17SLaurent Pinchart i, I2C_SMBUS_BLOCK_MAX, val + i); 601dd08beb9SMats Randgaard return err; 602dd08beb9SMats Randgaard } 603dd08beb9SMats Randgaard 604e9d50e9eSLaurent Pinchart static void adv7604_set_hpd(struct adv7604_state *state, unsigned int hpd) 605e9d50e9eSLaurent Pinchart { 606e9d50e9eSLaurent Pinchart unsigned int i; 607e9d50e9eSLaurent Pinchart 608e9d50e9eSLaurent Pinchart for (i = 0; i < state->info->num_dv_ports; ++i) { 609e9d50e9eSLaurent Pinchart if (IS_ERR(state->hpd_gpio[i])) 610e9d50e9eSLaurent Pinchart continue; 611e9d50e9eSLaurent Pinchart 612e9d50e9eSLaurent Pinchart gpiod_set_value_cansleep(state->hpd_gpio[i], hpd & BIT(i)); 613e9d50e9eSLaurent Pinchart } 614e9d50e9eSLaurent Pinchart 615e9d50e9eSLaurent Pinchart v4l2_subdev_notify(&state->sd, ADV7604_HOTPLUG, &hpd); 616e9d50e9eSLaurent Pinchart } 617e9d50e9eSLaurent Pinchart 61854450f59SHans Verkuil static void adv7604_delayed_work_enable_hotplug(struct work_struct *work) 61954450f59SHans Verkuil { 62054450f59SHans Verkuil struct delayed_work *dwork = to_delayed_work(work); 62154450f59SHans Verkuil struct adv7604_state *state = container_of(dwork, struct adv7604_state, 62254450f59SHans Verkuil delayed_work_enable_hotplug); 62354450f59SHans Verkuil struct v4l2_subdev *sd = &state->sd; 62454450f59SHans Verkuil 62554450f59SHans Verkuil v4l2_dbg(2, debug, sd, "%s: enable hotplug\n", __func__); 62654450f59SHans Verkuil 627e9d50e9eSLaurent Pinchart adv7604_set_hpd(state, state->edid.present); 62854450f59SHans Verkuil } 62954450f59SHans Verkuil 63054450f59SHans Verkuil static inline int hdmi_read(struct v4l2_subdev *sd, u8 reg) 63154450f59SHans Verkuil { 63254450f59SHans Verkuil struct adv7604_state *state = to_state(sd); 63354450f59SHans Verkuil 63405cacb17SLaurent Pinchart return adv_smbus_read_byte_data(state, ADV7604_PAGE_HDMI, reg); 63554450f59SHans Verkuil } 63654450f59SHans Verkuil 63751182a94SLaurent Pinchart static u16 hdmi_read16(struct v4l2_subdev *sd, u8 reg, u16 mask) 63851182a94SLaurent Pinchart { 63951182a94SLaurent Pinchart return ((hdmi_read(sd, reg) << 8) | hdmi_read(sd, reg + 1)) & mask; 64051182a94SLaurent Pinchart } 64151182a94SLaurent Pinchart 64254450f59SHans Verkuil static inline int hdmi_write(struct v4l2_subdev *sd, u8 reg, u8 val) 64354450f59SHans Verkuil { 64454450f59SHans Verkuil struct adv7604_state *state = to_state(sd); 64554450f59SHans Verkuil 64605cacb17SLaurent Pinchart return adv_smbus_write_byte_data(state, ADV7604_PAGE_HDMI, reg, val); 64754450f59SHans Verkuil } 64854450f59SHans Verkuil 64922d97e56SLaurent Pinchart static inline int hdmi_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) 6504a31a93aSMats Randgaard { 65122d97e56SLaurent Pinchart return hdmi_write(sd, reg, (hdmi_read(sd, reg) & ~mask) | val); 6524a31a93aSMats Randgaard } 6534a31a93aSMats Randgaard 65454450f59SHans Verkuil static inline int test_read(struct v4l2_subdev *sd, u8 reg) 65554450f59SHans Verkuil { 65654450f59SHans Verkuil struct adv7604_state *state = to_state(sd); 65754450f59SHans Verkuil 65805cacb17SLaurent Pinchart return adv_smbus_read_byte_data(state, ADV7604_PAGE_TEST, reg); 65954450f59SHans Verkuil } 66054450f59SHans Verkuil 66154450f59SHans Verkuil static inline int test_write(struct v4l2_subdev *sd, u8 reg, u8 val) 66254450f59SHans Verkuil { 66354450f59SHans Verkuil struct adv7604_state *state = to_state(sd); 66454450f59SHans Verkuil 66505cacb17SLaurent Pinchart return adv_smbus_write_byte_data(state, ADV7604_PAGE_TEST, reg, val); 66654450f59SHans Verkuil } 66754450f59SHans Verkuil 66854450f59SHans Verkuil static inline int cp_read(struct v4l2_subdev *sd, u8 reg) 66954450f59SHans Verkuil { 67054450f59SHans Verkuil struct adv7604_state *state = to_state(sd); 67154450f59SHans Verkuil 67205cacb17SLaurent Pinchart return adv_smbus_read_byte_data(state, ADV7604_PAGE_CP, reg); 67354450f59SHans Verkuil } 67454450f59SHans Verkuil 67551182a94SLaurent Pinchart static u16 cp_read16(struct v4l2_subdev *sd, u8 reg, u16 mask) 67651182a94SLaurent Pinchart { 67751182a94SLaurent Pinchart return ((cp_read(sd, reg) << 8) | cp_read(sd, reg + 1)) & mask; 67851182a94SLaurent Pinchart } 67951182a94SLaurent Pinchart 68054450f59SHans Verkuil static inline int cp_write(struct v4l2_subdev *sd, u8 reg, u8 val) 68154450f59SHans Verkuil { 68254450f59SHans Verkuil struct adv7604_state *state = to_state(sd); 68354450f59SHans Verkuil 68405cacb17SLaurent Pinchart return adv_smbus_write_byte_data(state, ADV7604_PAGE_CP, reg, val); 68554450f59SHans Verkuil } 68654450f59SHans Verkuil 68722d97e56SLaurent Pinchart static inline int cp_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) 68854450f59SHans Verkuil { 68922d97e56SLaurent Pinchart return cp_write(sd, reg, (cp_read(sd, reg) & ~mask) | val); 69054450f59SHans Verkuil } 69154450f59SHans Verkuil 69254450f59SHans Verkuil static inline int vdp_read(struct v4l2_subdev *sd, u8 reg) 69354450f59SHans Verkuil { 69454450f59SHans Verkuil struct adv7604_state *state = to_state(sd); 69554450f59SHans Verkuil 69605cacb17SLaurent Pinchart return adv_smbus_read_byte_data(state, ADV7604_PAGE_VDP, reg); 69754450f59SHans Verkuil } 69854450f59SHans Verkuil 69954450f59SHans Verkuil static inline int vdp_write(struct v4l2_subdev *sd, u8 reg, u8 val) 70054450f59SHans Verkuil { 70154450f59SHans Verkuil struct adv7604_state *state = to_state(sd); 70254450f59SHans Verkuil 70305cacb17SLaurent Pinchart return adv_smbus_write_byte_data(state, ADV7604_PAGE_VDP, reg, val); 70454450f59SHans Verkuil } 70554450f59SHans Verkuil 706d42010a1SLars-Peter Clausen #define ADV7604_REG(page, offset) (((page) << 8) | (offset)) 707d42010a1SLars-Peter Clausen #define ADV7604_REG_SEQ_TERM 0xffff 708d42010a1SLars-Peter Clausen 709d42010a1SLars-Peter Clausen #ifdef CONFIG_VIDEO_ADV_DEBUG 710d42010a1SLars-Peter Clausen static int adv7604_read_reg(struct v4l2_subdev *sd, unsigned int reg) 711d42010a1SLars-Peter Clausen { 712d42010a1SLars-Peter Clausen struct adv7604_state *state = to_state(sd); 713d42010a1SLars-Peter Clausen unsigned int page = reg >> 8; 714d42010a1SLars-Peter Clausen 715d42010a1SLars-Peter Clausen if (!(BIT(page) & state->info->page_mask)) 716d42010a1SLars-Peter Clausen return -EINVAL; 717d42010a1SLars-Peter Clausen 718d42010a1SLars-Peter Clausen reg &= 0xff; 719d42010a1SLars-Peter Clausen 72005cacb17SLaurent Pinchart return adv_smbus_read_byte_data(state, page, reg); 721d42010a1SLars-Peter Clausen } 722d42010a1SLars-Peter Clausen #endif 723d42010a1SLars-Peter Clausen 724d42010a1SLars-Peter Clausen static int adv7604_write_reg(struct v4l2_subdev *sd, unsigned int reg, u8 val) 725d42010a1SLars-Peter Clausen { 726d42010a1SLars-Peter Clausen struct adv7604_state *state = to_state(sd); 727d42010a1SLars-Peter Clausen unsigned int page = reg >> 8; 728d42010a1SLars-Peter Clausen 729d42010a1SLars-Peter Clausen if (!(BIT(page) & state->info->page_mask)) 730d42010a1SLars-Peter Clausen return -EINVAL; 731d42010a1SLars-Peter Clausen 732d42010a1SLars-Peter Clausen reg &= 0xff; 733d42010a1SLars-Peter Clausen 73405cacb17SLaurent Pinchart return adv_smbus_write_byte_data(state, page, reg, val); 735d42010a1SLars-Peter Clausen } 736d42010a1SLars-Peter Clausen 737d42010a1SLars-Peter Clausen static void adv7604_write_reg_seq(struct v4l2_subdev *sd, 738d42010a1SLars-Peter Clausen const struct adv7604_reg_seq *reg_seq) 739d42010a1SLars-Peter Clausen { 740d42010a1SLars-Peter Clausen unsigned int i; 741d42010a1SLars-Peter Clausen 742d42010a1SLars-Peter Clausen for (i = 0; reg_seq[i].reg != ADV7604_REG_SEQ_TERM; i++) 743d42010a1SLars-Peter Clausen adv7604_write_reg(sd, reg_seq[i].reg, reg_seq[i].val); 744d42010a1SLars-Peter Clausen } 745d42010a1SLars-Peter Clausen 746539b33b0SLaurent Pinchart /* ----------------------------------------------------------------------------- 747539b33b0SLaurent Pinchart * Format helpers 748539b33b0SLaurent Pinchart */ 749539b33b0SLaurent Pinchart 750539b33b0SLaurent Pinchart static const struct adv7604_format_info adv7604_formats[] = { 751539b33b0SLaurent Pinchart { V4L2_MBUS_FMT_RGB888_1X24, ADV7604_OP_CH_SEL_RGB, true, false, 752539b33b0SLaurent Pinchart ADV7604_OP_MODE_SEL_SDR_444 | ADV7604_OP_FORMAT_SEL_8BIT }, 753539b33b0SLaurent Pinchart { V4L2_MBUS_FMT_YUYV8_2X8, ADV7604_OP_CH_SEL_RGB, false, false, 754539b33b0SLaurent Pinchart ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_8BIT }, 755539b33b0SLaurent Pinchart { V4L2_MBUS_FMT_YVYU8_2X8, ADV7604_OP_CH_SEL_RGB, false, true, 756539b33b0SLaurent Pinchart ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_8BIT }, 757539b33b0SLaurent Pinchart { V4L2_MBUS_FMT_YUYV10_2X10, ADV7604_OP_CH_SEL_RGB, false, false, 758539b33b0SLaurent Pinchart ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_10BIT }, 759539b33b0SLaurent Pinchart { V4L2_MBUS_FMT_YVYU10_2X10, ADV7604_OP_CH_SEL_RGB, false, true, 760539b33b0SLaurent Pinchart ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_10BIT }, 761539b33b0SLaurent Pinchart { V4L2_MBUS_FMT_YUYV12_2X12, ADV7604_OP_CH_SEL_RGB, false, false, 762539b33b0SLaurent Pinchart ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_12BIT }, 763539b33b0SLaurent Pinchart { V4L2_MBUS_FMT_YVYU12_2X12, ADV7604_OP_CH_SEL_RGB, false, true, 764539b33b0SLaurent Pinchart ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_12BIT }, 765539b33b0SLaurent Pinchart { V4L2_MBUS_FMT_UYVY8_1X16, ADV7604_OP_CH_SEL_RBG, false, false, 766539b33b0SLaurent Pinchart ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_8BIT }, 767539b33b0SLaurent Pinchart { V4L2_MBUS_FMT_VYUY8_1X16, ADV7604_OP_CH_SEL_RBG, false, true, 768539b33b0SLaurent Pinchart ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_8BIT }, 769539b33b0SLaurent Pinchart { V4L2_MBUS_FMT_YUYV8_1X16, ADV7604_OP_CH_SEL_RGB, false, false, 770539b33b0SLaurent Pinchart ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_8BIT }, 771539b33b0SLaurent Pinchart { V4L2_MBUS_FMT_YVYU8_1X16, ADV7604_OP_CH_SEL_RGB, false, true, 772539b33b0SLaurent Pinchart ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_8BIT }, 773539b33b0SLaurent Pinchart { V4L2_MBUS_FMT_UYVY10_1X20, ADV7604_OP_CH_SEL_RBG, false, false, 774539b33b0SLaurent Pinchart ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT }, 775539b33b0SLaurent Pinchart { V4L2_MBUS_FMT_VYUY10_1X20, ADV7604_OP_CH_SEL_RBG, false, true, 776539b33b0SLaurent Pinchart ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT }, 777539b33b0SLaurent Pinchart { V4L2_MBUS_FMT_YUYV10_1X20, ADV7604_OP_CH_SEL_RGB, false, false, 778539b33b0SLaurent Pinchart ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT }, 779539b33b0SLaurent Pinchart { V4L2_MBUS_FMT_YVYU10_1X20, ADV7604_OP_CH_SEL_RGB, false, true, 780539b33b0SLaurent Pinchart ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT }, 781539b33b0SLaurent Pinchart { V4L2_MBUS_FMT_UYVY12_1X24, ADV7604_OP_CH_SEL_RBG, false, false, 782539b33b0SLaurent Pinchart ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_12BIT }, 783539b33b0SLaurent Pinchart { V4L2_MBUS_FMT_VYUY12_1X24, ADV7604_OP_CH_SEL_RBG, false, true, 784539b33b0SLaurent Pinchart ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_12BIT }, 785539b33b0SLaurent Pinchart { V4L2_MBUS_FMT_YUYV12_1X24, ADV7604_OP_CH_SEL_RGB, false, false, 786539b33b0SLaurent Pinchart ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_12BIT }, 787539b33b0SLaurent Pinchart { V4L2_MBUS_FMT_YVYU12_1X24, ADV7604_OP_CH_SEL_RGB, false, true, 788539b33b0SLaurent Pinchart ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_12BIT }, 789539b33b0SLaurent Pinchart }; 790539b33b0SLaurent Pinchart 791539b33b0SLaurent Pinchart static const struct adv7604_format_info adv7611_formats[] = { 792539b33b0SLaurent Pinchart { V4L2_MBUS_FMT_RGB888_1X24, ADV7604_OP_CH_SEL_RGB, true, false, 793539b33b0SLaurent Pinchart ADV7604_OP_MODE_SEL_SDR_444 | ADV7604_OP_FORMAT_SEL_8BIT }, 794539b33b0SLaurent Pinchart { V4L2_MBUS_FMT_YUYV8_2X8, ADV7604_OP_CH_SEL_RGB, false, false, 795539b33b0SLaurent Pinchart ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_8BIT }, 796539b33b0SLaurent Pinchart { V4L2_MBUS_FMT_YVYU8_2X8, ADV7604_OP_CH_SEL_RGB, false, true, 797539b33b0SLaurent Pinchart ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_8BIT }, 798539b33b0SLaurent Pinchart { V4L2_MBUS_FMT_YUYV12_2X12, ADV7604_OP_CH_SEL_RGB, false, false, 799539b33b0SLaurent Pinchart ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_12BIT }, 800539b33b0SLaurent Pinchart { V4L2_MBUS_FMT_YVYU12_2X12, ADV7604_OP_CH_SEL_RGB, false, true, 801539b33b0SLaurent Pinchart ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_12BIT }, 802539b33b0SLaurent Pinchart { V4L2_MBUS_FMT_UYVY8_1X16, ADV7604_OP_CH_SEL_RBG, false, false, 803539b33b0SLaurent Pinchart ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_8BIT }, 804539b33b0SLaurent Pinchart { V4L2_MBUS_FMT_VYUY8_1X16, ADV7604_OP_CH_SEL_RBG, false, true, 805539b33b0SLaurent Pinchart ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_8BIT }, 806539b33b0SLaurent Pinchart { V4L2_MBUS_FMT_YUYV8_1X16, ADV7604_OP_CH_SEL_RGB, false, false, 807539b33b0SLaurent Pinchart ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_8BIT }, 808539b33b0SLaurent Pinchart { V4L2_MBUS_FMT_YVYU8_1X16, ADV7604_OP_CH_SEL_RGB, false, true, 809539b33b0SLaurent Pinchart ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_8BIT }, 810539b33b0SLaurent Pinchart { V4L2_MBUS_FMT_UYVY12_1X24, ADV7604_OP_CH_SEL_RBG, false, false, 811539b33b0SLaurent Pinchart ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_12BIT }, 812539b33b0SLaurent Pinchart { V4L2_MBUS_FMT_VYUY12_1X24, ADV7604_OP_CH_SEL_RBG, false, true, 813539b33b0SLaurent Pinchart ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_12BIT }, 814539b33b0SLaurent Pinchart { V4L2_MBUS_FMT_YUYV12_1X24, ADV7604_OP_CH_SEL_RGB, false, false, 815539b33b0SLaurent Pinchart ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_12BIT }, 816539b33b0SLaurent Pinchart { V4L2_MBUS_FMT_YVYU12_1X24, ADV7604_OP_CH_SEL_RGB, false, true, 817539b33b0SLaurent Pinchart ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_12BIT }, 818539b33b0SLaurent Pinchart }; 819539b33b0SLaurent Pinchart 820539b33b0SLaurent Pinchart static const struct adv7604_format_info * 821539b33b0SLaurent Pinchart adv7604_format_info(struct adv7604_state *state, enum v4l2_mbus_pixelcode code) 822539b33b0SLaurent Pinchart { 823539b33b0SLaurent Pinchart unsigned int i; 824539b33b0SLaurent Pinchart 825539b33b0SLaurent Pinchart for (i = 0; i < state->info->nformats; ++i) { 826539b33b0SLaurent Pinchart if (state->info->formats[i].code == code) 827539b33b0SLaurent Pinchart return &state->info->formats[i]; 828539b33b0SLaurent Pinchart } 829539b33b0SLaurent Pinchart 830539b33b0SLaurent Pinchart return NULL; 831539b33b0SLaurent Pinchart } 832539b33b0SLaurent Pinchart 83354450f59SHans Verkuil /* ----------------------------------------------------------------------- */ 83454450f59SHans Verkuil 8354a31a93aSMats Randgaard static inline bool is_analog_input(struct v4l2_subdev *sd) 8364a31a93aSMats Randgaard { 8374a31a93aSMats Randgaard struct adv7604_state *state = to_state(sd); 8384a31a93aSMats Randgaard 839c784b1e2SLaurent Pinchart return state->selected_input == ADV7604_PAD_VGA_RGB || 840c784b1e2SLaurent Pinchart state->selected_input == ADV7604_PAD_VGA_COMP; 8414a31a93aSMats Randgaard } 8424a31a93aSMats Randgaard 8434a31a93aSMats Randgaard static inline bool is_digital_input(struct v4l2_subdev *sd) 8444a31a93aSMats Randgaard { 8454a31a93aSMats Randgaard struct adv7604_state *state = to_state(sd); 8464a31a93aSMats Randgaard 847c784b1e2SLaurent Pinchart return state->selected_input == ADV7604_PAD_HDMI_PORT_A || 848c784b1e2SLaurent Pinchart state->selected_input == ADV7604_PAD_HDMI_PORT_B || 849c784b1e2SLaurent Pinchart state->selected_input == ADV7604_PAD_HDMI_PORT_C || 850c784b1e2SLaurent Pinchart state->selected_input == ADV7604_PAD_HDMI_PORT_D; 8514a31a93aSMats Randgaard } 8524a31a93aSMats Randgaard 8534a31a93aSMats Randgaard /* ----------------------------------------------------------------------- */ 8544a31a93aSMats Randgaard 85554450f59SHans Verkuil #ifdef CONFIG_VIDEO_ADV_DEBUG 85654450f59SHans Verkuil static void adv7604_inv_register(struct v4l2_subdev *sd) 85754450f59SHans Verkuil { 85854450f59SHans Verkuil v4l2_info(sd, "0x000-0x0ff: IO Map\n"); 85954450f59SHans Verkuil v4l2_info(sd, "0x100-0x1ff: AVLink Map\n"); 86054450f59SHans Verkuil v4l2_info(sd, "0x200-0x2ff: CEC Map\n"); 86154450f59SHans Verkuil v4l2_info(sd, "0x300-0x3ff: InfoFrame Map\n"); 86254450f59SHans Verkuil v4l2_info(sd, "0x400-0x4ff: ESDP Map\n"); 86354450f59SHans Verkuil v4l2_info(sd, "0x500-0x5ff: DPP Map\n"); 86454450f59SHans Verkuil v4l2_info(sd, "0x600-0x6ff: AFE Map\n"); 86554450f59SHans Verkuil v4l2_info(sd, "0x700-0x7ff: Repeater Map\n"); 86654450f59SHans Verkuil v4l2_info(sd, "0x800-0x8ff: EDID Map\n"); 86754450f59SHans Verkuil v4l2_info(sd, "0x900-0x9ff: HDMI Map\n"); 86854450f59SHans Verkuil v4l2_info(sd, "0xa00-0xaff: Test Map\n"); 86954450f59SHans Verkuil v4l2_info(sd, "0xb00-0xbff: CP Map\n"); 87054450f59SHans Verkuil v4l2_info(sd, "0xc00-0xcff: VDP Map\n"); 87154450f59SHans Verkuil } 87254450f59SHans Verkuil 87354450f59SHans Verkuil static int adv7604_g_register(struct v4l2_subdev *sd, 87454450f59SHans Verkuil struct v4l2_dbg_register *reg) 87554450f59SHans Verkuil { 876d42010a1SLars-Peter Clausen int ret; 877d42010a1SLars-Peter Clausen 878d42010a1SLars-Peter Clausen ret = adv7604_read_reg(sd, reg->reg); 879d42010a1SLars-Peter Clausen if (ret < 0) { 88054450f59SHans Verkuil v4l2_info(sd, "Register %03llx not supported\n", reg->reg); 88154450f59SHans Verkuil adv7604_inv_register(sd); 882d42010a1SLars-Peter Clausen return ret; 88354450f59SHans Verkuil } 884d42010a1SLars-Peter Clausen 885d42010a1SLars-Peter Clausen reg->size = 1; 886d42010a1SLars-Peter Clausen reg->val = ret; 887d42010a1SLars-Peter Clausen 88854450f59SHans Verkuil return 0; 88954450f59SHans Verkuil } 89054450f59SHans Verkuil 89154450f59SHans Verkuil static int adv7604_s_register(struct v4l2_subdev *sd, 892977ba3b1SHans Verkuil const struct v4l2_dbg_register *reg) 89354450f59SHans Verkuil { 894d42010a1SLars-Peter Clausen int ret; 8951577461bSHans Verkuil 896d42010a1SLars-Peter Clausen ret = adv7604_write_reg(sd, reg->reg, reg->val); 897d42010a1SLars-Peter Clausen if (ret < 0) { 89854450f59SHans Verkuil v4l2_info(sd, "Register %03llx not supported\n", reg->reg); 89954450f59SHans Verkuil adv7604_inv_register(sd); 900d42010a1SLars-Peter Clausen return ret; 90154450f59SHans Verkuil } 902d42010a1SLars-Peter Clausen 90354450f59SHans Verkuil return 0; 90454450f59SHans Verkuil } 90554450f59SHans Verkuil #endif 90654450f59SHans Verkuil 907d42010a1SLars-Peter Clausen static unsigned int adv7604_read_cable_det(struct v4l2_subdev *sd) 908d42010a1SLars-Peter Clausen { 909d42010a1SLars-Peter Clausen u8 value = io_read(sd, 0x6f); 910d42010a1SLars-Peter Clausen 911d42010a1SLars-Peter Clausen return ((value & 0x10) >> 4) 912d42010a1SLars-Peter Clausen | ((value & 0x08) >> 2) 913d42010a1SLars-Peter Clausen | ((value & 0x04) << 0) 914d42010a1SLars-Peter Clausen | ((value & 0x02) << 2); 915d42010a1SLars-Peter Clausen } 916d42010a1SLars-Peter Clausen 917d42010a1SLars-Peter Clausen static unsigned int adv7611_read_cable_det(struct v4l2_subdev *sd) 918d42010a1SLars-Peter Clausen { 919d42010a1SLars-Peter Clausen u8 value = io_read(sd, 0x6f); 920d42010a1SLars-Peter Clausen 921d42010a1SLars-Peter Clausen return value & 1; 922d42010a1SLars-Peter Clausen } 923d42010a1SLars-Peter Clausen 92454450f59SHans Verkuil static int adv7604_s_detect_tx_5v_ctrl(struct v4l2_subdev *sd) 92554450f59SHans Verkuil { 92654450f59SHans Verkuil struct adv7604_state *state = to_state(sd); 927d42010a1SLars-Peter Clausen const struct adv7604_chip_info *info = state->info; 92854450f59SHans Verkuil 92954450f59SHans Verkuil return v4l2_ctrl_s_ctrl(state->detect_tx_5v_ctrl, 930d42010a1SLars-Peter Clausen info->read_cable_det(sd)); 93154450f59SHans Verkuil } 93254450f59SHans Verkuil 933ccbd5bc4SHans Verkuil static int find_and_set_predefined_video_timings(struct v4l2_subdev *sd, 934ccbd5bc4SHans Verkuil u8 prim_mode, 935ccbd5bc4SHans Verkuil const struct adv7604_video_standards *predef_vid_timings, 936ccbd5bc4SHans Verkuil const struct v4l2_dv_timings *timings) 93754450f59SHans Verkuil { 938ccbd5bc4SHans Verkuil int i; 93954450f59SHans Verkuil 940ccbd5bc4SHans Verkuil for (i = 0; predef_vid_timings[i].timings.bt.width; i++) { 941ef1ed8f5SHans Verkuil if (!v4l2_match_dv_timings(timings, &predef_vid_timings[i].timings, 9424a31a93aSMats Randgaard is_digital_input(sd) ? 250000 : 1000000)) 943ccbd5bc4SHans Verkuil continue; 944ccbd5bc4SHans Verkuil io_write(sd, 0x00, predef_vid_timings[i].vid_std); /* video std */ 945ccbd5bc4SHans Verkuil io_write(sd, 0x01, (predef_vid_timings[i].v_freq << 4) + 946ccbd5bc4SHans Verkuil prim_mode); /* v_freq and prim mode */ 947ccbd5bc4SHans Verkuil return 0; 94854450f59SHans Verkuil } 94954450f59SHans Verkuil 950ccbd5bc4SHans Verkuil return -1; 951ccbd5bc4SHans Verkuil } 95254450f59SHans Verkuil 953ccbd5bc4SHans Verkuil static int configure_predefined_video_timings(struct v4l2_subdev *sd, 954ccbd5bc4SHans Verkuil struct v4l2_dv_timings *timings) 955ccbd5bc4SHans Verkuil { 956ccbd5bc4SHans Verkuil struct adv7604_state *state = to_state(sd); 957ccbd5bc4SHans Verkuil int err; 958ccbd5bc4SHans Verkuil 959ccbd5bc4SHans Verkuil v4l2_dbg(1, debug, sd, "%s", __func__); 960ccbd5bc4SHans Verkuil 961d42010a1SLars-Peter Clausen if (adv7604_has_afe(state)) { 96254450f59SHans Verkuil /* reset to default values */ 96354450f59SHans Verkuil io_write(sd, 0x16, 0x43); 96454450f59SHans Verkuil io_write(sd, 0x17, 0x5a); 965d42010a1SLars-Peter Clausen } 966ccbd5bc4SHans Verkuil /* disable embedded syncs for auto graphics mode */ 96722d97e56SLaurent Pinchart cp_write_clr_set(sd, 0x81, 0x10, 0x00); 968ccbd5bc4SHans Verkuil cp_write(sd, 0x8f, 0x00); 969ccbd5bc4SHans Verkuil cp_write(sd, 0x90, 0x00); 97054450f59SHans Verkuil cp_write(sd, 0xa2, 0x00); 97154450f59SHans Verkuil cp_write(sd, 0xa3, 0x00); 97254450f59SHans Verkuil cp_write(sd, 0xa4, 0x00); 97354450f59SHans Verkuil cp_write(sd, 0xa5, 0x00); 97454450f59SHans Verkuil cp_write(sd, 0xa6, 0x00); 97554450f59SHans Verkuil cp_write(sd, 0xa7, 0x00); 976ccbd5bc4SHans Verkuil cp_write(sd, 0xab, 0x00); 977ccbd5bc4SHans Verkuil cp_write(sd, 0xac, 0x00); 978ccbd5bc4SHans Verkuil 9794a31a93aSMats Randgaard if (is_analog_input(sd)) { 980ccbd5bc4SHans Verkuil err = find_and_set_predefined_video_timings(sd, 981ccbd5bc4SHans Verkuil 0x01, adv7604_prim_mode_comp, timings); 982ccbd5bc4SHans Verkuil if (err) 983ccbd5bc4SHans Verkuil err = find_and_set_predefined_video_timings(sd, 984ccbd5bc4SHans Verkuil 0x02, adv7604_prim_mode_gr, timings); 9854a31a93aSMats Randgaard } else if (is_digital_input(sd)) { 986ccbd5bc4SHans Verkuil err = find_and_set_predefined_video_timings(sd, 987ccbd5bc4SHans Verkuil 0x05, adv7604_prim_mode_hdmi_comp, timings); 988ccbd5bc4SHans Verkuil if (err) 989ccbd5bc4SHans Verkuil err = find_and_set_predefined_video_timings(sd, 990ccbd5bc4SHans Verkuil 0x06, adv7604_prim_mode_hdmi_gr, timings); 9914a31a93aSMats Randgaard } else { 9924a31a93aSMats Randgaard v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n", 9934a31a93aSMats Randgaard __func__, state->selected_input); 994ccbd5bc4SHans Verkuil err = -1; 99554450f59SHans Verkuil } 99654450f59SHans Verkuil 99754450f59SHans Verkuil 998ccbd5bc4SHans Verkuil return err; 999ccbd5bc4SHans Verkuil } 1000ccbd5bc4SHans Verkuil 1001ccbd5bc4SHans Verkuil static void configure_custom_video_timings(struct v4l2_subdev *sd, 1002ccbd5bc4SHans Verkuil const struct v4l2_bt_timings *bt) 1003ccbd5bc4SHans Verkuil { 1004ccbd5bc4SHans Verkuil struct adv7604_state *state = to_state(sd); 1005ccbd5bc4SHans Verkuil u32 width = htotal(bt); 1006ccbd5bc4SHans Verkuil u32 height = vtotal(bt); 1007ccbd5bc4SHans Verkuil u16 cp_start_sav = bt->hsync + bt->hbackporch - 4; 1008ccbd5bc4SHans Verkuil u16 cp_start_eav = width - bt->hfrontporch; 1009ccbd5bc4SHans Verkuil u16 cp_start_vbi = height - bt->vfrontporch; 1010ccbd5bc4SHans Verkuil u16 cp_end_vbi = bt->vsync + bt->vbackporch; 1011ccbd5bc4SHans Verkuil u16 ch1_fr_ll = (((u32)bt->pixelclock / 100) > 0) ? 1012ccbd5bc4SHans Verkuil ((width * (ADV7604_fsc / 100)) / ((u32)bt->pixelclock / 100)) : 0; 1013ccbd5bc4SHans Verkuil const u8 pll[2] = { 1014ccbd5bc4SHans Verkuil 0xc0 | ((width >> 8) & 0x1f), 1015ccbd5bc4SHans Verkuil width & 0xff 1016ccbd5bc4SHans Verkuil }; 1017ccbd5bc4SHans Verkuil 1018ccbd5bc4SHans Verkuil v4l2_dbg(2, debug, sd, "%s\n", __func__); 1019ccbd5bc4SHans Verkuil 10204a31a93aSMats Randgaard if (is_analog_input(sd)) { 1021ccbd5bc4SHans Verkuil /* auto graphics */ 1022ccbd5bc4SHans Verkuil io_write(sd, 0x00, 0x07); /* video std */ 1023ccbd5bc4SHans Verkuil io_write(sd, 0x01, 0x02); /* prim mode */ 1024ccbd5bc4SHans Verkuil /* enable embedded syncs for auto graphics mode */ 102522d97e56SLaurent Pinchart cp_write_clr_set(sd, 0x81, 0x10, 0x10); 1026ccbd5bc4SHans Verkuil 1027ccbd5bc4SHans Verkuil /* Should only be set in auto-graphics mode [REF_02, p. 91-92] */ 1028ccbd5bc4SHans Verkuil /* setup PLL_DIV_MAN_EN and PLL_DIV_RATIO */ 1029ccbd5bc4SHans Verkuil /* IO-map reg. 0x16 and 0x17 should be written in sequence */ 103005cacb17SLaurent Pinchart if (adv_smbus_write_i2c_block_data(state, ADV7604_PAGE_IO, 103105cacb17SLaurent Pinchart 0x16, 2, pll)) 1032ccbd5bc4SHans Verkuil v4l2_err(sd, "writing to reg 0x16 and 0x17 failed\n"); 1033ccbd5bc4SHans Verkuil 1034ccbd5bc4SHans Verkuil /* active video - horizontal timing */ 1035ccbd5bc4SHans Verkuil cp_write(sd, 0xa2, (cp_start_sav >> 4) & 0xff); 1036ccbd5bc4SHans Verkuil cp_write(sd, 0xa3, ((cp_start_sav & 0x0f) << 4) | 1037ccbd5bc4SHans Verkuil ((cp_start_eav >> 8) & 0x0f)); 1038ccbd5bc4SHans Verkuil cp_write(sd, 0xa4, cp_start_eav & 0xff); 1039ccbd5bc4SHans Verkuil 1040ccbd5bc4SHans Verkuil /* active video - vertical timing */ 1041ccbd5bc4SHans Verkuil cp_write(sd, 0xa5, (cp_start_vbi >> 4) & 0xff); 1042ccbd5bc4SHans Verkuil cp_write(sd, 0xa6, ((cp_start_vbi & 0xf) << 4) | 1043ccbd5bc4SHans Verkuil ((cp_end_vbi >> 8) & 0xf)); 1044ccbd5bc4SHans Verkuil cp_write(sd, 0xa7, cp_end_vbi & 0xff); 10454a31a93aSMats Randgaard } else if (is_digital_input(sd)) { 1046ccbd5bc4SHans Verkuil /* set default prim_mode/vid_std for HDMI 104739c1cb2bSJonathan McCrohan according to [REF_03, c. 4.2] */ 1048ccbd5bc4SHans Verkuil io_write(sd, 0x00, 0x02); /* video std */ 1049ccbd5bc4SHans Verkuil io_write(sd, 0x01, 0x06); /* prim mode */ 10504a31a93aSMats Randgaard } else { 10514a31a93aSMats Randgaard v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n", 10524a31a93aSMats Randgaard __func__, state->selected_input); 1053ccbd5bc4SHans Verkuil } 1054ccbd5bc4SHans Verkuil 1055ccbd5bc4SHans Verkuil cp_write(sd, 0x8f, (ch1_fr_ll >> 8) & 0x7); 1056ccbd5bc4SHans Verkuil cp_write(sd, 0x90, ch1_fr_ll & 0xff); 1057ccbd5bc4SHans Verkuil cp_write(sd, 0xab, (height >> 4) & 0xff); 1058ccbd5bc4SHans Verkuil cp_write(sd, 0xac, (height & 0x0f) << 4); 1059ccbd5bc4SHans Verkuil } 1060ccbd5bc4SHans Verkuil 10615c6c6349SMats Randgaard static void adv7604_set_offset(struct v4l2_subdev *sd, bool auto_offset, u16 offset_a, u16 offset_b, u16 offset_c) 10625c6c6349SMats Randgaard { 10635c6c6349SMats Randgaard struct adv7604_state *state = to_state(sd); 10645c6c6349SMats Randgaard u8 offset_buf[4]; 10655c6c6349SMats Randgaard 10665c6c6349SMats Randgaard if (auto_offset) { 10675c6c6349SMats Randgaard offset_a = 0x3ff; 10685c6c6349SMats Randgaard offset_b = 0x3ff; 10695c6c6349SMats Randgaard offset_c = 0x3ff; 10705c6c6349SMats Randgaard } 10715c6c6349SMats Randgaard 10725c6c6349SMats Randgaard v4l2_dbg(2, debug, sd, "%s: %s offset: a = 0x%x, b = 0x%x, c = 0x%x\n", 10735c6c6349SMats Randgaard __func__, auto_offset ? "Auto" : "Manual", 10745c6c6349SMats Randgaard offset_a, offset_b, offset_c); 10755c6c6349SMats Randgaard 10765c6c6349SMats Randgaard offset_buf[0] = (cp_read(sd, 0x77) & 0xc0) | ((offset_a & 0x3f0) >> 4); 10775c6c6349SMats Randgaard offset_buf[1] = ((offset_a & 0x00f) << 4) | ((offset_b & 0x3c0) >> 6); 10785c6c6349SMats Randgaard offset_buf[2] = ((offset_b & 0x03f) << 2) | ((offset_c & 0x300) >> 8); 10795c6c6349SMats Randgaard offset_buf[3] = offset_c & 0x0ff; 10805c6c6349SMats Randgaard 10815c6c6349SMats Randgaard /* Registers must be written in this order with no i2c access in between */ 108205cacb17SLaurent Pinchart if (adv_smbus_write_i2c_block_data(state, ADV7604_PAGE_CP, 108305cacb17SLaurent Pinchart 0x77, 4, offset_buf)) 10845c6c6349SMats Randgaard v4l2_err(sd, "%s: i2c error writing to CP reg 0x77, 0x78, 0x79, 0x7a\n", __func__); 10855c6c6349SMats Randgaard } 10865c6c6349SMats Randgaard 10875c6c6349SMats Randgaard static void adv7604_set_gain(struct v4l2_subdev *sd, bool auto_gain, u16 gain_a, u16 gain_b, u16 gain_c) 10885c6c6349SMats Randgaard { 10895c6c6349SMats Randgaard struct adv7604_state *state = to_state(sd); 10905c6c6349SMats Randgaard u8 gain_buf[4]; 10915c6c6349SMats Randgaard u8 gain_man = 1; 10925c6c6349SMats Randgaard u8 agc_mode_man = 1; 10935c6c6349SMats Randgaard 10945c6c6349SMats Randgaard if (auto_gain) { 10955c6c6349SMats Randgaard gain_man = 0; 10965c6c6349SMats Randgaard agc_mode_man = 0; 10975c6c6349SMats Randgaard gain_a = 0x100; 10985c6c6349SMats Randgaard gain_b = 0x100; 10995c6c6349SMats Randgaard gain_c = 0x100; 11005c6c6349SMats Randgaard } 11015c6c6349SMats Randgaard 11025c6c6349SMats Randgaard v4l2_dbg(2, debug, sd, "%s: %s gain: a = 0x%x, b = 0x%x, c = 0x%x\n", 11035c6c6349SMats Randgaard __func__, auto_gain ? "Auto" : "Manual", 11045c6c6349SMats Randgaard gain_a, gain_b, gain_c); 11055c6c6349SMats Randgaard 11065c6c6349SMats Randgaard gain_buf[0] = ((gain_man << 7) | (agc_mode_man << 6) | ((gain_a & 0x3f0) >> 4)); 11075c6c6349SMats Randgaard gain_buf[1] = (((gain_a & 0x00f) << 4) | ((gain_b & 0x3c0) >> 6)); 11085c6c6349SMats Randgaard gain_buf[2] = (((gain_b & 0x03f) << 2) | ((gain_c & 0x300) >> 8)); 11095c6c6349SMats Randgaard gain_buf[3] = ((gain_c & 0x0ff)); 11105c6c6349SMats Randgaard 11115c6c6349SMats Randgaard /* Registers must be written in this order with no i2c access in between */ 111205cacb17SLaurent Pinchart if (adv_smbus_write_i2c_block_data(state, ADV7604_PAGE_CP, 111305cacb17SLaurent Pinchart 0x73, 4, gain_buf)) 11145c6c6349SMats Randgaard v4l2_err(sd, "%s: i2c error writing to CP reg 0x73, 0x74, 0x75, 0x76\n", __func__); 11155c6c6349SMats Randgaard } 11165c6c6349SMats Randgaard 111754450f59SHans Verkuil static void set_rgb_quantization_range(struct v4l2_subdev *sd) 111854450f59SHans Verkuil { 111954450f59SHans Verkuil struct adv7604_state *state = to_state(sd); 11205c6c6349SMats Randgaard bool rgb_output = io_read(sd, 0x02) & 0x02; 11215c6c6349SMats Randgaard bool hdmi_signal = hdmi_read(sd, 0x05) & 0x80; 112254450f59SHans Verkuil 11235c6c6349SMats Randgaard v4l2_dbg(2, debug, sd, "%s: RGB quantization range: %d, RGB out: %d, HDMI: %d\n", 11245c6c6349SMats Randgaard __func__, state->rgb_quantization_range, 11255c6c6349SMats Randgaard rgb_output, hdmi_signal); 11265c6c6349SMats Randgaard 11275c6c6349SMats Randgaard adv7604_set_gain(sd, true, 0x0, 0x0, 0x0); 11285c6c6349SMats Randgaard adv7604_set_offset(sd, true, 0x0, 0x0, 0x0); 11299833239eSMats Randgaard 113054450f59SHans Verkuil switch (state->rgb_quantization_range) { 113154450f59SHans Verkuil case V4L2_DV_RGB_RANGE_AUTO: 1132c784b1e2SLaurent Pinchart if (state->selected_input == ADV7604_PAD_VGA_RGB) { 11339833239eSMats Randgaard /* Receiving analog RGB signal 11349833239eSMats Randgaard * Set RGB full range (0-255) */ 113522d97e56SLaurent Pinchart io_write_clr_set(sd, 0x02, 0xf0, 0x10); 11369833239eSMats Randgaard break; 11379833239eSMats Randgaard } 113854450f59SHans Verkuil 1139c784b1e2SLaurent Pinchart if (state->selected_input == ADV7604_PAD_VGA_COMP) { 11409833239eSMats Randgaard /* Receiving analog YPbPr signal 11419833239eSMats Randgaard * Set automode */ 114222d97e56SLaurent Pinchart io_write_clr_set(sd, 0x02, 0xf0, 0xf0); 11439833239eSMats Randgaard break; 11449833239eSMats Randgaard } 11459833239eSMats Randgaard 11465c6c6349SMats Randgaard if (hdmi_signal) { 11479833239eSMats Randgaard /* Receiving HDMI signal 11489833239eSMats Randgaard * Set automode */ 114922d97e56SLaurent Pinchart io_write_clr_set(sd, 0x02, 0xf0, 0xf0); 11509833239eSMats Randgaard break; 11519833239eSMats Randgaard } 11529833239eSMats Randgaard 11539833239eSMats Randgaard /* Receiving DVI-D signal 11549833239eSMats Randgaard * ADV7604 selects RGB limited range regardless of 11559833239eSMats Randgaard * input format (CE/IT) in automatic mode */ 115654450f59SHans Verkuil if (state->timings.bt.standards & V4L2_DV_BT_STD_CEA861) { 115754450f59SHans Verkuil /* RGB limited range (16-235) */ 115822d97e56SLaurent Pinchart io_write_clr_set(sd, 0x02, 0xf0, 0x00); 115954450f59SHans Verkuil } else { 116054450f59SHans Verkuil /* RGB full range (0-255) */ 116122d97e56SLaurent Pinchart io_write_clr_set(sd, 0x02, 0xf0, 0x10); 11625c6c6349SMats Randgaard 11635c6c6349SMats Randgaard if (is_digital_input(sd) && rgb_output) { 11645c6c6349SMats Randgaard adv7604_set_offset(sd, false, 0x40, 0x40, 0x40); 11655c6c6349SMats Randgaard } else { 11665c6c6349SMats Randgaard adv7604_set_gain(sd, false, 0xe0, 0xe0, 0xe0); 11675c6c6349SMats Randgaard adv7604_set_offset(sd, false, 0x70, 0x70, 0x70); 11685c6c6349SMats Randgaard } 116954450f59SHans Verkuil } 117054450f59SHans Verkuil break; 117154450f59SHans Verkuil case V4L2_DV_RGB_RANGE_LIMITED: 1172c784b1e2SLaurent Pinchart if (state->selected_input == ADV7604_PAD_VGA_COMP) { 1173d261e842SMats Randgaard /* YCrCb limited range (16-235) */ 117422d97e56SLaurent Pinchart io_write_clr_set(sd, 0x02, 0xf0, 0x20); 11755c6c6349SMats Randgaard break; 11765c6c6349SMats Randgaard } 11775c6c6349SMats Randgaard 117854450f59SHans Verkuil /* RGB limited range (16-235) */ 117922d97e56SLaurent Pinchart io_write_clr_set(sd, 0x02, 0xf0, 0x00); 11805c6c6349SMats Randgaard 118154450f59SHans Verkuil break; 118254450f59SHans Verkuil case V4L2_DV_RGB_RANGE_FULL: 1183c784b1e2SLaurent Pinchart if (state->selected_input == ADV7604_PAD_VGA_COMP) { 1184d261e842SMats Randgaard /* YCrCb full range (0-255) */ 118522d97e56SLaurent Pinchart io_write_clr_set(sd, 0x02, 0xf0, 0x60); 11865c6c6349SMats Randgaard break; 11875c6c6349SMats Randgaard } 11885c6c6349SMats Randgaard 118954450f59SHans Verkuil /* RGB full range (0-255) */ 119022d97e56SLaurent Pinchart io_write_clr_set(sd, 0x02, 0xf0, 0x10); 11915c6c6349SMats Randgaard 11925c6c6349SMats Randgaard if (is_analog_input(sd) || hdmi_signal) 11935c6c6349SMats Randgaard break; 11945c6c6349SMats Randgaard 11955c6c6349SMats Randgaard /* Adjust gain/offset for DVI-D signals only */ 11965c6c6349SMats Randgaard if (rgb_output) { 11975c6c6349SMats Randgaard adv7604_set_offset(sd, false, 0x40, 0x40, 0x40); 11985c6c6349SMats Randgaard } else { 11995c6c6349SMats Randgaard adv7604_set_gain(sd, false, 0xe0, 0xe0, 0xe0); 12005c6c6349SMats Randgaard adv7604_set_offset(sd, false, 0x70, 0x70, 0x70); 1201d261e842SMats Randgaard } 120254450f59SHans Verkuil break; 120354450f59SHans Verkuil } 120454450f59SHans Verkuil } 120554450f59SHans Verkuil 120654450f59SHans Verkuil static int adv7604_s_ctrl(struct v4l2_ctrl *ctrl) 120754450f59SHans Verkuil { 1208c269887cSLaurent Pinchart struct v4l2_subdev *sd = 1209c269887cSLaurent Pinchart &container_of(ctrl->handler, struct adv7604_state, hdl)->sd; 1210c269887cSLaurent Pinchart 121154450f59SHans Verkuil struct adv7604_state *state = to_state(sd); 121254450f59SHans Verkuil 121354450f59SHans Verkuil switch (ctrl->id) { 121454450f59SHans Verkuil case V4L2_CID_BRIGHTNESS: 121554450f59SHans Verkuil cp_write(sd, 0x3c, ctrl->val); 121654450f59SHans Verkuil return 0; 121754450f59SHans Verkuil case V4L2_CID_CONTRAST: 121854450f59SHans Verkuil cp_write(sd, 0x3a, ctrl->val); 121954450f59SHans Verkuil return 0; 122054450f59SHans Verkuil case V4L2_CID_SATURATION: 122154450f59SHans Verkuil cp_write(sd, 0x3b, ctrl->val); 122254450f59SHans Verkuil return 0; 122354450f59SHans Verkuil case V4L2_CID_HUE: 122454450f59SHans Verkuil cp_write(sd, 0x3d, ctrl->val); 122554450f59SHans Verkuil return 0; 122654450f59SHans Verkuil case V4L2_CID_DV_RX_RGB_RANGE: 122754450f59SHans Verkuil state->rgb_quantization_range = ctrl->val; 122854450f59SHans Verkuil set_rgb_quantization_range(sd); 122954450f59SHans Verkuil return 0; 123054450f59SHans Verkuil case V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE: 1231d42010a1SLars-Peter Clausen if (!adv7604_has_afe(state)) 1232d42010a1SLars-Peter Clausen return -EINVAL; 123354450f59SHans Verkuil /* Set the analog sampling phase. This is needed to find the 123454450f59SHans Verkuil best sampling phase for analog video: an application or 123554450f59SHans Verkuil driver has to try a number of phases and analyze the picture 123654450f59SHans Verkuil quality before settling on the best performing phase. */ 123754450f59SHans Verkuil afe_write(sd, 0xc8, ctrl->val); 123854450f59SHans Verkuil return 0; 123954450f59SHans Verkuil case V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL: 124054450f59SHans Verkuil /* Use the default blue color for free running mode, 124154450f59SHans Verkuil or supply your own. */ 124222d97e56SLaurent Pinchart cp_write_clr_set(sd, 0xbf, 0x04, ctrl->val << 2); 124354450f59SHans Verkuil return 0; 124454450f59SHans Verkuil case V4L2_CID_ADV_RX_FREE_RUN_COLOR: 124554450f59SHans Verkuil cp_write(sd, 0xc0, (ctrl->val & 0xff0000) >> 16); 124654450f59SHans Verkuil cp_write(sd, 0xc1, (ctrl->val & 0x00ff00) >> 8); 124754450f59SHans Verkuil cp_write(sd, 0xc2, (u8)(ctrl->val & 0x0000ff)); 124854450f59SHans Verkuil return 0; 124954450f59SHans Verkuil } 125054450f59SHans Verkuil return -EINVAL; 125154450f59SHans Verkuil } 125254450f59SHans Verkuil 125354450f59SHans Verkuil /* ----------------------------------------------------------------------- */ 125454450f59SHans Verkuil 125554450f59SHans Verkuil static inline bool no_power(struct v4l2_subdev *sd) 125654450f59SHans Verkuil { 125754450f59SHans Verkuil /* Entire chip or CP powered off */ 125854450f59SHans Verkuil return io_read(sd, 0x0c) & 0x24; 125954450f59SHans Verkuil } 126054450f59SHans Verkuil 126154450f59SHans Verkuil static inline bool no_signal_tmds(struct v4l2_subdev *sd) 126254450f59SHans Verkuil { 12634a31a93aSMats Randgaard struct adv7604_state *state = to_state(sd); 12644a31a93aSMats Randgaard 12654a31a93aSMats Randgaard return !(io_read(sd, 0x6a) & (0x10 >> state->selected_input)); 126654450f59SHans Verkuil } 126754450f59SHans Verkuil 126854450f59SHans Verkuil static inline bool no_lock_tmds(struct v4l2_subdev *sd) 126954450f59SHans Verkuil { 1270d42010a1SLars-Peter Clausen struct adv7604_state *state = to_state(sd); 1271d42010a1SLars-Peter Clausen const struct adv7604_chip_info *info = state->info; 1272d42010a1SLars-Peter Clausen 1273d42010a1SLars-Peter Clausen return (io_read(sd, 0x6a) & info->tdms_lock_mask) != info->tdms_lock_mask; 127454450f59SHans Verkuil } 127554450f59SHans Verkuil 1276bb88f325SMartin Bugge static inline bool is_hdmi(struct v4l2_subdev *sd) 1277bb88f325SMartin Bugge { 1278bb88f325SMartin Bugge return hdmi_read(sd, 0x05) & 0x80; 1279bb88f325SMartin Bugge } 1280bb88f325SMartin Bugge 128154450f59SHans Verkuil static inline bool no_lock_sspd(struct v4l2_subdev *sd) 128254450f59SHans Verkuil { 1283d42010a1SLars-Peter Clausen struct adv7604_state *state = to_state(sd); 1284d42010a1SLars-Peter Clausen 1285d42010a1SLars-Peter Clausen /* 1286d42010a1SLars-Peter Clausen * Chips without a AFE don't expose registers for the SSPD, so just assume 1287d42010a1SLars-Peter Clausen * that we have a lock. 1288d42010a1SLars-Peter Clausen */ 1289d42010a1SLars-Peter Clausen if (adv7604_has_afe(state)) 1290d42010a1SLars-Peter Clausen return false; 1291d42010a1SLars-Peter Clausen 129254450f59SHans Verkuil /* TODO channel 2 */ 129354450f59SHans Verkuil return ((cp_read(sd, 0xb5) & 0xd0) != 0xd0); 129454450f59SHans Verkuil } 129554450f59SHans Verkuil 129654450f59SHans Verkuil static inline bool no_lock_stdi(struct v4l2_subdev *sd) 129754450f59SHans Verkuil { 129854450f59SHans Verkuil /* TODO channel 2 */ 129954450f59SHans Verkuil return !(cp_read(sd, 0xb1) & 0x80); 130054450f59SHans Verkuil } 130154450f59SHans Verkuil 130254450f59SHans Verkuil static inline bool no_signal(struct v4l2_subdev *sd) 130354450f59SHans Verkuil { 130454450f59SHans Verkuil bool ret; 130554450f59SHans Verkuil 130654450f59SHans Verkuil ret = no_power(sd); 130754450f59SHans Verkuil 130854450f59SHans Verkuil ret |= no_lock_stdi(sd); 130954450f59SHans Verkuil ret |= no_lock_sspd(sd); 131054450f59SHans Verkuil 13114a31a93aSMats Randgaard if (is_digital_input(sd)) { 131254450f59SHans Verkuil ret |= no_lock_tmds(sd); 131354450f59SHans Verkuil ret |= no_signal_tmds(sd); 131454450f59SHans Verkuil } 131554450f59SHans Verkuil 131654450f59SHans Verkuil return ret; 131754450f59SHans Verkuil } 131854450f59SHans Verkuil 131954450f59SHans Verkuil static inline bool no_lock_cp(struct v4l2_subdev *sd) 132054450f59SHans Verkuil { 1321d42010a1SLars-Peter Clausen struct adv7604_state *state = to_state(sd); 1322d42010a1SLars-Peter Clausen 1323d42010a1SLars-Peter Clausen if (!adv7604_has_afe(state)) 1324d42010a1SLars-Peter Clausen return false; 1325d42010a1SLars-Peter Clausen 132654450f59SHans Verkuil /* CP has detected a non standard number of lines on the incoming 132754450f59SHans Verkuil video compared to what it is configured to receive by s_dv_timings */ 132854450f59SHans Verkuil return io_read(sd, 0x12) & 0x01; 132954450f59SHans Verkuil } 133054450f59SHans Verkuil 133154450f59SHans Verkuil static int adv7604_g_input_status(struct v4l2_subdev *sd, u32 *status) 133254450f59SHans Verkuil { 133354450f59SHans Verkuil *status = 0; 133454450f59SHans Verkuil *status |= no_power(sd) ? V4L2_IN_ST_NO_POWER : 0; 133554450f59SHans Verkuil *status |= no_signal(sd) ? V4L2_IN_ST_NO_SIGNAL : 0; 133654450f59SHans Verkuil if (no_lock_cp(sd)) 13374a31a93aSMats Randgaard *status |= is_digital_input(sd) ? V4L2_IN_ST_NO_SYNC : V4L2_IN_ST_NO_H_LOCK; 133854450f59SHans Verkuil 133954450f59SHans Verkuil v4l2_dbg(1, debug, sd, "%s: status = 0x%x\n", __func__, *status); 134054450f59SHans Verkuil 134154450f59SHans Verkuil return 0; 134254450f59SHans Verkuil } 134354450f59SHans Verkuil 134454450f59SHans Verkuil /* ----------------------------------------------------------------------- */ 134554450f59SHans Verkuil 134654450f59SHans Verkuil struct stdi_readback { 134754450f59SHans Verkuil u16 bl, lcf, lcvs; 134854450f59SHans Verkuil u8 hs_pol, vs_pol; 134954450f59SHans Verkuil bool interlaced; 135054450f59SHans Verkuil }; 135154450f59SHans Verkuil 135254450f59SHans Verkuil static int stdi2dv_timings(struct v4l2_subdev *sd, 135354450f59SHans Verkuil struct stdi_readback *stdi, 135454450f59SHans Verkuil struct v4l2_dv_timings *timings) 135554450f59SHans Verkuil { 135654450f59SHans Verkuil struct adv7604_state *state = to_state(sd); 135754450f59SHans Verkuil u32 hfreq = (ADV7604_fsc * 8) / stdi->bl; 135854450f59SHans Verkuil u32 pix_clk; 135954450f59SHans Verkuil int i; 136054450f59SHans Verkuil 136154450f59SHans Verkuil for (i = 0; adv7604_timings[i].bt.height; i++) { 136254450f59SHans Verkuil if (vtotal(&adv7604_timings[i].bt) != stdi->lcf + 1) 136354450f59SHans Verkuil continue; 136454450f59SHans Verkuil if (adv7604_timings[i].bt.vsync != stdi->lcvs) 136554450f59SHans Verkuil continue; 136654450f59SHans Verkuil 136754450f59SHans Verkuil pix_clk = hfreq * htotal(&adv7604_timings[i].bt); 136854450f59SHans Verkuil 136954450f59SHans Verkuil if ((pix_clk < adv7604_timings[i].bt.pixelclock + 1000000) && 137054450f59SHans Verkuil (pix_clk > adv7604_timings[i].bt.pixelclock - 1000000)) { 137154450f59SHans Verkuil *timings = adv7604_timings[i]; 137254450f59SHans Verkuil return 0; 137354450f59SHans Verkuil } 137454450f59SHans Verkuil } 137554450f59SHans Verkuil 137654450f59SHans Verkuil if (v4l2_detect_cvt(stdi->lcf + 1, hfreq, stdi->lcvs, 137754450f59SHans Verkuil (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) | 137854450f59SHans Verkuil (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0), 137954450f59SHans Verkuil timings)) 138054450f59SHans Verkuil return 0; 138154450f59SHans Verkuil if (v4l2_detect_gtf(stdi->lcf + 1, hfreq, stdi->lcvs, 138254450f59SHans Verkuil (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) | 138354450f59SHans Verkuil (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0), 138454450f59SHans Verkuil state->aspect_ratio, timings)) 138554450f59SHans Verkuil return 0; 138654450f59SHans Verkuil 1387ccbd5bc4SHans Verkuil v4l2_dbg(2, debug, sd, 1388ccbd5bc4SHans Verkuil "%s: No format candidate found for lcvs = %d, lcf=%d, bl = %d, %chsync, %cvsync\n", 1389ccbd5bc4SHans Verkuil __func__, stdi->lcvs, stdi->lcf, stdi->bl, 1390ccbd5bc4SHans Verkuil stdi->hs_pol, stdi->vs_pol); 139154450f59SHans Verkuil return -1; 139254450f59SHans Verkuil } 139354450f59SHans Verkuil 1394d42010a1SLars-Peter Clausen 139554450f59SHans Verkuil static int read_stdi(struct v4l2_subdev *sd, struct stdi_readback *stdi) 139654450f59SHans Verkuil { 1397d42010a1SLars-Peter Clausen struct adv7604_state *state = to_state(sd); 1398d42010a1SLars-Peter Clausen const struct adv7604_chip_info *info = state->info; 13994a2ccdd2SLaurent Pinchart u8 polarity; 14004a2ccdd2SLaurent Pinchart 140154450f59SHans Verkuil if (no_lock_stdi(sd) || no_lock_sspd(sd)) { 140254450f59SHans Verkuil v4l2_dbg(2, debug, sd, "%s: STDI and/or SSPD not locked\n", __func__); 140354450f59SHans Verkuil return -1; 140454450f59SHans Verkuil } 140554450f59SHans Verkuil 140654450f59SHans Verkuil /* read STDI */ 140751182a94SLaurent Pinchart stdi->bl = cp_read16(sd, 0xb1, 0x3fff); 1408d42010a1SLars-Peter Clausen stdi->lcf = cp_read16(sd, info->lcf_reg, 0x7ff); 140954450f59SHans Verkuil stdi->lcvs = cp_read(sd, 0xb3) >> 3; 141054450f59SHans Verkuil stdi->interlaced = io_read(sd, 0x12) & 0x10; 141154450f59SHans Verkuil 1412d42010a1SLars-Peter Clausen if (adv7604_has_afe(state)) { 141354450f59SHans Verkuil /* read SSPD */ 14144a2ccdd2SLaurent Pinchart polarity = cp_read(sd, 0xb5); 14154a2ccdd2SLaurent Pinchart if ((polarity & 0x03) == 0x01) { 14164a2ccdd2SLaurent Pinchart stdi->hs_pol = polarity & 0x10 14174a2ccdd2SLaurent Pinchart ? (polarity & 0x08 ? '+' : '-') : 'x'; 14184a2ccdd2SLaurent Pinchart stdi->vs_pol = polarity & 0x40 14194a2ccdd2SLaurent Pinchart ? (polarity & 0x20 ? '+' : '-') : 'x'; 142054450f59SHans Verkuil } else { 142154450f59SHans Verkuil stdi->hs_pol = 'x'; 142254450f59SHans Verkuil stdi->vs_pol = 'x'; 142354450f59SHans Verkuil } 1424d42010a1SLars-Peter Clausen } else { 1425d42010a1SLars-Peter Clausen polarity = hdmi_read(sd, 0x05); 1426d42010a1SLars-Peter Clausen stdi->hs_pol = polarity & 0x20 ? '+' : '-'; 1427d42010a1SLars-Peter Clausen stdi->vs_pol = polarity & 0x10 ? '+' : '-'; 1428d42010a1SLars-Peter Clausen } 142954450f59SHans Verkuil 143054450f59SHans Verkuil if (no_lock_stdi(sd) || no_lock_sspd(sd)) { 143154450f59SHans Verkuil v4l2_dbg(2, debug, sd, 143254450f59SHans Verkuil "%s: signal lost during readout of STDI/SSPD\n", __func__); 143354450f59SHans Verkuil return -1; 143454450f59SHans Verkuil } 143554450f59SHans Verkuil 143654450f59SHans Verkuil if (stdi->lcf < 239 || stdi->bl < 8 || stdi->bl == 0x3fff) { 143754450f59SHans Verkuil v4l2_dbg(2, debug, sd, "%s: invalid signal\n", __func__); 143854450f59SHans Verkuil memset(stdi, 0, sizeof(struct stdi_readback)); 143954450f59SHans Verkuil return -1; 144054450f59SHans Verkuil } 144154450f59SHans Verkuil 144254450f59SHans Verkuil v4l2_dbg(2, debug, sd, 144354450f59SHans Verkuil "%s: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %chsync, %cvsync, %s\n", 144454450f59SHans Verkuil __func__, stdi->lcf, stdi->bl, stdi->lcvs, 144554450f59SHans Verkuil stdi->hs_pol, stdi->vs_pol, 144654450f59SHans Verkuil stdi->interlaced ? "interlaced" : "progressive"); 144754450f59SHans Verkuil 144854450f59SHans Verkuil return 0; 144954450f59SHans Verkuil } 145054450f59SHans Verkuil 145154450f59SHans Verkuil static int adv7604_enum_dv_timings(struct v4l2_subdev *sd, 145254450f59SHans Verkuil struct v4l2_enum_dv_timings *timings) 145354450f59SHans Verkuil { 1454afec5599SLaurent Pinchart struct adv7604_state *state = to_state(sd); 1455afec5599SLaurent Pinchart 145654450f59SHans Verkuil if (timings->index >= ARRAY_SIZE(adv7604_timings) - 1) 145754450f59SHans Verkuil return -EINVAL; 1458afec5599SLaurent Pinchart 1459afec5599SLaurent Pinchart if (timings->pad >= state->source_pad) 1460afec5599SLaurent Pinchart return -EINVAL; 1461afec5599SLaurent Pinchart 146254450f59SHans Verkuil memset(timings->reserved, 0, sizeof(timings->reserved)); 146354450f59SHans Verkuil timings->timings = adv7604_timings[timings->index]; 146454450f59SHans Verkuil return 0; 146554450f59SHans Verkuil } 146654450f59SHans Verkuil 14677515e096SLaurent Pinchart static int adv7604_dv_timings_cap(struct v4l2_subdev *sd, 14687515e096SLaurent Pinchart struct v4l2_dv_timings_cap *cap) 1469afec5599SLaurent Pinchart { 14707515e096SLaurent Pinchart struct adv7604_state *state = to_state(sd); 14717515e096SLaurent Pinchart 14727515e096SLaurent Pinchart if (cap->pad >= state->source_pad) 14737515e096SLaurent Pinchart return -EINVAL; 14747515e096SLaurent Pinchart 1475afec5599SLaurent Pinchart cap->type = V4L2_DV_BT_656_1120; 1476afec5599SLaurent Pinchart cap->bt.max_width = 1920; 1477afec5599SLaurent Pinchart cap->bt.max_height = 1200; 1478afec5599SLaurent Pinchart cap->bt.min_pixelclock = 25000000; 1479afec5599SLaurent Pinchart 14807515e096SLaurent Pinchart switch (cap->pad) { 1481afec5599SLaurent Pinchart case ADV7604_PAD_HDMI_PORT_A: 1482afec5599SLaurent Pinchart case ADV7604_PAD_HDMI_PORT_B: 1483afec5599SLaurent Pinchart case ADV7604_PAD_HDMI_PORT_C: 1484afec5599SLaurent Pinchart case ADV7604_PAD_HDMI_PORT_D: 1485afec5599SLaurent Pinchart cap->bt.max_pixelclock = 225000000; 1486afec5599SLaurent Pinchart break; 1487afec5599SLaurent Pinchart case ADV7604_PAD_VGA_RGB: 1488afec5599SLaurent Pinchart case ADV7604_PAD_VGA_COMP: 1489afec5599SLaurent Pinchart default: 1490afec5599SLaurent Pinchart cap->bt.max_pixelclock = 170000000; 1491afec5599SLaurent Pinchart break; 1492afec5599SLaurent Pinchart } 1493afec5599SLaurent Pinchart 1494afec5599SLaurent Pinchart cap->bt.standards = V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT | 1495afec5599SLaurent Pinchart V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT; 1496afec5599SLaurent Pinchart cap->bt.capabilities = V4L2_DV_BT_CAP_PROGRESSIVE | 1497afec5599SLaurent Pinchart V4L2_DV_BT_CAP_REDUCED_BLANKING | V4L2_DV_BT_CAP_CUSTOM; 1498afec5599SLaurent Pinchart return 0; 1499afec5599SLaurent Pinchart } 1500afec5599SLaurent Pinchart 150154450f59SHans Verkuil /* Fill the optional fields .standards and .flags in struct v4l2_dv_timings 150254450f59SHans Verkuil if the format is listed in adv7604_timings[] */ 150354450f59SHans Verkuil static void adv7604_fill_optional_dv_timings_fields(struct v4l2_subdev *sd, 150454450f59SHans Verkuil struct v4l2_dv_timings *timings) 150554450f59SHans Verkuil { 150654450f59SHans Verkuil int i; 150754450f59SHans Verkuil 150854450f59SHans Verkuil for (i = 0; adv7604_timings[i].bt.width; i++) { 1509ef1ed8f5SHans Verkuil if (v4l2_match_dv_timings(timings, &adv7604_timings[i], 15104a31a93aSMats Randgaard is_digital_input(sd) ? 250000 : 1000000)) { 151154450f59SHans Verkuil *timings = adv7604_timings[i]; 151254450f59SHans Verkuil break; 151354450f59SHans Verkuil } 151454450f59SHans Verkuil } 151554450f59SHans Verkuil } 151654450f59SHans Verkuil 1517d42010a1SLars-Peter Clausen static unsigned int adv7604_read_hdmi_pixelclock(struct v4l2_subdev *sd) 1518d42010a1SLars-Peter Clausen { 1519d42010a1SLars-Peter Clausen unsigned int freq; 1520d42010a1SLars-Peter Clausen int a, b; 1521d42010a1SLars-Peter Clausen 1522d42010a1SLars-Peter Clausen a = hdmi_read(sd, 0x06); 1523d42010a1SLars-Peter Clausen b = hdmi_read(sd, 0x3b); 1524d42010a1SLars-Peter Clausen if (a < 0 || b < 0) 1525d42010a1SLars-Peter Clausen return 0; 1526d42010a1SLars-Peter Clausen freq = a * 1000000 + ((b & 0x30) >> 4) * 250000; 1527d42010a1SLars-Peter Clausen 1528d42010a1SLars-Peter Clausen if (is_hdmi(sd)) { 1529d42010a1SLars-Peter Clausen /* adjust for deep color mode */ 1530d42010a1SLars-Peter Clausen unsigned bits_per_channel = ((hdmi_read(sd, 0x0b) & 0x60) >> 4) + 8; 1531d42010a1SLars-Peter Clausen 1532d42010a1SLars-Peter Clausen freq = freq * 8 / bits_per_channel; 1533d42010a1SLars-Peter Clausen } 1534d42010a1SLars-Peter Clausen 1535d42010a1SLars-Peter Clausen return freq; 1536d42010a1SLars-Peter Clausen } 1537d42010a1SLars-Peter Clausen 1538d42010a1SLars-Peter Clausen static unsigned int adv7611_read_hdmi_pixelclock(struct v4l2_subdev *sd) 1539d42010a1SLars-Peter Clausen { 1540d42010a1SLars-Peter Clausen int a, b; 1541d42010a1SLars-Peter Clausen 1542d42010a1SLars-Peter Clausen a = hdmi_read(sd, 0x51); 1543d42010a1SLars-Peter Clausen b = hdmi_read(sd, 0x52); 1544d42010a1SLars-Peter Clausen if (a < 0 || b < 0) 1545d42010a1SLars-Peter Clausen return 0; 1546d42010a1SLars-Peter Clausen return ((a << 1) | (b >> 7)) * 1000000 + (b & 0x7f) * 1000000 / 128; 1547d42010a1SLars-Peter Clausen } 1548d42010a1SLars-Peter Clausen 154954450f59SHans Verkuil static int adv7604_query_dv_timings(struct v4l2_subdev *sd, 155054450f59SHans Verkuil struct v4l2_dv_timings *timings) 155154450f59SHans Verkuil { 155254450f59SHans Verkuil struct adv7604_state *state = to_state(sd); 1553d42010a1SLars-Peter Clausen const struct adv7604_chip_info *info = state->info; 155454450f59SHans Verkuil struct v4l2_bt_timings *bt = &timings->bt; 155554450f59SHans Verkuil struct stdi_readback stdi; 155654450f59SHans Verkuil 155754450f59SHans Verkuil if (!timings) 155854450f59SHans Verkuil return -EINVAL; 155954450f59SHans Verkuil 156054450f59SHans Verkuil memset(timings, 0, sizeof(struct v4l2_dv_timings)); 156154450f59SHans Verkuil 156254450f59SHans Verkuil if (no_signal(sd)) { 15631e0b9156SMartin Bugge state->restart_stdi_once = true; 156454450f59SHans Verkuil v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__); 156554450f59SHans Verkuil return -ENOLINK; 156654450f59SHans Verkuil } 156754450f59SHans Verkuil 156854450f59SHans Verkuil /* read STDI */ 156954450f59SHans Verkuil if (read_stdi(sd, &stdi)) { 157054450f59SHans Verkuil v4l2_dbg(1, debug, sd, "%s: STDI/SSPD not locked\n", __func__); 157154450f59SHans Verkuil return -ENOLINK; 157254450f59SHans Verkuil } 157354450f59SHans Verkuil bt->interlaced = stdi.interlaced ? 157454450f59SHans Verkuil V4L2_DV_INTERLACED : V4L2_DV_PROGRESSIVE; 157554450f59SHans Verkuil 15764a31a93aSMats Randgaard if (is_digital_input(sd)) { 157754450f59SHans Verkuil timings->type = V4L2_DV_BT_656_1120; 157854450f59SHans Verkuil 1579d42010a1SLars-Peter Clausen /* FIXME: All masks are incorrect for ADV7611 */ 158051182a94SLaurent Pinchart bt->width = hdmi_read16(sd, 0x07, 0xfff); 158151182a94SLaurent Pinchart bt->height = hdmi_read16(sd, 0x09, 0xfff); 1582d42010a1SLars-Peter Clausen bt->pixelclock = info->read_hdmi_pixelclock(sd); 158351182a94SLaurent Pinchart bt->hfrontporch = hdmi_read16(sd, 0x20, 0x3ff); 158451182a94SLaurent Pinchart bt->hsync = hdmi_read16(sd, 0x22, 0x3ff); 158551182a94SLaurent Pinchart bt->hbackporch = hdmi_read16(sd, 0x24, 0x3ff); 158651182a94SLaurent Pinchart bt->vfrontporch = hdmi_read16(sd, 0x2a, 0x1fff) / 2; 158751182a94SLaurent Pinchart bt->vsync = hdmi_read16(sd, 0x2e, 0x1fff) / 2; 158851182a94SLaurent Pinchart bt->vbackporch = hdmi_read16(sd, 0x32, 0x1fff) / 2; 158954450f59SHans Verkuil bt->polarities = ((hdmi_read(sd, 0x05) & 0x10) ? V4L2_DV_VSYNC_POS_POL : 0) | 159054450f59SHans Verkuil ((hdmi_read(sd, 0x05) & 0x20) ? V4L2_DV_HSYNC_POS_POL : 0); 159154450f59SHans Verkuil if (bt->interlaced == V4L2_DV_INTERLACED) { 159251182a94SLaurent Pinchart bt->height += hdmi_read16(sd, 0x0b, 0xfff); 159351182a94SLaurent Pinchart bt->il_vfrontporch = hdmi_read16(sd, 0x2c, 0x1fff) / 2; 159451182a94SLaurent Pinchart bt->il_vsync = hdmi_read16(sd, 0x30, 0x1fff) / 2; 159551182a94SLaurent Pinchart bt->vbackporch = hdmi_read16(sd, 0x34, 0x1fff) / 2; 159654450f59SHans Verkuil } 159754450f59SHans Verkuil adv7604_fill_optional_dv_timings_fields(sd, timings); 159854450f59SHans Verkuil } else { 159954450f59SHans Verkuil /* find format 160080939647SHans Verkuil * Since LCVS values are inaccurate [REF_03, p. 275-276], 160154450f59SHans Verkuil * stdi2dv_timings() is called with lcvs +-1 if the first attempt fails. 160254450f59SHans Verkuil */ 160354450f59SHans Verkuil if (!stdi2dv_timings(sd, &stdi, timings)) 160454450f59SHans Verkuil goto found; 160554450f59SHans Verkuil stdi.lcvs += 1; 160654450f59SHans Verkuil v4l2_dbg(1, debug, sd, "%s: lcvs + 1 = %d\n", __func__, stdi.lcvs); 160754450f59SHans Verkuil if (!stdi2dv_timings(sd, &stdi, timings)) 160854450f59SHans Verkuil goto found; 160954450f59SHans Verkuil stdi.lcvs -= 2; 161054450f59SHans Verkuil v4l2_dbg(1, debug, sd, "%s: lcvs - 1 = %d\n", __func__, stdi.lcvs); 161154450f59SHans Verkuil if (stdi2dv_timings(sd, &stdi, timings)) { 1612cf9afb1dSHans Verkuil /* 1613cf9afb1dSHans Verkuil * The STDI block may measure wrong values, especially 1614cf9afb1dSHans Verkuil * for lcvs and lcf. If the driver can not find any 1615cf9afb1dSHans Verkuil * valid timing, the STDI block is restarted to measure 1616cf9afb1dSHans Verkuil * the video timings again. The function will return an 1617cf9afb1dSHans Verkuil * error, but the restart of STDI will generate a new 1618cf9afb1dSHans Verkuil * STDI interrupt and the format detection process will 1619cf9afb1dSHans Verkuil * restart. 1620cf9afb1dSHans Verkuil */ 1621cf9afb1dSHans Verkuil if (state->restart_stdi_once) { 1622cf9afb1dSHans Verkuil v4l2_dbg(1, debug, sd, "%s: restart STDI\n", __func__); 1623cf9afb1dSHans Verkuil /* TODO restart STDI for Sync Channel 2 */ 1624cf9afb1dSHans Verkuil /* enter one-shot mode */ 162522d97e56SLaurent Pinchart cp_write_clr_set(sd, 0x86, 0x06, 0x00); 1626cf9afb1dSHans Verkuil /* trigger STDI restart */ 162722d97e56SLaurent Pinchart cp_write_clr_set(sd, 0x86, 0x06, 0x04); 1628cf9afb1dSHans Verkuil /* reset to continuous mode */ 162922d97e56SLaurent Pinchart cp_write_clr_set(sd, 0x86, 0x06, 0x02); 1630cf9afb1dSHans Verkuil state->restart_stdi_once = false; 1631cf9afb1dSHans Verkuil return -ENOLINK; 1632cf9afb1dSHans Verkuil } 163354450f59SHans Verkuil v4l2_dbg(1, debug, sd, "%s: format not supported\n", __func__); 163454450f59SHans Verkuil return -ERANGE; 163554450f59SHans Verkuil } 1636cf9afb1dSHans Verkuil state->restart_stdi_once = true; 163754450f59SHans Verkuil } 163854450f59SHans Verkuil found: 163954450f59SHans Verkuil 164054450f59SHans Verkuil if (no_signal(sd)) { 164154450f59SHans Verkuil v4l2_dbg(1, debug, sd, "%s: signal lost during readout\n", __func__); 164254450f59SHans Verkuil memset(timings, 0, sizeof(struct v4l2_dv_timings)); 164354450f59SHans Verkuil return -ENOLINK; 164454450f59SHans Verkuil } 164554450f59SHans Verkuil 16464a31a93aSMats Randgaard if ((is_analog_input(sd) && bt->pixelclock > 170000000) || 16474a31a93aSMats Randgaard (is_digital_input(sd) && bt->pixelclock > 225000000)) { 164854450f59SHans Verkuil v4l2_dbg(1, debug, sd, "%s: pixelclock out of range %d\n", 164954450f59SHans Verkuil __func__, (u32)bt->pixelclock); 165054450f59SHans Verkuil return -ERANGE; 165154450f59SHans Verkuil } 165254450f59SHans Verkuil 165354450f59SHans Verkuil if (debug > 1) 165411d034c8SHans Verkuil v4l2_print_dv_timings(sd->name, "adv7604_query_dv_timings: ", 165511d034c8SHans Verkuil timings, true); 165654450f59SHans Verkuil 165754450f59SHans Verkuil return 0; 165854450f59SHans Verkuil } 165954450f59SHans Verkuil 166054450f59SHans Verkuil static int adv7604_s_dv_timings(struct v4l2_subdev *sd, 166154450f59SHans Verkuil struct v4l2_dv_timings *timings) 166254450f59SHans Verkuil { 166354450f59SHans Verkuil struct adv7604_state *state = to_state(sd); 166454450f59SHans Verkuil struct v4l2_bt_timings *bt; 1665ccbd5bc4SHans Verkuil int err; 166654450f59SHans Verkuil 166754450f59SHans Verkuil if (!timings) 166854450f59SHans Verkuil return -EINVAL; 166954450f59SHans Verkuil 1670d48eb48cSMats Randgaard if (v4l2_match_dv_timings(&state->timings, timings, 0)) { 1671d48eb48cSMats Randgaard v4l2_dbg(1, debug, sd, "%s: no change\n", __func__); 1672d48eb48cSMats Randgaard return 0; 1673d48eb48cSMats Randgaard } 1674d48eb48cSMats Randgaard 167554450f59SHans Verkuil bt = &timings->bt; 167654450f59SHans Verkuil 16774a31a93aSMats Randgaard if ((is_analog_input(sd) && bt->pixelclock > 170000000) || 16784a31a93aSMats Randgaard (is_digital_input(sd) && bt->pixelclock > 225000000)) { 167954450f59SHans Verkuil v4l2_dbg(1, debug, sd, "%s: pixelclock out of range %d\n", 168054450f59SHans Verkuil __func__, (u32)bt->pixelclock); 168154450f59SHans Verkuil return -ERANGE; 168254450f59SHans Verkuil } 1683ccbd5bc4SHans Verkuil 168454450f59SHans Verkuil adv7604_fill_optional_dv_timings_fields(sd, timings); 168554450f59SHans Verkuil 168654450f59SHans Verkuil state->timings = *timings; 168754450f59SHans Verkuil 168822d97e56SLaurent Pinchart cp_write_clr_set(sd, 0x91, 0x40, bt->interlaced ? 0x40 : 0x00); 1689ccbd5bc4SHans Verkuil 1690ccbd5bc4SHans Verkuil /* Use prim_mode and vid_std when available */ 1691ccbd5bc4SHans Verkuil err = configure_predefined_video_timings(sd, timings); 1692ccbd5bc4SHans Verkuil if (err) { 1693ccbd5bc4SHans Verkuil /* custom settings when the video format 1694ccbd5bc4SHans Verkuil does not have prim_mode/vid_std */ 1695ccbd5bc4SHans Verkuil configure_custom_video_timings(sd, bt); 1696ccbd5bc4SHans Verkuil } 169754450f59SHans Verkuil 169854450f59SHans Verkuil set_rgb_quantization_range(sd); 169954450f59SHans Verkuil 170054450f59SHans Verkuil if (debug > 1) 170111d034c8SHans Verkuil v4l2_print_dv_timings(sd->name, "adv7604_s_dv_timings: ", 170211d034c8SHans Verkuil timings, true); 170354450f59SHans Verkuil return 0; 170454450f59SHans Verkuil } 170554450f59SHans Verkuil 170654450f59SHans Verkuil static int adv7604_g_dv_timings(struct v4l2_subdev *sd, 170754450f59SHans Verkuil struct v4l2_dv_timings *timings) 170854450f59SHans Verkuil { 170954450f59SHans Verkuil struct adv7604_state *state = to_state(sd); 171054450f59SHans Verkuil 171154450f59SHans Verkuil *timings = state->timings; 171254450f59SHans Verkuil return 0; 171354450f59SHans Verkuil } 171454450f59SHans Verkuil 1715d42010a1SLars-Peter Clausen static void adv7604_set_termination(struct v4l2_subdev *sd, bool enable) 1716d42010a1SLars-Peter Clausen { 1717d42010a1SLars-Peter Clausen hdmi_write(sd, 0x01, enable ? 0x00 : 0x78); 1718d42010a1SLars-Peter Clausen } 1719d42010a1SLars-Peter Clausen 1720d42010a1SLars-Peter Clausen static void adv7611_set_termination(struct v4l2_subdev *sd, bool enable) 1721d42010a1SLars-Peter Clausen { 1722d42010a1SLars-Peter Clausen hdmi_write(sd, 0x83, enable ? 0xfe : 0xff); 1723d42010a1SLars-Peter Clausen } 1724d42010a1SLars-Peter Clausen 17256b0d5d34SHans Verkuil static void enable_input(struct v4l2_subdev *sd) 172654450f59SHans Verkuil { 17276b0d5d34SHans Verkuil struct adv7604_state *state = to_state(sd); 17286b0d5d34SHans Verkuil 17294a31a93aSMats Randgaard if (is_analog_input(sd)) { 173054450f59SHans Verkuil io_write(sd, 0x15, 0xb0); /* Disable Tristate of Pins (no audio) */ 17314a31a93aSMats Randgaard } else if (is_digital_input(sd)) { 173222d97e56SLaurent Pinchart hdmi_write_clr_set(sd, 0x00, 0x03, state->selected_input); 1733d42010a1SLars-Peter Clausen state->info->set_termination(sd, true); 173454450f59SHans Verkuil io_write(sd, 0x15, 0xa0); /* Disable Tristate of Pins */ 173522d97e56SLaurent Pinchart hdmi_write_clr_set(sd, 0x1a, 0x10, 0x00); /* Unmute audio */ 17364a31a93aSMats Randgaard } else { 17374a31a93aSMats Randgaard v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n", 17384a31a93aSMats Randgaard __func__, state->selected_input); 173954450f59SHans Verkuil } 174054450f59SHans Verkuil } 174154450f59SHans Verkuil 174254450f59SHans Verkuil static void disable_input(struct v4l2_subdev *sd) 174354450f59SHans Verkuil { 1744d42010a1SLars-Peter Clausen struct adv7604_state *state = to_state(sd); 1745d42010a1SLars-Peter Clausen 174622d97e56SLaurent Pinchart hdmi_write_clr_set(sd, 0x1a, 0x10, 0x10); /* Mute audio */ 17475474b983SMats Randgaard msleep(16); /* 512 samples with >= 32 kHz sample rate [REF_03, c. 7.16.10] */ 174854450f59SHans Verkuil io_write(sd, 0x15, 0xbe); /* Tristate all outputs from video core */ 1749d42010a1SLars-Peter Clausen state->info->set_termination(sd, false); 175054450f59SHans Verkuil } 175154450f59SHans Verkuil 17526b0d5d34SHans Verkuil static void select_input(struct v4l2_subdev *sd) 175354450f59SHans Verkuil { 17546b0d5d34SHans Verkuil struct adv7604_state *state = to_state(sd); 1755d42010a1SLars-Peter Clausen const struct adv7604_chip_info *info = state->info; 175654450f59SHans Verkuil 17574a31a93aSMats Randgaard if (is_analog_input(sd)) { 1758d42010a1SLars-Peter Clausen adv7604_write_reg_seq(sd, info->recommended_settings[0]); 175954450f59SHans Verkuil 176054450f59SHans Verkuil afe_write(sd, 0x00, 0x08); /* power up ADC */ 176154450f59SHans Verkuil afe_write(sd, 0x01, 0x06); /* power up Analog Front End */ 176254450f59SHans Verkuil afe_write(sd, 0xc8, 0x00); /* phase control */ 17634a31a93aSMats Randgaard } else if (is_digital_input(sd)) { 17644a31a93aSMats Randgaard hdmi_write(sd, 0x00, state->selected_input & 0x03); 176554450f59SHans Verkuil 1766d42010a1SLars-Peter Clausen adv7604_write_reg_seq(sd, info->recommended_settings[1]); 176754450f59SHans Verkuil 1768d42010a1SLars-Peter Clausen if (adv7604_has_afe(state)) { 176954450f59SHans Verkuil afe_write(sd, 0x00, 0xff); /* power down ADC */ 177054450f59SHans Verkuil afe_write(sd, 0x01, 0xfe); /* power down Analog Front End */ 177154450f59SHans Verkuil afe_write(sd, 0xc8, 0x40); /* phase control */ 1772d42010a1SLars-Peter Clausen } 177354450f59SHans Verkuil 177454450f59SHans Verkuil cp_write(sd, 0x3e, 0x00); /* CP core pre-gain control */ 177554450f59SHans Verkuil cp_write(sd, 0xc3, 0x39); /* CP coast control. Graphics mode */ 177654450f59SHans Verkuil cp_write(sd, 0x40, 0x80); /* CP core pre-gain control. Graphics mode */ 17774a31a93aSMats Randgaard } else { 17784a31a93aSMats Randgaard v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n", 17794a31a93aSMats Randgaard __func__, state->selected_input); 178054450f59SHans Verkuil } 178154450f59SHans Verkuil } 178254450f59SHans Verkuil 178354450f59SHans Verkuil static int adv7604_s_routing(struct v4l2_subdev *sd, 178454450f59SHans Verkuil u32 input, u32 output, u32 config) 178554450f59SHans Verkuil { 178654450f59SHans Verkuil struct adv7604_state *state = to_state(sd); 178754450f59SHans Verkuil 1788ff4f80fdSMats Randgaard v4l2_dbg(2, debug, sd, "%s: input %d, selected input %d", 1789ff4f80fdSMats Randgaard __func__, input, state->selected_input); 1790ff4f80fdSMats Randgaard 1791ff4f80fdSMats Randgaard if (input == state->selected_input) 1792ff4f80fdSMats Randgaard return 0; 179354450f59SHans Verkuil 1794d42010a1SLars-Peter Clausen if (input > state->info->max_port) 1795d42010a1SLars-Peter Clausen return -EINVAL; 1796d42010a1SLars-Peter Clausen 17974a31a93aSMats Randgaard state->selected_input = input; 179854450f59SHans Verkuil 179954450f59SHans Verkuil disable_input(sd); 180054450f59SHans Verkuil 18016b0d5d34SHans Verkuil select_input(sd); 180254450f59SHans Verkuil 18036b0d5d34SHans Verkuil enable_input(sd); 180454450f59SHans Verkuil 180554450f59SHans Verkuil return 0; 180654450f59SHans Verkuil } 180754450f59SHans Verkuil 1808539b33b0SLaurent Pinchart static int adv7604_enum_mbus_code(struct v4l2_subdev *sd, 1809539b33b0SLaurent Pinchart struct v4l2_subdev_fh *fh, 1810539b33b0SLaurent Pinchart struct v4l2_subdev_mbus_code_enum *code) 181154450f59SHans Verkuil { 181254450f59SHans Verkuil struct adv7604_state *state = to_state(sd); 181354450f59SHans Verkuil 1814539b33b0SLaurent Pinchart if (code->index >= state->info->nformats) 1815539b33b0SLaurent Pinchart return -EINVAL; 1816539b33b0SLaurent Pinchart 1817539b33b0SLaurent Pinchart code->code = state->info->formats[code->index].code; 1818539b33b0SLaurent Pinchart 1819539b33b0SLaurent Pinchart return 0; 1820539b33b0SLaurent Pinchart } 1821539b33b0SLaurent Pinchart 1822539b33b0SLaurent Pinchart static void adv7604_fill_format(struct adv7604_state *state, 1823539b33b0SLaurent Pinchart struct v4l2_mbus_framefmt *format) 1824539b33b0SLaurent Pinchart { 1825539b33b0SLaurent Pinchart memset(format, 0, sizeof(*format)); 1826539b33b0SLaurent Pinchart 1827539b33b0SLaurent Pinchart format->width = state->timings.bt.width; 1828539b33b0SLaurent Pinchart format->height = state->timings.bt.height; 1829539b33b0SLaurent Pinchart format->field = V4L2_FIELD_NONE; 1830539b33b0SLaurent Pinchart 1831539b33b0SLaurent Pinchart if (state->timings.bt.standards & V4L2_DV_BT_STD_CEA861) 1832539b33b0SLaurent Pinchart format->colorspace = (state->timings.bt.height <= 576) ? 183354450f59SHans Verkuil V4L2_COLORSPACE_SMPTE170M : V4L2_COLORSPACE_REC709; 183454450f59SHans Verkuil } 1835539b33b0SLaurent Pinchart 1836539b33b0SLaurent Pinchart /* 1837539b33b0SLaurent Pinchart * Compute the op_ch_sel value required to obtain on the bus the component order 1838539b33b0SLaurent Pinchart * corresponding to the selected format taking into account bus reordering 1839539b33b0SLaurent Pinchart * applied by the board at the output of the device. 1840539b33b0SLaurent Pinchart * 1841539b33b0SLaurent Pinchart * The following table gives the op_ch_value from the format component order 1842539b33b0SLaurent Pinchart * (expressed as op_ch_sel value in column) and the bus reordering (expressed as 1843539b33b0SLaurent Pinchart * adv7604_bus_order value in row). 1844539b33b0SLaurent Pinchart * 1845539b33b0SLaurent Pinchart * | GBR(0) GRB(1) BGR(2) RGB(3) BRG(4) RBG(5) 1846539b33b0SLaurent Pinchart * ----------+------------------------------------------------- 1847539b33b0SLaurent Pinchart * RGB (NOP) | GBR GRB BGR RGB BRG RBG 1848539b33b0SLaurent Pinchart * GRB (1-2) | BGR RGB GBR GRB RBG BRG 1849539b33b0SLaurent Pinchart * RBG (2-3) | GRB GBR BRG RBG BGR RGB 1850539b33b0SLaurent Pinchart * BGR (1-3) | RBG BRG RGB BGR GRB GBR 1851539b33b0SLaurent Pinchart * BRG (ROR) | BRG RBG GRB GBR RGB BGR 1852539b33b0SLaurent Pinchart * GBR (ROL) | RGB BGR RBG BRG GBR GRB 1853539b33b0SLaurent Pinchart */ 1854539b33b0SLaurent Pinchart static unsigned int adv7604_op_ch_sel(struct adv7604_state *state) 1855539b33b0SLaurent Pinchart { 1856539b33b0SLaurent Pinchart #define _SEL(a,b,c,d,e,f) { \ 1857539b33b0SLaurent Pinchart ADV7604_OP_CH_SEL_##a, ADV7604_OP_CH_SEL_##b, ADV7604_OP_CH_SEL_##c, \ 1858539b33b0SLaurent Pinchart ADV7604_OP_CH_SEL_##d, ADV7604_OP_CH_SEL_##e, ADV7604_OP_CH_SEL_##f } 1859539b33b0SLaurent Pinchart #define _BUS(x) [ADV7604_BUS_ORDER_##x] 1860539b33b0SLaurent Pinchart 1861539b33b0SLaurent Pinchart static const unsigned int op_ch_sel[6][6] = { 1862539b33b0SLaurent Pinchart _BUS(RGB) /* NOP */ = _SEL(GBR, GRB, BGR, RGB, BRG, RBG), 1863539b33b0SLaurent Pinchart _BUS(GRB) /* 1-2 */ = _SEL(BGR, RGB, GBR, GRB, RBG, BRG), 1864539b33b0SLaurent Pinchart _BUS(RBG) /* 2-3 */ = _SEL(GRB, GBR, BRG, RBG, BGR, RGB), 1865539b33b0SLaurent Pinchart _BUS(BGR) /* 1-3 */ = _SEL(RBG, BRG, RGB, BGR, GRB, GBR), 1866539b33b0SLaurent Pinchart _BUS(BRG) /* ROR */ = _SEL(BRG, RBG, GRB, GBR, RGB, BGR), 1867539b33b0SLaurent Pinchart _BUS(GBR) /* ROL */ = _SEL(RGB, BGR, RBG, BRG, GBR, GRB), 1868539b33b0SLaurent Pinchart }; 1869539b33b0SLaurent Pinchart 1870539b33b0SLaurent Pinchart return op_ch_sel[state->pdata.bus_order][state->format->op_ch_sel >> 5]; 1871539b33b0SLaurent Pinchart } 1872539b33b0SLaurent Pinchart 1873539b33b0SLaurent Pinchart static void adv7604_setup_format(struct adv7604_state *state) 1874539b33b0SLaurent Pinchart { 1875539b33b0SLaurent Pinchart struct v4l2_subdev *sd = &state->sd; 1876539b33b0SLaurent Pinchart 187722d97e56SLaurent Pinchart io_write_clr_set(sd, 0x02, 0x02, 1878539b33b0SLaurent Pinchart state->format->rgb_out ? ADV7604_RGB_OUT : 0); 1879539b33b0SLaurent Pinchart io_write(sd, 0x03, state->format->op_format_sel | 1880539b33b0SLaurent Pinchart state->pdata.op_format_mode_sel); 188122d97e56SLaurent Pinchart io_write_clr_set(sd, 0x04, 0xe0, adv7604_op_ch_sel(state)); 188222d97e56SLaurent Pinchart io_write_clr_set(sd, 0x05, 0x01, 1883539b33b0SLaurent Pinchart state->format->swap_cb_cr ? ADV7604_OP_SWAP_CB_CR : 0); 1884539b33b0SLaurent Pinchart } 1885539b33b0SLaurent Pinchart 1886539b33b0SLaurent Pinchart static int adv7604_get_format(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh, 1887539b33b0SLaurent Pinchart struct v4l2_subdev_format *format) 1888539b33b0SLaurent Pinchart { 1889539b33b0SLaurent Pinchart struct adv7604_state *state = to_state(sd); 1890539b33b0SLaurent Pinchart 1891539b33b0SLaurent Pinchart if (format->pad != state->source_pad) 1892539b33b0SLaurent Pinchart return -EINVAL; 1893539b33b0SLaurent Pinchart 1894539b33b0SLaurent Pinchart adv7604_fill_format(state, &format->format); 1895539b33b0SLaurent Pinchart 1896539b33b0SLaurent Pinchart if (format->which == V4L2_SUBDEV_FORMAT_TRY) { 1897539b33b0SLaurent Pinchart struct v4l2_mbus_framefmt *fmt; 1898539b33b0SLaurent Pinchart 1899539b33b0SLaurent Pinchart fmt = v4l2_subdev_get_try_format(fh, format->pad); 1900539b33b0SLaurent Pinchart format->format.code = fmt->code; 1901539b33b0SLaurent Pinchart } else { 1902539b33b0SLaurent Pinchart format->format.code = state->format->code; 1903539b33b0SLaurent Pinchart } 1904539b33b0SLaurent Pinchart 1905539b33b0SLaurent Pinchart return 0; 1906539b33b0SLaurent Pinchart } 1907539b33b0SLaurent Pinchart 1908539b33b0SLaurent Pinchart static int adv7604_set_format(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh, 1909539b33b0SLaurent Pinchart struct v4l2_subdev_format *format) 1910539b33b0SLaurent Pinchart { 1911539b33b0SLaurent Pinchart struct adv7604_state *state = to_state(sd); 1912539b33b0SLaurent Pinchart const struct adv7604_format_info *info; 1913539b33b0SLaurent Pinchart 1914539b33b0SLaurent Pinchart if (format->pad != state->source_pad) 1915539b33b0SLaurent Pinchart return -EINVAL; 1916539b33b0SLaurent Pinchart 1917539b33b0SLaurent Pinchart info = adv7604_format_info(state, format->format.code); 1918539b33b0SLaurent Pinchart if (info == NULL) 1919539b33b0SLaurent Pinchart info = adv7604_format_info(state, V4L2_MBUS_FMT_YUYV8_2X8); 1920539b33b0SLaurent Pinchart 1921539b33b0SLaurent Pinchart adv7604_fill_format(state, &format->format); 1922539b33b0SLaurent Pinchart format->format.code = info->code; 1923539b33b0SLaurent Pinchart 1924539b33b0SLaurent Pinchart if (format->which == V4L2_SUBDEV_FORMAT_TRY) { 1925539b33b0SLaurent Pinchart struct v4l2_mbus_framefmt *fmt; 1926539b33b0SLaurent Pinchart 1927539b33b0SLaurent Pinchart fmt = v4l2_subdev_get_try_format(fh, format->pad); 1928539b33b0SLaurent Pinchart fmt->code = format->format.code; 1929539b33b0SLaurent Pinchart } else { 1930539b33b0SLaurent Pinchart state->format = info; 1931539b33b0SLaurent Pinchart adv7604_setup_format(state); 1932539b33b0SLaurent Pinchart } 1933539b33b0SLaurent Pinchart 193454450f59SHans Verkuil return 0; 193554450f59SHans Verkuil } 193654450f59SHans Verkuil 193754450f59SHans Verkuil static int adv7604_isr(struct v4l2_subdev *sd, u32 status, bool *handled) 193854450f59SHans Verkuil { 1939d42010a1SLars-Peter Clausen struct adv7604_state *state = to_state(sd); 1940d42010a1SLars-Peter Clausen const struct adv7604_chip_info *info = state->info; 1941f24d229cSMats Randgaard const u8 irq_reg_0x43 = io_read(sd, 0x43); 1942f24d229cSMats Randgaard const u8 irq_reg_0x6b = io_read(sd, 0x6b); 1943f24d229cSMats Randgaard const u8 irq_reg_0x70 = io_read(sd, 0x70); 1944f24d229cSMats Randgaard u8 fmt_change_digital; 1945f24d229cSMats Randgaard u8 fmt_change; 1946f24d229cSMats Randgaard u8 tx_5v; 1947f24d229cSMats Randgaard 1948f24d229cSMats Randgaard if (irq_reg_0x43) 1949f24d229cSMats Randgaard io_write(sd, 0x44, irq_reg_0x43); 1950f24d229cSMats Randgaard if (irq_reg_0x70) 1951f24d229cSMats Randgaard io_write(sd, 0x71, irq_reg_0x70); 1952f24d229cSMats Randgaard if (irq_reg_0x6b) 1953f24d229cSMats Randgaard io_write(sd, 0x6c, irq_reg_0x6b); 195454450f59SHans Verkuil 1955ff4f80fdSMats Randgaard v4l2_dbg(2, debug, sd, "%s: ", __func__); 1956ff4f80fdSMats Randgaard 195754450f59SHans Verkuil /* format change */ 1958f24d229cSMats Randgaard fmt_change = irq_reg_0x43 & 0x98; 1959d42010a1SLars-Peter Clausen fmt_change_digital = is_digital_input(sd) 1960d42010a1SLars-Peter Clausen ? irq_reg_0x6b & info->fmt_change_digital_mask 1961d42010a1SLars-Peter Clausen : 0; 196214d03233SMats Randgaard 196354450f59SHans Verkuil if (fmt_change || fmt_change_digital) { 196454450f59SHans Verkuil v4l2_dbg(1, debug, sd, 196525a64ac9SMats Randgaard "%s: fmt_change = 0x%x, fmt_change_digital = 0x%x\n", 196654450f59SHans Verkuil __func__, fmt_change, fmt_change_digital); 196725a64ac9SMats Randgaard 196854450f59SHans Verkuil v4l2_subdev_notify(sd, ADV7604_FMT_CHANGE, NULL); 196925a64ac9SMats Randgaard 197054450f59SHans Verkuil if (handled) 197154450f59SHans Verkuil *handled = true; 197254450f59SHans Verkuil } 1973f24d229cSMats Randgaard /* HDMI/DVI mode */ 1974f24d229cSMats Randgaard if (irq_reg_0x6b & 0x01) { 1975f24d229cSMats Randgaard v4l2_dbg(1, debug, sd, "%s: irq %s mode\n", __func__, 1976f24d229cSMats Randgaard (io_read(sd, 0x6a) & 0x01) ? "HDMI" : "DVI"); 1977f24d229cSMats Randgaard set_rgb_quantization_range(sd); 1978f24d229cSMats Randgaard if (handled) 1979f24d229cSMats Randgaard *handled = true; 1980f24d229cSMats Randgaard } 1981f24d229cSMats Randgaard 198254450f59SHans Verkuil /* tx 5v detect */ 1983d42010a1SLars-Peter Clausen tx_5v = io_read(sd, 0x70) & info->cable_det_mask; 198454450f59SHans Verkuil if (tx_5v) { 198554450f59SHans Verkuil v4l2_dbg(1, debug, sd, "%s: tx_5v: 0x%x\n", __func__, tx_5v); 198654450f59SHans Verkuil io_write(sd, 0x71, tx_5v); 198754450f59SHans Verkuil adv7604_s_detect_tx_5v_ctrl(sd); 198854450f59SHans Verkuil if (handled) 198954450f59SHans Verkuil *handled = true; 199054450f59SHans Verkuil } 199154450f59SHans Verkuil return 0; 199254450f59SHans Verkuil } 199354450f59SHans Verkuil 1994b09dfac8SHans Verkuil static int adv7604_get_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid) 199554450f59SHans Verkuil { 199654450f59SHans Verkuil struct adv7604_state *state = to_state(sd); 19974a31a93aSMats Randgaard u8 *data = NULL; 199854450f59SHans Verkuil 1999c784b1e2SLaurent Pinchart if (edid->pad > ADV7604_PAD_HDMI_PORT_D) 200054450f59SHans Verkuil return -EINVAL; 200154450f59SHans Verkuil if (edid->blocks == 0) 200254450f59SHans Verkuil return -EINVAL; 20034a31a93aSMats Randgaard if (edid->blocks > 2) 200454450f59SHans Verkuil return -EINVAL; 20054a31a93aSMats Randgaard if (edid->start_block > 1) 20064a31a93aSMats Randgaard return -EINVAL; 20074a31a93aSMats Randgaard if (edid->start_block == 1) 20084a31a93aSMats Randgaard edid->blocks = 1; 20094a31a93aSMats Randgaard 20104a31a93aSMats Randgaard if (edid->blocks > state->edid.blocks) 20114a31a93aSMats Randgaard edid->blocks = state->edid.blocks; 20124a31a93aSMats Randgaard 20134a31a93aSMats Randgaard switch (edid->pad) { 2014c784b1e2SLaurent Pinchart case ADV7604_PAD_HDMI_PORT_A: 2015c784b1e2SLaurent Pinchart case ADV7604_PAD_HDMI_PORT_B: 2016c784b1e2SLaurent Pinchart case ADV7604_PAD_HDMI_PORT_C: 2017c784b1e2SLaurent Pinchart case ADV7604_PAD_HDMI_PORT_D: 20184a31a93aSMats Randgaard if (state->edid.present & (1 << edid->pad)) 20194a31a93aSMats Randgaard data = state->edid.edid; 20204a31a93aSMats Randgaard break; 20214a31a93aSMats Randgaard default: 20224a31a93aSMats Randgaard return -EINVAL; 20234a31a93aSMats Randgaard break; 20244a31a93aSMats Randgaard } 20254a31a93aSMats Randgaard if (!data) 20264a31a93aSMats Randgaard return -ENODATA; 20274a31a93aSMats Randgaard 20284a31a93aSMats Randgaard memcpy(edid->edid, 20294a31a93aSMats Randgaard data + edid->start_block * 128, 203054450f59SHans Verkuil edid->blocks * 128); 203154450f59SHans Verkuil return 0; 203254450f59SHans Verkuil } 203354450f59SHans Verkuil 2034dd08beb9SMats Randgaard static int get_edid_spa_location(const u8 *edid) 20353e86aa85SMats Randgaard { 20363e86aa85SMats Randgaard u8 d; 20373e86aa85SMats Randgaard 20383e86aa85SMats Randgaard if ((edid[0x7e] != 1) || 20393e86aa85SMats Randgaard (edid[0x80] != 0x02) || 20403e86aa85SMats Randgaard (edid[0x81] != 0x03)) { 20413e86aa85SMats Randgaard return -1; 20423e86aa85SMats Randgaard } 20433e86aa85SMats Randgaard 20443e86aa85SMats Randgaard /* search Vendor Specific Data Block (tag 3) */ 20453e86aa85SMats Randgaard d = edid[0x82] & 0x7f; 20463e86aa85SMats Randgaard if (d > 4) { 20473e86aa85SMats Randgaard int i = 0x84; 20483e86aa85SMats Randgaard int end = 0x80 + d; 20493e86aa85SMats Randgaard 20503e86aa85SMats Randgaard do { 20513e86aa85SMats Randgaard u8 tag = edid[i] >> 5; 20523e86aa85SMats Randgaard u8 len = edid[i] & 0x1f; 20533e86aa85SMats Randgaard 20543e86aa85SMats Randgaard if ((tag == 3) && (len >= 5)) 20553e86aa85SMats Randgaard return i + 4; 20563e86aa85SMats Randgaard i += len + 1; 20573e86aa85SMats Randgaard } while (i < end); 20583e86aa85SMats Randgaard } 20593e86aa85SMats Randgaard return -1; 20603e86aa85SMats Randgaard } 20613e86aa85SMats Randgaard 2062b09dfac8SHans Verkuil static int adv7604_set_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid) 206354450f59SHans Verkuil { 206454450f59SHans Verkuil struct adv7604_state *state = to_state(sd); 2065d42010a1SLars-Peter Clausen const struct adv7604_chip_info *info = state->info; 2066dd08beb9SMats Randgaard int spa_loc; 206754450f59SHans Verkuil int err; 2068dd08beb9SMats Randgaard int i; 206954450f59SHans Verkuil 2070c784b1e2SLaurent Pinchart if (edid->pad > ADV7604_PAD_HDMI_PORT_D) 207154450f59SHans Verkuil return -EINVAL; 207254450f59SHans Verkuil if (edid->start_block != 0) 207354450f59SHans Verkuil return -EINVAL; 207454450f59SHans Verkuil if (edid->blocks == 0) { 20753e86aa85SMats Randgaard /* Disable hotplug and I2C access to EDID RAM from DDC port */ 20764a31a93aSMats Randgaard state->edid.present &= ~(1 << edid->pad); 2077e9d50e9eSLaurent Pinchart adv7604_set_hpd(state, state->edid.present); 207822d97e56SLaurent Pinchart rep_write_clr_set(sd, info->edid_enable_reg, 0x0f, state->edid.present); 20793e86aa85SMats Randgaard 208054450f59SHans Verkuil /* Fall back to a 16:9 aspect ratio */ 208154450f59SHans Verkuil state->aspect_ratio.numerator = 16; 208254450f59SHans Verkuil state->aspect_ratio.denominator = 9; 20833e86aa85SMats Randgaard 20843e86aa85SMats Randgaard if (!state->edid.present) 20853e86aa85SMats Randgaard state->edid.blocks = 0; 20863e86aa85SMats Randgaard 20873e86aa85SMats Randgaard v4l2_dbg(2, debug, sd, "%s: clear EDID pad %d, edid.present = 0x%x\n", 20883e86aa85SMats Randgaard __func__, edid->pad, state->edid.present); 208954450f59SHans Verkuil return 0; 209054450f59SHans Verkuil } 20914a31a93aSMats Randgaard if (edid->blocks > 2) { 20924a31a93aSMats Randgaard edid->blocks = 2; 209354450f59SHans Verkuil return -E2BIG; 20944a31a93aSMats Randgaard } 20954a31a93aSMats Randgaard 2096dd08beb9SMats Randgaard v4l2_dbg(2, debug, sd, "%s: write EDID pad %d, edid.present = 0x%x\n", 2097dd08beb9SMats Randgaard __func__, edid->pad, state->edid.present); 2098dd08beb9SMats Randgaard 20993e86aa85SMats Randgaard /* Disable hotplug and I2C access to EDID RAM from DDC port */ 21004a31a93aSMats Randgaard cancel_delayed_work_sync(&state->delayed_work_enable_hotplug); 2101e9d50e9eSLaurent Pinchart adv7604_set_hpd(state, 0); 210222d97e56SLaurent Pinchart rep_write_clr_set(sd, info->edid_enable_reg, 0x0f, 0x00); 21033e86aa85SMats Randgaard 2104dd08beb9SMats Randgaard spa_loc = get_edid_spa_location(edid->edid); 2105dd08beb9SMats Randgaard if (spa_loc < 0) 2106dd08beb9SMats Randgaard spa_loc = 0xc0; /* Default value [REF_02, p. 116] */ 2107dd08beb9SMats Randgaard 21083e86aa85SMats Randgaard switch (edid->pad) { 2109c784b1e2SLaurent Pinchart case ADV7604_PAD_HDMI_PORT_A: 2110dd08beb9SMats Randgaard state->spa_port_a[0] = edid->edid[spa_loc]; 2111dd08beb9SMats Randgaard state->spa_port_a[1] = edid->edid[spa_loc + 1]; 21123e86aa85SMats Randgaard break; 2113c784b1e2SLaurent Pinchart case ADV7604_PAD_HDMI_PORT_B: 2114dd08beb9SMats Randgaard rep_write(sd, 0x70, edid->edid[spa_loc]); 2115dd08beb9SMats Randgaard rep_write(sd, 0x71, edid->edid[spa_loc + 1]); 21163e86aa85SMats Randgaard break; 2117c784b1e2SLaurent Pinchart case ADV7604_PAD_HDMI_PORT_C: 2118dd08beb9SMats Randgaard rep_write(sd, 0x72, edid->edid[spa_loc]); 2119dd08beb9SMats Randgaard rep_write(sd, 0x73, edid->edid[spa_loc + 1]); 21203e86aa85SMats Randgaard break; 2121c784b1e2SLaurent Pinchart case ADV7604_PAD_HDMI_PORT_D: 2122dd08beb9SMats Randgaard rep_write(sd, 0x74, edid->edid[spa_loc]); 2123dd08beb9SMats Randgaard rep_write(sd, 0x75, edid->edid[spa_loc + 1]); 21243e86aa85SMats Randgaard break; 2125dd08beb9SMats Randgaard default: 2126dd08beb9SMats Randgaard return -EINVAL; 21273e86aa85SMats Randgaard } 2128d42010a1SLars-Peter Clausen 2129d42010a1SLars-Peter Clausen if (info->type == ADV7604) { 2130dd08beb9SMats Randgaard rep_write(sd, 0x76, spa_loc & 0xff); 213122d97e56SLaurent Pinchart rep_write_clr_set(sd, 0x77, 0x40, (spa_loc & 0x100) >> 2); 2132d42010a1SLars-Peter Clausen } else { 2133d42010a1SLars-Peter Clausen /* FIXME: Where is the SPA location LSB register ? */ 213422d97e56SLaurent Pinchart rep_write_clr_set(sd, 0x71, 0x01, (spa_loc & 0x100) >> 8); 2135d42010a1SLars-Peter Clausen } 21363e86aa85SMats Randgaard 2137dd08beb9SMats Randgaard edid->edid[spa_loc] = state->spa_port_a[0]; 2138dd08beb9SMats Randgaard edid->edid[spa_loc + 1] = state->spa_port_a[1]; 21394a31a93aSMats Randgaard 21404a31a93aSMats Randgaard memcpy(state->edid.edid, edid->edid, 128 * edid->blocks); 21414a31a93aSMats Randgaard state->edid.blocks = edid->blocks; 214254450f59SHans Verkuil state->aspect_ratio = v4l2_calc_aspect_ratio(edid->edid[0x15], 214354450f59SHans Verkuil edid->edid[0x16]); 21443e86aa85SMats Randgaard state->edid.present |= 1 << edid->pad; 21454a31a93aSMats Randgaard 21464a31a93aSMats Randgaard err = edid_write_block(sd, 128 * edid->blocks, state->edid.edid); 21474a31a93aSMats Randgaard if (err < 0) { 21483e86aa85SMats Randgaard v4l2_err(sd, "error %d writing edid pad %d\n", err, edid->pad); 214954450f59SHans Verkuil return err; 215054450f59SHans Verkuil } 215154450f59SHans Verkuil 2152dd08beb9SMats Randgaard /* adv7604 calculates the checksums and enables I2C access to internal 2153dd08beb9SMats Randgaard EDID RAM from DDC port. */ 215422d97e56SLaurent Pinchart rep_write_clr_set(sd, info->edid_enable_reg, 0x0f, state->edid.present); 2155dd08beb9SMats Randgaard 2156dd08beb9SMats Randgaard for (i = 0; i < 1000; i++) { 2157d42010a1SLars-Peter Clausen if (rep_read(sd, info->edid_status_reg) & state->edid.present) 2158dd08beb9SMats Randgaard break; 2159dd08beb9SMats Randgaard mdelay(1); 2160dd08beb9SMats Randgaard } 2161dd08beb9SMats Randgaard if (i == 1000) { 2162dd08beb9SMats Randgaard v4l2_err(sd, "error enabling edid (0x%x)\n", state->edid.present); 2163dd08beb9SMats Randgaard return -EIO; 2164dd08beb9SMats Randgaard } 2165dd08beb9SMats Randgaard 2166dd08beb9SMats Randgaard 21674a31a93aSMats Randgaard /* enable hotplug after 100 ms */ 21684a31a93aSMats Randgaard queue_delayed_work(state->work_queues, 21694a31a93aSMats Randgaard &state->delayed_work_enable_hotplug, HZ / 10); 21704a31a93aSMats Randgaard return 0; 21714a31a93aSMats Randgaard } 21724a31a93aSMats Randgaard 217354450f59SHans Verkuil /*********** avi info frame CEA-861-E **************/ 217454450f59SHans Verkuil 217554450f59SHans Verkuil static void print_avi_infoframe(struct v4l2_subdev *sd) 217654450f59SHans Verkuil { 217754450f59SHans Verkuil int i; 217854450f59SHans Verkuil u8 buf[14]; 217954450f59SHans Verkuil u8 avi_len; 218054450f59SHans Verkuil u8 avi_ver; 218154450f59SHans Verkuil 2182bb88f325SMartin Bugge if (!is_hdmi(sd)) { 218354450f59SHans Verkuil v4l2_info(sd, "receive DVI-D signal (AVI infoframe not supported)\n"); 218454450f59SHans Verkuil return; 218554450f59SHans Verkuil } 218654450f59SHans Verkuil if (!(io_read(sd, 0x60) & 0x01)) { 218754450f59SHans Verkuil v4l2_info(sd, "AVI infoframe not received\n"); 218854450f59SHans Verkuil return; 218954450f59SHans Verkuil } 219054450f59SHans Verkuil 219154450f59SHans Verkuil if (io_read(sd, 0x83) & 0x01) { 219254450f59SHans Verkuil v4l2_info(sd, "AVI infoframe checksum error has occurred earlier\n"); 219354450f59SHans Verkuil io_write(sd, 0x85, 0x01); /* clear AVI_INF_CKS_ERR_RAW */ 219454450f59SHans Verkuil if (io_read(sd, 0x83) & 0x01) { 219554450f59SHans Verkuil v4l2_info(sd, "AVI infoframe checksum error still present\n"); 219654450f59SHans Verkuil io_write(sd, 0x85, 0x01); /* clear AVI_INF_CKS_ERR_RAW */ 219754450f59SHans Verkuil } 219854450f59SHans Verkuil } 219954450f59SHans Verkuil 220054450f59SHans Verkuil avi_len = infoframe_read(sd, 0xe2); 220154450f59SHans Verkuil avi_ver = infoframe_read(sd, 0xe1); 220254450f59SHans Verkuil v4l2_info(sd, "AVI infoframe version %d (%d byte)\n", 220354450f59SHans Verkuil avi_ver, avi_len); 220454450f59SHans Verkuil 220554450f59SHans Verkuil if (avi_ver != 0x02) 220654450f59SHans Verkuil return; 220754450f59SHans Verkuil 220854450f59SHans Verkuil for (i = 0; i < 14; i++) 220954450f59SHans Verkuil buf[i] = infoframe_read(sd, i); 221054450f59SHans Verkuil 221154450f59SHans Verkuil v4l2_info(sd, 221254450f59SHans Verkuil "\t%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n", 221354450f59SHans Verkuil buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6], buf[7], 221454450f59SHans Verkuil buf[8], buf[9], buf[10], buf[11], buf[12], buf[13]); 221554450f59SHans Verkuil } 221654450f59SHans Verkuil 221754450f59SHans Verkuil static int adv7604_log_status(struct v4l2_subdev *sd) 221854450f59SHans Verkuil { 221954450f59SHans Verkuil struct adv7604_state *state = to_state(sd); 2220d42010a1SLars-Peter Clausen const struct adv7604_chip_info *info = state->info; 222154450f59SHans Verkuil struct v4l2_dv_timings timings; 222254450f59SHans Verkuil struct stdi_readback stdi; 222354450f59SHans Verkuil u8 reg_io_0x02 = io_read(sd, 0x02); 22244a2ccdd2SLaurent Pinchart u8 edid_enabled; 22254a2ccdd2SLaurent Pinchart u8 cable_det; 222654450f59SHans Verkuil 2227f216ccb3SLars-Peter Clausen static const char * const csc_coeff_sel_rb[16] = { 222854450f59SHans Verkuil "bypassed", "YPbPr601 -> RGB", "reserved", "YPbPr709 -> RGB", 222954450f59SHans Verkuil "reserved", "RGB -> YPbPr601", "reserved", "RGB -> YPbPr709", 223054450f59SHans Verkuil "reserved", "YPbPr709 -> YPbPr601", "YPbPr601 -> YPbPr709", 223154450f59SHans Verkuil "reserved", "reserved", "reserved", "reserved", "manual" 223254450f59SHans Verkuil }; 2233f216ccb3SLars-Peter Clausen static const char * const input_color_space_txt[16] = { 223454450f59SHans Verkuil "RGB limited range (16-235)", "RGB full range (0-255)", 223554450f59SHans Verkuil "YCbCr Bt.601 (16-235)", "YCbCr Bt.709 (16-235)", 22369833239eSMats Randgaard "xvYCC Bt.601", "xvYCC Bt.709", 223754450f59SHans Verkuil "YCbCr Bt.601 (0-255)", "YCbCr Bt.709 (0-255)", 223854450f59SHans Verkuil "invalid", "invalid", "invalid", "invalid", "invalid", 223954450f59SHans Verkuil "invalid", "invalid", "automatic" 224054450f59SHans Verkuil }; 2241f216ccb3SLars-Peter Clausen static const char * const rgb_quantization_range_txt[] = { 224254450f59SHans Verkuil "Automatic", 224354450f59SHans Verkuil "RGB limited range (16-235)", 224454450f59SHans Verkuil "RGB full range (0-255)", 224554450f59SHans Verkuil }; 2246f216ccb3SLars-Peter Clausen static const char * const deep_color_mode_txt[4] = { 2247bb88f325SMartin Bugge "8-bits per channel", 2248bb88f325SMartin Bugge "10-bits per channel", 2249bb88f325SMartin Bugge "12-bits per channel", 2250bb88f325SMartin Bugge "16-bits per channel (not supported)" 2251bb88f325SMartin Bugge }; 225254450f59SHans Verkuil 225354450f59SHans Verkuil v4l2_info(sd, "-----Chip status-----\n"); 225454450f59SHans Verkuil v4l2_info(sd, "Chip power: %s\n", no_power(sd) ? "off" : "on"); 2255d42010a1SLars-Peter Clausen edid_enabled = rep_read(sd, info->edid_status_reg); 22564a31a93aSMats Randgaard v4l2_info(sd, "EDID enabled port A: %s, B: %s, C: %s, D: %s\n", 22574a2ccdd2SLaurent Pinchart ((edid_enabled & 0x01) ? "Yes" : "No"), 22584a2ccdd2SLaurent Pinchart ((edid_enabled & 0x02) ? "Yes" : "No"), 22594a2ccdd2SLaurent Pinchart ((edid_enabled & 0x04) ? "Yes" : "No"), 22604a2ccdd2SLaurent Pinchart ((edid_enabled & 0x08) ? "Yes" : "No")); 226154450f59SHans Verkuil v4l2_info(sd, "CEC: %s\n", !!(cec_read(sd, 0x2a) & 0x01) ? 226254450f59SHans Verkuil "enabled" : "disabled"); 226354450f59SHans Verkuil 226454450f59SHans Verkuil v4l2_info(sd, "-----Signal status-----\n"); 2265d42010a1SLars-Peter Clausen cable_det = info->read_cable_det(sd); 22664a31a93aSMats Randgaard v4l2_info(sd, "Cable detected (+5V power) port A: %s, B: %s, C: %s, D: %s\n", 2267d42010a1SLars-Peter Clausen ((cable_det & 0x01) ? "Yes" : "No"), 2268d42010a1SLars-Peter Clausen ((cable_det & 0x02) ? "Yes" : "No"), 22694a2ccdd2SLaurent Pinchart ((cable_det & 0x04) ? "Yes" : "No"), 2270d42010a1SLars-Peter Clausen ((cable_det & 0x08) ? "Yes" : "No")); 227154450f59SHans Verkuil v4l2_info(sd, "TMDS signal detected: %s\n", 227254450f59SHans Verkuil no_signal_tmds(sd) ? "false" : "true"); 227354450f59SHans Verkuil v4l2_info(sd, "TMDS signal locked: %s\n", 227454450f59SHans Verkuil no_lock_tmds(sd) ? "false" : "true"); 227554450f59SHans Verkuil v4l2_info(sd, "SSPD locked: %s\n", no_lock_sspd(sd) ? "false" : "true"); 227654450f59SHans Verkuil v4l2_info(sd, "STDI locked: %s\n", no_lock_stdi(sd) ? "false" : "true"); 227754450f59SHans Verkuil v4l2_info(sd, "CP locked: %s\n", no_lock_cp(sd) ? "false" : "true"); 227854450f59SHans Verkuil v4l2_info(sd, "CP free run: %s\n", 227954450f59SHans Verkuil (!!(cp_read(sd, 0xff) & 0x10) ? "on" : "off")); 2280ccbd5bc4SHans Verkuil v4l2_info(sd, "Prim-mode = 0x%x, video std = 0x%x, v_freq = 0x%x\n", 2281ccbd5bc4SHans Verkuil io_read(sd, 0x01) & 0x0f, io_read(sd, 0x00) & 0x3f, 2282ccbd5bc4SHans Verkuil (io_read(sd, 0x01) & 0x70) >> 4); 228354450f59SHans Verkuil 228454450f59SHans Verkuil v4l2_info(sd, "-----Video Timings-----\n"); 228554450f59SHans Verkuil if (read_stdi(sd, &stdi)) 228654450f59SHans Verkuil v4l2_info(sd, "STDI: not locked\n"); 228754450f59SHans Verkuil else 228854450f59SHans Verkuil v4l2_info(sd, "STDI: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %s, %chsync, %cvsync\n", 228954450f59SHans Verkuil stdi.lcf, stdi.bl, stdi.lcvs, 229054450f59SHans Verkuil stdi.interlaced ? "interlaced" : "progressive", 229154450f59SHans Verkuil stdi.hs_pol, stdi.vs_pol); 229254450f59SHans Verkuil if (adv7604_query_dv_timings(sd, &timings)) 229354450f59SHans Verkuil v4l2_info(sd, "No video detected\n"); 229454450f59SHans Verkuil else 229511d034c8SHans Verkuil v4l2_print_dv_timings(sd->name, "Detected format: ", 229611d034c8SHans Verkuil &timings, true); 229711d034c8SHans Verkuil v4l2_print_dv_timings(sd->name, "Configured format: ", 229811d034c8SHans Verkuil &state->timings, true); 229954450f59SHans Verkuil 230076eb2d30SMats Randgaard if (no_signal(sd)) 230176eb2d30SMats Randgaard return 0; 230276eb2d30SMats Randgaard 230354450f59SHans Verkuil v4l2_info(sd, "-----Color space-----\n"); 230454450f59SHans Verkuil v4l2_info(sd, "RGB quantization range ctrl: %s\n", 230554450f59SHans Verkuil rgb_quantization_range_txt[state->rgb_quantization_range]); 230654450f59SHans Verkuil v4l2_info(sd, "Input color space: %s\n", 230754450f59SHans Verkuil input_color_space_txt[reg_io_0x02 >> 4]); 230854450f59SHans Verkuil v4l2_info(sd, "Output color space: %s %s, saturator %s\n", 230954450f59SHans Verkuil (reg_io_0x02 & 0x02) ? "RGB" : "YCbCr", 231054450f59SHans Verkuil (reg_io_0x02 & 0x04) ? "(16-235)" : "(0-255)", 231154450f59SHans Verkuil ((reg_io_0x02 & 0x04) ^ (reg_io_0x02 & 0x01)) ? 231254450f59SHans Verkuil "enabled" : "disabled"); 231354450f59SHans Verkuil v4l2_info(sd, "Color space conversion: %s\n", 231454450f59SHans Verkuil csc_coeff_sel_rb[cp_read(sd, 0xfc) >> 4]); 231554450f59SHans Verkuil 23164a31a93aSMats Randgaard if (!is_digital_input(sd)) 231776eb2d30SMats Randgaard return 0; 231876eb2d30SMats Randgaard 231976eb2d30SMats Randgaard v4l2_info(sd, "-----%s status-----\n", is_hdmi(sd) ? "HDMI" : "DVI-D"); 23204a31a93aSMats Randgaard v4l2_info(sd, "Digital video port selected: %c\n", 23214a31a93aSMats Randgaard (hdmi_read(sd, 0x00) & 0x03) + 'A'); 23224a31a93aSMats Randgaard v4l2_info(sd, "HDCP encrypted content: %s\n", 23234a31a93aSMats Randgaard (hdmi_read(sd, 0x05) & 0x40) ? "true" : "false"); 232476eb2d30SMats Randgaard v4l2_info(sd, "HDCP keys read: %s%s\n", 232576eb2d30SMats Randgaard (hdmi_read(sd, 0x04) & 0x20) ? "yes" : "no", 232676eb2d30SMats Randgaard (hdmi_read(sd, 0x04) & 0x10) ? "ERROR" : ""); 232776eb2d30SMats Randgaard if (!is_hdmi(sd)) { 232876eb2d30SMats Randgaard bool audio_pll_locked = hdmi_read(sd, 0x04) & 0x01; 232976eb2d30SMats Randgaard bool audio_sample_packet_detect = hdmi_read(sd, 0x18) & 0x01; 233076eb2d30SMats Randgaard bool audio_mute = io_read(sd, 0x65) & 0x40; 233176eb2d30SMats Randgaard 233276eb2d30SMats Randgaard v4l2_info(sd, "Audio: pll %s, samples %s, %s\n", 233376eb2d30SMats Randgaard audio_pll_locked ? "locked" : "not locked", 233476eb2d30SMats Randgaard audio_sample_packet_detect ? "detected" : "not detected", 233576eb2d30SMats Randgaard audio_mute ? "muted" : "enabled"); 233676eb2d30SMats Randgaard if (audio_pll_locked && audio_sample_packet_detect) { 233776eb2d30SMats Randgaard v4l2_info(sd, "Audio format: %s\n", 233876eb2d30SMats Randgaard (hdmi_read(sd, 0x07) & 0x20) ? "multi-channel" : "stereo"); 233976eb2d30SMats Randgaard } 234076eb2d30SMats Randgaard v4l2_info(sd, "Audio CTS: %u\n", (hdmi_read(sd, 0x5b) << 12) + 234176eb2d30SMats Randgaard (hdmi_read(sd, 0x5c) << 8) + 234276eb2d30SMats Randgaard (hdmi_read(sd, 0x5d) & 0xf0)); 234376eb2d30SMats Randgaard v4l2_info(sd, "Audio N: %u\n", ((hdmi_read(sd, 0x5d) & 0x0f) << 16) + 234476eb2d30SMats Randgaard (hdmi_read(sd, 0x5e) << 8) + 234576eb2d30SMats Randgaard hdmi_read(sd, 0x5f)); 234676eb2d30SMats Randgaard v4l2_info(sd, "AV Mute: %s\n", (hdmi_read(sd, 0x04) & 0x40) ? "on" : "off"); 234776eb2d30SMats Randgaard 234876eb2d30SMats Randgaard v4l2_info(sd, "Deep color mode: %s\n", deep_color_mode_txt[(hdmi_read(sd, 0x0b) & 0x60) >> 5]); 234976eb2d30SMats Randgaard 235054450f59SHans Verkuil print_avi_infoframe(sd); 235154450f59SHans Verkuil } 235254450f59SHans Verkuil 235354450f59SHans Verkuil return 0; 235454450f59SHans Verkuil } 235554450f59SHans Verkuil 235654450f59SHans Verkuil /* ----------------------------------------------------------------------- */ 235754450f59SHans Verkuil 235854450f59SHans Verkuil static const struct v4l2_ctrl_ops adv7604_ctrl_ops = { 235954450f59SHans Verkuil .s_ctrl = adv7604_s_ctrl, 236054450f59SHans Verkuil }; 236154450f59SHans Verkuil 236254450f59SHans Verkuil static const struct v4l2_subdev_core_ops adv7604_core_ops = { 236354450f59SHans Verkuil .log_status = adv7604_log_status, 236454450f59SHans Verkuil .interrupt_service_routine = adv7604_isr, 236554450f59SHans Verkuil #ifdef CONFIG_VIDEO_ADV_DEBUG 236654450f59SHans Verkuil .g_register = adv7604_g_register, 236754450f59SHans Verkuil .s_register = adv7604_s_register, 236854450f59SHans Verkuil #endif 236954450f59SHans Verkuil }; 237054450f59SHans Verkuil 237154450f59SHans Verkuil static const struct v4l2_subdev_video_ops adv7604_video_ops = { 237254450f59SHans Verkuil .s_routing = adv7604_s_routing, 237354450f59SHans Verkuil .g_input_status = adv7604_g_input_status, 237454450f59SHans Verkuil .s_dv_timings = adv7604_s_dv_timings, 237554450f59SHans Verkuil .g_dv_timings = adv7604_g_dv_timings, 237654450f59SHans Verkuil .query_dv_timings = adv7604_query_dv_timings, 237754450f59SHans Verkuil }; 237854450f59SHans Verkuil 237954450f59SHans Verkuil static const struct v4l2_subdev_pad_ops adv7604_pad_ops = { 2380539b33b0SLaurent Pinchart .enum_mbus_code = adv7604_enum_mbus_code, 2381539b33b0SLaurent Pinchart .get_fmt = adv7604_get_format, 2382539b33b0SLaurent Pinchart .set_fmt = adv7604_set_format, 238354450f59SHans Verkuil .get_edid = adv7604_get_edid, 238454450f59SHans Verkuil .set_edid = adv7604_set_edid, 23857515e096SLaurent Pinchart .dv_timings_cap = adv7604_dv_timings_cap, 2386afec5599SLaurent Pinchart .enum_dv_timings = adv7604_enum_dv_timings, 238754450f59SHans Verkuil }; 238854450f59SHans Verkuil 238954450f59SHans Verkuil static const struct v4l2_subdev_ops adv7604_ops = { 239054450f59SHans Verkuil .core = &adv7604_core_ops, 239154450f59SHans Verkuil .video = &adv7604_video_ops, 239254450f59SHans Verkuil .pad = &adv7604_pad_ops, 239354450f59SHans Verkuil }; 239454450f59SHans Verkuil 239554450f59SHans Verkuil /* -------------------------- custom ctrls ---------------------------------- */ 239654450f59SHans Verkuil 239754450f59SHans Verkuil static const struct v4l2_ctrl_config adv7604_ctrl_analog_sampling_phase = { 239854450f59SHans Verkuil .ops = &adv7604_ctrl_ops, 239954450f59SHans Verkuil .id = V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE, 240054450f59SHans Verkuil .name = "Analog Sampling Phase", 240154450f59SHans Verkuil .type = V4L2_CTRL_TYPE_INTEGER, 240254450f59SHans Verkuil .min = 0, 240354450f59SHans Verkuil .max = 0x1f, 240454450f59SHans Verkuil .step = 1, 240554450f59SHans Verkuil .def = 0, 240654450f59SHans Verkuil }; 240754450f59SHans Verkuil 240854450f59SHans Verkuil static const struct v4l2_ctrl_config adv7604_ctrl_free_run_color_manual = { 240954450f59SHans Verkuil .ops = &adv7604_ctrl_ops, 241054450f59SHans Verkuil .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL, 241154450f59SHans Verkuil .name = "Free Running Color, Manual", 241254450f59SHans Verkuil .type = V4L2_CTRL_TYPE_BOOLEAN, 241354450f59SHans Verkuil .min = false, 241454450f59SHans Verkuil .max = true, 241554450f59SHans Verkuil .step = 1, 241654450f59SHans Verkuil .def = false, 241754450f59SHans Verkuil }; 241854450f59SHans Verkuil 241954450f59SHans Verkuil static const struct v4l2_ctrl_config adv7604_ctrl_free_run_color = { 242054450f59SHans Verkuil .ops = &adv7604_ctrl_ops, 242154450f59SHans Verkuil .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR, 242254450f59SHans Verkuil .name = "Free Running Color", 242354450f59SHans Verkuil .type = V4L2_CTRL_TYPE_INTEGER, 242454450f59SHans Verkuil .min = 0x0, 242554450f59SHans Verkuil .max = 0xffffff, 242654450f59SHans Verkuil .step = 0x1, 242754450f59SHans Verkuil .def = 0x0, 242854450f59SHans Verkuil }; 242954450f59SHans Verkuil 243054450f59SHans Verkuil /* ----------------------------------------------------------------------- */ 243154450f59SHans Verkuil 243254450f59SHans Verkuil static int adv7604_core_init(struct v4l2_subdev *sd) 243354450f59SHans Verkuil { 243454450f59SHans Verkuil struct adv7604_state *state = to_state(sd); 2435d42010a1SLars-Peter Clausen const struct adv7604_chip_info *info = state->info; 243654450f59SHans Verkuil struct adv7604_platform_data *pdata = &state->pdata; 243754450f59SHans Verkuil 243854450f59SHans Verkuil hdmi_write(sd, 0x48, 243954450f59SHans Verkuil (pdata->disable_pwrdnb ? 0x80 : 0) | 244054450f59SHans Verkuil (pdata->disable_cable_det_rst ? 0x40 : 0)); 244154450f59SHans Verkuil 244254450f59SHans Verkuil disable_input(sd); 244354450f59SHans Verkuil 244454450f59SHans Verkuil /* power */ 244554450f59SHans Verkuil io_write(sd, 0x0c, 0x42); /* Power up part and power down VDP */ 244654450f59SHans Verkuil io_write(sd, 0x0b, 0x44); /* Power down ESDP block */ 244754450f59SHans Verkuil cp_write(sd, 0xcf, 0x01); /* Power down macrovision */ 244854450f59SHans Verkuil 244954450f59SHans Verkuil /* video format */ 245022d97e56SLaurent Pinchart io_write_clr_set(sd, 0x02, 0x0f, 245154450f59SHans Verkuil pdata->alt_gamma << 3 | 245254450f59SHans Verkuil pdata->op_656_range << 2 | 245354450f59SHans Verkuil pdata->alt_data_sat << 0); 245422d97e56SLaurent Pinchart io_write_clr_set(sd, 0x05, 0x0e, pdata->blank_data << 3 | 245554450f59SHans Verkuil pdata->insert_av_codes << 2 | 2456539b33b0SLaurent Pinchart pdata->replicate_av_codes << 1); 2457539b33b0SLaurent Pinchart adv7604_setup_format(state); 245854450f59SHans Verkuil 245954450f59SHans Verkuil cp_write(sd, 0x69, 0x30); /* Enable CP CSC */ 246098908696SMartin Bugge 246198908696SMartin Bugge /* VS, HS polarities */ 246298908696SMartin Bugge io_write(sd, 0x06, 0xa0 | pdata->inv_vs_pol << 2 | pdata->inv_hs_pol << 1); 2463f31b62e1SMikhail Khelik 2464f31b62e1SMikhail Khelik /* Adjust drive strength */ 2465f31b62e1SMikhail Khelik io_write(sd, 0x14, 0x40 | pdata->dr_str_data << 4 | 2466f31b62e1SMikhail Khelik pdata->dr_str_clk << 2 | 2467f31b62e1SMikhail Khelik pdata->dr_str_sync); 2468f31b62e1SMikhail Khelik 246954450f59SHans Verkuil cp_write(sd, 0xba, (pdata->hdmi_free_run_mode << 1) | 0x01); /* HDMI free run */ 247054450f59SHans Verkuil cp_write(sd, 0xf3, 0xdc); /* Low threshold to enter/exit free run mode */ 247154450f59SHans Verkuil cp_write(sd, 0xf9, 0x23); /* STDI ch. 1 - LCVS change threshold - 247280939647SHans Verkuil ADI recommended setting [REF_01, c. 2.3.3] */ 247354450f59SHans Verkuil cp_write(sd, 0x45, 0x23); /* STDI ch. 2 - LCVS change threshold - 247480939647SHans Verkuil ADI recommended setting [REF_01, c. 2.3.3] */ 247554450f59SHans Verkuil cp_write(sd, 0xc9, 0x2d); /* use prim_mode and vid_std as free run resolution 247654450f59SHans Verkuil for digital formats */ 247754450f59SHans Verkuil 24785474b983SMats Randgaard /* HDMI audio */ 247922d97e56SLaurent Pinchart hdmi_write_clr_set(sd, 0x15, 0x03, 0x03); /* Mute on FIFO over-/underflow [REF_01, c. 1.2.18] */ 248022d97e56SLaurent Pinchart hdmi_write_clr_set(sd, 0x1a, 0x0e, 0x08); /* Wait 1 s before unmute */ 248122d97e56SLaurent Pinchart hdmi_write_clr_set(sd, 0x68, 0x06, 0x06); /* FIFO reset on over-/underflow [REF_01, c. 1.2.19] */ 24825474b983SMats Randgaard 248354450f59SHans Verkuil /* TODO from platform data */ 248454450f59SHans Verkuil afe_write(sd, 0xb5, 0x01); /* Setting MCLK to 256Fs */ 248554450f59SHans Verkuil 2486d42010a1SLars-Peter Clausen if (adv7604_has_afe(state)) { 248754450f59SHans Verkuil afe_write(sd, 0x02, pdata->ain_sel); /* Select analog input muxing mode */ 248822d97e56SLaurent Pinchart io_write_clr_set(sd, 0x30, 1 << 4, pdata->output_bus_lsb_to_msb << 4); 2489d42010a1SLars-Peter Clausen } 249054450f59SHans Verkuil 249154450f59SHans Verkuil /* interrupts */ 2492d42010a1SLars-Peter Clausen io_write(sd, 0x40, 0xc0 | pdata->int1_config); /* Configure INT1 */ 249354450f59SHans Verkuil io_write(sd, 0x46, 0x98); /* Enable SSPD, STDI and CP unlocked interrupts */ 2494d42010a1SLars-Peter Clausen io_write(sd, 0x6e, info->fmt_change_digital_mask); /* Enable V_LOCKED and DE_REGEN_LCK interrupts */ 2495d42010a1SLars-Peter Clausen io_write(sd, 0x73, info->cable_det_mask); /* Enable cable detection (+5v) interrupts */ 2496d42010a1SLars-Peter Clausen info->setup_irqs(sd); 249754450f59SHans Verkuil 249854450f59SHans Verkuil return v4l2_ctrl_handler_setup(sd->ctrl_handler); 249954450f59SHans Verkuil } 250054450f59SHans Verkuil 2501d42010a1SLars-Peter Clausen static void adv7604_setup_irqs(struct v4l2_subdev *sd) 2502d42010a1SLars-Peter Clausen { 2503d42010a1SLars-Peter Clausen io_write(sd, 0x41, 0xd7); /* STDI irq for any change, disable INT2 */ 2504d42010a1SLars-Peter Clausen } 2505d42010a1SLars-Peter Clausen 2506d42010a1SLars-Peter Clausen static void adv7611_setup_irqs(struct v4l2_subdev *sd) 2507d42010a1SLars-Peter Clausen { 2508d42010a1SLars-Peter Clausen io_write(sd, 0x41, 0xd0); /* STDI irq for any change, disable INT2 */ 2509d42010a1SLars-Peter Clausen } 2510d42010a1SLars-Peter Clausen 251154450f59SHans Verkuil static void adv7604_unregister_clients(struct adv7604_state *state) 251254450f59SHans Verkuil { 251305cacb17SLaurent Pinchart unsigned int i; 251405cacb17SLaurent Pinchart 251505cacb17SLaurent Pinchart for (i = 1; i < ARRAY_SIZE(state->i2c_clients); ++i) { 251605cacb17SLaurent Pinchart if (state->i2c_clients[i]) 251705cacb17SLaurent Pinchart i2c_unregister_device(state->i2c_clients[i]); 251805cacb17SLaurent Pinchart } 251954450f59SHans Verkuil } 252054450f59SHans Verkuil 252154450f59SHans Verkuil static struct i2c_client *adv7604_dummy_client(struct v4l2_subdev *sd, 252254450f59SHans Verkuil u8 addr, u8 io_reg) 252354450f59SHans Verkuil { 252454450f59SHans Verkuil struct i2c_client *client = v4l2_get_subdevdata(sd); 252554450f59SHans Verkuil 252654450f59SHans Verkuil if (addr) 252754450f59SHans Verkuil io_write(sd, io_reg, addr << 1); 252854450f59SHans Verkuil return i2c_new_dummy(client->adapter, io_read(sd, io_reg) >> 1); 252954450f59SHans Verkuil } 253054450f59SHans Verkuil 2531d42010a1SLars-Peter Clausen static const struct adv7604_reg_seq adv7604_recommended_settings_afe[] = { 2532d42010a1SLars-Peter Clausen /* reset ADI recommended settings for HDMI: */ 2533d42010a1SLars-Peter Clausen /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 4. */ 2534d42010a1SLars-Peter Clausen { ADV7604_REG(ADV7604_PAGE_HDMI, 0x0d), 0x04 }, /* HDMI filter optimization */ 2535d42010a1SLars-Peter Clausen { ADV7604_REG(ADV7604_PAGE_HDMI, 0x0d), 0x04 }, /* HDMI filter optimization */ 2536d42010a1SLars-Peter Clausen { ADV7604_REG(ADV7604_PAGE_HDMI, 0x3d), 0x00 }, /* DDC bus active pull-up control */ 2537d42010a1SLars-Peter Clausen { ADV7604_REG(ADV7604_PAGE_HDMI, 0x3e), 0x74 }, /* TMDS PLL optimization */ 2538d42010a1SLars-Peter Clausen { ADV7604_REG(ADV7604_PAGE_HDMI, 0x4e), 0x3b }, /* TMDS PLL optimization */ 2539d42010a1SLars-Peter Clausen { ADV7604_REG(ADV7604_PAGE_HDMI, 0x57), 0x74 }, /* TMDS PLL optimization */ 2540d42010a1SLars-Peter Clausen { ADV7604_REG(ADV7604_PAGE_HDMI, 0x58), 0x63 }, /* TMDS PLL optimization */ 2541d42010a1SLars-Peter Clausen { ADV7604_REG(ADV7604_PAGE_HDMI, 0x8d), 0x18 }, /* equaliser */ 2542d42010a1SLars-Peter Clausen { ADV7604_REG(ADV7604_PAGE_HDMI, 0x8e), 0x34 }, /* equaliser */ 2543d42010a1SLars-Peter Clausen { ADV7604_REG(ADV7604_PAGE_HDMI, 0x93), 0x88 }, /* equaliser */ 2544d42010a1SLars-Peter Clausen { ADV7604_REG(ADV7604_PAGE_HDMI, 0x94), 0x2e }, /* equaliser */ 2545d42010a1SLars-Peter Clausen { ADV7604_REG(ADV7604_PAGE_HDMI, 0x96), 0x00 }, /* enable automatic EQ changing */ 2546d42010a1SLars-Peter Clausen 2547d42010a1SLars-Peter Clausen /* set ADI recommended settings for digitizer */ 2548d42010a1SLars-Peter Clausen /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 17. */ 2549d42010a1SLars-Peter Clausen { ADV7604_REG(ADV7604_PAGE_AFE, 0x12), 0x7b }, /* ADC noise shaping filter controls */ 2550d42010a1SLars-Peter Clausen { ADV7604_REG(ADV7604_PAGE_AFE, 0x0c), 0x1f }, /* CP core gain controls */ 2551d42010a1SLars-Peter Clausen { ADV7604_REG(ADV7604_PAGE_CP, 0x3e), 0x04 }, /* CP core pre-gain control */ 2552d42010a1SLars-Peter Clausen { ADV7604_REG(ADV7604_PAGE_CP, 0xc3), 0x39 }, /* CP coast control. Graphics mode */ 2553d42010a1SLars-Peter Clausen { ADV7604_REG(ADV7604_PAGE_CP, 0x40), 0x5c }, /* CP core pre-gain control. Graphics mode */ 2554d42010a1SLars-Peter Clausen 2555d42010a1SLars-Peter Clausen { ADV7604_REG_SEQ_TERM, 0 }, 2556d42010a1SLars-Peter Clausen }; 2557d42010a1SLars-Peter Clausen 2558d42010a1SLars-Peter Clausen static const struct adv7604_reg_seq adv7604_recommended_settings_hdmi[] = { 2559d42010a1SLars-Peter Clausen /* set ADI recommended settings for HDMI: */ 2560d42010a1SLars-Peter Clausen /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 4. */ 2561d42010a1SLars-Peter Clausen { ADV7604_REG(ADV7604_PAGE_HDMI, 0x0d), 0x84 }, /* HDMI filter optimization */ 2562d42010a1SLars-Peter Clausen { ADV7604_REG(ADV7604_PAGE_HDMI, 0x3d), 0x10 }, /* DDC bus active pull-up control */ 2563d42010a1SLars-Peter Clausen { ADV7604_REG(ADV7604_PAGE_HDMI, 0x3e), 0x39 }, /* TMDS PLL optimization */ 2564d42010a1SLars-Peter Clausen { ADV7604_REG(ADV7604_PAGE_HDMI, 0x4e), 0x3b }, /* TMDS PLL optimization */ 2565d42010a1SLars-Peter Clausen { ADV7604_REG(ADV7604_PAGE_HDMI, 0x57), 0xb6 }, /* TMDS PLL optimization */ 2566d42010a1SLars-Peter Clausen { ADV7604_REG(ADV7604_PAGE_HDMI, 0x58), 0x03 }, /* TMDS PLL optimization */ 2567d42010a1SLars-Peter Clausen { ADV7604_REG(ADV7604_PAGE_HDMI, 0x8d), 0x18 }, /* equaliser */ 2568d42010a1SLars-Peter Clausen { ADV7604_REG(ADV7604_PAGE_HDMI, 0x8e), 0x34 }, /* equaliser */ 2569d42010a1SLars-Peter Clausen { ADV7604_REG(ADV7604_PAGE_HDMI, 0x93), 0x8b }, /* equaliser */ 2570d42010a1SLars-Peter Clausen { ADV7604_REG(ADV7604_PAGE_HDMI, 0x94), 0x2d }, /* equaliser */ 2571d42010a1SLars-Peter Clausen { ADV7604_REG(ADV7604_PAGE_HDMI, 0x96), 0x01 }, /* enable automatic EQ changing */ 2572d42010a1SLars-Peter Clausen 2573d42010a1SLars-Peter Clausen /* reset ADI recommended settings for digitizer */ 2574d42010a1SLars-Peter Clausen /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 17. */ 2575d42010a1SLars-Peter Clausen { ADV7604_REG(ADV7604_PAGE_AFE, 0x12), 0xfb }, /* ADC noise shaping filter controls */ 2576d42010a1SLars-Peter Clausen { ADV7604_REG(ADV7604_PAGE_AFE, 0x0c), 0x0d }, /* CP core gain controls */ 2577d42010a1SLars-Peter Clausen 2578d42010a1SLars-Peter Clausen { ADV7604_REG_SEQ_TERM, 0 }, 2579d42010a1SLars-Peter Clausen }; 2580d42010a1SLars-Peter Clausen 2581d42010a1SLars-Peter Clausen static const struct adv7604_reg_seq adv7611_recommended_settings_hdmi[] = { 2582d42010a1SLars-Peter Clausen { ADV7604_REG(ADV7604_PAGE_CP, 0x6c), 0x00 }, 2583d42010a1SLars-Peter Clausen { ADV7604_REG(ADV7604_PAGE_HDMI, 0x6f), 0x0c }, 2584d42010a1SLars-Peter Clausen { ADV7604_REG(ADV7604_PAGE_HDMI, 0x87), 0x70 }, 2585d42010a1SLars-Peter Clausen { ADV7604_REG(ADV7604_PAGE_HDMI, 0x57), 0xda }, 2586d42010a1SLars-Peter Clausen { ADV7604_REG(ADV7604_PAGE_HDMI, 0x58), 0x01 }, 2587d42010a1SLars-Peter Clausen { ADV7604_REG(ADV7604_PAGE_HDMI, 0x03), 0x98 }, 2588d42010a1SLars-Peter Clausen { ADV7604_REG(ADV7604_PAGE_HDMI, 0x4c), 0x44 }, 2589d42010a1SLars-Peter Clausen { ADV7604_REG(ADV7604_PAGE_HDMI, 0x8d), 0x04 }, 2590d42010a1SLars-Peter Clausen { ADV7604_REG(ADV7604_PAGE_HDMI, 0x8e), 0x1e }, 2591d42010a1SLars-Peter Clausen 2592d42010a1SLars-Peter Clausen { ADV7604_REG_SEQ_TERM, 0 }, 2593d42010a1SLars-Peter Clausen }; 2594d42010a1SLars-Peter Clausen 2595d42010a1SLars-Peter Clausen static const struct adv7604_chip_info adv7604_chip_info[] = { 2596d42010a1SLars-Peter Clausen [ADV7604] = { 2597d42010a1SLars-Peter Clausen .type = ADV7604, 2598d42010a1SLars-Peter Clausen .has_afe = true, 2599c784b1e2SLaurent Pinchart .max_port = ADV7604_PAD_VGA_COMP, 2600d42010a1SLars-Peter Clausen .num_dv_ports = 4, 2601d42010a1SLars-Peter Clausen .edid_enable_reg = 0x77, 2602d42010a1SLars-Peter Clausen .edid_status_reg = 0x7d, 2603d42010a1SLars-Peter Clausen .lcf_reg = 0xb3, 2604d42010a1SLars-Peter Clausen .tdms_lock_mask = 0xe0, 2605d42010a1SLars-Peter Clausen .cable_det_mask = 0x1e, 2606d42010a1SLars-Peter Clausen .fmt_change_digital_mask = 0xc1, 2607539b33b0SLaurent Pinchart .formats = adv7604_formats, 2608539b33b0SLaurent Pinchart .nformats = ARRAY_SIZE(adv7604_formats), 2609d42010a1SLars-Peter Clausen .set_termination = adv7604_set_termination, 2610d42010a1SLars-Peter Clausen .setup_irqs = adv7604_setup_irqs, 2611d42010a1SLars-Peter Clausen .read_hdmi_pixelclock = adv7604_read_hdmi_pixelclock, 2612d42010a1SLars-Peter Clausen .read_cable_det = adv7604_read_cable_det, 2613d42010a1SLars-Peter Clausen .recommended_settings = { 2614d42010a1SLars-Peter Clausen [0] = adv7604_recommended_settings_afe, 2615d42010a1SLars-Peter Clausen [1] = adv7604_recommended_settings_hdmi, 2616d42010a1SLars-Peter Clausen }, 2617d42010a1SLars-Peter Clausen .num_recommended_settings = { 2618d42010a1SLars-Peter Clausen [0] = ARRAY_SIZE(adv7604_recommended_settings_afe), 2619d42010a1SLars-Peter Clausen [1] = ARRAY_SIZE(adv7604_recommended_settings_hdmi), 2620d42010a1SLars-Peter Clausen }, 2621d42010a1SLars-Peter Clausen .page_mask = BIT(ADV7604_PAGE_IO) | BIT(ADV7604_PAGE_AVLINK) | 2622d42010a1SLars-Peter Clausen BIT(ADV7604_PAGE_CEC) | BIT(ADV7604_PAGE_INFOFRAME) | 2623d42010a1SLars-Peter Clausen BIT(ADV7604_PAGE_ESDP) | BIT(ADV7604_PAGE_DPP) | 2624d42010a1SLars-Peter Clausen BIT(ADV7604_PAGE_AFE) | BIT(ADV7604_PAGE_REP) | 2625d42010a1SLars-Peter Clausen BIT(ADV7604_PAGE_EDID) | BIT(ADV7604_PAGE_HDMI) | 2626d42010a1SLars-Peter Clausen BIT(ADV7604_PAGE_TEST) | BIT(ADV7604_PAGE_CP) | 2627d42010a1SLars-Peter Clausen BIT(ADV7604_PAGE_VDP), 2628d42010a1SLars-Peter Clausen }, 2629d42010a1SLars-Peter Clausen [ADV7611] = { 2630d42010a1SLars-Peter Clausen .type = ADV7611, 2631d42010a1SLars-Peter Clausen .has_afe = false, 2632c784b1e2SLaurent Pinchart .max_port = ADV7604_PAD_HDMI_PORT_A, 2633d42010a1SLars-Peter Clausen .num_dv_ports = 1, 2634d42010a1SLars-Peter Clausen .edid_enable_reg = 0x74, 2635d42010a1SLars-Peter Clausen .edid_status_reg = 0x76, 2636d42010a1SLars-Peter Clausen .lcf_reg = 0xa3, 2637d42010a1SLars-Peter Clausen .tdms_lock_mask = 0x43, 2638d42010a1SLars-Peter Clausen .cable_det_mask = 0x01, 2639d42010a1SLars-Peter Clausen .fmt_change_digital_mask = 0x03, 2640539b33b0SLaurent Pinchart .formats = adv7611_formats, 2641539b33b0SLaurent Pinchart .nformats = ARRAY_SIZE(adv7611_formats), 2642d42010a1SLars-Peter Clausen .set_termination = adv7611_set_termination, 2643d42010a1SLars-Peter Clausen .setup_irqs = adv7611_setup_irqs, 2644d42010a1SLars-Peter Clausen .read_hdmi_pixelclock = adv7611_read_hdmi_pixelclock, 2645d42010a1SLars-Peter Clausen .read_cable_det = adv7611_read_cable_det, 2646d42010a1SLars-Peter Clausen .recommended_settings = { 2647d42010a1SLars-Peter Clausen [1] = adv7611_recommended_settings_hdmi, 2648d42010a1SLars-Peter Clausen }, 2649d42010a1SLars-Peter Clausen .num_recommended_settings = { 2650d42010a1SLars-Peter Clausen [1] = ARRAY_SIZE(adv7611_recommended_settings_hdmi), 2651d42010a1SLars-Peter Clausen }, 2652d42010a1SLars-Peter Clausen .page_mask = BIT(ADV7604_PAGE_IO) | BIT(ADV7604_PAGE_CEC) | 2653d42010a1SLars-Peter Clausen BIT(ADV7604_PAGE_INFOFRAME) | BIT(ADV7604_PAGE_AFE) | 2654d42010a1SLars-Peter Clausen BIT(ADV7604_PAGE_REP) | BIT(ADV7604_PAGE_EDID) | 2655d42010a1SLars-Peter Clausen BIT(ADV7604_PAGE_HDMI) | BIT(ADV7604_PAGE_CP), 2656d42010a1SLars-Peter Clausen }, 2657d42010a1SLars-Peter Clausen }; 2658d42010a1SLars-Peter Clausen 265954450f59SHans Verkuil static int adv7604_probe(struct i2c_client *client, 266054450f59SHans Verkuil const struct i2c_device_id *id) 266154450f59SHans Verkuil { 2662591b72feSHans Verkuil static const struct v4l2_dv_timings cea640x480 = 2663591b72feSHans Verkuil V4L2_DV_BT_CEA_640X480P59_94; 266454450f59SHans Verkuil struct adv7604_state *state; 266554450f59SHans Verkuil struct adv7604_platform_data *pdata = client->dev.platform_data; 266654450f59SHans Verkuil struct v4l2_ctrl_handler *hdl; 266754450f59SHans Verkuil struct v4l2_subdev *sd; 2668c784b1e2SLaurent Pinchart unsigned int i; 2669d42010a1SLars-Peter Clausen u16 val; 267054450f59SHans Verkuil int err; 267154450f59SHans Verkuil 267254450f59SHans Verkuil /* Check if the adapter supports the needed features */ 267354450f59SHans Verkuil if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA)) 267454450f59SHans Verkuil return -EIO; 267554450f59SHans Verkuil v4l_dbg(1, debug, client, "detecting adv7604 client on address 0x%x\n", 267654450f59SHans Verkuil client->addr << 1); 267754450f59SHans Verkuil 2678c02b211dSLaurent Pinchart state = devm_kzalloc(&client->dev, sizeof(*state), GFP_KERNEL); 267954450f59SHans Verkuil if (!state) { 268054450f59SHans Verkuil v4l_err(client, "Could not allocate adv7604_state memory!\n"); 268154450f59SHans Verkuil return -ENOMEM; 268254450f59SHans Verkuil } 268354450f59SHans Verkuil 2684d42010a1SLars-Peter Clausen state->info = &adv7604_chip_info[id->driver_data]; 268505cacb17SLaurent Pinchart state->i2c_clients[ADV7604_PAGE_IO] = client; 2686d42010a1SLars-Peter Clausen 268725a64ac9SMats Randgaard /* initialize variables */ 268825a64ac9SMats Randgaard state->restart_stdi_once = true; 2689ff4f80fdSMats Randgaard state->selected_input = ~0; 269025a64ac9SMats Randgaard 269154450f59SHans Verkuil /* platform data */ 269254450f59SHans Verkuil if (!pdata) { 269354450f59SHans Verkuil v4l_err(client, "No platform data!\n"); 2694c02b211dSLaurent Pinchart return -ENODEV; 269554450f59SHans Verkuil } 2696591b72feSHans Verkuil state->pdata = *pdata; 2697e9d50e9eSLaurent Pinchart 2698e9d50e9eSLaurent Pinchart /* Request GPIOs. */ 2699e9d50e9eSLaurent Pinchart for (i = 0; i < state->info->num_dv_ports; ++i) { 2700e9d50e9eSLaurent Pinchart state->hpd_gpio[i] = 2701e9d50e9eSLaurent Pinchart devm_gpiod_get_index(&client->dev, "hpd", i); 2702e9d50e9eSLaurent Pinchart if (IS_ERR(state->hpd_gpio[i])) 2703e9d50e9eSLaurent Pinchart continue; 2704e9d50e9eSLaurent Pinchart 2705e9d50e9eSLaurent Pinchart gpiod_set_value_cansleep(state->hpd_gpio[i], 0); 2706e9d50e9eSLaurent Pinchart 2707e9d50e9eSLaurent Pinchart v4l_info(client, "Handling HPD %u GPIO\n", i); 2708e9d50e9eSLaurent Pinchart } 2709e9d50e9eSLaurent Pinchart 2710591b72feSHans Verkuil state->timings = cea640x480; 2711539b33b0SLaurent Pinchart state->format = adv7604_format_info(state, V4L2_MBUS_FMT_YUYV8_2X8); 271254450f59SHans Verkuil 271354450f59SHans Verkuil sd = &state->sd; 271454450f59SHans Verkuil v4l2_i2c_subdev_init(sd, client, &adv7604_ops); 2715d42010a1SLars-Peter Clausen snprintf(sd->name, sizeof(sd->name), "%s %d-%04x", 2716d42010a1SLars-Peter Clausen id->name, i2c_adapter_id(client->adapter), 2717d42010a1SLars-Peter Clausen client->addr); 271854450f59SHans Verkuil sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; 271954450f59SHans Verkuil 2720d42010a1SLars-Peter Clausen /* 2721d42010a1SLars-Peter Clausen * Verify that the chip is present. On ADV7604 the RD_INFO register only 2722d42010a1SLars-Peter Clausen * identifies the revision, while on ADV7611 it identifies the model as 2723d42010a1SLars-Peter Clausen * well. Use the HDMI slave address on ADV7604 and RD_INFO on ADV7611. 2724d42010a1SLars-Peter Clausen */ 2725d42010a1SLars-Peter Clausen if (state->info->type == ADV7604) { 2726d42010a1SLars-Peter Clausen val = adv_smbus_read_byte_data_check(client, 0xfb, false); 2727d42010a1SLars-Peter Clausen if (val != 0x68) { 272854450f59SHans Verkuil v4l2_info(sd, "not an adv7604 on address 0x%x\n", 272954450f59SHans Verkuil client->addr << 1); 2730c02b211dSLaurent Pinchart return -ENODEV; 273154450f59SHans Verkuil } 2732d42010a1SLars-Peter Clausen } else { 2733d42010a1SLars-Peter Clausen val = (adv_smbus_read_byte_data_check(client, 0xea, false) << 8) 2734d42010a1SLars-Peter Clausen | (adv_smbus_read_byte_data_check(client, 0xeb, false) << 0); 2735d42010a1SLars-Peter Clausen if (val != 0x2051) { 2736d42010a1SLars-Peter Clausen v4l2_info(sd, "not an adv7611 on address 0x%x\n", 2737d42010a1SLars-Peter Clausen client->addr << 1); 2738d42010a1SLars-Peter Clausen return -ENODEV; 2739d42010a1SLars-Peter Clausen } 2740d42010a1SLars-Peter Clausen } 274154450f59SHans Verkuil 274254450f59SHans Verkuil /* control handlers */ 274354450f59SHans Verkuil hdl = &state->hdl; 2744d42010a1SLars-Peter Clausen v4l2_ctrl_handler_init(hdl, adv7604_has_afe(state) ? 9 : 8); 274554450f59SHans Verkuil 274654450f59SHans Verkuil v4l2_ctrl_new_std(hdl, &adv7604_ctrl_ops, 274754450f59SHans Verkuil V4L2_CID_BRIGHTNESS, -128, 127, 1, 0); 274854450f59SHans Verkuil v4l2_ctrl_new_std(hdl, &adv7604_ctrl_ops, 274954450f59SHans Verkuil V4L2_CID_CONTRAST, 0, 255, 1, 128); 275054450f59SHans Verkuil v4l2_ctrl_new_std(hdl, &adv7604_ctrl_ops, 275154450f59SHans Verkuil V4L2_CID_SATURATION, 0, 255, 1, 128); 275254450f59SHans Verkuil v4l2_ctrl_new_std(hdl, &adv7604_ctrl_ops, 275354450f59SHans Verkuil V4L2_CID_HUE, 0, 128, 1, 0); 275454450f59SHans Verkuil 275554450f59SHans Verkuil /* private controls */ 275654450f59SHans Verkuil state->detect_tx_5v_ctrl = v4l2_ctrl_new_std(hdl, NULL, 2757d42010a1SLars-Peter Clausen V4L2_CID_DV_RX_POWER_PRESENT, 0, 2758d42010a1SLars-Peter Clausen (1 << state->info->num_dv_ports) - 1, 0, 0); 275954450f59SHans Verkuil state->rgb_quantization_range_ctrl = 276054450f59SHans Verkuil v4l2_ctrl_new_std_menu(hdl, &adv7604_ctrl_ops, 276154450f59SHans Verkuil V4L2_CID_DV_RX_RGB_RANGE, V4L2_DV_RGB_RANGE_FULL, 276254450f59SHans Verkuil 0, V4L2_DV_RGB_RANGE_AUTO); 276354450f59SHans Verkuil 276454450f59SHans Verkuil /* custom controls */ 2765d42010a1SLars-Peter Clausen if (adv7604_has_afe(state)) 276654450f59SHans Verkuil state->analog_sampling_phase_ctrl = 276754450f59SHans Verkuil v4l2_ctrl_new_custom(hdl, &adv7604_ctrl_analog_sampling_phase, NULL); 276854450f59SHans Verkuil state->free_run_color_manual_ctrl = 276954450f59SHans Verkuil v4l2_ctrl_new_custom(hdl, &adv7604_ctrl_free_run_color_manual, NULL); 277054450f59SHans Verkuil state->free_run_color_ctrl = 277154450f59SHans Verkuil v4l2_ctrl_new_custom(hdl, &adv7604_ctrl_free_run_color, NULL); 277254450f59SHans Verkuil 277354450f59SHans Verkuil sd->ctrl_handler = hdl; 277454450f59SHans Verkuil if (hdl->error) { 277554450f59SHans Verkuil err = hdl->error; 277654450f59SHans Verkuil goto err_hdl; 277754450f59SHans Verkuil } 27788c0eadb8SHans Verkuil state->detect_tx_5v_ctrl->is_private = true; 27798c0eadb8SHans Verkuil state->rgb_quantization_range_ctrl->is_private = true; 2780d42010a1SLars-Peter Clausen if (adv7604_has_afe(state)) 27818c0eadb8SHans Verkuil state->analog_sampling_phase_ctrl->is_private = true; 27828c0eadb8SHans Verkuil state->free_run_color_manual_ctrl->is_private = true; 27838c0eadb8SHans Verkuil state->free_run_color_ctrl->is_private = true; 27848c0eadb8SHans Verkuil 278554450f59SHans Verkuil if (adv7604_s_detect_tx_5v_ctrl(sd)) { 278654450f59SHans Verkuil err = -ENODEV; 278754450f59SHans Verkuil goto err_hdl; 278854450f59SHans Verkuil } 278954450f59SHans Verkuil 279005cacb17SLaurent Pinchart for (i = 1; i < ADV7604_PAGE_MAX; ++i) { 279105cacb17SLaurent Pinchart if (!(BIT(i) & state->info->page_mask)) 279205cacb17SLaurent Pinchart continue; 279305cacb17SLaurent Pinchart 279405cacb17SLaurent Pinchart state->i2c_clients[i] = 279505cacb17SLaurent Pinchart adv7604_dummy_client(sd, pdata->i2c_addresses[i], 279605cacb17SLaurent Pinchart 0xf2 + i); 279705cacb17SLaurent Pinchart if (state->i2c_clients[i] == NULL) { 279854450f59SHans Verkuil err = -ENOMEM; 279905cacb17SLaurent Pinchart v4l2_err(sd, "failed to create i2c client %u\n", i); 280054450f59SHans Verkuil goto err_i2c; 280154450f59SHans Verkuil } 280205cacb17SLaurent Pinchart } 280354450f59SHans Verkuil 280454450f59SHans Verkuil /* work queues */ 280554450f59SHans Verkuil state->work_queues = create_singlethread_workqueue(client->name); 280654450f59SHans Verkuil if (!state->work_queues) { 280754450f59SHans Verkuil v4l2_err(sd, "Could not create work queue\n"); 280854450f59SHans Verkuil err = -ENOMEM; 280954450f59SHans Verkuil goto err_i2c; 281054450f59SHans Verkuil } 281154450f59SHans Verkuil 281254450f59SHans Verkuil INIT_DELAYED_WORK(&state->delayed_work_enable_hotplug, 281354450f59SHans Verkuil adv7604_delayed_work_enable_hotplug); 281454450f59SHans Verkuil 2815c784b1e2SLaurent Pinchart state->source_pad = state->info->num_dv_ports 2816c784b1e2SLaurent Pinchart + (state->info->has_afe ? 2 : 0); 2817c784b1e2SLaurent Pinchart for (i = 0; i < state->source_pad; ++i) 2818c784b1e2SLaurent Pinchart state->pads[i].flags = MEDIA_PAD_FL_SINK; 2819c784b1e2SLaurent Pinchart state->pads[state->source_pad].flags = MEDIA_PAD_FL_SOURCE; 2820c784b1e2SLaurent Pinchart 2821c784b1e2SLaurent Pinchart err = media_entity_init(&sd->entity, state->source_pad + 1, 2822c784b1e2SLaurent Pinchart state->pads, 0); 282354450f59SHans Verkuil if (err) 282454450f59SHans Verkuil goto err_work_queues; 282554450f59SHans Verkuil 282654450f59SHans Verkuil err = adv7604_core_init(sd); 282754450f59SHans Verkuil if (err) 282854450f59SHans Verkuil goto err_entity; 282954450f59SHans Verkuil v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name, 283054450f59SHans Verkuil client->addr << 1, client->adapter->name); 2831bedc3939SLars-Peter Clausen 2832bedc3939SLars-Peter Clausen err = v4l2_async_register_subdev(sd); 2833bedc3939SLars-Peter Clausen if (err) 2834bedc3939SLars-Peter Clausen goto err_entity; 2835bedc3939SLars-Peter Clausen 283654450f59SHans Verkuil return 0; 283754450f59SHans Verkuil 283854450f59SHans Verkuil err_entity: 283954450f59SHans Verkuil media_entity_cleanup(&sd->entity); 284054450f59SHans Verkuil err_work_queues: 284154450f59SHans Verkuil cancel_delayed_work(&state->delayed_work_enable_hotplug); 284254450f59SHans Verkuil destroy_workqueue(state->work_queues); 284354450f59SHans Verkuil err_i2c: 284454450f59SHans Verkuil adv7604_unregister_clients(state); 284554450f59SHans Verkuil err_hdl: 284654450f59SHans Verkuil v4l2_ctrl_handler_free(hdl); 284754450f59SHans Verkuil return err; 284854450f59SHans Verkuil } 284954450f59SHans Verkuil 285054450f59SHans Verkuil /* ----------------------------------------------------------------------- */ 285154450f59SHans Verkuil 285254450f59SHans Verkuil static int adv7604_remove(struct i2c_client *client) 285354450f59SHans Verkuil { 285454450f59SHans Verkuil struct v4l2_subdev *sd = i2c_get_clientdata(client); 285554450f59SHans Verkuil struct adv7604_state *state = to_state(sd); 285654450f59SHans Verkuil 285754450f59SHans Verkuil cancel_delayed_work(&state->delayed_work_enable_hotplug); 285854450f59SHans Verkuil destroy_workqueue(state->work_queues); 2859bedc3939SLars-Peter Clausen v4l2_async_unregister_subdev(sd); 286054450f59SHans Verkuil v4l2_device_unregister_subdev(sd); 286154450f59SHans Verkuil media_entity_cleanup(&sd->entity); 286254450f59SHans Verkuil adv7604_unregister_clients(to_state(sd)); 286354450f59SHans Verkuil v4l2_ctrl_handler_free(sd->ctrl_handler); 286454450f59SHans Verkuil return 0; 286554450f59SHans Verkuil } 286654450f59SHans Verkuil 286754450f59SHans Verkuil /* ----------------------------------------------------------------------- */ 286854450f59SHans Verkuil 286954450f59SHans Verkuil static struct i2c_device_id adv7604_id[] = { 2870d42010a1SLars-Peter Clausen { "adv7604", ADV7604 }, 2871d42010a1SLars-Peter Clausen { "adv7611", ADV7611 }, 287254450f59SHans Verkuil { } 287354450f59SHans Verkuil }; 287454450f59SHans Verkuil MODULE_DEVICE_TABLE(i2c, adv7604_id); 287554450f59SHans Verkuil 287654450f59SHans Verkuil static struct i2c_driver adv7604_driver = { 287754450f59SHans Verkuil .driver = { 287854450f59SHans Verkuil .owner = THIS_MODULE, 287954450f59SHans Verkuil .name = "adv7604", 288054450f59SHans Verkuil }, 288154450f59SHans Verkuil .probe = adv7604_probe, 288254450f59SHans Verkuil .remove = adv7604_remove, 288354450f59SHans Verkuil .id_table = adv7604_id, 288454450f59SHans Verkuil }; 288554450f59SHans Verkuil 288654450f59SHans Verkuil module_i2c_driver(adv7604_driver); 2887