154450f59SHans Verkuil /* 254450f59SHans Verkuil * adv7604 - Analog Devices ADV7604 video decoder driver 354450f59SHans Verkuil * 454450f59SHans Verkuil * Copyright 2012 Cisco Systems, Inc. and/or its affiliates. All rights reserved. 554450f59SHans Verkuil * 654450f59SHans Verkuil * This program is free software; you may redistribute it and/or modify 754450f59SHans Verkuil * it under the terms of the GNU General Public License as published by 854450f59SHans Verkuil * the Free Software Foundation; version 2 of the License. 954450f59SHans Verkuil * 1054450f59SHans Verkuil * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 1154450f59SHans Verkuil * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 1254450f59SHans Verkuil * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 1354450f59SHans Verkuil * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 1454450f59SHans Verkuil * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 1554450f59SHans Verkuil * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 1654450f59SHans Verkuil * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 1754450f59SHans Verkuil * SOFTWARE. 1854450f59SHans Verkuil * 1954450f59SHans Verkuil */ 2054450f59SHans Verkuil 2154450f59SHans Verkuil /* 2254450f59SHans Verkuil * References (c = chapter, p = page): 2354450f59SHans Verkuil * REF_01 - Analog devices, ADV7604, Register Settings Recommendations, 2454450f59SHans Verkuil * Revision 2.5, June 2010 2554450f59SHans Verkuil * REF_02 - Analog devices, Register map documentation, Documentation of 2654450f59SHans Verkuil * the register maps, Software manual, Rev. F, June 2010 2754450f59SHans Verkuil * REF_03 - Analog devices, ADV7604, Hardware Manual, Rev. F, August 2010 2854450f59SHans Verkuil */ 2954450f59SHans Verkuil 30c72a53ceSLaurent Pinchart #include <linux/delay.h> 31e9d50e9eSLaurent Pinchart #include <linux/gpio/consumer.h> 32516613c1SHans Verkuil #include <linux/hdmi.h> 33c72a53ceSLaurent Pinchart #include <linux/i2c.h> 3454450f59SHans Verkuil #include <linux/kernel.h> 3554450f59SHans Verkuil #include <linux/module.h> 3654450f59SHans Verkuil #include <linux/slab.h> 37c72a53ceSLaurent Pinchart #include <linux/v4l2-dv-timings.h> 3854450f59SHans Verkuil #include <linux/videodev2.h> 3954450f59SHans Verkuil #include <linux/workqueue.h> 40f862f57dSPablo Anton #include <linux/regmap.h> 41c72a53ceSLaurent Pinchart 42b5dcee22SMauro Carvalho Chehab #include <media/i2c/adv7604.h> 43c72a53ceSLaurent Pinchart #include <media/v4l2-ctrls.h> 44c72a53ceSLaurent Pinchart #include <media/v4l2-device.h> 450975626dSLars-Peter Clausen #include <media/v4l2-event.h> 46c72a53ceSLaurent Pinchart #include <media/v4l2-dv-timings.h> 476fa88045SLaurent Pinchart #include <media/v4l2-of.h> 4854450f59SHans Verkuil 4954450f59SHans Verkuil static int debug; 5054450f59SHans Verkuil module_param(debug, int, 0644); 5154450f59SHans Verkuil MODULE_PARM_DESC(debug, "debug level (0-2)"); 5254450f59SHans Verkuil 5354450f59SHans Verkuil MODULE_DESCRIPTION("Analog Devices ADV7604 video decoder driver"); 5454450f59SHans Verkuil MODULE_AUTHOR("Hans Verkuil <hans.verkuil@cisco.com>"); 5554450f59SHans Verkuil MODULE_AUTHOR("Mats Randgaard <mats.randgaard@cisco.com>"); 5654450f59SHans Verkuil MODULE_LICENSE("GPL"); 5754450f59SHans Verkuil 5854450f59SHans Verkuil /* ADV7604 system clock frequency */ 59b44b2e06SPablo Anton #define ADV76XX_FSC (28636360) 6054450f59SHans Verkuil 61b44b2e06SPablo Anton #define ADV76XX_RGB_OUT (1 << 1) 62539b33b0SLaurent Pinchart 63b44b2e06SPablo Anton #define ADV76XX_OP_FORMAT_SEL_8BIT (0 << 0) 64539b33b0SLaurent Pinchart #define ADV7604_OP_FORMAT_SEL_10BIT (1 << 0) 65b44b2e06SPablo Anton #define ADV76XX_OP_FORMAT_SEL_12BIT (2 << 0) 66539b33b0SLaurent Pinchart 67b44b2e06SPablo Anton #define ADV76XX_OP_MODE_SEL_SDR_422 (0 << 5) 68539b33b0SLaurent Pinchart #define ADV7604_OP_MODE_SEL_DDR_422 (1 << 5) 69b44b2e06SPablo Anton #define ADV76XX_OP_MODE_SEL_SDR_444 (2 << 5) 70539b33b0SLaurent Pinchart #define ADV7604_OP_MODE_SEL_DDR_444 (3 << 5) 71b44b2e06SPablo Anton #define ADV76XX_OP_MODE_SEL_SDR_422_2X (4 << 5) 72539b33b0SLaurent Pinchart #define ADV7604_OP_MODE_SEL_ADI_CM (5 << 5) 73539b33b0SLaurent Pinchart 74b44b2e06SPablo Anton #define ADV76XX_OP_CH_SEL_GBR (0 << 5) 75b44b2e06SPablo Anton #define ADV76XX_OP_CH_SEL_GRB (1 << 5) 76b44b2e06SPablo Anton #define ADV76XX_OP_CH_SEL_BGR (2 << 5) 77b44b2e06SPablo Anton #define ADV76XX_OP_CH_SEL_RGB (3 << 5) 78b44b2e06SPablo Anton #define ADV76XX_OP_CH_SEL_BRG (4 << 5) 79b44b2e06SPablo Anton #define ADV76XX_OP_CH_SEL_RBG (5 << 5) 80539b33b0SLaurent Pinchart 81b44b2e06SPablo Anton #define ADV76XX_OP_SWAP_CB_CR (1 << 0) 82539b33b0SLaurent Pinchart 83b44b2e06SPablo Anton enum adv76xx_type { 84d42010a1SLars-Peter Clausen ADV7604, 85d42010a1SLars-Peter Clausen ADV7611, 868331d30bSWilliam Towle ADV7612, 87d42010a1SLars-Peter Clausen }; 88d42010a1SLars-Peter Clausen 89b44b2e06SPablo Anton struct adv76xx_reg_seq { 90d42010a1SLars-Peter Clausen unsigned int reg; 91d42010a1SLars-Peter Clausen u8 val; 92d42010a1SLars-Peter Clausen }; 93d42010a1SLars-Peter Clausen 94b44b2e06SPablo Anton struct adv76xx_format_info { 95f5fe58fdSBoris BREZILLON u32 code; 96539b33b0SLaurent Pinchart u8 op_ch_sel; 97539b33b0SLaurent Pinchart bool rgb_out; 98539b33b0SLaurent Pinchart bool swap_cb_cr; 99539b33b0SLaurent Pinchart u8 op_format_sel; 100539b33b0SLaurent Pinchart }; 101539b33b0SLaurent Pinchart 102516613c1SHans Verkuil struct adv76xx_cfg_read_infoframe { 103516613c1SHans Verkuil const char *desc; 104516613c1SHans Verkuil u8 present_mask; 105516613c1SHans Verkuil u8 head_addr; 106516613c1SHans Verkuil u8 payload_addr; 107516613c1SHans Verkuil }; 108516613c1SHans Verkuil 109b44b2e06SPablo Anton struct adv76xx_chip_info { 110b44b2e06SPablo Anton enum adv76xx_type type; 111d42010a1SLars-Peter Clausen 112d42010a1SLars-Peter Clausen bool has_afe; 113d42010a1SLars-Peter Clausen unsigned int max_port; 114d42010a1SLars-Peter Clausen unsigned int num_dv_ports; 115d42010a1SLars-Peter Clausen 116d42010a1SLars-Peter Clausen unsigned int edid_enable_reg; 117d42010a1SLars-Peter Clausen unsigned int edid_status_reg; 118d42010a1SLars-Peter Clausen unsigned int lcf_reg; 119d42010a1SLars-Peter Clausen 120d42010a1SLars-Peter Clausen unsigned int cable_det_mask; 121d42010a1SLars-Peter Clausen unsigned int tdms_lock_mask; 122d42010a1SLars-Peter Clausen unsigned int fmt_change_digital_mask; 12380f4944eSjean-michel.hautbois@vodalys.com unsigned int cp_csc; 124d42010a1SLars-Peter Clausen 125b44b2e06SPablo Anton const struct adv76xx_format_info *formats; 126539b33b0SLaurent Pinchart unsigned int nformats; 127539b33b0SLaurent Pinchart 128d42010a1SLars-Peter Clausen void (*set_termination)(struct v4l2_subdev *sd, bool enable); 129d42010a1SLars-Peter Clausen void (*setup_irqs)(struct v4l2_subdev *sd); 130d42010a1SLars-Peter Clausen unsigned int (*read_hdmi_pixelclock)(struct v4l2_subdev *sd); 131d42010a1SLars-Peter Clausen unsigned int (*read_cable_det)(struct v4l2_subdev *sd); 132d42010a1SLars-Peter Clausen 133d42010a1SLars-Peter Clausen /* 0 = AFE, 1 = HDMI */ 134b44b2e06SPablo Anton const struct adv76xx_reg_seq *recommended_settings[2]; 135d42010a1SLars-Peter Clausen unsigned int num_recommended_settings[2]; 136d42010a1SLars-Peter Clausen 137d42010a1SLars-Peter Clausen unsigned long page_mask; 1385380baafSjean-michel.hautbois@vodalys.com 1395380baafSjean-michel.hautbois@vodalys.com /* Masks for timings */ 1405380baafSjean-michel.hautbois@vodalys.com unsigned int linewidth_mask; 1415380baafSjean-michel.hautbois@vodalys.com unsigned int field0_height_mask; 1425380baafSjean-michel.hautbois@vodalys.com unsigned int field1_height_mask; 1435380baafSjean-michel.hautbois@vodalys.com unsigned int hfrontporch_mask; 1445380baafSjean-michel.hautbois@vodalys.com unsigned int hsync_mask; 1455380baafSjean-michel.hautbois@vodalys.com unsigned int hbackporch_mask; 1465380baafSjean-michel.hautbois@vodalys.com unsigned int field0_vfrontporch_mask; 1475380baafSjean-michel.hautbois@vodalys.com unsigned int field1_vfrontporch_mask; 1485380baafSjean-michel.hautbois@vodalys.com unsigned int field0_vsync_mask; 1495380baafSjean-michel.hautbois@vodalys.com unsigned int field1_vsync_mask; 1505380baafSjean-michel.hautbois@vodalys.com unsigned int field0_vbackporch_mask; 1515380baafSjean-michel.hautbois@vodalys.com unsigned int field1_vbackporch_mask; 152d42010a1SLars-Peter Clausen }; 153d42010a1SLars-Peter Clausen 15454450f59SHans Verkuil /* 15554450f59SHans Verkuil ********************************************************************** 15654450f59SHans Verkuil * 15754450f59SHans Verkuil * Arrays with configuration parameters for the ADV7604 15854450f59SHans Verkuil * 15954450f59SHans Verkuil ********************************************************************** 16054450f59SHans Verkuil */ 161c784b1e2SLaurent Pinchart 162b44b2e06SPablo Anton struct adv76xx_state { 163b44b2e06SPablo Anton const struct adv76xx_chip_info *info; 164b44b2e06SPablo Anton struct adv76xx_platform_data pdata; 165539b33b0SLaurent Pinchart 166e9d50e9eSLaurent Pinchart struct gpio_desc *hpd_gpio[4]; 167e9d50e9eSLaurent Pinchart 16854450f59SHans Verkuil struct v4l2_subdev sd; 169b44b2e06SPablo Anton struct media_pad pads[ADV76XX_PAD_MAX]; 170c784b1e2SLaurent Pinchart unsigned int source_pad; 171539b33b0SLaurent Pinchart 17254450f59SHans Verkuil struct v4l2_ctrl_handler hdl; 173539b33b0SLaurent Pinchart 174b44b2e06SPablo Anton enum adv76xx_pad selected_input; 175539b33b0SLaurent Pinchart 17654450f59SHans Verkuil struct v4l2_dv_timings timings; 177b44b2e06SPablo Anton const struct adv76xx_format_info *format; 178539b33b0SLaurent Pinchart 1794a31a93aSMats Randgaard struct { 18054450f59SHans Verkuil u8 edid[256]; 1814a31a93aSMats Randgaard u32 present; 1824a31a93aSMats Randgaard unsigned blocks; 1834a31a93aSMats Randgaard } edid; 184dd08beb9SMats Randgaard u16 spa_port_a[2]; 18554450f59SHans Verkuil struct v4l2_fract aspect_ratio; 18654450f59SHans Verkuil u32 rgb_quantization_range; 18754450f59SHans Verkuil struct workqueue_struct *work_queues; 18854450f59SHans Verkuil struct delayed_work delayed_work_enable_hotplug; 189cf9afb1dSHans Verkuil bool restart_stdi_once; 19054450f59SHans Verkuil 19154450f59SHans Verkuil /* i2c clients */ 192b44b2e06SPablo Anton struct i2c_client *i2c_clients[ADV76XX_PAGE_MAX]; 19354450f59SHans Verkuil 194f862f57dSPablo Anton /* Regmaps */ 195f862f57dSPablo Anton struct regmap *regmap[ADV76XX_PAGE_MAX]; 196f862f57dSPablo Anton 19754450f59SHans Verkuil /* controls */ 19854450f59SHans Verkuil struct v4l2_ctrl *detect_tx_5v_ctrl; 19954450f59SHans Verkuil struct v4l2_ctrl *analog_sampling_phase_ctrl; 20054450f59SHans Verkuil struct v4l2_ctrl *free_run_color_manual_ctrl; 20154450f59SHans Verkuil struct v4l2_ctrl *free_run_color_ctrl; 20254450f59SHans Verkuil struct v4l2_ctrl *rgb_quantization_range_ctrl; 20354450f59SHans Verkuil }; 20454450f59SHans Verkuil 205b44b2e06SPablo Anton static bool adv76xx_has_afe(struct adv76xx_state *state) 206d42010a1SLars-Peter Clausen { 207d42010a1SLars-Peter Clausen return state->info->has_afe; 208d42010a1SLars-Peter Clausen } 209d42010a1SLars-Peter Clausen 21054450f59SHans Verkuil /* Supported CEA and DMT timings */ 211b44b2e06SPablo Anton static const struct v4l2_dv_timings adv76xx_timings[] = { 21254450f59SHans Verkuil V4L2_DV_BT_CEA_720X480P59_94, 21354450f59SHans Verkuil V4L2_DV_BT_CEA_720X576P50, 21454450f59SHans Verkuil V4L2_DV_BT_CEA_1280X720P24, 21554450f59SHans Verkuil V4L2_DV_BT_CEA_1280X720P25, 21654450f59SHans Verkuil V4L2_DV_BT_CEA_1280X720P50, 21754450f59SHans Verkuil V4L2_DV_BT_CEA_1280X720P60, 21854450f59SHans Verkuil V4L2_DV_BT_CEA_1920X1080P24, 21954450f59SHans Verkuil V4L2_DV_BT_CEA_1920X1080P25, 22054450f59SHans Verkuil V4L2_DV_BT_CEA_1920X1080P30, 22154450f59SHans Verkuil V4L2_DV_BT_CEA_1920X1080P50, 22254450f59SHans Verkuil V4L2_DV_BT_CEA_1920X1080P60, 22354450f59SHans Verkuil 224ccbd5bc4SHans Verkuil /* sorted by DMT ID */ 22554450f59SHans Verkuil V4L2_DV_BT_DMT_640X350P85, 22654450f59SHans Verkuil V4L2_DV_BT_DMT_640X400P85, 22754450f59SHans Verkuil V4L2_DV_BT_DMT_720X400P85, 22854450f59SHans Verkuil V4L2_DV_BT_DMT_640X480P60, 22954450f59SHans Verkuil V4L2_DV_BT_DMT_640X480P72, 23054450f59SHans Verkuil V4L2_DV_BT_DMT_640X480P75, 23154450f59SHans Verkuil V4L2_DV_BT_DMT_640X480P85, 23254450f59SHans Verkuil V4L2_DV_BT_DMT_800X600P56, 23354450f59SHans Verkuil V4L2_DV_BT_DMT_800X600P60, 23454450f59SHans Verkuil V4L2_DV_BT_DMT_800X600P72, 23554450f59SHans Verkuil V4L2_DV_BT_DMT_800X600P75, 23654450f59SHans Verkuil V4L2_DV_BT_DMT_800X600P85, 23754450f59SHans Verkuil V4L2_DV_BT_DMT_848X480P60, 23854450f59SHans Verkuil V4L2_DV_BT_DMT_1024X768P60, 23954450f59SHans Verkuil V4L2_DV_BT_DMT_1024X768P70, 24054450f59SHans Verkuil V4L2_DV_BT_DMT_1024X768P75, 24154450f59SHans Verkuil V4L2_DV_BT_DMT_1024X768P85, 24254450f59SHans Verkuil V4L2_DV_BT_DMT_1152X864P75, 24354450f59SHans Verkuil V4L2_DV_BT_DMT_1280X768P60_RB, 24454450f59SHans Verkuil V4L2_DV_BT_DMT_1280X768P60, 24554450f59SHans Verkuil V4L2_DV_BT_DMT_1280X768P75, 24654450f59SHans Verkuil V4L2_DV_BT_DMT_1280X768P85, 24754450f59SHans Verkuil V4L2_DV_BT_DMT_1280X800P60_RB, 24854450f59SHans Verkuil V4L2_DV_BT_DMT_1280X800P60, 24954450f59SHans Verkuil V4L2_DV_BT_DMT_1280X800P75, 25054450f59SHans Verkuil V4L2_DV_BT_DMT_1280X800P85, 25154450f59SHans Verkuil V4L2_DV_BT_DMT_1280X960P60, 25254450f59SHans Verkuil V4L2_DV_BT_DMT_1280X960P85, 25354450f59SHans Verkuil V4L2_DV_BT_DMT_1280X1024P60, 25454450f59SHans Verkuil V4L2_DV_BT_DMT_1280X1024P75, 25554450f59SHans Verkuil V4L2_DV_BT_DMT_1280X1024P85, 25654450f59SHans Verkuil V4L2_DV_BT_DMT_1360X768P60, 25754450f59SHans Verkuil V4L2_DV_BT_DMT_1400X1050P60_RB, 25854450f59SHans Verkuil V4L2_DV_BT_DMT_1400X1050P60, 25954450f59SHans Verkuil V4L2_DV_BT_DMT_1400X1050P75, 26054450f59SHans Verkuil V4L2_DV_BT_DMT_1400X1050P85, 26154450f59SHans Verkuil V4L2_DV_BT_DMT_1440X900P60_RB, 26254450f59SHans Verkuil V4L2_DV_BT_DMT_1440X900P60, 26354450f59SHans Verkuil V4L2_DV_BT_DMT_1600X1200P60, 26454450f59SHans Verkuil V4L2_DV_BT_DMT_1680X1050P60_RB, 26554450f59SHans Verkuil V4L2_DV_BT_DMT_1680X1050P60, 26654450f59SHans Verkuil V4L2_DV_BT_DMT_1792X1344P60, 26754450f59SHans Verkuil V4L2_DV_BT_DMT_1856X1392P60, 26854450f59SHans Verkuil V4L2_DV_BT_DMT_1920X1200P60_RB, 269547ed542SMartin Bugge V4L2_DV_BT_DMT_1366X768P60_RB, 27054450f59SHans Verkuil V4L2_DV_BT_DMT_1366X768P60, 27154450f59SHans Verkuil V4L2_DV_BT_DMT_1920X1080P60, 27254450f59SHans Verkuil { }, 27354450f59SHans Verkuil }; 27454450f59SHans Verkuil 275b44b2e06SPablo Anton struct adv76xx_video_standards { 276ccbd5bc4SHans Verkuil struct v4l2_dv_timings timings; 277ccbd5bc4SHans Verkuil u8 vid_std; 278ccbd5bc4SHans Verkuil u8 v_freq; 279ccbd5bc4SHans Verkuil }; 280ccbd5bc4SHans Verkuil 281ccbd5bc4SHans Verkuil /* sorted by number of lines */ 282b44b2e06SPablo Anton static const struct adv76xx_video_standards adv7604_prim_mode_comp[] = { 283ccbd5bc4SHans Verkuil /* { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 }, TODO flickering */ 284ccbd5bc4SHans Verkuil { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 }, 285ccbd5bc4SHans Verkuil { V4L2_DV_BT_CEA_1280X720P50, 0x19, 0x01 }, 286ccbd5bc4SHans Verkuil { V4L2_DV_BT_CEA_1280X720P60, 0x19, 0x00 }, 287ccbd5bc4SHans Verkuil { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 }, 288ccbd5bc4SHans Verkuil { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 }, 289ccbd5bc4SHans Verkuil { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 }, 290ccbd5bc4SHans Verkuil { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 }, 291ccbd5bc4SHans Verkuil { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 }, 292ccbd5bc4SHans Verkuil /* TODO add 1920x1080P60_RB (CVT timing) */ 293ccbd5bc4SHans Verkuil { }, 294ccbd5bc4SHans Verkuil }; 295ccbd5bc4SHans Verkuil 296ccbd5bc4SHans Verkuil /* sorted by number of lines */ 297b44b2e06SPablo Anton static const struct adv76xx_video_standards adv7604_prim_mode_gr[] = { 298ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 }, 299ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 }, 300ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 }, 301ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 }, 302ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 }, 303ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 }, 304ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 }, 305ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 }, 306ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 }, 307ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 }, 308ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 }, 309ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 }, 310ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 }, 311ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 }, 312ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 }, 313ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_1360X768P60, 0x12, 0x00 }, 314ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_1366X768P60, 0x13, 0x00 }, 315ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_1400X1050P60, 0x14, 0x00 }, 316ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_1400X1050P75, 0x15, 0x00 }, 317ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_1600X1200P60, 0x16, 0x00 }, /* TODO not tested */ 318ccbd5bc4SHans Verkuil /* TODO add 1600X1200P60_RB (not a DMT timing) */ 319ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_1680X1050P60, 0x18, 0x00 }, 320ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_1920X1200P60_RB, 0x19, 0x00 }, /* TODO not tested */ 321ccbd5bc4SHans Verkuil { }, 322ccbd5bc4SHans Verkuil }; 323ccbd5bc4SHans Verkuil 324ccbd5bc4SHans Verkuil /* sorted by number of lines */ 325b44b2e06SPablo Anton static const struct adv76xx_video_standards adv76xx_prim_mode_hdmi_comp[] = { 326ccbd5bc4SHans Verkuil { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 }, 327ccbd5bc4SHans Verkuil { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 }, 328ccbd5bc4SHans Verkuil { V4L2_DV_BT_CEA_1280X720P50, 0x13, 0x01 }, 329ccbd5bc4SHans Verkuil { V4L2_DV_BT_CEA_1280X720P60, 0x13, 0x00 }, 330ccbd5bc4SHans Verkuil { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 }, 331ccbd5bc4SHans Verkuil { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 }, 332ccbd5bc4SHans Verkuil { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 }, 333ccbd5bc4SHans Verkuil { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 }, 334ccbd5bc4SHans Verkuil { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 }, 335ccbd5bc4SHans Verkuil { }, 336ccbd5bc4SHans Verkuil }; 337ccbd5bc4SHans Verkuil 338ccbd5bc4SHans Verkuil /* sorted by number of lines */ 339b44b2e06SPablo Anton static const struct adv76xx_video_standards adv76xx_prim_mode_hdmi_gr[] = { 340ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 }, 341ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 }, 342ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 }, 343ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 }, 344ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 }, 345ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 }, 346ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 }, 347ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 }, 348ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 }, 349ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 }, 350ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 }, 351ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 }, 352ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 }, 353ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 }, 354ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 }, 355ccbd5bc4SHans Verkuil { }, 356ccbd5bc4SHans Verkuil }; 357ccbd5bc4SHans Verkuil 35848519838SHans Verkuil static const struct v4l2_event adv76xx_ev_fmt = { 35948519838SHans Verkuil .type = V4L2_EVENT_SOURCE_CHANGE, 36048519838SHans Verkuil .u.src_change.changes = V4L2_EVENT_SRC_CH_RESOLUTION, 36148519838SHans Verkuil }; 36248519838SHans Verkuil 36354450f59SHans Verkuil /* ----------------------------------------------------------------------- */ 36454450f59SHans Verkuil 365b44b2e06SPablo Anton static inline struct adv76xx_state *to_state(struct v4l2_subdev *sd) 36654450f59SHans Verkuil { 367b44b2e06SPablo Anton return container_of(sd, struct adv76xx_state, sd); 36854450f59SHans Verkuil } 36954450f59SHans Verkuil 37054450f59SHans Verkuil static inline unsigned htotal(const struct v4l2_bt_timings *t) 37154450f59SHans Verkuil { 372eacf8f9aSHans Verkuil return V4L2_DV_BT_FRAME_WIDTH(t); 37354450f59SHans Verkuil } 37454450f59SHans Verkuil 37554450f59SHans Verkuil static inline unsigned vtotal(const struct v4l2_bt_timings *t) 37654450f59SHans Verkuil { 377eacf8f9aSHans Verkuil return V4L2_DV_BT_FRAME_HEIGHT(t); 37854450f59SHans Verkuil } 37954450f59SHans Verkuil 38054450f59SHans Verkuil /* ----------------------------------------------------------------------- */ 38154450f59SHans Verkuil 382f862f57dSPablo Anton static int adv76xx_read_check(struct adv76xx_state *state, 383f862f57dSPablo Anton int client_page, u8 reg) 38454450f59SHans Verkuil { 385f862f57dSPablo Anton struct i2c_client *client = state->i2c_clients[client_page]; 38654450f59SHans Verkuil int err; 387f862f57dSPablo Anton unsigned int val; 38854450f59SHans Verkuil 389f862f57dSPablo Anton err = regmap_read(state->regmap[client_page], reg, &val); 390f862f57dSPablo Anton 391f862f57dSPablo Anton if (err) { 392f862f57dSPablo Anton v4l_err(client, "error reading %02x, %02x\n", 393f862f57dSPablo Anton client->addr, reg); 39454450f59SHans Verkuil return err; 39554450f59SHans Verkuil } 396f862f57dSPablo Anton return val; 397f862f57dSPablo Anton } 39854450f59SHans Verkuil 399f862f57dSPablo Anton /* adv76xx_write_block(): Write raw data with a maximum of I2C_SMBUS_BLOCK_MAX 400f862f57dSPablo Anton * size to one or more registers. 401f862f57dSPablo Anton * 402f862f57dSPablo Anton * A value of zero will be returned on success, a negative errno will 403f862f57dSPablo Anton * be returned in error cases. 404f862f57dSPablo Anton */ 405f862f57dSPablo Anton static int adv76xx_write_block(struct adv76xx_state *state, int client_page, 406f862f57dSPablo Anton unsigned int init_reg, const void *val, 407f862f57dSPablo Anton size_t val_len) 40854450f59SHans Verkuil { 409f862f57dSPablo Anton struct regmap *regmap = state->regmap[client_page]; 41054450f59SHans Verkuil 411f862f57dSPablo Anton if (val_len > I2C_SMBUS_BLOCK_MAX) 412f862f57dSPablo Anton val_len = I2C_SMBUS_BLOCK_MAX; 413f862f57dSPablo Anton 414f862f57dSPablo Anton return regmap_raw_write(regmap, init_reg, val, val_len); 41554450f59SHans Verkuil } 41654450f59SHans Verkuil 41754450f59SHans Verkuil /* ----------------------------------------------------------------------- */ 41854450f59SHans Verkuil 41954450f59SHans Verkuil static inline int io_read(struct v4l2_subdev *sd, u8 reg) 42054450f59SHans Verkuil { 421b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 42254450f59SHans Verkuil 423f862f57dSPablo Anton return adv76xx_read_check(state, ADV76XX_PAGE_IO, reg); 42454450f59SHans Verkuil } 42554450f59SHans Verkuil 42654450f59SHans Verkuil static inline int io_write(struct v4l2_subdev *sd, u8 reg, u8 val) 42754450f59SHans Verkuil { 428b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 42954450f59SHans Verkuil 430f862f57dSPablo Anton return regmap_write(state->regmap[ADV76XX_PAGE_IO], reg, val); 43154450f59SHans Verkuil } 43254450f59SHans Verkuil 43322d97e56SLaurent Pinchart static inline int io_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) 43454450f59SHans Verkuil { 43522d97e56SLaurent Pinchart return io_write(sd, reg, (io_read(sd, reg) & ~mask) | val); 43654450f59SHans Verkuil } 43754450f59SHans Verkuil 43854450f59SHans Verkuil static inline int avlink_read(struct v4l2_subdev *sd, u8 reg) 43954450f59SHans Verkuil { 440b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 44154450f59SHans Verkuil 442f862f57dSPablo Anton return adv76xx_read_check(state, ADV7604_PAGE_AVLINK, reg); 44354450f59SHans Verkuil } 44454450f59SHans Verkuil 44554450f59SHans Verkuil static inline int avlink_write(struct v4l2_subdev *sd, u8 reg, u8 val) 44654450f59SHans Verkuil { 447b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 44854450f59SHans Verkuil 449f862f57dSPablo Anton return regmap_write(state->regmap[ADV7604_PAGE_AVLINK], reg, val); 45054450f59SHans Verkuil } 45154450f59SHans Verkuil 45254450f59SHans Verkuil static inline int cec_read(struct v4l2_subdev *sd, u8 reg) 45354450f59SHans Verkuil { 454b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 45554450f59SHans Verkuil 456f862f57dSPablo Anton return adv76xx_read_check(state, ADV76XX_PAGE_CEC, reg); 45754450f59SHans Verkuil } 45854450f59SHans Verkuil 45954450f59SHans Verkuil static inline int cec_write(struct v4l2_subdev *sd, u8 reg, u8 val) 46054450f59SHans Verkuil { 461b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 46254450f59SHans Verkuil 463f862f57dSPablo Anton return regmap_write(state->regmap[ADV76XX_PAGE_CEC], reg, val); 46454450f59SHans Verkuil } 46554450f59SHans Verkuil 46654450f59SHans Verkuil static inline int infoframe_read(struct v4l2_subdev *sd, u8 reg) 46754450f59SHans Verkuil { 468b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 46954450f59SHans Verkuil 470f862f57dSPablo Anton return adv76xx_read_check(state, ADV76XX_PAGE_INFOFRAME, reg); 47154450f59SHans Verkuil } 47254450f59SHans Verkuil 47354450f59SHans Verkuil static inline int infoframe_write(struct v4l2_subdev *sd, u8 reg, u8 val) 47454450f59SHans Verkuil { 475b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 47654450f59SHans Verkuil 477f862f57dSPablo Anton return regmap_write(state->regmap[ADV76XX_PAGE_INFOFRAME], reg, val); 47854450f59SHans Verkuil } 47954450f59SHans Verkuil 48054450f59SHans Verkuil static inline int afe_read(struct v4l2_subdev *sd, u8 reg) 48154450f59SHans Verkuil { 482b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 48354450f59SHans Verkuil 484f862f57dSPablo Anton return adv76xx_read_check(state, ADV76XX_PAGE_AFE, reg); 48554450f59SHans Verkuil } 48654450f59SHans Verkuil 48754450f59SHans Verkuil static inline int afe_write(struct v4l2_subdev *sd, u8 reg, u8 val) 48854450f59SHans Verkuil { 489b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 49054450f59SHans Verkuil 491f862f57dSPablo Anton return regmap_write(state->regmap[ADV76XX_PAGE_AFE], reg, val); 49254450f59SHans Verkuil } 49354450f59SHans Verkuil 49454450f59SHans Verkuil static inline int rep_read(struct v4l2_subdev *sd, u8 reg) 49554450f59SHans Verkuil { 496b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 49754450f59SHans Verkuil 498f862f57dSPablo Anton return adv76xx_read_check(state, ADV76XX_PAGE_REP, reg); 49954450f59SHans Verkuil } 50054450f59SHans Verkuil 50154450f59SHans Verkuil static inline int rep_write(struct v4l2_subdev *sd, u8 reg, u8 val) 50254450f59SHans Verkuil { 503b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 50454450f59SHans Verkuil 505f862f57dSPablo Anton return regmap_write(state->regmap[ADV76XX_PAGE_REP], reg, val); 50654450f59SHans Verkuil } 50754450f59SHans Verkuil 50822d97e56SLaurent Pinchart static inline int rep_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) 50954450f59SHans Verkuil { 51022d97e56SLaurent Pinchart return rep_write(sd, reg, (rep_read(sd, reg) & ~mask) | val); 51154450f59SHans Verkuil } 51254450f59SHans Verkuil 51354450f59SHans Verkuil static inline int edid_read(struct v4l2_subdev *sd, u8 reg) 51454450f59SHans Verkuil { 515b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 51654450f59SHans Verkuil 517f862f57dSPablo Anton return adv76xx_read_check(state, ADV76XX_PAGE_EDID, reg); 51854450f59SHans Verkuil } 51954450f59SHans Verkuil 52054450f59SHans Verkuil static inline int edid_write(struct v4l2_subdev *sd, u8 reg, u8 val) 52154450f59SHans Verkuil { 522b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 52354450f59SHans Verkuil 524f862f57dSPablo Anton return regmap_write(state->regmap[ADV76XX_PAGE_EDID], reg, val); 52554450f59SHans Verkuil } 52654450f59SHans Verkuil 527dd08beb9SMats Randgaard static inline int edid_write_block(struct v4l2_subdev *sd, 528f862f57dSPablo Anton unsigned int total_len, const u8 *val) 529dd08beb9SMats Randgaard { 530b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 531dd08beb9SMats Randgaard int err = 0; 532f862f57dSPablo Anton int i = 0; 533f862f57dSPablo Anton int len = 0; 534dd08beb9SMats Randgaard 535f862f57dSPablo Anton v4l2_dbg(2, debug, sd, "%s: write EDID block (%d byte)\n", 536f862f57dSPablo Anton __func__, total_len); 537dd08beb9SMats Randgaard 538f862f57dSPablo Anton while (!err && i < total_len) { 539f862f57dSPablo Anton len = (total_len - i) > I2C_SMBUS_BLOCK_MAX ? 540f862f57dSPablo Anton I2C_SMBUS_BLOCK_MAX : 541f862f57dSPablo Anton (total_len - i); 542f862f57dSPablo Anton 543f862f57dSPablo Anton err = adv76xx_write_block(state, ADV76XX_PAGE_EDID, 544f862f57dSPablo Anton i, val + i, len); 545f862f57dSPablo Anton i += len; 546f862f57dSPablo Anton } 547f862f57dSPablo Anton 548dd08beb9SMats Randgaard return err; 549dd08beb9SMats Randgaard } 550dd08beb9SMats Randgaard 551b44b2e06SPablo Anton static void adv76xx_set_hpd(struct adv76xx_state *state, unsigned int hpd) 552e9d50e9eSLaurent Pinchart { 553e9d50e9eSLaurent Pinchart unsigned int i; 554e9d50e9eSLaurent Pinchart 555269bd132SUwe Kleine-König for (i = 0; i < state->info->num_dv_ports; ++i) 556e9d50e9eSLaurent Pinchart gpiod_set_value_cansleep(state->hpd_gpio[i], hpd & BIT(i)); 557e9d50e9eSLaurent Pinchart 558b44b2e06SPablo Anton v4l2_subdev_notify(&state->sd, ADV76XX_HOTPLUG, &hpd); 559e9d50e9eSLaurent Pinchart } 560e9d50e9eSLaurent Pinchart 561b44b2e06SPablo Anton static void adv76xx_delayed_work_enable_hotplug(struct work_struct *work) 56254450f59SHans Verkuil { 56354450f59SHans Verkuil struct delayed_work *dwork = to_delayed_work(work); 564b44b2e06SPablo Anton struct adv76xx_state *state = container_of(dwork, struct adv76xx_state, 56554450f59SHans Verkuil delayed_work_enable_hotplug); 56654450f59SHans Verkuil struct v4l2_subdev *sd = &state->sd; 56754450f59SHans Verkuil 56854450f59SHans Verkuil v4l2_dbg(2, debug, sd, "%s: enable hotplug\n", __func__); 56954450f59SHans Verkuil 570b44b2e06SPablo Anton adv76xx_set_hpd(state, state->edid.present); 57154450f59SHans Verkuil } 57254450f59SHans Verkuil 57354450f59SHans Verkuil static inline int hdmi_read(struct v4l2_subdev *sd, u8 reg) 57454450f59SHans Verkuil { 575b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 57654450f59SHans Verkuil 577f862f57dSPablo Anton return adv76xx_read_check(state, ADV76XX_PAGE_HDMI, reg); 57854450f59SHans Verkuil } 57954450f59SHans Verkuil 58051182a94SLaurent Pinchart static u16 hdmi_read16(struct v4l2_subdev *sd, u8 reg, u16 mask) 58151182a94SLaurent Pinchart { 58251182a94SLaurent Pinchart return ((hdmi_read(sd, reg) << 8) | hdmi_read(sd, reg + 1)) & mask; 58351182a94SLaurent Pinchart } 58451182a94SLaurent Pinchart 58554450f59SHans Verkuil static inline int hdmi_write(struct v4l2_subdev *sd, u8 reg, u8 val) 58654450f59SHans Verkuil { 587b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 58854450f59SHans Verkuil 589f862f57dSPablo Anton return regmap_write(state->regmap[ADV76XX_PAGE_HDMI], reg, val); 59054450f59SHans Verkuil } 59154450f59SHans Verkuil 59222d97e56SLaurent Pinchart static inline int hdmi_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) 5934a31a93aSMats Randgaard { 59422d97e56SLaurent Pinchart return hdmi_write(sd, reg, (hdmi_read(sd, reg) & ~mask) | val); 5954a31a93aSMats Randgaard } 5964a31a93aSMats Randgaard 59754450f59SHans Verkuil static inline int test_write(struct v4l2_subdev *sd, u8 reg, u8 val) 59854450f59SHans Verkuil { 599b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 60054450f59SHans Verkuil 601f862f57dSPablo Anton return regmap_write(state->regmap[ADV76XX_PAGE_TEST], reg, val); 60254450f59SHans Verkuil } 60354450f59SHans Verkuil 60454450f59SHans Verkuil static inline int cp_read(struct v4l2_subdev *sd, u8 reg) 60554450f59SHans Verkuil { 606b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 60754450f59SHans Verkuil 608f862f57dSPablo Anton return adv76xx_read_check(state, ADV76XX_PAGE_CP, reg); 60954450f59SHans Verkuil } 61054450f59SHans Verkuil 61151182a94SLaurent Pinchart static u16 cp_read16(struct v4l2_subdev *sd, u8 reg, u16 mask) 61251182a94SLaurent Pinchart { 61351182a94SLaurent Pinchart return ((cp_read(sd, reg) << 8) | cp_read(sd, reg + 1)) & mask; 61451182a94SLaurent Pinchart } 61551182a94SLaurent Pinchart 61654450f59SHans Verkuil static inline int cp_write(struct v4l2_subdev *sd, u8 reg, u8 val) 61754450f59SHans Verkuil { 618b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 61954450f59SHans Verkuil 620f862f57dSPablo Anton return regmap_write(state->regmap[ADV76XX_PAGE_CP], reg, val); 62154450f59SHans Verkuil } 62254450f59SHans Verkuil 62322d97e56SLaurent Pinchart static inline int cp_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) 62454450f59SHans Verkuil { 62522d97e56SLaurent Pinchart return cp_write(sd, reg, (cp_read(sd, reg) & ~mask) | val); 62654450f59SHans Verkuil } 62754450f59SHans Verkuil 62854450f59SHans Verkuil static inline int vdp_read(struct v4l2_subdev *sd, u8 reg) 62954450f59SHans Verkuil { 630b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 63154450f59SHans Verkuil 632f862f57dSPablo Anton return adv76xx_read_check(state, ADV7604_PAGE_VDP, reg); 63354450f59SHans Verkuil } 63454450f59SHans Verkuil 63554450f59SHans Verkuil static inline int vdp_write(struct v4l2_subdev *sd, u8 reg, u8 val) 63654450f59SHans Verkuil { 637b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 63854450f59SHans Verkuil 639f862f57dSPablo Anton return regmap_write(state->regmap[ADV7604_PAGE_VDP], reg, val); 64054450f59SHans Verkuil } 64154450f59SHans Verkuil 642b44b2e06SPablo Anton #define ADV76XX_REG(page, offset) (((page) << 8) | (offset)) 643b44b2e06SPablo Anton #define ADV76XX_REG_SEQ_TERM 0xffff 644d42010a1SLars-Peter Clausen 645d42010a1SLars-Peter Clausen #ifdef CONFIG_VIDEO_ADV_DEBUG 646b44b2e06SPablo Anton static int adv76xx_read_reg(struct v4l2_subdev *sd, unsigned int reg) 647d42010a1SLars-Peter Clausen { 648b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 649d42010a1SLars-Peter Clausen unsigned int page = reg >> 8; 650f862f57dSPablo Anton unsigned int val; 651f862f57dSPablo Anton int err; 652d42010a1SLars-Peter Clausen 653d42010a1SLars-Peter Clausen if (!(BIT(page) & state->info->page_mask)) 654d42010a1SLars-Peter Clausen return -EINVAL; 655d42010a1SLars-Peter Clausen 656d42010a1SLars-Peter Clausen reg &= 0xff; 657f862f57dSPablo Anton err = regmap_read(state->regmap[page], reg, &val); 658d42010a1SLars-Peter Clausen 659f862f57dSPablo Anton return err ? err : val; 660d42010a1SLars-Peter Clausen } 661d42010a1SLars-Peter Clausen #endif 662d42010a1SLars-Peter Clausen 663b44b2e06SPablo Anton static int adv76xx_write_reg(struct v4l2_subdev *sd, unsigned int reg, u8 val) 664d42010a1SLars-Peter Clausen { 665b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 666d42010a1SLars-Peter Clausen unsigned int page = reg >> 8; 667d42010a1SLars-Peter Clausen 668d42010a1SLars-Peter Clausen if (!(BIT(page) & state->info->page_mask)) 669d42010a1SLars-Peter Clausen return -EINVAL; 670d42010a1SLars-Peter Clausen 671d42010a1SLars-Peter Clausen reg &= 0xff; 672d42010a1SLars-Peter Clausen 673f862f57dSPablo Anton return regmap_write(state->regmap[page], reg, val); 674d42010a1SLars-Peter Clausen } 675d42010a1SLars-Peter Clausen 676b44b2e06SPablo Anton static void adv76xx_write_reg_seq(struct v4l2_subdev *sd, 677b44b2e06SPablo Anton const struct adv76xx_reg_seq *reg_seq) 678d42010a1SLars-Peter Clausen { 679d42010a1SLars-Peter Clausen unsigned int i; 680d42010a1SLars-Peter Clausen 681b44b2e06SPablo Anton for (i = 0; reg_seq[i].reg != ADV76XX_REG_SEQ_TERM; i++) 682b44b2e06SPablo Anton adv76xx_write_reg(sd, reg_seq[i].reg, reg_seq[i].val); 683d42010a1SLars-Peter Clausen } 684d42010a1SLars-Peter Clausen 685539b33b0SLaurent Pinchart /* ----------------------------------------------------------------------------- 686539b33b0SLaurent Pinchart * Format helpers 687539b33b0SLaurent Pinchart */ 688539b33b0SLaurent Pinchart 689b44b2e06SPablo Anton static const struct adv76xx_format_info adv7604_formats[] = { 690b44b2e06SPablo Anton { MEDIA_BUS_FMT_RGB888_1X24, ADV76XX_OP_CH_SEL_RGB, true, false, 691b44b2e06SPablo Anton ADV76XX_OP_MODE_SEL_SDR_444 | ADV76XX_OP_FORMAT_SEL_8BIT }, 692b44b2e06SPablo Anton { MEDIA_BUS_FMT_YUYV8_2X8, ADV76XX_OP_CH_SEL_RGB, false, false, 693b44b2e06SPablo Anton ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT }, 694b44b2e06SPablo Anton { MEDIA_BUS_FMT_YVYU8_2X8, ADV76XX_OP_CH_SEL_RGB, false, true, 695b44b2e06SPablo Anton ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT }, 696b44b2e06SPablo Anton { MEDIA_BUS_FMT_YUYV10_2X10, ADV76XX_OP_CH_SEL_RGB, false, false, 697b44b2e06SPablo Anton ADV76XX_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_10BIT }, 698b44b2e06SPablo Anton { MEDIA_BUS_FMT_YVYU10_2X10, ADV76XX_OP_CH_SEL_RGB, false, true, 699b44b2e06SPablo Anton ADV76XX_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_10BIT }, 700b44b2e06SPablo Anton { MEDIA_BUS_FMT_YUYV12_2X12, ADV76XX_OP_CH_SEL_RGB, false, false, 701b44b2e06SPablo Anton ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_12BIT }, 702b44b2e06SPablo Anton { MEDIA_BUS_FMT_YVYU12_2X12, ADV76XX_OP_CH_SEL_RGB, false, true, 703b44b2e06SPablo Anton ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_12BIT }, 704b44b2e06SPablo Anton { MEDIA_BUS_FMT_UYVY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, false, 705b44b2e06SPablo Anton ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT }, 706b44b2e06SPablo Anton { MEDIA_BUS_FMT_VYUY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, true, 707b44b2e06SPablo Anton ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT }, 708b44b2e06SPablo Anton { MEDIA_BUS_FMT_YUYV8_1X16, ADV76XX_OP_CH_SEL_RGB, false, false, 709b44b2e06SPablo Anton ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT }, 710b44b2e06SPablo Anton { MEDIA_BUS_FMT_YVYU8_1X16, ADV76XX_OP_CH_SEL_RGB, false, true, 711b44b2e06SPablo Anton ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT }, 712b44b2e06SPablo Anton { MEDIA_BUS_FMT_UYVY10_1X20, ADV76XX_OP_CH_SEL_RBG, false, false, 713b44b2e06SPablo Anton ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT }, 714b44b2e06SPablo Anton { MEDIA_BUS_FMT_VYUY10_1X20, ADV76XX_OP_CH_SEL_RBG, false, true, 715b44b2e06SPablo Anton ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT }, 716b44b2e06SPablo Anton { MEDIA_BUS_FMT_YUYV10_1X20, ADV76XX_OP_CH_SEL_RGB, false, false, 717b44b2e06SPablo Anton ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT }, 718b44b2e06SPablo Anton { MEDIA_BUS_FMT_YVYU10_1X20, ADV76XX_OP_CH_SEL_RGB, false, true, 719b44b2e06SPablo Anton ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT }, 720b44b2e06SPablo Anton { MEDIA_BUS_FMT_UYVY12_1X24, ADV76XX_OP_CH_SEL_RBG, false, false, 721b44b2e06SPablo Anton ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT }, 722b44b2e06SPablo Anton { MEDIA_BUS_FMT_VYUY12_1X24, ADV76XX_OP_CH_SEL_RBG, false, true, 723b44b2e06SPablo Anton ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT }, 724b44b2e06SPablo Anton { MEDIA_BUS_FMT_YUYV12_1X24, ADV76XX_OP_CH_SEL_RGB, false, false, 725b44b2e06SPablo Anton ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT }, 726b44b2e06SPablo Anton { MEDIA_BUS_FMT_YVYU12_1X24, ADV76XX_OP_CH_SEL_RGB, false, true, 727b44b2e06SPablo Anton ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT }, 728539b33b0SLaurent Pinchart }; 729539b33b0SLaurent Pinchart 730b44b2e06SPablo Anton static const struct adv76xx_format_info adv7611_formats[] = { 731b44b2e06SPablo Anton { MEDIA_BUS_FMT_RGB888_1X24, ADV76XX_OP_CH_SEL_RGB, true, false, 732b44b2e06SPablo Anton ADV76XX_OP_MODE_SEL_SDR_444 | ADV76XX_OP_FORMAT_SEL_8BIT }, 733b44b2e06SPablo Anton { MEDIA_BUS_FMT_YUYV8_2X8, ADV76XX_OP_CH_SEL_RGB, false, false, 734b44b2e06SPablo Anton ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT }, 735b44b2e06SPablo Anton { MEDIA_BUS_FMT_YVYU8_2X8, ADV76XX_OP_CH_SEL_RGB, false, true, 736b44b2e06SPablo Anton ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT }, 737b44b2e06SPablo Anton { MEDIA_BUS_FMT_YUYV12_2X12, ADV76XX_OP_CH_SEL_RGB, false, false, 738b44b2e06SPablo Anton ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_12BIT }, 739b44b2e06SPablo Anton { MEDIA_BUS_FMT_YVYU12_2X12, ADV76XX_OP_CH_SEL_RGB, false, true, 740b44b2e06SPablo Anton ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_12BIT }, 741b44b2e06SPablo Anton { MEDIA_BUS_FMT_UYVY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, false, 742b44b2e06SPablo Anton ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT }, 743b44b2e06SPablo Anton { MEDIA_BUS_FMT_VYUY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, true, 744b44b2e06SPablo Anton ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT }, 745b44b2e06SPablo Anton { MEDIA_BUS_FMT_YUYV8_1X16, ADV76XX_OP_CH_SEL_RGB, false, false, 746b44b2e06SPablo Anton ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT }, 747b44b2e06SPablo Anton { MEDIA_BUS_FMT_YVYU8_1X16, ADV76XX_OP_CH_SEL_RGB, false, true, 748b44b2e06SPablo Anton ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT }, 749b44b2e06SPablo Anton { MEDIA_BUS_FMT_UYVY12_1X24, ADV76XX_OP_CH_SEL_RBG, false, false, 750b44b2e06SPablo Anton ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT }, 751b44b2e06SPablo Anton { MEDIA_BUS_FMT_VYUY12_1X24, ADV76XX_OP_CH_SEL_RBG, false, true, 752b44b2e06SPablo Anton ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT }, 753b44b2e06SPablo Anton { MEDIA_BUS_FMT_YUYV12_1X24, ADV76XX_OP_CH_SEL_RGB, false, false, 754b44b2e06SPablo Anton ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT }, 755b44b2e06SPablo Anton { MEDIA_BUS_FMT_YVYU12_1X24, ADV76XX_OP_CH_SEL_RGB, false, true, 756b44b2e06SPablo Anton ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT }, 757539b33b0SLaurent Pinchart }; 758539b33b0SLaurent Pinchart 7598331d30bSWilliam Towle static const struct adv76xx_format_info adv7612_formats[] = { 7608331d30bSWilliam Towle { MEDIA_BUS_FMT_RGB888_1X24, ADV76XX_OP_CH_SEL_RGB, true, false, 7618331d30bSWilliam Towle ADV76XX_OP_MODE_SEL_SDR_444 | ADV76XX_OP_FORMAT_SEL_8BIT }, 7628331d30bSWilliam Towle { MEDIA_BUS_FMT_YUYV8_2X8, ADV76XX_OP_CH_SEL_RGB, false, false, 7638331d30bSWilliam Towle ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT }, 7648331d30bSWilliam Towle { MEDIA_BUS_FMT_YVYU8_2X8, ADV76XX_OP_CH_SEL_RGB, false, true, 7658331d30bSWilliam Towle ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT }, 7668331d30bSWilliam Towle { MEDIA_BUS_FMT_UYVY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, false, 7678331d30bSWilliam Towle ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT }, 7688331d30bSWilliam Towle { MEDIA_BUS_FMT_VYUY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, true, 7698331d30bSWilliam Towle ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT }, 7708331d30bSWilliam Towle { MEDIA_BUS_FMT_YUYV8_1X16, ADV76XX_OP_CH_SEL_RGB, false, false, 7718331d30bSWilliam Towle ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT }, 7728331d30bSWilliam Towle { MEDIA_BUS_FMT_YVYU8_1X16, ADV76XX_OP_CH_SEL_RGB, false, true, 7738331d30bSWilliam Towle ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT }, 7748331d30bSWilliam Towle }; 7758331d30bSWilliam Towle 776b44b2e06SPablo Anton static const struct adv76xx_format_info * 777b44b2e06SPablo Anton adv76xx_format_info(struct adv76xx_state *state, u32 code) 778539b33b0SLaurent Pinchart { 779539b33b0SLaurent Pinchart unsigned int i; 780539b33b0SLaurent Pinchart 781539b33b0SLaurent Pinchart for (i = 0; i < state->info->nformats; ++i) { 782539b33b0SLaurent Pinchart if (state->info->formats[i].code == code) 783539b33b0SLaurent Pinchart return &state->info->formats[i]; 784539b33b0SLaurent Pinchart } 785539b33b0SLaurent Pinchart 786539b33b0SLaurent Pinchart return NULL; 787539b33b0SLaurent Pinchart } 788539b33b0SLaurent Pinchart 78954450f59SHans Verkuil /* ----------------------------------------------------------------------- */ 79054450f59SHans Verkuil 7914a31a93aSMats Randgaard static inline bool is_analog_input(struct v4l2_subdev *sd) 7924a31a93aSMats Randgaard { 793b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 7944a31a93aSMats Randgaard 795c784b1e2SLaurent Pinchart return state->selected_input == ADV7604_PAD_VGA_RGB || 796c784b1e2SLaurent Pinchart state->selected_input == ADV7604_PAD_VGA_COMP; 7974a31a93aSMats Randgaard } 7984a31a93aSMats Randgaard 7994a31a93aSMats Randgaard static inline bool is_digital_input(struct v4l2_subdev *sd) 8004a31a93aSMats Randgaard { 801b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 8024a31a93aSMats Randgaard 803b44b2e06SPablo Anton return state->selected_input == ADV76XX_PAD_HDMI_PORT_A || 804c784b1e2SLaurent Pinchart state->selected_input == ADV7604_PAD_HDMI_PORT_B || 805c784b1e2SLaurent Pinchart state->selected_input == ADV7604_PAD_HDMI_PORT_C || 806c784b1e2SLaurent Pinchart state->selected_input == ADV7604_PAD_HDMI_PORT_D; 8074a31a93aSMats Randgaard } 8084a31a93aSMats Randgaard 8094a31a93aSMats Randgaard /* ----------------------------------------------------------------------- */ 8104a31a93aSMats Randgaard 81154450f59SHans Verkuil #ifdef CONFIG_VIDEO_ADV_DEBUG 812b44b2e06SPablo Anton static void adv76xx_inv_register(struct v4l2_subdev *sd) 81354450f59SHans Verkuil { 81454450f59SHans Verkuil v4l2_info(sd, "0x000-0x0ff: IO Map\n"); 81554450f59SHans Verkuil v4l2_info(sd, "0x100-0x1ff: AVLink Map\n"); 81654450f59SHans Verkuil v4l2_info(sd, "0x200-0x2ff: CEC Map\n"); 81754450f59SHans Verkuil v4l2_info(sd, "0x300-0x3ff: InfoFrame Map\n"); 81854450f59SHans Verkuil v4l2_info(sd, "0x400-0x4ff: ESDP Map\n"); 81954450f59SHans Verkuil v4l2_info(sd, "0x500-0x5ff: DPP Map\n"); 82054450f59SHans Verkuil v4l2_info(sd, "0x600-0x6ff: AFE Map\n"); 82154450f59SHans Verkuil v4l2_info(sd, "0x700-0x7ff: Repeater Map\n"); 82254450f59SHans Verkuil v4l2_info(sd, "0x800-0x8ff: EDID Map\n"); 82354450f59SHans Verkuil v4l2_info(sd, "0x900-0x9ff: HDMI Map\n"); 82454450f59SHans Verkuil v4l2_info(sd, "0xa00-0xaff: Test Map\n"); 82554450f59SHans Verkuil v4l2_info(sd, "0xb00-0xbff: CP Map\n"); 82654450f59SHans Verkuil v4l2_info(sd, "0xc00-0xcff: VDP Map\n"); 82754450f59SHans Verkuil } 82854450f59SHans Verkuil 829b44b2e06SPablo Anton static int adv76xx_g_register(struct v4l2_subdev *sd, 83054450f59SHans Verkuil struct v4l2_dbg_register *reg) 83154450f59SHans Verkuil { 832d42010a1SLars-Peter Clausen int ret; 833d42010a1SLars-Peter Clausen 834b44b2e06SPablo Anton ret = adv76xx_read_reg(sd, reg->reg); 835d42010a1SLars-Peter Clausen if (ret < 0) { 83654450f59SHans Verkuil v4l2_info(sd, "Register %03llx not supported\n", reg->reg); 837b44b2e06SPablo Anton adv76xx_inv_register(sd); 838d42010a1SLars-Peter Clausen return ret; 83954450f59SHans Verkuil } 840d42010a1SLars-Peter Clausen 841d42010a1SLars-Peter Clausen reg->size = 1; 842d42010a1SLars-Peter Clausen reg->val = ret; 843d42010a1SLars-Peter Clausen 84454450f59SHans Verkuil return 0; 84554450f59SHans Verkuil } 84654450f59SHans Verkuil 847b44b2e06SPablo Anton static int adv76xx_s_register(struct v4l2_subdev *sd, 848977ba3b1SHans Verkuil const struct v4l2_dbg_register *reg) 84954450f59SHans Verkuil { 850d42010a1SLars-Peter Clausen int ret; 8511577461bSHans Verkuil 852b44b2e06SPablo Anton ret = adv76xx_write_reg(sd, reg->reg, reg->val); 853d42010a1SLars-Peter Clausen if (ret < 0) { 85454450f59SHans Verkuil v4l2_info(sd, "Register %03llx not supported\n", reg->reg); 855b44b2e06SPablo Anton adv76xx_inv_register(sd); 856d42010a1SLars-Peter Clausen return ret; 85754450f59SHans Verkuil } 858d42010a1SLars-Peter Clausen 85954450f59SHans Verkuil return 0; 86054450f59SHans Verkuil } 86154450f59SHans Verkuil #endif 86254450f59SHans Verkuil 863d42010a1SLars-Peter Clausen static unsigned int adv7604_read_cable_det(struct v4l2_subdev *sd) 864d42010a1SLars-Peter Clausen { 865d42010a1SLars-Peter Clausen u8 value = io_read(sd, 0x6f); 866d42010a1SLars-Peter Clausen 867d42010a1SLars-Peter Clausen return ((value & 0x10) >> 4) 868d42010a1SLars-Peter Clausen | ((value & 0x08) >> 2) 869d42010a1SLars-Peter Clausen | ((value & 0x04) << 0) 870d42010a1SLars-Peter Clausen | ((value & 0x02) << 2); 871d42010a1SLars-Peter Clausen } 872d42010a1SLars-Peter Clausen 873d42010a1SLars-Peter Clausen static unsigned int adv7611_read_cable_det(struct v4l2_subdev *sd) 874d42010a1SLars-Peter Clausen { 875d42010a1SLars-Peter Clausen u8 value = io_read(sd, 0x6f); 876d42010a1SLars-Peter Clausen 877d42010a1SLars-Peter Clausen return value & 1; 878d42010a1SLars-Peter Clausen } 879d42010a1SLars-Peter Clausen 8807111cdddSWilliam Towle static unsigned int adv7612_read_cable_det(struct v4l2_subdev *sd) 8817111cdddSWilliam Towle { 8827111cdddSWilliam Towle /* Reads CABLE_DET_A_RAW. For input B support, need to 8837111cdddSWilliam Towle * account for bit 7 [MSB] of 0x6a (ie. CABLE_DET_B_RAW) 8847111cdddSWilliam Towle */ 8857111cdddSWilliam Towle u8 value = io_read(sd, 0x6f); 8867111cdddSWilliam Towle 8877111cdddSWilliam Towle return value & 1; 8887111cdddSWilliam Towle } 8897111cdddSWilliam Towle 890b44b2e06SPablo Anton static int adv76xx_s_detect_tx_5v_ctrl(struct v4l2_subdev *sd) 89154450f59SHans Verkuil { 892b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 893b44b2e06SPablo Anton const struct adv76xx_chip_info *info = state->info; 89454450f59SHans Verkuil 89554450f59SHans Verkuil return v4l2_ctrl_s_ctrl(state->detect_tx_5v_ctrl, 896d42010a1SLars-Peter Clausen info->read_cable_det(sd)); 89754450f59SHans Verkuil } 89854450f59SHans Verkuil 899ccbd5bc4SHans Verkuil static int find_and_set_predefined_video_timings(struct v4l2_subdev *sd, 900ccbd5bc4SHans Verkuil u8 prim_mode, 901b44b2e06SPablo Anton const struct adv76xx_video_standards *predef_vid_timings, 902ccbd5bc4SHans Verkuil const struct v4l2_dv_timings *timings) 90354450f59SHans Verkuil { 904ccbd5bc4SHans Verkuil int i; 90554450f59SHans Verkuil 906ccbd5bc4SHans Verkuil for (i = 0; predef_vid_timings[i].timings.bt.width; i++) { 907ef1ed8f5SHans Verkuil if (!v4l2_match_dv_timings(timings, &predef_vid_timings[i].timings, 90885f9e06cSHans Verkuil is_digital_input(sd) ? 250000 : 1000000, false)) 909ccbd5bc4SHans Verkuil continue; 910ccbd5bc4SHans Verkuil io_write(sd, 0x00, predef_vid_timings[i].vid_std); /* video std */ 911ccbd5bc4SHans Verkuil io_write(sd, 0x01, (predef_vid_timings[i].v_freq << 4) + 912ccbd5bc4SHans Verkuil prim_mode); /* v_freq and prim mode */ 913ccbd5bc4SHans Verkuil return 0; 91454450f59SHans Verkuil } 91554450f59SHans Verkuil 916ccbd5bc4SHans Verkuil return -1; 917ccbd5bc4SHans Verkuil } 91854450f59SHans Verkuil 919ccbd5bc4SHans Verkuil static int configure_predefined_video_timings(struct v4l2_subdev *sd, 920ccbd5bc4SHans Verkuil struct v4l2_dv_timings *timings) 921ccbd5bc4SHans Verkuil { 922b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 923ccbd5bc4SHans Verkuil int err; 924ccbd5bc4SHans Verkuil 925ccbd5bc4SHans Verkuil v4l2_dbg(1, debug, sd, "%s", __func__); 926ccbd5bc4SHans Verkuil 927b44b2e06SPablo Anton if (adv76xx_has_afe(state)) { 92854450f59SHans Verkuil /* reset to default values */ 92954450f59SHans Verkuil io_write(sd, 0x16, 0x43); 93054450f59SHans Verkuil io_write(sd, 0x17, 0x5a); 931d42010a1SLars-Peter Clausen } 932ccbd5bc4SHans Verkuil /* disable embedded syncs for auto graphics mode */ 93322d97e56SLaurent Pinchart cp_write_clr_set(sd, 0x81, 0x10, 0x00); 934ccbd5bc4SHans Verkuil cp_write(sd, 0x8f, 0x00); 935ccbd5bc4SHans Verkuil cp_write(sd, 0x90, 0x00); 93654450f59SHans Verkuil cp_write(sd, 0xa2, 0x00); 93754450f59SHans Verkuil cp_write(sd, 0xa3, 0x00); 93854450f59SHans Verkuil cp_write(sd, 0xa4, 0x00); 93954450f59SHans Verkuil cp_write(sd, 0xa5, 0x00); 94054450f59SHans Verkuil cp_write(sd, 0xa6, 0x00); 94154450f59SHans Verkuil cp_write(sd, 0xa7, 0x00); 942ccbd5bc4SHans Verkuil cp_write(sd, 0xab, 0x00); 943ccbd5bc4SHans Verkuil cp_write(sd, 0xac, 0x00); 944ccbd5bc4SHans Verkuil 9454a31a93aSMats Randgaard if (is_analog_input(sd)) { 946ccbd5bc4SHans Verkuil err = find_and_set_predefined_video_timings(sd, 947ccbd5bc4SHans Verkuil 0x01, adv7604_prim_mode_comp, timings); 948ccbd5bc4SHans Verkuil if (err) 949ccbd5bc4SHans Verkuil err = find_and_set_predefined_video_timings(sd, 950ccbd5bc4SHans Verkuil 0x02, adv7604_prim_mode_gr, timings); 9514a31a93aSMats Randgaard } else if (is_digital_input(sd)) { 952ccbd5bc4SHans Verkuil err = find_and_set_predefined_video_timings(sd, 953b44b2e06SPablo Anton 0x05, adv76xx_prim_mode_hdmi_comp, timings); 954ccbd5bc4SHans Verkuil if (err) 955ccbd5bc4SHans Verkuil err = find_and_set_predefined_video_timings(sd, 956b44b2e06SPablo Anton 0x06, adv76xx_prim_mode_hdmi_gr, timings); 9574a31a93aSMats Randgaard } else { 9584a31a93aSMats Randgaard v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n", 9594a31a93aSMats Randgaard __func__, state->selected_input); 960ccbd5bc4SHans Verkuil err = -1; 96154450f59SHans Verkuil } 96254450f59SHans Verkuil 96354450f59SHans Verkuil 964ccbd5bc4SHans Verkuil return err; 965ccbd5bc4SHans Verkuil } 966ccbd5bc4SHans Verkuil 967ccbd5bc4SHans Verkuil static void configure_custom_video_timings(struct v4l2_subdev *sd, 968ccbd5bc4SHans Verkuil const struct v4l2_bt_timings *bt) 969ccbd5bc4SHans Verkuil { 970b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 971ccbd5bc4SHans Verkuil u32 width = htotal(bt); 972ccbd5bc4SHans Verkuil u32 height = vtotal(bt); 973ccbd5bc4SHans Verkuil u16 cp_start_sav = bt->hsync + bt->hbackporch - 4; 974ccbd5bc4SHans Verkuil u16 cp_start_eav = width - bt->hfrontporch; 975ccbd5bc4SHans Verkuil u16 cp_start_vbi = height - bt->vfrontporch; 976ccbd5bc4SHans Verkuil u16 cp_end_vbi = bt->vsync + bt->vbackporch; 977ccbd5bc4SHans Verkuil u16 ch1_fr_ll = (((u32)bt->pixelclock / 100) > 0) ? 978b44b2e06SPablo Anton ((width * (ADV76XX_FSC / 100)) / ((u32)bt->pixelclock / 100)) : 0; 979ccbd5bc4SHans Verkuil const u8 pll[2] = { 980ccbd5bc4SHans Verkuil 0xc0 | ((width >> 8) & 0x1f), 981ccbd5bc4SHans Verkuil width & 0xff 982ccbd5bc4SHans Verkuil }; 983ccbd5bc4SHans Verkuil 984ccbd5bc4SHans Verkuil v4l2_dbg(2, debug, sd, "%s\n", __func__); 985ccbd5bc4SHans Verkuil 9864a31a93aSMats Randgaard if (is_analog_input(sd)) { 987ccbd5bc4SHans Verkuil /* auto graphics */ 988ccbd5bc4SHans Verkuil io_write(sd, 0x00, 0x07); /* video std */ 989ccbd5bc4SHans Verkuil io_write(sd, 0x01, 0x02); /* prim mode */ 990ccbd5bc4SHans Verkuil /* enable embedded syncs for auto graphics mode */ 99122d97e56SLaurent Pinchart cp_write_clr_set(sd, 0x81, 0x10, 0x10); 992ccbd5bc4SHans Verkuil 993ccbd5bc4SHans Verkuil /* Should only be set in auto-graphics mode [REF_02, p. 91-92] */ 994ccbd5bc4SHans Verkuil /* setup PLL_DIV_MAN_EN and PLL_DIV_RATIO */ 995ccbd5bc4SHans Verkuil /* IO-map reg. 0x16 and 0x17 should be written in sequence */ 996f862f57dSPablo Anton if (regmap_raw_write(state->regmap[ADV76XX_PAGE_IO], 997f862f57dSPablo Anton 0x16, pll, 2)) 998ccbd5bc4SHans Verkuil v4l2_err(sd, "writing to reg 0x16 and 0x17 failed\n"); 999ccbd5bc4SHans Verkuil 1000ccbd5bc4SHans Verkuil /* active video - horizontal timing */ 1001ccbd5bc4SHans Verkuil cp_write(sd, 0xa2, (cp_start_sav >> 4) & 0xff); 1002ccbd5bc4SHans Verkuil cp_write(sd, 0xa3, ((cp_start_sav & 0x0f) << 4) | 1003ccbd5bc4SHans Verkuil ((cp_start_eav >> 8) & 0x0f)); 1004ccbd5bc4SHans Verkuil cp_write(sd, 0xa4, cp_start_eav & 0xff); 1005ccbd5bc4SHans Verkuil 1006ccbd5bc4SHans Verkuil /* active video - vertical timing */ 1007ccbd5bc4SHans Verkuil cp_write(sd, 0xa5, (cp_start_vbi >> 4) & 0xff); 1008ccbd5bc4SHans Verkuil cp_write(sd, 0xa6, ((cp_start_vbi & 0xf) << 4) | 1009ccbd5bc4SHans Verkuil ((cp_end_vbi >> 8) & 0xf)); 1010ccbd5bc4SHans Verkuil cp_write(sd, 0xa7, cp_end_vbi & 0xff); 10114a31a93aSMats Randgaard } else if (is_digital_input(sd)) { 1012ccbd5bc4SHans Verkuil /* set default prim_mode/vid_std for HDMI 101339c1cb2bSJonathan McCrohan according to [REF_03, c. 4.2] */ 1014ccbd5bc4SHans Verkuil io_write(sd, 0x00, 0x02); /* video std */ 1015ccbd5bc4SHans Verkuil io_write(sd, 0x01, 0x06); /* prim mode */ 10164a31a93aSMats Randgaard } else { 10174a31a93aSMats Randgaard v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n", 10184a31a93aSMats Randgaard __func__, state->selected_input); 1019ccbd5bc4SHans Verkuil } 1020ccbd5bc4SHans Verkuil 1021ccbd5bc4SHans Verkuil cp_write(sd, 0x8f, (ch1_fr_ll >> 8) & 0x7); 1022ccbd5bc4SHans Verkuil cp_write(sd, 0x90, ch1_fr_ll & 0xff); 1023ccbd5bc4SHans Verkuil cp_write(sd, 0xab, (height >> 4) & 0xff); 1024ccbd5bc4SHans Verkuil cp_write(sd, 0xac, (height & 0x0f) << 4); 1025ccbd5bc4SHans Verkuil } 1026ccbd5bc4SHans Verkuil 1027b44b2e06SPablo Anton static void adv76xx_set_offset(struct v4l2_subdev *sd, bool auto_offset, u16 offset_a, u16 offset_b, u16 offset_c) 10285c6c6349SMats Randgaard { 1029b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 10305c6c6349SMats Randgaard u8 offset_buf[4]; 10315c6c6349SMats Randgaard 10325c6c6349SMats Randgaard if (auto_offset) { 10335c6c6349SMats Randgaard offset_a = 0x3ff; 10345c6c6349SMats Randgaard offset_b = 0x3ff; 10355c6c6349SMats Randgaard offset_c = 0x3ff; 10365c6c6349SMats Randgaard } 10375c6c6349SMats Randgaard 10385c6c6349SMats Randgaard v4l2_dbg(2, debug, sd, "%s: %s offset: a = 0x%x, b = 0x%x, c = 0x%x\n", 10395c6c6349SMats Randgaard __func__, auto_offset ? "Auto" : "Manual", 10405c6c6349SMats Randgaard offset_a, offset_b, offset_c); 10415c6c6349SMats Randgaard 10425c6c6349SMats Randgaard offset_buf[0] = (cp_read(sd, 0x77) & 0xc0) | ((offset_a & 0x3f0) >> 4); 10435c6c6349SMats Randgaard offset_buf[1] = ((offset_a & 0x00f) << 4) | ((offset_b & 0x3c0) >> 6); 10445c6c6349SMats Randgaard offset_buf[2] = ((offset_b & 0x03f) << 2) | ((offset_c & 0x300) >> 8); 10455c6c6349SMats Randgaard offset_buf[3] = offset_c & 0x0ff; 10465c6c6349SMats Randgaard 10475c6c6349SMats Randgaard /* Registers must be written in this order with no i2c access in between */ 1048f862f57dSPablo Anton if (regmap_raw_write(state->regmap[ADV76XX_PAGE_CP], 1049f862f57dSPablo Anton 0x77, offset_buf, 4)) 10505c6c6349SMats Randgaard v4l2_err(sd, "%s: i2c error writing to CP reg 0x77, 0x78, 0x79, 0x7a\n", __func__); 10515c6c6349SMats Randgaard } 10525c6c6349SMats Randgaard 1053b44b2e06SPablo Anton static void adv76xx_set_gain(struct v4l2_subdev *sd, bool auto_gain, u16 gain_a, u16 gain_b, u16 gain_c) 10545c6c6349SMats Randgaard { 1055b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 10565c6c6349SMats Randgaard u8 gain_buf[4]; 10575c6c6349SMats Randgaard u8 gain_man = 1; 10585c6c6349SMats Randgaard u8 agc_mode_man = 1; 10595c6c6349SMats Randgaard 10605c6c6349SMats Randgaard if (auto_gain) { 10615c6c6349SMats Randgaard gain_man = 0; 10625c6c6349SMats Randgaard agc_mode_man = 0; 10635c6c6349SMats Randgaard gain_a = 0x100; 10645c6c6349SMats Randgaard gain_b = 0x100; 10655c6c6349SMats Randgaard gain_c = 0x100; 10665c6c6349SMats Randgaard } 10675c6c6349SMats Randgaard 10685c6c6349SMats Randgaard v4l2_dbg(2, debug, sd, "%s: %s gain: a = 0x%x, b = 0x%x, c = 0x%x\n", 10695c6c6349SMats Randgaard __func__, auto_gain ? "Auto" : "Manual", 10705c6c6349SMats Randgaard gain_a, gain_b, gain_c); 10715c6c6349SMats Randgaard 10725c6c6349SMats Randgaard gain_buf[0] = ((gain_man << 7) | (agc_mode_man << 6) | ((gain_a & 0x3f0) >> 4)); 10735c6c6349SMats Randgaard gain_buf[1] = (((gain_a & 0x00f) << 4) | ((gain_b & 0x3c0) >> 6)); 10745c6c6349SMats Randgaard gain_buf[2] = (((gain_b & 0x03f) << 2) | ((gain_c & 0x300) >> 8)); 10755c6c6349SMats Randgaard gain_buf[3] = ((gain_c & 0x0ff)); 10765c6c6349SMats Randgaard 10775c6c6349SMats Randgaard /* Registers must be written in this order with no i2c access in between */ 1078f862f57dSPablo Anton if (regmap_raw_write(state->regmap[ADV76XX_PAGE_CP], 1079f862f57dSPablo Anton 0x73, gain_buf, 4)) 10805c6c6349SMats Randgaard v4l2_err(sd, "%s: i2c error writing to CP reg 0x73, 0x74, 0x75, 0x76\n", __func__); 10815c6c6349SMats Randgaard } 10825c6c6349SMats Randgaard 108354450f59SHans Verkuil static void set_rgb_quantization_range(struct v4l2_subdev *sd) 108454450f59SHans Verkuil { 1085b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 10865c6c6349SMats Randgaard bool rgb_output = io_read(sd, 0x02) & 0x02; 10875c6c6349SMats Randgaard bool hdmi_signal = hdmi_read(sd, 0x05) & 0x80; 108854450f59SHans Verkuil 10895c6c6349SMats Randgaard v4l2_dbg(2, debug, sd, "%s: RGB quantization range: %d, RGB out: %d, HDMI: %d\n", 10905c6c6349SMats Randgaard __func__, state->rgb_quantization_range, 10915c6c6349SMats Randgaard rgb_output, hdmi_signal); 10925c6c6349SMats Randgaard 1093b44b2e06SPablo Anton adv76xx_set_gain(sd, true, 0x0, 0x0, 0x0); 1094b44b2e06SPablo Anton adv76xx_set_offset(sd, true, 0x0, 0x0, 0x0); 10959833239eSMats Randgaard 109654450f59SHans Verkuil switch (state->rgb_quantization_range) { 109754450f59SHans Verkuil case V4L2_DV_RGB_RANGE_AUTO: 1098c784b1e2SLaurent Pinchart if (state->selected_input == ADV7604_PAD_VGA_RGB) { 10999833239eSMats Randgaard /* Receiving analog RGB signal 11009833239eSMats Randgaard * Set RGB full range (0-255) */ 110122d97e56SLaurent Pinchart io_write_clr_set(sd, 0x02, 0xf0, 0x10); 11029833239eSMats Randgaard break; 11039833239eSMats Randgaard } 110454450f59SHans Verkuil 1105c784b1e2SLaurent Pinchart if (state->selected_input == ADV7604_PAD_VGA_COMP) { 11069833239eSMats Randgaard /* Receiving analog YPbPr signal 11079833239eSMats Randgaard * Set automode */ 110822d97e56SLaurent Pinchart io_write_clr_set(sd, 0x02, 0xf0, 0xf0); 11099833239eSMats Randgaard break; 11109833239eSMats Randgaard } 11119833239eSMats Randgaard 11125c6c6349SMats Randgaard if (hdmi_signal) { 11139833239eSMats Randgaard /* Receiving HDMI signal 11149833239eSMats Randgaard * Set automode */ 111522d97e56SLaurent Pinchart io_write_clr_set(sd, 0x02, 0xf0, 0xf0); 11169833239eSMats Randgaard break; 11179833239eSMats Randgaard } 11189833239eSMats Randgaard 11199833239eSMats Randgaard /* Receiving DVI-D signal 11209833239eSMats Randgaard * ADV7604 selects RGB limited range regardless of 11219833239eSMats Randgaard * input format (CE/IT) in automatic mode */ 1122680fee04SHans Verkuil if (state->timings.bt.flags & V4L2_DV_FL_IS_CE_VIDEO) { 112354450f59SHans Verkuil /* RGB limited range (16-235) */ 112422d97e56SLaurent Pinchart io_write_clr_set(sd, 0x02, 0xf0, 0x00); 112554450f59SHans Verkuil } else { 112654450f59SHans Verkuil /* RGB full range (0-255) */ 112722d97e56SLaurent Pinchart io_write_clr_set(sd, 0x02, 0xf0, 0x10); 11285c6c6349SMats Randgaard 11295c6c6349SMats Randgaard if (is_digital_input(sd) && rgb_output) { 1130b44b2e06SPablo Anton adv76xx_set_offset(sd, false, 0x40, 0x40, 0x40); 11315c6c6349SMats Randgaard } else { 1132b44b2e06SPablo Anton adv76xx_set_gain(sd, false, 0xe0, 0xe0, 0xe0); 1133b44b2e06SPablo Anton adv76xx_set_offset(sd, false, 0x70, 0x70, 0x70); 11345c6c6349SMats Randgaard } 113554450f59SHans Verkuil } 113654450f59SHans Verkuil break; 113754450f59SHans Verkuil case V4L2_DV_RGB_RANGE_LIMITED: 1138c784b1e2SLaurent Pinchart if (state->selected_input == ADV7604_PAD_VGA_COMP) { 1139d261e842SMats Randgaard /* YCrCb limited range (16-235) */ 114022d97e56SLaurent Pinchart io_write_clr_set(sd, 0x02, 0xf0, 0x20); 11415c6c6349SMats Randgaard break; 11425c6c6349SMats Randgaard } 11435c6c6349SMats Randgaard 114454450f59SHans Verkuil /* RGB limited range (16-235) */ 114522d97e56SLaurent Pinchart io_write_clr_set(sd, 0x02, 0xf0, 0x00); 11465c6c6349SMats Randgaard 114754450f59SHans Verkuil break; 114854450f59SHans Verkuil case V4L2_DV_RGB_RANGE_FULL: 1149c784b1e2SLaurent Pinchart if (state->selected_input == ADV7604_PAD_VGA_COMP) { 1150d261e842SMats Randgaard /* YCrCb full range (0-255) */ 115122d97e56SLaurent Pinchart io_write_clr_set(sd, 0x02, 0xf0, 0x60); 11525c6c6349SMats Randgaard break; 11535c6c6349SMats Randgaard } 11545c6c6349SMats Randgaard 115554450f59SHans Verkuil /* RGB full range (0-255) */ 115622d97e56SLaurent Pinchart io_write_clr_set(sd, 0x02, 0xf0, 0x10); 11575c6c6349SMats Randgaard 11585c6c6349SMats Randgaard if (is_analog_input(sd) || hdmi_signal) 11595c6c6349SMats Randgaard break; 11605c6c6349SMats Randgaard 11615c6c6349SMats Randgaard /* Adjust gain/offset for DVI-D signals only */ 11625c6c6349SMats Randgaard if (rgb_output) { 1163b44b2e06SPablo Anton adv76xx_set_offset(sd, false, 0x40, 0x40, 0x40); 11645c6c6349SMats Randgaard } else { 1165b44b2e06SPablo Anton adv76xx_set_gain(sd, false, 0xe0, 0xe0, 0xe0); 1166b44b2e06SPablo Anton adv76xx_set_offset(sd, false, 0x70, 0x70, 0x70); 1167d261e842SMats Randgaard } 116854450f59SHans Verkuil break; 116954450f59SHans Verkuil } 117054450f59SHans Verkuil } 117154450f59SHans Verkuil 1172b44b2e06SPablo Anton static int adv76xx_s_ctrl(struct v4l2_ctrl *ctrl) 117354450f59SHans Verkuil { 1174c269887cSLaurent Pinchart struct v4l2_subdev *sd = 1175b44b2e06SPablo Anton &container_of(ctrl->handler, struct adv76xx_state, hdl)->sd; 1176c269887cSLaurent Pinchart 1177b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 117854450f59SHans Verkuil 117954450f59SHans Verkuil switch (ctrl->id) { 118054450f59SHans Verkuil case V4L2_CID_BRIGHTNESS: 118154450f59SHans Verkuil cp_write(sd, 0x3c, ctrl->val); 118254450f59SHans Verkuil return 0; 118354450f59SHans Verkuil case V4L2_CID_CONTRAST: 118454450f59SHans Verkuil cp_write(sd, 0x3a, ctrl->val); 118554450f59SHans Verkuil return 0; 118654450f59SHans Verkuil case V4L2_CID_SATURATION: 118754450f59SHans Verkuil cp_write(sd, 0x3b, ctrl->val); 118854450f59SHans Verkuil return 0; 118954450f59SHans Verkuil case V4L2_CID_HUE: 119054450f59SHans Verkuil cp_write(sd, 0x3d, ctrl->val); 119154450f59SHans Verkuil return 0; 119254450f59SHans Verkuil case V4L2_CID_DV_RX_RGB_RANGE: 119354450f59SHans Verkuil state->rgb_quantization_range = ctrl->val; 119454450f59SHans Verkuil set_rgb_quantization_range(sd); 119554450f59SHans Verkuil return 0; 119654450f59SHans Verkuil case V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE: 1197b44b2e06SPablo Anton if (!adv76xx_has_afe(state)) 1198d42010a1SLars-Peter Clausen return -EINVAL; 119954450f59SHans Verkuil /* Set the analog sampling phase. This is needed to find the 120054450f59SHans Verkuil best sampling phase for analog video: an application or 120154450f59SHans Verkuil driver has to try a number of phases and analyze the picture 120254450f59SHans Verkuil quality before settling on the best performing phase. */ 120354450f59SHans Verkuil afe_write(sd, 0xc8, ctrl->val); 120454450f59SHans Verkuil return 0; 120554450f59SHans Verkuil case V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL: 120654450f59SHans Verkuil /* Use the default blue color for free running mode, 120754450f59SHans Verkuil or supply your own. */ 120822d97e56SLaurent Pinchart cp_write_clr_set(sd, 0xbf, 0x04, ctrl->val << 2); 120954450f59SHans Verkuil return 0; 121054450f59SHans Verkuil case V4L2_CID_ADV_RX_FREE_RUN_COLOR: 121154450f59SHans Verkuil cp_write(sd, 0xc0, (ctrl->val & 0xff0000) >> 16); 121254450f59SHans Verkuil cp_write(sd, 0xc1, (ctrl->val & 0x00ff00) >> 8); 121354450f59SHans Verkuil cp_write(sd, 0xc2, (u8)(ctrl->val & 0x0000ff)); 121454450f59SHans Verkuil return 0; 121554450f59SHans Verkuil } 121654450f59SHans Verkuil return -EINVAL; 121754450f59SHans Verkuil } 121854450f59SHans Verkuil 121954450f59SHans Verkuil /* ----------------------------------------------------------------------- */ 122054450f59SHans Verkuil 122154450f59SHans Verkuil static inline bool no_power(struct v4l2_subdev *sd) 122254450f59SHans Verkuil { 122354450f59SHans Verkuil /* Entire chip or CP powered off */ 122454450f59SHans Verkuil return io_read(sd, 0x0c) & 0x24; 122554450f59SHans Verkuil } 122654450f59SHans Verkuil 122754450f59SHans Verkuil static inline bool no_signal_tmds(struct v4l2_subdev *sd) 122854450f59SHans Verkuil { 1229b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 12304a31a93aSMats Randgaard 12314a31a93aSMats Randgaard return !(io_read(sd, 0x6a) & (0x10 >> state->selected_input)); 123254450f59SHans Verkuil } 123354450f59SHans Verkuil 123454450f59SHans Verkuil static inline bool no_lock_tmds(struct v4l2_subdev *sd) 123554450f59SHans Verkuil { 1236b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 1237b44b2e06SPablo Anton const struct adv76xx_chip_info *info = state->info; 1238d42010a1SLars-Peter Clausen 1239d42010a1SLars-Peter Clausen return (io_read(sd, 0x6a) & info->tdms_lock_mask) != info->tdms_lock_mask; 124054450f59SHans Verkuil } 124154450f59SHans Verkuil 1242bb88f325SMartin Bugge static inline bool is_hdmi(struct v4l2_subdev *sd) 1243bb88f325SMartin Bugge { 1244bb88f325SMartin Bugge return hdmi_read(sd, 0x05) & 0x80; 1245bb88f325SMartin Bugge } 1246bb88f325SMartin Bugge 124754450f59SHans Verkuil static inline bool no_lock_sspd(struct v4l2_subdev *sd) 124854450f59SHans Verkuil { 1249b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 1250d42010a1SLars-Peter Clausen 1251d42010a1SLars-Peter Clausen /* 1252d42010a1SLars-Peter Clausen * Chips without a AFE don't expose registers for the SSPD, so just assume 1253d42010a1SLars-Peter Clausen * that we have a lock. 1254d42010a1SLars-Peter Clausen */ 1255b44b2e06SPablo Anton if (adv76xx_has_afe(state)) 1256d42010a1SLars-Peter Clausen return false; 1257d42010a1SLars-Peter Clausen 125854450f59SHans Verkuil /* TODO channel 2 */ 125954450f59SHans Verkuil return ((cp_read(sd, 0xb5) & 0xd0) != 0xd0); 126054450f59SHans Verkuil } 126154450f59SHans Verkuil 126254450f59SHans Verkuil static inline bool no_lock_stdi(struct v4l2_subdev *sd) 126354450f59SHans Verkuil { 126454450f59SHans Verkuil /* TODO channel 2 */ 126554450f59SHans Verkuil return !(cp_read(sd, 0xb1) & 0x80); 126654450f59SHans Verkuil } 126754450f59SHans Verkuil 126854450f59SHans Verkuil static inline bool no_signal(struct v4l2_subdev *sd) 126954450f59SHans Verkuil { 127054450f59SHans Verkuil bool ret; 127154450f59SHans Verkuil 127254450f59SHans Verkuil ret = no_power(sd); 127354450f59SHans Verkuil 127454450f59SHans Verkuil ret |= no_lock_stdi(sd); 127554450f59SHans Verkuil ret |= no_lock_sspd(sd); 127654450f59SHans Verkuil 12774a31a93aSMats Randgaard if (is_digital_input(sd)) { 127854450f59SHans Verkuil ret |= no_lock_tmds(sd); 127954450f59SHans Verkuil ret |= no_signal_tmds(sd); 128054450f59SHans Verkuil } 128154450f59SHans Verkuil 128254450f59SHans Verkuil return ret; 128354450f59SHans Verkuil } 128454450f59SHans Verkuil 128554450f59SHans Verkuil static inline bool no_lock_cp(struct v4l2_subdev *sd) 128654450f59SHans Verkuil { 1287b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 1288d42010a1SLars-Peter Clausen 1289b44b2e06SPablo Anton if (!adv76xx_has_afe(state)) 1290d42010a1SLars-Peter Clausen return false; 1291d42010a1SLars-Peter Clausen 129254450f59SHans Verkuil /* CP has detected a non standard number of lines on the incoming 129354450f59SHans Verkuil video compared to what it is configured to receive by s_dv_timings */ 129454450f59SHans Verkuil return io_read(sd, 0x12) & 0x01; 129554450f59SHans Verkuil } 129654450f59SHans Verkuil 129758514625Sjean-michel.hautbois@vodalys.com static inline bool in_free_run(struct v4l2_subdev *sd) 129858514625Sjean-michel.hautbois@vodalys.com { 129958514625Sjean-michel.hautbois@vodalys.com return cp_read(sd, 0xff) & 0x10; 130058514625Sjean-michel.hautbois@vodalys.com } 130158514625Sjean-michel.hautbois@vodalys.com 1302b44b2e06SPablo Anton static int adv76xx_g_input_status(struct v4l2_subdev *sd, u32 *status) 130354450f59SHans Verkuil { 130454450f59SHans Verkuil *status = 0; 130554450f59SHans Verkuil *status |= no_power(sd) ? V4L2_IN_ST_NO_POWER : 0; 130654450f59SHans Verkuil *status |= no_signal(sd) ? V4L2_IN_ST_NO_SIGNAL : 0; 130758514625Sjean-michel.hautbois@vodalys.com if (!in_free_run(sd) && no_lock_cp(sd)) 130858514625Sjean-michel.hautbois@vodalys.com *status |= is_digital_input(sd) ? 130958514625Sjean-michel.hautbois@vodalys.com V4L2_IN_ST_NO_SYNC : V4L2_IN_ST_NO_H_LOCK; 131054450f59SHans Verkuil 131154450f59SHans Verkuil v4l2_dbg(1, debug, sd, "%s: status = 0x%x\n", __func__, *status); 131254450f59SHans Verkuil 131354450f59SHans Verkuil return 0; 131454450f59SHans Verkuil } 131554450f59SHans Verkuil 131654450f59SHans Verkuil /* ----------------------------------------------------------------------- */ 131754450f59SHans Verkuil 131854450f59SHans Verkuil struct stdi_readback { 131954450f59SHans Verkuil u16 bl, lcf, lcvs; 132054450f59SHans Verkuil u8 hs_pol, vs_pol; 132154450f59SHans Verkuil bool interlaced; 132254450f59SHans Verkuil }; 132354450f59SHans Verkuil 132454450f59SHans Verkuil static int stdi2dv_timings(struct v4l2_subdev *sd, 132554450f59SHans Verkuil struct stdi_readback *stdi, 132654450f59SHans Verkuil struct v4l2_dv_timings *timings) 132754450f59SHans Verkuil { 1328b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 1329b44b2e06SPablo Anton u32 hfreq = (ADV76XX_FSC * 8) / stdi->bl; 133054450f59SHans Verkuil u32 pix_clk; 133154450f59SHans Verkuil int i; 133254450f59SHans Verkuil 1333b44b2e06SPablo Anton for (i = 0; adv76xx_timings[i].bt.height; i++) { 1334b44b2e06SPablo Anton if (vtotal(&adv76xx_timings[i].bt) != stdi->lcf + 1) 133554450f59SHans Verkuil continue; 1336b44b2e06SPablo Anton if (adv76xx_timings[i].bt.vsync != stdi->lcvs) 133754450f59SHans Verkuil continue; 133854450f59SHans Verkuil 1339b44b2e06SPablo Anton pix_clk = hfreq * htotal(&adv76xx_timings[i].bt); 134054450f59SHans Verkuil 1341b44b2e06SPablo Anton if ((pix_clk < adv76xx_timings[i].bt.pixelclock + 1000000) && 1342b44b2e06SPablo Anton (pix_clk > adv76xx_timings[i].bt.pixelclock - 1000000)) { 1343b44b2e06SPablo Anton *timings = adv76xx_timings[i]; 134454450f59SHans Verkuil return 0; 134554450f59SHans Verkuil } 134654450f59SHans Verkuil } 134754450f59SHans Verkuil 13485fea1bb7SPrashant Laddha if (v4l2_detect_cvt(stdi->lcf + 1, hfreq, stdi->lcvs, 0, 134954450f59SHans Verkuil (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) | 135054450f59SHans Verkuil (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0), 1351061ddda6SPrashant Laddha false, timings)) 135254450f59SHans Verkuil return 0; 135354450f59SHans Verkuil if (v4l2_detect_gtf(stdi->lcf + 1, hfreq, stdi->lcvs, 135454450f59SHans Verkuil (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) | 135554450f59SHans Verkuil (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0), 1356061ddda6SPrashant Laddha false, state->aspect_ratio, timings)) 135754450f59SHans Verkuil return 0; 135854450f59SHans Verkuil 1359ccbd5bc4SHans Verkuil v4l2_dbg(2, debug, sd, 1360ccbd5bc4SHans Verkuil "%s: No format candidate found for lcvs = %d, lcf=%d, bl = %d, %chsync, %cvsync\n", 1361ccbd5bc4SHans Verkuil __func__, stdi->lcvs, stdi->lcf, stdi->bl, 1362ccbd5bc4SHans Verkuil stdi->hs_pol, stdi->vs_pol); 136354450f59SHans Verkuil return -1; 136454450f59SHans Verkuil } 136554450f59SHans Verkuil 1366d42010a1SLars-Peter Clausen 136754450f59SHans Verkuil static int read_stdi(struct v4l2_subdev *sd, struct stdi_readback *stdi) 136854450f59SHans Verkuil { 1369b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 1370b44b2e06SPablo Anton const struct adv76xx_chip_info *info = state->info; 13714a2ccdd2SLaurent Pinchart u8 polarity; 13724a2ccdd2SLaurent Pinchart 137354450f59SHans Verkuil if (no_lock_stdi(sd) || no_lock_sspd(sd)) { 137454450f59SHans Verkuil v4l2_dbg(2, debug, sd, "%s: STDI and/or SSPD not locked\n", __func__); 137554450f59SHans Verkuil return -1; 137654450f59SHans Verkuil } 137754450f59SHans Verkuil 137854450f59SHans Verkuil /* read STDI */ 137951182a94SLaurent Pinchart stdi->bl = cp_read16(sd, 0xb1, 0x3fff); 1380d42010a1SLars-Peter Clausen stdi->lcf = cp_read16(sd, info->lcf_reg, 0x7ff); 138154450f59SHans Verkuil stdi->lcvs = cp_read(sd, 0xb3) >> 3; 138254450f59SHans Verkuil stdi->interlaced = io_read(sd, 0x12) & 0x10; 138354450f59SHans Verkuil 1384b44b2e06SPablo Anton if (adv76xx_has_afe(state)) { 138554450f59SHans Verkuil /* read SSPD */ 13864a2ccdd2SLaurent Pinchart polarity = cp_read(sd, 0xb5); 13874a2ccdd2SLaurent Pinchart if ((polarity & 0x03) == 0x01) { 13884a2ccdd2SLaurent Pinchart stdi->hs_pol = polarity & 0x10 13894a2ccdd2SLaurent Pinchart ? (polarity & 0x08 ? '+' : '-') : 'x'; 13904a2ccdd2SLaurent Pinchart stdi->vs_pol = polarity & 0x40 13914a2ccdd2SLaurent Pinchart ? (polarity & 0x20 ? '+' : '-') : 'x'; 139254450f59SHans Verkuil } else { 139354450f59SHans Verkuil stdi->hs_pol = 'x'; 139454450f59SHans Verkuil stdi->vs_pol = 'x'; 139554450f59SHans Verkuil } 1396d42010a1SLars-Peter Clausen } else { 1397d42010a1SLars-Peter Clausen polarity = hdmi_read(sd, 0x05); 1398d42010a1SLars-Peter Clausen stdi->hs_pol = polarity & 0x20 ? '+' : '-'; 1399d42010a1SLars-Peter Clausen stdi->vs_pol = polarity & 0x10 ? '+' : '-'; 1400d42010a1SLars-Peter Clausen } 140154450f59SHans Verkuil 140254450f59SHans Verkuil if (no_lock_stdi(sd) || no_lock_sspd(sd)) { 140354450f59SHans Verkuil v4l2_dbg(2, debug, sd, 140454450f59SHans Verkuil "%s: signal lost during readout of STDI/SSPD\n", __func__); 140554450f59SHans Verkuil return -1; 140654450f59SHans Verkuil } 140754450f59SHans Verkuil 140854450f59SHans Verkuil if (stdi->lcf < 239 || stdi->bl < 8 || stdi->bl == 0x3fff) { 140954450f59SHans Verkuil v4l2_dbg(2, debug, sd, "%s: invalid signal\n", __func__); 141054450f59SHans Verkuil memset(stdi, 0, sizeof(struct stdi_readback)); 141154450f59SHans Verkuil return -1; 141254450f59SHans Verkuil } 141354450f59SHans Verkuil 141454450f59SHans Verkuil v4l2_dbg(2, debug, sd, 141554450f59SHans Verkuil "%s: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %chsync, %cvsync, %s\n", 141654450f59SHans Verkuil __func__, stdi->lcf, stdi->bl, stdi->lcvs, 141754450f59SHans Verkuil stdi->hs_pol, stdi->vs_pol, 141854450f59SHans Verkuil stdi->interlaced ? "interlaced" : "progressive"); 141954450f59SHans Verkuil 142054450f59SHans Verkuil return 0; 142154450f59SHans Verkuil } 142254450f59SHans Verkuil 1423b44b2e06SPablo Anton static int adv76xx_enum_dv_timings(struct v4l2_subdev *sd, 142454450f59SHans Verkuil struct v4l2_enum_dv_timings *timings) 142554450f59SHans Verkuil { 1426b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 1427afec5599SLaurent Pinchart 1428b44b2e06SPablo Anton if (timings->index >= ARRAY_SIZE(adv76xx_timings) - 1) 142954450f59SHans Verkuil return -EINVAL; 1430afec5599SLaurent Pinchart 1431afec5599SLaurent Pinchart if (timings->pad >= state->source_pad) 1432afec5599SLaurent Pinchart return -EINVAL; 1433afec5599SLaurent Pinchart 143454450f59SHans Verkuil memset(timings->reserved, 0, sizeof(timings->reserved)); 1435b44b2e06SPablo Anton timings->timings = adv76xx_timings[timings->index]; 143654450f59SHans Verkuil return 0; 143754450f59SHans Verkuil } 143854450f59SHans Verkuil 1439b44b2e06SPablo Anton static int adv76xx_dv_timings_cap(struct v4l2_subdev *sd, 14407515e096SLaurent Pinchart struct v4l2_dv_timings_cap *cap) 1441afec5599SLaurent Pinchart { 1442b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 14437515e096SLaurent Pinchart 14447515e096SLaurent Pinchart if (cap->pad >= state->source_pad) 14457515e096SLaurent Pinchart return -EINVAL; 14467515e096SLaurent Pinchart 1447afec5599SLaurent Pinchart cap->type = V4L2_DV_BT_656_1120; 1448afec5599SLaurent Pinchart cap->bt.max_width = 1920; 1449afec5599SLaurent Pinchart cap->bt.max_height = 1200; 1450afec5599SLaurent Pinchart cap->bt.min_pixelclock = 25000000; 1451afec5599SLaurent Pinchart 14527515e096SLaurent Pinchart switch (cap->pad) { 1453b44b2e06SPablo Anton case ADV76XX_PAD_HDMI_PORT_A: 1454afec5599SLaurent Pinchart case ADV7604_PAD_HDMI_PORT_B: 1455afec5599SLaurent Pinchart case ADV7604_PAD_HDMI_PORT_C: 1456afec5599SLaurent Pinchart case ADV7604_PAD_HDMI_PORT_D: 1457afec5599SLaurent Pinchart cap->bt.max_pixelclock = 225000000; 1458afec5599SLaurent Pinchart break; 1459afec5599SLaurent Pinchart case ADV7604_PAD_VGA_RGB: 1460afec5599SLaurent Pinchart case ADV7604_PAD_VGA_COMP: 1461afec5599SLaurent Pinchart default: 1462afec5599SLaurent Pinchart cap->bt.max_pixelclock = 170000000; 1463afec5599SLaurent Pinchart break; 1464afec5599SLaurent Pinchart } 1465afec5599SLaurent Pinchart 1466afec5599SLaurent Pinchart cap->bt.standards = V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT | 1467afec5599SLaurent Pinchart V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT; 1468afec5599SLaurent Pinchart cap->bt.capabilities = V4L2_DV_BT_CAP_PROGRESSIVE | 1469afec5599SLaurent Pinchart V4L2_DV_BT_CAP_REDUCED_BLANKING | V4L2_DV_BT_CAP_CUSTOM; 1470afec5599SLaurent Pinchart return 0; 1471afec5599SLaurent Pinchart } 1472afec5599SLaurent Pinchart 147354450f59SHans Verkuil /* Fill the optional fields .standards and .flags in struct v4l2_dv_timings 1474b44b2e06SPablo Anton if the format is listed in adv76xx_timings[] */ 1475b44b2e06SPablo Anton static void adv76xx_fill_optional_dv_timings_fields(struct v4l2_subdev *sd, 147654450f59SHans Verkuil struct v4l2_dv_timings *timings) 147754450f59SHans Verkuil { 147854450f59SHans Verkuil int i; 147954450f59SHans Verkuil 1480b44b2e06SPablo Anton for (i = 0; adv76xx_timings[i].bt.width; i++) { 1481b44b2e06SPablo Anton if (v4l2_match_dv_timings(timings, &adv76xx_timings[i], 148285f9e06cSHans Verkuil is_digital_input(sd) ? 250000 : 1000000, false)) { 1483b44b2e06SPablo Anton *timings = adv76xx_timings[i]; 148454450f59SHans Verkuil break; 148554450f59SHans Verkuil } 148654450f59SHans Verkuil } 148754450f59SHans Verkuil } 148854450f59SHans Verkuil 1489d42010a1SLars-Peter Clausen static unsigned int adv7604_read_hdmi_pixelclock(struct v4l2_subdev *sd) 1490d42010a1SLars-Peter Clausen { 1491d42010a1SLars-Peter Clausen unsigned int freq; 1492d42010a1SLars-Peter Clausen int a, b; 1493d42010a1SLars-Peter Clausen 1494d42010a1SLars-Peter Clausen a = hdmi_read(sd, 0x06); 1495d42010a1SLars-Peter Clausen b = hdmi_read(sd, 0x3b); 1496d42010a1SLars-Peter Clausen if (a < 0 || b < 0) 1497d42010a1SLars-Peter Clausen return 0; 1498d42010a1SLars-Peter Clausen freq = a * 1000000 + ((b & 0x30) >> 4) * 250000; 1499d42010a1SLars-Peter Clausen 1500d42010a1SLars-Peter Clausen if (is_hdmi(sd)) { 1501d42010a1SLars-Peter Clausen /* adjust for deep color mode */ 1502d42010a1SLars-Peter Clausen unsigned bits_per_channel = ((hdmi_read(sd, 0x0b) & 0x60) >> 4) + 8; 1503d42010a1SLars-Peter Clausen 1504d42010a1SLars-Peter Clausen freq = freq * 8 / bits_per_channel; 1505d42010a1SLars-Peter Clausen } 1506d42010a1SLars-Peter Clausen 1507d42010a1SLars-Peter Clausen return freq; 1508d42010a1SLars-Peter Clausen } 1509d42010a1SLars-Peter Clausen 1510d42010a1SLars-Peter Clausen static unsigned int adv7611_read_hdmi_pixelclock(struct v4l2_subdev *sd) 1511d42010a1SLars-Peter Clausen { 1512d42010a1SLars-Peter Clausen int a, b; 1513d42010a1SLars-Peter Clausen 1514d42010a1SLars-Peter Clausen a = hdmi_read(sd, 0x51); 1515d42010a1SLars-Peter Clausen b = hdmi_read(sd, 0x52); 1516d42010a1SLars-Peter Clausen if (a < 0 || b < 0) 1517d42010a1SLars-Peter Clausen return 0; 1518d42010a1SLars-Peter Clausen return ((a << 1) | (b >> 7)) * 1000000 + (b & 0x7f) * 1000000 / 128; 1519d42010a1SLars-Peter Clausen } 1520d42010a1SLars-Peter Clausen 1521b44b2e06SPablo Anton static int adv76xx_query_dv_timings(struct v4l2_subdev *sd, 152254450f59SHans Verkuil struct v4l2_dv_timings *timings) 152354450f59SHans Verkuil { 1524b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 1525b44b2e06SPablo Anton const struct adv76xx_chip_info *info = state->info; 152654450f59SHans Verkuil struct v4l2_bt_timings *bt = &timings->bt; 152754450f59SHans Verkuil struct stdi_readback stdi; 152854450f59SHans Verkuil 152954450f59SHans Verkuil if (!timings) 153054450f59SHans Verkuil return -EINVAL; 153154450f59SHans Verkuil 153254450f59SHans Verkuil memset(timings, 0, sizeof(struct v4l2_dv_timings)); 153354450f59SHans Verkuil 153454450f59SHans Verkuil if (no_signal(sd)) { 15351e0b9156SMartin Bugge state->restart_stdi_once = true; 153654450f59SHans Verkuil v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__); 153754450f59SHans Verkuil return -ENOLINK; 153854450f59SHans Verkuil } 153954450f59SHans Verkuil 154054450f59SHans Verkuil /* read STDI */ 154154450f59SHans Verkuil if (read_stdi(sd, &stdi)) { 154254450f59SHans Verkuil v4l2_dbg(1, debug, sd, "%s: STDI/SSPD not locked\n", __func__); 154354450f59SHans Verkuil return -ENOLINK; 154454450f59SHans Verkuil } 154554450f59SHans Verkuil bt->interlaced = stdi.interlaced ? 154654450f59SHans Verkuil V4L2_DV_INTERLACED : V4L2_DV_PROGRESSIVE; 154754450f59SHans Verkuil 15484a31a93aSMats Randgaard if (is_digital_input(sd)) { 154954450f59SHans Verkuil timings->type = V4L2_DV_BT_656_1120; 155054450f59SHans Verkuil 15515380baafSjean-michel.hautbois@vodalys.com bt->width = hdmi_read16(sd, 0x07, info->linewidth_mask); 15525380baafSjean-michel.hautbois@vodalys.com bt->height = hdmi_read16(sd, 0x09, info->field0_height_mask); 1553d42010a1SLars-Peter Clausen bt->pixelclock = info->read_hdmi_pixelclock(sd); 15545380baafSjean-michel.hautbois@vodalys.com bt->hfrontporch = hdmi_read16(sd, 0x20, info->hfrontporch_mask); 15555380baafSjean-michel.hautbois@vodalys.com bt->hsync = hdmi_read16(sd, 0x22, info->hsync_mask); 15565380baafSjean-michel.hautbois@vodalys.com bt->hbackporch = hdmi_read16(sd, 0x24, info->hbackporch_mask); 15575380baafSjean-michel.hautbois@vodalys.com bt->vfrontporch = hdmi_read16(sd, 0x2a, 15585380baafSjean-michel.hautbois@vodalys.com info->field0_vfrontporch_mask) / 2; 15595380baafSjean-michel.hautbois@vodalys.com bt->vsync = hdmi_read16(sd, 0x2e, info->field0_vsync_mask) / 2; 15605380baafSjean-michel.hautbois@vodalys.com bt->vbackporch = hdmi_read16(sd, 0x32, 15615380baafSjean-michel.hautbois@vodalys.com info->field0_vbackporch_mask) / 2; 156254450f59SHans Verkuil bt->polarities = ((hdmi_read(sd, 0x05) & 0x10) ? V4L2_DV_VSYNC_POS_POL : 0) | 156354450f59SHans Verkuil ((hdmi_read(sd, 0x05) & 0x20) ? V4L2_DV_HSYNC_POS_POL : 0); 156454450f59SHans Verkuil if (bt->interlaced == V4L2_DV_INTERLACED) { 15655380baafSjean-michel.hautbois@vodalys.com bt->height += hdmi_read16(sd, 0x0b, 15665380baafSjean-michel.hautbois@vodalys.com info->field1_height_mask); 15675380baafSjean-michel.hautbois@vodalys.com bt->il_vfrontporch = hdmi_read16(sd, 0x2c, 15685380baafSjean-michel.hautbois@vodalys.com info->field1_vfrontporch_mask) / 2; 15695380baafSjean-michel.hautbois@vodalys.com bt->il_vsync = hdmi_read16(sd, 0x30, 15705380baafSjean-michel.hautbois@vodalys.com info->field1_vsync_mask) / 2; 15715380baafSjean-michel.hautbois@vodalys.com bt->il_vbackporch = hdmi_read16(sd, 0x34, 15725380baafSjean-michel.hautbois@vodalys.com info->field1_vbackporch_mask) / 2; 157354450f59SHans Verkuil } 1574b44b2e06SPablo Anton adv76xx_fill_optional_dv_timings_fields(sd, timings); 157554450f59SHans Verkuil } else { 157654450f59SHans Verkuil /* find format 157780939647SHans Verkuil * Since LCVS values are inaccurate [REF_03, p. 275-276], 157854450f59SHans Verkuil * stdi2dv_timings() is called with lcvs +-1 if the first attempt fails. 157954450f59SHans Verkuil */ 158054450f59SHans Verkuil if (!stdi2dv_timings(sd, &stdi, timings)) 158154450f59SHans Verkuil goto found; 158254450f59SHans Verkuil stdi.lcvs += 1; 158354450f59SHans Verkuil v4l2_dbg(1, debug, sd, "%s: lcvs + 1 = %d\n", __func__, stdi.lcvs); 158454450f59SHans Verkuil if (!stdi2dv_timings(sd, &stdi, timings)) 158554450f59SHans Verkuil goto found; 158654450f59SHans Verkuil stdi.lcvs -= 2; 158754450f59SHans Verkuil v4l2_dbg(1, debug, sd, "%s: lcvs - 1 = %d\n", __func__, stdi.lcvs); 158854450f59SHans Verkuil if (stdi2dv_timings(sd, &stdi, timings)) { 1589cf9afb1dSHans Verkuil /* 1590cf9afb1dSHans Verkuil * The STDI block may measure wrong values, especially 1591cf9afb1dSHans Verkuil * for lcvs and lcf. If the driver can not find any 1592cf9afb1dSHans Verkuil * valid timing, the STDI block is restarted to measure 1593cf9afb1dSHans Verkuil * the video timings again. The function will return an 1594cf9afb1dSHans Verkuil * error, but the restart of STDI will generate a new 1595cf9afb1dSHans Verkuil * STDI interrupt and the format detection process will 1596cf9afb1dSHans Verkuil * restart. 1597cf9afb1dSHans Verkuil */ 1598cf9afb1dSHans Verkuil if (state->restart_stdi_once) { 1599cf9afb1dSHans Verkuil v4l2_dbg(1, debug, sd, "%s: restart STDI\n", __func__); 1600cf9afb1dSHans Verkuil /* TODO restart STDI for Sync Channel 2 */ 1601cf9afb1dSHans Verkuil /* enter one-shot mode */ 160222d97e56SLaurent Pinchart cp_write_clr_set(sd, 0x86, 0x06, 0x00); 1603cf9afb1dSHans Verkuil /* trigger STDI restart */ 160422d97e56SLaurent Pinchart cp_write_clr_set(sd, 0x86, 0x06, 0x04); 1605cf9afb1dSHans Verkuil /* reset to continuous mode */ 160622d97e56SLaurent Pinchart cp_write_clr_set(sd, 0x86, 0x06, 0x02); 1607cf9afb1dSHans Verkuil state->restart_stdi_once = false; 1608cf9afb1dSHans Verkuil return -ENOLINK; 1609cf9afb1dSHans Verkuil } 161054450f59SHans Verkuil v4l2_dbg(1, debug, sd, "%s: format not supported\n", __func__); 161154450f59SHans Verkuil return -ERANGE; 161254450f59SHans Verkuil } 1613cf9afb1dSHans Verkuil state->restart_stdi_once = true; 161454450f59SHans Verkuil } 161554450f59SHans Verkuil found: 161654450f59SHans Verkuil 161754450f59SHans Verkuil if (no_signal(sd)) { 161854450f59SHans Verkuil v4l2_dbg(1, debug, sd, "%s: signal lost during readout\n", __func__); 161954450f59SHans Verkuil memset(timings, 0, sizeof(struct v4l2_dv_timings)); 162054450f59SHans Verkuil return -ENOLINK; 162154450f59SHans Verkuil } 162254450f59SHans Verkuil 16234a31a93aSMats Randgaard if ((is_analog_input(sd) && bt->pixelclock > 170000000) || 16244a31a93aSMats Randgaard (is_digital_input(sd) && bt->pixelclock > 225000000)) { 162554450f59SHans Verkuil v4l2_dbg(1, debug, sd, "%s: pixelclock out of range %d\n", 162654450f59SHans Verkuil __func__, (u32)bt->pixelclock); 162754450f59SHans Verkuil return -ERANGE; 162854450f59SHans Verkuil } 162954450f59SHans Verkuil 163054450f59SHans Verkuil if (debug > 1) 1631b44b2e06SPablo Anton v4l2_print_dv_timings(sd->name, "adv76xx_query_dv_timings: ", 163211d034c8SHans Verkuil timings, true); 163354450f59SHans Verkuil 163454450f59SHans Verkuil return 0; 163554450f59SHans Verkuil } 163654450f59SHans Verkuil 1637b44b2e06SPablo Anton static int adv76xx_s_dv_timings(struct v4l2_subdev *sd, 163854450f59SHans Verkuil struct v4l2_dv_timings *timings) 163954450f59SHans Verkuil { 1640b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 164154450f59SHans Verkuil struct v4l2_bt_timings *bt; 1642ccbd5bc4SHans Verkuil int err; 164354450f59SHans Verkuil 164454450f59SHans Verkuil if (!timings) 164554450f59SHans Verkuil return -EINVAL; 164654450f59SHans Verkuil 164785f9e06cSHans Verkuil if (v4l2_match_dv_timings(&state->timings, timings, 0, false)) { 1648d48eb48cSMats Randgaard v4l2_dbg(1, debug, sd, "%s: no change\n", __func__); 1649d48eb48cSMats Randgaard return 0; 1650d48eb48cSMats Randgaard } 1651d48eb48cSMats Randgaard 165254450f59SHans Verkuil bt = &timings->bt; 165354450f59SHans Verkuil 16544a31a93aSMats Randgaard if ((is_analog_input(sd) && bt->pixelclock > 170000000) || 16554a31a93aSMats Randgaard (is_digital_input(sd) && bt->pixelclock > 225000000)) { 165654450f59SHans Verkuil v4l2_dbg(1, debug, sd, "%s: pixelclock out of range %d\n", 165754450f59SHans Verkuil __func__, (u32)bt->pixelclock); 165854450f59SHans Verkuil return -ERANGE; 165954450f59SHans Verkuil } 1660ccbd5bc4SHans Verkuil 1661b44b2e06SPablo Anton adv76xx_fill_optional_dv_timings_fields(sd, timings); 166254450f59SHans Verkuil 166354450f59SHans Verkuil state->timings = *timings; 166454450f59SHans Verkuil 166522d97e56SLaurent Pinchart cp_write_clr_set(sd, 0x91, 0x40, bt->interlaced ? 0x40 : 0x00); 1666ccbd5bc4SHans Verkuil 1667ccbd5bc4SHans Verkuil /* Use prim_mode and vid_std when available */ 1668ccbd5bc4SHans Verkuil err = configure_predefined_video_timings(sd, timings); 1669ccbd5bc4SHans Verkuil if (err) { 1670ccbd5bc4SHans Verkuil /* custom settings when the video format 1671ccbd5bc4SHans Verkuil does not have prim_mode/vid_std */ 1672ccbd5bc4SHans Verkuil configure_custom_video_timings(sd, bt); 1673ccbd5bc4SHans Verkuil } 167454450f59SHans Verkuil 167554450f59SHans Verkuil set_rgb_quantization_range(sd); 167654450f59SHans Verkuil 167754450f59SHans Verkuil if (debug > 1) 1678b44b2e06SPablo Anton v4l2_print_dv_timings(sd->name, "adv76xx_s_dv_timings: ", 167911d034c8SHans Verkuil timings, true); 168054450f59SHans Verkuil return 0; 168154450f59SHans Verkuil } 168254450f59SHans Verkuil 1683b44b2e06SPablo Anton static int adv76xx_g_dv_timings(struct v4l2_subdev *sd, 168454450f59SHans Verkuil struct v4l2_dv_timings *timings) 168554450f59SHans Verkuil { 1686b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 168754450f59SHans Verkuil 168854450f59SHans Verkuil *timings = state->timings; 168954450f59SHans Verkuil return 0; 169054450f59SHans Verkuil } 169154450f59SHans Verkuil 1692d42010a1SLars-Peter Clausen static void adv7604_set_termination(struct v4l2_subdev *sd, bool enable) 1693d42010a1SLars-Peter Clausen { 1694d42010a1SLars-Peter Clausen hdmi_write(sd, 0x01, enable ? 0x00 : 0x78); 1695d42010a1SLars-Peter Clausen } 1696d42010a1SLars-Peter Clausen 1697d42010a1SLars-Peter Clausen static void adv7611_set_termination(struct v4l2_subdev *sd, bool enable) 1698d42010a1SLars-Peter Clausen { 1699d42010a1SLars-Peter Clausen hdmi_write(sd, 0x83, enable ? 0xfe : 0xff); 1700d42010a1SLars-Peter Clausen } 1701d42010a1SLars-Peter Clausen 17026b0d5d34SHans Verkuil static void enable_input(struct v4l2_subdev *sd) 170354450f59SHans Verkuil { 1704b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 17056b0d5d34SHans Verkuil 17064a31a93aSMats Randgaard if (is_analog_input(sd)) { 170754450f59SHans Verkuil io_write(sd, 0x15, 0xb0); /* Disable Tristate of Pins (no audio) */ 17084a31a93aSMats Randgaard } else if (is_digital_input(sd)) { 170922d97e56SLaurent Pinchart hdmi_write_clr_set(sd, 0x00, 0x03, state->selected_input); 1710d42010a1SLars-Peter Clausen state->info->set_termination(sd, true); 171154450f59SHans Verkuil io_write(sd, 0x15, 0xa0); /* Disable Tristate of Pins */ 171222d97e56SLaurent Pinchart hdmi_write_clr_set(sd, 0x1a, 0x10, 0x00); /* Unmute audio */ 17134a31a93aSMats Randgaard } else { 17144a31a93aSMats Randgaard v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n", 17154a31a93aSMats Randgaard __func__, state->selected_input); 171654450f59SHans Verkuil } 171754450f59SHans Verkuil } 171854450f59SHans Verkuil 171954450f59SHans Verkuil static void disable_input(struct v4l2_subdev *sd) 172054450f59SHans Verkuil { 1721b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 1722d42010a1SLars-Peter Clausen 172322d97e56SLaurent Pinchart hdmi_write_clr_set(sd, 0x1a, 0x10, 0x10); /* Mute audio */ 17245474b983SMats Randgaard msleep(16); /* 512 samples with >= 32 kHz sample rate [REF_03, c. 7.16.10] */ 172554450f59SHans Verkuil io_write(sd, 0x15, 0xbe); /* Tristate all outputs from video core */ 1726d42010a1SLars-Peter Clausen state->info->set_termination(sd, false); 172754450f59SHans Verkuil } 172854450f59SHans Verkuil 17296b0d5d34SHans Verkuil static void select_input(struct v4l2_subdev *sd) 173054450f59SHans Verkuil { 1731b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 1732b44b2e06SPablo Anton const struct adv76xx_chip_info *info = state->info; 173354450f59SHans Verkuil 17344a31a93aSMats Randgaard if (is_analog_input(sd)) { 1735b44b2e06SPablo Anton adv76xx_write_reg_seq(sd, info->recommended_settings[0]); 173654450f59SHans Verkuil 173754450f59SHans Verkuil afe_write(sd, 0x00, 0x08); /* power up ADC */ 173854450f59SHans Verkuil afe_write(sd, 0x01, 0x06); /* power up Analog Front End */ 173954450f59SHans Verkuil afe_write(sd, 0xc8, 0x00); /* phase control */ 17404a31a93aSMats Randgaard } else if (is_digital_input(sd)) { 17414a31a93aSMats Randgaard hdmi_write(sd, 0x00, state->selected_input & 0x03); 174254450f59SHans Verkuil 1743b44b2e06SPablo Anton adv76xx_write_reg_seq(sd, info->recommended_settings[1]); 174454450f59SHans Verkuil 1745b44b2e06SPablo Anton if (adv76xx_has_afe(state)) { 174654450f59SHans Verkuil afe_write(sd, 0x00, 0xff); /* power down ADC */ 174754450f59SHans Verkuil afe_write(sd, 0x01, 0xfe); /* power down Analog Front End */ 174854450f59SHans Verkuil afe_write(sd, 0xc8, 0x40); /* phase control */ 1749d42010a1SLars-Peter Clausen } 175054450f59SHans Verkuil 175154450f59SHans Verkuil cp_write(sd, 0x3e, 0x00); /* CP core pre-gain control */ 175254450f59SHans Verkuil cp_write(sd, 0xc3, 0x39); /* CP coast control. Graphics mode */ 175354450f59SHans Verkuil cp_write(sd, 0x40, 0x80); /* CP core pre-gain control. Graphics mode */ 17544a31a93aSMats Randgaard } else { 17554a31a93aSMats Randgaard v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n", 17564a31a93aSMats Randgaard __func__, state->selected_input); 175754450f59SHans Verkuil } 175854450f59SHans Verkuil } 175954450f59SHans Verkuil 1760b44b2e06SPablo Anton static int adv76xx_s_routing(struct v4l2_subdev *sd, 176154450f59SHans Verkuil u32 input, u32 output, u32 config) 176254450f59SHans Verkuil { 1763b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 176454450f59SHans Verkuil 1765ff4f80fdSMats Randgaard v4l2_dbg(2, debug, sd, "%s: input %d, selected input %d", 1766ff4f80fdSMats Randgaard __func__, input, state->selected_input); 1767ff4f80fdSMats Randgaard 1768ff4f80fdSMats Randgaard if (input == state->selected_input) 1769ff4f80fdSMats Randgaard return 0; 177054450f59SHans Verkuil 1771d42010a1SLars-Peter Clausen if (input > state->info->max_port) 1772d42010a1SLars-Peter Clausen return -EINVAL; 1773d42010a1SLars-Peter Clausen 17744a31a93aSMats Randgaard state->selected_input = input; 177554450f59SHans Verkuil 177654450f59SHans Verkuil disable_input(sd); 17776b0d5d34SHans Verkuil select_input(sd); 17786b0d5d34SHans Verkuil enable_input(sd); 177954450f59SHans Verkuil 17806f5bcfc3SLars-Peter Clausen v4l2_subdev_notify_event(sd, &adv76xx_ev_fmt); 17816f5bcfc3SLars-Peter Clausen 178254450f59SHans Verkuil return 0; 178354450f59SHans Verkuil } 178454450f59SHans Verkuil 1785b44b2e06SPablo Anton static int adv76xx_enum_mbus_code(struct v4l2_subdev *sd, 1786f7234138SHans Verkuil struct v4l2_subdev_pad_config *cfg, 1787539b33b0SLaurent Pinchart struct v4l2_subdev_mbus_code_enum *code) 178854450f59SHans Verkuil { 1789b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 179054450f59SHans Verkuil 1791539b33b0SLaurent Pinchart if (code->index >= state->info->nformats) 1792539b33b0SLaurent Pinchart return -EINVAL; 1793539b33b0SLaurent Pinchart 1794539b33b0SLaurent Pinchart code->code = state->info->formats[code->index].code; 1795539b33b0SLaurent Pinchart 1796539b33b0SLaurent Pinchart return 0; 1797539b33b0SLaurent Pinchart } 1798539b33b0SLaurent Pinchart 1799b44b2e06SPablo Anton static void adv76xx_fill_format(struct adv76xx_state *state, 1800539b33b0SLaurent Pinchart struct v4l2_mbus_framefmt *format) 1801539b33b0SLaurent Pinchart { 1802539b33b0SLaurent Pinchart memset(format, 0, sizeof(*format)); 1803539b33b0SLaurent Pinchart 1804539b33b0SLaurent Pinchart format->width = state->timings.bt.width; 1805539b33b0SLaurent Pinchart format->height = state->timings.bt.height; 1806539b33b0SLaurent Pinchart format->field = V4L2_FIELD_NONE; 1807680fee04SHans Verkuil format->colorspace = V4L2_COLORSPACE_SRGB; 1808539b33b0SLaurent Pinchart 1809680fee04SHans Verkuil if (state->timings.bt.flags & V4L2_DV_FL_IS_CE_VIDEO) 1810539b33b0SLaurent Pinchart format->colorspace = (state->timings.bt.height <= 576) ? 181154450f59SHans Verkuil V4L2_COLORSPACE_SMPTE170M : V4L2_COLORSPACE_REC709; 181254450f59SHans Verkuil } 1813539b33b0SLaurent Pinchart 1814539b33b0SLaurent Pinchart /* 1815539b33b0SLaurent Pinchart * Compute the op_ch_sel value required to obtain on the bus the component order 1816539b33b0SLaurent Pinchart * corresponding to the selected format taking into account bus reordering 1817539b33b0SLaurent Pinchart * applied by the board at the output of the device. 1818539b33b0SLaurent Pinchart * 1819539b33b0SLaurent Pinchart * The following table gives the op_ch_value from the format component order 1820539b33b0SLaurent Pinchart * (expressed as op_ch_sel value in column) and the bus reordering (expressed as 1821b44b2e06SPablo Anton * adv76xx_bus_order value in row). 1822539b33b0SLaurent Pinchart * 1823539b33b0SLaurent Pinchart * | GBR(0) GRB(1) BGR(2) RGB(3) BRG(4) RBG(5) 1824539b33b0SLaurent Pinchart * ----------+------------------------------------------------- 1825539b33b0SLaurent Pinchart * RGB (NOP) | GBR GRB BGR RGB BRG RBG 1826539b33b0SLaurent Pinchart * GRB (1-2) | BGR RGB GBR GRB RBG BRG 1827539b33b0SLaurent Pinchart * RBG (2-3) | GRB GBR BRG RBG BGR RGB 1828539b33b0SLaurent Pinchart * BGR (1-3) | RBG BRG RGB BGR GRB GBR 1829539b33b0SLaurent Pinchart * BRG (ROR) | BRG RBG GRB GBR RGB BGR 1830539b33b0SLaurent Pinchart * GBR (ROL) | RGB BGR RBG BRG GBR GRB 1831539b33b0SLaurent Pinchart */ 1832b44b2e06SPablo Anton static unsigned int adv76xx_op_ch_sel(struct adv76xx_state *state) 1833539b33b0SLaurent Pinchart { 1834539b33b0SLaurent Pinchart #define _SEL(a,b,c,d,e,f) { \ 1835b44b2e06SPablo Anton ADV76XX_OP_CH_SEL_##a, ADV76XX_OP_CH_SEL_##b, ADV76XX_OP_CH_SEL_##c, \ 1836b44b2e06SPablo Anton ADV76XX_OP_CH_SEL_##d, ADV76XX_OP_CH_SEL_##e, ADV76XX_OP_CH_SEL_##f } 1837539b33b0SLaurent Pinchart #define _BUS(x) [ADV7604_BUS_ORDER_##x] 1838539b33b0SLaurent Pinchart 1839539b33b0SLaurent Pinchart static const unsigned int op_ch_sel[6][6] = { 1840539b33b0SLaurent Pinchart _BUS(RGB) /* NOP */ = _SEL(GBR, GRB, BGR, RGB, BRG, RBG), 1841539b33b0SLaurent Pinchart _BUS(GRB) /* 1-2 */ = _SEL(BGR, RGB, GBR, GRB, RBG, BRG), 1842539b33b0SLaurent Pinchart _BUS(RBG) /* 2-3 */ = _SEL(GRB, GBR, BRG, RBG, BGR, RGB), 1843539b33b0SLaurent Pinchart _BUS(BGR) /* 1-3 */ = _SEL(RBG, BRG, RGB, BGR, GRB, GBR), 1844539b33b0SLaurent Pinchart _BUS(BRG) /* ROR */ = _SEL(BRG, RBG, GRB, GBR, RGB, BGR), 1845539b33b0SLaurent Pinchart _BUS(GBR) /* ROL */ = _SEL(RGB, BGR, RBG, BRG, GBR, GRB), 1846539b33b0SLaurent Pinchart }; 1847539b33b0SLaurent Pinchart 1848539b33b0SLaurent Pinchart return op_ch_sel[state->pdata.bus_order][state->format->op_ch_sel >> 5]; 1849539b33b0SLaurent Pinchart } 1850539b33b0SLaurent Pinchart 1851b44b2e06SPablo Anton static void adv76xx_setup_format(struct adv76xx_state *state) 1852539b33b0SLaurent Pinchart { 1853539b33b0SLaurent Pinchart struct v4l2_subdev *sd = &state->sd; 1854539b33b0SLaurent Pinchart 185522d97e56SLaurent Pinchart io_write_clr_set(sd, 0x02, 0x02, 1856b44b2e06SPablo Anton state->format->rgb_out ? ADV76XX_RGB_OUT : 0); 1857539b33b0SLaurent Pinchart io_write(sd, 0x03, state->format->op_format_sel | 1858539b33b0SLaurent Pinchart state->pdata.op_format_mode_sel); 1859b44b2e06SPablo Anton io_write_clr_set(sd, 0x04, 0xe0, adv76xx_op_ch_sel(state)); 186022d97e56SLaurent Pinchart io_write_clr_set(sd, 0x05, 0x01, 1861b44b2e06SPablo Anton state->format->swap_cb_cr ? ADV76XX_OP_SWAP_CB_CR : 0); 1862539b33b0SLaurent Pinchart } 1863539b33b0SLaurent Pinchart 1864f7234138SHans Verkuil static int adv76xx_get_format(struct v4l2_subdev *sd, 1865f7234138SHans Verkuil struct v4l2_subdev_pad_config *cfg, 1866539b33b0SLaurent Pinchart struct v4l2_subdev_format *format) 1867539b33b0SLaurent Pinchart { 1868b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 1869539b33b0SLaurent Pinchart 1870539b33b0SLaurent Pinchart if (format->pad != state->source_pad) 1871539b33b0SLaurent Pinchart return -EINVAL; 1872539b33b0SLaurent Pinchart 1873b44b2e06SPablo Anton adv76xx_fill_format(state, &format->format); 1874539b33b0SLaurent Pinchart 1875539b33b0SLaurent Pinchart if (format->which == V4L2_SUBDEV_FORMAT_TRY) { 1876539b33b0SLaurent Pinchart struct v4l2_mbus_framefmt *fmt; 1877539b33b0SLaurent Pinchart 1878f7234138SHans Verkuil fmt = v4l2_subdev_get_try_format(sd, cfg, format->pad); 1879539b33b0SLaurent Pinchart format->format.code = fmt->code; 1880539b33b0SLaurent Pinchart } else { 1881539b33b0SLaurent Pinchart format->format.code = state->format->code; 1882539b33b0SLaurent Pinchart } 1883539b33b0SLaurent Pinchart 1884539b33b0SLaurent Pinchart return 0; 1885539b33b0SLaurent Pinchart } 1886539b33b0SLaurent Pinchart 1887f7234138SHans Verkuil static int adv76xx_set_format(struct v4l2_subdev *sd, 1888f7234138SHans Verkuil struct v4l2_subdev_pad_config *cfg, 1889539b33b0SLaurent Pinchart struct v4l2_subdev_format *format) 1890539b33b0SLaurent Pinchart { 1891b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 1892b44b2e06SPablo Anton const struct adv76xx_format_info *info; 1893539b33b0SLaurent Pinchart 1894539b33b0SLaurent Pinchart if (format->pad != state->source_pad) 1895539b33b0SLaurent Pinchart return -EINVAL; 1896539b33b0SLaurent Pinchart 1897b44b2e06SPablo Anton info = adv76xx_format_info(state, format->format.code); 1898539b33b0SLaurent Pinchart if (info == NULL) 1899b44b2e06SPablo Anton info = adv76xx_format_info(state, MEDIA_BUS_FMT_YUYV8_2X8); 1900539b33b0SLaurent Pinchart 1901b44b2e06SPablo Anton adv76xx_fill_format(state, &format->format); 1902539b33b0SLaurent Pinchart format->format.code = info->code; 1903539b33b0SLaurent Pinchart 1904539b33b0SLaurent Pinchart if (format->which == V4L2_SUBDEV_FORMAT_TRY) { 1905539b33b0SLaurent Pinchart struct v4l2_mbus_framefmt *fmt; 1906539b33b0SLaurent Pinchart 1907f7234138SHans Verkuil fmt = v4l2_subdev_get_try_format(sd, cfg, format->pad); 1908539b33b0SLaurent Pinchart fmt->code = format->format.code; 1909539b33b0SLaurent Pinchart } else { 1910539b33b0SLaurent Pinchart state->format = info; 1911b44b2e06SPablo Anton adv76xx_setup_format(state); 1912539b33b0SLaurent Pinchart } 1913539b33b0SLaurent Pinchart 191454450f59SHans Verkuil return 0; 191554450f59SHans Verkuil } 191654450f59SHans Verkuil 1917b44b2e06SPablo Anton static int adv76xx_isr(struct v4l2_subdev *sd, u32 status, bool *handled) 191854450f59SHans Verkuil { 1919b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 1920b44b2e06SPablo Anton const struct adv76xx_chip_info *info = state->info; 1921f24d229cSMats Randgaard const u8 irq_reg_0x43 = io_read(sd, 0x43); 1922f24d229cSMats Randgaard const u8 irq_reg_0x6b = io_read(sd, 0x6b); 1923f24d229cSMats Randgaard const u8 irq_reg_0x70 = io_read(sd, 0x70); 1924f24d229cSMats Randgaard u8 fmt_change_digital; 1925f24d229cSMats Randgaard u8 fmt_change; 1926f24d229cSMats Randgaard u8 tx_5v; 1927f24d229cSMats Randgaard 1928f24d229cSMats Randgaard if (irq_reg_0x43) 1929f24d229cSMats Randgaard io_write(sd, 0x44, irq_reg_0x43); 1930f24d229cSMats Randgaard if (irq_reg_0x70) 1931f24d229cSMats Randgaard io_write(sd, 0x71, irq_reg_0x70); 1932f24d229cSMats Randgaard if (irq_reg_0x6b) 1933f24d229cSMats Randgaard io_write(sd, 0x6c, irq_reg_0x6b); 193454450f59SHans Verkuil 1935ff4f80fdSMats Randgaard v4l2_dbg(2, debug, sd, "%s: ", __func__); 1936ff4f80fdSMats Randgaard 193754450f59SHans Verkuil /* format change */ 1938f24d229cSMats Randgaard fmt_change = irq_reg_0x43 & 0x98; 1939d42010a1SLars-Peter Clausen fmt_change_digital = is_digital_input(sd) 1940d42010a1SLars-Peter Clausen ? irq_reg_0x6b & info->fmt_change_digital_mask 1941d42010a1SLars-Peter Clausen : 0; 194214d03233SMats Randgaard 194354450f59SHans Verkuil if (fmt_change || fmt_change_digital) { 194454450f59SHans Verkuil v4l2_dbg(1, debug, sd, 194525a64ac9SMats Randgaard "%s: fmt_change = 0x%x, fmt_change_digital = 0x%x\n", 194654450f59SHans Verkuil __func__, fmt_change, fmt_change_digital); 194725a64ac9SMats Randgaard 19486f5bcfc3SLars-Peter Clausen v4l2_subdev_notify_event(sd, &adv76xx_ev_fmt); 194925a64ac9SMats Randgaard 195054450f59SHans Verkuil if (handled) 195154450f59SHans Verkuil *handled = true; 195254450f59SHans Verkuil } 1953f24d229cSMats Randgaard /* HDMI/DVI mode */ 1954f24d229cSMats Randgaard if (irq_reg_0x6b & 0x01) { 1955f24d229cSMats Randgaard v4l2_dbg(1, debug, sd, "%s: irq %s mode\n", __func__, 1956f24d229cSMats Randgaard (io_read(sd, 0x6a) & 0x01) ? "HDMI" : "DVI"); 1957f24d229cSMats Randgaard set_rgb_quantization_range(sd); 1958f24d229cSMats Randgaard if (handled) 1959f24d229cSMats Randgaard *handled = true; 1960f24d229cSMats Randgaard } 1961f24d229cSMats Randgaard 196254450f59SHans Verkuil /* tx 5v detect */ 1963d42010a1SLars-Peter Clausen tx_5v = io_read(sd, 0x70) & info->cable_det_mask; 196454450f59SHans Verkuil if (tx_5v) { 196554450f59SHans Verkuil v4l2_dbg(1, debug, sd, "%s: tx_5v: 0x%x\n", __func__, tx_5v); 196654450f59SHans Verkuil io_write(sd, 0x71, tx_5v); 1967b44b2e06SPablo Anton adv76xx_s_detect_tx_5v_ctrl(sd); 196854450f59SHans Verkuil if (handled) 196954450f59SHans Verkuil *handled = true; 197054450f59SHans Verkuil } 197154450f59SHans Verkuil return 0; 197254450f59SHans Verkuil } 197354450f59SHans Verkuil 1974b44b2e06SPablo Anton static int adv76xx_get_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid) 197554450f59SHans Verkuil { 1976b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 19774a31a93aSMats Randgaard u8 *data = NULL; 197854450f59SHans Verkuil 1979dd9ac11aSHans Verkuil memset(edid->reserved, 0, sizeof(edid->reserved)); 19804a31a93aSMats Randgaard 19814a31a93aSMats Randgaard switch (edid->pad) { 1982b44b2e06SPablo Anton case ADV76XX_PAD_HDMI_PORT_A: 1983c784b1e2SLaurent Pinchart case ADV7604_PAD_HDMI_PORT_B: 1984c784b1e2SLaurent Pinchart case ADV7604_PAD_HDMI_PORT_C: 1985c784b1e2SLaurent Pinchart case ADV7604_PAD_HDMI_PORT_D: 19864a31a93aSMats Randgaard if (state->edid.present & (1 << edid->pad)) 19874a31a93aSMats Randgaard data = state->edid.edid; 19884a31a93aSMats Randgaard break; 19894a31a93aSMats Randgaard default: 19904a31a93aSMats Randgaard return -EINVAL; 19914a31a93aSMats Randgaard } 1992dd9ac11aSHans Verkuil 1993dd9ac11aSHans Verkuil if (edid->start_block == 0 && edid->blocks == 0) { 1994dd9ac11aSHans Verkuil edid->blocks = data ? state->edid.blocks : 0; 1995dd9ac11aSHans Verkuil return 0; 1996dd9ac11aSHans Verkuil } 1997dd9ac11aSHans Verkuil 1998dd9ac11aSHans Verkuil if (data == NULL) 19994a31a93aSMats Randgaard return -ENODATA; 20004a31a93aSMats Randgaard 2001dd9ac11aSHans Verkuil if (edid->start_block >= state->edid.blocks) 2002dd9ac11aSHans Verkuil return -EINVAL; 2003dd9ac11aSHans Verkuil 2004dd9ac11aSHans Verkuil if (edid->start_block + edid->blocks > state->edid.blocks) 2005dd9ac11aSHans Verkuil edid->blocks = state->edid.blocks - edid->start_block; 2006dd9ac11aSHans Verkuil 2007dd9ac11aSHans Verkuil memcpy(edid->edid, data + edid->start_block * 128, edid->blocks * 128); 2008dd9ac11aSHans Verkuil 200954450f59SHans Verkuil return 0; 201054450f59SHans Verkuil } 201154450f59SHans Verkuil 2012dd08beb9SMats Randgaard static int get_edid_spa_location(const u8 *edid) 20133e86aa85SMats Randgaard { 20143e86aa85SMats Randgaard u8 d; 20153e86aa85SMats Randgaard 20163e86aa85SMats Randgaard if ((edid[0x7e] != 1) || 20173e86aa85SMats Randgaard (edid[0x80] != 0x02) || 20183e86aa85SMats Randgaard (edid[0x81] != 0x03)) { 20193e86aa85SMats Randgaard return -1; 20203e86aa85SMats Randgaard } 20213e86aa85SMats Randgaard 20223e86aa85SMats Randgaard /* search Vendor Specific Data Block (tag 3) */ 20233e86aa85SMats Randgaard d = edid[0x82] & 0x7f; 20243e86aa85SMats Randgaard if (d > 4) { 20253e86aa85SMats Randgaard int i = 0x84; 20263e86aa85SMats Randgaard int end = 0x80 + d; 20273e86aa85SMats Randgaard 20283e86aa85SMats Randgaard do { 20293e86aa85SMats Randgaard u8 tag = edid[i] >> 5; 20303e86aa85SMats Randgaard u8 len = edid[i] & 0x1f; 20313e86aa85SMats Randgaard 20323e86aa85SMats Randgaard if ((tag == 3) && (len >= 5)) 20333e86aa85SMats Randgaard return i + 4; 20343e86aa85SMats Randgaard i += len + 1; 20353e86aa85SMats Randgaard } while (i < end); 20363e86aa85SMats Randgaard } 20373e86aa85SMats Randgaard return -1; 20383e86aa85SMats Randgaard } 20393e86aa85SMats Randgaard 2040b44b2e06SPablo Anton static int adv76xx_set_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid) 204154450f59SHans Verkuil { 2042b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 2043b44b2e06SPablo Anton const struct adv76xx_chip_info *info = state->info; 2044dd08beb9SMats Randgaard int spa_loc; 204554450f59SHans Verkuil int err; 2046dd08beb9SMats Randgaard int i; 204754450f59SHans Verkuil 2048dd9ac11aSHans Verkuil memset(edid->reserved, 0, sizeof(edid->reserved)); 2049dd9ac11aSHans Verkuil 2050c784b1e2SLaurent Pinchart if (edid->pad > ADV7604_PAD_HDMI_PORT_D) 205154450f59SHans Verkuil return -EINVAL; 205254450f59SHans Verkuil if (edid->start_block != 0) 205354450f59SHans Verkuil return -EINVAL; 205454450f59SHans Verkuil if (edid->blocks == 0) { 20553e86aa85SMats Randgaard /* Disable hotplug and I2C access to EDID RAM from DDC port */ 20564a31a93aSMats Randgaard state->edid.present &= ~(1 << edid->pad); 2057b44b2e06SPablo Anton adv76xx_set_hpd(state, state->edid.present); 205822d97e56SLaurent Pinchart rep_write_clr_set(sd, info->edid_enable_reg, 0x0f, state->edid.present); 20593e86aa85SMats Randgaard 206054450f59SHans Verkuil /* Fall back to a 16:9 aspect ratio */ 206154450f59SHans Verkuil state->aspect_ratio.numerator = 16; 206254450f59SHans Verkuil state->aspect_ratio.denominator = 9; 20633e86aa85SMats Randgaard 20643e86aa85SMats Randgaard if (!state->edid.present) 20653e86aa85SMats Randgaard state->edid.blocks = 0; 20663e86aa85SMats Randgaard 20673e86aa85SMats Randgaard v4l2_dbg(2, debug, sd, "%s: clear EDID pad %d, edid.present = 0x%x\n", 20683e86aa85SMats Randgaard __func__, edid->pad, state->edid.present); 206954450f59SHans Verkuil return 0; 207054450f59SHans Verkuil } 20714a31a93aSMats Randgaard if (edid->blocks > 2) { 20724a31a93aSMats Randgaard edid->blocks = 2; 207354450f59SHans Verkuil return -E2BIG; 20744a31a93aSMats Randgaard } 20754a31a93aSMats Randgaard 2076dd08beb9SMats Randgaard v4l2_dbg(2, debug, sd, "%s: write EDID pad %d, edid.present = 0x%x\n", 2077dd08beb9SMats Randgaard __func__, edid->pad, state->edid.present); 2078dd08beb9SMats Randgaard 20793e86aa85SMats Randgaard /* Disable hotplug and I2C access to EDID RAM from DDC port */ 20804a31a93aSMats Randgaard cancel_delayed_work_sync(&state->delayed_work_enable_hotplug); 2081b44b2e06SPablo Anton adv76xx_set_hpd(state, 0); 208222d97e56SLaurent Pinchart rep_write_clr_set(sd, info->edid_enable_reg, 0x0f, 0x00); 20833e86aa85SMats Randgaard 2084dd08beb9SMats Randgaard spa_loc = get_edid_spa_location(edid->edid); 2085dd08beb9SMats Randgaard if (spa_loc < 0) 2086dd08beb9SMats Randgaard spa_loc = 0xc0; /* Default value [REF_02, p. 116] */ 2087dd08beb9SMats Randgaard 20883e86aa85SMats Randgaard switch (edid->pad) { 2089b44b2e06SPablo Anton case ADV76XX_PAD_HDMI_PORT_A: 2090dd08beb9SMats Randgaard state->spa_port_a[0] = edid->edid[spa_loc]; 2091dd08beb9SMats Randgaard state->spa_port_a[1] = edid->edid[spa_loc + 1]; 20923e86aa85SMats Randgaard break; 2093c784b1e2SLaurent Pinchart case ADV7604_PAD_HDMI_PORT_B: 2094dd08beb9SMats Randgaard rep_write(sd, 0x70, edid->edid[spa_loc]); 2095dd08beb9SMats Randgaard rep_write(sd, 0x71, edid->edid[spa_loc + 1]); 20963e86aa85SMats Randgaard break; 2097c784b1e2SLaurent Pinchart case ADV7604_PAD_HDMI_PORT_C: 2098dd08beb9SMats Randgaard rep_write(sd, 0x72, edid->edid[spa_loc]); 2099dd08beb9SMats Randgaard rep_write(sd, 0x73, edid->edid[spa_loc + 1]); 21003e86aa85SMats Randgaard break; 2101c784b1e2SLaurent Pinchart case ADV7604_PAD_HDMI_PORT_D: 2102dd08beb9SMats Randgaard rep_write(sd, 0x74, edid->edid[spa_loc]); 2103dd08beb9SMats Randgaard rep_write(sd, 0x75, edid->edid[spa_loc + 1]); 21043e86aa85SMats Randgaard break; 2105dd08beb9SMats Randgaard default: 2106dd08beb9SMats Randgaard return -EINVAL; 21073e86aa85SMats Randgaard } 2108d42010a1SLars-Peter Clausen 2109d42010a1SLars-Peter Clausen if (info->type == ADV7604) { 2110dd08beb9SMats Randgaard rep_write(sd, 0x76, spa_loc & 0xff); 211122d97e56SLaurent Pinchart rep_write_clr_set(sd, 0x77, 0x40, (spa_loc & 0x100) >> 2); 2112d42010a1SLars-Peter Clausen } else { 2113d42010a1SLars-Peter Clausen /* FIXME: Where is the SPA location LSB register ? */ 211422d97e56SLaurent Pinchart rep_write_clr_set(sd, 0x71, 0x01, (spa_loc & 0x100) >> 8); 2115d42010a1SLars-Peter Clausen } 21163e86aa85SMats Randgaard 2117dd08beb9SMats Randgaard edid->edid[spa_loc] = state->spa_port_a[0]; 2118dd08beb9SMats Randgaard edid->edid[spa_loc + 1] = state->spa_port_a[1]; 21194a31a93aSMats Randgaard 21204a31a93aSMats Randgaard memcpy(state->edid.edid, edid->edid, 128 * edid->blocks); 21214a31a93aSMats Randgaard state->edid.blocks = edid->blocks; 212254450f59SHans Verkuil state->aspect_ratio = v4l2_calc_aspect_ratio(edid->edid[0x15], 212354450f59SHans Verkuil edid->edid[0x16]); 21243e86aa85SMats Randgaard state->edid.present |= 1 << edid->pad; 21254a31a93aSMats Randgaard 21264a31a93aSMats Randgaard err = edid_write_block(sd, 128 * edid->blocks, state->edid.edid); 21274a31a93aSMats Randgaard if (err < 0) { 21283e86aa85SMats Randgaard v4l2_err(sd, "error %d writing edid pad %d\n", err, edid->pad); 212954450f59SHans Verkuil return err; 213054450f59SHans Verkuil } 213154450f59SHans Verkuil 2132b44b2e06SPablo Anton /* adv76xx calculates the checksums and enables I2C access to internal 2133dd08beb9SMats Randgaard EDID RAM from DDC port. */ 213422d97e56SLaurent Pinchart rep_write_clr_set(sd, info->edid_enable_reg, 0x0f, state->edid.present); 2135dd08beb9SMats Randgaard 2136dd08beb9SMats Randgaard for (i = 0; i < 1000; i++) { 2137d42010a1SLars-Peter Clausen if (rep_read(sd, info->edid_status_reg) & state->edid.present) 2138dd08beb9SMats Randgaard break; 2139dd08beb9SMats Randgaard mdelay(1); 2140dd08beb9SMats Randgaard } 2141dd08beb9SMats Randgaard if (i == 1000) { 2142dd08beb9SMats Randgaard v4l2_err(sd, "error enabling edid (0x%x)\n", state->edid.present); 2143dd08beb9SMats Randgaard return -EIO; 2144dd08beb9SMats Randgaard } 2145dd08beb9SMats Randgaard 21464a31a93aSMats Randgaard /* enable hotplug after 100 ms */ 21474a31a93aSMats Randgaard queue_delayed_work(state->work_queues, 21484a31a93aSMats Randgaard &state->delayed_work_enable_hotplug, HZ / 10); 21494a31a93aSMats Randgaard return 0; 21504a31a93aSMats Randgaard } 21514a31a93aSMats Randgaard 215254450f59SHans Verkuil /*********** avi info frame CEA-861-E **************/ 215354450f59SHans Verkuil 2154516613c1SHans Verkuil static const struct adv76xx_cfg_read_infoframe adv76xx_cri[] = { 2155516613c1SHans Verkuil { "AVI", 0x01, 0xe0, 0x00 }, 2156516613c1SHans Verkuil { "Audio", 0x02, 0xe3, 0x1c }, 2157516613c1SHans Verkuil { "SDP", 0x04, 0xe6, 0x2a }, 2158516613c1SHans Verkuil { "Vendor", 0x10, 0xec, 0x54 } 2159516613c1SHans Verkuil }; 2160516613c1SHans Verkuil 2161516613c1SHans Verkuil static int adv76xx_read_infoframe(struct v4l2_subdev *sd, int index, 2162516613c1SHans Verkuil union hdmi_infoframe *frame) 2163516613c1SHans Verkuil { 2164516613c1SHans Verkuil uint8_t buffer[32]; 2165516613c1SHans Verkuil u8 len; 2166516613c1SHans Verkuil int i; 2167516613c1SHans Verkuil 2168516613c1SHans Verkuil if (!(io_read(sd, 0x60) & adv76xx_cri[index].present_mask)) { 2169516613c1SHans Verkuil v4l2_info(sd, "%s infoframe not received\n", 2170516613c1SHans Verkuil adv76xx_cri[index].desc); 2171516613c1SHans Verkuil return -ENOENT; 2172516613c1SHans Verkuil } 2173516613c1SHans Verkuil 2174516613c1SHans Verkuil for (i = 0; i < 3; i++) 2175516613c1SHans Verkuil buffer[i] = infoframe_read(sd, 2176516613c1SHans Verkuil adv76xx_cri[index].head_addr + i); 2177516613c1SHans Verkuil 2178516613c1SHans Verkuil len = buffer[2] + 1; 2179516613c1SHans Verkuil 2180516613c1SHans Verkuil if (len + 3 > sizeof(buffer)) { 2181516613c1SHans Verkuil v4l2_err(sd, "%s: invalid %s infoframe length %d\n", __func__, 2182516613c1SHans Verkuil adv76xx_cri[index].desc, len); 2183516613c1SHans Verkuil return -ENOENT; 2184516613c1SHans Verkuil } 2185516613c1SHans Verkuil 2186516613c1SHans Verkuil for (i = 0; i < len; i++) 2187516613c1SHans Verkuil buffer[i + 3] = infoframe_read(sd, 2188516613c1SHans Verkuil adv76xx_cri[index].payload_addr + i); 2189516613c1SHans Verkuil 2190516613c1SHans Verkuil if (hdmi_infoframe_unpack(frame, buffer) < 0) { 2191516613c1SHans Verkuil v4l2_err(sd, "%s: unpack of %s infoframe failed\n", __func__, 2192516613c1SHans Verkuil adv76xx_cri[index].desc); 2193516613c1SHans Verkuil return -ENOENT; 2194516613c1SHans Verkuil } 2195516613c1SHans Verkuil return 0; 2196516613c1SHans Verkuil } 2197516613c1SHans Verkuil 2198516613c1SHans Verkuil static void adv76xx_log_infoframes(struct v4l2_subdev *sd) 219954450f59SHans Verkuil { 220054450f59SHans Verkuil int i; 220154450f59SHans Verkuil 2202bb88f325SMartin Bugge if (!is_hdmi(sd)) { 2203516613c1SHans Verkuil v4l2_info(sd, "receive DVI-D signal, no infoframes\n"); 220454450f59SHans Verkuil return; 220554450f59SHans Verkuil } 220654450f59SHans Verkuil 2207516613c1SHans Verkuil for (i = 0; i < ARRAY_SIZE(adv76xx_cri); i++) { 2208516613c1SHans Verkuil union hdmi_infoframe frame; 2209516613c1SHans Verkuil struct i2c_client *client = v4l2_get_subdevdata(sd); 221054450f59SHans Verkuil 2211516613c1SHans Verkuil if (adv76xx_read_infoframe(sd, i, &frame)) 221254450f59SHans Verkuil return; 2213516613c1SHans Verkuil hdmi_infoframe_log(KERN_INFO, &client->dev, &frame); 2214516613c1SHans Verkuil } 221554450f59SHans Verkuil } 221654450f59SHans Verkuil 2217b44b2e06SPablo Anton static int adv76xx_log_status(struct v4l2_subdev *sd) 221854450f59SHans Verkuil { 2219b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 2220b44b2e06SPablo Anton const struct adv76xx_chip_info *info = state->info; 222154450f59SHans Verkuil struct v4l2_dv_timings timings; 222254450f59SHans Verkuil struct stdi_readback stdi; 222354450f59SHans Verkuil u8 reg_io_0x02 = io_read(sd, 0x02); 22244a2ccdd2SLaurent Pinchart u8 edid_enabled; 22254a2ccdd2SLaurent Pinchart u8 cable_det; 222654450f59SHans Verkuil 2227f216ccb3SLars-Peter Clausen static const char * const csc_coeff_sel_rb[16] = { 222854450f59SHans Verkuil "bypassed", "YPbPr601 -> RGB", "reserved", "YPbPr709 -> RGB", 222954450f59SHans Verkuil "reserved", "RGB -> YPbPr601", "reserved", "RGB -> YPbPr709", 223054450f59SHans Verkuil "reserved", "YPbPr709 -> YPbPr601", "YPbPr601 -> YPbPr709", 223154450f59SHans Verkuil "reserved", "reserved", "reserved", "reserved", "manual" 223254450f59SHans Verkuil }; 2233f216ccb3SLars-Peter Clausen static const char * const input_color_space_txt[16] = { 223454450f59SHans Verkuil "RGB limited range (16-235)", "RGB full range (0-255)", 223554450f59SHans Verkuil "YCbCr Bt.601 (16-235)", "YCbCr Bt.709 (16-235)", 22369833239eSMats Randgaard "xvYCC Bt.601", "xvYCC Bt.709", 223754450f59SHans Verkuil "YCbCr Bt.601 (0-255)", "YCbCr Bt.709 (0-255)", 223854450f59SHans Verkuil "invalid", "invalid", "invalid", "invalid", "invalid", 223954450f59SHans Verkuil "invalid", "invalid", "automatic" 224054450f59SHans Verkuil }; 22417a5d99e7SHans Verkuil static const char * const hdmi_color_space_txt[16] = { 22427a5d99e7SHans Verkuil "RGB limited range (16-235)", "RGB full range (0-255)", 22437a5d99e7SHans Verkuil "YCbCr Bt.601 (16-235)", "YCbCr Bt.709 (16-235)", 22447a5d99e7SHans Verkuil "xvYCC Bt.601", "xvYCC Bt.709", 22457a5d99e7SHans Verkuil "YCbCr Bt.601 (0-255)", "YCbCr Bt.709 (0-255)", 22467a5d99e7SHans Verkuil "sYCC", "Adobe YCC 601", "AdobeRGB", "invalid", "invalid", 22477a5d99e7SHans Verkuil "invalid", "invalid", "invalid" 22487a5d99e7SHans Verkuil }; 2249f216ccb3SLars-Peter Clausen static const char * const rgb_quantization_range_txt[] = { 225054450f59SHans Verkuil "Automatic", 225154450f59SHans Verkuil "RGB limited range (16-235)", 225254450f59SHans Verkuil "RGB full range (0-255)", 225354450f59SHans Verkuil }; 2254f216ccb3SLars-Peter Clausen static const char * const deep_color_mode_txt[4] = { 2255bb88f325SMartin Bugge "8-bits per channel", 2256bb88f325SMartin Bugge "10-bits per channel", 2257bb88f325SMartin Bugge "12-bits per channel", 2258bb88f325SMartin Bugge "16-bits per channel (not supported)" 2259bb88f325SMartin Bugge }; 226054450f59SHans Verkuil 226154450f59SHans Verkuil v4l2_info(sd, "-----Chip status-----\n"); 226254450f59SHans Verkuil v4l2_info(sd, "Chip power: %s\n", no_power(sd) ? "off" : "on"); 2263d42010a1SLars-Peter Clausen edid_enabled = rep_read(sd, info->edid_status_reg); 22644a31a93aSMats Randgaard v4l2_info(sd, "EDID enabled port A: %s, B: %s, C: %s, D: %s\n", 22654a2ccdd2SLaurent Pinchart ((edid_enabled & 0x01) ? "Yes" : "No"), 22664a2ccdd2SLaurent Pinchart ((edid_enabled & 0x02) ? "Yes" : "No"), 22674a2ccdd2SLaurent Pinchart ((edid_enabled & 0x04) ? "Yes" : "No"), 22684a2ccdd2SLaurent Pinchart ((edid_enabled & 0x08) ? "Yes" : "No")); 226954450f59SHans Verkuil v4l2_info(sd, "CEC: %s\n", !!(cec_read(sd, 0x2a) & 0x01) ? 227054450f59SHans Verkuil "enabled" : "disabled"); 227154450f59SHans Verkuil 227254450f59SHans Verkuil v4l2_info(sd, "-----Signal status-----\n"); 2273d42010a1SLars-Peter Clausen cable_det = info->read_cable_det(sd); 22744a31a93aSMats Randgaard v4l2_info(sd, "Cable detected (+5V power) port A: %s, B: %s, C: %s, D: %s\n", 2275d42010a1SLars-Peter Clausen ((cable_det & 0x01) ? "Yes" : "No"), 2276d42010a1SLars-Peter Clausen ((cable_det & 0x02) ? "Yes" : "No"), 22774a2ccdd2SLaurent Pinchart ((cable_det & 0x04) ? "Yes" : "No"), 2278d42010a1SLars-Peter Clausen ((cable_det & 0x08) ? "Yes" : "No")); 227954450f59SHans Verkuil v4l2_info(sd, "TMDS signal detected: %s\n", 228054450f59SHans Verkuil no_signal_tmds(sd) ? "false" : "true"); 228154450f59SHans Verkuil v4l2_info(sd, "TMDS signal locked: %s\n", 228254450f59SHans Verkuil no_lock_tmds(sd) ? "false" : "true"); 228354450f59SHans Verkuil v4l2_info(sd, "SSPD locked: %s\n", no_lock_sspd(sd) ? "false" : "true"); 228454450f59SHans Verkuil v4l2_info(sd, "STDI locked: %s\n", no_lock_stdi(sd) ? "false" : "true"); 228554450f59SHans Verkuil v4l2_info(sd, "CP locked: %s\n", no_lock_cp(sd) ? "false" : "true"); 228654450f59SHans Verkuil v4l2_info(sd, "CP free run: %s\n", 228758514625Sjean-michel.hautbois@vodalys.com (in_free_run(sd)) ? "on" : "off"); 2288ccbd5bc4SHans Verkuil v4l2_info(sd, "Prim-mode = 0x%x, video std = 0x%x, v_freq = 0x%x\n", 2289ccbd5bc4SHans Verkuil io_read(sd, 0x01) & 0x0f, io_read(sd, 0x00) & 0x3f, 2290ccbd5bc4SHans Verkuil (io_read(sd, 0x01) & 0x70) >> 4); 229154450f59SHans Verkuil 229254450f59SHans Verkuil v4l2_info(sd, "-----Video Timings-----\n"); 229354450f59SHans Verkuil if (read_stdi(sd, &stdi)) 229454450f59SHans Verkuil v4l2_info(sd, "STDI: not locked\n"); 229554450f59SHans Verkuil else 229654450f59SHans Verkuil v4l2_info(sd, "STDI: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %s, %chsync, %cvsync\n", 229754450f59SHans Verkuil stdi.lcf, stdi.bl, stdi.lcvs, 229854450f59SHans Verkuil stdi.interlaced ? "interlaced" : "progressive", 229954450f59SHans Verkuil stdi.hs_pol, stdi.vs_pol); 2300b44b2e06SPablo Anton if (adv76xx_query_dv_timings(sd, &timings)) 230154450f59SHans Verkuil v4l2_info(sd, "No video detected\n"); 230254450f59SHans Verkuil else 230311d034c8SHans Verkuil v4l2_print_dv_timings(sd->name, "Detected format: ", 230411d034c8SHans Verkuil &timings, true); 230511d034c8SHans Verkuil v4l2_print_dv_timings(sd->name, "Configured format: ", 230611d034c8SHans Verkuil &state->timings, true); 230754450f59SHans Verkuil 230876eb2d30SMats Randgaard if (no_signal(sd)) 230976eb2d30SMats Randgaard return 0; 231076eb2d30SMats Randgaard 231154450f59SHans Verkuil v4l2_info(sd, "-----Color space-----\n"); 231254450f59SHans Verkuil v4l2_info(sd, "RGB quantization range ctrl: %s\n", 231354450f59SHans Verkuil rgb_quantization_range_txt[state->rgb_quantization_range]); 231454450f59SHans Verkuil v4l2_info(sd, "Input color space: %s\n", 231554450f59SHans Verkuil input_color_space_txt[reg_io_0x02 >> 4]); 23167a5d99e7SHans Verkuil v4l2_info(sd, "Output color space: %s %s, saturator %s, alt-gamma %s\n", 231754450f59SHans Verkuil (reg_io_0x02 & 0x02) ? "RGB" : "YCbCr", 231854450f59SHans Verkuil (reg_io_0x02 & 0x04) ? "(16-235)" : "(0-255)", 23195dd7d88aSHans Verkuil (((reg_io_0x02 >> 2) & 0x01) ^ (reg_io_0x02 & 0x01)) ? 23207a5d99e7SHans Verkuil "enabled" : "disabled", 23217a5d99e7SHans Verkuil (reg_io_0x02 & 0x08) ? "enabled" : "disabled"); 232254450f59SHans Verkuil v4l2_info(sd, "Color space conversion: %s\n", 232380f4944eSjean-michel.hautbois@vodalys.com csc_coeff_sel_rb[cp_read(sd, info->cp_csc) >> 4]); 232454450f59SHans Verkuil 23254a31a93aSMats Randgaard if (!is_digital_input(sd)) 232676eb2d30SMats Randgaard return 0; 232776eb2d30SMats Randgaard 232876eb2d30SMats Randgaard v4l2_info(sd, "-----%s status-----\n", is_hdmi(sd) ? "HDMI" : "DVI-D"); 23294a31a93aSMats Randgaard v4l2_info(sd, "Digital video port selected: %c\n", 23304a31a93aSMats Randgaard (hdmi_read(sd, 0x00) & 0x03) + 'A'); 23314a31a93aSMats Randgaard v4l2_info(sd, "HDCP encrypted content: %s\n", 23324a31a93aSMats Randgaard (hdmi_read(sd, 0x05) & 0x40) ? "true" : "false"); 233376eb2d30SMats Randgaard v4l2_info(sd, "HDCP keys read: %s%s\n", 233476eb2d30SMats Randgaard (hdmi_read(sd, 0x04) & 0x20) ? "yes" : "no", 233576eb2d30SMats Randgaard (hdmi_read(sd, 0x04) & 0x10) ? "ERROR" : ""); 233677639ff2SHans Verkuil if (is_hdmi(sd)) { 233776eb2d30SMats Randgaard bool audio_pll_locked = hdmi_read(sd, 0x04) & 0x01; 233876eb2d30SMats Randgaard bool audio_sample_packet_detect = hdmi_read(sd, 0x18) & 0x01; 233976eb2d30SMats Randgaard bool audio_mute = io_read(sd, 0x65) & 0x40; 234076eb2d30SMats Randgaard 234176eb2d30SMats Randgaard v4l2_info(sd, "Audio: pll %s, samples %s, %s\n", 234276eb2d30SMats Randgaard audio_pll_locked ? "locked" : "not locked", 234376eb2d30SMats Randgaard audio_sample_packet_detect ? "detected" : "not detected", 234476eb2d30SMats Randgaard audio_mute ? "muted" : "enabled"); 234576eb2d30SMats Randgaard if (audio_pll_locked && audio_sample_packet_detect) { 234676eb2d30SMats Randgaard v4l2_info(sd, "Audio format: %s\n", 234776eb2d30SMats Randgaard (hdmi_read(sd, 0x07) & 0x20) ? "multi-channel" : "stereo"); 234876eb2d30SMats Randgaard } 234976eb2d30SMats Randgaard v4l2_info(sd, "Audio CTS: %u\n", (hdmi_read(sd, 0x5b) << 12) + 235076eb2d30SMats Randgaard (hdmi_read(sd, 0x5c) << 8) + 235176eb2d30SMats Randgaard (hdmi_read(sd, 0x5d) & 0xf0)); 235276eb2d30SMats Randgaard v4l2_info(sd, "Audio N: %u\n", ((hdmi_read(sd, 0x5d) & 0x0f) << 16) + 235376eb2d30SMats Randgaard (hdmi_read(sd, 0x5e) << 8) + 235476eb2d30SMats Randgaard hdmi_read(sd, 0x5f)); 235576eb2d30SMats Randgaard v4l2_info(sd, "AV Mute: %s\n", (hdmi_read(sd, 0x04) & 0x40) ? "on" : "off"); 235676eb2d30SMats Randgaard 235776eb2d30SMats Randgaard v4l2_info(sd, "Deep color mode: %s\n", deep_color_mode_txt[(hdmi_read(sd, 0x0b) & 0x60) >> 5]); 23587a5d99e7SHans Verkuil v4l2_info(sd, "HDMI colorspace: %s\n", hdmi_color_space_txt[hdmi_read(sd, 0x53) & 0xf]); 235976eb2d30SMats Randgaard 2360516613c1SHans Verkuil adv76xx_log_infoframes(sd); 236154450f59SHans Verkuil } 236254450f59SHans Verkuil 236354450f59SHans Verkuil return 0; 236454450f59SHans Verkuil } 236554450f59SHans Verkuil 23666f5bcfc3SLars-Peter Clausen static int adv76xx_subscribe_event(struct v4l2_subdev *sd, 23676f5bcfc3SLars-Peter Clausen struct v4l2_fh *fh, 23686f5bcfc3SLars-Peter Clausen struct v4l2_event_subscription *sub) 23696f5bcfc3SLars-Peter Clausen { 23706f5bcfc3SLars-Peter Clausen switch (sub->type) { 23716f5bcfc3SLars-Peter Clausen case V4L2_EVENT_SOURCE_CHANGE: 23726f5bcfc3SLars-Peter Clausen return v4l2_src_change_event_subdev_subscribe(sd, fh, sub); 23736f5bcfc3SLars-Peter Clausen case V4L2_EVENT_CTRL: 23746f5bcfc3SLars-Peter Clausen return v4l2_ctrl_subdev_subscribe_event(sd, fh, sub); 23756f5bcfc3SLars-Peter Clausen default: 23766f5bcfc3SLars-Peter Clausen return -EINVAL; 23776f5bcfc3SLars-Peter Clausen } 23786f5bcfc3SLars-Peter Clausen } 23796f5bcfc3SLars-Peter Clausen 238054450f59SHans Verkuil /* ----------------------------------------------------------------------- */ 238154450f59SHans Verkuil 2382b44b2e06SPablo Anton static const struct v4l2_ctrl_ops adv76xx_ctrl_ops = { 2383b44b2e06SPablo Anton .s_ctrl = adv76xx_s_ctrl, 238454450f59SHans Verkuil }; 238554450f59SHans Verkuil 2386b44b2e06SPablo Anton static const struct v4l2_subdev_core_ops adv76xx_core_ops = { 2387b44b2e06SPablo Anton .log_status = adv76xx_log_status, 2388b44b2e06SPablo Anton .interrupt_service_routine = adv76xx_isr, 23896f5bcfc3SLars-Peter Clausen .subscribe_event = adv76xx_subscribe_event, 23900975626dSLars-Peter Clausen .unsubscribe_event = v4l2_event_subdev_unsubscribe, 239154450f59SHans Verkuil #ifdef CONFIG_VIDEO_ADV_DEBUG 2392b44b2e06SPablo Anton .g_register = adv76xx_g_register, 2393b44b2e06SPablo Anton .s_register = adv76xx_s_register, 239454450f59SHans Verkuil #endif 239554450f59SHans Verkuil }; 239654450f59SHans Verkuil 2397b44b2e06SPablo Anton static const struct v4l2_subdev_video_ops adv76xx_video_ops = { 2398b44b2e06SPablo Anton .s_routing = adv76xx_s_routing, 2399b44b2e06SPablo Anton .g_input_status = adv76xx_g_input_status, 2400b44b2e06SPablo Anton .s_dv_timings = adv76xx_s_dv_timings, 2401b44b2e06SPablo Anton .g_dv_timings = adv76xx_g_dv_timings, 2402b44b2e06SPablo Anton .query_dv_timings = adv76xx_query_dv_timings, 240354450f59SHans Verkuil }; 240454450f59SHans Verkuil 2405b44b2e06SPablo Anton static const struct v4l2_subdev_pad_ops adv76xx_pad_ops = { 2406b44b2e06SPablo Anton .enum_mbus_code = adv76xx_enum_mbus_code, 2407b44b2e06SPablo Anton .get_fmt = adv76xx_get_format, 2408b44b2e06SPablo Anton .set_fmt = adv76xx_set_format, 2409b44b2e06SPablo Anton .get_edid = adv76xx_get_edid, 2410b44b2e06SPablo Anton .set_edid = adv76xx_set_edid, 2411b44b2e06SPablo Anton .dv_timings_cap = adv76xx_dv_timings_cap, 2412b44b2e06SPablo Anton .enum_dv_timings = adv76xx_enum_dv_timings, 241354450f59SHans Verkuil }; 241454450f59SHans Verkuil 2415b44b2e06SPablo Anton static const struct v4l2_subdev_ops adv76xx_ops = { 2416b44b2e06SPablo Anton .core = &adv76xx_core_ops, 2417b44b2e06SPablo Anton .video = &adv76xx_video_ops, 2418b44b2e06SPablo Anton .pad = &adv76xx_pad_ops, 241954450f59SHans Verkuil }; 242054450f59SHans Verkuil 242154450f59SHans Verkuil /* -------------------------- custom ctrls ---------------------------------- */ 242254450f59SHans Verkuil 242354450f59SHans Verkuil static const struct v4l2_ctrl_config adv7604_ctrl_analog_sampling_phase = { 2424b44b2e06SPablo Anton .ops = &adv76xx_ctrl_ops, 242554450f59SHans Verkuil .id = V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE, 242654450f59SHans Verkuil .name = "Analog Sampling Phase", 242754450f59SHans Verkuil .type = V4L2_CTRL_TYPE_INTEGER, 242854450f59SHans Verkuil .min = 0, 242954450f59SHans Verkuil .max = 0x1f, 243054450f59SHans Verkuil .step = 1, 243154450f59SHans Verkuil .def = 0, 243254450f59SHans Verkuil }; 243354450f59SHans Verkuil 2434b44b2e06SPablo Anton static const struct v4l2_ctrl_config adv76xx_ctrl_free_run_color_manual = { 2435b44b2e06SPablo Anton .ops = &adv76xx_ctrl_ops, 243654450f59SHans Verkuil .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL, 243754450f59SHans Verkuil .name = "Free Running Color, Manual", 243854450f59SHans Verkuil .type = V4L2_CTRL_TYPE_BOOLEAN, 243954450f59SHans Verkuil .min = false, 244054450f59SHans Verkuil .max = true, 244154450f59SHans Verkuil .step = 1, 244254450f59SHans Verkuil .def = false, 244354450f59SHans Verkuil }; 244454450f59SHans Verkuil 2445b44b2e06SPablo Anton static const struct v4l2_ctrl_config adv76xx_ctrl_free_run_color = { 2446b44b2e06SPablo Anton .ops = &adv76xx_ctrl_ops, 244754450f59SHans Verkuil .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR, 244854450f59SHans Verkuil .name = "Free Running Color", 244954450f59SHans Verkuil .type = V4L2_CTRL_TYPE_INTEGER, 245054450f59SHans Verkuil .min = 0x0, 245154450f59SHans Verkuil .max = 0xffffff, 245254450f59SHans Verkuil .step = 0x1, 245354450f59SHans Verkuil .def = 0x0, 245454450f59SHans Verkuil }; 245554450f59SHans Verkuil 245654450f59SHans Verkuil /* ----------------------------------------------------------------------- */ 245754450f59SHans Verkuil 2458b44b2e06SPablo Anton static int adv76xx_core_init(struct v4l2_subdev *sd) 245954450f59SHans Verkuil { 2460b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 2461b44b2e06SPablo Anton const struct adv76xx_chip_info *info = state->info; 2462b44b2e06SPablo Anton struct adv76xx_platform_data *pdata = &state->pdata; 246354450f59SHans Verkuil 246454450f59SHans Verkuil hdmi_write(sd, 0x48, 246554450f59SHans Verkuil (pdata->disable_pwrdnb ? 0x80 : 0) | 246654450f59SHans Verkuil (pdata->disable_cable_det_rst ? 0x40 : 0)); 246754450f59SHans Verkuil 246854450f59SHans Verkuil disable_input(sd); 246954450f59SHans Verkuil 24705ef54b59SLaurent Pinchart if (pdata->default_input >= 0 && 24715ef54b59SLaurent Pinchart pdata->default_input < state->source_pad) { 24725ef54b59SLaurent Pinchart state->selected_input = pdata->default_input; 24735ef54b59SLaurent Pinchart select_input(sd); 24745ef54b59SLaurent Pinchart enable_input(sd); 24755ef54b59SLaurent Pinchart } 24765ef54b59SLaurent Pinchart 247754450f59SHans Verkuil /* power */ 247854450f59SHans Verkuil io_write(sd, 0x0c, 0x42); /* Power up part and power down VDP */ 247954450f59SHans Verkuil io_write(sd, 0x0b, 0x44); /* Power down ESDP block */ 248054450f59SHans Verkuil cp_write(sd, 0xcf, 0x01); /* Power down macrovision */ 248154450f59SHans Verkuil 248254450f59SHans Verkuil /* video format */ 248322d97e56SLaurent Pinchart io_write_clr_set(sd, 0x02, 0x0f, 248454450f59SHans Verkuil pdata->alt_gamma << 3 | 248554450f59SHans Verkuil pdata->op_656_range << 2 | 248654450f59SHans Verkuil pdata->alt_data_sat << 0); 248722d97e56SLaurent Pinchart io_write_clr_set(sd, 0x05, 0x0e, pdata->blank_data << 3 | 248854450f59SHans Verkuil pdata->insert_av_codes << 2 | 2489539b33b0SLaurent Pinchart pdata->replicate_av_codes << 1); 2490b44b2e06SPablo Anton adv76xx_setup_format(state); 249154450f59SHans Verkuil 249254450f59SHans Verkuil cp_write(sd, 0x69, 0x30); /* Enable CP CSC */ 249398908696SMartin Bugge 249498908696SMartin Bugge /* VS, HS polarities */ 24951b5ab875SLaurent Pinchart io_write(sd, 0x06, 0xa0 | pdata->inv_vs_pol << 2 | 24961b5ab875SLaurent Pinchart pdata->inv_hs_pol << 1 | pdata->inv_llc_pol); 2497f31b62e1SMikhail Khelik 2498f31b62e1SMikhail Khelik /* Adjust drive strength */ 2499f31b62e1SMikhail Khelik io_write(sd, 0x14, 0x40 | pdata->dr_str_data << 4 | 2500f31b62e1SMikhail Khelik pdata->dr_str_clk << 2 | 2501f31b62e1SMikhail Khelik pdata->dr_str_sync); 2502f31b62e1SMikhail Khelik 250354450f59SHans Verkuil cp_write(sd, 0xba, (pdata->hdmi_free_run_mode << 1) | 0x01); /* HDMI free run */ 250454450f59SHans Verkuil cp_write(sd, 0xf3, 0xdc); /* Low threshold to enter/exit free run mode */ 250554450f59SHans Verkuil cp_write(sd, 0xf9, 0x23); /* STDI ch. 1 - LCVS change threshold - 250680939647SHans Verkuil ADI recommended setting [REF_01, c. 2.3.3] */ 250754450f59SHans Verkuil cp_write(sd, 0x45, 0x23); /* STDI ch. 2 - LCVS change threshold - 250880939647SHans Verkuil ADI recommended setting [REF_01, c. 2.3.3] */ 250954450f59SHans Verkuil cp_write(sd, 0xc9, 0x2d); /* use prim_mode and vid_std as free run resolution 251054450f59SHans Verkuil for digital formats */ 251154450f59SHans Verkuil 25125474b983SMats Randgaard /* HDMI audio */ 251322d97e56SLaurent Pinchart hdmi_write_clr_set(sd, 0x15, 0x03, 0x03); /* Mute on FIFO over-/underflow [REF_01, c. 1.2.18] */ 251422d97e56SLaurent Pinchart hdmi_write_clr_set(sd, 0x1a, 0x0e, 0x08); /* Wait 1 s before unmute */ 251522d97e56SLaurent Pinchart hdmi_write_clr_set(sd, 0x68, 0x06, 0x06); /* FIFO reset on over-/underflow [REF_01, c. 1.2.19] */ 25165474b983SMats Randgaard 251754450f59SHans Verkuil /* TODO from platform data */ 251854450f59SHans Verkuil afe_write(sd, 0xb5, 0x01); /* Setting MCLK to 256Fs */ 251954450f59SHans Verkuil 2520b44b2e06SPablo Anton if (adv76xx_has_afe(state)) { 252154450f59SHans Verkuil afe_write(sd, 0x02, pdata->ain_sel); /* Select analog input muxing mode */ 252222d97e56SLaurent Pinchart io_write_clr_set(sd, 0x30, 1 << 4, pdata->output_bus_lsb_to_msb << 4); 2523d42010a1SLars-Peter Clausen } 252454450f59SHans Verkuil 252554450f59SHans Verkuil /* interrupts */ 2526d42010a1SLars-Peter Clausen io_write(sd, 0x40, 0xc0 | pdata->int1_config); /* Configure INT1 */ 252754450f59SHans Verkuil io_write(sd, 0x46, 0x98); /* Enable SSPD, STDI and CP unlocked interrupts */ 2528d42010a1SLars-Peter Clausen io_write(sd, 0x6e, info->fmt_change_digital_mask); /* Enable V_LOCKED and DE_REGEN_LCK interrupts */ 2529d42010a1SLars-Peter Clausen io_write(sd, 0x73, info->cable_det_mask); /* Enable cable detection (+5v) interrupts */ 2530d42010a1SLars-Peter Clausen info->setup_irqs(sd); 253154450f59SHans Verkuil 253254450f59SHans Verkuil return v4l2_ctrl_handler_setup(sd->ctrl_handler); 253354450f59SHans Verkuil } 253454450f59SHans Verkuil 2535d42010a1SLars-Peter Clausen static void adv7604_setup_irqs(struct v4l2_subdev *sd) 2536d42010a1SLars-Peter Clausen { 2537d42010a1SLars-Peter Clausen io_write(sd, 0x41, 0xd7); /* STDI irq for any change, disable INT2 */ 2538d42010a1SLars-Peter Clausen } 2539d42010a1SLars-Peter Clausen 2540d42010a1SLars-Peter Clausen static void adv7611_setup_irqs(struct v4l2_subdev *sd) 2541d42010a1SLars-Peter Clausen { 2542d42010a1SLars-Peter Clausen io_write(sd, 0x41, 0xd0); /* STDI irq for any change, disable INT2 */ 2543d42010a1SLars-Peter Clausen } 2544d42010a1SLars-Peter Clausen 25458331d30bSWilliam Towle static void adv7612_setup_irqs(struct v4l2_subdev *sd) 25468331d30bSWilliam Towle { 25478331d30bSWilliam Towle io_write(sd, 0x41, 0xd0); /* disable INT2 */ 25488331d30bSWilliam Towle } 25498331d30bSWilliam Towle 2550b44b2e06SPablo Anton static void adv76xx_unregister_clients(struct adv76xx_state *state) 255154450f59SHans Verkuil { 255205cacb17SLaurent Pinchart unsigned int i; 255305cacb17SLaurent Pinchart 255405cacb17SLaurent Pinchart for (i = 1; i < ARRAY_SIZE(state->i2c_clients); ++i) { 255505cacb17SLaurent Pinchart if (state->i2c_clients[i]) 255605cacb17SLaurent Pinchart i2c_unregister_device(state->i2c_clients[i]); 255705cacb17SLaurent Pinchart } 255854450f59SHans Verkuil } 255954450f59SHans Verkuil 2560b44b2e06SPablo Anton static struct i2c_client *adv76xx_dummy_client(struct v4l2_subdev *sd, 256154450f59SHans Verkuil u8 addr, u8 io_reg) 256254450f59SHans Verkuil { 256354450f59SHans Verkuil struct i2c_client *client = v4l2_get_subdevdata(sd); 256454450f59SHans Verkuil 256554450f59SHans Verkuil if (addr) 256654450f59SHans Verkuil io_write(sd, io_reg, addr << 1); 256754450f59SHans Verkuil return i2c_new_dummy(client->adapter, io_read(sd, io_reg) >> 1); 256854450f59SHans Verkuil } 256954450f59SHans Verkuil 2570b44b2e06SPablo Anton static const struct adv76xx_reg_seq adv7604_recommended_settings_afe[] = { 2571d42010a1SLars-Peter Clausen /* reset ADI recommended settings for HDMI: */ 2572d42010a1SLars-Peter Clausen /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 4. */ 2573b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x0d), 0x04 }, /* HDMI filter optimization */ 2574b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x0d), 0x04 }, /* HDMI filter optimization */ 2575b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x3d), 0x00 }, /* DDC bus active pull-up control */ 2576b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x3e), 0x74 }, /* TMDS PLL optimization */ 2577b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x4e), 0x3b }, /* TMDS PLL optimization */ 2578b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x57), 0x74 }, /* TMDS PLL optimization */ 2579b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x58), 0x63 }, /* TMDS PLL optimization */ 2580b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8d), 0x18 }, /* equaliser */ 2581b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8e), 0x34 }, /* equaliser */ 2582b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x93), 0x88 }, /* equaliser */ 2583b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x94), 0x2e }, /* equaliser */ 2584b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x96), 0x00 }, /* enable automatic EQ changing */ 2585d42010a1SLars-Peter Clausen 2586d42010a1SLars-Peter Clausen /* set ADI recommended settings for digitizer */ 2587d42010a1SLars-Peter Clausen /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 17. */ 2588b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_AFE, 0x12), 0x7b }, /* ADC noise shaping filter controls */ 2589b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_AFE, 0x0c), 0x1f }, /* CP core gain controls */ 2590b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_CP, 0x3e), 0x04 }, /* CP core pre-gain control */ 2591b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_CP, 0xc3), 0x39 }, /* CP coast control. Graphics mode */ 2592b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_CP, 0x40), 0x5c }, /* CP core pre-gain control. Graphics mode */ 2593d42010a1SLars-Peter Clausen 2594b44b2e06SPablo Anton { ADV76XX_REG_SEQ_TERM, 0 }, 2595d42010a1SLars-Peter Clausen }; 2596d42010a1SLars-Peter Clausen 2597b44b2e06SPablo Anton static const struct adv76xx_reg_seq adv7604_recommended_settings_hdmi[] = { 2598d42010a1SLars-Peter Clausen /* set ADI recommended settings for HDMI: */ 2599d42010a1SLars-Peter Clausen /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 4. */ 2600b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x0d), 0x84 }, /* HDMI filter optimization */ 2601b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x3d), 0x10 }, /* DDC bus active pull-up control */ 2602b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x3e), 0x39 }, /* TMDS PLL optimization */ 2603b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x4e), 0x3b }, /* TMDS PLL optimization */ 2604b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x57), 0xb6 }, /* TMDS PLL optimization */ 2605b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x58), 0x03 }, /* TMDS PLL optimization */ 2606b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8d), 0x18 }, /* equaliser */ 2607b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8e), 0x34 }, /* equaliser */ 2608b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x93), 0x8b }, /* equaliser */ 2609b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x94), 0x2d }, /* equaliser */ 2610b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x96), 0x01 }, /* enable automatic EQ changing */ 2611d42010a1SLars-Peter Clausen 2612d42010a1SLars-Peter Clausen /* reset ADI recommended settings for digitizer */ 2613d42010a1SLars-Peter Clausen /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 17. */ 2614b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_AFE, 0x12), 0xfb }, /* ADC noise shaping filter controls */ 2615b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_AFE, 0x0c), 0x0d }, /* CP core gain controls */ 2616d42010a1SLars-Peter Clausen 2617b44b2e06SPablo Anton { ADV76XX_REG_SEQ_TERM, 0 }, 2618d42010a1SLars-Peter Clausen }; 2619d42010a1SLars-Peter Clausen 2620b44b2e06SPablo Anton static const struct adv76xx_reg_seq adv7611_recommended_settings_hdmi[] = { 2621c41ad9c3SLars-Peter Clausen /* ADV7611 Register Settings Recommendations Rev 1.5, May 2014 */ 2622b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_CP, 0x6c), 0x00 }, 2623b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x9b), 0x03 }, 2624b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x6f), 0x08 }, 2625b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x85), 0x1f }, 2626b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x87), 0x70 }, 2627b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x57), 0xda }, 2628b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x58), 0x01 }, 2629b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x03), 0x98 }, 2630b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x4c), 0x44 }, 2631b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8d), 0x04 }, 2632b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8e), 0x1e }, 2633d42010a1SLars-Peter Clausen 2634b44b2e06SPablo Anton { ADV76XX_REG_SEQ_TERM, 0 }, 2635d42010a1SLars-Peter Clausen }; 2636d42010a1SLars-Peter Clausen 26378331d30bSWilliam Towle static const struct adv76xx_reg_seq adv7612_recommended_settings_hdmi[] = { 26388331d30bSWilliam Towle { ADV76XX_REG(ADV76XX_PAGE_CP, 0x6c), 0x00 }, 26398331d30bSWilliam Towle { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x9b), 0x03 }, 26408331d30bSWilliam Towle { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x6f), 0x08 }, 26418331d30bSWilliam Towle { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x85), 0x1f }, 26428331d30bSWilliam Towle { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x87), 0x70 }, 26438331d30bSWilliam Towle { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x57), 0xda }, 26448331d30bSWilliam Towle { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x58), 0x01 }, 26458331d30bSWilliam Towle { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x03), 0x98 }, 26468331d30bSWilliam Towle { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x4c), 0x44 }, 26478331d30bSWilliam Towle { ADV76XX_REG_SEQ_TERM, 0 }, 26488331d30bSWilliam Towle }; 26498331d30bSWilliam Towle 2650b44b2e06SPablo Anton static const struct adv76xx_chip_info adv76xx_chip_info[] = { 2651d42010a1SLars-Peter Clausen [ADV7604] = { 2652d42010a1SLars-Peter Clausen .type = ADV7604, 2653d42010a1SLars-Peter Clausen .has_afe = true, 2654c784b1e2SLaurent Pinchart .max_port = ADV7604_PAD_VGA_COMP, 2655d42010a1SLars-Peter Clausen .num_dv_ports = 4, 2656d42010a1SLars-Peter Clausen .edid_enable_reg = 0x77, 2657d42010a1SLars-Peter Clausen .edid_status_reg = 0x7d, 2658d42010a1SLars-Peter Clausen .lcf_reg = 0xb3, 2659d42010a1SLars-Peter Clausen .tdms_lock_mask = 0xe0, 2660d42010a1SLars-Peter Clausen .cable_det_mask = 0x1e, 2661d42010a1SLars-Peter Clausen .fmt_change_digital_mask = 0xc1, 266280f4944eSjean-michel.hautbois@vodalys.com .cp_csc = 0xfc, 2663539b33b0SLaurent Pinchart .formats = adv7604_formats, 2664539b33b0SLaurent Pinchart .nformats = ARRAY_SIZE(adv7604_formats), 2665d42010a1SLars-Peter Clausen .set_termination = adv7604_set_termination, 2666d42010a1SLars-Peter Clausen .setup_irqs = adv7604_setup_irqs, 2667d42010a1SLars-Peter Clausen .read_hdmi_pixelclock = adv7604_read_hdmi_pixelclock, 2668d42010a1SLars-Peter Clausen .read_cable_det = adv7604_read_cable_det, 2669d42010a1SLars-Peter Clausen .recommended_settings = { 2670d42010a1SLars-Peter Clausen [0] = adv7604_recommended_settings_afe, 2671d42010a1SLars-Peter Clausen [1] = adv7604_recommended_settings_hdmi, 2672d42010a1SLars-Peter Clausen }, 2673d42010a1SLars-Peter Clausen .num_recommended_settings = { 2674d42010a1SLars-Peter Clausen [0] = ARRAY_SIZE(adv7604_recommended_settings_afe), 2675d42010a1SLars-Peter Clausen [1] = ARRAY_SIZE(adv7604_recommended_settings_hdmi), 2676d42010a1SLars-Peter Clausen }, 2677b44b2e06SPablo Anton .page_mask = BIT(ADV76XX_PAGE_IO) | BIT(ADV7604_PAGE_AVLINK) | 2678b44b2e06SPablo Anton BIT(ADV76XX_PAGE_CEC) | BIT(ADV76XX_PAGE_INFOFRAME) | 2679d42010a1SLars-Peter Clausen BIT(ADV7604_PAGE_ESDP) | BIT(ADV7604_PAGE_DPP) | 2680b44b2e06SPablo Anton BIT(ADV76XX_PAGE_AFE) | BIT(ADV76XX_PAGE_REP) | 2681b44b2e06SPablo Anton BIT(ADV76XX_PAGE_EDID) | BIT(ADV76XX_PAGE_HDMI) | 2682b44b2e06SPablo Anton BIT(ADV76XX_PAGE_TEST) | BIT(ADV76XX_PAGE_CP) | 2683d42010a1SLars-Peter Clausen BIT(ADV7604_PAGE_VDP), 26845380baafSjean-michel.hautbois@vodalys.com .linewidth_mask = 0xfff, 26855380baafSjean-michel.hautbois@vodalys.com .field0_height_mask = 0xfff, 26865380baafSjean-michel.hautbois@vodalys.com .field1_height_mask = 0xfff, 26875380baafSjean-michel.hautbois@vodalys.com .hfrontporch_mask = 0x3ff, 26885380baafSjean-michel.hautbois@vodalys.com .hsync_mask = 0x3ff, 26895380baafSjean-michel.hautbois@vodalys.com .hbackporch_mask = 0x3ff, 26905380baafSjean-michel.hautbois@vodalys.com .field0_vfrontporch_mask = 0x1fff, 26915380baafSjean-michel.hautbois@vodalys.com .field0_vsync_mask = 0x1fff, 26925380baafSjean-michel.hautbois@vodalys.com .field0_vbackporch_mask = 0x1fff, 26935380baafSjean-michel.hautbois@vodalys.com .field1_vfrontporch_mask = 0x1fff, 26945380baafSjean-michel.hautbois@vodalys.com .field1_vsync_mask = 0x1fff, 26955380baafSjean-michel.hautbois@vodalys.com .field1_vbackporch_mask = 0x1fff, 2696d42010a1SLars-Peter Clausen }, 2697d42010a1SLars-Peter Clausen [ADV7611] = { 2698d42010a1SLars-Peter Clausen .type = ADV7611, 2699d42010a1SLars-Peter Clausen .has_afe = false, 2700b44b2e06SPablo Anton .max_port = ADV76XX_PAD_HDMI_PORT_A, 2701d42010a1SLars-Peter Clausen .num_dv_ports = 1, 2702d42010a1SLars-Peter Clausen .edid_enable_reg = 0x74, 2703d42010a1SLars-Peter Clausen .edid_status_reg = 0x76, 2704d42010a1SLars-Peter Clausen .lcf_reg = 0xa3, 2705d42010a1SLars-Peter Clausen .tdms_lock_mask = 0x43, 2706d42010a1SLars-Peter Clausen .cable_det_mask = 0x01, 2707d42010a1SLars-Peter Clausen .fmt_change_digital_mask = 0x03, 270880f4944eSjean-michel.hautbois@vodalys.com .cp_csc = 0xf4, 2709539b33b0SLaurent Pinchart .formats = adv7611_formats, 2710539b33b0SLaurent Pinchart .nformats = ARRAY_SIZE(adv7611_formats), 2711d42010a1SLars-Peter Clausen .set_termination = adv7611_set_termination, 2712d42010a1SLars-Peter Clausen .setup_irqs = adv7611_setup_irqs, 2713d42010a1SLars-Peter Clausen .read_hdmi_pixelclock = adv7611_read_hdmi_pixelclock, 2714d42010a1SLars-Peter Clausen .read_cable_det = adv7611_read_cable_det, 2715d42010a1SLars-Peter Clausen .recommended_settings = { 2716d42010a1SLars-Peter Clausen [1] = adv7611_recommended_settings_hdmi, 2717d42010a1SLars-Peter Clausen }, 2718d42010a1SLars-Peter Clausen .num_recommended_settings = { 2719d42010a1SLars-Peter Clausen [1] = ARRAY_SIZE(adv7611_recommended_settings_hdmi), 2720d42010a1SLars-Peter Clausen }, 2721b44b2e06SPablo Anton .page_mask = BIT(ADV76XX_PAGE_IO) | BIT(ADV76XX_PAGE_CEC) | 2722b44b2e06SPablo Anton BIT(ADV76XX_PAGE_INFOFRAME) | BIT(ADV76XX_PAGE_AFE) | 2723b44b2e06SPablo Anton BIT(ADV76XX_PAGE_REP) | BIT(ADV76XX_PAGE_EDID) | 2724b44b2e06SPablo Anton BIT(ADV76XX_PAGE_HDMI) | BIT(ADV76XX_PAGE_CP), 27255380baafSjean-michel.hautbois@vodalys.com .linewidth_mask = 0x1fff, 27265380baafSjean-michel.hautbois@vodalys.com .field0_height_mask = 0x1fff, 27275380baafSjean-michel.hautbois@vodalys.com .field1_height_mask = 0x1fff, 27285380baafSjean-michel.hautbois@vodalys.com .hfrontporch_mask = 0x1fff, 27295380baafSjean-michel.hautbois@vodalys.com .hsync_mask = 0x1fff, 27305380baafSjean-michel.hautbois@vodalys.com .hbackporch_mask = 0x1fff, 27315380baafSjean-michel.hautbois@vodalys.com .field0_vfrontporch_mask = 0x3fff, 27325380baafSjean-michel.hautbois@vodalys.com .field0_vsync_mask = 0x3fff, 27335380baafSjean-michel.hautbois@vodalys.com .field0_vbackporch_mask = 0x3fff, 27345380baafSjean-michel.hautbois@vodalys.com .field1_vfrontporch_mask = 0x3fff, 27355380baafSjean-michel.hautbois@vodalys.com .field1_vsync_mask = 0x3fff, 27365380baafSjean-michel.hautbois@vodalys.com .field1_vbackporch_mask = 0x3fff, 2737d42010a1SLars-Peter Clausen }, 27388331d30bSWilliam Towle [ADV7612] = { 27398331d30bSWilliam Towle .type = ADV7612, 27408331d30bSWilliam Towle .has_afe = false, 27417111cdddSWilliam Towle .max_port = ADV76XX_PAD_HDMI_PORT_A, /* B not supported */ 27427111cdddSWilliam Towle .num_dv_ports = 1, /* normally 2 */ 27438331d30bSWilliam Towle .edid_enable_reg = 0x74, 27448331d30bSWilliam Towle .edid_status_reg = 0x76, 27458331d30bSWilliam Towle .lcf_reg = 0xa3, 27468331d30bSWilliam Towle .tdms_lock_mask = 0x43, 27478331d30bSWilliam Towle .cable_det_mask = 0x01, 27488331d30bSWilliam Towle .fmt_change_digital_mask = 0x03, 27497111cdddSWilliam Towle .cp_csc = 0xf4, 27508331d30bSWilliam Towle .formats = adv7612_formats, 27518331d30bSWilliam Towle .nformats = ARRAY_SIZE(adv7612_formats), 27528331d30bSWilliam Towle .set_termination = adv7611_set_termination, 27538331d30bSWilliam Towle .setup_irqs = adv7612_setup_irqs, 27548331d30bSWilliam Towle .read_hdmi_pixelclock = adv7611_read_hdmi_pixelclock, 27557111cdddSWilliam Towle .read_cable_det = adv7612_read_cable_det, 27568331d30bSWilliam Towle .recommended_settings = { 27578331d30bSWilliam Towle [1] = adv7612_recommended_settings_hdmi, 27588331d30bSWilliam Towle }, 27598331d30bSWilliam Towle .num_recommended_settings = { 27608331d30bSWilliam Towle [1] = ARRAY_SIZE(adv7612_recommended_settings_hdmi), 27618331d30bSWilliam Towle }, 27628331d30bSWilliam Towle .page_mask = BIT(ADV76XX_PAGE_IO) | BIT(ADV76XX_PAGE_CEC) | 27638331d30bSWilliam Towle BIT(ADV76XX_PAGE_INFOFRAME) | BIT(ADV76XX_PAGE_AFE) | 27648331d30bSWilliam Towle BIT(ADV76XX_PAGE_REP) | BIT(ADV76XX_PAGE_EDID) | 27658331d30bSWilliam Towle BIT(ADV76XX_PAGE_HDMI) | BIT(ADV76XX_PAGE_CP), 27668331d30bSWilliam Towle .linewidth_mask = 0x1fff, 27678331d30bSWilliam Towle .field0_height_mask = 0x1fff, 27688331d30bSWilliam Towle .field1_height_mask = 0x1fff, 27698331d30bSWilliam Towle .hfrontporch_mask = 0x1fff, 27708331d30bSWilliam Towle .hsync_mask = 0x1fff, 27718331d30bSWilliam Towle .hbackporch_mask = 0x1fff, 27728331d30bSWilliam Towle .field0_vfrontporch_mask = 0x3fff, 27738331d30bSWilliam Towle .field0_vsync_mask = 0x3fff, 27748331d30bSWilliam Towle .field0_vbackporch_mask = 0x3fff, 27758331d30bSWilliam Towle .field1_vfrontporch_mask = 0x3fff, 27768331d30bSWilliam Towle .field1_vsync_mask = 0x3fff, 27778331d30bSWilliam Towle .field1_vbackporch_mask = 0x3fff, 27788331d30bSWilliam Towle }, 2779d42010a1SLars-Peter Clausen }; 2780d42010a1SLars-Peter Clausen 27817f099a75SFabian Frederick static const struct i2c_device_id adv76xx_i2c_id[] = { 2782b44b2e06SPablo Anton { "adv7604", (kernel_ulong_t)&adv76xx_chip_info[ADV7604] }, 2783b44b2e06SPablo Anton { "adv7611", (kernel_ulong_t)&adv76xx_chip_info[ADV7611] }, 27848331d30bSWilliam Towle { "adv7612", (kernel_ulong_t)&adv76xx_chip_info[ADV7612] }, 2785f82f313eSLaurent Pinchart { } 2786f82f313eSLaurent Pinchart }; 2787b44b2e06SPablo Anton MODULE_DEVICE_TABLE(i2c, adv76xx_i2c_id); 2788f82f313eSLaurent Pinchart 27897f099a75SFabian Frederick static const struct of_device_id adv76xx_of_id[] __maybe_unused = { 2790b44b2e06SPablo Anton { .compatible = "adi,adv7611", .data = &adv76xx_chip_info[ADV7611] }, 27918331d30bSWilliam Towle { .compatible = "adi,adv7612", .data = &adv76xx_chip_info[ADV7612] }, 2792f82f313eSLaurent Pinchart { } 2793f82f313eSLaurent Pinchart }; 2794b44b2e06SPablo Anton MODULE_DEVICE_TABLE(of, adv76xx_of_id); 2795f82f313eSLaurent Pinchart 2796b44b2e06SPablo Anton static int adv76xx_parse_dt(struct adv76xx_state *state) 2797f82f313eSLaurent Pinchart { 27986fa88045SLaurent Pinchart struct v4l2_of_endpoint bus_cfg; 27996fa88045SLaurent Pinchart struct device_node *endpoint; 28006fa88045SLaurent Pinchart struct device_node *np; 28016fa88045SLaurent Pinchart unsigned int flags; 2802bf9c8227SIan Molton u32 v; 28036fa88045SLaurent Pinchart 2804b44b2e06SPablo Anton np = state->i2c_clients[ADV76XX_PAGE_IO]->dev.of_node; 28056fa88045SLaurent Pinchart 28066fa88045SLaurent Pinchart /* Parse the endpoint. */ 28076fa88045SLaurent Pinchart endpoint = of_graph_get_next_endpoint(np, NULL); 28086fa88045SLaurent Pinchart if (!endpoint) 28096fa88045SLaurent Pinchart return -EINVAL; 28106fa88045SLaurent Pinchart 28116fa88045SLaurent Pinchart v4l2_of_parse_endpoint(endpoint, &bus_cfg); 2812bf9c8227SIan Molton 2813bf9c8227SIan Molton if (!of_property_read_u32(endpoint, "default-input", &v)) 2814bf9c8227SIan Molton state->pdata.default_input = v; 2815bf9c8227SIan Molton else 2816bf9c8227SIan Molton state->pdata.default_input = -1; 2817bf9c8227SIan Molton 28186fa88045SLaurent Pinchart of_node_put(endpoint); 28196fa88045SLaurent Pinchart 28206fa88045SLaurent Pinchart flags = bus_cfg.bus.parallel.flags; 28216fa88045SLaurent Pinchart 28226fa88045SLaurent Pinchart if (flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH) 28236fa88045SLaurent Pinchart state->pdata.inv_hs_pol = 1; 28246fa88045SLaurent Pinchart 28256fa88045SLaurent Pinchart if (flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH) 28266fa88045SLaurent Pinchart state->pdata.inv_vs_pol = 1; 28276fa88045SLaurent Pinchart 28286fa88045SLaurent Pinchart if (flags & V4L2_MBUS_PCLK_SAMPLE_RISING) 28296fa88045SLaurent Pinchart state->pdata.inv_llc_pol = 1; 28306fa88045SLaurent Pinchart 28316fa88045SLaurent Pinchart if (bus_cfg.bus_type == V4L2_MBUS_BT656) { 28326fa88045SLaurent Pinchart state->pdata.insert_av_codes = 1; 28336fa88045SLaurent Pinchart state->pdata.op_656_range = 1; 28346fa88045SLaurent Pinchart } 28356fa88045SLaurent Pinchart 2836f82f313eSLaurent Pinchart /* Disable the interrupt for now as no DT-based board uses it. */ 2837b44b2e06SPablo Anton state->pdata.int1_config = ADV76XX_INT1_CONFIG_DISABLED; 2838f82f313eSLaurent Pinchart 2839f82f313eSLaurent Pinchart /* Use the default I2C addresses. */ 2840f82f313eSLaurent Pinchart state->pdata.i2c_addresses[ADV7604_PAGE_AVLINK] = 0x42; 2841b44b2e06SPablo Anton state->pdata.i2c_addresses[ADV76XX_PAGE_CEC] = 0x40; 2842b44b2e06SPablo Anton state->pdata.i2c_addresses[ADV76XX_PAGE_INFOFRAME] = 0x3e; 2843f82f313eSLaurent Pinchart state->pdata.i2c_addresses[ADV7604_PAGE_ESDP] = 0x38; 2844f82f313eSLaurent Pinchart state->pdata.i2c_addresses[ADV7604_PAGE_DPP] = 0x3c; 2845b44b2e06SPablo Anton state->pdata.i2c_addresses[ADV76XX_PAGE_AFE] = 0x26; 2846b44b2e06SPablo Anton state->pdata.i2c_addresses[ADV76XX_PAGE_REP] = 0x32; 2847b44b2e06SPablo Anton state->pdata.i2c_addresses[ADV76XX_PAGE_EDID] = 0x36; 2848b44b2e06SPablo Anton state->pdata.i2c_addresses[ADV76XX_PAGE_HDMI] = 0x34; 2849b44b2e06SPablo Anton state->pdata.i2c_addresses[ADV76XX_PAGE_TEST] = 0x30; 2850b44b2e06SPablo Anton state->pdata.i2c_addresses[ADV76XX_PAGE_CP] = 0x22; 2851f82f313eSLaurent Pinchart state->pdata.i2c_addresses[ADV7604_PAGE_VDP] = 0x24; 2852f82f313eSLaurent Pinchart 2853f82f313eSLaurent Pinchart /* Hardcode the remaining platform data fields. */ 2854f82f313eSLaurent Pinchart state->pdata.disable_pwrdnb = 0; 2855f82f313eSLaurent Pinchart state->pdata.disable_cable_det_rst = 0; 2856f82f313eSLaurent Pinchart state->pdata.blank_data = 1; 2857f82f313eSLaurent Pinchart state->pdata.alt_data_sat = 1; 2858f82f313eSLaurent Pinchart state->pdata.op_format_mode_sel = ADV7604_OP_FORMAT_MODE0; 2859f82f313eSLaurent Pinchart state->pdata.bus_order = ADV7604_BUS_ORDER_RGB; 2860f82f313eSLaurent Pinchart 2861f82f313eSLaurent Pinchart return 0; 2862f82f313eSLaurent Pinchart } 2863f82f313eSLaurent Pinchart 2864f862f57dSPablo Anton static const struct regmap_config adv76xx_regmap_cnf[] = { 2865f862f57dSPablo Anton { 2866f862f57dSPablo Anton .name = "io", 2867f862f57dSPablo Anton .reg_bits = 8, 2868f862f57dSPablo Anton .val_bits = 8, 2869f862f57dSPablo Anton 2870f862f57dSPablo Anton .max_register = 0xff, 2871f862f57dSPablo Anton .cache_type = REGCACHE_NONE, 2872f862f57dSPablo Anton }, 2873f862f57dSPablo Anton { 2874f862f57dSPablo Anton .name = "avlink", 2875f862f57dSPablo Anton .reg_bits = 8, 2876f862f57dSPablo Anton .val_bits = 8, 2877f862f57dSPablo Anton 2878f862f57dSPablo Anton .max_register = 0xff, 2879f862f57dSPablo Anton .cache_type = REGCACHE_NONE, 2880f862f57dSPablo Anton }, 2881f862f57dSPablo Anton { 2882f862f57dSPablo Anton .name = "cec", 2883f862f57dSPablo Anton .reg_bits = 8, 2884f862f57dSPablo Anton .val_bits = 8, 2885f862f57dSPablo Anton 2886f862f57dSPablo Anton .max_register = 0xff, 2887f862f57dSPablo Anton .cache_type = REGCACHE_NONE, 2888f862f57dSPablo Anton }, 2889f862f57dSPablo Anton { 2890f862f57dSPablo Anton .name = "infoframe", 2891f862f57dSPablo Anton .reg_bits = 8, 2892f862f57dSPablo Anton .val_bits = 8, 2893f862f57dSPablo Anton 2894f862f57dSPablo Anton .max_register = 0xff, 2895f862f57dSPablo Anton .cache_type = REGCACHE_NONE, 2896f862f57dSPablo Anton }, 2897f862f57dSPablo Anton { 2898f862f57dSPablo Anton .name = "esdp", 2899f862f57dSPablo Anton .reg_bits = 8, 2900f862f57dSPablo Anton .val_bits = 8, 2901f862f57dSPablo Anton 2902f862f57dSPablo Anton .max_register = 0xff, 2903f862f57dSPablo Anton .cache_type = REGCACHE_NONE, 2904f862f57dSPablo Anton }, 2905f862f57dSPablo Anton { 2906f862f57dSPablo Anton .name = "epp", 2907f862f57dSPablo Anton .reg_bits = 8, 2908f862f57dSPablo Anton .val_bits = 8, 2909f862f57dSPablo Anton 2910f862f57dSPablo Anton .max_register = 0xff, 2911f862f57dSPablo Anton .cache_type = REGCACHE_NONE, 2912f862f57dSPablo Anton }, 2913f862f57dSPablo Anton { 2914f862f57dSPablo Anton .name = "afe", 2915f862f57dSPablo Anton .reg_bits = 8, 2916f862f57dSPablo Anton .val_bits = 8, 2917f862f57dSPablo Anton 2918f862f57dSPablo Anton .max_register = 0xff, 2919f862f57dSPablo Anton .cache_type = REGCACHE_NONE, 2920f862f57dSPablo Anton }, 2921f862f57dSPablo Anton { 2922f862f57dSPablo Anton .name = "rep", 2923f862f57dSPablo Anton .reg_bits = 8, 2924f862f57dSPablo Anton .val_bits = 8, 2925f862f57dSPablo Anton 2926f862f57dSPablo Anton .max_register = 0xff, 2927f862f57dSPablo Anton .cache_type = REGCACHE_NONE, 2928f862f57dSPablo Anton }, 2929f862f57dSPablo Anton { 2930f862f57dSPablo Anton .name = "edid", 2931f862f57dSPablo Anton .reg_bits = 8, 2932f862f57dSPablo Anton .val_bits = 8, 2933f862f57dSPablo Anton 2934f862f57dSPablo Anton .max_register = 0xff, 2935f862f57dSPablo Anton .cache_type = REGCACHE_NONE, 2936f862f57dSPablo Anton }, 2937f862f57dSPablo Anton 2938f862f57dSPablo Anton { 2939f862f57dSPablo Anton .name = "hdmi", 2940f862f57dSPablo Anton .reg_bits = 8, 2941f862f57dSPablo Anton .val_bits = 8, 2942f862f57dSPablo Anton 2943f862f57dSPablo Anton .max_register = 0xff, 2944f862f57dSPablo Anton .cache_type = REGCACHE_NONE, 2945f862f57dSPablo Anton }, 2946f862f57dSPablo Anton { 2947f862f57dSPablo Anton .name = "test", 2948f862f57dSPablo Anton .reg_bits = 8, 2949f862f57dSPablo Anton .val_bits = 8, 2950f862f57dSPablo Anton 2951f862f57dSPablo Anton .max_register = 0xff, 2952f862f57dSPablo Anton .cache_type = REGCACHE_NONE, 2953f862f57dSPablo Anton }, 2954f862f57dSPablo Anton { 2955f862f57dSPablo Anton .name = "cp", 2956f862f57dSPablo Anton .reg_bits = 8, 2957f862f57dSPablo Anton .val_bits = 8, 2958f862f57dSPablo Anton 2959f862f57dSPablo Anton .max_register = 0xff, 2960f862f57dSPablo Anton .cache_type = REGCACHE_NONE, 2961f862f57dSPablo Anton }, 2962f862f57dSPablo Anton { 2963f862f57dSPablo Anton .name = "vdp", 2964f862f57dSPablo Anton .reg_bits = 8, 2965f862f57dSPablo Anton .val_bits = 8, 2966f862f57dSPablo Anton 2967f862f57dSPablo Anton .max_register = 0xff, 2968f862f57dSPablo Anton .cache_type = REGCACHE_NONE, 2969f862f57dSPablo Anton }, 2970f862f57dSPablo Anton }; 2971f862f57dSPablo Anton 2972f862f57dSPablo Anton static int configure_regmap(struct adv76xx_state *state, int region) 2973f862f57dSPablo Anton { 2974f862f57dSPablo Anton int err; 2975f862f57dSPablo Anton 2976f862f57dSPablo Anton if (!state->i2c_clients[region]) 2977f862f57dSPablo Anton return -ENODEV; 2978f862f57dSPablo Anton 2979f862f57dSPablo Anton state->regmap[region] = 2980f862f57dSPablo Anton devm_regmap_init_i2c(state->i2c_clients[region], 2981f862f57dSPablo Anton &adv76xx_regmap_cnf[region]); 2982f862f57dSPablo Anton 2983f862f57dSPablo Anton if (IS_ERR(state->regmap[region])) { 2984f862f57dSPablo Anton err = PTR_ERR(state->regmap[region]); 2985f862f57dSPablo Anton v4l_err(state->i2c_clients[region], 2986f862f57dSPablo Anton "Error initializing regmap %d with error %d\n", 2987f862f57dSPablo Anton region, err); 2988f862f57dSPablo Anton return -EINVAL; 2989f862f57dSPablo Anton } 2990f862f57dSPablo Anton 2991f862f57dSPablo Anton return 0; 2992f862f57dSPablo Anton } 2993f862f57dSPablo Anton 2994f862f57dSPablo Anton static int configure_regmaps(struct adv76xx_state *state) 2995f862f57dSPablo Anton { 2996f862f57dSPablo Anton int i, err; 2997f862f57dSPablo Anton 2998f862f57dSPablo Anton for (i = ADV7604_PAGE_AVLINK ; i < ADV76XX_PAGE_MAX; i++) { 2999f862f57dSPablo Anton err = configure_regmap(state, i); 3000f862f57dSPablo Anton if (err && (err != -ENODEV)) 3001f862f57dSPablo Anton return err; 3002f862f57dSPablo Anton } 3003f862f57dSPablo Anton return 0; 3004f862f57dSPablo Anton } 3005f862f57dSPablo Anton 3006b44b2e06SPablo Anton static int adv76xx_probe(struct i2c_client *client, 300754450f59SHans Verkuil const struct i2c_device_id *id) 300854450f59SHans Verkuil { 3009591b72feSHans Verkuil static const struct v4l2_dv_timings cea640x480 = 3010591b72feSHans Verkuil V4L2_DV_BT_CEA_640X480P59_94; 3011b44b2e06SPablo Anton struct adv76xx_state *state; 301254450f59SHans Verkuil struct v4l2_ctrl_handler *hdl; 301354450f59SHans Verkuil struct v4l2_subdev *sd; 3014c784b1e2SLaurent Pinchart unsigned int i; 3015f862f57dSPablo Anton unsigned int val, val2; 301654450f59SHans Verkuil int err; 301754450f59SHans Verkuil 301854450f59SHans Verkuil /* Check if the adapter supports the needed features */ 301954450f59SHans Verkuil if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA)) 302054450f59SHans Verkuil return -EIO; 3021b44b2e06SPablo Anton v4l_dbg(1, debug, client, "detecting adv76xx client on address 0x%x\n", 302254450f59SHans Verkuil client->addr << 1); 302354450f59SHans Verkuil 3024c02b211dSLaurent Pinchart state = devm_kzalloc(&client->dev, sizeof(*state), GFP_KERNEL); 302554450f59SHans Verkuil if (!state) { 3026b44b2e06SPablo Anton v4l_err(client, "Could not allocate adv76xx_state memory!\n"); 302754450f59SHans Verkuil return -ENOMEM; 302854450f59SHans Verkuil } 302954450f59SHans Verkuil 3030b44b2e06SPablo Anton state->i2c_clients[ADV76XX_PAGE_IO] = client; 3031d42010a1SLars-Peter Clausen 303225a64ac9SMats Randgaard /* initialize variables */ 303325a64ac9SMats Randgaard state->restart_stdi_once = true; 3034ff4f80fdSMats Randgaard state->selected_input = ~0; 303525a64ac9SMats Randgaard 3036f82f313eSLaurent Pinchart if (IS_ENABLED(CONFIG_OF) && client->dev.of_node) { 3037f82f313eSLaurent Pinchart const struct of_device_id *oid; 3038f82f313eSLaurent Pinchart 3039b44b2e06SPablo Anton oid = of_match_node(adv76xx_of_id, client->dev.of_node); 3040f82f313eSLaurent Pinchart state->info = oid->data; 3041f82f313eSLaurent Pinchart 3042b44b2e06SPablo Anton err = adv76xx_parse_dt(state); 3043f82f313eSLaurent Pinchart if (err < 0) { 3044f82f313eSLaurent Pinchart v4l_err(client, "DT parsing error\n"); 3045f82f313eSLaurent Pinchart return err; 3046f82f313eSLaurent Pinchart } 3047f82f313eSLaurent Pinchart } else if (client->dev.platform_data) { 3048b44b2e06SPablo Anton struct adv76xx_platform_data *pdata = client->dev.platform_data; 3049f82f313eSLaurent Pinchart 3050b44b2e06SPablo Anton state->info = (const struct adv76xx_chip_info *)id->driver_data; 3051f82f313eSLaurent Pinchart state->pdata = *pdata; 3052f82f313eSLaurent Pinchart } else { 305354450f59SHans Verkuil v4l_err(client, "No platform data!\n"); 3054c02b211dSLaurent Pinchart return -ENODEV; 305554450f59SHans Verkuil } 3056e9d50e9eSLaurent Pinchart 3057e9d50e9eSLaurent Pinchart /* Request GPIOs. */ 3058e9d50e9eSLaurent Pinchart for (i = 0; i < state->info->num_dv_ports; ++i) { 3059e9d50e9eSLaurent Pinchart state->hpd_gpio[i] = 3060269bd132SUwe Kleine-König devm_gpiod_get_index_optional(&client->dev, "hpd", i, 3061269bd132SUwe Kleine-König GPIOD_OUT_LOW); 3062e9d50e9eSLaurent Pinchart if (IS_ERR(state->hpd_gpio[i])) 3063269bd132SUwe Kleine-König return PTR_ERR(state->hpd_gpio[i]); 3064e9d50e9eSLaurent Pinchart 3065269bd132SUwe Kleine-König if (state->hpd_gpio[i]) 3066e9d50e9eSLaurent Pinchart v4l_info(client, "Handling HPD %u GPIO\n", i); 3067e9d50e9eSLaurent Pinchart } 3068e9d50e9eSLaurent Pinchart 3069591b72feSHans Verkuil state->timings = cea640x480; 3070b44b2e06SPablo Anton state->format = adv76xx_format_info(state, MEDIA_BUS_FMT_YUYV8_2X8); 307154450f59SHans Verkuil 307254450f59SHans Verkuil sd = &state->sd; 3073b44b2e06SPablo Anton v4l2_i2c_subdev_init(sd, client, &adv76xx_ops); 3074d42010a1SLars-Peter Clausen snprintf(sd->name, sizeof(sd->name), "%s %d-%04x", 3075d42010a1SLars-Peter Clausen id->name, i2c_adapter_id(client->adapter), 3076d42010a1SLars-Peter Clausen client->addr); 30770975626dSLars-Peter Clausen sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS; 307854450f59SHans Verkuil 3079f862f57dSPablo Anton /* Configure IO Regmap region */ 3080f862f57dSPablo Anton err = configure_regmap(state, ADV76XX_PAGE_IO); 3081f862f57dSPablo Anton 3082f862f57dSPablo Anton if (err) { 3083f862f57dSPablo Anton v4l2_err(sd, "Error configuring IO regmap region\n"); 3084f862f57dSPablo Anton return -ENODEV; 3085f862f57dSPablo Anton } 3086f862f57dSPablo Anton 3087d42010a1SLars-Peter Clausen /* 3088d42010a1SLars-Peter Clausen * Verify that the chip is present. On ADV7604 the RD_INFO register only 3089d42010a1SLars-Peter Clausen * identifies the revision, while on ADV7611 it identifies the model as 3090d42010a1SLars-Peter Clausen * well. Use the HDMI slave address on ADV7604 and RD_INFO on ADV7611. 3091d42010a1SLars-Peter Clausen */ 30928331d30bSWilliam Towle switch (state->info->type) { 30938331d30bSWilliam Towle case ADV7604: 3094f862f57dSPablo Anton err = regmap_read(state->regmap[ADV76XX_PAGE_IO], 0xfb, &val); 3095f862f57dSPablo Anton if (err) { 3096f862f57dSPablo Anton v4l2_err(sd, "Error %d reading IO Regmap\n", err); 3097f862f57dSPablo Anton return -ENODEV; 3098f862f57dSPablo Anton } 3099d42010a1SLars-Peter Clausen if (val != 0x68) { 3100f862f57dSPablo Anton v4l2_err(sd, "not an adv7604 on address 0x%x\n", 310154450f59SHans Verkuil client->addr << 1); 3102c02b211dSLaurent Pinchart return -ENODEV; 310354450f59SHans Verkuil } 31048331d30bSWilliam Towle break; 31058331d30bSWilliam Towle case ADV7611: 31068331d30bSWilliam Towle case ADV7612: 3107f862f57dSPablo Anton err = regmap_read(state->regmap[ADV76XX_PAGE_IO], 3108f862f57dSPablo Anton 0xea, 3109f862f57dSPablo Anton &val); 3110f862f57dSPablo Anton if (err) { 3111f862f57dSPablo Anton v4l2_err(sd, "Error %d reading IO Regmap\n", err); 3112f862f57dSPablo Anton return -ENODEV; 3113f862f57dSPablo Anton } 3114f862f57dSPablo Anton val2 = val << 8; 3115f862f57dSPablo Anton err = regmap_read(state->regmap[ADV76XX_PAGE_IO], 3116f862f57dSPablo Anton 0xeb, 3117f862f57dSPablo Anton &val); 3118f862f57dSPablo Anton if (err) { 3119f862f57dSPablo Anton v4l2_err(sd, "Error %d reading IO Regmap\n", err); 3120f862f57dSPablo Anton return -ENODEV; 3121f862f57dSPablo Anton } 3122c1362384SWilliam Towle val |= val2; 31238331d30bSWilliam Towle if ((state->info->type == ADV7611 && val != 0x2051) || 31248331d30bSWilliam Towle (state->info->type == ADV7612 && val != 0x2041)) { 31258331d30bSWilliam Towle v4l2_err(sd, "not an adv761x on address 0x%x\n", 3126d42010a1SLars-Peter Clausen client->addr << 1); 3127d42010a1SLars-Peter Clausen return -ENODEV; 3128d42010a1SLars-Peter Clausen } 31298331d30bSWilliam Towle break; 3130d42010a1SLars-Peter Clausen } 313154450f59SHans Verkuil 313254450f59SHans Verkuil /* control handlers */ 313354450f59SHans Verkuil hdl = &state->hdl; 3134b44b2e06SPablo Anton v4l2_ctrl_handler_init(hdl, adv76xx_has_afe(state) ? 9 : 8); 313554450f59SHans Verkuil 3136b44b2e06SPablo Anton v4l2_ctrl_new_std(hdl, &adv76xx_ctrl_ops, 313754450f59SHans Verkuil V4L2_CID_BRIGHTNESS, -128, 127, 1, 0); 3138b44b2e06SPablo Anton v4l2_ctrl_new_std(hdl, &adv76xx_ctrl_ops, 313954450f59SHans Verkuil V4L2_CID_CONTRAST, 0, 255, 1, 128); 3140b44b2e06SPablo Anton v4l2_ctrl_new_std(hdl, &adv76xx_ctrl_ops, 314154450f59SHans Verkuil V4L2_CID_SATURATION, 0, 255, 1, 128); 3142b44b2e06SPablo Anton v4l2_ctrl_new_std(hdl, &adv76xx_ctrl_ops, 314354450f59SHans Verkuil V4L2_CID_HUE, 0, 128, 1, 0); 314454450f59SHans Verkuil 314554450f59SHans Verkuil /* private controls */ 314654450f59SHans Verkuil state->detect_tx_5v_ctrl = v4l2_ctrl_new_std(hdl, NULL, 3147d42010a1SLars-Peter Clausen V4L2_CID_DV_RX_POWER_PRESENT, 0, 3148d42010a1SLars-Peter Clausen (1 << state->info->num_dv_ports) - 1, 0, 0); 314954450f59SHans Verkuil state->rgb_quantization_range_ctrl = 3150b44b2e06SPablo Anton v4l2_ctrl_new_std_menu(hdl, &adv76xx_ctrl_ops, 315154450f59SHans Verkuil V4L2_CID_DV_RX_RGB_RANGE, V4L2_DV_RGB_RANGE_FULL, 315254450f59SHans Verkuil 0, V4L2_DV_RGB_RANGE_AUTO); 315354450f59SHans Verkuil 315454450f59SHans Verkuil /* custom controls */ 3155b44b2e06SPablo Anton if (adv76xx_has_afe(state)) 315654450f59SHans Verkuil state->analog_sampling_phase_ctrl = 315754450f59SHans Verkuil v4l2_ctrl_new_custom(hdl, &adv7604_ctrl_analog_sampling_phase, NULL); 315854450f59SHans Verkuil state->free_run_color_manual_ctrl = 3159b44b2e06SPablo Anton v4l2_ctrl_new_custom(hdl, &adv76xx_ctrl_free_run_color_manual, NULL); 316054450f59SHans Verkuil state->free_run_color_ctrl = 3161b44b2e06SPablo Anton v4l2_ctrl_new_custom(hdl, &adv76xx_ctrl_free_run_color, NULL); 316254450f59SHans Verkuil 316354450f59SHans Verkuil sd->ctrl_handler = hdl; 316454450f59SHans Verkuil if (hdl->error) { 316554450f59SHans Verkuil err = hdl->error; 316654450f59SHans Verkuil goto err_hdl; 316754450f59SHans Verkuil } 31688c0eadb8SHans Verkuil state->detect_tx_5v_ctrl->is_private = true; 31698c0eadb8SHans Verkuil state->rgb_quantization_range_ctrl->is_private = true; 3170b44b2e06SPablo Anton if (adv76xx_has_afe(state)) 31718c0eadb8SHans Verkuil state->analog_sampling_phase_ctrl->is_private = true; 31728c0eadb8SHans Verkuil state->free_run_color_manual_ctrl->is_private = true; 31738c0eadb8SHans Verkuil state->free_run_color_ctrl->is_private = true; 31748c0eadb8SHans Verkuil 3175b44b2e06SPablo Anton if (adv76xx_s_detect_tx_5v_ctrl(sd)) { 317654450f59SHans Verkuil err = -ENODEV; 317754450f59SHans Verkuil goto err_hdl; 317854450f59SHans Verkuil } 317954450f59SHans Verkuil 3180b44b2e06SPablo Anton for (i = 1; i < ADV76XX_PAGE_MAX; ++i) { 318105cacb17SLaurent Pinchart if (!(BIT(i) & state->info->page_mask)) 318205cacb17SLaurent Pinchart continue; 318305cacb17SLaurent Pinchart 318405cacb17SLaurent Pinchart state->i2c_clients[i] = 3185b44b2e06SPablo Anton adv76xx_dummy_client(sd, state->pdata.i2c_addresses[i], 318605cacb17SLaurent Pinchart 0xf2 + i); 318705cacb17SLaurent Pinchart if (state->i2c_clients[i] == NULL) { 318854450f59SHans Verkuil err = -ENOMEM; 318905cacb17SLaurent Pinchart v4l2_err(sd, "failed to create i2c client %u\n", i); 319054450f59SHans Verkuil goto err_i2c; 319154450f59SHans Verkuil } 319205cacb17SLaurent Pinchart } 319354450f59SHans Verkuil 319454450f59SHans Verkuil /* work queues */ 319554450f59SHans Verkuil state->work_queues = create_singlethread_workqueue(client->name); 319654450f59SHans Verkuil if (!state->work_queues) { 319754450f59SHans Verkuil v4l2_err(sd, "Could not create work queue\n"); 319854450f59SHans Verkuil err = -ENOMEM; 319954450f59SHans Verkuil goto err_i2c; 320054450f59SHans Verkuil } 320154450f59SHans Verkuil 320254450f59SHans Verkuil INIT_DELAYED_WORK(&state->delayed_work_enable_hotplug, 3203b44b2e06SPablo Anton adv76xx_delayed_work_enable_hotplug); 320454450f59SHans Verkuil 3205c784b1e2SLaurent Pinchart state->source_pad = state->info->num_dv_ports 3206c784b1e2SLaurent Pinchart + (state->info->has_afe ? 2 : 0); 3207c784b1e2SLaurent Pinchart for (i = 0; i < state->source_pad; ++i) 3208c784b1e2SLaurent Pinchart state->pads[i].flags = MEDIA_PAD_FL_SINK; 3209c784b1e2SLaurent Pinchart state->pads[state->source_pad].flags = MEDIA_PAD_FL_SOURCE; 3210c784b1e2SLaurent Pinchart 3211ab22e77cSMauro Carvalho Chehab err = media_entity_pads_init(&sd->entity, state->source_pad + 1, 321218095107SMauro Carvalho Chehab state->pads); 321354450f59SHans Verkuil if (err) 321454450f59SHans Verkuil goto err_work_queues; 321554450f59SHans Verkuil 3216f862f57dSPablo Anton /* Configure regmaps */ 3217f862f57dSPablo Anton err = configure_regmaps(state); 3218f862f57dSPablo Anton if (err) 3219f862f57dSPablo Anton goto err_entity; 3220f862f57dSPablo Anton 3221b44b2e06SPablo Anton err = adv76xx_core_init(sd); 322254450f59SHans Verkuil if (err) 322354450f59SHans Verkuil goto err_entity; 322454450f59SHans Verkuil v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name, 322554450f59SHans Verkuil client->addr << 1, client->adapter->name); 3226bedc3939SLars-Peter Clausen 3227bedc3939SLars-Peter Clausen err = v4l2_async_register_subdev(sd); 3228bedc3939SLars-Peter Clausen if (err) 3229bedc3939SLars-Peter Clausen goto err_entity; 3230bedc3939SLars-Peter Clausen 323154450f59SHans Verkuil return 0; 323254450f59SHans Verkuil 323354450f59SHans Verkuil err_entity: 323454450f59SHans Verkuil media_entity_cleanup(&sd->entity); 323554450f59SHans Verkuil err_work_queues: 323654450f59SHans Verkuil cancel_delayed_work(&state->delayed_work_enable_hotplug); 323754450f59SHans Verkuil destroy_workqueue(state->work_queues); 323854450f59SHans Verkuil err_i2c: 3239b44b2e06SPablo Anton adv76xx_unregister_clients(state); 324054450f59SHans Verkuil err_hdl: 324154450f59SHans Verkuil v4l2_ctrl_handler_free(hdl); 324254450f59SHans Verkuil return err; 324354450f59SHans Verkuil } 324454450f59SHans Verkuil 324554450f59SHans Verkuil /* ----------------------------------------------------------------------- */ 324654450f59SHans Verkuil 3247b44b2e06SPablo Anton static int adv76xx_remove(struct i2c_client *client) 324854450f59SHans Verkuil { 324954450f59SHans Verkuil struct v4l2_subdev *sd = i2c_get_clientdata(client); 3250b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 325154450f59SHans Verkuil 325254450f59SHans Verkuil cancel_delayed_work(&state->delayed_work_enable_hotplug); 325354450f59SHans Verkuil destroy_workqueue(state->work_queues); 3254bedc3939SLars-Peter Clausen v4l2_async_unregister_subdev(sd); 325554450f59SHans Verkuil media_entity_cleanup(&sd->entity); 3256b44b2e06SPablo Anton adv76xx_unregister_clients(to_state(sd)); 325754450f59SHans Verkuil v4l2_ctrl_handler_free(sd->ctrl_handler); 325854450f59SHans Verkuil return 0; 325954450f59SHans Verkuil } 326054450f59SHans Verkuil 326154450f59SHans Verkuil /* ----------------------------------------------------------------------- */ 326254450f59SHans Verkuil 3263b44b2e06SPablo Anton static struct i2c_driver adv76xx_driver = { 326454450f59SHans Verkuil .driver = { 326554450f59SHans Verkuil .name = "adv7604", 3266b44b2e06SPablo Anton .of_match_table = of_match_ptr(adv76xx_of_id), 326754450f59SHans Verkuil }, 3268b44b2e06SPablo Anton .probe = adv76xx_probe, 3269b44b2e06SPablo Anton .remove = adv76xx_remove, 3270b44b2e06SPablo Anton .id_table = adv76xx_i2c_id, 327154450f59SHans Verkuil }; 327254450f59SHans Verkuil 3273b44b2e06SPablo Anton module_i2c_driver(adv76xx_driver); 3274