154450f59SHans Verkuil /* 254450f59SHans Verkuil * adv7604 - Analog Devices ADV7604 video decoder driver 354450f59SHans Verkuil * 454450f59SHans Verkuil * Copyright 2012 Cisco Systems, Inc. and/or its affiliates. All rights reserved. 554450f59SHans Verkuil * 654450f59SHans Verkuil * This program is free software; you may redistribute it and/or modify 754450f59SHans Verkuil * it under the terms of the GNU General Public License as published by 854450f59SHans Verkuil * the Free Software Foundation; version 2 of the License. 954450f59SHans Verkuil * 1054450f59SHans Verkuil * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 1154450f59SHans Verkuil * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 1254450f59SHans Verkuil * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 1354450f59SHans Verkuil * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 1454450f59SHans Verkuil * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 1554450f59SHans Verkuil * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 1654450f59SHans Verkuil * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 1754450f59SHans Verkuil * SOFTWARE. 1854450f59SHans Verkuil * 1954450f59SHans Verkuil */ 2054450f59SHans Verkuil 2154450f59SHans Verkuil /* 2254450f59SHans Verkuil * References (c = chapter, p = page): 2354450f59SHans Verkuil * REF_01 - Analog devices, ADV7604, Register Settings Recommendations, 2454450f59SHans Verkuil * Revision 2.5, June 2010 2554450f59SHans Verkuil * REF_02 - Analog devices, Register map documentation, Documentation of 2654450f59SHans Verkuil * the register maps, Software manual, Rev. F, June 2010 2754450f59SHans Verkuil * REF_03 - Analog devices, ADV7604, Hardware Manual, Rev. F, August 2010 2854450f59SHans Verkuil */ 2954450f59SHans Verkuil 30c72a53ceSLaurent Pinchart #include <linux/delay.h> 31e9d50e9eSLaurent Pinchart #include <linux/gpio/consumer.h> 32516613c1SHans Verkuil #include <linux/hdmi.h> 33c72a53ceSLaurent Pinchart #include <linux/i2c.h> 3454450f59SHans Verkuil #include <linux/kernel.h> 3554450f59SHans Verkuil #include <linux/module.h> 3654450f59SHans Verkuil #include <linux/slab.h> 37c72a53ceSLaurent Pinchart #include <linux/v4l2-dv-timings.h> 3854450f59SHans Verkuil #include <linux/videodev2.h> 3954450f59SHans Verkuil #include <linux/workqueue.h> 40f862f57dSPablo Anton #include <linux/regmap.h> 41c72a53ceSLaurent Pinchart 4254450f59SHans Verkuil #include <media/adv7604.h> 43c72a53ceSLaurent Pinchart #include <media/v4l2-ctrls.h> 44c72a53ceSLaurent Pinchart #include <media/v4l2-device.h> 45c72a53ceSLaurent Pinchart #include <media/v4l2-dv-timings.h> 466fa88045SLaurent Pinchart #include <media/v4l2-of.h> 4754450f59SHans Verkuil 4854450f59SHans Verkuil static int debug; 4954450f59SHans Verkuil module_param(debug, int, 0644); 5054450f59SHans Verkuil MODULE_PARM_DESC(debug, "debug level (0-2)"); 5154450f59SHans Verkuil 5254450f59SHans Verkuil MODULE_DESCRIPTION("Analog Devices ADV7604 video decoder driver"); 5354450f59SHans Verkuil MODULE_AUTHOR("Hans Verkuil <hans.verkuil@cisco.com>"); 5454450f59SHans Verkuil MODULE_AUTHOR("Mats Randgaard <mats.randgaard@cisco.com>"); 5554450f59SHans Verkuil MODULE_LICENSE("GPL"); 5654450f59SHans Verkuil 5754450f59SHans Verkuil /* ADV7604 system clock frequency */ 58b44b2e06SPablo Anton #define ADV76XX_FSC (28636360) 5954450f59SHans Verkuil 60b44b2e06SPablo Anton #define ADV76XX_RGB_OUT (1 << 1) 61539b33b0SLaurent Pinchart 62b44b2e06SPablo Anton #define ADV76XX_OP_FORMAT_SEL_8BIT (0 << 0) 63539b33b0SLaurent Pinchart #define ADV7604_OP_FORMAT_SEL_10BIT (1 << 0) 64b44b2e06SPablo Anton #define ADV76XX_OP_FORMAT_SEL_12BIT (2 << 0) 65539b33b0SLaurent Pinchart 66b44b2e06SPablo Anton #define ADV76XX_OP_MODE_SEL_SDR_422 (0 << 5) 67539b33b0SLaurent Pinchart #define ADV7604_OP_MODE_SEL_DDR_422 (1 << 5) 68b44b2e06SPablo Anton #define ADV76XX_OP_MODE_SEL_SDR_444 (2 << 5) 69539b33b0SLaurent Pinchart #define ADV7604_OP_MODE_SEL_DDR_444 (3 << 5) 70b44b2e06SPablo Anton #define ADV76XX_OP_MODE_SEL_SDR_422_2X (4 << 5) 71539b33b0SLaurent Pinchart #define ADV7604_OP_MODE_SEL_ADI_CM (5 << 5) 72539b33b0SLaurent Pinchart 73b44b2e06SPablo Anton #define ADV76XX_OP_CH_SEL_GBR (0 << 5) 74b44b2e06SPablo Anton #define ADV76XX_OP_CH_SEL_GRB (1 << 5) 75b44b2e06SPablo Anton #define ADV76XX_OP_CH_SEL_BGR (2 << 5) 76b44b2e06SPablo Anton #define ADV76XX_OP_CH_SEL_RGB (3 << 5) 77b44b2e06SPablo Anton #define ADV76XX_OP_CH_SEL_BRG (4 << 5) 78b44b2e06SPablo Anton #define ADV76XX_OP_CH_SEL_RBG (5 << 5) 79539b33b0SLaurent Pinchart 80b44b2e06SPablo Anton #define ADV76XX_OP_SWAP_CB_CR (1 << 0) 81539b33b0SLaurent Pinchart 82b44b2e06SPablo Anton enum adv76xx_type { 83d42010a1SLars-Peter Clausen ADV7604, 84d42010a1SLars-Peter Clausen ADV7611, 858331d30bSWilliam Towle ADV7612, 86d42010a1SLars-Peter Clausen }; 87d42010a1SLars-Peter Clausen 88b44b2e06SPablo Anton struct adv76xx_reg_seq { 89d42010a1SLars-Peter Clausen unsigned int reg; 90d42010a1SLars-Peter Clausen u8 val; 91d42010a1SLars-Peter Clausen }; 92d42010a1SLars-Peter Clausen 93b44b2e06SPablo Anton struct adv76xx_format_info { 94f5fe58fdSBoris BREZILLON u32 code; 95539b33b0SLaurent Pinchart u8 op_ch_sel; 96539b33b0SLaurent Pinchart bool rgb_out; 97539b33b0SLaurent Pinchart bool swap_cb_cr; 98539b33b0SLaurent Pinchart u8 op_format_sel; 99539b33b0SLaurent Pinchart }; 100539b33b0SLaurent Pinchart 101516613c1SHans Verkuil struct adv76xx_cfg_read_infoframe { 102516613c1SHans Verkuil const char *desc; 103516613c1SHans Verkuil u8 present_mask; 104516613c1SHans Verkuil u8 head_addr; 105516613c1SHans Verkuil u8 payload_addr; 106516613c1SHans Verkuil }; 107516613c1SHans Verkuil 108b44b2e06SPablo Anton struct adv76xx_chip_info { 109b44b2e06SPablo Anton enum adv76xx_type type; 110d42010a1SLars-Peter Clausen 111d42010a1SLars-Peter Clausen bool has_afe; 112d42010a1SLars-Peter Clausen unsigned int max_port; 113d42010a1SLars-Peter Clausen unsigned int num_dv_ports; 114d42010a1SLars-Peter Clausen 115d42010a1SLars-Peter Clausen unsigned int edid_enable_reg; 116d42010a1SLars-Peter Clausen unsigned int edid_status_reg; 117d42010a1SLars-Peter Clausen unsigned int lcf_reg; 118d42010a1SLars-Peter Clausen 119d42010a1SLars-Peter Clausen unsigned int cable_det_mask; 120d42010a1SLars-Peter Clausen unsigned int tdms_lock_mask; 121d42010a1SLars-Peter Clausen unsigned int fmt_change_digital_mask; 12280f4944eSjean-michel.hautbois@vodalys.com unsigned int cp_csc; 123d42010a1SLars-Peter Clausen 124b44b2e06SPablo Anton const struct adv76xx_format_info *formats; 125539b33b0SLaurent Pinchart unsigned int nformats; 126539b33b0SLaurent Pinchart 127d42010a1SLars-Peter Clausen void (*set_termination)(struct v4l2_subdev *sd, bool enable); 128d42010a1SLars-Peter Clausen void (*setup_irqs)(struct v4l2_subdev *sd); 129d42010a1SLars-Peter Clausen unsigned int (*read_hdmi_pixelclock)(struct v4l2_subdev *sd); 130d42010a1SLars-Peter Clausen unsigned int (*read_cable_det)(struct v4l2_subdev *sd); 131d42010a1SLars-Peter Clausen 132d42010a1SLars-Peter Clausen /* 0 = AFE, 1 = HDMI */ 133b44b2e06SPablo Anton const struct adv76xx_reg_seq *recommended_settings[2]; 134d42010a1SLars-Peter Clausen unsigned int num_recommended_settings[2]; 135d42010a1SLars-Peter Clausen 136d42010a1SLars-Peter Clausen unsigned long page_mask; 1375380baafSjean-michel.hautbois@vodalys.com 1385380baafSjean-michel.hautbois@vodalys.com /* Masks for timings */ 1395380baafSjean-michel.hautbois@vodalys.com unsigned int linewidth_mask; 1405380baafSjean-michel.hautbois@vodalys.com unsigned int field0_height_mask; 1415380baafSjean-michel.hautbois@vodalys.com unsigned int field1_height_mask; 1425380baafSjean-michel.hautbois@vodalys.com unsigned int hfrontporch_mask; 1435380baafSjean-michel.hautbois@vodalys.com unsigned int hsync_mask; 1445380baafSjean-michel.hautbois@vodalys.com unsigned int hbackporch_mask; 1455380baafSjean-michel.hautbois@vodalys.com unsigned int field0_vfrontporch_mask; 1465380baafSjean-michel.hautbois@vodalys.com unsigned int field1_vfrontporch_mask; 1475380baafSjean-michel.hautbois@vodalys.com unsigned int field0_vsync_mask; 1485380baafSjean-michel.hautbois@vodalys.com unsigned int field1_vsync_mask; 1495380baafSjean-michel.hautbois@vodalys.com unsigned int field0_vbackporch_mask; 1505380baafSjean-michel.hautbois@vodalys.com unsigned int field1_vbackporch_mask; 151d42010a1SLars-Peter Clausen }; 152d42010a1SLars-Peter Clausen 15354450f59SHans Verkuil /* 15454450f59SHans Verkuil ********************************************************************** 15554450f59SHans Verkuil * 15654450f59SHans Verkuil * Arrays with configuration parameters for the ADV7604 15754450f59SHans Verkuil * 15854450f59SHans Verkuil ********************************************************************** 15954450f59SHans Verkuil */ 160c784b1e2SLaurent Pinchart 161b44b2e06SPablo Anton struct adv76xx_state { 162b44b2e06SPablo Anton const struct adv76xx_chip_info *info; 163b44b2e06SPablo Anton struct adv76xx_platform_data pdata; 164539b33b0SLaurent Pinchart 165e9d50e9eSLaurent Pinchart struct gpio_desc *hpd_gpio[4]; 166e9d50e9eSLaurent Pinchart 16754450f59SHans Verkuil struct v4l2_subdev sd; 168b44b2e06SPablo Anton struct media_pad pads[ADV76XX_PAD_MAX]; 169c784b1e2SLaurent Pinchart unsigned int source_pad; 170539b33b0SLaurent Pinchart 17154450f59SHans Verkuil struct v4l2_ctrl_handler hdl; 172539b33b0SLaurent Pinchart 173b44b2e06SPablo Anton enum adv76xx_pad selected_input; 174539b33b0SLaurent Pinchart 17554450f59SHans Verkuil struct v4l2_dv_timings timings; 176b44b2e06SPablo Anton const struct adv76xx_format_info *format; 177539b33b0SLaurent Pinchart 1784a31a93aSMats Randgaard struct { 17954450f59SHans Verkuil u8 edid[256]; 1804a31a93aSMats Randgaard u32 present; 1814a31a93aSMats Randgaard unsigned blocks; 1824a31a93aSMats Randgaard } edid; 183dd08beb9SMats Randgaard u16 spa_port_a[2]; 18454450f59SHans Verkuil struct v4l2_fract aspect_ratio; 18554450f59SHans Verkuil u32 rgb_quantization_range; 18654450f59SHans Verkuil struct workqueue_struct *work_queues; 18754450f59SHans Verkuil struct delayed_work delayed_work_enable_hotplug; 188cf9afb1dSHans Verkuil bool restart_stdi_once; 18954450f59SHans Verkuil 19054450f59SHans Verkuil /* i2c clients */ 191b44b2e06SPablo Anton struct i2c_client *i2c_clients[ADV76XX_PAGE_MAX]; 19254450f59SHans Verkuil 193f862f57dSPablo Anton /* Regmaps */ 194f862f57dSPablo Anton struct regmap *regmap[ADV76XX_PAGE_MAX]; 195f862f57dSPablo Anton 19654450f59SHans Verkuil /* controls */ 19754450f59SHans Verkuil struct v4l2_ctrl *detect_tx_5v_ctrl; 19854450f59SHans Verkuil struct v4l2_ctrl *analog_sampling_phase_ctrl; 19954450f59SHans Verkuil struct v4l2_ctrl *free_run_color_manual_ctrl; 20054450f59SHans Verkuil struct v4l2_ctrl *free_run_color_ctrl; 20154450f59SHans Verkuil struct v4l2_ctrl *rgb_quantization_range_ctrl; 20254450f59SHans Verkuil }; 20354450f59SHans Verkuil 204b44b2e06SPablo Anton static bool adv76xx_has_afe(struct adv76xx_state *state) 205d42010a1SLars-Peter Clausen { 206d42010a1SLars-Peter Clausen return state->info->has_afe; 207d42010a1SLars-Peter Clausen } 208d42010a1SLars-Peter Clausen 20954450f59SHans Verkuil /* Supported CEA and DMT timings */ 210b44b2e06SPablo Anton static const struct v4l2_dv_timings adv76xx_timings[] = { 21154450f59SHans Verkuil V4L2_DV_BT_CEA_720X480P59_94, 21254450f59SHans Verkuil V4L2_DV_BT_CEA_720X576P50, 21354450f59SHans Verkuil V4L2_DV_BT_CEA_1280X720P24, 21454450f59SHans Verkuil V4L2_DV_BT_CEA_1280X720P25, 21554450f59SHans Verkuil V4L2_DV_BT_CEA_1280X720P50, 21654450f59SHans Verkuil V4L2_DV_BT_CEA_1280X720P60, 21754450f59SHans Verkuil V4L2_DV_BT_CEA_1920X1080P24, 21854450f59SHans Verkuil V4L2_DV_BT_CEA_1920X1080P25, 21954450f59SHans Verkuil V4L2_DV_BT_CEA_1920X1080P30, 22054450f59SHans Verkuil V4L2_DV_BT_CEA_1920X1080P50, 22154450f59SHans Verkuil V4L2_DV_BT_CEA_1920X1080P60, 22254450f59SHans Verkuil 223ccbd5bc4SHans Verkuil /* sorted by DMT ID */ 22454450f59SHans Verkuil V4L2_DV_BT_DMT_640X350P85, 22554450f59SHans Verkuil V4L2_DV_BT_DMT_640X400P85, 22654450f59SHans Verkuil V4L2_DV_BT_DMT_720X400P85, 22754450f59SHans Verkuil V4L2_DV_BT_DMT_640X480P60, 22854450f59SHans Verkuil V4L2_DV_BT_DMT_640X480P72, 22954450f59SHans Verkuil V4L2_DV_BT_DMT_640X480P75, 23054450f59SHans Verkuil V4L2_DV_BT_DMT_640X480P85, 23154450f59SHans Verkuil V4L2_DV_BT_DMT_800X600P56, 23254450f59SHans Verkuil V4L2_DV_BT_DMT_800X600P60, 23354450f59SHans Verkuil V4L2_DV_BT_DMT_800X600P72, 23454450f59SHans Verkuil V4L2_DV_BT_DMT_800X600P75, 23554450f59SHans Verkuil V4L2_DV_BT_DMT_800X600P85, 23654450f59SHans Verkuil V4L2_DV_BT_DMT_848X480P60, 23754450f59SHans Verkuil V4L2_DV_BT_DMT_1024X768P60, 23854450f59SHans Verkuil V4L2_DV_BT_DMT_1024X768P70, 23954450f59SHans Verkuil V4L2_DV_BT_DMT_1024X768P75, 24054450f59SHans Verkuil V4L2_DV_BT_DMT_1024X768P85, 24154450f59SHans Verkuil V4L2_DV_BT_DMT_1152X864P75, 24254450f59SHans Verkuil V4L2_DV_BT_DMT_1280X768P60_RB, 24354450f59SHans Verkuil V4L2_DV_BT_DMT_1280X768P60, 24454450f59SHans Verkuil V4L2_DV_BT_DMT_1280X768P75, 24554450f59SHans Verkuil V4L2_DV_BT_DMT_1280X768P85, 24654450f59SHans Verkuil V4L2_DV_BT_DMT_1280X800P60_RB, 24754450f59SHans Verkuil V4L2_DV_BT_DMT_1280X800P60, 24854450f59SHans Verkuil V4L2_DV_BT_DMT_1280X800P75, 24954450f59SHans Verkuil V4L2_DV_BT_DMT_1280X800P85, 25054450f59SHans Verkuil V4L2_DV_BT_DMT_1280X960P60, 25154450f59SHans Verkuil V4L2_DV_BT_DMT_1280X960P85, 25254450f59SHans Verkuil V4L2_DV_BT_DMT_1280X1024P60, 25354450f59SHans Verkuil V4L2_DV_BT_DMT_1280X1024P75, 25454450f59SHans Verkuil V4L2_DV_BT_DMT_1280X1024P85, 25554450f59SHans Verkuil V4L2_DV_BT_DMT_1360X768P60, 25654450f59SHans Verkuil V4L2_DV_BT_DMT_1400X1050P60_RB, 25754450f59SHans Verkuil V4L2_DV_BT_DMT_1400X1050P60, 25854450f59SHans Verkuil V4L2_DV_BT_DMT_1400X1050P75, 25954450f59SHans Verkuil V4L2_DV_BT_DMT_1400X1050P85, 26054450f59SHans Verkuil V4L2_DV_BT_DMT_1440X900P60_RB, 26154450f59SHans Verkuil V4L2_DV_BT_DMT_1440X900P60, 26254450f59SHans Verkuil V4L2_DV_BT_DMT_1600X1200P60, 26354450f59SHans Verkuil V4L2_DV_BT_DMT_1680X1050P60_RB, 26454450f59SHans Verkuil V4L2_DV_BT_DMT_1680X1050P60, 26554450f59SHans Verkuil V4L2_DV_BT_DMT_1792X1344P60, 26654450f59SHans Verkuil V4L2_DV_BT_DMT_1856X1392P60, 26754450f59SHans Verkuil V4L2_DV_BT_DMT_1920X1200P60_RB, 268547ed542SMartin Bugge V4L2_DV_BT_DMT_1366X768P60_RB, 26954450f59SHans Verkuil V4L2_DV_BT_DMT_1366X768P60, 27054450f59SHans Verkuil V4L2_DV_BT_DMT_1920X1080P60, 27154450f59SHans Verkuil { }, 27254450f59SHans Verkuil }; 27354450f59SHans Verkuil 274b44b2e06SPablo Anton struct adv76xx_video_standards { 275ccbd5bc4SHans Verkuil struct v4l2_dv_timings timings; 276ccbd5bc4SHans Verkuil u8 vid_std; 277ccbd5bc4SHans Verkuil u8 v_freq; 278ccbd5bc4SHans Verkuil }; 279ccbd5bc4SHans Verkuil 280ccbd5bc4SHans Verkuil /* sorted by number of lines */ 281b44b2e06SPablo Anton static const struct adv76xx_video_standards adv7604_prim_mode_comp[] = { 282ccbd5bc4SHans Verkuil /* { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 }, TODO flickering */ 283ccbd5bc4SHans Verkuil { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 }, 284ccbd5bc4SHans Verkuil { V4L2_DV_BT_CEA_1280X720P50, 0x19, 0x01 }, 285ccbd5bc4SHans Verkuil { V4L2_DV_BT_CEA_1280X720P60, 0x19, 0x00 }, 286ccbd5bc4SHans Verkuil { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 }, 287ccbd5bc4SHans Verkuil { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 }, 288ccbd5bc4SHans Verkuil { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 }, 289ccbd5bc4SHans Verkuil { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 }, 290ccbd5bc4SHans Verkuil { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 }, 291ccbd5bc4SHans Verkuil /* TODO add 1920x1080P60_RB (CVT timing) */ 292ccbd5bc4SHans Verkuil { }, 293ccbd5bc4SHans Verkuil }; 294ccbd5bc4SHans Verkuil 295ccbd5bc4SHans Verkuil /* sorted by number of lines */ 296b44b2e06SPablo Anton static const struct adv76xx_video_standards adv7604_prim_mode_gr[] = { 297ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 }, 298ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 }, 299ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 }, 300ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 }, 301ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 }, 302ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 }, 303ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 }, 304ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 }, 305ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 }, 306ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 }, 307ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 }, 308ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 }, 309ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 }, 310ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 }, 311ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 }, 312ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_1360X768P60, 0x12, 0x00 }, 313ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_1366X768P60, 0x13, 0x00 }, 314ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_1400X1050P60, 0x14, 0x00 }, 315ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_1400X1050P75, 0x15, 0x00 }, 316ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_1600X1200P60, 0x16, 0x00 }, /* TODO not tested */ 317ccbd5bc4SHans Verkuil /* TODO add 1600X1200P60_RB (not a DMT timing) */ 318ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_1680X1050P60, 0x18, 0x00 }, 319ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_1920X1200P60_RB, 0x19, 0x00 }, /* TODO not tested */ 320ccbd5bc4SHans Verkuil { }, 321ccbd5bc4SHans Verkuil }; 322ccbd5bc4SHans Verkuil 323ccbd5bc4SHans Verkuil /* sorted by number of lines */ 324b44b2e06SPablo Anton static const struct adv76xx_video_standards adv76xx_prim_mode_hdmi_comp[] = { 325ccbd5bc4SHans Verkuil { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 }, 326ccbd5bc4SHans Verkuil { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 }, 327ccbd5bc4SHans Verkuil { V4L2_DV_BT_CEA_1280X720P50, 0x13, 0x01 }, 328ccbd5bc4SHans Verkuil { V4L2_DV_BT_CEA_1280X720P60, 0x13, 0x00 }, 329ccbd5bc4SHans Verkuil { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 }, 330ccbd5bc4SHans Verkuil { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 }, 331ccbd5bc4SHans Verkuil { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 }, 332ccbd5bc4SHans Verkuil { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 }, 333ccbd5bc4SHans Verkuil { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 }, 334ccbd5bc4SHans Verkuil { }, 335ccbd5bc4SHans Verkuil }; 336ccbd5bc4SHans Verkuil 337ccbd5bc4SHans Verkuil /* sorted by number of lines */ 338b44b2e06SPablo Anton static const struct adv76xx_video_standards adv76xx_prim_mode_hdmi_gr[] = { 339ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 }, 340ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 }, 341ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 }, 342ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 }, 343ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 }, 344ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 }, 345ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 }, 346ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 }, 347ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 }, 348ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 }, 349ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 }, 350ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 }, 351ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 }, 352ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 }, 353ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 }, 354ccbd5bc4SHans Verkuil { }, 355ccbd5bc4SHans Verkuil }; 356ccbd5bc4SHans Verkuil 35748519838SHans Verkuil static const struct v4l2_event adv76xx_ev_fmt = { 35848519838SHans Verkuil .type = V4L2_EVENT_SOURCE_CHANGE, 35948519838SHans Verkuil .u.src_change.changes = V4L2_EVENT_SRC_CH_RESOLUTION, 36048519838SHans Verkuil }; 36148519838SHans Verkuil 36254450f59SHans Verkuil /* ----------------------------------------------------------------------- */ 36354450f59SHans Verkuil 364b44b2e06SPablo Anton static inline struct adv76xx_state *to_state(struct v4l2_subdev *sd) 36554450f59SHans Verkuil { 366b44b2e06SPablo Anton return container_of(sd, struct adv76xx_state, sd); 36754450f59SHans Verkuil } 36854450f59SHans Verkuil 36954450f59SHans Verkuil static inline unsigned htotal(const struct v4l2_bt_timings *t) 37054450f59SHans Verkuil { 371eacf8f9aSHans Verkuil return V4L2_DV_BT_FRAME_WIDTH(t); 37254450f59SHans Verkuil } 37354450f59SHans Verkuil 37454450f59SHans Verkuil static inline unsigned vtotal(const struct v4l2_bt_timings *t) 37554450f59SHans Verkuil { 376eacf8f9aSHans Verkuil return V4L2_DV_BT_FRAME_HEIGHT(t); 37754450f59SHans Verkuil } 37854450f59SHans Verkuil 37954450f59SHans Verkuil /* ----------------------------------------------------------------------- */ 38054450f59SHans Verkuil 381f862f57dSPablo Anton static int adv76xx_read_check(struct adv76xx_state *state, 382f862f57dSPablo Anton int client_page, u8 reg) 38354450f59SHans Verkuil { 384f862f57dSPablo Anton struct i2c_client *client = state->i2c_clients[client_page]; 38554450f59SHans Verkuil int err; 386f862f57dSPablo Anton unsigned int val; 38754450f59SHans Verkuil 388f862f57dSPablo Anton err = regmap_read(state->regmap[client_page], reg, &val); 389f862f57dSPablo Anton 390f862f57dSPablo Anton if (err) { 391f862f57dSPablo Anton v4l_err(client, "error reading %02x, %02x\n", 392f862f57dSPablo Anton client->addr, reg); 39354450f59SHans Verkuil return err; 39454450f59SHans Verkuil } 395f862f57dSPablo Anton return val; 396f862f57dSPablo Anton } 39754450f59SHans Verkuil 398f862f57dSPablo Anton /* adv76xx_write_block(): Write raw data with a maximum of I2C_SMBUS_BLOCK_MAX 399f862f57dSPablo Anton * size to one or more registers. 400f862f57dSPablo Anton * 401f862f57dSPablo Anton * A value of zero will be returned on success, a negative errno will 402f862f57dSPablo Anton * be returned in error cases. 403f862f57dSPablo Anton */ 404f862f57dSPablo Anton static int adv76xx_write_block(struct adv76xx_state *state, int client_page, 405f862f57dSPablo Anton unsigned int init_reg, const void *val, 406f862f57dSPablo Anton size_t val_len) 40754450f59SHans Verkuil { 408f862f57dSPablo Anton struct regmap *regmap = state->regmap[client_page]; 40954450f59SHans Verkuil 410f862f57dSPablo Anton if (val_len > I2C_SMBUS_BLOCK_MAX) 411f862f57dSPablo Anton val_len = I2C_SMBUS_BLOCK_MAX; 412f862f57dSPablo Anton 413f862f57dSPablo Anton return regmap_raw_write(regmap, init_reg, val, val_len); 41454450f59SHans Verkuil } 41554450f59SHans Verkuil 41654450f59SHans Verkuil /* ----------------------------------------------------------------------- */ 41754450f59SHans Verkuil 41854450f59SHans Verkuil static inline int io_read(struct v4l2_subdev *sd, u8 reg) 41954450f59SHans Verkuil { 420b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 42154450f59SHans Verkuil 422f862f57dSPablo Anton return adv76xx_read_check(state, ADV76XX_PAGE_IO, reg); 42354450f59SHans Verkuil } 42454450f59SHans Verkuil 42554450f59SHans Verkuil static inline int io_write(struct v4l2_subdev *sd, u8 reg, u8 val) 42654450f59SHans Verkuil { 427b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 42854450f59SHans Verkuil 429f862f57dSPablo Anton return regmap_write(state->regmap[ADV76XX_PAGE_IO], reg, val); 43054450f59SHans Verkuil } 43154450f59SHans Verkuil 43222d97e56SLaurent Pinchart static inline int io_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) 43354450f59SHans Verkuil { 43422d97e56SLaurent Pinchart return io_write(sd, reg, (io_read(sd, reg) & ~mask) | val); 43554450f59SHans Verkuil } 43654450f59SHans Verkuil 43754450f59SHans Verkuil static inline int avlink_read(struct v4l2_subdev *sd, u8 reg) 43854450f59SHans Verkuil { 439b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 44054450f59SHans Verkuil 441f862f57dSPablo Anton return adv76xx_read_check(state, ADV7604_PAGE_AVLINK, reg); 44254450f59SHans Verkuil } 44354450f59SHans Verkuil 44454450f59SHans Verkuil static inline int avlink_write(struct v4l2_subdev *sd, u8 reg, u8 val) 44554450f59SHans Verkuil { 446b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 44754450f59SHans Verkuil 448f862f57dSPablo Anton return regmap_write(state->regmap[ADV7604_PAGE_AVLINK], reg, val); 44954450f59SHans Verkuil } 45054450f59SHans Verkuil 45154450f59SHans Verkuil static inline int cec_read(struct v4l2_subdev *sd, u8 reg) 45254450f59SHans Verkuil { 453b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 45454450f59SHans Verkuil 455f862f57dSPablo Anton return adv76xx_read_check(state, ADV76XX_PAGE_CEC, reg); 45654450f59SHans Verkuil } 45754450f59SHans Verkuil 45854450f59SHans Verkuil static inline int cec_write(struct v4l2_subdev *sd, u8 reg, u8 val) 45954450f59SHans Verkuil { 460b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 46154450f59SHans Verkuil 462f862f57dSPablo Anton return regmap_write(state->regmap[ADV76XX_PAGE_CEC], reg, val); 46354450f59SHans Verkuil } 46454450f59SHans Verkuil 46554450f59SHans Verkuil static inline int infoframe_read(struct v4l2_subdev *sd, u8 reg) 46654450f59SHans Verkuil { 467b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 46854450f59SHans Verkuil 469f862f57dSPablo Anton return adv76xx_read_check(state, ADV76XX_PAGE_INFOFRAME, reg); 47054450f59SHans Verkuil } 47154450f59SHans Verkuil 47254450f59SHans Verkuil static inline int infoframe_write(struct v4l2_subdev *sd, u8 reg, u8 val) 47354450f59SHans Verkuil { 474b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 47554450f59SHans Verkuil 476f862f57dSPablo Anton return regmap_write(state->regmap[ADV76XX_PAGE_INFOFRAME], reg, val); 47754450f59SHans Verkuil } 47854450f59SHans Verkuil 47954450f59SHans Verkuil static inline int afe_read(struct v4l2_subdev *sd, u8 reg) 48054450f59SHans Verkuil { 481b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 48254450f59SHans Verkuil 483f862f57dSPablo Anton return adv76xx_read_check(state, ADV76XX_PAGE_AFE, reg); 48454450f59SHans Verkuil } 48554450f59SHans Verkuil 48654450f59SHans Verkuil static inline int afe_write(struct v4l2_subdev *sd, u8 reg, u8 val) 48754450f59SHans Verkuil { 488b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 48954450f59SHans Verkuil 490f862f57dSPablo Anton return regmap_write(state->regmap[ADV76XX_PAGE_AFE], reg, val); 49154450f59SHans Verkuil } 49254450f59SHans Verkuil 49354450f59SHans Verkuil static inline int rep_read(struct v4l2_subdev *sd, u8 reg) 49454450f59SHans Verkuil { 495b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 49654450f59SHans Verkuil 497f862f57dSPablo Anton return adv76xx_read_check(state, ADV76XX_PAGE_REP, reg); 49854450f59SHans Verkuil } 49954450f59SHans Verkuil 50054450f59SHans Verkuil static inline int rep_write(struct v4l2_subdev *sd, u8 reg, u8 val) 50154450f59SHans Verkuil { 502b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 50354450f59SHans Verkuil 504f862f57dSPablo Anton return regmap_write(state->regmap[ADV76XX_PAGE_REP], reg, val); 50554450f59SHans Verkuil } 50654450f59SHans Verkuil 50722d97e56SLaurent Pinchart static inline int rep_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) 50854450f59SHans Verkuil { 50922d97e56SLaurent Pinchart return rep_write(sd, reg, (rep_read(sd, reg) & ~mask) | val); 51054450f59SHans Verkuil } 51154450f59SHans Verkuil 51254450f59SHans Verkuil static inline int edid_read(struct v4l2_subdev *sd, u8 reg) 51354450f59SHans Verkuil { 514b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 51554450f59SHans Verkuil 516f862f57dSPablo Anton return adv76xx_read_check(state, ADV76XX_PAGE_EDID, reg); 51754450f59SHans Verkuil } 51854450f59SHans Verkuil 51954450f59SHans Verkuil static inline int edid_write(struct v4l2_subdev *sd, u8 reg, u8 val) 52054450f59SHans Verkuil { 521b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 52254450f59SHans Verkuil 523f862f57dSPablo Anton return regmap_write(state->regmap[ADV76XX_PAGE_EDID], reg, val); 52454450f59SHans Verkuil } 52554450f59SHans Verkuil 526dd08beb9SMats Randgaard static inline int edid_write_block(struct v4l2_subdev *sd, 527f862f57dSPablo Anton unsigned int total_len, const u8 *val) 528dd08beb9SMats Randgaard { 529b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 530dd08beb9SMats Randgaard int err = 0; 531f862f57dSPablo Anton int i = 0; 532f862f57dSPablo Anton int len = 0; 533dd08beb9SMats Randgaard 534f862f57dSPablo Anton v4l2_dbg(2, debug, sd, "%s: write EDID block (%d byte)\n", 535f862f57dSPablo Anton __func__, total_len); 536dd08beb9SMats Randgaard 537f862f57dSPablo Anton while (!err && i < total_len) { 538f862f57dSPablo Anton len = (total_len - i) > I2C_SMBUS_BLOCK_MAX ? 539f862f57dSPablo Anton I2C_SMBUS_BLOCK_MAX : 540f862f57dSPablo Anton (total_len - i); 541f862f57dSPablo Anton 542f862f57dSPablo Anton err = adv76xx_write_block(state, ADV76XX_PAGE_EDID, 543f862f57dSPablo Anton i, val + i, len); 544f862f57dSPablo Anton i += len; 545f862f57dSPablo Anton } 546f862f57dSPablo Anton 547dd08beb9SMats Randgaard return err; 548dd08beb9SMats Randgaard } 549dd08beb9SMats Randgaard 550b44b2e06SPablo Anton static void adv76xx_set_hpd(struct adv76xx_state *state, unsigned int hpd) 551e9d50e9eSLaurent Pinchart { 552e9d50e9eSLaurent Pinchart unsigned int i; 553e9d50e9eSLaurent Pinchart 554269bd132SUwe Kleine-König for (i = 0; i < state->info->num_dv_ports; ++i) 555e9d50e9eSLaurent Pinchart gpiod_set_value_cansleep(state->hpd_gpio[i], hpd & BIT(i)); 556e9d50e9eSLaurent Pinchart 557b44b2e06SPablo Anton v4l2_subdev_notify(&state->sd, ADV76XX_HOTPLUG, &hpd); 558e9d50e9eSLaurent Pinchart } 559e9d50e9eSLaurent Pinchart 560b44b2e06SPablo Anton static void adv76xx_delayed_work_enable_hotplug(struct work_struct *work) 56154450f59SHans Verkuil { 56254450f59SHans Verkuil struct delayed_work *dwork = to_delayed_work(work); 563b44b2e06SPablo Anton struct adv76xx_state *state = container_of(dwork, struct adv76xx_state, 56454450f59SHans Verkuil delayed_work_enable_hotplug); 56554450f59SHans Verkuil struct v4l2_subdev *sd = &state->sd; 56654450f59SHans Verkuil 56754450f59SHans Verkuil v4l2_dbg(2, debug, sd, "%s: enable hotplug\n", __func__); 56854450f59SHans Verkuil 569b44b2e06SPablo Anton adv76xx_set_hpd(state, state->edid.present); 57054450f59SHans Verkuil } 57154450f59SHans Verkuil 57254450f59SHans Verkuil static inline int hdmi_read(struct v4l2_subdev *sd, u8 reg) 57354450f59SHans Verkuil { 574b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 57554450f59SHans Verkuil 576f862f57dSPablo Anton return adv76xx_read_check(state, ADV76XX_PAGE_HDMI, reg); 57754450f59SHans Verkuil } 57854450f59SHans Verkuil 57951182a94SLaurent Pinchart static u16 hdmi_read16(struct v4l2_subdev *sd, u8 reg, u16 mask) 58051182a94SLaurent Pinchart { 58151182a94SLaurent Pinchart return ((hdmi_read(sd, reg) << 8) | hdmi_read(sd, reg + 1)) & mask; 58251182a94SLaurent Pinchart } 58351182a94SLaurent Pinchart 58454450f59SHans Verkuil static inline int hdmi_write(struct v4l2_subdev *sd, u8 reg, u8 val) 58554450f59SHans Verkuil { 586b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 58754450f59SHans Verkuil 588f862f57dSPablo Anton return regmap_write(state->regmap[ADV76XX_PAGE_HDMI], reg, val); 58954450f59SHans Verkuil } 59054450f59SHans Verkuil 59122d97e56SLaurent Pinchart static inline int hdmi_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) 5924a31a93aSMats Randgaard { 59322d97e56SLaurent Pinchart return hdmi_write(sd, reg, (hdmi_read(sd, reg) & ~mask) | val); 5944a31a93aSMats Randgaard } 5954a31a93aSMats Randgaard 59654450f59SHans Verkuil static inline int test_write(struct v4l2_subdev *sd, u8 reg, u8 val) 59754450f59SHans Verkuil { 598b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 59954450f59SHans Verkuil 600f862f57dSPablo Anton return regmap_write(state->regmap[ADV76XX_PAGE_TEST], reg, val); 60154450f59SHans Verkuil } 60254450f59SHans Verkuil 60354450f59SHans Verkuil static inline int cp_read(struct v4l2_subdev *sd, u8 reg) 60454450f59SHans Verkuil { 605b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 60654450f59SHans Verkuil 607f862f57dSPablo Anton return adv76xx_read_check(state, ADV76XX_PAGE_CP, reg); 60854450f59SHans Verkuil } 60954450f59SHans Verkuil 61051182a94SLaurent Pinchart static u16 cp_read16(struct v4l2_subdev *sd, u8 reg, u16 mask) 61151182a94SLaurent Pinchart { 61251182a94SLaurent Pinchart return ((cp_read(sd, reg) << 8) | cp_read(sd, reg + 1)) & mask; 61351182a94SLaurent Pinchart } 61451182a94SLaurent Pinchart 61554450f59SHans Verkuil static inline int cp_write(struct v4l2_subdev *sd, u8 reg, u8 val) 61654450f59SHans Verkuil { 617b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 61854450f59SHans Verkuil 619f862f57dSPablo Anton return regmap_write(state->regmap[ADV76XX_PAGE_CP], reg, val); 62054450f59SHans Verkuil } 62154450f59SHans Verkuil 62222d97e56SLaurent Pinchart static inline int cp_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) 62354450f59SHans Verkuil { 62422d97e56SLaurent Pinchart return cp_write(sd, reg, (cp_read(sd, reg) & ~mask) | val); 62554450f59SHans Verkuil } 62654450f59SHans Verkuil 62754450f59SHans Verkuil static inline int vdp_read(struct v4l2_subdev *sd, u8 reg) 62854450f59SHans Verkuil { 629b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 63054450f59SHans Verkuil 631f862f57dSPablo Anton return adv76xx_read_check(state, ADV7604_PAGE_VDP, reg); 63254450f59SHans Verkuil } 63354450f59SHans Verkuil 63454450f59SHans Verkuil static inline int vdp_write(struct v4l2_subdev *sd, u8 reg, u8 val) 63554450f59SHans Verkuil { 636b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 63754450f59SHans Verkuil 638f862f57dSPablo Anton return regmap_write(state->regmap[ADV7604_PAGE_VDP], reg, val); 63954450f59SHans Verkuil } 64054450f59SHans Verkuil 641b44b2e06SPablo Anton #define ADV76XX_REG(page, offset) (((page) << 8) | (offset)) 642b44b2e06SPablo Anton #define ADV76XX_REG_SEQ_TERM 0xffff 643d42010a1SLars-Peter Clausen 644d42010a1SLars-Peter Clausen #ifdef CONFIG_VIDEO_ADV_DEBUG 645b44b2e06SPablo Anton static int adv76xx_read_reg(struct v4l2_subdev *sd, unsigned int reg) 646d42010a1SLars-Peter Clausen { 647b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 648d42010a1SLars-Peter Clausen unsigned int page = reg >> 8; 649f862f57dSPablo Anton unsigned int val; 650f862f57dSPablo Anton int err; 651d42010a1SLars-Peter Clausen 652d42010a1SLars-Peter Clausen if (!(BIT(page) & state->info->page_mask)) 653d42010a1SLars-Peter Clausen return -EINVAL; 654d42010a1SLars-Peter Clausen 655d42010a1SLars-Peter Clausen reg &= 0xff; 656f862f57dSPablo Anton err = regmap_read(state->regmap[page], reg, &val); 657d42010a1SLars-Peter Clausen 658f862f57dSPablo Anton return err ? err : val; 659d42010a1SLars-Peter Clausen } 660d42010a1SLars-Peter Clausen #endif 661d42010a1SLars-Peter Clausen 662b44b2e06SPablo Anton static int adv76xx_write_reg(struct v4l2_subdev *sd, unsigned int reg, u8 val) 663d42010a1SLars-Peter Clausen { 664b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 665d42010a1SLars-Peter Clausen unsigned int page = reg >> 8; 666d42010a1SLars-Peter Clausen 667d42010a1SLars-Peter Clausen if (!(BIT(page) & state->info->page_mask)) 668d42010a1SLars-Peter Clausen return -EINVAL; 669d42010a1SLars-Peter Clausen 670d42010a1SLars-Peter Clausen reg &= 0xff; 671d42010a1SLars-Peter Clausen 672f862f57dSPablo Anton return regmap_write(state->regmap[page], reg, val); 673d42010a1SLars-Peter Clausen } 674d42010a1SLars-Peter Clausen 675b44b2e06SPablo Anton static void adv76xx_write_reg_seq(struct v4l2_subdev *sd, 676b44b2e06SPablo Anton const struct adv76xx_reg_seq *reg_seq) 677d42010a1SLars-Peter Clausen { 678d42010a1SLars-Peter Clausen unsigned int i; 679d42010a1SLars-Peter Clausen 680b44b2e06SPablo Anton for (i = 0; reg_seq[i].reg != ADV76XX_REG_SEQ_TERM; i++) 681b44b2e06SPablo Anton adv76xx_write_reg(sd, reg_seq[i].reg, reg_seq[i].val); 682d42010a1SLars-Peter Clausen } 683d42010a1SLars-Peter Clausen 684539b33b0SLaurent Pinchart /* ----------------------------------------------------------------------------- 685539b33b0SLaurent Pinchart * Format helpers 686539b33b0SLaurent Pinchart */ 687539b33b0SLaurent Pinchart 688b44b2e06SPablo Anton static const struct adv76xx_format_info adv7604_formats[] = { 689b44b2e06SPablo Anton { MEDIA_BUS_FMT_RGB888_1X24, ADV76XX_OP_CH_SEL_RGB, true, false, 690b44b2e06SPablo Anton ADV76XX_OP_MODE_SEL_SDR_444 | ADV76XX_OP_FORMAT_SEL_8BIT }, 691b44b2e06SPablo Anton { MEDIA_BUS_FMT_YUYV8_2X8, ADV76XX_OP_CH_SEL_RGB, false, false, 692b44b2e06SPablo Anton ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT }, 693b44b2e06SPablo Anton { MEDIA_BUS_FMT_YVYU8_2X8, ADV76XX_OP_CH_SEL_RGB, false, true, 694b44b2e06SPablo Anton ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT }, 695b44b2e06SPablo Anton { MEDIA_BUS_FMT_YUYV10_2X10, ADV76XX_OP_CH_SEL_RGB, false, false, 696b44b2e06SPablo Anton ADV76XX_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_10BIT }, 697b44b2e06SPablo Anton { MEDIA_BUS_FMT_YVYU10_2X10, ADV76XX_OP_CH_SEL_RGB, false, true, 698b44b2e06SPablo Anton ADV76XX_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_10BIT }, 699b44b2e06SPablo Anton { MEDIA_BUS_FMT_YUYV12_2X12, ADV76XX_OP_CH_SEL_RGB, false, false, 700b44b2e06SPablo Anton ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_12BIT }, 701b44b2e06SPablo Anton { MEDIA_BUS_FMT_YVYU12_2X12, ADV76XX_OP_CH_SEL_RGB, false, true, 702b44b2e06SPablo Anton ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_12BIT }, 703b44b2e06SPablo Anton { MEDIA_BUS_FMT_UYVY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, false, 704b44b2e06SPablo Anton ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT }, 705b44b2e06SPablo Anton { MEDIA_BUS_FMT_VYUY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, true, 706b44b2e06SPablo Anton ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT }, 707b44b2e06SPablo Anton { MEDIA_BUS_FMT_YUYV8_1X16, ADV76XX_OP_CH_SEL_RGB, false, false, 708b44b2e06SPablo Anton ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT }, 709b44b2e06SPablo Anton { MEDIA_BUS_FMT_YVYU8_1X16, ADV76XX_OP_CH_SEL_RGB, false, true, 710b44b2e06SPablo Anton ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT }, 711b44b2e06SPablo Anton { MEDIA_BUS_FMT_UYVY10_1X20, ADV76XX_OP_CH_SEL_RBG, false, false, 712b44b2e06SPablo Anton ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT }, 713b44b2e06SPablo Anton { MEDIA_BUS_FMT_VYUY10_1X20, ADV76XX_OP_CH_SEL_RBG, false, true, 714b44b2e06SPablo Anton ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT }, 715b44b2e06SPablo Anton { MEDIA_BUS_FMT_YUYV10_1X20, ADV76XX_OP_CH_SEL_RGB, false, false, 716b44b2e06SPablo Anton ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT }, 717b44b2e06SPablo Anton { MEDIA_BUS_FMT_YVYU10_1X20, ADV76XX_OP_CH_SEL_RGB, false, true, 718b44b2e06SPablo Anton ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT }, 719b44b2e06SPablo Anton { MEDIA_BUS_FMT_UYVY12_1X24, ADV76XX_OP_CH_SEL_RBG, false, false, 720b44b2e06SPablo Anton ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT }, 721b44b2e06SPablo Anton { MEDIA_BUS_FMT_VYUY12_1X24, ADV76XX_OP_CH_SEL_RBG, false, true, 722b44b2e06SPablo Anton ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT }, 723b44b2e06SPablo Anton { MEDIA_BUS_FMT_YUYV12_1X24, ADV76XX_OP_CH_SEL_RGB, false, false, 724b44b2e06SPablo Anton ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT }, 725b44b2e06SPablo Anton { MEDIA_BUS_FMT_YVYU12_1X24, ADV76XX_OP_CH_SEL_RGB, false, true, 726b44b2e06SPablo Anton ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT }, 727539b33b0SLaurent Pinchart }; 728539b33b0SLaurent Pinchart 729b44b2e06SPablo Anton static const struct adv76xx_format_info adv7611_formats[] = { 730b44b2e06SPablo Anton { MEDIA_BUS_FMT_RGB888_1X24, ADV76XX_OP_CH_SEL_RGB, true, false, 731b44b2e06SPablo Anton ADV76XX_OP_MODE_SEL_SDR_444 | ADV76XX_OP_FORMAT_SEL_8BIT }, 732b44b2e06SPablo Anton { MEDIA_BUS_FMT_YUYV8_2X8, ADV76XX_OP_CH_SEL_RGB, false, false, 733b44b2e06SPablo Anton ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT }, 734b44b2e06SPablo Anton { MEDIA_BUS_FMT_YVYU8_2X8, ADV76XX_OP_CH_SEL_RGB, false, true, 735b44b2e06SPablo Anton ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT }, 736b44b2e06SPablo Anton { MEDIA_BUS_FMT_YUYV12_2X12, ADV76XX_OP_CH_SEL_RGB, false, false, 737b44b2e06SPablo Anton ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_12BIT }, 738b44b2e06SPablo Anton { MEDIA_BUS_FMT_YVYU12_2X12, ADV76XX_OP_CH_SEL_RGB, false, true, 739b44b2e06SPablo Anton ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_12BIT }, 740b44b2e06SPablo Anton { MEDIA_BUS_FMT_UYVY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, false, 741b44b2e06SPablo Anton ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT }, 742b44b2e06SPablo Anton { MEDIA_BUS_FMT_VYUY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, true, 743b44b2e06SPablo Anton ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT }, 744b44b2e06SPablo Anton { MEDIA_BUS_FMT_YUYV8_1X16, ADV76XX_OP_CH_SEL_RGB, false, false, 745b44b2e06SPablo Anton ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT }, 746b44b2e06SPablo Anton { MEDIA_BUS_FMT_YVYU8_1X16, ADV76XX_OP_CH_SEL_RGB, false, true, 747b44b2e06SPablo Anton ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT }, 748b44b2e06SPablo Anton { MEDIA_BUS_FMT_UYVY12_1X24, ADV76XX_OP_CH_SEL_RBG, false, false, 749b44b2e06SPablo Anton ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT }, 750b44b2e06SPablo Anton { MEDIA_BUS_FMT_VYUY12_1X24, ADV76XX_OP_CH_SEL_RBG, false, true, 751b44b2e06SPablo Anton ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT }, 752b44b2e06SPablo Anton { MEDIA_BUS_FMT_YUYV12_1X24, ADV76XX_OP_CH_SEL_RGB, false, false, 753b44b2e06SPablo Anton ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT }, 754b44b2e06SPablo Anton { MEDIA_BUS_FMT_YVYU12_1X24, ADV76XX_OP_CH_SEL_RGB, false, true, 755b44b2e06SPablo Anton ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT }, 756539b33b0SLaurent Pinchart }; 757539b33b0SLaurent Pinchart 7588331d30bSWilliam Towle static const struct adv76xx_format_info adv7612_formats[] = { 7598331d30bSWilliam Towle { MEDIA_BUS_FMT_RGB888_1X24, ADV76XX_OP_CH_SEL_RGB, true, false, 7608331d30bSWilliam Towle ADV76XX_OP_MODE_SEL_SDR_444 | ADV76XX_OP_FORMAT_SEL_8BIT }, 7618331d30bSWilliam Towle { MEDIA_BUS_FMT_YUYV8_2X8, ADV76XX_OP_CH_SEL_RGB, false, false, 7628331d30bSWilliam Towle ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT }, 7638331d30bSWilliam Towle { MEDIA_BUS_FMT_YVYU8_2X8, ADV76XX_OP_CH_SEL_RGB, false, true, 7648331d30bSWilliam Towle ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT }, 7658331d30bSWilliam Towle { MEDIA_BUS_FMT_UYVY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, false, 7668331d30bSWilliam Towle ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT }, 7678331d30bSWilliam Towle { MEDIA_BUS_FMT_VYUY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, true, 7688331d30bSWilliam Towle ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT }, 7698331d30bSWilliam Towle { MEDIA_BUS_FMT_YUYV8_1X16, ADV76XX_OP_CH_SEL_RGB, false, false, 7708331d30bSWilliam Towle ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT }, 7718331d30bSWilliam Towle { MEDIA_BUS_FMT_YVYU8_1X16, ADV76XX_OP_CH_SEL_RGB, false, true, 7728331d30bSWilliam Towle ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT }, 7738331d30bSWilliam Towle }; 7748331d30bSWilliam Towle 775b44b2e06SPablo Anton static const struct adv76xx_format_info * 776b44b2e06SPablo Anton adv76xx_format_info(struct adv76xx_state *state, u32 code) 777539b33b0SLaurent Pinchart { 778539b33b0SLaurent Pinchart unsigned int i; 779539b33b0SLaurent Pinchart 780539b33b0SLaurent Pinchart for (i = 0; i < state->info->nformats; ++i) { 781539b33b0SLaurent Pinchart if (state->info->formats[i].code == code) 782539b33b0SLaurent Pinchart return &state->info->formats[i]; 783539b33b0SLaurent Pinchart } 784539b33b0SLaurent Pinchart 785539b33b0SLaurent Pinchart return NULL; 786539b33b0SLaurent Pinchart } 787539b33b0SLaurent Pinchart 78854450f59SHans Verkuil /* ----------------------------------------------------------------------- */ 78954450f59SHans Verkuil 7904a31a93aSMats Randgaard static inline bool is_analog_input(struct v4l2_subdev *sd) 7914a31a93aSMats Randgaard { 792b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 7934a31a93aSMats Randgaard 794c784b1e2SLaurent Pinchart return state->selected_input == ADV7604_PAD_VGA_RGB || 795c784b1e2SLaurent Pinchart state->selected_input == ADV7604_PAD_VGA_COMP; 7964a31a93aSMats Randgaard } 7974a31a93aSMats Randgaard 7984a31a93aSMats Randgaard static inline bool is_digital_input(struct v4l2_subdev *sd) 7994a31a93aSMats Randgaard { 800b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 8014a31a93aSMats Randgaard 802b44b2e06SPablo Anton return state->selected_input == ADV76XX_PAD_HDMI_PORT_A || 803c784b1e2SLaurent Pinchart state->selected_input == ADV7604_PAD_HDMI_PORT_B || 804c784b1e2SLaurent Pinchart state->selected_input == ADV7604_PAD_HDMI_PORT_C || 805c784b1e2SLaurent Pinchart state->selected_input == ADV7604_PAD_HDMI_PORT_D; 8064a31a93aSMats Randgaard } 8074a31a93aSMats Randgaard 8084a31a93aSMats Randgaard /* ----------------------------------------------------------------------- */ 8094a31a93aSMats Randgaard 81054450f59SHans Verkuil #ifdef CONFIG_VIDEO_ADV_DEBUG 811b44b2e06SPablo Anton static void adv76xx_inv_register(struct v4l2_subdev *sd) 81254450f59SHans Verkuil { 81354450f59SHans Verkuil v4l2_info(sd, "0x000-0x0ff: IO Map\n"); 81454450f59SHans Verkuil v4l2_info(sd, "0x100-0x1ff: AVLink Map\n"); 81554450f59SHans Verkuil v4l2_info(sd, "0x200-0x2ff: CEC Map\n"); 81654450f59SHans Verkuil v4l2_info(sd, "0x300-0x3ff: InfoFrame Map\n"); 81754450f59SHans Verkuil v4l2_info(sd, "0x400-0x4ff: ESDP Map\n"); 81854450f59SHans Verkuil v4l2_info(sd, "0x500-0x5ff: DPP Map\n"); 81954450f59SHans Verkuil v4l2_info(sd, "0x600-0x6ff: AFE Map\n"); 82054450f59SHans Verkuil v4l2_info(sd, "0x700-0x7ff: Repeater Map\n"); 82154450f59SHans Verkuil v4l2_info(sd, "0x800-0x8ff: EDID Map\n"); 82254450f59SHans Verkuil v4l2_info(sd, "0x900-0x9ff: HDMI Map\n"); 82354450f59SHans Verkuil v4l2_info(sd, "0xa00-0xaff: Test Map\n"); 82454450f59SHans Verkuil v4l2_info(sd, "0xb00-0xbff: CP Map\n"); 82554450f59SHans Verkuil v4l2_info(sd, "0xc00-0xcff: VDP Map\n"); 82654450f59SHans Verkuil } 82754450f59SHans Verkuil 828b44b2e06SPablo Anton static int adv76xx_g_register(struct v4l2_subdev *sd, 82954450f59SHans Verkuil struct v4l2_dbg_register *reg) 83054450f59SHans Verkuil { 831d42010a1SLars-Peter Clausen int ret; 832d42010a1SLars-Peter Clausen 833b44b2e06SPablo Anton ret = adv76xx_read_reg(sd, reg->reg); 834d42010a1SLars-Peter Clausen if (ret < 0) { 83554450f59SHans Verkuil v4l2_info(sd, "Register %03llx not supported\n", reg->reg); 836b44b2e06SPablo Anton adv76xx_inv_register(sd); 837d42010a1SLars-Peter Clausen return ret; 83854450f59SHans Verkuil } 839d42010a1SLars-Peter Clausen 840d42010a1SLars-Peter Clausen reg->size = 1; 841d42010a1SLars-Peter Clausen reg->val = ret; 842d42010a1SLars-Peter Clausen 84354450f59SHans Verkuil return 0; 84454450f59SHans Verkuil } 84554450f59SHans Verkuil 846b44b2e06SPablo Anton static int adv76xx_s_register(struct v4l2_subdev *sd, 847977ba3b1SHans Verkuil const struct v4l2_dbg_register *reg) 84854450f59SHans Verkuil { 849d42010a1SLars-Peter Clausen int ret; 8501577461bSHans Verkuil 851b44b2e06SPablo Anton ret = adv76xx_write_reg(sd, reg->reg, reg->val); 852d42010a1SLars-Peter Clausen if (ret < 0) { 85354450f59SHans Verkuil v4l2_info(sd, "Register %03llx not supported\n", reg->reg); 854b44b2e06SPablo Anton adv76xx_inv_register(sd); 855d42010a1SLars-Peter Clausen return ret; 85654450f59SHans Verkuil } 857d42010a1SLars-Peter Clausen 85854450f59SHans Verkuil return 0; 85954450f59SHans Verkuil } 86054450f59SHans Verkuil #endif 86154450f59SHans Verkuil 862d42010a1SLars-Peter Clausen static unsigned int adv7604_read_cable_det(struct v4l2_subdev *sd) 863d42010a1SLars-Peter Clausen { 864d42010a1SLars-Peter Clausen u8 value = io_read(sd, 0x6f); 865d42010a1SLars-Peter Clausen 866d42010a1SLars-Peter Clausen return ((value & 0x10) >> 4) 867d42010a1SLars-Peter Clausen | ((value & 0x08) >> 2) 868d42010a1SLars-Peter Clausen | ((value & 0x04) << 0) 869d42010a1SLars-Peter Clausen | ((value & 0x02) << 2); 870d42010a1SLars-Peter Clausen } 871d42010a1SLars-Peter Clausen 872d42010a1SLars-Peter Clausen static unsigned int adv7611_read_cable_det(struct v4l2_subdev *sd) 873d42010a1SLars-Peter Clausen { 874d42010a1SLars-Peter Clausen u8 value = io_read(sd, 0x6f); 875d42010a1SLars-Peter Clausen 876d42010a1SLars-Peter Clausen return value & 1; 877d42010a1SLars-Peter Clausen } 878d42010a1SLars-Peter Clausen 879b44b2e06SPablo Anton static int adv76xx_s_detect_tx_5v_ctrl(struct v4l2_subdev *sd) 88054450f59SHans Verkuil { 881b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 882b44b2e06SPablo Anton const struct adv76xx_chip_info *info = state->info; 88354450f59SHans Verkuil 88454450f59SHans Verkuil return v4l2_ctrl_s_ctrl(state->detect_tx_5v_ctrl, 885d42010a1SLars-Peter Clausen info->read_cable_det(sd)); 88654450f59SHans Verkuil } 88754450f59SHans Verkuil 888ccbd5bc4SHans Verkuil static int find_and_set_predefined_video_timings(struct v4l2_subdev *sd, 889ccbd5bc4SHans Verkuil u8 prim_mode, 890b44b2e06SPablo Anton const struct adv76xx_video_standards *predef_vid_timings, 891ccbd5bc4SHans Verkuil const struct v4l2_dv_timings *timings) 89254450f59SHans Verkuil { 893ccbd5bc4SHans Verkuil int i; 89454450f59SHans Verkuil 895ccbd5bc4SHans Verkuil for (i = 0; predef_vid_timings[i].timings.bt.width; i++) { 896ef1ed8f5SHans Verkuil if (!v4l2_match_dv_timings(timings, &predef_vid_timings[i].timings, 8974a31a93aSMats Randgaard is_digital_input(sd) ? 250000 : 1000000)) 898ccbd5bc4SHans Verkuil continue; 899ccbd5bc4SHans Verkuil io_write(sd, 0x00, predef_vid_timings[i].vid_std); /* video std */ 900ccbd5bc4SHans Verkuil io_write(sd, 0x01, (predef_vid_timings[i].v_freq << 4) + 901ccbd5bc4SHans Verkuil prim_mode); /* v_freq and prim mode */ 902ccbd5bc4SHans Verkuil return 0; 90354450f59SHans Verkuil } 90454450f59SHans Verkuil 905ccbd5bc4SHans Verkuil return -1; 906ccbd5bc4SHans Verkuil } 90754450f59SHans Verkuil 908ccbd5bc4SHans Verkuil static int configure_predefined_video_timings(struct v4l2_subdev *sd, 909ccbd5bc4SHans Verkuil struct v4l2_dv_timings *timings) 910ccbd5bc4SHans Verkuil { 911b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 912ccbd5bc4SHans Verkuil int err; 913ccbd5bc4SHans Verkuil 914ccbd5bc4SHans Verkuil v4l2_dbg(1, debug, sd, "%s", __func__); 915ccbd5bc4SHans Verkuil 916b44b2e06SPablo Anton if (adv76xx_has_afe(state)) { 91754450f59SHans Verkuil /* reset to default values */ 91854450f59SHans Verkuil io_write(sd, 0x16, 0x43); 91954450f59SHans Verkuil io_write(sd, 0x17, 0x5a); 920d42010a1SLars-Peter Clausen } 921ccbd5bc4SHans Verkuil /* disable embedded syncs for auto graphics mode */ 92222d97e56SLaurent Pinchart cp_write_clr_set(sd, 0x81, 0x10, 0x00); 923ccbd5bc4SHans Verkuil cp_write(sd, 0x8f, 0x00); 924ccbd5bc4SHans Verkuil cp_write(sd, 0x90, 0x00); 92554450f59SHans Verkuil cp_write(sd, 0xa2, 0x00); 92654450f59SHans Verkuil cp_write(sd, 0xa3, 0x00); 92754450f59SHans Verkuil cp_write(sd, 0xa4, 0x00); 92854450f59SHans Verkuil cp_write(sd, 0xa5, 0x00); 92954450f59SHans Verkuil cp_write(sd, 0xa6, 0x00); 93054450f59SHans Verkuil cp_write(sd, 0xa7, 0x00); 931ccbd5bc4SHans Verkuil cp_write(sd, 0xab, 0x00); 932ccbd5bc4SHans Verkuil cp_write(sd, 0xac, 0x00); 933ccbd5bc4SHans Verkuil 9344a31a93aSMats Randgaard if (is_analog_input(sd)) { 935ccbd5bc4SHans Verkuil err = find_and_set_predefined_video_timings(sd, 936ccbd5bc4SHans Verkuil 0x01, adv7604_prim_mode_comp, timings); 937ccbd5bc4SHans Verkuil if (err) 938ccbd5bc4SHans Verkuil err = find_and_set_predefined_video_timings(sd, 939ccbd5bc4SHans Verkuil 0x02, adv7604_prim_mode_gr, timings); 9404a31a93aSMats Randgaard } else if (is_digital_input(sd)) { 941ccbd5bc4SHans Verkuil err = find_and_set_predefined_video_timings(sd, 942b44b2e06SPablo Anton 0x05, adv76xx_prim_mode_hdmi_comp, timings); 943ccbd5bc4SHans Verkuil if (err) 944ccbd5bc4SHans Verkuil err = find_and_set_predefined_video_timings(sd, 945b44b2e06SPablo Anton 0x06, adv76xx_prim_mode_hdmi_gr, timings); 9464a31a93aSMats Randgaard } else { 9474a31a93aSMats Randgaard v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n", 9484a31a93aSMats Randgaard __func__, state->selected_input); 949ccbd5bc4SHans Verkuil err = -1; 95054450f59SHans Verkuil } 95154450f59SHans Verkuil 95254450f59SHans Verkuil 953ccbd5bc4SHans Verkuil return err; 954ccbd5bc4SHans Verkuil } 955ccbd5bc4SHans Verkuil 956ccbd5bc4SHans Verkuil static void configure_custom_video_timings(struct v4l2_subdev *sd, 957ccbd5bc4SHans Verkuil const struct v4l2_bt_timings *bt) 958ccbd5bc4SHans Verkuil { 959b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 960ccbd5bc4SHans Verkuil u32 width = htotal(bt); 961ccbd5bc4SHans Verkuil u32 height = vtotal(bt); 962ccbd5bc4SHans Verkuil u16 cp_start_sav = bt->hsync + bt->hbackporch - 4; 963ccbd5bc4SHans Verkuil u16 cp_start_eav = width - bt->hfrontporch; 964ccbd5bc4SHans Verkuil u16 cp_start_vbi = height - bt->vfrontporch; 965ccbd5bc4SHans Verkuil u16 cp_end_vbi = bt->vsync + bt->vbackporch; 966ccbd5bc4SHans Verkuil u16 ch1_fr_ll = (((u32)bt->pixelclock / 100) > 0) ? 967b44b2e06SPablo Anton ((width * (ADV76XX_FSC / 100)) / ((u32)bt->pixelclock / 100)) : 0; 968ccbd5bc4SHans Verkuil const u8 pll[2] = { 969ccbd5bc4SHans Verkuil 0xc0 | ((width >> 8) & 0x1f), 970ccbd5bc4SHans Verkuil width & 0xff 971ccbd5bc4SHans Verkuil }; 972ccbd5bc4SHans Verkuil 973ccbd5bc4SHans Verkuil v4l2_dbg(2, debug, sd, "%s\n", __func__); 974ccbd5bc4SHans Verkuil 9754a31a93aSMats Randgaard if (is_analog_input(sd)) { 976ccbd5bc4SHans Verkuil /* auto graphics */ 977ccbd5bc4SHans Verkuil io_write(sd, 0x00, 0x07); /* video std */ 978ccbd5bc4SHans Verkuil io_write(sd, 0x01, 0x02); /* prim mode */ 979ccbd5bc4SHans Verkuil /* enable embedded syncs for auto graphics mode */ 98022d97e56SLaurent Pinchart cp_write_clr_set(sd, 0x81, 0x10, 0x10); 981ccbd5bc4SHans Verkuil 982ccbd5bc4SHans Verkuil /* Should only be set in auto-graphics mode [REF_02, p. 91-92] */ 983ccbd5bc4SHans Verkuil /* setup PLL_DIV_MAN_EN and PLL_DIV_RATIO */ 984ccbd5bc4SHans Verkuil /* IO-map reg. 0x16 and 0x17 should be written in sequence */ 985f862f57dSPablo Anton if (regmap_raw_write(state->regmap[ADV76XX_PAGE_IO], 986f862f57dSPablo Anton 0x16, pll, 2)) 987ccbd5bc4SHans Verkuil v4l2_err(sd, "writing to reg 0x16 and 0x17 failed\n"); 988ccbd5bc4SHans Verkuil 989ccbd5bc4SHans Verkuil /* active video - horizontal timing */ 990ccbd5bc4SHans Verkuil cp_write(sd, 0xa2, (cp_start_sav >> 4) & 0xff); 991ccbd5bc4SHans Verkuil cp_write(sd, 0xa3, ((cp_start_sav & 0x0f) << 4) | 992ccbd5bc4SHans Verkuil ((cp_start_eav >> 8) & 0x0f)); 993ccbd5bc4SHans Verkuil cp_write(sd, 0xa4, cp_start_eav & 0xff); 994ccbd5bc4SHans Verkuil 995ccbd5bc4SHans Verkuil /* active video - vertical timing */ 996ccbd5bc4SHans Verkuil cp_write(sd, 0xa5, (cp_start_vbi >> 4) & 0xff); 997ccbd5bc4SHans Verkuil cp_write(sd, 0xa6, ((cp_start_vbi & 0xf) << 4) | 998ccbd5bc4SHans Verkuil ((cp_end_vbi >> 8) & 0xf)); 999ccbd5bc4SHans Verkuil cp_write(sd, 0xa7, cp_end_vbi & 0xff); 10004a31a93aSMats Randgaard } else if (is_digital_input(sd)) { 1001ccbd5bc4SHans Verkuil /* set default prim_mode/vid_std for HDMI 100239c1cb2bSJonathan McCrohan according to [REF_03, c. 4.2] */ 1003ccbd5bc4SHans Verkuil io_write(sd, 0x00, 0x02); /* video std */ 1004ccbd5bc4SHans Verkuil io_write(sd, 0x01, 0x06); /* prim mode */ 10054a31a93aSMats Randgaard } else { 10064a31a93aSMats Randgaard v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n", 10074a31a93aSMats Randgaard __func__, state->selected_input); 1008ccbd5bc4SHans Verkuil } 1009ccbd5bc4SHans Verkuil 1010ccbd5bc4SHans Verkuil cp_write(sd, 0x8f, (ch1_fr_ll >> 8) & 0x7); 1011ccbd5bc4SHans Verkuil cp_write(sd, 0x90, ch1_fr_ll & 0xff); 1012ccbd5bc4SHans Verkuil cp_write(sd, 0xab, (height >> 4) & 0xff); 1013ccbd5bc4SHans Verkuil cp_write(sd, 0xac, (height & 0x0f) << 4); 1014ccbd5bc4SHans Verkuil } 1015ccbd5bc4SHans Verkuil 1016b44b2e06SPablo Anton static void adv76xx_set_offset(struct v4l2_subdev *sd, bool auto_offset, u16 offset_a, u16 offset_b, u16 offset_c) 10175c6c6349SMats Randgaard { 1018b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 10195c6c6349SMats Randgaard u8 offset_buf[4]; 10205c6c6349SMats Randgaard 10215c6c6349SMats Randgaard if (auto_offset) { 10225c6c6349SMats Randgaard offset_a = 0x3ff; 10235c6c6349SMats Randgaard offset_b = 0x3ff; 10245c6c6349SMats Randgaard offset_c = 0x3ff; 10255c6c6349SMats Randgaard } 10265c6c6349SMats Randgaard 10275c6c6349SMats Randgaard v4l2_dbg(2, debug, sd, "%s: %s offset: a = 0x%x, b = 0x%x, c = 0x%x\n", 10285c6c6349SMats Randgaard __func__, auto_offset ? "Auto" : "Manual", 10295c6c6349SMats Randgaard offset_a, offset_b, offset_c); 10305c6c6349SMats Randgaard 10315c6c6349SMats Randgaard offset_buf[0] = (cp_read(sd, 0x77) & 0xc0) | ((offset_a & 0x3f0) >> 4); 10325c6c6349SMats Randgaard offset_buf[1] = ((offset_a & 0x00f) << 4) | ((offset_b & 0x3c0) >> 6); 10335c6c6349SMats Randgaard offset_buf[2] = ((offset_b & 0x03f) << 2) | ((offset_c & 0x300) >> 8); 10345c6c6349SMats Randgaard offset_buf[3] = offset_c & 0x0ff; 10355c6c6349SMats Randgaard 10365c6c6349SMats Randgaard /* Registers must be written in this order with no i2c access in between */ 1037f862f57dSPablo Anton if (regmap_raw_write(state->regmap[ADV76XX_PAGE_CP], 1038f862f57dSPablo Anton 0x77, offset_buf, 4)) 10395c6c6349SMats Randgaard v4l2_err(sd, "%s: i2c error writing to CP reg 0x77, 0x78, 0x79, 0x7a\n", __func__); 10405c6c6349SMats Randgaard } 10415c6c6349SMats Randgaard 1042b44b2e06SPablo Anton static void adv76xx_set_gain(struct v4l2_subdev *sd, bool auto_gain, u16 gain_a, u16 gain_b, u16 gain_c) 10435c6c6349SMats Randgaard { 1044b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 10455c6c6349SMats Randgaard u8 gain_buf[4]; 10465c6c6349SMats Randgaard u8 gain_man = 1; 10475c6c6349SMats Randgaard u8 agc_mode_man = 1; 10485c6c6349SMats Randgaard 10495c6c6349SMats Randgaard if (auto_gain) { 10505c6c6349SMats Randgaard gain_man = 0; 10515c6c6349SMats Randgaard agc_mode_man = 0; 10525c6c6349SMats Randgaard gain_a = 0x100; 10535c6c6349SMats Randgaard gain_b = 0x100; 10545c6c6349SMats Randgaard gain_c = 0x100; 10555c6c6349SMats Randgaard } 10565c6c6349SMats Randgaard 10575c6c6349SMats Randgaard v4l2_dbg(2, debug, sd, "%s: %s gain: a = 0x%x, b = 0x%x, c = 0x%x\n", 10585c6c6349SMats Randgaard __func__, auto_gain ? "Auto" : "Manual", 10595c6c6349SMats Randgaard gain_a, gain_b, gain_c); 10605c6c6349SMats Randgaard 10615c6c6349SMats Randgaard gain_buf[0] = ((gain_man << 7) | (agc_mode_man << 6) | ((gain_a & 0x3f0) >> 4)); 10625c6c6349SMats Randgaard gain_buf[1] = (((gain_a & 0x00f) << 4) | ((gain_b & 0x3c0) >> 6)); 10635c6c6349SMats Randgaard gain_buf[2] = (((gain_b & 0x03f) << 2) | ((gain_c & 0x300) >> 8)); 10645c6c6349SMats Randgaard gain_buf[3] = ((gain_c & 0x0ff)); 10655c6c6349SMats Randgaard 10665c6c6349SMats Randgaard /* Registers must be written in this order with no i2c access in between */ 1067f862f57dSPablo Anton if (regmap_raw_write(state->regmap[ADV76XX_PAGE_CP], 1068f862f57dSPablo Anton 0x73, gain_buf, 4)) 10695c6c6349SMats Randgaard v4l2_err(sd, "%s: i2c error writing to CP reg 0x73, 0x74, 0x75, 0x76\n", __func__); 10705c6c6349SMats Randgaard } 10715c6c6349SMats Randgaard 107254450f59SHans Verkuil static void set_rgb_quantization_range(struct v4l2_subdev *sd) 107354450f59SHans Verkuil { 1074b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 10755c6c6349SMats Randgaard bool rgb_output = io_read(sd, 0x02) & 0x02; 10765c6c6349SMats Randgaard bool hdmi_signal = hdmi_read(sd, 0x05) & 0x80; 107754450f59SHans Verkuil 10785c6c6349SMats Randgaard v4l2_dbg(2, debug, sd, "%s: RGB quantization range: %d, RGB out: %d, HDMI: %d\n", 10795c6c6349SMats Randgaard __func__, state->rgb_quantization_range, 10805c6c6349SMats Randgaard rgb_output, hdmi_signal); 10815c6c6349SMats Randgaard 1082b44b2e06SPablo Anton adv76xx_set_gain(sd, true, 0x0, 0x0, 0x0); 1083b44b2e06SPablo Anton adv76xx_set_offset(sd, true, 0x0, 0x0, 0x0); 10849833239eSMats Randgaard 108554450f59SHans Verkuil switch (state->rgb_quantization_range) { 108654450f59SHans Verkuil case V4L2_DV_RGB_RANGE_AUTO: 1087c784b1e2SLaurent Pinchart if (state->selected_input == ADV7604_PAD_VGA_RGB) { 10889833239eSMats Randgaard /* Receiving analog RGB signal 10899833239eSMats Randgaard * Set RGB full range (0-255) */ 109022d97e56SLaurent Pinchart io_write_clr_set(sd, 0x02, 0xf0, 0x10); 10919833239eSMats Randgaard break; 10929833239eSMats Randgaard } 109354450f59SHans Verkuil 1094c784b1e2SLaurent Pinchart if (state->selected_input == ADV7604_PAD_VGA_COMP) { 10959833239eSMats Randgaard /* Receiving analog YPbPr signal 10969833239eSMats Randgaard * Set automode */ 109722d97e56SLaurent Pinchart io_write_clr_set(sd, 0x02, 0xf0, 0xf0); 10989833239eSMats Randgaard break; 10999833239eSMats Randgaard } 11009833239eSMats Randgaard 11015c6c6349SMats Randgaard if (hdmi_signal) { 11029833239eSMats Randgaard /* Receiving HDMI signal 11039833239eSMats Randgaard * Set automode */ 110422d97e56SLaurent Pinchart io_write_clr_set(sd, 0x02, 0xf0, 0xf0); 11059833239eSMats Randgaard break; 11069833239eSMats Randgaard } 11079833239eSMats Randgaard 11089833239eSMats Randgaard /* Receiving DVI-D signal 11099833239eSMats Randgaard * ADV7604 selects RGB limited range regardless of 11109833239eSMats Randgaard * input format (CE/IT) in automatic mode */ 1111680fee04SHans Verkuil if (state->timings.bt.flags & V4L2_DV_FL_IS_CE_VIDEO) { 111254450f59SHans Verkuil /* RGB limited range (16-235) */ 111322d97e56SLaurent Pinchart io_write_clr_set(sd, 0x02, 0xf0, 0x00); 111454450f59SHans Verkuil } else { 111554450f59SHans Verkuil /* RGB full range (0-255) */ 111622d97e56SLaurent Pinchart io_write_clr_set(sd, 0x02, 0xf0, 0x10); 11175c6c6349SMats Randgaard 11185c6c6349SMats Randgaard if (is_digital_input(sd) && rgb_output) { 1119b44b2e06SPablo Anton adv76xx_set_offset(sd, false, 0x40, 0x40, 0x40); 11205c6c6349SMats Randgaard } else { 1121b44b2e06SPablo Anton adv76xx_set_gain(sd, false, 0xe0, 0xe0, 0xe0); 1122b44b2e06SPablo Anton adv76xx_set_offset(sd, false, 0x70, 0x70, 0x70); 11235c6c6349SMats Randgaard } 112454450f59SHans Verkuil } 112554450f59SHans Verkuil break; 112654450f59SHans Verkuil case V4L2_DV_RGB_RANGE_LIMITED: 1127c784b1e2SLaurent Pinchart if (state->selected_input == ADV7604_PAD_VGA_COMP) { 1128d261e842SMats Randgaard /* YCrCb limited range (16-235) */ 112922d97e56SLaurent Pinchart io_write_clr_set(sd, 0x02, 0xf0, 0x20); 11305c6c6349SMats Randgaard break; 11315c6c6349SMats Randgaard } 11325c6c6349SMats Randgaard 113354450f59SHans Verkuil /* RGB limited range (16-235) */ 113422d97e56SLaurent Pinchart io_write_clr_set(sd, 0x02, 0xf0, 0x00); 11355c6c6349SMats Randgaard 113654450f59SHans Verkuil break; 113754450f59SHans Verkuil case V4L2_DV_RGB_RANGE_FULL: 1138c784b1e2SLaurent Pinchart if (state->selected_input == ADV7604_PAD_VGA_COMP) { 1139d261e842SMats Randgaard /* YCrCb full range (0-255) */ 114022d97e56SLaurent Pinchart io_write_clr_set(sd, 0x02, 0xf0, 0x60); 11415c6c6349SMats Randgaard break; 11425c6c6349SMats Randgaard } 11435c6c6349SMats Randgaard 114454450f59SHans Verkuil /* RGB full range (0-255) */ 114522d97e56SLaurent Pinchart io_write_clr_set(sd, 0x02, 0xf0, 0x10); 11465c6c6349SMats Randgaard 11475c6c6349SMats Randgaard if (is_analog_input(sd) || hdmi_signal) 11485c6c6349SMats Randgaard break; 11495c6c6349SMats Randgaard 11505c6c6349SMats Randgaard /* Adjust gain/offset for DVI-D signals only */ 11515c6c6349SMats Randgaard if (rgb_output) { 1152b44b2e06SPablo Anton adv76xx_set_offset(sd, false, 0x40, 0x40, 0x40); 11535c6c6349SMats Randgaard } else { 1154b44b2e06SPablo Anton adv76xx_set_gain(sd, false, 0xe0, 0xe0, 0xe0); 1155b44b2e06SPablo Anton adv76xx_set_offset(sd, false, 0x70, 0x70, 0x70); 1156d261e842SMats Randgaard } 115754450f59SHans Verkuil break; 115854450f59SHans Verkuil } 115954450f59SHans Verkuil } 116054450f59SHans Verkuil 1161b44b2e06SPablo Anton static int adv76xx_s_ctrl(struct v4l2_ctrl *ctrl) 116254450f59SHans Verkuil { 1163c269887cSLaurent Pinchart struct v4l2_subdev *sd = 1164b44b2e06SPablo Anton &container_of(ctrl->handler, struct adv76xx_state, hdl)->sd; 1165c269887cSLaurent Pinchart 1166b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 116754450f59SHans Verkuil 116854450f59SHans Verkuil switch (ctrl->id) { 116954450f59SHans Verkuil case V4L2_CID_BRIGHTNESS: 117054450f59SHans Verkuil cp_write(sd, 0x3c, ctrl->val); 117154450f59SHans Verkuil return 0; 117254450f59SHans Verkuil case V4L2_CID_CONTRAST: 117354450f59SHans Verkuil cp_write(sd, 0x3a, ctrl->val); 117454450f59SHans Verkuil return 0; 117554450f59SHans Verkuil case V4L2_CID_SATURATION: 117654450f59SHans Verkuil cp_write(sd, 0x3b, ctrl->val); 117754450f59SHans Verkuil return 0; 117854450f59SHans Verkuil case V4L2_CID_HUE: 117954450f59SHans Verkuil cp_write(sd, 0x3d, ctrl->val); 118054450f59SHans Verkuil return 0; 118154450f59SHans Verkuil case V4L2_CID_DV_RX_RGB_RANGE: 118254450f59SHans Verkuil state->rgb_quantization_range = ctrl->val; 118354450f59SHans Verkuil set_rgb_quantization_range(sd); 118454450f59SHans Verkuil return 0; 118554450f59SHans Verkuil case V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE: 1186b44b2e06SPablo Anton if (!adv76xx_has_afe(state)) 1187d42010a1SLars-Peter Clausen return -EINVAL; 118854450f59SHans Verkuil /* Set the analog sampling phase. This is needed to find the 118954450f59SHans Verkuil best sampling phase for analog video: an application or 119054450f59SHans Verkuil driver has to try a number of phases and analyze the picture 119154450f59SHans Verkuil quality before settling on the best performing phase. */ 119254450f59SHans Verkuil afe_write(sd, 0xc8, ctrl->val); 119354450f59SHans Verkuil return 0; 119454450f59SHans Verkuil case V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL: 119554450f59SHans Verkuil /* Use the default blue color for free running mode, 119654450f59SHans Verkuil or supply your own. */ 119722d97e56SLaurent Pinchart cp_write_clr_set(sd, 0xbf, 0x04, ctrl->val << 2); 119854450f59SHans Verkuil return 0; 119954450f59SHans Verkuil case V4L2_CID_ADV_RX_FREE_RUN_COLOR: 120054450f59SHans Verkuil cp_write(sd, 0xc0, (ctrl->val & 0xff0000) >> 16); 120154450f59SHans Verkuil cp_write(sd, 0xc1, (ctrl->val & 0x00ff00) >> 8); 120254450f59SHans Verkuil cp_write(sd, 0xc2, (u8)(ctrl->val & 0x0000ff)); 120354450f59SHans Verkuil return 0; 120454450f59SHans Verkuil } 120554450f59SHans Verkuil return -EINVAL; 120654450f59SHans Verkuil } 120754450f59SHans Verkuil 120854450f59SHans Verkuil /* ----------------------------------------------------------------------- */ 120954450f59SHans Verkuil 121054450f59SHans Verkuil static inline bool no_power(struct v4l2_subdev *sd) 121154450f59SHans Verkuil { 121254450f59SHans Verkuil /* Entire chip or CP powered off */ 121354450f59SHans Verkuil return io_read(sd, 0x0c) & 0x24; 121454450f59SHans Verkuil } 121554450f59SHans Verkuil 121654450f59SHans Verkuil static inline bool no_signal_tmds(struct v4l2_subdev *sd) 121754450f59SHans Verkuil { 1218b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 12194a31a93aSMats Randgaard 12204a31a93aSMats Randgaard return !(io_read(sd, 0x6a) & (0x10 >> state->selected_input)); 122154450f59SHans Verkuil } 122254450f59SHans Verkuil 122354450f59SHans Verkuil static inline bool no_lock_tmds(struct v4l2_subdev *sd) 122454450f59SHans Verkuil { 1225b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 1226b44b2e06SPablo Anton const struct adv76xx_chip_info *info = state->info; 1227d42010a1SLars-Peter Clausen 1228d42010a1SLars-Peter Clausen return (io_read(sd, 0x6a) & info->tdms_lock_mask) != info->tdms_lock_mask; 122954450f59SHans Verkuil } 123054450f59SHans Verkuil 1231bb88f325SMartin Bugge static inline bool is_hdmi(struct v4l2_subdev *sd) 1232bb88f325SMartin Bugge { 1233bb88f325SMartin Bugge return hdmi_read(sd, 0x05) & 0x80; 1234bb88f325SMartin Bugge } 1235bb88f325SMartin Bugge 123654450f59SHans Verkuil static inline bool no_lock_sspd(struct v4l2_subdev *sd) 123754450f59SHans Verkuil { 1238b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 1239d42010a1SLars-Peter Clausen 1240d42010a1SLars-Peter Clausen /* 1241d42010a1SLars-Peter Clausen * Chips without a AFE don't expose registers for the SSPD, so just assume 1242d42010a1SLars-Peter Clausen * that we have a lock. 1243d42010a1SLars-Peter Clausen */ 1244b44b2e06SPablo Anton if (adv76xx_has_afe(state)) 1245d42010a1SLars-Peter Clausen return false; 1246d42010a1SLars-Peter Clausen 124754450f59SHans Verkuil /* TODO channel 2 */ 124854450f59SHans Verkuil return ((cp_read(sd, 0xb5) & 0xd0) != 0xd0); 124954450f59SHans Verkuil } 125054450f59SHans Verkuil 125154450f59SHans Verkuil static inline bool no_lock_stdi(struct v4l2_subdev *sd) 125254450f59SHans Verkuil { 125354450f59SHans Verkuil /* TODO channel 2 */ 125454450f59SHans Verkuil return !(cp_read(sd, 0xb1) & 0x80); 125554450f59SHans Verkuil } 125654450f59SHans Verkuil 125754450f59SHans Verkuil static inline bool no_signal(struct v4l2_subdev *sd) 125854450f59SHans Verkuil { 125954450f59SHans Verkuil bool ret; 126054450f59SHans Verkuil 126154450f59SHans Verkuil ret = no_power(sd); 126254450f59SHans Verkuil 126354450f59SHans Verkuil ret |= no_lock_stdi(sd); 126454450f59SHans Verkuil ret |= no_lock_sspd(sd); 126554450f59SHans Verkuil 12664a31a93aSMats Randgaard if (is_digital_input(sd)) { 126754450f59SHans Verkuil ret |= no_lock_tmds(sd); 126854450f59SHans Verkuil ret |= no_signal_tmds(sd); 126954450f59SHans Verkuil } 127054450f59SHans Verkuil 127154450f59SHans Verkuil return ret; 127254450f59SHans Verkuil } 127354450f59SHans Verkuil 127454450f59SHans Verkuil static inline bool no_lock_cp(struct v4l2_subdev *sd) 127554450f59SHans Verkuil { 1276b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 1277d42010a1SLars-Peter Clausen 1278b44b2e06SPablo Anton if (!adv76xx_has_afe(state)) 1279d42010a1SLars-Peter Clausen return false; 1280d42010a1SLars-Peter Clausen 128154450f59SHans Verkuil /* CP has detected a non standard number of lines on the incoming 128254450f59SHans Verkuil video compared to what it is configured to receive by s_dv_timings */ 128354450f59SHans Verkuil return io_read(sd, 0x12) & 0x01; 128454450f59SHans Verkuil } 128554450f59SHans Verkuil 128658514625Sjean-michel.hautbois@vodalys.com static inline bool in_free_run(struct v4l2_subdev *sd) 128758514625Sjean-michel.hautbois@vodalys.com { 128858514625Sjean-michel.hautbois@vodalys.com return cp_read(sd, 0xff) & 0x10; 128958514625Sjean-michel.hautbois@vodalys.com } 129058514625Sjean-michel.hautbois@vodalys.com 1291b44b2e06SPablo Anton static int adv76xx_g_input_status(struct v4l2_subdev *sd, u32 *status) 129254450f59SHans Verkuil { 129354450f59SHans Verkuil *status = 0; 129454450f59SHans Verkuil *status |= no_power(sd) ? V4L2_IN_ST_NO_POWER : 0; 129554450f59SHans Verkuil *status |= no_signal(sd) ? V4L2_IN_ST_NO_SIGNAL : 0; 129658514625Sjean-michel.hautbois@vodalys.com if (!in_free_run(sd) && no_lock_cp(sd)) 129758514625Sjean-michel.hautbois@vodalys.com *status |= is_digital_input(sd) ? 129858514625Sjean-michel.hautbois@vodalys.com V4L2_IN_ST_NO_SYNC : V4L2_IN_ST_NO_H_LOCK; 129954450f59SHans Verkuil 130054450f59SHans Verkuil v4l2_dbg(1, debug, sd, "%s: status = 0x%x\n", __func__, *status); 130154450f59SHans Verkuil 130254450f59SHans Verkuil return 0; 130354450f59SHans Verkuil } 130454450f59SHans Verkuil 130554450f59SHans Verkuil /* ----------------------------------------------------------------------- */ 130654450f59SHans Verkuil 130754450f59SHans Verkuil struct stdi_readback { 130854450f59SHans Verkuil u16 bl, lcf, lcvs; 130954450f59SHans Verkuil u8 hs_pol, vs_pol; 131054450f59SHans Verkuil bool interlaced; 131154450f59SHans Verkuil }; 131254450f59SHans Verkuil 131354450f59SHans Verkuil static int stdi2dv_timings(struct v4l2_subdev *sd, 131454450f59SHans Verkuil struct stdi_readback *stdi, 131554450f59SHans Verkuil struct v4l2_dv_timings *timings) 131654450f59SHans Verkuil { 1317b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 1318b44b2e06SPablo Anton u32 hfreq = (ADV76XX_FSC * 8) / stdi->bl; 131954450f59SHans Verkuil u32 pix_clk; 132054450f59SHans Verkuil int i; 132154450f59SHans Verkuil 1322b44b2e06SPablo Anton for (i = 0; adv76xx_timings[i].bt.height; i++) { 1323b44b2e06SPablo Anton if (vtotal(&adv76xx_timings[i].bt) != stdi->lcf + 1) 132454450f59SHans Verkuil continue; 1325b44b2e06SPablo Anton if (adv76xx_timings[i].bt.vsync != stdi->lcvs) 132654450f59SHans Verkuil continue; 132754450f59SHans Verkuil 1328b44b2e06SPablo Anton pix_clk = hfreq * htotal(&adv76xx_timings[i].bt); 132954450f59SHans Verkuil 1330b44b2e06SPablo Anton if ((pix_clk < adv76xx_timings[i].bt.pixelclock + 1000000) && 1331b44b2e06SPablo Anton (pix_clk > adv76xx_timings[i].bt.pixelclock - 1000000)) { 1332b44b2e06SPablo Anton *timings = adv76xx_timings[i]; 133354450f59SHans Verkuil return 0; 133454450f59SHans Verkuil } 133554450f59SHans Verkuil } 133654450f59SHans Verkuil 13375fea1bb7SPrashant Laddha if (v4l2_detect_cvt(stdi->lcf + 1, hfreq, stdi->lcvs, 0, 133854450f59SHans Verkuil (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) | 133954450f59SHans Verkuil (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0), 1340061ddda6SPrashant Laddha false, timings)) 134154450f59SHans Verkuil return 0; 134254450f59SHans Verkuil if (v4l2_detect_gtf(stdi->lcf + 1, hfreq, stdi->lcvs, 134354450f59SHans Verkuil (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) | 134454450f59SHans Verkuil (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0), 1345061ddda6SPrashant Laddha false, state->aspect_ratio, timings)) 134654450f59SHans Verkuil return 0; 134754450f59SHans Verkuil 1348ccbd5bc4SHans Verkuil v4l2_dbg(2, debug, sd, 1349ccbd5bc4SHans Verkuil "%s: No format candidate found for lcvs = %d, lcf=%d, bl = %d, %chsync, %cvsync\n", 1350ccbd5bc4SHans Verkuil __func__, stdi->lcvs, stdi->lcf, stdi->bl, 1351ccbd5bc4SHans Verkuil stdi->hs_pol, stdi->vs_pol); 135254450f59SHans Verkuil return -1; 135354450f59SHans Verkuil } 135454450f59SHans Verkuil 1355d42010a1SLars-Peter Clausen 135654450f59SHans Verkuil static int read_stdi(struct v4l2_subdev *sd, struct stdi_readback *stdi) 135754450f59SHans Verkuil { 1358b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 1359b44b2e06SPablo Anton const struct adv76xx_chip_info *info = state->info; 13604a2ccdd2SLaurent Pinchart u8 polarity; 13614a2ccdd2SLaurent Pinchart 136254450f59SHans Verkuil if (no_lock_stdi(sd) || no_lock_sspd(sd)) { 136354450f59SHans Verkuil v4l2_dbg(2, debug, sd, "%s: STDI and/or SSPD not locked\n", __func__); 136454450f59SHans Verkuil return -1; 136554450f59SHans Verkuil } 136654450f59SHans Verkuil 136754450f59SHans Verkuil /* read STDI */ 136851182a94SLaurent Pinchart stdi->bl = cp_read16(sd, 0xb1, 0x3fff); 1369d42010a1SLars-Peter Clausen stdi->lcf = cp_read16(sd, info->lcf_reg, 0x7ff); 137054450f59SHans Verkuil stdi->lcvs = cp_read(sd, 0xb3) >> 3; 137154450f59SHans Verkuil stdi->interlaced = io_read(sd, 0x12) & 0x10; 137254450f59SHans Verkuil 1373b44b2e06SPablo Anton if (adv76xx_has_afe(state)) { 137454450f59SHans Verkuil /* read SSPD */ 13754a2ccdd2SLaurent Pinchart polarity = cp_read(sd, 0xb5); 13764a2ccdd2SLaurent Pinchart if ((polarity & 0x03) == 0x01) { 13774a2ccdd2SLaurent Pinchart stdi->hs_pol = polarity & 0x10 13784a2ccdd2SLaurent Pinchart ? (polarity & 0x08 ? '+' : '-') : 'x'; 13794a2ccdd2SLaurent Pinchart stdi->vs_pol = polarity & 0x40 13804a2ccdd2SLaurent Pinchart ? (polarity & 0x20 ? '+' : '-') : 'x'; 138154450f59SHans Verkuil } else { 138254450f59SHans Verkuil stdi->hs_pol = 'x'; 138354450f59SHans Verkuil stdi->vs_pol = 'x'; 138454450f59SHans Verkuil } 1385d42010a1SLars-Peter Clausen } else { 1386d42010a1SLars-Peter Clausen polarity = hdmi_read(sd, 0x05); 1387d42010a1SLars-Peter Clausen stdi->hs_pol = polarity & 0x20 ? '+' : '-'; 1388d42010a1SLars-Peter Clausen stdi->vs_pol = polarity & 0x10 ? '+' : '-'; 1389d42010a1SLars-Peter Clausen } 139054450f59SHans Verkuil 139154450f59SHans Verkuil if (no_lock_stdi(sd) || no_lock_sspd(sd)) { 139254450f59SHans Verkuil v4l2_dbg(2, debug, sd, 139354450f59SHans Verkuil "%s: signal lost during readout of STDI/SSPD\n", __func__); 139454450f59SHans Verkuil return -1; 139554450f59SHans Verkuil } 139654450f59SHans Verkuil 139754450f59SHans Verkuil if (stdi->lcf < 239 || stdi->bl < 8 || stdi->bl == 0x3fff) { 139854450f59SHans Verkuil v4l2_dbg(2, debug, sd, "%s: invalid signal\n", __func__); 139954450f59SHans Verkuil memset(stdi, 0, sizeof(struct stdi_readback)); 140054450f59SHans Verkuil return -1; 140154450f59SHans Verkuil } 140254450f59SHans Verkuil 140354450f59SHans Verkuil v4l2_dbg(2, debug, sd, 140454450f59SHans Verkuil "%s: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %chsync, %cvsync, %s\n", 140554450f59SHans Verkuil __func__, stdi->lcf, stdi->bl, stdi->lcvs, 140654450f59SHans Verkuil stdi->hs_pol, stdi->vs_pol, 140754450f59SHans Verkuil stdi->interlaced ? "interlaced" : "progressive"); 140854450f59SHans Verkuil 140954450f59SHans Verkuil return 0; 141054450f59SHans Verkuil } 141154450f59SHans Verkuil 1412b44b2e06SPablo Anton static int adv76xx_enum_dv_timings(struct v4l2_subdev *sd, 141354450f59SHans Verkuil struct v4l2_enum_dv_timings *timings) 141454450f59SHans Verkuil { 1415b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 1416afec5599SLaurent Pinchart 1417b44b2e06SPablo Anton if (timings->index >= ARRAY_SIZE(adv76xx_timings) - 1) 141854450f59SHans Verkuil return -EINVAL; 1419afec5599SLaurent Pinchart 1420afec5599SLaurent Pinchart if (timings->pad >= state->source_pad) 1421afec5599SLaurent Pinchart return -EINVAL; 1422afec5599SLaurent Pinchart 142354450f59SHans Verkuil memset(timings->reserved, 0, sizeof(timings->reserved)); 1424b44b2e06SPablo Anton timings->timings = adv76xx_timings[timings->index]; 142554450f59SHans Verkuil return 0; 142654450f59SHans Verkuil } 142754450f59SHans Verkuil 1428b44b2e06SPablo Anton static int adv76xx_dv_timings_cap(struct v4l2_subdev *sd, 14297515e096SLaurent Pinchart struct v4l2_dv_timings_cap *cap) 1430afec5599SLaurent Pinchart { 1431b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 14327515e096SLaurent Pinchart 14337515e096SLaurent Pinchart if (cap->pad >= state->source_pad) 14347515e096SLaurent Pinchart return -EINVAL; 14357515e096SLaurent Pinchart 1436afec5599SLaurent Pinchart cap->type = V4L2_DV_BT_656_1120; 1437afec5599SLaurent Pinchart cap->bt.max_width = 1920; 1438afec5599SLaurent Pinchart cap->bt.max_height = 1200; 1439afec5599SLaurent Pinchart cap->bt.min_pixelclock = 25000000; 1440afec5599SLaurent Pinchart 14417515e096SLaurent Pinchart switch (cap->pad) { 1442b44b2e06SPablo Anton case ADV76XX_PAD_HDMI_PORT_A: 1443afec5599SLaurent Pinchart case ADV7604_PAD_HDMI_PORT_B: 1444afec5599SLaurent Pinchart case ADV7604_PAD_HDMI_PORT_C: 1445afec5599SLaurent Pinchart case ADV7604_PAD_HDMI_PORT_D: 1446afec5599SLaurent Pinchart cap->bt.max_pixelclock = 225000000; 1447afec5599SLaurent Pinchart break; 1448afec5599SLaurent Pinchart case ADV7604_PAD_VGA_RGB: 1449afec5599SLaurent Pinchart case ADV7604_PAD_VGA_COMP: 1450afec5599SLaurent Pinchart default: 1451afec5599SLaurent Pinchart cap->bt.max_pixelclock = 170000000; 1452afec5599SLaurent Pinchart break; 1453afec5599SLaurent Pinchart } 1454afec5599SLaurent Pinchart 1455afec5599SLaurent Pinchart cap->bt.standards = V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT | 1456afec5599SLaurent Pinchart V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT; 1457afec5599SLaurent Pinchart cap->bt.capabilities = V4L2_DV_BT_CAP_PROGRESSIVE | 1458afec5599SLaurent Pinchart V4L2_DV_BT_CAP_REDUCED_BLANKING | V4L2_DV_BT_CAP_CUSTOM; 1459afec5599SLaurent Pinchart return 0; 1460afec5599SLaurent Pinchart } 1461afec5599SLaurent Pinchart 146254450f59SHans Verkuil /* Fill the optional fields .standards and .flags in struct v4l2_dv_timings 1463b44b2e06SPablo Anton if the format is listed in adv76xx_timings[] */ 1464b44b2e06SPablo Anton static void adv76xx_fill_optional_dv_timings_fields(struct v4l2_subdev *sd, 146554450f59SHans Verkuil struct v4l2_dv_timings *timings) 146654450f59SHans Verkuil { 146754450f59SHans Verkuil int i; 146854450f59SHans Verkuil 1469b44b2e06SPablo Anton for (i = 0; adv76xx_timings[i].bt.width; i++) { 1470b44b2e06SPablo Anton if (v4l2_match_dv_timings(timings, &adv76xx_timings[i], 14714a31a93aSMats Randgaard is_digital_input(sd) ? 250000 : 1000000)) { 1472b44b2e06SPablo Anton *timings = adv76xx_timings[i]; 147354450f59SHans Verkuil break; 147454450f59SHans Verkuil } 147554450f59SHans Verkuil } 147654450f59SHans Verkuil } 147754450f59SHans Verkuil 1478d42010a1SLars-Peter Clausen static unsigned int adv7604_read_hdmi_pixelclock(struct v4l2_subdev *sd) 1479d42010a1SLars-Peter Clausen { 1480d42010a1SLars-Peter Clausen unsigned int freq; 1481d42010a1SLars-Peter Clausen int a, b; 1482d42010a1SLars-Peter Clausen 1483d42010a1SLars-Peter Clausen a = hdmi_read(sd, 0x06); 1484d42010a1SLars-Peter Clausen b = hdmi_read(sd, 0x3b); 1485d42010a1SLars-Peter Clausen if (a < 0 || b < 0) 1486d42010a1SLars-Peter Clausen return 0; 1487d42010a1SLars-Peter Clausen freq = a * 1000000 + ((b & 0x30) >> 4) * 250000; 1488d42010a1SLars-Peter Clausen 1489d42010a1SLars-Peter Clausen if (is_hdmi(sd)) { 1490d42010a1SLars-Peter Clausen /* adjust for deep color mode */ 1491d42010a1SLars-Peter Clausen unsigned bits_per_channel = ((hdmi_read(sd, 0x0b) & 0x60) >> 4) + 8; 1492d42010a1SLars-Peter Clausen 1493d42010a1SLars-Peter Clausen freq = freq * 8 / bits_per_channel; 1494d42010a1SLars-Peter Clausen } 1495d42010a1SLars-Peter Clausen 1496d42010a1SLars-Peter Clausen return freq; 1497d42010a1SLars-Peter Clausen } 1498d42010a1SLars-Peter Clausen 1499d42010a1SLars-Peter Clausen static unsigned int adv7611_read_hdmi_pixelclock(struct v4l2_subdev *sd) 1500d42010a1SLars-Peter Clausen { 1501d42010a1SLars-Peter Clausen int a, b; 1502d42010a1SLars-Peter Clausen 1503d42010a1SLars-Peter Clausen a = hdmi_read(sd, 0x51); 1504d42010a1SLars-Peter Clausen b = hdmi_read(sd, 0x52); 1505d42010a1SLars-Peter Clausen if (a < 0 || b < 0) 1506d42010a1SLars-Peter Clausen return 0; 1507d42010a1SLars-Peter Clausen return ((a << 1) | (b >> 7)) * 1000000 + (b & 0x7f) * 1000000 / 128; 1508d42010a1SLars-Peter Clausen } 1509d42010a1SLars-Peter Clausen 1510b44b2e06SPablo Anton static int adv76xx_query_dv_timings(struct v4l2_subdev *sd, 151154450f59SHans Verkuil struct v4l2_dv_timings *timings) 151254450f59SHans Verkuil { 1513b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 1514b44b2e06SPablo Anton const struct adv76xx_chip_info *info = state->info; 151554450f59SHans Verkuil struct v4l2_bt_timings *bt = &timings->bt; 151654450f59SHans Verkuil struct stdi_readback stdi; 151754450f59SHans Verkuil 151854450f59SHans Verkuil if (!timings) 151954450f59SHans Verkuil return -EINVAL; 152054450f59SHans Verkuil 152154450f59SHans Verkuil memset(timings, 0, sizeof(struct v4l2_dv_timings)); 152254450f59SHans Verkuil 152354450f59SHans Verkuil if (no_signal(sd)) { 15241e0b9156SMartin Bugge state->restart_stdi_once = true; 152554450f59SHans Verkuil v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__); 152654450f59SHans Verkuil return -ENOLINK; 152754450f59SHans Verkuil } 152854450f59SHans Verkuil 152954450f59SHans Verkuil /* read STDI */ 153054450f59SHans Verkuil if (read_stdi(sd, &stdi)) { 153154450f59SHans Verkuil v4l2_dbg(1, debug, sd, "%s: STDI/SSPD not locked\n", __func__); 153254450f59SHans Verkuil return -ENOLINK; 153354450f59SHans Verkuil } 153454450f59SHans Verkuil bt->interlaced = stdi.interlaced ? 153554450f59SHans Verkuil V4L2_DV_INTERLACED : V4L2_DV_PROGRESSIVE; 153654450f59SHans Verkuil 15374a31a93aSMats Randgaard if (is_digital_input(sd)) { 153854450f59SHans Verkuil timings->type = V4L2_DV_BT_656_1120; 153954450f59SHans Verkuil 15405380baafSjean-michel.hautbois@vodalys.com bt->width = hdmi_read16(sd, 0x07, info->linewidth_mask); 15415380baafSjean-michel.hautbois@vodalys.com bt->height = hdmi_read16(sd, 0x09, info->field0_height_mask); 1542d42010a1SLars-Peter Clausen bt->pixelclock = info->read_hdmi_pixelclock(sd); 15435380baafSjean-michel.hautbois@vodalys.com bt->hfrontporch = hdmi_read16(sd, 0x20, info->hfrontporch_mask); 15445380baafSjean-michel.hautbois@vodalys.com bt->hsync = hdmi_read16(sd, 0x22, info->hsync_mask); 15455380baafSjean-michel.hautbois@vodalys.com bt->hbackporch = hdmi_read16(sd, 0x24, info->hbackporch_mask); 15465380baafSjean-michel.hautbois@vodalys.com bt->vfrontporch = hdmi_read16(sd, 0x2a, 15475380baafSjean-michel.hautbois@vodalys.com info->field0_vfrontporch_mask) / 2; 15485380baafSjean-michel.hautbois@vodalys.com bt->vsync = hdmi_read16(sd, 0x2e, info->field0_vsync_mask) / 2; 15495380baafSjean-michel.hautbois@vodalys.com bt->vbackporch = hdmi_read16(sd, 0x32, 15505380baafSjean-michel.hautbois@vodalys.com info->field0_vbackporch_mask) / 2; 155154450f59SHans Verkuil bt->polarities = ((hdmi_read(sd, 0x05) & 0x10) ? V4L2_DV_VSYNC_POS_POL : 0) | 155254450f59SHans Verkuil ((hdmi_read(sd, 0x05) & 0x20) ? V4L2_DV_HSYNC_POS_POL : 0); 155354450f59SHans Verkuil if (bt->interlaced == V4L2_DV_INTERLACED) { 15545380baafSjean-michel.hautbois@vodalys.com bt->height += hdmi_read16(sd, 0x0b, 15555380baafSjean-michel.hautbois@vodalys.com info->field1_height_mask); 15565380baafSjean-michel.hautbois@vodalys.com bt->il_vfrontporch = hdmi_read16(sd, 0x2c, 15575380baafSjean-michel.hautbois@vodalys.com info->field1_vfrontporch_mask) / 2; 15585380baafSjean-michel.hautbois@vodalys.com bt->il_vsync = hdmi_read16(sd, 0x30, 15595380baafSjean-michel.hautbois@vodalys.com info->field1_vsync_mask) / 2; 15605380baafSjean-michel.hautbois@vodalys.com bt->il_vbackporch = hdmi_read16(sd, 0x34, 15615380baafSjean-michel.hautbois@vodalys.com info->field1_vbackporch_mask) / 2; 156254450f59SHans Verkuil } 1563b44b2e06SPablo Anton adv76xx_fill_optional_dv_timings_fields(sd, timings); 156454450f59SHans Verkuil } else { 156554450f59SHans Verkuil /* find format 156680939647SHans Verkuil * Since LCVS values are inaccurate [REF_03, p. 275-276], 156754450f59SHans Verkuil * stdi2dv_timings() is called with lcvs +-1 if the first attempt fails. 156854450f59SHans Verkuil */ 156954450f59SHans Verkuil if (!stdi2dv_timings(sd, &stdi, timings)) 157054450f59SHans Verkuil goto found; 157154450f59SHans Verkuil stdi.lcvs += 1; 157254450f59SHans Verkuil v4l2_dbg(1, debug, sd, "%s: lcvs + 1 = %d\n", __func__, stdi.lcvs); 157354450f59SHans Verkuil if (!stdi2dv_timings(sd, &stdi, timings)) 157454450f59SHans Verkuil goto found; 157554450f59SHans Verkuil stdi.lcvs -= 2; 157654450f59SHans Verkuil v4l2_dbg(1, debug, sd, "%s: lcvs - 1 = %d\n", __func__, stdi.lcvs); 157754450f59SHans Verkuil if (stdi2dv_timings(sd, &stdi, timings)) { 1578cf9afb1dSHans Verkuil /* 1579cf9afb1dSHans Verkuil * The STDI block may measure wrong values, especially 1580cf9afb1dSHans Verkuil * for lcvs and lcf. If the driver can not find any 1581cf9afb1dSHans Verkuil * valid timing, the STDI block is restarted to measure 1582cf9afb1dSHans Verkuil * the video timings again. The function will return an 1583cf9afb1dSHans Verkuil * error, but the restart of STDI will generate a new 1584cf9afb1dSHans Verkuil * STDI interrupt and the format detection process will 1585cf9afb1dSHans Verkuil * restart. 1586cf9afb1dSHans Verkuil */ 1587cf9afb1dSHans Verkuil if (state->restart_stdi_once) { 1588cf9afb1dSHans Verkuil v4l2_dbg(1, debug, sd, "%s: restart STDI\n", __func__); 1589cf9afb1dSHans Verkuil /* TODO restart STDI for Sync Channel 2 */ 1590cf9afb1dSHans Verkuil /* enter one-shot mode */ 159122d97e56SLaurent Pinchart cp_write_clr_set(sd, 0x86, 0x06, 0x00); 1592cf9afb1dSHans Verkuil /* trigger STDI restart */ 159322d97e56SLaurent Pinchart cp_write_clr_set(sd, 0x86, 0x06, 0x04); 1594cf9afb1dSHans Verkuil /* reset to continuous mode */ 159522d97e56SLaurent Pinchart cp_write_clr_set(sd, 0x86, 0x06, 0x02); 1596cf9afb1dSHans Verkuil state->restart_stdi_once = false; 1597cf9afb1dSHans Verkuil return -ENOLINK; 1598cf9afb1dSHans Verkuil } 159954450f59SHans Verkuil v4l2_dbg(1, debug, sd, "%s: format not supported\n", __func__); 160054450f59SHans Verkuil return -ERANGE; 160154450f59SHans Verkuil } 1602cf9afb1dSHans Verkuil state->restart_stdi_once = true; 160354450f59SHans Verkuil } 160454450f59SHans Verkuil found: 160554450f59SHans Verkuil 160654450f59SHans Verkuil if (no_signal(sd)) { 160754450f59SHans Verkuil v4l2_dbg(1, debug, sd, "%s: signal lost during readout\n", __func__); 160854450f59SHans Verkuil memset(timings, 0, sizeof(struct v4l2_dv_timings)); 160954450f59SHans Verkuil return -ENOLINK; 161054450f59SHans Verkuil } 161154450f59SHans Verkuil 16124a31a93aSMats Randgaard if ((is_analog_input(sd) && bt->pixelclock > 170000000) || 16134a31a93aSMats Randgaard (is_digital_input(sd) && bt->pixelclock > 225000000)) { 161454450f59SHans Verkuil v4l2_dbg(1, debug, sd, "%s: pixelclock out of range %d\n", 161554450f59SHans Verkuil __func__, (u32)bt->pixelclock); 161654450f59SHans Verkuil return -ERANGE; 161754450f59SHans Verkuil } 161854450f59SHans Verkuil 161954450f59SHans Verkuil if (debug > 1) 1620b44b2e06SPablo Anton v4l2_print_dv_timings(sd->name, "adv76xx_query_dv_timings: ", 162111d034c8SHans Verkuil timings, true); 162254450f59SHans Verkuil 162354450f59SHans Verkuil return 0; 162454450f59SHans Verkuil } 162554450f59SHans Verkuil 1626b44b2e06SPablo Anton static int adv76xx_s_dv_timings(struct v4l2_subdev *sd, 162754450f59SHans Verkuil struct v4l2_dv_timings *timings) 162854450f59SHans Verkuil { 1629b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 163054450f59SHans Verkuil struct v4l2_bt_timings *bt; 1631ccbd5bc4SHans Verkuil int err; 163254450f59SHans Verkuil 163354450f59SHans Verkuil if (!timings) 163454450f59SHans Verkuil return -EINVAL; 163554450f59SHans Verkuil 1636d48eb48cSMats Randgaard if (v4l2_match_dv_timings(&state->timings, timings, 0)) { 1637d48eb48cSMats Randgaard v4l2_dbg(1, debug, sd, "%s: no change\n", __func__); 1638d48eb48cSMats Randgaard return 0; 1639d48eb48cSMats Randgaard } 1640d48eb48cSMats Randgaard 164154450f59SHans Verkuil bt = &timings->bt; 164254450f59SHans Verkuil 16434a31a93aSMats Randgaard if ((is_analog_input(sd) && bt->pixelclock > 170000000) || 16444a31a93aSMats Randgaard (is_digital_input(sd) && bt->pixelclock > 225000000)) { 164554450f59SHans Verkuil v4l2_dbg(1, debug, sd, "%s: pixelclock out of range %d\n", 164654450f59SHans Verkuil __func__, (u32)bt->pixelclock); 164754450f59SHans Verkuil return -ERANGE; 164854450f59SHans Verkuil } 1649ccbd5bc4SHans Verkuil 1650b44b2e06SPablo Anton adv76xx_fill_optional_dv_timings_fields(sd, timings); 165154450f59SHans Verkuil 165254450f59SHans Verkuil state->timings = *timings; 165354450f59SHans Verkuil 165422d97e56SLaurent Pinchart cp_write_clr_set(sd, 0x91, 0x40, bt->interlaced ? 0x40 : 0x00); 1655ccbd5bc4SHans Verkuil 1656ccbd5bc4SHans Verkuil /* Use prim_mode and vid_std when available */ 1657ccbd5bc4SHans Verkuil err = configure_predefined_video_timings(sd, timings); 1658ccbd5bc4SHans Verkuil if (err) { 1659ccbd5bc4SHans Verkuil /* custom settings when the video format 1660ccbd5bc4SHans Verkuil does not have prim_mode/vid_std */ 1661ccbd5bc4SHans Verkuil configure_custom_video_timings(sd, bt); 1662ccbd5bc4SHans Verkuil } 166354450f59SHans Verkuil 166454450f59SHans Verkuil set_rgb_quantization_range(sd); 166554450f59SHans Verkuil 166654450f59SHans Verkuil if (debug > 1) 1667b44b2e06SPablo Anton v4l2_print_dv_timings(sd->name, "adv76xx_s_dv_timings: ", 166811d034c8SHans Verkuil timings, true); 166954450f59SHans Verkuil return 0; 167054450f59SHans Verkuil } 167154450f59SHans Verkuil 1672b44b2e06SPablo Anton static int adv76xx_g_dv_timings(struct v4l2_subdev *sd, 167354450f59SHans Verkuil struct v4l2_dv_timings *timings) 167454450f59SHans Verkuil { 1675b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 167654450f59SHans Verkuil 167754450f59SHans Verkuil *timings = state->timings; 167854450f59SHans Verkuil return 0; 167954450f59SHans Verkuil } 168054450f59SHans Verkuil 1681d42010a1SLars-Peter Clausen static void adv7604_set_termination(struct v4l2_subdev *sd, bool enable) 1682d42010a1SLars-Peter Clausen { 1683d42010a1SLars-Peter Clausen hdmi_write(sd, 0x01, enable ? 0x00 : 0x78); 1684d42010a1SLars-Peter Clausen } 1685d42010a1SLars-Peter Clausen 1686d42010a1SLars-Peter Clausen static void adv7611_set_termination(struct v4l2_subdev *sd, bool enable) 1687d42010a1SLars-Peter Clausen { 1688d42010a1SLars-Peter Clausen hdmi_write(sd, 0x83, enable ? 0xfe : 0xff); 1689d42010a1SLars-Peter Clausen } 1690d42010a1SLars-Peter Clausen 16916b0d5d34SHans Verkuil static void enable_input(struct v4l2_subdev *sd) 169254450f59SHans Verkuil { 1693b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 16946b0d5d34SHans Verkuil 16954a31a93aSMats Randgaard if (is_analog_input(sd)) { 169654450f59SHans Verkuil io_write(sd, 0x15, 0xb0); /* Disable Tristate of Pins (no audio) */ 16974a31a93aSMats Randgaard } else if (is_digital_input(sd)) { 169822d97e56SLaurent Pinchart hdmi_write_clr_set(sd, 0x00, 0x03, state->selected_input); 1699d42010a1SLars-Peter Clausen state->info->set_termination(sd, true); 170054450f59SHans Verkuil io_write(sd, 0x15, 0xa0); /* Disable Tristate of Pins */ 170122d97e56SLaurent Pinchart hdmi_write_clr_set(sd, 0x1a, 0x10, 0x00); /* Unmute audio */ 17024a31a93aSMats Randgaard } else { 17034a31a93aSMats Randgaard v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n", 17044a31a93aSMats Randgaard __func__, state->selected_input); 170554450f59SHans Verkuil } 170654450f59SHans Verkuil } 170754450f59SHans Verkuil 170854450f59SHans Verkuil static void disable_input(struct v4l2_subdev *sd) 170954450f59SHans Verkuil { 1710b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 1711d42010a1SLars-Peter Clausen 171222d97e56SLaurent Pinchart hdmi_write_clr_set(sd, 0x1a, 0x10, 0x10); /* Mute audio */ 17135474b983SMats Randgaard msleep(16); /* 512 samples with >= 32 kHz sample rate [REF_03, c. 7.16.10] */ 171454450f59SHans Verkuil io_write(sd, 0x15, 0xbe); /* Tristate all outputs from video core */ 1715d42010a1SLars-Peter Clausen state->info->set_termination(sd, false); 171654450f59SHans Verkuil } 171754450f59SHans Verkuil 17186b0d5d34SHans Verkuil static void select_input(struct v4l2_subdev *sd) 171954450f59SHans Verkuil { 1720b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 1721b44b2e06SPablo Anton const struct adv76xx_chip_info *info = state->info; 172254450f59SHans Verkuil 17234a31a93aSMats Randgaard if (is_analog_input(sd)) { 1724b44b2e06SPablo Anton adv76xx_write_reg_seq(sd, info->recommended_settings[0]); 172554450f59SHans Verkuil 172654450f59SHans Verkuil afe_write(sd, 0x00, 0x08); /* power up ADC */ 172754450f59SHans Verkuil afe_write(sd, 0x01, 0x06); /* power up Analog Front End */ 172854450f59SHans Verkuil afe_write(sd, 0xc8, 0x00); /* phase control */ 17294a31a93aSMats Randgaard } else if (is_digital_input(sd)) { 17304a31a93aSMats Randgaard hdmi_write(sd, 0x00, state->selected_input & 0x03); 173154450f59SHans Verkuil 1732b44b2e06SPablo Anton adv76xx_write_reg_seq(sd, info->recommended_settings[1]); 173354450f59SHans Verkuil 1734b44b2e06SPablo Anton if (adv76xx_has_afe(state)) { 173554450f59SHans Verkuil afe_write(sd, 0x00, 0xff); /* power down ADC */ 173654450f59SHans Verkuil afe_write(sd, 0x01, 0xfe); /* power down Analog Front End */ 173754450f59SHans Verkuil afe_write(sd, 0xc8, 0x40); /* phase control */ 1738d42010a1SLars-Peter Clausen } 173954450f59SHans Verkuil 174054450f59SHans Verkuil cp_write(sd, 0x3e, 0x00); /* CP core pre-gain control */ 174154450f59SHans Verkuil cp_write(sd, 0xc3, 0x39); /* CP coast control. Graphics mode */ 174254450f59SHans Verkuil cp_write(sd, 0x40, 0x80); /* CP core pre-gain control. Graphics mode */ 17434a31a93aSMats Randgaard } else { 17444a31a93aSMats Randgaard v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n", 17454a31a93aSMats Randgaard __func__, state->selected_input); 174654450f59SHans Verkuil } 174754450f59SHans Verkuil } 174854450f59SHans Verkuil 1749b44b2e06SPablo Anton static int adv76xx_s_routing(struct v4l2_subdev *sd, 175054450f59SHans Verkuil u32 input, u32 output, u32 config) 175154450f59SHans Verkuil { 1752b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 175354450f59SHans Verkuil 1754ff4f80fdSMats Randgaard v4l2_dbg(2, debug, sd, "%s: input %d, selected input %d", 1755ff4f80fdSMats Randgaard __func__, input, state->selected_input); 1756ff4f80fdSMats Randgaard 1757ff4f80fdSMats Randgaard if (input == state->selected_input) 1758ff4f80fdSMats Randgaard return 0; 175954450f59SHans Verkuil 1760d42010a1SLars-Peter Clausen if (input > state->info->max_port) 1761d42010a1SLars-Peter Clausen return -EINVAL; 1762d42010a1SLars-Peter Clausen 17634a31a93aSMats Randgaard state->selected_input = input; 176454450f59SHans Verkuil 176554450f59SHans Verkuil disable_input(sd); 17666b0d5d34SHans Verkuil select_input(sd); 17676b0d5d34SHans Verkuil enable_input(sd); 176854450f59SHans Verkuil 176948519838SHans Verkuil v4l2_subdev_notify(sd, V4L2_DEVICE_NOTIFY_EVENT, 177048519838SHans Verkuil (void *)&adv76xx_ev_fmt); 177154450f59SHans Verkuil return 0; 177254450f59SHans Verkuil } 177354450f59SHans Verkuil 1774b44b2e06SPablo Anton static int adv76xx_enum_mbus_code(struct v4l2_subdev *sd, 1775f7234138SHans Verkuil struct v4l2_subdev_pad_config *cfg, 1776539b33b0SLaurent Pinchart struct v4l2_subdev_mbus_code_enum *code) 177754450f59SHans Verkuil { 1778b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 177954450f59SHans Verkuil 1780539b33b0SLaurent Pinchart if (code->index >= state->info->nformats) 1781539b33b0SLaurent Pinchart return -EINVAL; 1782539b33b0SLaurent Pinchart 1783539b33b0SLaurent Pinchart code->code = state->info->formats[code->index].code; 1784539b33b0SLaurent Pinchart 1785539b33b0SLaurent Pinchart return 0; 1786539b33b0SLaurent Pinchart } 1787539b33b0SLaurent Pinchart 1788b44b2e06SPablo Anton static void adv76xx_fill_format(struct adv76xx_state *state, 1789539b33b0SLaurent Pinchart struct v4l2_mbus_framefmt *format) 1790539b33b0SLaurent Pinchart { 1791539b33b0SLaurent Pinchart memset(format, 0, sizeof(*format)); 1792539b33b0SLaurent Pinchart 1793539b33b0SLaurent Pinchart format->width = state->timings.bt.width; 1794539b33b0SLaurent Pinchart format->height = state->timings.bt.height; 1795539b33b0SLaurent Pinchart format->field = V4L2_FIELD_NONE; 1796680fee04SHans Verkuil format->colorspace = V4L2_COLORSPACE_SRGB; 1797539b33b0SLaurent Pinchart 1798680fee04SHans Verkuil if (state->timings.bt.flags & V4L2_DV_FL_IS_CE_VIDEO) 1799539b33b0SLaurent Pinchart format->colorspace = (state->timings.bt.height <= 576) ? 180054450f59SHans Verkuil V4L2_COLORSPACE_SMPTE170M : V4L2_COLORSPACE_REC709; 180154450f59SHans Verkuil } 1802539b33b0SLaurent Pinchart 1803539b33b0SLaurent Pinchart /* 1804539b33b0SLaurent Pinchart * Compute the op_ch_sel value required to obtain on the bus the component order 1805539b33b0SLaurent Pinchart * corresponding to the selected format taking into account bus reordering 1806539b33b0SLaurent Pinchart * applied by the board at the output of the device. 1807539b33b0SLaurent Pinchart * 1808539b33b0SLaurent Pinchart * The following table gives the op_ch_value from the format component order 1809539b33b0SLaurent Pinchart * (expressed as op_ch_sel value in column) and the bus reordering (expressed as 1810b44b2e06SPablo Anton * adv76xx_bus_order value in row). 1811539b33b0SLaurent Pinchart * 1812539b33b0SLaurent Pinchart * | GBR(0) GRB(1) BGR(2) RGB(3) BRG(4) RBG(5) 1813539b33b0SLaurent Pinchart * ----------+------------------------------------------------- 1814539b33b0SLaurent Pinchart * RGB (NOP) | GBR GRB BGR RGB BRG RBG 1815539b33b0SLaurent Pinchart * GRB (1-2) | BGR RGB GBR GRB RBG BRG 1816539b33b0SLaurent Pinchart * RBG (2-3) | GRB GBR BRG RBG BGR RGB 1817539b33b0SLaurent Pinchart * BGR (1-3) | RBG BRG RGB BGR GRB GBR 1818539b33b0SLaurent Pinchart * BRG (ROR) | BRG RBG GRB GBR RGB BGR 1819539b33b0SLaurent Pinchart * GBR (ROL) | RGB BGR RBG BRG GBR GRB 1820539b33b0SLaurent Pinchart */ 1821b44b2e06SPablo Anton static unsigned int adv76xx_op_ch_sel(struct adv76xx_state *state) 1822539b33b0SLaurent Pinchart { 1823539b33b0SLaurent Pinchart #define _SEL(a,b,c,d,e,f) { \ 1824b44b2e06SPablo Anton ADV76XX_OP_CH_SEL_##a, ADV76XX_OP_CH_SEL_##b, ADV76XX_OP_CH_SEL_##c, \ 1825b44b2e06SPablo Anton ADV76XX_OP_CH_SEL_##d, ADV76XX_OP_CH_SEL_##e, ADV76XX_OP_CH_SEL_##f } 1826539b33b0SLaurent Pinchart #define _BUS(x) [ADV7604_BUS_ORDER_##x] 1827539b33b0SLaurent Pinchart 1828539b33b0SLaurent Pinchart static const unsigned int op_ch_sel[6][6] = { 1829539b33b0SLaurent Pinchart _BUS(RGB) /* NOP */ = _SEL(GBR, GRB, BGR, RGB, BRG, RBG), 1830539b33b0SLaurent Pinchart _BUS(GRB) /* 1-2 */ = _SEL(BGR, RGB, GBR, GRB, RBG, BRG), 1831539b33b0SLaurent Pinchart _BUS(RBG) /* 2-3 */ = _SEL(GRB, GBR, BRG, RBG, BGR, RGB), 1832539b33b0SLaurent Pinchart _BUS(BGR) /* 1-3 */ = _SEL(RBG, BRG, RGB, BGR, GRB, GBR), 1833539b33b0SLaurent Pinchart _BUS(BRG) /* ROR */ = _SEL(BRG, RBG, GRB, GBR, RGB, BGR), 1834539b33b0SLaurent Pinchart _BUS(GBR) /* ROL */ = _SEL(RGB, BGR, RBG, BRG, GBR, GRB), 1835539b33b0SLaurent Pinchart }; 1836539b33b0SLaurent Pinchart 1837539b33b0SLaurent Pinchart return op_ch_sel[state->pdata.bus_order][state->format->op_ch_sel >> 5]; 1838539b33b0SLaurent Pinchart } 1839539b33b0SLaurent Pinchart 1840b44b2e06SPablo Anton static void adv76xx_setup_format(struct adv76xx_state *state) 1841539b33b0SLaurent Pinchart { 1842539b33b0SLaurent Pinchart struct v4l2_subdev *sd = &state->sd; 1843539b33b0SLaurent Pinchart 184422d97e56SLaurent Pinchart io_write_clr_set(sd, 0x02, 0x02, 1845b44b2e06SPablo Anton state->format->rgb_out ? ADV76XX_RGB_OUT : 0); 1846539b33b0SLaurent Pinchart io_write(sd, 0x03, state->format->op_format_sel | 1847539b33b0SLaurent Pinchart state->pdata.op_format_mode_sel); 1848b44b2e06SPablo Anton io_write_clr_set(sd, 0x04, 0xe0, adv76xx_op_ch_sel(state)); 184922d97e56SLaurent Pinchart io_write_clr_set(sd, 0x05, 0x01, 1850b44b2e06SPablo Anton state->format->swap_cb_cr ? ADV76XX_OP_SWAP_CB_CR : 0); 1851539b33b0SLaurent Pinchart } 1852539b33b0SLaurent Pinchart 1853f7234138SHans Verkuil static int adv76xx_get_format(struct v4l2_subdev *sd, 1854f7234138SHans Verkuil struct v4l2_subdev_pad_config *cfg, 1855539b33b0SLaurent Pinchart struct v4l2_subdev_format *format) 1856539b33b0SLaurent Pinchart { 1857b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 1858539b33b0SLaurent Pinchart 1859539b33b0SLaurent Pinchart if (format->pad != state->source_pad) 1860539b33b0SLaurent Pinchart return -EINVAL; 1861539b33b0SLaurent Pinchart 1862b44b2e06SPablo Anton adv76xx_fill_format(state, &format->format); 1863539b33b0SLaurent Pinchart 1864539b33b0SLaurent Pinchart if (format->which == V4L2_SUBDEV_FORMAT_TRY) { 1865539b33b0SLaurent Pinchart struct v4l2_mbus_framefmt *fmt; 1866539b33b0SLaurent Pinchart 1867f7234138SHans Verkuil fmt = v4l2_subdev_get_try_format(sd, cfg, format->pad); 1868539b33b0SLaurent Pinchart format->format.code = fmt->code; 1869539b33b0SLaurent Pinchart } else { 1870539b33b0SLaurent Pinchart format->format.code = state->format->code; 1871539b33b0SLaurent Pinchart } 1872539b33b0SLaurent Pinchart 1873539b33b0SLaurent Pinchart return 0; 1874539b33b0SLaurent Pinchart } 1875539b33b0SLaurent Pinchart 1876f7234138SHans Verkuil static int adv76xx_set_format(struct v4l2_subdev *sd, 1877f7234138SHans Verkuil struct v4l2_subdev_pad_config *cfg, 1878539b33b0SLaurent Pinchart struct v4l2_subdev_format *format) 1879539b33b0SLaurent Pinchart { 1880b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 1881b44b2e06SPablo Anton const struct adv76xx_format_info *info; 1882539b33b0SLaurent Pinchart 1883539b33b0SLaurent Pinchart if (format->pad != state->source_pad) 1884539b33b0SLaurent Pinchart return -EINVAL; 1885539b33b0SLaurent Pinchart 1886b44b2e06SPablo Anton info = adv76xx_format_info(state, format->format.code); 1887539b33b0SLaurent Pinchart if (info == NULL) 1888b44b2e06SPablo Anton info = adv76xx_format_info(state, MEDIA_BUS_FMT_YUYV8_2X8); 1889539b33b0SLaurent Pinchart 1890b44b2e06SPablo Anton adv76xx_fill_format(state, &format->format); 1891539b33b0SLaurent Pinchart format->format.code = info->code; 1892539b33b0SLaurent Pinchart 1893539b33b0SLaurent Pinchart if (format->which == V4L2_SUBDEV_FORMAT_TRY) { 1894539b33b0SLaurent Pinchart struct v4l2_mbus_framefmt *fmt; 1895539b33b0SLaurent Pinchart 1896f7234138SHans Verkuil fmt = v4l2_subdev_get_try_format(sd, cfg, format->pad); 1897539b33b0SLaurent Pinchart fmt->code = format->format.code; 1898539b33b0SLaurent Pinchart } else { 1899539b33b0SLaurent Pinchart state->format = info; 1900b44b2e06SPablo Anton adv76xx_setup_format(state); 1901539b33b0SLaurent Pinchart } 1902539b33b0SLaurent Pinchart 190354450f59SHans Verkuil return 0; 190454450f59SHans Verkuil } 190554450f59SHans Verkuil 1906b44b2e06SPablo Anton static int adv76xx_isr(struct v4l2_subdev *sd, u32 status, bool *handled) 190754450f59SHans Verkuil { 1908b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 1909b44b2e06SPablo Anton const struct adv76xx_chip_info *info = state->info; 1910f24d229cSMats Randgaard const u8 irq_reg_0x43 = io_read(sd, 0x43); 1911f24d229cSMats Randgaard const u8 irq_reg_0x6b = io_read(sd, 0x6b); 1912f24d229cSMats Randgaard const u8 irq_reg_0x70 = io_read(sd, 0x70); 1913f24d229cSMats Randgaard u8 fmt_change_digital; 1914f24d229cSMats Randgaard u8 fmt_change; 1915f24d229cSMats Randgaard u8 tx_5v; 1916f24d229cSMats Randgaard 1917f24d229cSMats Randgaard if (irq_reg_0x43) 1918f24d229cSMats Randgaard io_write(sd, 0x44, irq_reg_0x43); 1919f24d229cSMats Randgaard if (irq_reg_0x70) 1920f24d229cSMats Randgaard io_write(sd, 0x71, irq_reg_0x70); 1921f24d229cSMats Randgaard if (irq_reg_0x6b) 1922f24d229cSMats Randgaard io_write(sd, 0x6c, irq_reg_0x6b); 192354450f59SHans Verkuil 1924ff4f80fdSMats Randgaard v4l2_dbg(2, debug, sd, "%s: ", __func__); 1925ff4f80fdSMats Randgaard 192654450f59SHans Verkuil /* format change */ 1927f24d229cSMats Randgaard fmt_change = irq_reg_0x43 & 0x98; 1928d42010a1SLars-Peter Clausen fmt_change_digital = is_digital_input(sd) 1929d42010a1SLars-Peter Clausen ? irq_reg_0x6b & info->fmt_change_digital_mask 1930d42010a1SLars-Peter Clausen : 0; 193114d03233SMats Randgaard 193254450f59SHans Verkuil if (fmt_change || fmt_change_digital) { 193354450f59SHans Verkuil v4l2_dbg(1, debug, sd, 193425a64ac9SMats Randgaard "%s: fmt_change = 0x%x, fmt_change_digital = 0x%x\n", 193554450f59SHans Verkuil __func__, fmt_change, fmt_change_digital); 193625a64ac9SMats Randgaard 193748519838SHans Verkuil v4l2_subdev_notify(sd, V4L2_DEVICE_NOTIFY_EVENT, 193848519838SHans Verkuil (void *)&adv76xx_ev_fmt); 193925a64ac9SMats Randgaard 194054450f59SHans Verkuil if (handled) 194154450f59SHans Verkuil *handled = true; 194254450f59SHans Verkuil } 1943f24d229cSMats Randgaard /* HDMI/DVI mode */ 1944f24d229cSMats Randgaard if (irq_reg_0x6b & 0x01) { 1945f24d229cSMats Randgaard v4l2_dbg(1, debug, sd, "%s: irq %s mode\n", __func__, 1946f24d229cSMats Randgaard (io_read(sd, 0x6a) & 0x01) ? "HDMI" : "DVI"); 1947f24d229cSMats Randgaard set_rgb_quantization_range(sd); 1948f24d229cSMats Randgaard if (handled) 1949f24d229cSMats Randgaard *handled = true; 1950f24d229cSMats Randgaard } 1951f24d229cSMats Randgaard 195254450f59SHans Verkuil /* tx 5v detect */ 1953d42010a1SLars-Peter Clausen tx_5v = io_read(sd, 0x70) & info->cable_det_mask; 195454450f59SHans Verkuil if (tx_5v) { 195554450f59SHans Verkuil v4l2_dbg(1, debug, sd, "%s: tx_5v: 0x%x\n", __func__, tx_5v); 195654450f59SHans Verkuil io_write(sd, 0x71, tx_5v); 1957b44b2e06SPablo Anton adv76xx_s_detect_tx_5v_ctrl(sd); 195854450f59SHans Verkuil if (handled) 195954450f59SHans Verkuil *handled = true; 196054450f59SHans Verkuil } 196154450f59SHans Verkuil return 0; 196254450f59SHans Verkuil } 196354450f59SHans Verkuil 1964b44b2e06SPablo Anton static int adv76xx_get_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid) 196554450f59SHans Verkuil { 1966b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 19674a31a93aSMats Randgaard u8 *data = NULL; 196854450f59SHans Verkuil 1969dd9ac11aSHans Verkuil memset(edid->reserved, 0, sizeof(edid->reserved)); 19704a31a93aSMats Randgaard 19714a31a93aSMats Randgaard switch (edid->pad) { 1972b44b2e06SPablo Anton case ADV76XX_PAD_HDMI_PORT_A: 1973c784b1e2SLaurent Pinchart case ADV7604_PAD_HDMI_PORT_B: 1974c784b1e2SLaurent Pinchart case ADV7604_PAD_HDMI_PORT_C: 1975c784b1e2SLaurent Pinchart case ADV7604_PAD_HDMI_PORT_D: 19764a31a93aSMats Randgaard if (state->edid.present & (1 << edid->pad)) 19774a31a93aSMats Randgaard data = state->edid.edid; 19784a31a93aSMats Randgaard break; 19794a31a93aSMats Randgaard default: 19804a31a93aSMats Randgaard return -EINVAL; 19814a31a93aSMats Randgaard } 1982dd9ac11aSHans Verkuil 1983dd9ac11aSHans Verkuil if (edid->start_block == 0 && edid->blocks == 0) { 1984dd9ac11aSHans Verkuil edid->blocks = data ? state->edid.blocks : 0; 1985dd9ac11aSHans Verkuil return 0; 1986dd9ac11aSHans Verkuil } 1987dd9ac11aSHans Verkuil 1988dd9ac11aSHans Verkuil if (data == NULL) 19894a31a93aSMats Randgaard return -ENODATA; 19904a31a93aSMats Randgaard 1991dd9ac11aSHans Verkuil if (edid->start_block >= state->edid.blocks) 1992dd9ac11aSHans Verkuil return -EINVAL; 1993dd9ac11aSHans Verkuil 1994dd9ac11aSHans Verkuil if (edid->start_block + edid->blocks > state->edid.blocks) 1995dd9ac11aSHans Verkuil edid->blocks = state->edid.blocks - edid->start_block; 1996dd9ac11aSHans Verkuil 1997dd9ac11aSHans Verkuil memcpy(edid->edid, data + edid->start_block * 128, edid->blocks * 128); 1998dd9ac11aSHans Verkuil 199954450f59SHans Verkuil return 0; 200054450f59SHans Verkuil } 200154450f59SHans Verkuil 2002dd08beb9SMats Randgaard static int get_edid_spa_location(const u8 *edid) 20033e86aa85SMats Randgaard { 20043e86aa85SMats Randgaard u8 d; 20053e86aa85SMats Randgaard 20063e86aa85SMats Randgaard if ((edid[0x7e] != 1) || 20073e86aa85SMats Randgaard (edid[0x80] != 0x02) || 20083e86aa85SMats Randgaard (edid[0x81] != 0x03)) { 20093e86aa85SMats Randgaard return -1; 20103e86aa85SMats Randgaard } 20113e86aa85SMats Randgaard 20123e86aa85SMats Randgaard /* search Vendor Specific Data Block (tag 3) */ 20133e86aa85SMats Randgaard d = edid[0x82] & 0x7f; 20143e86aa85SMats Randgaard if (d > 4) { 20153e86aa85SMats Randgaard int i = 0x84; 20163e86aa85SMats Randgaard int end = 0x80 + d; 20173e86aa85SMats Randgaard 20183e86aa85SMats Randgaard do { 20193e86aa85SMats Randgaard u8 tag = edid[i] >> 5; 20203e86aa85SMats Randgaard u8 len = edid[i] & 0x1f; 20213e86aa85SMats Randgaard 20223e86aa85SMats Randgaard if ((tag == 3) && (len >= 5)) 20233e86aa85SMats Randgaard return i + 4; 20243e86aa85SMats Randgaard i += len + 1; 20253e86aa85SMats Randgaard } while (i < end); 20263e86aa85SMats Randgaard } 20273e86aa85SMats Randgaard return -1; 20283e86aa85SMats Randgaard } 20293e86aa85SMats Randgaard 2030b44b2e06SPablo Anton static int adv76xx_set_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid) 203154450f59SHans Verkuil { 2032b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 2033b44b2e06SPablo Anton const struct adv76xx_chip_info *info = state->info; 2034dd08beb9SMats Randgaard int spa_loc; 203554450f59SHans Verkuil int err; 2036dd08beb9SMats Randgaard int i; 203754450f59SHans Verkuil 2038dd9ac11aSHans Verkuil memset(edid->reserved, 0, sizeof(edid->reserved)); 2039dd9ac11aSHans Verkuil 2040c784b1e2SLaurent Pinchart if (edid->pad > ADV7604_PAD_HDMI_PORT_D) 204154450f59SHans Verkuil return -EINVAL; 204254450f59SHans Verkuil if (edid->start_block != 0) 204354450f59SHans Verkuil return -EINVAL; 204454450f59SHans Verkuil if (edid->blocks == 0) { 20453e86aa85SMats Randgaard /* Disable hotplug and I2C access to EDID RAM from DDC port */ 20464a31a93aSMats Randgaard state->edid.present &= ~(1 << edid->pad); 2047b44b2e06SPablo Anton adv76xx_set_hpd(state, state->edid.present); 204822d97e56SLaurent Pinchart rep_write_clr_set(sd, info->edid_enable_reg, 0x0f, state->edid.present); 20493e86aa85SMats Randgaard 205054450f59SHans Verkuil /* Fall back to a 16:9 aspect ratio */ 205154450f59SHans Verkuil state->aspect_ratio.numerator = 16; 205254450f59SHans Verkuil state->aspect_ratio.denominator = 9; 20533e86aa85SMats Randgaard 20543e86aa85SMats Randgaard if (!state->edid.present) 20553e86aa85SMats Randgaard state->edid.blocks = 0; 20563e86aa85SMats Randgaard 20573e86aa85SMats Randgaard v4l2_dbg(2, debug, sd, "%s: clear EDID pad %d, edid.present = 0x%x\n", 20583e86aa85SMats Randgaard __func__, edid->pad, state->edid.present); 205954450f59SHans Verkuil return 0; 206054450f59SHans Verkuil } 20614a31a93aSMats Randgaard if (edid->blocks > 2) { 20624a31a93aSMats Randgaard edid->blocks = 2; 206354450f59SHans Verkuil return -E2BIG; 20644a31a93aSMats Randgaard } 20654a31a93aSMats Randgaard 2066dd08beb9SMats Randgaard v4l2_dbg(2, debug, sd, "%s: write EDID pad %d, edid.present = 0x%x\n", 2067dd08beb9SMats Randgaard __func__, edid->pad, state->edid.present); 2068dd08beb9SMats Randgaard 20693e86aa85SMats Randgaard /* Disable hotplug and I2C access to EDID RAM from DDC port */ 20704a31a93aSMats Randgaard cancel_delayed_work_sync(&state->delayed_work_enable_hotplug); 2071b44b2e06SPablo Anton adv76xx_set_hpd(state, 0); 207222d97e56SLaurent Pinchart rep_write_clr_set(sd, info->edid_enable_reg, 0x0f, 0x00); 20733e86aa85SMats Randgaard 2074dd08beb9SMats Randgaard spa_loc = get_edid_spa_location(edid->edid); 2075dd08beb9SMats Randgaard if (spa_loc < 0) 2076dd08beb9SMats Randgaard spa_loc = 0xc0; /* Default value [REF_02, p. 116] */ 2077dd08beb9SMats Randgaard 20783e86aa85SMats Randgaard switch (edid->pad) { 2079b44b2e06SPablo Anton case ADV76XX_PAD_HDMI_PORT_A: 2080dd08beb9SMats Randgaard state->spa_port_a[0] = edid->edid[spa_loc]; 2081dd08beb9SMats Randgaard state->spa_port_a[1] = edid->edid[spa_loc + 1]; 20823e86aa85SMats Randgaard break; 2083c784b1e2SLaurent Pinchart case ADV7604_PAD_HDMI_PORT_B: 2084dd08beb9SMats Randgaard rep_write(sd, 0x70, edid->edid[spa_loc]); 2085dd08beb9SMats Randgaard rep_write(sd, 0x71, edid->edid[spa_loc + 1]); 20863e86aa85SMats Randgaard break; 2087c784b1e2SLaurent Pinchart case ADV7604_PAD_HDMI_PORT_C: 2088dd08beb9SMats Randgaard rep_write(sd, 0x72, edid->edid[spa_loc]); 2089dd08beb9SMats Randgaard rep_write(sd, 0x73, edid->edid[spa_loc + 1]); 20903e86aa85SMats Randgaard break; 2091c784b1e2SLaurent Pinchart case ADV7604_PAD_HDMI_PORT_D: 2092dd08beb9SMats Randgaard rep_write(sd, 0x74, edid->edid[spa_loc]); 2093dd08beb9SMats Randgaard rep_write(sd, 0x75, edid->edid[spa_loc + 1]); 20943e86aa85SMats Randgaard break; 2095dd08beb9SMats Randgaard default: 2096dd08beb9SMats Randgaard return -EINVAL; 20973e86aa85SMats Randgaard } 2098d42010a1SLars-Peter Clausen 2099d42010a1SLars-Peter Clausen if (info->type == ADV7604) { 2100dd08beb9SMats Randgaard rep_write(sd, 0x76, spa_loc & 0xff); 210122d97e56SLaurent Pinchart rep_write_clr_set(sd, 0x77, 0x40, (spa_loc & 0x100) >> 2); 2102d42010a1SLars-Peter Clausen } else { 2103d42010a1SLars-Peter Clausen /* FIXME: Where is the SPA location LSB register ? */ 210422d97e56SLaurent Pinchart rep_write_clr_set(sd, 0x71, 0x01, (spa_loc & 0x100) >> 8); 2105d42010a1SLars-Peter Clausen } 21063e86aa85SMats Randgaard 2107dd08beb9SMats Randgaard edid->edid[spa_loc] = state->spa_port_a[0]; 2108dd08beb9SMats Randgaard edid->edid[spa_loc + 1] = state->spa_port_a[1]; 21094a31a93aSMats Randgaard 21104a31a93aSMats Randgaard memcpy(state->edid.edid, edid->edid, 128 * edid->blocks); 21114a31a93aSMats Randgaard state->edid.blocks = edid->blocks; 211254450f59SHans Verkuil state->aspect_ratio = v4l2_calc_aspect_ratio(edid->edid[0x15], 211354450f59SHans Verkuil edid->edid[0x16]); 21143e86aa85SMats Randgaard state->edid.present |= 1 << edid->pad; 21154a31a93aSMats Randgaard 21164a31a93aSMats Randgaard err = edid_write_block(sd, 128 * edid->blocks, state->edid.edid); 21174a31a93aSMats Randgaard if (err < 0) { 21183e86aa85SMats Randgaard v4l2_err(sd, "error %d writing edid pad %d\n", err, edid->pad); 211954450f59SHans Verkuil return err; 212054450f59SHans Verkuil } 212154450f59SHans Verkuil 2122b44b2e06SPablo Anton /* adv76xx calculates the checksums and enables I2C access to internal 2123dd08beb9SMats Randgaard EDID RAM from DDC port. */ 212422d97e56SLaurent Pinchart rep_write_clr_set(sd, info->edid_enable_reg, 0x0f, state->edid.present); 2125dd08beb9SMats Randgaard 2126dd08beb9SMats Randgaard for (i = 0; i < 1000; i++) { 2127d42010a1SLars-Peter Clausen if (rep_read(sd, info->edid_status_reg) & state->edid.present) 2128dd08beb9SMats Randgaard break; 2129dd08beb9SMats Randgaard mdelay(1); 2130dd08beb9SMats Randgaard } 2131dd08beb9SMats Randgaard if (i == 1000) { 2132dd08beb9SMats Randgaard v4l2_err(sd, "error enabling edid (0x%x)\n", state->edid.present); 2133dd08beb9SMats Randgaard return -EIO; 2134dd08beb9SMats Randgaard } 2135dd08beb9SMats Randgaard 21364a31a93aSMats Randgaard /* enable hotplug after 100 ms */ 21374a31a93aSMats Randgaard queue_delayed_work(state->work_queues, 21384a31a93aSMats Randgaard &state->delayed_work_enable_hotplug, HZ / 10); 21394a31a93aSMats Randgaard return 0; 21404a31a93aSMats Randgaard } 21414a31a93aSMats Randgaard 214254450f59SHans Verkuil /*********** avi info frame CEA-861-E **************/ 214354450f59SHans Verkuil 2144516613c1SHans Verkuil static const struct adv76xx_cfg_read_infoframe adv76xx_cri[] = { 2145516613c1SHans Verkuil { "AVI", 0x01, 0xe0, 0x00 }, 2146516613c1SHans Verkuil { "Audio", 0x02, 0xe3, 0x1c }, 2147516613c1SHans Verkuil { "SDP", 0x04, 0xe6, 0x2a }, 2148516613c1SHans Verkuil { "Vendor", 0x10, 0xec, 0x54 } 2149516613c1SHans Verkuil }; 2150516613c1SHans Verkuil 2151516613c1SHans Verkuil static int adv76xx_read_infoframe(struct v4l2_subdev *sd, int index, 2152516613c1SHans Verkuil union hdmi_infoframe *frame) 2153516613c1SHans Verkuil { 2154516613c1SHans Verkuil uint8_t buffer[32]; 2155516613c1SHans Verkuil u8 len; 2156516613c1SHans Verkuil int i; 2157516613c1SHans Verkuil 2158516613c1SHans Verkuil if (!(io_read(sd, 0x60) & adv76xx_cri[index].present_mask)) { 2159516613c1SHans Verkuil v4l2_info(sd, "%s infoframe not received\n", 2160516613c1SHans Verkuil adv76xx_cri[index].desc); 2161516613c1SHans Verkuil return -ENOENT; 2162516613c1SHans Verkuil } 2163516613c1SHans Verkuil 2164516613c1SHans Verkuil for (i = 0; i < 3; i++) 2165516613c1SHans Verkuil buffer[i] = infoframe_read(sd, 2166516613c1SHans Verkuil adv76xx_cri[index].head_addr + i); 2167516613c1SHans Verkuil 2168516613c1SHans Verkuil len = buffer[2] + 1; 2169516613c1SHans Verkuil 2170516613c1SHans Verkuil if (len + 3 > sizeof(buffer)) { 2171516613c1SHans Verkuil v4l2_err(sd, "%s: invalid %s infoframe length %d\n", __func__, 2172516613c1SHans Verkuil adv76xx_cri[index].desc, len); 2173516613c1SHans Verkuil return -ENOENT; 2174516613c1SHans Verkuil } 2175516613c1SHans Verkuil 2176516613c1SHans Verkuil for (i = 0; i < len; i++) 2177516613c1SHans Verkuil buffer[i + 3] = infoframe_read(sd, 2178516613c1SHans Verkuil adv76xx_cri[index].payload_addr + i); 2179516613c1SHans Verkuil 2180516613c1SHans Verkuil if (hdmi_infoframe_unpack(frame, buffer) < 0) { 2181516613c1SHans Verkuil v4l2_err(sd, "%s: unpack of %s infoframe failed\n", __func__, 2182516613c1SHans Verkuil adv76xx_cri[index].desc); 2183516613c1SHans Verkuil return -ENOENT; 2184516613c1SHans Verkuil } 2185516613c1SHans Verkuil return 0; 2186516613c1SHans Verkuil } 2187516613c1SHans Verkuil 2188516613c1SHans Verkuil static void adv76xx_log_infoframes(struct v4l2_subdev *sd) 218954450f59SHans Verkuil { 219054450f59SHans Verkuil int i; 219154450f59SHans Verkuil 2192bb88f325SMartin Bugge if (!is_hdmi(sd)) { 2193516613c1SHans Verkuil v4l2_info(sd, "receive DVI-D signal, no infoframes\n"); 219454450f59SHans Verkuil return; 219554450f59SHans Verkuil } 219654450f59SHans Verkuil 2197516613c1SHans Verkuil for (i = 0; i < ARRAY_SIZE(adv76xx_cri); i++) { 2198516613c1SHans Verkuil union hdmi_infoframe frame; 2199516613c1SHans Verkuil struct i2c_client *client = v4l2_get_subdevdata(sd); 220054450f59SHans Verkuil 2201516613c1SHans Verkuil if (adv76xx_read_infoframe(sd, i, &frame)) 220254450f59SHans Verkuil return; 2203516613c1SHans Verkuil hdmi_infoframe_log(KERN_INFO, &client->dev, &frame); 2204516613c1SHans Verkuil } 220554450f59SHans Verkuil } 220654450f59SHans Verkuil 2207b44b2e06SPablo Anton static int adv76xx_log_status(struct v4l2_subdev *sd) 220854450f59SHans Verkuil { 2209b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 2210b44b2e06SPablo Anton const struct adv76xx_chip_info *info = state->info; 221154450f59SHans Verkuil struct v4l2_dv_timings timings; 221254450f59SHans Verkuil struct stdi_readback stdi; 221354450f59SHans Verkuil u8 reg_io_0x02 = io_read(sd, 0x02); 22144a2ccdd2SLaurent Pinchart u8 edid_enabled; 22154a2ccdd2SLaurent Pinchart u8 cable_det; 221654450f59SHans Verkuil 2217f216ccb3SLars-Peter Clausen static const char * const csc_coeff_sel_rb[16] = { 221854450f59SHans Verkuil "bypassed", "YPbPr601 -> RGB", "reserved", "YPbPr709 -> RGB", 221954450f59SHans Verkuil "reserved", "RGB -> YPbPr601", "reserved", "RGB -> YPbPr709", 222054450f59SHans Verkuil "reserved", "YPbPr709 -> YPbPr601", "YPbPr601 -> YPbPr709", 222154450f59SHans Verkuil "reserved", "reserved", "reserved", "reserved", "manual" 222254450f59SHans Verkuil }; 2223f216ccb3SLars-Peter Clausen static const char * const input_color_space_txt[16] = { 222454450f59SHans Verkuil "RGB limited range (16-235)", "RGB full range (0-255)", 222554450f59SHans Verkuil "YCbCr Bt.601 (16-235)", "YCbCr Bt.709 (16-235)", 22269833239eSMats Randgaard "xvYCC Bt.601", "xvYCC Bt.709", 222754450f59SHans Verkuil "YCbCr Bt.601 (0-255)", "YCbCr Bt.709 (0-255)", 222854450f59SHans Verkuil "invalid", "invalid", "invalid", "invalid", "invalid", 222954450f59SHans Verkuil "invalid", "invalid", "automatic" 223054450f59SHans Verkuil }; 22317a5d99e7SHans Verkuil static const char * const hdmi_color_space_txt[16] = { 22327a5d99e7SHans Verkuil "RGB limited range (16-235)", "RGB full range (0-255)", 22337a5d99e7SHans Verkuil "YCbCr Bt.601 (16-235)", "YCbCr Bt.709 (16-235)", 22347a5d99e7SHans Verkuil "xvYCC Bt.601", "xvYCC Bt.709", 22357a5d99e7SHans Verkuil "YCbCr Bt.601 (0-255)", "YCbCr Bt.709 (0-255)", 22367a5d99e7SHans Verkuil "sYCC", "Adobe YCC 601", "AdobeRGB", "invalid", "invalid", 22377a5d99e7SHans Verkuil "invalid", "invalid", "invalid" 22387a5d99e7SHans Verkuil }; 2239f216ccb3SLars-Peter Clausen static const char * const rgb_quantization_range_txt[] = { 224054450f59SHans Verkuil "Automatic", 224154450f59SHans Verkuil "RGB limited range (16-235)", 224254450f59SHans Verkuil "RGB full range (0-255)", 224354450f59SHans Verkuil }; 2244f216ccb3SLars-Peter Clausen static const char * const deep_color_mode_txt[4] = { 2245bb88f325SMartin Bugge "8-bits per channel", 2246bb88f325SMartin Bugge "10-bits per channel", 2247bb88f325SMartin Bugge "12-bits per channel", 2248bb88f325SMartin Bugge "16-bits per channel (not supported)" 2249bb88f325SMartin Bugge }; 225054450f59SHans Verkuil 225154450f59SHans Verkuil v4l2_info(sd, "-----Chip status-----\n"); 225254450f59SHans Verkuil v4l2_info(sd, "Chip power: %s\n", no_power(sd) ? "off" : "on"); 2253d42010a1SLars-Peter Clausen edid_enabled = rep_read(sd, info->edid_status_reg); 22544a31a93aSMats Randgaard v4l2_info(sd, "EDID enabled port A: %s, B: %s, C: %s, D: %s\n", 22554a2ccdd2SLaurent Pinchart ((edid_enabled & 0x01) ? "Yes" : "No"), 22564a2ccdd2SLaurent Pinchart ((edid_enabled & 0x02) ? "Yes" : "No"), 22574a2ccdd2SLaurent Pinchart ((edid_enabled & 0x04) ? "Yes" : "No"), 22584a2ccdd2SLaurent Pinchart ((edid_enabled & 0x08) ? "Yes" : "No")); 225954450f59SHans Verkuil v4l2_info(sd, "CEC: %s\n", !!(cec_read(sd, 0x2a) & 0x01) ? 226054450f59SHans Verkuil "enabled" : "disabled"); 226154450f59SHans Verkuil 226254450f59SHans Verkuil v4l2_info(sd, "-----Signal status-----\n"); 2263d42010a1SLars-Peter Clausen cable_det = info->read_cable_det(sd); 22644a31a93aSMats Randgaard v4l2_info(sd, "Cable detected (+5V power) port A: %s, B: %s, C: %s, D: %s\n", 2265d42010a1SLars-Peter Clausen ((cable_det & 0x01) ? "Yes" : "No"), 2266d42010a1SLars-Peter Clausen ((cable_det & 0x02) ? "Yes" : "No"), 22674a2ccdd2SLaurent Pinchart ((cable_det & 0x04) ? "Yes" : "No"), 2268d42010a1SLars-Peter Clausen ((cable_det & 0x08) ? "Yes" : "No")); 226954450f59SHans Verkuil v4l2_info(sd, "TMDS signal detected: %s\n", 227054450f59SHans Verkuil no_signal_tmds(sd) ? "false" : "true"); 227154450f59SHans Verkuil v4l2_info(sd, "TMDS signal locked: %s\n", 227254450f59SHans Verkuil no_lock_tmds(sd) ? "false" : "true"); 227354450f59SHans Verkuil v4l2_info(sd, "SSPD locked: %s\n", no_lock_sspd(sd) ? "false" : "true"); 227454450f59SHans Verkuil v4l2_info(sd, "STDI locked: %s\n", no_lock_stdi(sd) ? "false" : "true"); 227554450f59SHans Verkuil v4l2_info(sd, "CP locked: %s\n", no_lock_cp(sd) ? "false" : "true"); 227654450f59SHans Verkuil v4l2_info(sd, "CP free run: %s\n", 227758514625Sjean-michel.hautbois@vodalys.com (in_free_run(sd)) ? "on" : "off"); 2278ccbd5bc4SHans Verkuil v4l2_info(sd, "Prim-mode = 0x%x, video std = 0x%x, v_freq = 0x%x\n", 2279ccbd5bc4SHans Verkuil io_read(sd, 0x01) & 0x0f, io_read(sd, 0x00) & 0x3f, 2280ccbd5bc4SHans Verkuil (io_read(sd, 0x01) & 0x70) >> 4); 228154450f59SHans Verkuil 228254450f59SHans Verkuil v4l2_info(sd, "-----Video Timings-----\n"); 228354450f59SHans Verkuil if (read_stdi(sd, &stdi)) 228454450f59SHans Verkuil v4l2_info(sd, "STDI: not locked\n"); 228554450f59SHans Verkuil else 228654450f59SHans Verkuil v4l2_info(sd, "STDI: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %s, %chsync, %cvsync\n", 228754450f59SHans Verkuil stdi.lcf, stdi.bl, stdi.lcvs, 228854450f59SHans Verkuil stdi.interlaced ? "interlaced" : "progressive", 228954450f59SHans Verkuil stdi.hs_pol, stdi.vs_pol); 2290b44b2e06SPablo Anton if (adv76xx_query_dv_timings(sd, &timings)) 229154450f59SHans Verkuil v4l2_info(sd, "No video detected\n"); 229254450f59SHans Verkuil else 229311d034c8SHans Verkuil v4l2_print_dv_timings(sd->name, "Detected format: ", 229411d034c8SHans Verkuil &timings, true); 229511d034c8SHans Verkuil v4l2_print_dv_timings(sd->name, "Configured format: ", 229611d034c8SHans Verkuil &state->timings, true); 229754450f59SHans Verkuil 229876eb2d30SMats Randgaard if (no_signal(sd)) 229976eb2d30SMats Randgaard return 0; 230076eb2d30SMats Randgaard 230154450f59SHans Verkuil v4l2_info(sd, "-----Color space-----\n"); 230254450f59SHans Verkuil v4l2_info(sd, "RGB quantization range ctrl: %s\n", 230354450f59SHans Verkuil rgb_quantization_range_txt[state->rgb_quantization_range]); 230454450f59SHans Verkuil v4l2_info(sd, "Input color space: %s\n", 230554450f59SHans Verkuil input_color_space_txt[reg_io_0x02 >> 4]); 23067a5d99e7SHans Verkuil v4l2_info(sd, "Output color space: %s %s, saturator %s, alt-gamma %s\n", 230754450f59SHans Verkuil (reg_io_0x02 & 0x02) ? "RGB" : "YCbCr", 230854450f59SHans Verkuil (reg_io_0x02 & 0x04) ? "(16-235)" : "(0-255)", 23095dd7d88aSHans Verkuil (((reg_io_0x02 >> 2) & 0x01) ^ (reg_io_0x02 & 0x01)) ? 23107a5d99e7SHans Verkuil "enabled" : "disabled", 23117a5d99e7SHans Verkuil (reg_io_0x02 & 0x08) ? "enabled" : "disabled"); 231254450f59SHans Verkuil v4l2_info(sd, "Color space conversion: %s\n", 231380f4944eSjean-michel.hautbois@vodalys.com csc_coeff_sel_rb[cp_read(sd, info->cp_csc) >> 4]); 231454450f59SHans Verkuil 23154a31a93aSMats Randgaard if (!is_digital_input(sd)) 231676eb2d30SMats Randgaard return 0; 231776eb2d30SMats Randgaard 231876eb2d30SMats Randgaard v4l2_info(sd, "-----%s status-----\n", is_hdmi(sd) ? "HDMI" : "DVI-D"); 23194a31a93aSMats Randgaard v4l2_info(sd, "Digital video port selected: %c\n", 23204a31a93aSMats Randgaard (hdmi_read(sd, 0x00) & 0x03) + 'A'); 23214a31a93aSMats Randgaard v4l2_info(sd, "HDCP encrypted content: %s\n", 23224a31a93aSMats Randgaard (hdmi_read(sd, 0x05) & 0x40) ? "true" : "false"); 232376eb2d30SMats Randgaard v4l2_info(sd, "HDCP keys read: %s%s\n", 232476eb2d30SMats Randgaard (hdmi_read(sd, 0x04) & 0x20) ? "yes" : "no", 232576eb2d30SMats Randgaard (hdmi_read(sd, 0x04) & 0x10) ? "ERROR" : ""); 232677639ff2SHans Verkuil if (is_hdmi(sd)) { 232776eb2d30SMats Randgaard bool audio_pll_locked = hdmi_read(sd, 0x04) & 0x01; 232876eb2d30SMats Randgaard bool audio_sample_packet_detect = hdmi_read(sd, 0x18) & 0x01; 232976eb2d30SMats Randgaard bool audio_mute = io_read(sd, 0x65) & 0x40; 233076eb2d30SMats Randgaard 233176eb2d30SMats Randgaard v4l2_info(sd, "Audio: pll %s, samples %s, %s\n", 233276eb2d30SMats Randgaard audio_pll_locked ? "locked" : "not locked", 233376eb2d30SMats Randgaard audio_sample_packet_detect ? "detected" : "not detected", 233476eb2d30SMats Randgaard audio_mute ? "muted" : "enabled"); 233576eb2d30SMats Randgaard if (audio_pll_locked && audio_sample_packet_detect) { 233676eb2d30SMats Randgaard v4l2_info(sd, "Audio format: %s\n", 233776eb2d30SMats Randgaard (hdmi_read(sd, 0x07) & 0x20) ? "multi-channel" : "stereo"); 233876eb2d30SMats Randgaard } 233976eb2d30SMats Randgaard v4l2_info(sd, "Audio CTS: %u\n", (hdmi_read(sd, 0x5b) << 12) + 234076eb2d30SMats Randgaard (hdmi_read(sd, 0x5c) << 8) + 234176eb2d30SMats Randgaard (hdmi_read(sd, 0x5d) & 0xf0)); 234276eb2d30SMats Randgaard v4l2_info(sd, "Audio N: %u\n", ((hdmi_read(sd, 0x5d) & 0x0f) << 16) + 234376eb2d30SMats Randgaard (hdmi_read(sd, 0x5e) << 8) + 234476eb2d30SMats Randgaard hdmi_read(sd, 0x5f)); 234576eb2d30SMats Randgaard v4l2_info(sd, "AV Mute: %s\n", (hdmi_read(sd, 0x04) & 0x40) ? "on" : "off"); 234676eb2d30SMats Randgaard 234776eb2d30SMats Randgaard v4l2_info(sd, "Deep color mode: %s\n", deep_color_mode_txt[(hdmi_read(sd, 0x0b) & 0x60) >> 5]); 23487a5d99e7SHans Verkuil v4l2_info(sd, "HDMI colorspace: %s\n", hdmi_color_space_txt[hdmi_read(sd, 0x53) & 0xf]); 234976eb2d30SMats Randgaard 2350516613c1SHans Verkuil adv76xx_log_infoframes(sd); 235154450f59SHans Verkuil } 235254450f59SHans Verkuil 235354450f59SHans Verkuil return 0; 235454450f59SHans Verkuil } 235554450f59SHans Verkuil 235654450f59SHans Verkuil /* ----------------------------------------------------------------------- */ 235754450f59SHans Verkuil 2358b44b2e06SPablo Anton static const struct v4l2_ctrl_ops adv76xx_ctrl_ops = { 2359b44b2e06SPablo Anton .s_ctrl = adv76xx_s_ctrl, 236054450f59SHans Verkuil }; 236154450f59SHans Verkuil 2362b44b2e06SPablo Anton static const struct v4l2_subdev_core_ops adv76xx_core_ops = { 2363b44b2e06SPablo Anton .log_status = adv76xx_log_status, 2364b44b2e06SPablo Anton .interrupt_service_routine = adv76xx_isr, 236554450f59SHans Verkuil #ifdef CONFIG_VIDEO_ADV_DEBUG 2366b44b2e06SPablo Anton .g_register = adv76xx_g_register, 2367b44b2e06SPablo Anton .s_register = adv76xx_s_register, 236854450f59SHans Verkuil #endif 236954450f59SHans Verkuil }; 237054450f59SHans Verkuil 2371b44b2e06SPablo Anton static const struct v4l2_subdev_video_ops adv76xx_video_ops = { 2372b44b2e06SPablo Anton .s_routing = adv76xx_s_routing, 2373b44b2e06SPablo Anton .g_input_status = adv76xx_g_input_status, 2374b44b2e06SPablo Anton .s_dv_timings = adv76xx_s_dv_timings, 2375b44b2e06SPablo Anton .g_dv_timings = adv76xx_g_dv_timings, 2376b44b2e06SPablo Anton .query_dv_timings = adv76xx_query_dv_timings, 237754450f59SHans Verkuil }; 237854450f59SHans Verkuil 2379b44b2e06SPablo Anton static const struct v4l2_subdev_pad_ops adv76xx_pad_ops = { 2380b44b2e06SPablo Anton .enum_mbus_code = adv76xx_enum_mbus_code, 2381b44b2e06SPablo Anton .get_fmt = adv76xx_get_format, 2382b44b2e06SPablo Anton .set_fmt = adv76xx_set_format, 2383b44b2e06SPablo Anton .get_edid = adv76xx_get_edid, 2384b44b2e06SPablo Anton .set_edid = adv76xx_set_edid, 2385b44b2e06SPablo Anton .dv_timings_cap = adv76xx_dv_timings_cap, 2386b44b2e06SPablo Anton .enum_dv_timings = adv76xx_enum_dv_timings, 238754450f59SHans Verkuil }; 238854450f59SHans Verkuil 2389b44b2e06SPablo Anton static const struct v4l2_subdev_ops adv76xx_ops = { 2390b44b2e06SPablo Anton .core = &adv76xx_core_ops, 2391b44b2e06SPablo Anton .video = &adv76xx_video_ops, 2392b44b2e06SPablo Anton .pad = &adv76xx_pad_ops, 239354450f59SHans Verkuil }; 239454450f59SHans Verkuil 239554450f59SHans Verkuil /* -------------------------- custom ctrls ---------------------------------- */ 239654450f59SHans Verkuil 239754450f59SHans Verkuil static const struct v4l2_ctrl_config adv7604_ctrl_analog_sampling_phase = { 2398b44b2e06SPablo Anton .ops = &adv76xx_ctrl_ops, 239954450f59SHans Verkuil .id = V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE, 240054450f59SHans Verkuil .name = "Analog Sampling Phase", 240154450f59SHans Verkuil .type = V4L2_CTRL_TYPE_INTEGER, 240254450f59SHans Verkuil .min = 0, 240354450f59SHans Verkuil .max = 0x1f, 240454450f59SHans Verkuil .step = 1, 240554450f59SHans Verkuil .def = 0, 240654450f59SHans Verkuil }; 240754450f59SHans Verkuil 2408b44b2e06SPablo Anton static const struct v4l2_ctrl_config adv76xx_ctrl_free_run_color_manual = { 2409b44b2e06SPablo Anton .ops = &adv76xx_ctrl_ops, 241054450f59SHans Verkuil .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL, 241154450f59SHans Verkuil .name = "Free Running Color, Manual", 241254450f59SHans Verkuil .type = V4L2_CTRL_TYPE_BOOLEAN, 241354450f59SHans Verkuil .min = false, 241454450f59SHans Verkuil .max = true, 241554450f59SHans Verkuil .step = 1, 241654450f59SHans Verkuil .def = false, 241754450f59SHans Verkuil }; 241854450f59SHans Verkuil 2419b44b2e06SPablo Anton static const struct v4l2_ctrl_config adv76xx_ctrl_free_run_color = { 2420b44b2e06SPablo Anton .ops = &adv76xx_ctrl_ops, 242154450f59SHans Verkuil .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR, 242254450f59SHans Verkuil .name = "Free Running Color", 242354450f59SHans Verkuil .type = V4L2_CTRL_TYPE_INTEGER, 242454450f59SHans Verkuil .min = 0x0, 242554450f59SHans Verkuil .max = 0xffffff, 242654450f59SHans Verkuil .step = 0x1, 242754450f59SHans Verkuil .def = 0x0, 242854450f59SHans Verkuil }; 242954450f59SHans Verkuil 243054450f59SHans Verkuil /* ----------------------------------------------------------------------- */ 243154450f59SHans Verkuil 2432b44b2e06SPablo Anton static int adv76xx_core_init(struct v4l2_subdev *sd) 243354450f59SHans Verkuil { 2434b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 2435b44b2e06SPablo Anton const struct adv76xx_chip_info *info = state->info; 2436b44b2e06SPablo Anton struct adv76xx_platform_data *pdata = &state->pdata; 243754450f59SHans Verkuil 243854450f59SHans Verkuil hdmi_write(sd, 0x48, 243954450f59SHans Verkuil (pdata->disable_pwrdnb ? 0x80 : 0) | 244054450f59SHans Verkuil (pdata->disable_cable_det_rst ? 0x40 : 0)); 244154450f59SHans Verkuil 244254450f59SHans Verkuil disable_input(sd); 244354450f59SHans Verkuil 24445ef54b59SLaurent Pinchart if (pdata->default_input >= 0 && 24455ef54b59SLaurent Pinchart pdata->default_input < state->source_pad) { 24465ef54b59SLaurent Pinchart state->selected_input = pdata->default_input; 24475ef54b59SLaurent Pinchart select_input(sd); 24485ef54b59SLaurent Pinchart enable_input(sd); 24495ef54b59SLaurent Pinchart } 24505ef54b59SLaurent Pinchart 245154450f59SHans Verkuil /* power */ 245254450f59SHans Verkuil io_write(sd, 0x0c, 0x42); /* Power up part and power down VDP */ 245354450f59SHans Verkuil io_write(sd, 0x0b, 0x44); /* Power down ESDP block */ 245454450f59SHans Verkuil cp_write(sd, 0xcf, 0x01); /* Power down macrovision */ 245554450f59SHans Verkuil 245654450f59SHans Verkuil /* video format */ 245722d97e56SLaurent Pinchart io_write_clr_set(sd, 0x02, 0x0f, 245854450f59SHans Verkuil pdata->alt_gamma << 3 | 245954450f59SHans Verkuil pdata->op_656_range << 2 | 246054450f59SHans Verkuil pdata->alt_data_sat << 0); 246122d97e56SLaurent Pinchart io_write_clr_set(sd, 0x05, 0x0e, pdata->blank_data << 3 | 246254450f59SHans Verkuil pdata->insert_av_codes << 2 | 2463539b33b0SLaurent Pinchart pdata->replicate_av_codes << 1); 2464b44b2e06SPablo Anton adv76xx_setup_format(state); 246554450f59SHans Verkuil 246654450f59SHans Verkuil cp_write(sd, 0x69, 0x30); /* Enable CP CSC */ 246798908696SMartin Bugge 246898908696SMartin Bugge /* VS, HS polarities */ 24691b5ab875SLaurent Pinchart io_write(sd, 0x06, 0xa0 | pdata->inv_vs_pol << 2 | 24701b5ab875SLaurent Pinchart pdata->inv_hs_pol << 1 | pdata->inv_llc_pol); 2471f31b62e1SMikhail Khelik 2472f31b62e1SMikhail Khelik /* Adjust drive strength */ 2473f31b62e1SMikhail Khelik io_write(sd, 0x14, 0x40 | pdata->dr_str_data << 4 | 2474f31b62e1SMikhail Khelik pdata->dr_str_clk << 2 | 2475f31b62e1SMikhail Khelik pdata->dr_str_sync); 2476f31b62e1SMikhail Khelik 247754450f59SHans Verkuil cp_write(sd, 0xba, (pdata->hdmi_free_run_mode << 1) | 0x01); /* HDMI free run */ 247854450f59SHans Verkuil cp_write(sd, 0xf3, 0xdc); /* Low threshold to enter/exit free run mode */ 247954450f59SHans Verkuil cp_write(sd, 0xf9, 0x23); /* STDI ch. 1 - LCVS change threshold - 248080939647SHans Verkuil ADI recommended setting [REF_01, c. 2.3.3] */ 248154450f59SHans Verkuil cp_write(sd, 0x45, 0x23); /* STDI ch. 2 - LCVS change threshold - 248280939647SHans Verkuil ADI recommended setting [REF_01, c. 2.3.3] */ 248354450f59SHans Verkuil cp_write(sd, 0xc9, 0x2d); /* use prim_mode and vid_std as free run resolution 248454450f59SHans Verkuil for digital formats */ 248554450f59SHans Verkuil 24865474b983SMats Randgaard /* HDMI audio */ 248722d97e56SLaurent Pinchart hdmi_write_clr_set(sd, 0x15, 0x03, 0x03); /* Mute on FIFO over-/underflow [REF_01, c. 1.2.18] */ 248822d97e56SLaurent Pinchart hdmi_write_clr_set(sd, 0x1a, 0x0e, 0x08); /* Wait 1 s before unmute */ 248922d97e56SLaurent Pinchart hdmi_write_clr_set(sd, 0x68, 0x06, 0x06); /* FIFO reset on over-/underflow [REF_01, c. 1.2.19] */ 24905474b983SMats Randgaard 249154450f59SHans Verkuil /* TODO from platform data */ 249254450f59SHans Verkuil afe_write(sd, 0xb5, 0x01); /* Setting MCLK to 256Fs */ 249354450f59SHans Verkuil 2494b44b2e06SPablo Anton if (adv76xx_has_afe(state)) { 249554450f59SHans Verkuil afe_write(sd, 0x02, pdata->ain_sel); /* Select analog input muxing mode */ 249622d97e56SLaurent Pinchart io_write_clr_set(sd, 0x30, 1 << 4, pdata->output_bus_lsb_to_msb << 4); 2497d42010a1SLars-Peter Clausen } 249854450f59SHans Verkuil 249954450f59SHans Verkuil /* interrupts */ 2500d42010a1SLars-Peter Clausen io_write(sd, 0x40, 0xc0 | pdata->int1_config); /* Configure INT1 */ 250154450f59SHans Verkuil io_write(sd, 0x46, 0x98); /* Enable SSPD, STDI and CP unlocked interrupts */ 2502d42010a1SLars-Peter Clausen io_write(sd, 0x6e, info->fmt_change_digital_mask); /* Enable V_LOCKED and DE_REGEN_LCK interrupts */ 2503d42010a1SLars-Peter Clausen io_write(sd, 0x73, info->cable_det_mask); /* Enable cable detection (+5v) interrupts */ 2504d42010a1SLars-Peter Clausen info->setup_irqs(sd); 250554450f59SHans Verkuil 250654450f59SHans Verkuil return v4l2_ctrl_handler_setup(sd->ctrl_handler); 250754450f59SHans Verkuil } 250854450f59SHans Verkuil 2509d42010a1SLars-Peter Clausen static void adv7604_setup_irqs(struct v4l2_subdev *sd) 2510d42010a1SLars-Peter Clausen { 2511d42010a1SLars-Peter Clausen io_write(sd, 0x41, 0xd7); /* STDI irq for any change, disable INT2 */ 2512d42010a1SLars-Peter Clausen } 2513d42010a1SLars-Peter Clausen 2514d42010a1SLars-Peter Clausen static void adv7611_setup_irqs(struct v4l2_subdev *sd) 2515d42010a1SLars-Peter Clausen { 2516d42010a1SLars-Peter Clausen io_write(sd, 0x41, 0xd0); /* STDI irq for any change, disable INT2 */ 2517d42010a1SLars-Peter Clausen } 2518d42010a1SLars-Peter Clausen 25198331d30bSWilliam Towle static void adv7612_setup_irqs(struct v4l2_subdev *sd) 25208331d30bSWilliam Towle { 25218331d30bSWilliam Towle io_write(sd, 0x41, 0xd0); /* disable INT2 */ 25228331d30bSWilliam Towle } 25238331d30bSWilliam Towle 2524b44b2e06SPablo Anton static void adv76xx_unregister_clients(struct adv76xx_state *state) 252554450f59SHans Verkuil { 252605cacb17SLaurent Pinchart unsigned int i; 252705cacb17SLaurent Pinchart 252805cacb17SLaurent Pinchart for (i = 1; i < ARRAY_SIZE(state->i2c_clients); ++i) { 252905cacb17SLaurent Pinchart if (state->i2c_clients[i]) 253005cacb17SLaurent Pinchart i2c_unregister_device(state->i2c_clients[i]); 253105cacb17SLaurent Pinchart } 253254450f59SHans Verkuil } 253354450f59SHans Verkuil 2534b44b2e06SPablo Anton static struct i2c_client *adv76xx_dummy_client(struct v4l2_subdev *sd, 253554450f59SHans Verkuil u8 addr, u8 io_reg) 253654450f59SHans Verkuil { 253754450f59SHans Verkuil struct i2c_client *client = v4l2_get_subdevdata(sd); 253854450f59SHans Verkuil 253954450f59SHans Verkuil if (addr) 254054450f59SHans Verkuil io_write(sd, io_reg, addr << 1); 254154450f59SHans Verkuil return i2c_new_dummy(client->adapter, io_read(sd, io_reg) >> 1); 254254450f59SHans Verkuil } 254354450f59SHans Verkuil 2544b44b2e06SPablo Anton static const struct adv76xx_reg_seq adv7604_recommended_settings_afe[] = { 2545d42010a1SLars-Peter Clausen /* reset ADI recommended settings for HDMI: */ 2546d42010a1SLars-Peter Clausen /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 4. */ 2547b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x0d), 0x04 }, /* HDMI filter optimization */ 2548b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x0d), 0x04 }, /* HDMI filter optimization */ 2549b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x3d), 0x00 }, /* DDC bus active pull-up control */ 2550b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x3e), 0x74 }, /* TMDS PLL optimization */ 2551b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x4e), 0x3b }, /* TMDS PLL optimization */ 2552b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x57), 0x74 }, /* TMDS PLL optimization */ 2553b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x58), 0x63 }, /* TMDS PLL optimization */ 2554b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8d), 0x18 }, /* equaliser */ 2555b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8e), 0x34 }, /* equaliser */ 2556b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x93), 0x88 }, /* equaliser */ 2557b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x94), 0x2e }, /* equaliser */ 2558b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x96), 0x00 }, /* enable automatic EQ changing */ 2559d42010a1SLars-Peter Clausen 2560d42010a1SLars-Peter Clausen /* set ADI recommended settings for digitizer */ 2561d42010a1SLars-Peter Clausen /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 17. */ 2562b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_AFE, 0x12), 0x7b }, /* ADC noise shaping filter controls */ 2563b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_AFE, 0x0c), 0x1f }, /* CP core gain controls */ 2564b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_CP, 0x3e), 0x04 }, /* CP core pre-gain control */ 2565b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_CP, 0xc3), 0x39 }, /* CP coast control. Graphics mode */ 2566b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_CP, 0x40), 0x5c }, /* CP core pre-gain control. Graphics mode */ 2567d42010a1SLars-Peter Clausen 2568b44b2e06SPablo Anton { ADV76XX_REG_SEQ_TERM, 0 }, 2569d42010a1SLars-Peter Clausen }; 2570d42010a1SLars-Peter Clausen 2571b44b2e06SPablo Anton static const struct adv76xx_reg_seq adv7604_recommended_settings_hdmi[] = { 2572d42010a1SLars-Peter Clausen /* set ADI recommended settings for HDMI: */ 2573d42010a1SLars-Peter Clausen /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 4. */ 2574b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x0d), 0x84 }, /* HDMI filter optimization */ 2575b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x3d), 0x10 }, /* DDC bus active pull-up control */ 2576b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x3e), 0x39 }, /* TMDS PLL optimization */ 2577b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x4e), 0x3b }, /* TMDS PLL optimization */ 2578b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x57), 0xb6 }, /* TMDS PLL optimization */ 2579b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x58), 0x03 }, /* TMDS PLL optimization */ 2580b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8d), 0x18 }, /* equaliser */ 2581b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8e), 0x34 }, /* equaliser */ 2582b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x93), 0x8b }, /* equaliser */ 2583b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x94), 0x2d }, /* equaliser */ 2584b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x96), 0x01 }, /* enable automatic EQ changing */ 2585d42010a1SLars-Peter Clausen 2586d42010a1SLars-Peter Clausen /* reset ADI recommended settings for digitizer */ 2587d42010a1SLars-Peter Clausen /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 17. */ 2588b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_AFE, 0x12), 0xfb }, /* ADC noise shaping filter controls */ 2589b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_AFE, 0x0c), 0x0d }, /* CP core gain controls */ 2590d42010a1SLars-Peter Clausen 2591b44b2e06SPablo Anton { ADV76XX_REG_SEQ_TERM, 0 }, 2592d42010a1SLars-Peter Clausen }; 2593d42010a1SLars-Peter Clausen 2594b44b2e06SPablo Anton static const struct adv76xx_reg_seq adv7611_recommended_settings_hdmi[] = { 2595c41ad9c3SLars-Peter Clausen /* ADV7611 Register Settings Recommendations Rev 1.5, May 2014 */ 2596b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_CP, 0x6c), 0x00 }, 2597b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x9b), 0x03 }, 2598b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x6f), 0x08 }, 2599b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x85), 0x1f }, 2600b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x87), 0x70 }, 2601b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x57), 0xda }, 2602b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x58), 0x01 }, 2603b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x03), 0x98 }, 2604b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x4c), 0x44 }, 2605b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8d), 0x04 }, 2606b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8e), 0x1e }, 2607d42010a1SLars-Peter Clausen 2608b44b2e06SPablo Anton { ADV76XX_REG_SEQ_TERM, 0 }, 2609d42010a1SLars-Peter Clausen }; 2610d42010a1SLars-Peter Clausen 26118331d30bSWilliam Towle static const struct adv76xx_reg_seq adv7612_recommended_settings_hdmi[] = { 26128331d30bSWilliam Towle { ADV76XX_REG(ADV76XX_PAGE_CP, 0x6c), 0x00 }, 26138331d30bSWilliam Towle { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x9b), 0x03 }, 26148331d30bSWilliam Towle { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x6f), 0x08 }, 26158331d30bSWilliam Towle { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x85), 0x1f }, 26168331d30bSWilliam Towle { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x87), 0x70 }, 26178331d30bSWilliam Towle { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x57), 0xda }, 26188331d30bSWilliam Towle { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x58), 0x01 }, 26198331d30bSWilliam Towle { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x03), 0x98 }, 26208331d30bSWilliam Towle { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x4c), 0x44 }, 26218331d30bSWilliam Towle { ADV76XX_REG_SEQ_TERM, 0 }, 26228331d30bSWilliam Towle }; 26238331d30bSWilliam Towle 2624b44b2e06SPablo Anton static const struct adv76xx_chip_info adv76xx_chip_info[] = { 2625d42010a1SLars-Peter Clausen [ADV7604] = { 2626d42010a1SLars-Peter Clausen .type = ADV7604, 2627d42010a1SLars-Peter Clausen .has_afe = true, 2628c784b1e2SLaurent Pinchart .max_port = ADV7604_PAD_VGA_COMP, 2629d42010a1SLars-Peter Clausen .num_dv_ports = 4, 2630d42010a1SLars-Peter Clausen .edid_enable_reg = 0x77, 2631d42010a1SLars-Peter Clausen .edid_status_reg = 0x7d, 2632d42010a1SLars-Peter Clausen .lcf_reg = 0xb3, 2633d42010a1SLars-Peter Clausen .tdms_lock_mask = 0xe0, 2634d42010a1SLars-Peter Clausen .cable_det_mask = 0x1e, 2635d42010a1SLars-Peter Clausen .fmt_change_digital_mask = 0xc1, 263680f4944eSjean-michel.hautbois@vodalys.com .cp_csc = 0xfc, 2637539b33b0SLaurent Pinchart .formats = adv7604_formats, 2638539b33b0SLaurent Pinchart .nformats = ARRAY_SIZE(adv7604_formats), 2639d42010a1SLars-Peter Clausen .set_termination = adv7604_set_termination, 2640d42010a1SLars-Peter Clausen .setup_irqs = adv7604_setup_irqs, 2641d42010a1SLars-Peter Clausen .read_hdmi_pixelclock = adv7604_read_hdmi_pixelclock, 2642d42010a1SLars-Peter Clausen .read_cable_det = adv7604_read_cable_det, 2643d42010a1SLars-Peter Clausen .recommended_settings = { 2644d42010a1SLars-Peter Clausen [0] = adv7604_recommended_settings_afe, 2645d42010a1SLars-Peter Clausen [1] = adv7604_recommended_settings_hdmi, 2646d42010a1SLars-Peter Clausen }, 2647d42010a1SLars-Peter Clausen .num_recommended_settings = { 2648d42010a1SLars-Peter Clausen [0] = ARRAY_SIZE(adv7604_recommended_settings_afe), 2649d42010a1SLars-Peter Clausen [1] = ARRAY_SIZE(adv7604_recommended_settings_hdmi), 2650d42010a1SLars-Peter Clausen }, 2651b44b2e06SPablo Anton .page_mask = BIT(ADV76XX_PAGE_IO) | BIT(ADV7604_PAGE_AVLINK) | 2652b44b2e06SPablo Anton BIT(ADV76XX_PAGE_CEC) | BIT(ADV76XX_PAGE_INFOFRAME) | 2653d42010a1SLars-Peter Clausen BIT(ADV7604_PAGE_ESDP) | BIT(ADV7604_PAGE_DPP) | 2654b44b2e06SPablo Anton BIT(ADV76XX_PAGE_AFE) | BIT(ADV76XX_PAGE_REP) | 2655b44b2e06SPablo Anton BIT(ADV76XX_PAGE_EDID) | BIT(ADV76XX_PAGE_HDMI) | 2656b44b2e06SPablo Anton BIT(ADV76XX_PAGE_TEST) | BIT(ADV76XX_PAGE_CP) | 2657d42010a1SLars-Peter Clausen BIT(ADV7604_PAGE_VDP), 26585380baafSjean-michel.hautbois@vodalys.com .linewidth_mask = 0xfff, 26595380baafSjean-michel.hautbois@vodalys.com .field0_height_mask = 0xfff, 26605380baafSjean-michel.hautbois@vodalys.com .field1_height_mask = 0xfff, 26615380baafSjean-michel.hautbois@vodalys.com .hfrontporch_mask = 0x3ff, 26625380baafSjean-michel.hautbois@vodalys.com .hsync_mask = 0x3ff, 26635380baafSjean-michel.hautbois@vodalys.com .hbackporch_mask = 0x3ff, 26645380baafSjean-michel.hautbois@vodalys.com .field0_vfrontporch_mask = 0x1fff, 26655380baafSjean-michel.hautbois@vodalys.com .field0_vsync_mask = 0x1fff, 26665380baafSjean-michel.hautbois@vodalys.com .field0_vbackporch_mask = 0x1fff, 26675380baafSjean-michel.hautbois@vodalys.com .field1_vfrontporch_mask = 0x1fff, 26685380baafSjean-michel.hautbois@vodalys.com .field1_vsync_mask = 0x1fff, 26695380baafSjean-michel.hautbois@vodalys.com .field1_vbackporch_mask = 0x1fff, 2670d42010a1SLars-Peter Clausen }, 2671d42010a1SLars-Peter Clausen [ADV7611] = { 2672d42010a1SLars-Peter Clausen .type = ADV7611, 2673d42010a1SLars-Peter Clausen .has_afe = false, 2674b44b2e06SPablo Anton .max_port = ADV76XX_PAD_HDMI_PORT_A, 2675d42010a1SLars-Peter Clausen .num_dv_ports = 1, 2676d42010a1SLars-Peter Clausen .edid_enable_reg = 0x74, 2677d42010a1SLars-Peter Clausen .edid_status_reg = 0x76, 2678d42010a1SLars-Peter Clausen .lcf_reg = 0xa3, 2679d42010a1SLars-Peter Clausen .tdms_lock_mask = 0x43, 2680d42010a1SLars-Peter Clausen .cable_det_mask = 0x01, 2681d42010a1SLars-Peter Clausen .fmt_change_digital_mask = 0x03, 268280f4944eSjean-michel.hautbois@vodalys.com .cp_csc = 0xf4, 2683539b33b0SLaurent Pinchart .formats = adv7611_formats, 2684539b33b0SLaurent Pinchart .nformats = ARRAY_SIZE(adv7611_formats), 2685d42010a1SLars-Peter Clausen .set_termination = adv7611_set_termination, 2686d42010a1SLars-Peter Clausen .setup_irqs = adv7611_setup_irqs, 2687d42010a1SLars-Peter Clausen .read_hdmi_pixelclock = adv7611_read_hdmi_pixelclock, 2688d42010a1SLars-Peter Clausen .read_cable_det = adv7611_read_cable_det, 2689d42010a1SLars-Peter Clausen .recommended_settings = { 2690d42010a1SLars-Peter Clausen [1] = adv7611_recommended_settings_hdmi, 2691d42010a1SLars-Peter Clausen }, 2692d42010a1SLars-Peter Clausen .num_recommended_settings = { 2693d42010a1SLars-Peter Clausen [1] = ARRAY_SIZE(adv7611_recommended_settings_hdmi), 2694d42010a1SLars-Peter Clausen }, 2695b44b2e06SPablo Anton .page_mask = BIT(ADV76XX_PAGE_IO) | BIT(ADV76XX_PAGE_CEC) | 2696b44b2e06SPablo Anton BIT(ADV76XX_PAGE_INFOFRAME) | BIT(ADV76XX_PAGE_AFE) | 2697b44b2e06SPablo Anton BIT(ADV76XX_PAGE_REP) | BIT(ADV76XX_PAGE_EDID) | 2698b44b2e06SPablo Anton BIT(ADV76XX_PAGE_HDMI) | BIT(ADV76XX_PAGE_CP), 26995380baafSjean-michel.hautbois@vodalys.com .linewidth_mask = 0x1fff, 27005380baafSjean-michel.hautbois@vodalys.com .field0_height_mask = 0x1fff, 27015380baafSjean-michel.hautbois@vodalys.com .field1_height_mask = 0x1fff, 27025380baafSjean-michel.hautbois@vodalys.com .hfrontporch_mask = 0x1fff, 27035380baafSjean-michel.hautbois@vodalys.com .hsync_mask = 0x1fff, 27045380baafSjean-michel.hautbois@vodalys.com .hbackporch_mask = 0x1fff, 27055380baafSjean-michel.hautbois@vodalys.com .field0_vfrontporch_mask = 0x3fff, 27065380baafSjean-michel.hautbois@vodalys.com .field0_vsync_mask = 0x3fff, 27075380baafSjean-michel.hautbois@vodalys.com .field0_vbackporch_mask = 0x3fff, 27085380baafSjean-michel.hautbois@vodalys.com .field1_vfrontporch_mask = 0x3fff, 27095380baafSjean-michel.hautbois@vodalys.com .field1_vsync_mask = 0x3fff, 27105380baafSjean-michel.hautbois@vodalys.com .field1_vbackporch_mask = 0x3fff, 2711d42010a1SLars-Peter Clausen }, 27128331d30bSWilliam Towle [ADV7612] = { 27138331d30bSWilliam Towle .type = ADV7612, 27148331d30bSWilliam Towle .has_afe = false, 27158331d30bSWilliam Towle .max_port = ADV7604_PAD_HDMI_PORT_B, 27168331d30bSWilliam Towle .num_dv_ports = 2, 27178331d30bSWilliam Towle .edid_enable_reg = 0x74, 27188331d30bSWilliam Towle .edid_status_reg = 0x76, 27198331d30bSWilliam Towle .lcf_reg = 0xa3, 27208331d30bSWilliam Towle .tdms_lock_mask = 0x43, 27218331d30bSWilliam Towle .cable_det_mask = 0x01, 27228331d30bSWilliam Towle .fmt_change_digital_mask = 0x03, 27238331d30bSWilliam Towle .formats = adv7612_formats, 27248331d30bSWilliam Towle .nformats = ARRAY_SIZE(adv7612_formats), 27258331d30bSWilliam Towle .set_termination = adv7611_set_termination, 27268331d30bSWilliam Towle .setup_irqs = adv7612_setup_irqs, 27278331d30bSWilliam Towle .read_hdmi_pixelclock = adv7611_read_hdmi_pixelclock, 27288331d30bSWilliam Towle .read_cable_det = adv7611_read_cable_det, 27298331d30bSWilliam Towle .recommended_settings = { 27308331d30bSWilliam Towle [1] = adv7612_recommended_settings_hdmi, 27318331d30bSWilliam Towle }, 27328331d30bSWilliam Towle .num_recommended_settings = { 27338331d30bSWilliam Towle [1] = ARRAY_SIZE(adv7612_recommended_settings_hdmi), 27348331d30bSWilliam Towle }, 27358331d30bSWilliam Towle .page_mask = BIT(ADV76XX_PAGE_IO) | BIT(ADV76XX_PAGE_CEC) | 27368331d30bSWilliam Towle BIT(ADV76XX_PAGE_INFOFRAME) | BIT(ADV76XX_PAGE_AFE) | 27378331d30bSWilliam Towle BIT(ADV76XX_PAGE_REP) | BIT(ADV76XX_PAGE_EDID) | 27388331d30bSWilliam Towle BIT(ADV76XX_PAGE_HDMI) | BIT(ADV76XX_PAGE_CP), 27398331d30bSWilliam Towle .linewidth_mask = 0x1fff, 27408331d30bSWilliam Towle .field0_height_mask = 0x1fff, 27418331d30bSWilliam Towle .field1_height_mask = 0x1fff, 27428331d30bSWilliam Towle .hfrontporch_mask = 0x1fff, 27438331d30bSWilliam Towle .hsync_mask = 0x1fff, 27448331d30bSWilliam Towle .hbackporch_mask = 0x1fff, 27458331d30bSWilliam Towle .field0_vfrontporch_mask = 0x3fff, 27468331d30bSWilliam Towle .field0_vsync_mask = 0x3fff, 27478331d30bSWilliam Towle .field0_vbackporch_mask = 0x3fff, 27488331d30bSWilliam Towle .field1_vfrontporch_mask = 0x3fff, 27498331d30bSWilliam Towle .field1_vsync_mask = 0x3fff, 27508331d30bSWilliam Towle .field1_vbackporch_mask = 0x3fff, 27518331d30bSWilliam Towle }, 2752d42010a1SLars-Peter Clausen }; 2753d42010a1SLars-Peter Clausen 27547f099a75SFabian Frederick static const struct i2c_device_id adv76xx_i2c_id[] = { 2755b44b2e06SPablo Anton { "adv7604", (kernel_ulong_t)&adv76xx_chip_info[ADV7604] }, 2756b44b2e06SPablo Anton { "adv7611", (kernel_ulong_t)&adv76xx_chip_info[ADV7611] }, 27578331d30bSWilliam Towle { "adv7612", (kernel_ulong_t)&adv76xx_chip_info[ADV7612] }, 2758f82f313eSLaurent Pinchart { } 2759f82f313eSLaurent Pinchart }; 2760b44b2e06SPablo Anton MODULE_DEVICE_TABLE(i2c, adv76xx_i2c_id); 2761f82f313eSLaurent Pinchart 27627f099a75SFabian Frederick static const struct of_device_id adv76xx_of_id[] __maybe_unused = { 2763b44b2e06SPablo Anton { .compatible = "adi,adv7611", .data = &adv76xx_chip_info[ADV7611] }, 27648331d30bSWilliam Towle { .compatible = "adi,adv7612", .data = &adv76xx_chip_info[ADV7612] }, 2765f82f313eSLaurent Pinchart { } 2766f82f313eSLaurent Pinchart }; 2767b44b2e06SPablo Anton MODULE_DEVICE_TABLE(of, adv76xx_of_id); 2768f82f313eSLaurent Pinchart 2769b44b2e06SPablo Anton static int adv76xx_parse_dt(struct adv76xx_state *state) 2770f82f313eSLaurent Pinchart { 27716fa88045SLaurent Pinchart struct v4l2_of_endpoint bus_cfg; 27726fa88045SLaurent Pinchart struct device_node *endpoint; 27736fa88045SLaurent Pinchart struct device_node *np; 27746fa88045SLaurent Pinchart unsigned int flags; 27756fa88045SLaurent Pinchart 2776b44b2e06SPablo Anton np = state->i2c_clients[ADV76XX_PAGE_IO]->dev.of_node; 27776fa88045SLaurent Pinchart 27786fa88045SLaurent Pinchart /* Parse the endpoint. */ 27796fa88045SLaurent Pinchart endpoint = of_graph_get_next_endpoint(np, NULL); 27806fa88045SLaurent Pinchart if (!endpoint) 27816fa88045SLaurent Pinchart return -EINVAL; 27826fa88045SLaurent Pinchart 27836fa88045SLaurent Pinchart v4l2_of_parse_endpoint(endpoint, &bus_cfg); 27846fa88045SLaurent Pinchart of_node_put(endpoint); 27856fa88045SLaurent Pinchart 27866fa88045SLaurent Pinchart flags = bus_cfg.bus.parallel.flags; 27876fa88045SLaurent Pinchart 27886fa88045SLaurent Pinchart if (flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH) 27896fa88045SLaurent Pinchart state->pdata.inv_hs_pol = 1; 27906fa88045SLaurent Pinchart 27916fa88045SLaurent Pinchart if (flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH) 27926fa88045SLaurent Pinchart state->pdata.inv_vs_pol = 1; 27936fa88045SLaurent Pinchart 27946fa88045SLaurent Pinchart if (flags & V4L2_MBUS_PCLK_SAMPLE_RISING) 27956fa88045SLaurent Pinchart state->pdata.inv_llc_pol = 1; 27966fa88045SLaurent Pinchart 27976fa88045SLaurent Pinchart if (bus_cfg.bus_type == V4L2_MBUS_BT656) { 27986fa88045SLaurent Pinchart state->pdata.insert_av_codes = 1; 27996fa88045SLaurent Pinchart state->pdata.op_656_range = 1; 28006fa88045SLaurent Pinchart } 28016fa88045SLaurent Pinchart 2802f82f313eSLaurent Pinchart /* Disable the interrupt for now as no DT-based board uses it. */ 2803b44b2e06SPablo Anton state->pdata.int1_config = ADV76XX_INT1_CONFIG_DISABLED; 2804f82f313eSLaurent Pinchart 2805f82f313eSLaurent Pinchart /* Use the default I2C addresses. */ 2806f82f313eSLaurent Pinchart state->pdata.i2c_addresses[ADV7604_PAGE_AVLINK] = 0x42; 2807b44b2e06SPablo Anton state->pdata.i2c_addresses[ADV76XX_PAGE_CEC] = 0x40; 2808b44b2e06SPablo Anton state->pdata.i2c_addresses[ADV76XX_PAGE_INFOFRAME] = 0x3e; 2809f82f313eSLaurent Pinchart state->pdata.i2c_addresses[ADV7604_PAGE_ESDP] = 0x38; 2810f82f313eSLaurent Pinchart state->pdata.i2c_addresses[ADV7604_PAGE_DPP] = 0x3c; 2811b44b2e06SPablo Anton state->pdata.i2c_addresses[ADV76XX_PAGE_AFE] = 0x26; 2812b44b2e06SPablo Anton state->pdata.i2c_addresses[ADV76XX_PAGE_REP] = 0x32; 2813b44b2e06SPablo Anton state->pdata.i2c_addresses[ADV76XX_PAGE_EDID] = 0x36; 2814b44b2e06SPablo Anton state->pdata.i2c_addresses[ADV76XX_PAGE_HDMI] = 0x34; 2815b44b2e06SPablo Anton state->pdata.i2c_addresses[ADV76XX_PAGE_TEST] = 0x30; 2816b44b2e06SPablo Anton state->pdata.i2c_addresses[ADV76XX_PAGE_CP] = 0x22; 2817f82f313eSLaurent Pinchart state->pdata.i2c_addresses[ADV7604_PAGE_VDP] = 0x24; 2818f82f313eSLaurent Pinchart 2819f82f313eSLaurent Pinchart /* Hardcode the remaining platform data fields. */ 2820f82f313eSLaurent Pinchart state->pdata.disable_pwrdnb = 0; 2821f82f313eSLaurent Pinchart state->pdata.disable_cable_det_rst = 0; 2822f82f313eSLaurent Pinchart state->pdata.default_input = -1; 2823f82f313eSLaurent Pinchart state->pdata.blank_data = 1; 2824f82f313eSLaurent Pinchart state->pdata.alt_data_sat = 1; 2825f82f313eSLaurent Pinchart state->pdata.op_format_mode_sel = ADV7604_OP_FORMAT_MODE0; 2826f82f313eSLaurent Pinchart state->pdata.bus_order = ADV7604_BUS_ORDER_RGB; 2827f82f313eSLaurent Pinchart 2828f82f313eSLaurent Pinchart return 0; 2829f82f313eSLaurent Pinchart } 2830f82f313eSLaurent Pinchart 2831f862f57dSPablo Anton static const struct regmap_config adv76xx_regmap_cnf[] = { 2832f862f57dSPablo Anton { 2833f862f57dSPablo Anton .name = "io", 2834f862f57dSPablo Anton .reg_bits = 8, 2835f862f57dSPablo Anton .val_bits = 8, 2836f862f57dSPablo Anton 2837f862f57dSPablo Anton .max_register = 0xff, 2838f862f57dSPablo Anton .cache_type = REGCACHE_NONE, 2839f862f57dSPablo Anton }, 2840f862f57dSPablo Anton { 2841f862f57dSPablo Anton .name = "avlink", 2842f862f57dSPablo Anton .reg_bits = 8, 2843f862f57dSPablo Anton .val_bits = 8, 2844f862f57dSPablo Anton 2845f862f57dSPablo Anton .max_register = 0xff, 2846f862f57dSPablo Anton .cache_type = REGCACHE_NONE, 2847f862f57dSPablo Anton }, 2848f862f57dSPablo Anton { 2849f862f57dSPablo Anton .name = "cec", 2850f862f57dSPablo Anton .reg_bits = 8, 2851f862f57dSPablo Anton .val_bits = 8, 2852f862f57dSPablo Anton 2853f862f57dSPablo Anton .max_register = 0xff, 2854f862f57dSPablo Anton .cache_type = REGCACHE_NONE, 2855f862f57dSPablo Anton }, 2856f862f57dSPablo Anton { 2857f862f57dSPablo Anton .name = "infoframe", 2858f862f57dSPablo Anton .reg_bits = 8, 2859f862f57dSPablo Anton .val_bits = 8, 2860f862f57dSPablo Anton 2861f862f57dSPablo Anton .max_register = 0xff, 2862f862f57dSPablo Anton .cache_type = REGCACHE_NONE, 2863f862f57dSPablo Anton }, 2864f862f57dSPablo Anton { 2865f862f57dSPablo Anton .name = "esdp", 2866f862f57dSPablo Anton .reg_bits = 8, 2867f862f57dSPablo Anton .val_bits = 8, 2868f862f57dSPablo Anton 2869f862f57dSPablo Anton .max_register = 0xff, 2870f862f57dSPablo Anton .cache_type = REGCACHE_NONE, 2871f862f57dSPablo Anton }, 2872f862f57dSPablo Anton { 2873f862f57dSPablo Anton .name = "epp", 2874f862f57dSPablo Anton .reg_bits = 8, 2875f862f57dSPablo Anton .val_bits = 8, 2876f862f57dSPablo Anton 2877f862f57dSPablo Anton .max_register = 0xff, 2878f862f57dSPablo Anton .cache_type = REGCACHE_NONE, 2879f862f57dSPablo Anton }, 2880f862f57dSPablo Anton { 2881f862f57dSPablo Anton .name = "afe", 2882f862f57dSPablo Anton .reg_bits = 8, 2883f862f57dSPablo Anton .val_bits = 8, 2884f862f57dSPablo Anton 2885f862f57dSPablo Anton .max_register = 0xff, 2886f862f57dSPablo Anton .cache_type = REGCACHE_NONE, 2887f862f57dSPablo Anton }, 2888f862f57dSPablo Anton { 2889f862f57dSPablo Anton .name = "rep", 2890f862f57dSPablo Anton .reg_bits = 8, 2891f862f57dSPablo Anton .val_bits = 8, 2892f862f57dSPablo Anton 2893f862f57dSPablo Anton .max_register = 0xff, 2894f862f57dSPablo Anton .cache_type = REGCACHE_NONE, 2895f862f57dSPablo Anton }, 2896f862f57dSPablo Anton { 2897f862f57dSPablo Anton .name = "edid", 2898f862f57dSPablo Anton .reg_bits = 8, 2899f862f57dSPablo Anton .val_bits = 8, 2900f862f57dSPablo Anton 2901f862f57dSPablo Anton .max_register = 0xff, 2902f862f57dSPablo Anton .cache_type = REGCACHE_NONE, 2903f862f57dSPablo Anton }, 2904f862f57dSPablo Anton 2905f862f57dSPablo Anton { 2906f862f57dSPablo Anton .name = "hdmi", 2907f862f57dSPablo Anton .reg_bits = 8, 2908f862f57dSPablo Anton .val_bits = 8, 2909f862f57dSPablo Anton 2910f862f57dSPablo Anton .max_register = 0xff, 2911f862f57dSPablo Anton .cache_type = REGCACHE_NONE, 2912f862f57dSPablo Anton }, 2913f862f57dSPablo Anton { 2914f862f57dSPablo Anton .name = "test", 2915f862f57dSPablo Anton .reg_bits = 8, 2916f862f57dSPablo Anton .val_bits = 8, 2917f862f57dSPablo Anton 2918f862f57dSPablo Anton .max_register = 0xff, 2919f862f57dSPablo Anton .cache_type = REGCACHE_NONE, 2920f862f57dSPablo Anton }, 2921f862f57dSPablo Anton { 2922f862f57dSPablo Anton .name = "cp", 2923f862f57dSPablo Anton .reg_bits = 8, 2924f862f57dSPablo Anton .val_bits = 8, 2925f862f57dSPablo Anton 2926f862f57dSPablo Anton .max_register = 0xff, 2927f862f57dSPablo Anton .cache_type = REGCACHE_NONE, 2928f862f57dSPablo Anton }, 2929f862f57dSPablo Anton { 2930f862f57dSPablo Anton .name = "vdp", 2931f862f57dSPablo Anton .reg_bits = 8, 2932f862f57dSPablo Anton .val_bits = 8, 2933f862f57dSPablo Anton 2934f862f57dSPablo Anton .max_register = 0xff, 2935f862f57dSPablo Anton .cache_type = REGCACHE_NONE, 2936f862f57dSPablo Anton }, 2937f862f57dSPablo Anton }; 2938f862f57dSPablo Anton 2939f862f57dSPablo Anton static int configure_regmap(struct adv76xx_state *state, int region) 2940f862f57dSPablo Anton { 2941f862f57dSPablo Anton int err; 2942f862f57dSPablo Anton 2943f862f57dSPablo Anton if (!state->i2c_clients[region]) 2944f862f57dSPablo Anton return -ENODEV; 2945f862f57dSPablo Anton 2946f862f57dSPablo Anton state->regmap[region] = 2947f862f57dSPablo Anton devm_regmap_init_i2c(state->i2c_clients[region], 2948f862f57dSPablo Anton &adv76xx_regmap_cnf[region]); 2949f862f57dSPablo Anton 2950f862f57dSPablo Anton if (IS_ERR(state->regmap[region])) { 2951f862f57dSPablo Anton err = PTR_ERR(state->regmap[region]); 2952f862f57dSPablo Anton v4l_err(state->i2c_clients[region], 2953f862f57dSPablo Anton "Error initializing regmap %d with error %d\n", 2954f862f57dSPablo Anton region, err); 2955f862f57dSPablo Anton return -EINVAL; 2956f862f57dSPablo Anton } 2957f862f57dSPablo Anton 2958f862f57dSPablo Anton return 0; 2959f862f57dSPablo Anton } 2960f862f57dSPablo Anton 2961f862f57dSPablo Anton static int configure_regmaps(struct adv76xx_state *state) 2962f862f57dSPablo Anton { 2963f862f57dSPablo Anton int i, err; 2964f862f57dSPablo Anton 2965f862f57dSPablo Anton for (i = ADV7604_PAGE_AVLINK ; i < ADV76XX_PAGE_MAX; i++) { 2966f862f57dSPablo Anton err = configure_regmap(state, i); 2967f862f57dSPablo Anton if (err && (err != -ENODEV)) 2968f862f57dSPablo Anton return err; 2969f862f57dSPablo Anton } 2970f862f57dSPablo Anton return 0; 2971f862f57dSPablo Anton } 2972f862f57dSPablo Anton 2973b44b2e06SPablo Anton static int adv76xx_probe(struct i2c_client *client, 297454450f59SHans Verkuil const struct i2c_device_id *id) 297554450f59SHans Verkuil { 2976591b72feSHans Verkuil static const struct v4l2_dv_timings cea640x480 = 2977591b72feSHans Verkuil V4L2_DV_BT_CEA_640X480P59_94; 2978b44b2e06SPablo Anton struct adv76xx_state *state; 297954450f59SHans Verkuil struct v4l2_ctrl_handler *hdl; 298054450f59SHans Verkuil struct v4l2_subdev *sd; 2981c784b1e2SLaurent Pinchart unsigned int i; 2982f862f57dSPablo Anton unsigned int val, val2; 298354450f59SHans Verkuil int err; 298454450f59SHans Verkuil 298554450f59SHans Verkuil /* Check if the adapter supports the needed features */ 298654450f59SHans Verkuil if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA)) 298754450f59SHans Verkuil return -EIO; 2988b44b2e06SPablo Anton v4l_dbg(1, debug, client, "detecting adv76xx client on address 0x%x\n", 298954450f59SHans Verkuil client->addr << 1); 299054450f59SHans Verkuil 2991c02b211dSLaurent Pinchart state = devm_kzalloc(&client->dev, sizeof(*state), GFP_KERNEL); 299254450f59SHans Verkuil if (!state) { 2993b44b2e06SPablo Anton v4l_err(client, "Could not allocate adv76xx_state memory!\n"); 299454450f59SHans Verkuil return -ENOMEM; 299554450f59SHans Verkuil } 299654450f59SHans Verkuil 2997b44b2e06SPablo Anton state->i2c_clients[ADV76XX_PAGE_IO] = client; 2998d42010a1SLars-Peter Clausen 299925a64ac9SMats Randgaard /* initialize variables */ 300025a64ac9SMats Randgaard state->restart_stdi_once = true; 3001ff4f80fdSMats Randgaard state->selected_input = ~0; 300225a64ac9SMats Randgaard 3003f82f313eSLaurent Pinchart if (IS_ENABLED(CONFIG_OF) && client->dev.of_node) { 3004f82f313eSLaurent Pinchart const struct of_device_id *oid; 3005f82f313eSLaurent Pinchart 3006b44b2e06SPablo Anton oid = of_match_node(adv76xx_of_id, client->dev.of_node); 3007f82f313eSLaurent Pinchart state->info = oid->data; 3008f82f313eSLaurent Pinchart 3009b44b2e06SPablo Anton err = adv76xx_parse_dt(state); 3010f82f313eSLaurent Pinchart if (err < 0) { 3011f82f313eSLaurent Pinchart v4l_err(client, "DT parsing error\n"); 3012f82f313eSLaurent Pinchart return err; 3013f82f313eSLaurent Pinchart } 3014f82f313eSLaurent Pinchart } else if (client->dev.platform_data) { 3015b44b2e06SPablo Anton struct adv76xx_platform_data *pdata = client->dev.platform_data; 3016f82f313eSLaurent Pinchart 3017b44b2e06SPablo Anton state->info = (const struct adv76xx_chip_info *)id->driver_data; 3018f82f313eSLaurent Pinchart state->pdata = *pdata; 3019f82f313eSLaurent Pinchart } else { 302054450f59SHans Verkuil v4l_err(client, "No platform data!\n"); 3021c02b211dSLaurent Pinchart return -ENODEV; 302254450f59SHans Verkuil } 3023e9d50e9eSLaurent Pinchart 3024e9d50e9eSLaurent Pinchart /* Request GPIOs. */ 3025e9d50e9eSLaurent Pinchart for (i = 0; i < state->info->num_dv_ports; ++i) { 3026e9d50e9eSLaurent Pinchart state->hpd_gpio[i] = 3027269bd132SUwe Kleine-König devm_gpiod_get_index_optional(&client->dev, "hpd", i, 3028269bd132SUwe Kleine-König GPIOD_OUT_LOW); 3029e9d50e9eSLaurent Pinchart if (IS_ERR(state->hpd_gpio[i])) 3030269bd132SUwe Kleine-König return PTR_ERR(state->hpd_gpio[i]); 3031e9d50e9eSLaurent Pinchart 3032269bd132SUwe Kleine-König if (state->hpd_gpio[i]) 3033e9d50e9eSLaurent Pinchart v4l_info(client, "Handling HPD %u GPIO\n", i); 3034e9d50e9eSLaurent Pinchart } 3035e9d50e9eSLaurent Pinchart 3036591b72feSHans Verkuil state->timings = cea640x480; 3037b44b2e06SPablo Anton state->format = adv76xx_format_info(state, MEDIA_BUS_FMT_YUYV8_2X8); 303854450f59SHans Verkuil 303954450f59SHans Verkuil sd = &state->sd; 3040b44b2e06SPablo Anton v4l2_i2c_subdev_init(sd, client, &adv76xx_ops); 3041d42010a1SLars-Peter Clausen snprintf(sd->name, sizeof(sd->name), "%s %d-%04x", 3042d42010a1SLars-Peter Clausen id->name, i2c_adapter_id(client->adapter), 3043d42010a1SLars-Peter Clausen client->addr); 304454450f59SHans Verkuil sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; 304554450f59SHans Verkuil 3046f862f57dSPablo Anton /* Configure IO Regmap region */ 3047f862f57dSPablo Anton err = configure_regmap(state, ADV76XX_PAGE_IO); 3048f862f57dSPablo Anton 3049f862f57dSPablo Anton if (err) { 3050f862f57dSPablo Anton v4l2_err(sd, "Error configuring IO regmap region\n"); 3051f862f57dSPablo Anton return -ENODEV; 3052f862f57dSPablo Anton } 3053f862f57dSPablo Anton 3054d42010a1SLars-Peter Clausen /* 3055d42010a1SLars-Peter Clausen * Verify that the chip is present. On ADV7604 the RD_INFO register only 3056d42010a1SLars-Peter Clausen * identifies the revision, while on ADV7611 it identifies the model as 3057d42010a1SLars-Peter Clausen * well. Use the HDMI slave address on ADV7604 and RD_INFO on ADV7611. 3058d42010a1SLars-Peter Clausen */ 30598331d30bSWilliam Towle switch (state->info->type) { 30608331d30bSWilliam Towle case ADV7604: 3061f862f57dSPablo Anton err = regmap_read(state->regmap[ADV76XX_PAGE_IO], 0xfb, &val); 3062f862f57dSPablo Anton if (err) { 3063f862f57dSPablo Anton v4l2_err(sd, "Error %d reading IO Regmap\n", err); 3064f862f57dSPablo Anton return -ENODEV; 3065f862f57dSPablo Anton } 3066d42010a1SLars-Peter Clausen if (val != 0x68) { 3067f862f57dSPablo Anton v4l2_err(sd, "not an adv7604 on address 0x%x\n", 306854450f59SHans Verkuil client->addr << 1); 3069c02b211dSLaurent Pinchart return -ENODEV; 307054450f59SHans Verkuil } 30718331d30bSWilliam Towle break; 30728331d30bSWilliam Towle case ADV7611: 30738331d30bSWilliam Towle case ADV7612: 3074f862f57dSPablo Anton err = regmap_read(state->regmap[ADV76XX_PAGE_IO], 3075f862f57dSPablo Anton 0xea, 3076f862f57dSPablo Anton &val); 3077f862f57dSPablo Anton if (err) { 3078f862f57dSPablo Anton v4l2_err(sd, "Error %d reading IO Regmap\n", err); 3079f862f57dSPablo Anton return -ENODEV; 3080f862f57dSPablo Anton } 3081f862f57dSPablo Anton val2 = val << 8; 3082f862f57dSPablo Anton err = regmap_read(state->regmap[ADV76XX_PAGE_IO], 3083f862f57dSPablo Anton 0xeb, 3084f862f57dSPablo Anton &val); 3085f862f57dSPablo Anton if (err) { 3086f862f57dSPablo Anton v4l2_err(sd, "Error %d reading IO Regmap\n", err); 3087f862f57dSPablo Anton return -ENODEV; 3088f862f57dSPablo Anton } 3089f862f57dSPablo Anton val2 |= val; 30908331d30bSWilliam Towle if ((state->info->type == ADV7611 && val != 0x2051) || 30918331d30bSWilliam Towle (state->info->type == ADV7612 && val != 0x2041)) { 30928331d30bSWilliam Towle v4l2_err(sd, "not an adv761x on address 0x%x\n", 3093d42010a1SLars-Peter Clausen client->addr << 1); 3094d42010a1SLars-Peter Clausen return -ENODEV; 3095d42010a1SLars-Peter Clausen } 30968331d30bSWilliam Towle break; 3097d42010a1SLars-Peter Clausen } 309854450f59SHans Verkuil 309954450f59SHans Verkuil /* control handlers */ 310054450f59SHans Verkuil hdl = &state->hdl; 3101b44b2e06SPablo Anton v4l2_ctrl_handler_init(hdl, adv76xx_has_afe(state) ? 9 : 8); 310254450f59SHans Verkuil 3103b44b2e06SPablo Anton v4l2_ctrl_new_std(hdl, &adv76xx_ctrl_ops, 310454450f59SHans Verkuil V4L2_CID_BRIGHTNESS, -128, 127, 1, 0); 3105b44b2e06SPablo Anton v4l2_ctrl_new_std(hdl, &adv76xx_ctrl_ops, 310654450f59SHans Verkuil V4L2_CID_CONTRAST, 0, 255, 1, 128); 3107b44b2e06SPablo Anton v4l2_ctrl_new_std(hdl, &adv76xx_ctrl_ops, 310854450f59SHans Verkuil V4L2_CID_SATURATION, 0, 255, 1, 128); 3109b44b2e06SPablo Anton v4l2_ctrl_new_std(hdl, &adv76xx_ctrl_ops, 311054450f59SHans Verkuil V4L2_CID_HUE, 0, 128, 1, 0); 311154450f59SHans Verkuil 311254450f59SHans Verkuil /* private controls */ 311354450f59SHans Verkuil state->detect_tx_5v_ctrl = v4l2_ctrl_new_std(hdl, NULL, 3114d42010a1SLars-Peter Clausen V4L2_CID_DV_RX_POWER_PRESENT, 0, 3115d42010a1SLars-Peter Clausen (1 << state->info->num_dv_ports) - 1, 0, 0); 311654450f59SHans Verkuil state->rgb_quantization_range_ctrl = 3117b44b2e06SPablo Anton v4l2_ctrl_new_std_menu(hdl, &adv76xx_ctrl_ops, 311854450f59SHans Verkuil V4L2_CID_DV_RX_RGB_RANGE, V4L2_DV_RGB_RANGE_FULL, 311954450f59SHans Verkuil 0, V4L2_DV_RGB_RANGE_AUTO); 312054450f59SHans Verkuil 312154450f59SHans Verkuil /* custom controls */ 3122b44b2e06SPablo Anton if (adv76xx_has_afe(state)) 312354450f59SHans Verkuil state->analog_sampling_phase_ctrl = 312454450f59SHans Verkuil v4l2_ctrl_new_custom(hdl, &adv7604_ctrl_analog_sampling_phase, NULL); 312554450f59SHans Verkuil state->free_run_color_manual_ctrl = 3126b44b2e06SPablo Anton v4l2_ctrl_new_custom(hdl, &adv76xx_ctrl_free_run_color_manual, NULL); 312754450f59SHans Verkuil state->free_run_color_ctrl = 3128b44b2e06SPablo Anton v4l2_ctrl_new_custom(hdl, &adv76xx_ctrl_free_run_color, NULL); 312954450f59SHans Verkuil 313054450f59SHans Verkuil sd->ctrl_handler = hdl; 313154450f59SHans Verkuil if (hdl->error) { 313254450f59SHans Verkuil err = hdl->error; 313354450f59SHans Verkuil goto err_hdl; 313454450f59SHans Verkuil } 31358c0eadb8SHans Verkuil state->detect_tx_5v_ctrl->is_private = true; 31368c0eadb8SHans Verkuil state->rgb_quantization_range_ctrl->is_private = true; 3137b44b2e06SPablo Anton if (adv76xx_has_afe(state)) 31388c0eadb8SHans Verkuil state->analog_sampling_phase_ctrl->is_private = true; 31398c0eadb8SHans Verkuil state->free_run_color_manual_ctrl->is_private = true; 31408c0eadb8SHans Verkuil state->free_run_color_ctrl->is_private = true; 31418c0eadb8SHans Verkuil 3142b44b2e06SPablo Anton if (adv76xx_s_detect_tx_5v_ctrl(sd)) { 314354450f59SHans Verkuil err = -ENODEV; 314454450f59SHans Verkuil goto err_hdl; 314554450f59SHans Verkuil } 314654450f59SHans Verkuil 3147b44b2e06SPablo Anton for (i = 1; i < ADV76XX_PAGE_MAX; ++i) { 314805cacb17SLaurent Pinchart if (!(BIT(i) & state->info->page_mask)) 314905cacb17SLaurent Pinchart continue; 315005cacb17SLaurent Pinchart 315105cacb17SLaurent Pinchart state->i2c_clients[i] = 3152b44b2e06SPablo Anton adv76xx_dummy_client(sd, state->pdata.i2c_addresses[i], 315305cacb17SLaurent Pinchart 0xf2 + i); 315405cacb17SLaurent Pinchart if (state->i2c_clients[i] == NULL) { 315554450f59SHans Verkuil err = -ENOMEM; 315605cacb17SLaurent Pinchart v4l2_err(sd, "failed to create i2c client %u\n", i); 315754450f59SHans Verkuil goto err_i2c; 315854450f59SHans Verkuil } 315905cacb17SLaurent Pinchart } 316054450f59SHans Verkuil 316154450f59SHans Verkuil /* work queues */ 316254450f59SHans Verkuil state->work_queues = create_singlethread_workqueue(client->name); 316354450f59SHans Verkuil if (!state->work_queues) { 316454450f59SHans Verkuil v4l2_err(sd, "Could not create work queue\n"); 316554450f59SHans Verkuil err = -ENOMEM; 316654450f59SHans Verkuil goto err_i2c; 316754450f59SHans Verkuil } 316854450f59SHans Verkuil 316954450f59SHans Verkuil INIT_DELAYED_WORK(&state->delayed_work_enable_hotplug, 3170b44b2e06SPablo Anton adv76xx_delayed_work_enable_hotplug); 317154450f59SHans Verkuil 3172c784b1e2SLaurent Pinchart state->source_pad = state->info->num_dv_ports 3173c784b1e2SLaurent Pinchart + (state->info->has_afe ? 2 : 0); 3174c784b1e2SLaurent Pinchart for (i = 0; i < state->source_pad; ++i) 3175c784b1e2SLaurent Pinchart state->pads[i].flags = MEDIA_PAD_FL_SINK; 3176c784b1e2SLaurent Pinchart state->pads[state->source_pad].flags = MEDIA_PAD_FL_SOURCE; 3177c784b1e2SLaurent Pinchart 3178c784b1e2SLaurent Pinchart err = media_entity_init(&sd->entity, state->source_pad + 1, 3179c784b1e2SLaurent Pinchart state->pads, 0); 318054450f59SHans Verkuil if (err) 318154450f59SHans Verkuil goto err_work_queues; 318254450f59SHans Verkuil 3183f862f57dSPablo Anton /* Configure regmaps */ 3184f862f57dSPablo Anton err = configure_regmaps(state); 3185f862f57dSPablo Anton if (err) 3186f862f57dSPablo Anton goto err_entity; 3187f862f57dSPablo Anton 3188b44b2e06SPablo Anton err = adv76xx_core_init(sd); 318954450f59SHans Verkuil if (err) 319054450f59SHans Verkuil goto err_entity; 319154450f59SHans Verkuil v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name, 319254450f59SHans Verkuil client->addr << 1, client->adapter->name); 3193bedc3939SLars-Peter Clausen 3194bedc3939SLars-Peter Clausen err = v4l2_async_register_subdev(sd); 3195bedc3939SLars-Peter Clausen if (err) 3196bedc3939SLars-Peter Clausen goto err_entity; 3197bedc3939SLars-Peter Clausen 319854450f59SHans Verkuil return 0; 319954450f59SHans Verkuil 320054450f59SHans Verkuil err_entity: 320154450f59SHans Verkuil media_entity_cleanup(&sd->entity); 320254450f59SHans Verkuil err_work_queues: 320354450f59SHans Verkuil cancel_delayed_work(&state->delayed_work_enable_hotplug); 320454450f59SHans Verkuil destroy_workqueue(state->work_queues); 320554450f59SHans Verkuil err_i2c: 3206b44b2e06SPablo Anton adv76xx_unregister_clients(state); 320754450f59SHans Verkuil err_hdl: 320854450f59SHans Verkuil v4l2_ctrl_handler_free(hdl); 320954450f59SHans Verkuil return err; 321054450f59SHans Verkuil } 321154450f59SHans Verkuil 321254450f59SHans Verkuil /* ----------------------------------------------------------------------- */ 321354450f59SHans Verkuil 3214b44b2e06SPablo Anton static int adv76xx_remove(struct i2c_client *client) 321554450f59SHans Verkuil { 321654450f59SHans Verkuil struct v4l2_subdev *sd = i2c_get_clientdata(client); 3217b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 321854450f59SHans Verkuil 321954450f59SHans Verkuil cancel_delayed_work(&state->delayed_work_enable_hotplug); 322054450f59SHans Verkuil destroy_workqueue(state->work_queues); 3221bedc3939SLars-Peter Clausen v4l2_async_unregister_subdev(sd); 322254450f59SHans Verkuil media_entity_cleanup(&sd->entity); 3223b44b2e06SPablo Anton adv76xx_unregister_clients(to_state(sd)); 322454450f59SHans Verkuil v4l2_ctrl_handler_free(sd->ctrl_handler); 322554450f59SHans Verkuil return 0; 322654450f59SHans Verkuil } 322754450f59SHans Verkuil 322854450f59SHans Verkuil /* ----------------------------------------------------------------------- */ 322954450f59SHans Verkuil 3230b44b2e06SPablo Anton static struct i2c_driver adv76xx_driver = { 323154450f59SHans Verkuil .driver = { 323254450f59SHans Verkuil .owner = THIS_MODULE, 323354450f59SHans Verkuil .name = "adv7604", 3234b44b2e06SPablo Anton .of_match_table = of_match_ptr(adv76xx_of_id), 323554450f59SHans Verkuil }, 3236b44b2e06SPablo Anton .probe = adv76xx_probe, 3237b44b2e06SPablo Anton .remove = adv76xx_remove, 3238b44b2e06SPablo Anton .id_table = adv76xx_i2c_id, 323954450f59SHans Verkuil }; 324054450f59SHans Verkuil 3241b44b2e06SPablo Anton module_i2c_driver(adv76xx_driver); 3242