154450f59SHans Verkuil /* 254450f59SHans Verkuil * adv7604 - Analog Devices ADV7604 video decoder driver 354450f59SHans Verkuil * 454450f59SHans Verkuil * Copyright 2012 Cisco Systems, Inc. and/or its affiliates. All rights reserved. 554450f59SHans Verkuil * 654450f59SHans Verkuil * This program is free software; you may redistribute it and/or modify 754450f59SHans Verkuil * it under the terms of the GNU General Public License as published by 854450f59SHans Verkuil * the Free Software Foundation; version 2 of the License. 954450f59SHans Verkuil * 1054450f59SHans Verkuil * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 1154450f59SHans Verkuil * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 1254450f59SHans Verkuil * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 1354450f59SHans Verkuil * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 1454450f59SHans Verkuil * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 1554450f59SHans Verkuil * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 1654450f59SHans Verkuil * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 1754450f59SHans Verkuil * SOFTWARE. 1854450f59SHans Verkuil * 1954450f59SHans Verkuil */ 2054450f59SHans Verkuil 2154450f59SHans Verkuil /* 2254450f59SHans Verkuil * References (c = chapter, p = page): 2354450f59SHans Verkuil * REF_01 - Analog devices, ADV7604, Register Settings Recommendations, 2454450f59SHans Verkuil * Revision 2.5, June 2010 2554450f59SHans Verkuil * REF_02 - Analog devices, Register map documentation, Documentation of 2654450f59SHans Verkuil * the register maps, Software manual, Rev. F, June 2010 2754450f59SHans Verkuil * REF_03 - Analog devices, ADV7604, Hardware Manual, Rev. F, August 2010 2854450f59SHans Verkuil */ 2954450f59SHans Verkuil 30c72a53ceSLaurent Pinchart #include <linux/delay.h> 31e9d50e9eSLaurent Pinchart #include <linux/gpio/consumer.h> 32c72a53ceSLaurent Pinchart #include <linux/i2c.h> 3354450f59SHans Verkuil #include <linux/kernel.h> 3454450f59SHans Verkuil #include <linux/module.h> 3554450f59SHans Verkuil #include <linux/slab.h> 36c72a53ceSLaurent Pinchart #include <linux/v4l2-dv-timings.h> 3754450f59SHans Verkuil #include <linux/videodev2.h> 3854450f59SHans Verkuil #include <linux/workqueue.h> 39c72a53ceSLaurent Pinchart 4054450f59SHans Verkuil #include <media/adv7604.h> 41c72a53ceSLaurent Pinchart #include <media/v4l2-ctrls.h> 42c72a53ceSLaurent Pinchart #include <media/v4l2-device.h> 43c72a53ceSLaurent Pinchart #include <media/v4l2-dv-timings.h> 446fa88045SLaurent Pinchart #include <media/v4l2-of.h> 4554450f59SHans Verkuil 4654450f59SHans Verkuil static int debug; 4754450f59SHans Verkuil module_param(debug, int, 0644); 4854450f59SHans Verkuil MODULE_PARM_DESC(debug, "debug level (0-2)"); 4954450f59SHans Verkuil 5054450f59SHans Verkuil MODULE_DESCRIPTION("Analog Devices ADV7604 video decoder driver"); 5154450f59SHans Verkuil MODULE_AUTHOR("Hans Verkuil <hans.verkuil@cisco.com>"); 5254450f59SHans Verkuil MODULE_AUTHOR("Mats Randgaard <mats.randgaard@cisco.com>"); 5354450f59SHans Verkuil MODULE_LICENSE("GPL"); 5454450f59SHans Verkuil 5554450f59SHans Verkuil /* ADV7604 system clock frequency */ 56b44b2e06SPablo Anton #define ADV76XX_FSC (28636360) 5754450f59SHans Verkuil 58b44b2e06SPablo Anton #define ADV76XX_RGB_OUT (1 << 1) 59539b33b0SLaurent Pinchart 60b44b2e06SPablo Anton #define ADV76XX_OP_FORMAT_SEL_8BIT (0 << 0) 61539b33b0SLaurent Pinchart #define ADV7604_OP_FORMAT_SEL_10BIT (1 << 0) 62b44b2e06SPablo Anton #define ADV76XX_OP_FORMAT_SEL_12BIT (2 << 0) 63539b33b0SLaurent Pinchart 64b44b2e06SPablo Anton #define ADV76XX_OP_MODE_SEL_SDR_422 (0 << 5) 65539b33b0SLaurent Pinchart #define ADV7604_OP_MODE_SEL_DDR_422 (1 << 5) 66b44b2e06SPablo Anton #define ADV76XX_OP_MODE_SEL_SDR_444 (2 << 5) 67539b33b0SLaurent Pinchart #define ADV7604_OP_MODE_SEL_DDR_444 (3 << 5) 68b44b2e06SPablo Anton #define ADV76XX_OP_MODE_SEL_SDR_422_2X (4 << 5) 69539b33b0SLaurent Pinchart #define ADV7604_OP_MODE_SEL_ADI_CM (5 << 5) 70539b33b0SLaurent Pinchart 71b44b2e06SPablo Anton #define ADV76XX_OP_CH_SEL_GBR (0 << 5) 72b44b2e06SPablo Anton #define ADV76XX_OP_CH_SEL_GRB (1 << 5) 73b44b2e06SPablo Anton #define ADV76XX_OP_CH_SEL_BGR (2 << 5) 74b44b2e06SPablo Anton #define ADV76XX_OP_CH_SEL_RGB (3 << 5) 75b44b2e06SPablo Anton #define ADV76XX_OP_CH_SEL_BRG (4 << 5) 76b44b2e06SPablo Anton #define ADV76XX_OP_CH_SEL_RBG (5 << 5) 77539b33b0SLaurent Pinchart 78b44b2e06SPablo Anton #define ADV76XX_OP_SWAP_CB_CR (1 << 0) 79539b33b0SLaurent Pinchart 80b44b2e06SPablo Anton enum adv76xx_type { 81d42010a1SLars-Peter Clausen ADV7604, 82d42010a1SLars-Peter Clausen ADV7611, 83d42010a1SLars-Peter Clausen }; 84d42010a1SLars-Peter Clausen 85b44b2e06SPablo Anton struct adv76xx_reg_seq { 86d42010a1SLars-Peter Clausen unsigned int reg; 87d42010a1SLars-Peter Clausen u8 val; 88d42010a1SLars-Peter Clausen }; 89d42010a1SLars-Peter Clausen 90b44b2e06SPablo Anton struct adv76xx_format_info { 91f5fe58fdSBoris BREZILLON u32 code; 92539b33b0SLaurent Pinchart u8 op_ch_sel; 93539b33b0SLaurent Pinchart bool rgb_out; 94539b33b0SLaurent Pinchart bool swap_cb_cr; 95539b33b0SLaurent Pinchart u8 op_format_sel; 96539b33b0SLaurent Pinchart }; 97539b33b0SLaurent Pinchart 98b44b2e06SPablo Anton struct adv76xx_chip_info { 99b44b2e06SPablo Anton enum adv76xx_type type; 100d42010a1SLars-Peter Clausen 101d42010a1SLars-Peter Clausen bool has_afe; 102d42010a1SLars-Peter Clausen unsigned int max_port; 103d42010a1SLars-Peter Clausen unsigned int num_dv_ports; 104d42010a1SLars-Peter Clausen 105d42010a1SLars-Peter Clausen unsigned int edid_enable_reg; 106d42010a1SLars-Peter Clausen unsigned int edid_status_reg; 107d42010a1SLars-Peter Clausen unsigned int lcf_reg; 108d42010a1SLars-Peter Clausen 109d42010a1SLars-Peter Clausen unsigned int cable_det_mask; 110d42010a1SLars-Peter Clausen unsigned int tdms_lock_mask; 111d42010a1SLars-Peter Clausen unsigned int fmt_change_digital_mask; 11280f4944eSjean-michel.hautbois@vodalys.com unsigned int cp_csc; 113d42010a1SLars-Peter Clausen 114b44b2e06SPablo Anton const struct adv76xx_format_info *formats; 115539b33b0SLaurent Pinchart unsigned int nformats; 116539b33b0SLaurent Pinchart 117d42010a1SLars-Peter Clausen void (*set_termination)(struct v4l2_subdev *sd, bool enable); 118d42010a1SLars-Peter Clausen void (*setup_irqs)(struct v4l2_subdev *sd); 119d42010a1SLars-Peter Clausen unsigned int (*read_hdmi_pixelclock)(struct v4l2_subdev *sd); 120d42010a1SLars-Peter Clausen unsigned int (*read_cable_det)(struct v4l2_subdev *sd); 121d42010a1SLars-Peter Clausen 122d42010a1SLars-Peter Clausen /* 0 = AFE, 1 = HDMI */ 123b44b2e06SPablo Anton const struct adv76xx_reg_seq *recommended_settings[2]; 124d42010a1SLars-Peter Clausen unsigned int num_recommended_settings[2]; 125d42010a1SLars-Peter Clausen 126d42010a1SLars-Peter Clausen unsigned long page_mask; 1275380baafSjean-michel.hautbois@vodalys.com 1285380baafSjean-michel.hautbois@vodalys.com /* Masks for timings */ 1295380baafSjean-michel.hautbois@vodalys.com unsigned int linewidth_mask; 1305380baafSjean-michel.hautbois@vodalys.com unsigned int field0_height_mask; 1315380baafSjean-michel.hautbois@vodalys.com unsigned int field1_height_mask; 1325380baafSjean-michel.hautbois@vodalys.com unsigned int hfrontporch_mask; 1335380baafSjean-michel.hautbois@vodalys.com unsigned int hsync_mask; 1345380baafSjean-michel.hautbois@vodalys.com unsigned int hbackporch_mask; 1355380baafSjean-michel.hautbois@vodalys.com unsigned int field0_vfrontporch_mask; 1365380baafSjean-michel.hautbois@vodalys.com unsigned int field1_vfrontporch_mask; 1375380baafSjean-michel.hautbois@vodalys.com unsigned int field0_vsync_mask; 1385380baafSjean-michel.hautbois@vodalys.com unsigned int field1_vsync_mask; 1395380baafSjean-michel.hautbois@vodalys.com unsigned int field0_vbackporch_mask; 1405380baafSjean-michel.hautbois@vodalys.com unsigned int field1_vbackporch_mask; 141d42010a1SLars-Peter Clausen }; 142d42010a1SLars-Peter Clausen 14354450f59SHans Verkuil /* 14454450f59SHans Verkuil ********************************************************************** 14554450f59SHans Verkuil * 14654450f59SHans Verkuil * Arrays with configuration parameters for the ADV7604 14754450f59SHans Verkuil * 14854450f59SHans Verkuil ********************************************************************** 14954450f59SHans Verkuil */ 150c784b1e2SLaurent Pinchart 151b44b2e06SPablo Anton struct adv76xx_state { 152b44b2e06SPablo Anton const struct adv76xx_chip_info *info; 153b44b2e06SPablo Anton struct adv76xx_platform_data pdata; 154539b33b0SLaurent Pinchart 155e9d50e9eSLaurent Pinchart struct gpio_desc *hpd_gpio[4]; 156e9d50e9eSLaurent Pinchart 15754450f59SHans Verkuil struct v4l2_subdev sd; 158b44b2e06SPablo Anton struct media_pad pads[ADV76XX_PAD_MAX]; 159c784b1e2SLaurent Pinchart unsigned int source_pad; 160539b33b0SLaurent Pinchart 16154450f59SHans Verkuil struct v4l2_ctrl_handler hdl; 162539b33b0SLaurent Pinchart 163b44b2e06SPablo Anton enum adv76xx_pad selected_input; 164539b33b0SLaurent Pinchart 16554450f59SHans Verkuil struct v4l2_dv_timings timings; 166b44b2e06SPablo Anton const struct adv76xx_format_info *format; 167539b33b0SLaurent Pinchart 1684a31a93aSMats Randgaard struct { 16954450f59SHans Verkuil u8 edid[256]; 1704a31a93aSMats Randgaard u32 present; 1714a31a93aSMats Randgaard unsigned blocks; 1724a31a93aSMats Randgaard } edid; 173dd08beb9SMats Randgaard u16 spa_port_a[2]; 17454450f59SHans Verkuil struct v4l2_fract aspect_ratio; 17554450f59SHans Verkuil u32 rgb_quantization_range; 17654450f59SHans Verkuil struct workqueue_struct *work_queues; 17754450f59SHans Verkuil struct delayed_work delayed_work_enable_hotplug; 178cf9afb1dSHans Verkuil bool restart_stdi_once; 17954450f59SHans Verkuil 18054450f59SHans Verkuil /* i2c clients */ 181b44b2e06SPablo Anton struct i2c_client *i2c_clients[ADV76XX_PAGE_MAX]; 18254450f59SHans Verkuil 18354450f59SHans Verkuil /* controls */ 18454450f59SHans Verkuil struct v4l2_ctrl *detect_tx_5v_ctrl; 18554450f59SHans Verkuil struct v4l2_ctrl *analog_sampling_phase_ctrl; 18654450f59SHans Verkuil struct v4l2_ctrl *free_run_color_manual_ctrl; 18754450f59SHans Verkuil struct v4l2_ctrl *free_run_color_ctrl; 18854450f59SHans Verkuil struct v4l2_ctrl *rgb_quantization_range_ctrl; 18954450f59SHans Verkuil }; 19054450f59SHans Verkuil 191b44b2e06SPablo Anton static bool adv76xx_has_afe(struct adv76xx_state *state) 192d42010a1SLars-Peter Clausen { 193d42010a1SLars-Peter Clausen return state->info->has_afe; 194d42010a1SLars-Peter Clausen } 195d42010a1SLars-Peter Clausen 19654450f59SHans Verkuil /* Supported CEA and DMT timings */ 197b44b2e06SPablo Anton static const struct v4l2_dv_timings adv76xx_timings[] = { 19854450f59SHans Verkuil V4L2_DV_BT_CEA_720X480P59_94, 19954450f59SHans Verkuil V4L2_DV_BT_CEA_720X576P50, 20054450f59SHans Verkuil V4L2_DV_BT_CEA_1280X720P24, 20154450f59SHans Verkuil V4L2_DV_BT_CEA_1280X720P25, 20254450f59SHans Verkuil V4L2_DV_BT_CEA_1280X720P50, 20354450f59SHans Verkuil V4L2_DV_BT_CEA_1280X720P60, 20454450f59SHans Verkuil V4L2_DV_BT_CEA_1920X1080P24, 20554450f59SHans Verkuil V4L2_DV_BT_CEA_1920X1080P25, 20654450f59SHans Verkuil V4L2_DV_BT_CEA_1920X1080P30, 20754450f59SHans Verkuil V4L2_DV_BT_CEA_1920X1080P50, 20854450f59SHans Verkuil V4L2_DV_BT_CEA_1920X1080P60, 20954450f59SHans Verkuil 210ccbd5bc4SHans Verkuil /* sorted by DMT ID */ 21154450f59SHans Verkuil V4L2_DV_BT_DMT_640X350P85, 21254450f59SHans Verkuil V4L2_DV_BT_DMT_640X400P85, 21354450f59SHans Verkuil V4L2_DV_BT_DMT_720X400P85, 21454450f59SHans Verkuil V4L2_DV_BT_DMT_640X480P60, 21554450f59SHans Verkuil V4L2_DV_BT_DMT_640X480P72, 21654450f59SHans Verkuil V4L2_DV_BT_DMT_640X480P75, 21754450f59SHans Verkuil V4L2_DV_BT_DMT_640X480P85, 21854450f59SHans Verkuil V4L2_DV_BT_DMT_800X600P56, 21954450f59SHans Verkuil V4L2_DV_BT_DMT_800X600P60, 22054450f59SHans Verkuil V4L2_DV_BT_DMT_800X600P72, 22154450f59SHans Verkuil V4L2_DV_BT_DMT_800X600P75, 22254450f59SHans Verkuil V4L2_DV_BT_DMT_800X600P85, 22354450f59SHans Verkuil V4L2_DV_BT_DMT_848X480P60, 22454450f59SHans Verkuil V4L2_DV_BT_DMT_1024X768P60, 22554450f59SHans Verkuil V4L2_DV_BT_DMT_1024X768P70, 22654450f59SHans Verkuil V4L2_DV_BT_DMT_1024X768P75, 22754450f59SHans Verkuil V4L2_DV_BT_DMT_1024X768P85, 22854450f59SHans Verkuil V4L2_DV_BT_DMT_1152X864P75, 22954450f59SHans Verkuil V4L2_DV_BT_DMT_1280X768P60_RB, 23054450f59SHans Verkuil V4L2_DV_BT_DMT_1280X768P60, 23154450f59SHans Verkuil V4L2_DV_BT_DMT_1280X768P75, 23254450f59SHans Verkuil V4L2_DV_BT_DMT_1280X768P85, 23354450f59SHans Verkuil V4L2_DV_BT_DMT_1280X800P60_RB, 23454450f59SHans Verkuil V4L2_DV_BT_DMT_1280X800P60, 23554450f59SHans Verkuil V4L2_DV_BT_DMT_1280X800P75, 23654450f59SHans Verkuil V4L2_DV_BT_DMT_1280X800P85, 23754450f59SHans Verkuil V4L2_DV_BT_DMT_1280X960P60, 23854450f59SHans Verkuil V4L2_DV_BT_DMT_1280X960P85, 23954450f59SHans Verkuil V4L2_DV_BT_DMT_1280X1024P60, 24054450f59SHans Verkuil V4L2_DV_BT_DMT_1280X1024P75, 24154450f59SHans Verkuil V4L2_DV_BT_DMT_1280X1024P85, 24254450f59SHans Verkuil V4L2_DV_BT_DMT_1360X768P60, 24354450f59SHans Verkuil V4L2_DV_BT_DMT_1400X1050P60_RB, 24454450f59SHans Verkuil V4L2_DV_BT_DMT_1400X1050P60, 24554450f59SHans Verkuil V4L2_DV_BT_DMT_1400X1050P75, 24654450f59SHans Verkuil V4L2_DV_BT_DMT_1400X1050P85, 24754450f59SHans Verkuil V4L2_DV_BT_DMT_1440X900P60_RB, 24854450f59SHans Verkuil V4L2_DV_BT_DMT_1440X900P60, 24954450f59SHans Verkuil V4L2_DV_BT_DMT_1600X1200P60, 25054450f59SHans Verkuil V4L2_DV_BT_DMT_1680X1050P60_RB, 25154450f59SHans Verkuil V4L2_DV_BT_DMT_1680X1050P60, 25254450f59SHans Verkuil V4L2_DV_BT_DMT_1792X1344P60, 25354450f59SHans Verkuil V4L2_DV_BT_DMT_1856X1392P60, 25454450f59SHans Verkuil V4L2_DV_BT_DMT_1920X1200P60_RB, 255547ed542SMartin Bugge V4L2_DV_BT_DMT_1366X768P60_RB, 25654450f59SHans Verkuil V4L2_DV_BT_DMT_1366X768P60, 25754450f59SHans Verkuil V4L2_DV_BT_DMT_1920X1080P60, 25854450f59SHans Verkuil { }, 25954450f59SHans Verkuil }; 26054450f59SHans Verkuil 261b44b2e06SPablo Anton struct adv76xx_video_standards { 262ccbd5bc4SHans Verkuil struct v4l2_dv_timings timings; 263ccbd5bc4SHans Verkuil u8 vid_std; 264ccbd5bc4SHans Verkuil u8 v_freq; 265ccbd5bc4SHans Verkuil }; 266ccbd5bc4SHans Verkuil 267ccbd5bc4SHans Verkuil /* sorted by number of lines */ 268b44b2e06SPablo Anton static const struct adv76xx_video_standards adv7604_prim_mode_comp[] = { 269ccbd5bc4SHans Verkuil /* { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 }, TODO flickering */ 270ccbd5bc4SHans Verkuil { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 }, 271ccbd5bc4SHans Verkuil { V4L2_DV_BT_CEA_1280X720P50, 0x19, 0x01 }, 272ccbd5bc4SHans Verkuil { V4L2_DV_BT_CEA_1280X720P60, 0x19, 0x00 }, 273ccbd5bc4SHans Verkuil { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 }, 274ccbd5bc4SHans Verkuil { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 }, 275ccbd5bc4SHans Verkuil { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 }, 276ccbd5bc4SHans Verkuil { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 }, 277ccbd5bc4SHans Verkuil { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 }, 278ccbd5bc4SHans Verkuil /* TODO add 1920x1080P60_RB (CVT timing) */ 279ccbd5bc4SHans Verkuil { }, 280ccbd5bc4SHans Verkuil }; 281ccbd5bc4SHans Verkuil 282ccbd5bc4SHans Verkuil /* sorted by number of lines */ 283b44b2e06SPablo Anton static const struct adv76xx_video_standards adv7604_prim_mode_gr[] = { 284ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 }, 285ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 }, 286ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 }, 287ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 }, 288ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 }, 289ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 }, 290ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 }, 291ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 }, 292ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 }, 293ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 }, 294ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 }, 295ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 }, 296ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 }, 297ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 }, 298ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 }, 299ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_1360X768P60, 0x12, 0x00 }, 300ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_1366X768P60, 0x13, 0x00 }, 301ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_1400X1050P60, 0x14, 0x00 }, 302ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_1400X1050P75, 0x15, 0x00 }, 303ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_1600X1200P60, 0x16, 0x00 }, /* TODO not tested */ 304ccbd5bc4SHans Verkuil /* TODO add 1600X1200P60_RB (not a DMT timing) */ 305ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_1680X1050P60, 0x18, 0x00 }, 306ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_1920X1200P60_RB, 0x19, 0x00 }, /* TODO not tested */ 307ccbd5bc4SHans Verkuil { }, 308ccbd5bc4SHans Verkuil }; 309ccbd5bc4SHans Verkuil 310ccbd5bc4SHans Verkuil /* sorted by number of lines */ 311b44b2e06SPablo Anton static const struct adv76xx_video_standards adv76xx_prim_mode_hdmi_comp[] = { 312ccbd5bc4SHans Verkuil { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 }, 313ccbd5bc4SHans Verkuil { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 }, 314ccbd5bc4SHans Verkuil { V4L2_DV_BT_CEA_1280X720P50, 0x13, 0x01 }, 315ccbd5bc4SHans Verkuil { V4L2_DV_BT_CEA_1280X720P60, 0x13, 0x00 }, 316ccbd5bc4SHans Verkuil { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 }, 317ccbd5bc4SHans Verkuil { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 }, 318ccbd5bc4SHans Verkuil { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 }, 319ccbd5bc4SHans Verkuil { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 }, 320ccbd5bc4SHans Verkuil { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 }, 321ccbd5bc4SHans Verkuil { }, 322ccbd5bc4SHans Verkuil }; 323ccbd5bc4SHans Verkuil 324ccbd5bc4SHans Verkuil /* sorted by number of lines */ 325b44b2e06SPablo Anton static const struct adv76xx_video_standards adv76xx_prim_mode_hdmi_gr[] = { 326ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 }, 327ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 }, 328ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 }, 329ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 }, 330ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 }, 331ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 }, 332ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 }, 333ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 }, 334ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 }, 335ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 }, 336ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 }, 337ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 }, 338ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 }, 339ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 }, 340ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 }, 341ccbd5bc4SHans Verkuil { }, 342ccbd5bc4SHans Verkuil }; 343ccbd5bc4SHans Verkuil 34454450f59SHans Verkuil /* ----------------------------------------------------------------------- */ 34554450f59SHans Verkuil 346b44b2e06SPablo Anton static inline struct adv76xx_state *to_state(struct v4l2_subdev *sd) 34754450f59SHans Verkuil { 348b44b2e06SPablo Anton return container_of(sd, struct adv76xx_state, sd); 34954450f59SHans Verkuil } 35054450f59SHans Verkuil 35154450f59SHans Verkuil static inline unsigned htotal(const struct v4l2_bt_timings *t) 35254450f59SHans Verkuil { 353eacf8f9aSHans Verkuil return V4L2_DV_BT_FRAME_WIDTH(t); 35454450f59SHans Verkuil } 35554450f59SHans Verkuil 35654450f59SHans Verkuil static inline unsigned vtotal(const struct v4l2_bt_timings *t) 35754450f59SHans Verkuil { 358eacf8f9aSHans Verkuil return V4L2_DV_BT_FRAME_HEIGHT(t); 35954450f59SHans Verkuil } 36054450f59SHans Verkuil 36154450f59SHans Verkuil /* ----------------------------------------------------------------------- */ 36254450f59SHans Verkuil 36354450f59SHans Verkuil static s32 adv_smbus_read_byte_data_check(struct i2c_client *client, 36454450f59SHans Verkuil u8 command, bool check) 36554450f59SHans Verkuil { 36654450f59SHans Verkuil union i2c_smbus_data data; 36754450f59SHans Verkuil 36854450f59SHans Verkuil if (!i2c_smbus_xfer(client->adapter, client->addr, client->flags, 36954450f59SHans Verkuil I2C_SMBUS_READ, command, 37054450f59SHans Verkuil I2C_SMBUS_BYTE_DATA, &data)) 37154450f59SHans Verkuil return data.byte; 37254450f59SHans Verkuil if (check) 37354450f59SHans Verkuil v4l_err(client, "error reading %02x, %02x\n", 37454450f59SHans Verkuil client->addr, command); 37554450f59SHans Verkuil return -EIO; 37654450f59SHans Verkuil } 37754450f59SHans Verkuil 378b44b2e06SPablo Anton static s32 adv_smbus_read_byte_data(struct adv76xx_state *state, 379b44b2e06SPablo Anton enum adv76xx_page page, u8 command) 38054450f59SHans Verkuil { 38105cacb17SLaurent Pinchart return adv_smbus_read_byte_data_check(state->i2c_clients[page], 38205cacb17SLaurent Pinchart command, true); 38354450f59SHans Verkuil } 38454450f59SHans Verkuil 385b44b2e06SPablo Anton static s32 adv_smbus_write_byte_data(struct adv76xx_state *state, 386b44b2e06SPablo Anton enum adv76xx_page page, u8 command, 38705cacb17SLaurent Pinchart u8 value) 38854450f59SHans Verkuil { 38905cacb17SLaurent Pinchart struct i2c_client *client = state->i2c_clients[page]; 39054450f59SHans Verkuil union i2c_smbus_data data; 39154450f59SHans Verkuil int err; 39254450f59SHans Verkuil int i; 39354450f59SHans Verkuil 39454450f59SHans Verkuil data.byte = value; 39554450f59SHans Verkuil for (i = 0; i < 3; i++) { 39654450f59SHans Verkuil err = i2c_smbus_xfer(client->adapter, client->addr, 39754450f59SHans Verkuil client->flags, 39854450f59SHans Verkuil I2C_SMBUS_WRITE, command, 39954450f59SHans Verkuil I2C_SMBUS_BYTE_DATA, &data); 40054450f59SHans Verkuil if (!err) 40154450f59SHans Verkuil break; 40254450f59SHans Verkuil } 40354450f59SHans Verkuil if (err < 0) 40454450f59SHans Verkuil v4l_err(client, "error writing %02x, %02x, %02x\n", 40554450f59SHans Verkuil client->addr, command, value); 40654450f59SHans Verkuil return err; 40754450f59SHans Verkuil } 40854450f59SHans Verkuil 409b44b2e06SPablo Anton static s32 adv_smbus_write_i2c_block_data(struct adv76xx_state *state, 410b44b2e06SPablo Anton enum adv76xx_page page, u8 command, 41105cacb17SLaurent Pinchart unsigned length, const u8 *values) 41254450f59SHans Verkuil { 41305cacb17SLaurent Pinchart struct i2c_client *client = state->i2c_clients[page]; 41454450f59SHans Verkuil union i2c_smbus_data data; 41554450f59SHans Verkuil 41654450f59SHans Verkuil if (length > I2C_SMBUS_BLOCK_MAX) 41754450f59SHans Verkuil length = I2C_SMBUS_BLOCK_MAX; 41854450f59SHans Verkuil data.block[0] = length; 41954450f59SHans Verkuil memcpy(data.block + 1, values, length); 42054450f59SHans Verkuil return i2c_smbus_xfer(client->adapter, client->addr, client->flags, 42154450f59SHans Verkuil I2C_SMBUS_WRITE, command, 42254450f59SHans Verkuil I2C_SMBUS_I2C_BLOCK_DATA, &data); 42354450f59SHans Verkuil } 42454450f59SHans Verkuil 42554450f59SHans Verkuil /* ----------------------------------------------------------------------- */ 42654450f59SHans Verkuil 42754450f59SHans Verkuil static inline int io_read(struct v4l2_subdev *sd, u8 reg) 42854450f59SHans Verkuil { 429b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 43054450f59SHans Verkuil 431b44b2e06SPablo Anton return adv_smbus_read_byte_data(state, ADV76XX_PAGE_IO, reg); 43254450f59SHans Verkuil } 43354450f59SHans Verkuil 43454450f59SHans Verkuil static inline int io_write(struct v4l2_subdev *sd, u8 reg, u8 val) 43554450f59SHans Verkuil { 436b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 43754450f59SHans Verkuil 438b44b2e06SPablo Anton return adv_smbus_write_byte_data(state, ADV76XX_PAGE_IO, reg, val); 43954450f59SHans Verkuil } 44054450f59SHans Verkuil 44122d97e56SLaurent Pinchart static inline int io_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) 44254450f59SHans Verkuil { 44322d97e56SLaurent Pinchart return io_write(sd, reg, (io_read(sd, reg) & ~mask) | val); 44454450f59SHans Verkuil } 44554450f59SHans Verkuil 44654450f59SHans Verkuil static inline int avlink_read(struct v4l2_subdev *sd, u8 reg) 44754450f59SHans Verkuil { 448b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 44954450f59SHans Verkuil 45005cacb17SLaurent Pinchart return adv_smbus_read_byte_data(state, ADV7604_PAGE_AVLINK, reg); 45154450f59SHans Verkuil } 45254450f59SHans Verkuil 45354450f59SHans Verkuil static inline int avlink_write(struct v4l2_subdev *sd, u8 reg, u8 val) 45454450f59SHans Verkuil { 455b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 45654450f59SHans Verkuil 45705cacb17SLaurent Pinchart return adv_smbus_write_byte_data(state, ADV7604_PAGE_AVLINK, reg, val); 45854450f59SHans Verkuil } 45954450f59SHans Verkuil 46054450f59SHans Verkuil static inline int cec_read(struct v4l2_subdev *sd, u8 reg) 46154450f59SHans Verkuil { 462b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 46354450f59SHans Verkuil 464b44b2e06SPablo Anton return adv_smbus_read_byte_data(state, ADV76XX_PAGE_CEC, reg); 46554450f59SHans Verkuil } 46654450f59SHans Verkuil 46754450f59SHans Verkuil static inline int cec_write(struct v4l2_subdev *sd, u8 reg, u8 val) 46854450f59SHans Verkuil { 469b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 47054450f59SHans Verkuil 471b44b2e06SPablo Anton return adv_smbus_write_byte_data(state, ADV76XX_PAGE_CEC, reg, val); 47254450f59SHans Verkuil } 47354450f59SHans Verkuil 47454450f59SHans Verkuil static inline int infoframe_read(struct v4l2_subdev *sd, u8 reg) 47554450f59SHans Verkuil { 476b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 47754450f59SHans Verkuil 478b44b2e06SPablo Anton return adv_smbus_read_byte_data(state, ADV76XX_PAGE_INFOFRAME, reg); 47954450f59SHans Verkuil } 48054450f59SHans Verkuil 48154450f59SHans Verkuil static inline int infoframe_write(struct v4l2_subdev *sd, u8 reg, u8 val) 48254450f59SHans Verkuil { 483b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 48454450f59SHans Verkuil 485b44b2e06SPablo Anton return adv_smbus_write_byte_data(state, ADV76XX_PAGE_INFOFRAME, 48605cacb17SLaurent Pinchart reg, val); 48754450f59SHans Verkuil } 48854450f59SHans Verkuil 48954450f59SHans Verkuil static inline int afe_read(struct v4l2_subdev *sd, u8 reg) 49054450f59SHans Verkuil { 491b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 49254450f59SHans Verkuil 493b44b2e06SPablo Anton return adv_smbus_read_byte_data(state, ADV76XX_PAGE_AFE, reg); 49454450f59SHans Verkuil } 49554450f59SHans Verkuil 49654450f59SHans Verkuil static inline int afe_write(struct v4l2_subdev *sd, u8 reg, u8 val) 49754450f59SHans Verkuil { 498b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 49954450f59SHans Verkuil 500b44b2e06SPablo Anton return adv_smbus_write_byte_data(state, ADV76XX_PAGE_AFE, reg, val); 50154450f59SHans Verkuil } 50254450f59SHans Verkuil 50354450f59SHans Verkuil static inline int rep_read(struct v4l2_subdev *sd, u8 reg) 50454450f59SHans Verkuil { 505b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 50654450f59SHans Verkuil 507b44b2e06SPablo Anton return adv_smbus_read_byte_data(state, ADV76XX_PAGE_REP, reg); 50854450f59SHans Verkuil } 50954450f59SHans Verkuil 51054450f59SHans Verkuil static inline int rep_write(struct v4l2_subdev *sd, u8 reg, u8 val) 51154450f59SHans Verkuil { 512b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 51354450f59SHans Verkuil 514b44b2e06SPablo Anton return adv_smbus_write_byte_data(state, ADV76XX_PAGE_REP, reg, val); 51554450f59SHans Verkuil } 51654450f59SHans Verkuil 51722d97e56SLaurent Pinchart static inline int rep_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) 51854450f59SHans Verkuil { 51922d97e56SLaurent Pinchart return rep_write(sd, reg, (rep_read(sd, reg) & ~mask) | val); 52054450f59SHans Verkuil } 52154450f59SHans Verkuil 52254450f59SHans Verkuil static inline int edid_read(struct v4l2_subdev *sd, u8 reg) 52354450f59SHans Verkuil { 524b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 52554450f59SHans Verkuil 526b44b2e06SPablo Anton return adv_smbus_read_byte_data(state, ADV76XX_PAGE_EDID, reg); 52754450f59SHans Verkuil } 52854450f59SHans Verkuil 52954450f59SHans Verkuil static inline int edid_write(struct v4l2_subdev *sd, u8 reg, u8 val) 53054450f59SHans Verkuil { 531b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 53254450f59SHans Verkuil 533b44b2e06SPablo Anton return adv_smbus_write_byte_data(state, ADV76XX_PAGE_EDID, reg, val); 53454450f59SHans Verkuil } 53554450f59SHans Verkuil 536dd08beb9SMats Randgaard static inline int edid_write_block(struct v4l2_subdev *sd, 537dd08beb9SMats Randgaard unsigned len, const u8 *val) 538dd08beb9SMats Randgaard { 539b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 540dd08beb9SMats Randgaard int err = 0; 541dd08beb9SMats Randgaard int i; 542dd08beb9SMats Randgaard 543dd08beb9SMats Randgaard v4l2_dbg(2, debug, sd, "%s: write EDID block (%d byte)\n", __func__, len); 544dd08beb9SMats Randgaard 545dd08beb9SMats Randgaard for (i = 0; !err && i < len; i += I2C_SMBUS_BLOCK_MAX) 546b44b2e06SPablo Anton err = adv_smbus_write_i2c_block_data(state, ADV76XX_PAGE_EDID, 54705cacb17SLaurent Pinchart i, I2C_SMBUS_BLOCK_MAX, val + i); 548dd08beb9SMats Randgaard return err; 549dd08beb9SMats Randgaard } 550dd08beb9SMats Randgaard 551b44b2e06SPablo Anton static void adv76xx_set_hpd(struct adv76xx_state *state, unsigned int hpd) 552e9d50e9eSLaurent Pinchart { 553e9d50e9eSLaurent Pinchart unsigned int i; 554e9d50e9eSLaurent Pinchart 555269bd132SUwe Kleine-König for (i = 0; i < state->info->num_dv_ports; ++i) 556e9d50e9eSLaurent Pinchart gpiod_set_value_cansleep(state->hpd_gpio[i], hpd & BIT(i)); 557e9d50e9eSLaurent Pinchart 558b44b2e06SPablo Anton v4l2_subdev_notify(&state->sd, ADV76XX_HOTPLUG, &hpd); 559e9d50e9eSLaurent Pinchart } 560e9d50e9eSLaurent Pinchart 561b44b2e06SPablo Anton static void adv76xx_delayed_work_enable_hotplug(struct work_struct *work) 56254450f59SHans Verkuil { 56354450f59SHans Verkuil struct delayed_work *dwork = to_delayed_work(work); 564b44b2e06SPablo Anton struct adv76xx_state *state = container_of(dwork, struct adv76xx_state, 56554450f59SHans Verkuil delayed_work_enable_hotplug); 56654450f59SHans Verkuil struct v4l2_subdev *sd = &state->sd; 56754450f59SHans Verkuil 56854450f59SHans Verkuil v4l2_dbg(2, debug, sd, "%s: enable hotplug\n", __func__); 56954450f59SHans Verkuil 570b44b2e06SPablo Anton adv76xx_set_hpd(state, state->edid.present); 57154450f59SHans Verkuil } 57254450f59SHans Verkuil 57354450f59SHans Verkuil static inline int hdmi_read(struct v4l2_subdev *sd, u8 reg) 57454450f59SHans Verkuil { 575b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 57654450f59SHans Verkuil 577b44b2e06SPablo Anton return adv_smbus_read_byte_data(state, ADV76XX_PAGE_HDMI, reg); 57854450f59SHans Verkuil } 57954450f59SHans Verkuil 58051182a94SLaurent Pinchart static u16 hdmi_read16(struct v4l2_subdev *sd, u8 reg, u16 mask) 58151182a94SLaurent Pinchart { 58251182a94SLaurent Pinchart return ((hdmi_read(sd, reg) << 8) | hdmi_read(sd, reg + 1)) & mask; 58351182a94SLaurent Pinchart } 58451182a94SLaurent Pinchart 58554450f59SHans Verkuil static inline int hdmi_write(struct v4l2_subdev *sd, u8 reg, u8 val) 58654450f59SHans Verkuil { 587b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 58854450f59SHans Verkuil 589b44b2e06SPablo Anton return adv_smbus_write_byte_data(state, ADV76XX_PAGE_HDMI, reg, val); 59054450f59SHans Verkuil } 59154450f59SHans Verkuil 59222d97e56SLaurent Pinchart static inline int hdmi_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) 5934a31a93aSMats Randgaard { 59422d97e56SLaurent Pinchart return hdmi_write(sd, reg, (hdmi_read(sd, reg) & ~mask) | val); 5954a31a93aSMats Randgaard } 5964a31a93aSMats Randgaard 59754450f59SHans Verkuil static inline int test_write(struct v4l2_subdev *sd, u8 reg, u8 val) 59854450f59SHans Verkuil { 599b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 60054450f59SHans Verkuil 601b44b2e06SPablo Anton return adv_smbus_write_byte_data(state, ADV76XX_PAGE_TEST, reg, val); 60254450f59SHans Verkuil } 60354450f59SHans Verkuil 60454450f59SHans Verkuil static inline int cp_read(struct v4l2_subdev *sd, u8 reg) 60554450f59SHans Verkuil { 606b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 60754450f59SHans Verkuil 608b44b2e06SPablo Anton return adv_smbus_read_byte_data(state, ADV76XX_PAGE_CP, reg); 60954450f59SHans Verkuil } 61054450f59SHans Verkuil 61151182a94SLaurent Pinchart static u16 cp_read16(struct v4l2_subdev *sd, u8 reg, u16 mask) 61251182a94SLaurent Pinchart { 61351182a94SLaurent Pinchart return ((cp_read(sd, reg) << 8) | cp_read(sd, reg + 1)) & mask; 61451182a94SLaurent Pinchart } 61551182a94SLaurent Pinchart 61654450f59SHans Verkuil static inline int cp_write(struct v4l2_subdev *sd, u8 reg, u8 val) 61754450f59SHans Verkuil { 618b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 61954450f59SHans Verkuil 620b44b2e06SPablo Anton return adv_smbus_write_byte_data(state, ADV76XX_PAGE_CP, reg, val); 62154450f59SHans Verkuil } 62254450f59SHans Verkuil 62322d97e56SLaurent Pinchart static inline int cp_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) 62454450f59SHans Verkuil { 62522d97e56SLaurent Pinchart return cp_write(sd, reg, (cp_read(sd, reg) & ~mask) | val); 62654450f59SHans Verkuil } 62754450f59SHans Verkuil 62854450f59SHans Verkuil static inline int vdp_read(struct v4l2_subdev *sd, u8 reg) 62954450f59SHans Verkuil { 630b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 63154450f59SHans Verkuil 63205cacb17SLaurent Pinchart return adv_smbus_read_byte_data(state, ADV7604_PAGE_VDP, reg); 63354450f59SHans Verkuil } 63454450f59SHans Verkuil 63554450f59SHans Verkuil static inline int vdp_write(struct v4l2_subdev *sd, u8 reg, u8 val) 63654450f59SHans Verkuil { 637b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 63854450f59SHans Verkuil 63905cacb17SLaurent Pinchart return adv_smbus_write_byte_data(state, ADV7604_PAGE_VDP, reg, val); 64054450f59SHans Verkuil } 64154450f59SHans Verkuil 642b44b2e06SPablo Anton #define ADV76XX_REG(page, offset) (((page) << 8) | (offset)) 643b44b2e06SPablo Anton #define ADV76XX_REG_SEQ_TERM 0xffff 644d42010a1SLars-Peter Clausen 645d42010a1SLars-Peter Clausen #ifdef CONFIG_VIDEO_ADV_DEBUG 646b44b2e06SPablo Anton static int adv76xx_read_reg(struct v4l2_subdev *sd, unsigned int reg) 647d42010a1SLars-Peter Clausen { 648b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 649d42010a1SLars-Peter Clausen unsigned int page = reg >> 8; 650d42010a1SLars-Peter Clausen 651d42010a1SLars-Peter Clausen if (!(BIT(page) & state->info->page_mask)) 652d42010a1SLars-Peter Clausen return -EINVAL; 653d42010a1SLars-Peter Clausen 654d42010a1SLars-Peter Clausen reg &= 0xff; 655d42010a1SLars-Peter Clausen 65605cacb17SLaurent Pinchart return adv_smbus_read_byte_data(state, page, reg); 657d42010a1SLars-Peter Clausen } 658d42010a1SLars-Peter Clausen #endif 659d42010a1SLars-Peter Clausen 660b44b2e06SPablo Anton static int adv76xx_write_reg(struct v4l2_subdev *sd, unsigned int reg, u8 val) 661d42010a1SLars-Peter Clausen { 662b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 663d42010a1SLars-Peter Clausen unsigned int page = reg >> 8; 664d42010a1SLars-Peter Clausen 665d42010a1SLars-Peter Clausen if (!(BIT(page) & state->info->page_mask)) 666d42010a1SLars-Peter Clausen return -EINVAL; 667d42010a1SLars-Peter Clausen 668d42010a1SLars-Peter Clausen reg &= 0xff; 669d42010a1SLars-Peter Clausen 67005cacb17SLaurent Pinchart return adv_smbus_write_byte_data(state, page, reg, val); 671d42010a1SLars-Peter Clausen } 672d42010a1SLars-Peter Clausen 673b44b2e06SPablo Anton static void adv76xx_write_reg_seq(struct v4l2_subdev *sd, 674b44b2e06SPablo Anton const struct adv76xx_reg_seq *reg_seq) 675d42010a1SLars-Peter Clausen { 676d42010a1SLars-Peter Clausen unsigned int i; 677d42010a1SLars-Peter Clausen 678b44b2e06SPablo Anton for (i = 0; reg_seq[i].reg != ADV76XX_REG_SEQ_TERM; i++) 679b44b2e06SPablo Anton adv76xx_write_reg(sd, reg_seq[i].reg, reg_seq[i].val); 680d42010a1SLars-Peter Clausen } 681d42010a1SLars-Peter Clausen 682539b33b0SLaurent Pinchart /* ----------------------------------------------------------------------------- 683539b33b0SLaurent Pinchart * Format helpers 684539b33b0SLaurent Pinchart */ 685539b33b0SLaurent Pinchart 686b44b2e06SPablo Anton static const struct adv76xx_format_info adv7604_formats[] = { 687b44b2e06SPablo Anton { MEDIA_BUS_FMT_RGB888_1X24, ADV76XX_OP_CH_SEL_RGB, true, false, 688b44b2e06SPablo Anton ADV76XX_OP_MODE_SEL_SDR_444 | ADV76XX_OP_FORMAT_SEL_8BIT }, 689b44b2e06SPablo Anton { MEDIA_BUS_FMT_YUYV8_2X8, ADV76XX_OP_CH_SEL_RGB, false, false, 690b44b2e06SPablo Anton ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT }, 691b44b2e06SPablo Anton { MEDIA_BUS_FMT_YVYU8_2X8, ADV76XX_OP_CH_SEL_RGB, false, true, 692b44b2e06SPablo Anton ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT }, 693b44b2e06SPablo Anton { MEDIA_BUS_FMT_YUYV10_2X10, ADV76XX_OP_CH_SEL_RGB, false, false, 694b44b2e06SPablo Anton ADV76XX_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_10BIT }, 695b44b2e06SPablo Anton { MEDIA_BUS_FMT_YVYU10_2X10, ADV76XX_OP_CH_SEL_RGB, false, true, 696b44b2e06SPablo Anton ADV76XX_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_10BIT }, 697b44b2e06SPablo Anton { MEDIA_BUS_FMT_YUYV12_2X12, ADV76XX_OP_CH_SEL_RGB, false, false, 698b44b2e06SPablo Anton ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_12BIT }, 699b44b2e06SPablo Anton { MEDIA_BUS_FMT_YVYU12_2X12, ADV76XX_OP_CH_SEL_RGB, false, true, 700b44b2e06SPablo Anton ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_12BIT }, 701b44b2e06SPablo Anton { MEDIA_BUS_FMT_UYVY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, false, 702b44b2e06SPablo Anton ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT }, 703b44b2e06SPablo Anton { MEDIA_BUS_FMT_VYUY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, true, 704b44b2e06SPablo Anton ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT }, 705b44b2e06SPablo Anton { MEDIA_BUS_FMT_YUYV8_1X16, ADV76XX_OP_CH_SEL_RGB, false, false, 706b44b2e06SPablo Anton ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT }, 707b44b2e06SPablo Anton { MEDIA_BUS_FMT_YVYU8_1X16, ADV76XX_OP_CH_SEL_RGB, false, true, 708b44b2e06SPablo Anton ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT }, 709b44b2e06SPablo Anton { MEDIA_BUS_FMT_UYVY10_1X20, ADV76XX_OP_CH_SEL_RBG, false, false, 710b44b2e06SPablo Anton ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT }, 711b44b2e06SPablo Anton { MEDIA_BUS_FMT_VYUY10_1X20, ADV76XX_OP_CH_SEL_RBG, false, true, 712b44b2e06SPablo Anton ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT }, 713b44b2e06SPablo Anton { MEDIA_BUS_FMT_YUYV10_1X20, ADV76XX_OP_CH_SEL_RGB, false, false, 714b44b2e06SPablo Anton ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT }, 715b44b2e06SPablo Anton { MEDIA_BUS_FMT_YVYU10_1X20, ADV76XX_OP_CH_SEL_RGB, false, true, 716b44b2e06SPablo Anton ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT }, 717b44b2e06SPablo Anton { MEDIA_BUS_FMT_UYVY12_1X24, ADV76XX_OP_CH_SEL_RBG, false, false, 718b44b2e06SPablo Anton ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT }, 719b44b2e06SPablo Anton { MEDIA_BUS_FMT_VYUY12_1X24, ADV76XX_OP_CH_SEL_RBG, false, true, 720b44b2e06SPablo Anton ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT }, 721b44b2e06SPablo Anton { MEDIA_BUS_FMT_YUYV12_1X24, ADV76XX_OP_CH_SEL_RGB, false, false, 722b44b2e06SPablo Anton ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT }, 723b44b2e06SPablo Anton { MEDIA_BUS_FMT_YVYU12_1X24, ADV76XX_OP_CH_SEL_RGB, false, true, 724b44b2e06SPablo Anton ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT }, 725539b33b0SLaurent Pinchart }; 726539b33b0SLaurent Pinchart 727b44b2e06SPablo Anton static const struct adv76xx_format_info adv7611_formats[] = { 728b44b2e06SPablo Anton { MEDIA_BUS_FMT_RGB888_1X24, ADV76XX_OP_CH_SEL_RGB, true, false, 729b44b2e06SPablo Anton ADV76XX_OP_MODE_SEL_SDR_444 | ADV76XX_OP_FORMAT_SEL_8BIT }, 730b44b2e06SPablo Anton { MEDIA_BUS_FMT_YUYV8_2X8, ADV76XX_OP_CH_SEL_RGB, false, false, 731b44b2e06SPablo Anton ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT }, 732b44b2e06SPablo Anton { MEDIA_BUS_FMT_YVYU8_2X8, ADV76XX_OP_CH_SEL_RGB, false, true, 733b44b2e06SPablo Anton ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT }, 734b44b2e06SPablo Anton { MEDIA_BUS_FMT_YUYV12_2X12, ADV76XX_OP_CH_SEL_RGB, false, false, 735b44b2e06SPablo Anton ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_12BIT }, 736b44b2e06SPablo Anton { MEDIA_BUS_FMT_YVYU12_2X12, ADV76XX_OP_CH_SEL_RGB, false, true, 737b44b2e06SPablo Anton ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_12BIT }, 738b44b2e06SPablo Anton { MEDIA_BUS_FMT_UYVY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, false, 739b44b2e06SPablo Anton ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT }, 740b44b2e06SPablo Anton { MEDIA_BUS_FMT_VYUY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, true, 741b44b2e06SPablo Anton ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT }, 742b44b2e06SPablo Anton { MEDIA_BUS_FMT_YUYV8_1X16, ADV76XX_OP_CH_SEL_RGB, false, false, 743b44b2e06SPablo Anton ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT }, 744b44b2e06SPablo Anton { MEDIA_BUS_FMT_YVYU8_1X16, ADV76XX_OP_CH_SEL_RGB, false, true, 745b44b2e06SPablo Anton ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT }, 746b44b2e06SPablo Anton { MEDIA_BUS_FMT_UYVY12_1X24, ADV76XX_OP_CH_SEL_RBG, false, false, 747b44b2e06SPablo Anton ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT }, 748b44b2e06SPablo Anton { MEDIA_BUS_FMT_VYUY12_1X24, ADV76XX_OP_CH_SEL_RBG, false, true, 749b44b2e06SPablo Anton ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT }, 750b44b2e06SPablo Anton { MEDIA_BUS_FMT_YUYV12_1X24, ADV76XX_OP_CH_SEL_RGB, false, false, 751b44b2e06SPablo Anton ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT }, 752b44b2e06SPablo Anton { MEDIA_BUS_FMT_YVYU12_1X24, ADV76XX_OP_CH_SEL_RGB, false, true, 753b44b2e06SPablo Anton ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT }, 754539b33b0SLaurent Pinchart }; 755539b33b0SLaurent Pinchart 756b44b2e06SPablo Anton static const struct adv76xx_format_info * 757b44b2e06SPablo Anton adv76xx_format_info(struct adv76xx_state *state, u32 code) 758539b33b0SLaurent Pinchart { 759539b33b0SLaurent Pinchart unsigned int i; 760539b33b0SLaurent Pinchart 761539b33b0SLaurent Pinchart for (i = 0; i < state->info->nformats; ++i) { 762539b33b0SLaurent Pinchart if (state->info->formats[i].code == code) 763539b33b0SLaurent Pinchart return &state->info->formats[i]; 764539b33b0SLaurent Pinchart } 765539b33b0SLaurent Pinchart 766539b33b0SLaurent Pinchart return NULL; 767539b33b0SLaurent Pinchart } 768539b33b0SLaurent Pinchart 76954450f59SHans Verkuil /* ----------------------------------------------------------------------- */ 77054450f59SHans Verkuil 7714a31a93aSMats Randgaard static inline bool is_analog_input(struct v4l2_subdev *sd) 7724a31a93aSMats Randgaard { 773b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 7744a31a93aSMats Randgaard 775c784b1e2SLaurent Pinchart return state->selected_input == ADV7604_PAD_VGA_RGB || 776c784b1e2SLaurent Pinchart state->selected_input == ADV7604_PAD_VGA_COMP; 7774a31a93aSMats Randgaard } 7784a31a93aSMats Randgaard 7794a31a93aSMats Randgaard static inline bool is_digital_input(struct v4l2_subdev *sd) 7804a31a93aSMats Randgaard { 781b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 7824a31a93aSMats Randgaard 783b44b2e06SPablo Anton return state->selected_input == ADV76XX_PAD_HDMI_PORT_A || 784c784b1e2SLaurent Pinchart state->selected_input == ADV7604_PAD_HDMI_PORT_B || 785c784b1e2SLaurent Pinchart state->selected_input == ADV7604_PAD_HDMI_PORT_C || 786c784b1e2SLaurent Pinchart state->selected_input == ADV7604_PAD_HDMI_PORT_D; 7874a31a93aSMats Randgaard } 7884a31a93aSMats Randgaard 7894a31a93aSMats Randgaard /* ----------------------------------------------------------------------- */ 7904a31a93aSMats Randgaard 79154450f59SHans Verkuil #ifdef CONFIG_VIDEO_ADV_DEBUG 792b44b2e06SPablo Anton static void adv76xx_inv_register(struct v4l2_subdev *sd) 79354450f59SHans Verkuil { 79454450f59SHans Verkuil v4l2_info(sd, "0x000-0x0ff: IO Map\n"); 79554450f59SHans Verkuil v4l2_info(sd, "0x100-0x1ff: AVLink Map\n"); 79654450f59SHans Verkuil v4l2_info(sd, "0x200-0x2ff: CEC Map\n"); 79754450f59SHans Verkuil v4l2_info(sd, "0x300-0x3ff: InfoFrame Map\n"); 79854450f59SHans Verkuil v4l2_info(sd, "0x400-0x4ff: ESDP Map\n"); 79954450f59SHans Verkuil v4l2_info(sd, "0x500-0x5ff: DPP Map\n"); 80054450f59SHans Verkuil v4l2_info(sd, "0x600-0x6ff: AFE Map\n"); 80154450f59SHans Verkuil v4l2_info(sd, "0x700-0x7ff: Repeater Map\n"); 80254450f59SHans Verkuil v4l2_info(sd, "0x800-0x8ff: EDID Map\n"); 80354450f59SHans Verkuil v4l2_info(sd, "0x900-0x9ff: HDMI Map\n"); 80454450f59SHans Verkuil v4l2_info(sd, "0xa00-0xaff: Test Map\n"); 80554450f59SHans Verkuil v4l2_info(sd, "0xb00-0xbff: CP Map\n"); 80654450f59SHans Verkuil v4l2_info(sd, "0xc00-0xcff: VDP Map\n"); 80754450f59SHans Verkuil } 80854450f59SHans Verkuil 809b44b2e06SPablo Anton static int adv76xx_g_register(struct v4l2_subdev *sd, 81054450f59SHans Verkuil struct v4l2_dbg_register *reg) 81154450f59SHans Verkuil { 812d42010a1SLars-Peter Clausen int ret; 813d42010a1SLars-Peter Clausen 814b44b2e06SPablo Anton ret = adv76xx_read_reg(sd, reg->reg); 815d42010a1SLars-Peter Clausen if (ret < 0) { 81654450f59SHans Verkuil v4l2_info(sd, "Register %03llx not supported\n", reg->reg); 817b44b2e06SPablo Anton adv76xx_inv_register(sd); 818d42010a1SLars-Peter Clausen return ret; 81954450f59SHans Verkuil } 820d42010a1SLars-Peter Clausen 821d42010a1SLars-Peter Clausen reg->size = 1; 822d42010a1SLars-Peter Clausen reg->val = ret; 823d42010a1SLars-Peter Clausen 82454450f59SHans Verkuil return 0; 82554450f59SHans Verkuil } 82654450f59SHans Verkuil 827b44b2e06SPablo Anton static int adv76xx_s_register(struct v4l2_subdev *sd, 828977ba3b1SHans Verkuil const struct v4l2_dbg_register *reg) 82954450f59SHans Verkuil { 830d42010a1SLars-Peter Clausen int ret; 8311577461bSHans Verkuil 832b44b2e06SPablo Anton ret = adv76xx_write_reg(sd, reg->reg, reg->val); 833d42010a1SLars-Peter Clausen if (ret < 0) { 83454450f59SHans Verkuil v4l2_info(sd, "Register %03llx not supported\n", reg->reg); 835b44b2e06SPablo Anton adv76xx_inv_register(sd); 836d42010a1SLars-Peter Clausen return ret; 83754450f59SHans Verkuil } 838d42010a1SLars-Peter Clausen 83954450f59SHans Verkuil return 0; 84054450f59SHans Verkuil } 84154450f59SHans Verkuil #endif 84254450f59SHans Verkuil 843d42010a1SLars-Peter Clausen static unsigned int adv7604_read_cable_det(struct v4l2_subdev *sd) 844d42010a1SLars-Peter Clausen { 845d42010a1SLars-Peter Clausen u8 value = io_read(sd, 0x6f); 846d42010a1SLars-Peter Clausen 847d42010a1SLars-Peter Clausen return ((value & 0x10) >> 4) 848d42010a1SLars-Peter Clausen | ((value & 0x08) >> 2) 849d42010a1SLars-Peter Clausen | ((value & 0x04) << 0) 850d42010a1SLars-Peter Clausen | ((value & 0x02) << 2); 851d42010a1SLars-Peter Clausen } 852d42010a1SLars-Peter Clausen 853d42010a1SLars-Peter Clausen static unsigned int adv7611_read_cable_det(struct v4l2_subdev *sd) 854d42010a1SLars-Peter Clausen { 855d42010a1SLars-Peter Clausen u8 value = io_read(sd, 0x6f); 856d42010a1SLars-Peter Clausen 857d42010a1SLars-Peter Clausen return value & 1; 858d42010a1SLars-Peter Clausen } 859d42010a1SLars-Peter Clausen 860b44b2e06SPablo Anton static int adv76xx_s_detect_tx_5v_ctrl(struct v4l2_subdev *sd) 86154450f59SHans Verkuil { 862b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 863b44b2e06SPablo Anton const struct adv76xx_chip_info *info = state->info; 86454450f59SHans Verkuil 86554450f59SHans Verkuil return v4l2_ctrl_s_ctrl(state->detect_tx_5v_ctrl, 866d42010a1SLars-Peter Clausen info->read_cable_det(sd)); 86754450f59SHans Verkuil } 86854450f59SHans Verkuil 869ccbd5bc4SHans Verkuil static int find_and_set_predefined_video_timings(struct v4l2_subdev *sd, 870ccbd5bc4SHans Verkuil u8 prim_mode, 871b44b2e06SPablo Anton const struct adv76xx_video_standards *predef_vid_timings, 872ccbd5bc4SHans Verkuil const struct v4l2_dv_timings *timings) 87354450f59SHans Verkuil { 874ccbd5bc4SHans Verkuil int i; 87554450f59SHans Verkuil 876ccbd5bc4SHans Verkuil for (i = 0; predef_vid_timings[i].timings.bt.width; i++) { 877ef1ed8f5SHans Verkuil if (!v4l2_match_dv_timings(timings, &predef_vid_timings[i].timings, 8784a31a93aSMats Randgaard is_digital_input(sd) ? 250000 : 1000000)) 879ccbd5bc4SHans Verkuil continue; 880ccbd5bc4SHans Verkuil io_write(sd, 0x00, predef_vid_timings[i].vid_std); /* video std */ 881ccbd5bc4SHans Verkuil io_write(sd, 0x01, (predef_vid_timings[i].v_freq << 4) + 882ccbd5bc4SHans Verkuil prim_mode); /* v_freq and prim mode */ 883ccbd5bc4SHans Verkuil return 0; 88454450f59SHans Verkuil } 88554450f59SHans Verkuil 886ccbd5bc4SHans Verkuil return -1; 887ccbd5bc4SHans Verkuil } 88854450f59SHans Verkuil 889ccbd5bc4SHans Verkuil static int configure_predefined_video_timings(struct v4l2_subdev *sd, 890ccbd5bc4SHans Verkuil struct v4l2_dv_timings *timings) 891ccbd5bc4SHans Verkuil { 892b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 893ccbd5bc4SHans Verkuil int err; 894ccbd5bc4SHans Verkuil 895ccbd5bc4SHans Verkuil v4l2_dbg(1, debug, sd, "%s", __func__); 896ccbd5bc4SHans Verkuil 897b44b2e06SPablo Anton if (adv76xx_has_afe(state)) { 89854450f59SHans Verkuil /* reset to default values */ 89954450f59SHans Verkuil io_write(sd, 0x16, 0x43); 90054450f59SHans Verkuil io_write(sd, 0x17, 0x5a); 901d42010a1SLars-Peter Clausen } 902ccbd5bc4SHans Verkuil /* disable embedded syncs for auto graphics mode */ 90322d97e56SLaurent Pinchart cp_write_clr_set(sd, 0x81, 0x10, 0x00); 904ccbd5bc4SHans Verkuil cp_write(sd, 0x8f, 0x00); 905ccbd5bc4SHans Verkuil cp_write(sd, 0x90, 0x00); 90654450f59SHans Verkuil cp_write(sd, 0xa2, 0x00); 90754450f59SHans Verkuil cp_write(sd, 0xa3, 0x00); 90854450f59SHans Verkuil cp_write(sd, 0xa4, 0x00); 90954450f59SHans Verkuil cp_write(sd, 0xa5, 0x00); 91054450f59SHans Verkuil cp_write(sd, 0xa6, 0x00); 91154450f59SHans Verkuil cp_write(sd, 0xa7, 0x00); 912ccbd5bc4SHans Verkuil cp_write(sd, 0xab, 0x00); 913ccbd5bc4SHans Verkuil cp_write(sd, 0xac, 0x00); 914ccbd5bc4SHans Verkuil 9154a31a93aSMats Randgaard if (is_analog_input(sd)) { 916ccbd5bc4SHans Verkuil err = find_and_set_predefined_video_timings(sd, 917ccbd5bc4SHans Verkuil 0x01, adv7604_prim_mode_comp, timings); 918ccbd5bc4SHans Verkuil if (err) 919ccbd5bc4SHans Verkuil err = find_and_set_predefined_video_timings(sd, 920ccbd5bc4SHans Verkuil 0x02, adv7604_prim_mode_gr, timings); 9214a31a93aSMats Randgaard } else if (is_digital_input(sd)) { 922ccbd5bc4SHans Verkuil err = find_and_set_predefined_video_timings(sd, 923b44b2e06SPablo Anton 0x05, adv76xx_prim_mode_hdmi_comp, timings); 924ccbd5bc4SHans Verkuil if (err) 925ccbd5bc4SHans Verkuil err = find_and_set_predefined_video_timings(sd, 926b44b2e06SPablo Anton 0x06, adv76xx_prim_mode_hdmi_gr, timings); 9274a31a93aSMats Randgaard } else { 9284a31a93aSMats Randgaard v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n", 9294a31a93aSMats Randgaard __func__, state->selected_input); 930ccbd5bc4SHans Verkuil err = -1; 93154450f59SHans Verkuil } 93254450f59SHans Verkuil 93354450f59SHans Verkuil 934ccbd5bc4SHans Verkuil return err; 935ccbd5bc4SHans Verkuil } 936ccbd5bc4SHans Verkuil 937ccbd5bc4SHans Verkuil static void configure_custom_video_timings(struct v4l2_subdev *sd, 938ccbd5bc4SHans Verkuil const struct v4l2_bt_timings *bt) 939ccbd5bc4SHans Verkuil { 940b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 941ccbd5bc4SHans Verkuil u32 width = htotal(bt); 942ccbd5bc4SHans Verkuil u32 height = vtotal(bt); 943ccbd5bc4SHans Verkuil u16 cp_start_sav = bt->hsync + bt->hbackporch - 4; 944ccbd5bc4SHans Verkuil u16 cp_start_eav = width - bt->hfrontporch; 945ccbd5bc4SHans Verkuil u16 cp_start_vbi = height - bt->vfrontporch; 946ccbd5bc4SHans Verkuil u16 cp_end_vbi = bt->vsync + bt->vbackporch; 947ccbd5bc4SHans Verkuil u16 ch1_fr_ll = (((u32)bt->pixelclock / 100) > 0) ? 948b44b2e06SPablo Anton ((width * (ADV76XX_FSC / 100)) / ((u32)bt->pixelclock / 100)) : 0; 949ccbd5bc4SHans Verkuil const u8 pll[2] = { 950ccbd5bc4SHans Verkuil 0xc0 | ((width >> 8) & 0x1f), 951ccbd5bc4SHans Verkuil width & 0xff 952ccbd5bc4SHans Verkuil }; 953ccbd5bc4SHans Verkuil 954ccbd5bc4SHans Verkuil v4l2_dbg(2, debug, sd, "%s\n", __func__); 955ccbd5bc4SHans Verkuil 9564a31a93aSMats Randgaard if (is_analog_input(sd)) { 957ccbd5bc4SHans Verkuil /* auto graphics */ 958ccbd5bc4SHans Verkuil io_write(sd, 0x00, 0x07); /* video std */ 959ccbd5bc4SHans Verkuil io_write(sd, 0x01, 0x02); /* prim mode */ 960ccbd5bc4SHans Verkuil /* enable embedded syncs for auto graphics mode */ 96122d97e56SLaurent Pinchart cp_write_clr_set(sd, 0x81, 0x10, 0x10); 962ccbd5bc4SHans Verkuil 963ccbd5bc4SHans Verkuil /* Should only be set in auto-graphics mode [REF_02, p. 91-92] */ 964ccbd5bc4SHans Verkuil /* setup PLL_DIV_MAN_EN and PLL_DIV_RATIO */ 965ccbd5bc4SHans Verkuil /* IO-map reg. 0x16 and 0x17 should be written in sequence */ 966b44b2e06SPablo Anton if (adv_smbus_write_i2c_block_data(state, ADV76XX_PAGE_IO, 96705cacb17SLaurent Pinchart 0x16, 2, pll)) 968ccbd5bc4SHans Verkuil v4l2_err(sd, "writing to reg 0x16 and 0x17 failed\n"); 969ccbd5bc4SHans Verkuil 970ccbd5bc4SHans Verkuil /* active video - horizontal timing */ 971ccbd5bc4SHans Verkuil cp_write(sd, 0xa2, (cp_start_sav >> 4) & 0xff); 972ccbd5bc4SHans Verkuil cp_write(sd, 0xa3, ((cp_start_sav & 0x0f) << 4) | 973ccbd5bc4SHans Verkuil ((cp_start_eav >> 8) & 0x0f)); 974ccbd5bc4SHans Verkuil cp_write(sd, 0xa4, cp_start_eav & 0xff); 975ccbd5bc4SHans Verkuil 976ccbd5bc4SHans Verkuil /* active video - vertical timing */ 977ccbd5bc4SHans Verkuil cp_write(sd, 0xa5, (cp_start_vbi >> 4) & 0xff); 978ccbd5bc4SHans Verkuil cp_write(sd, 0xa6, ((cp_start_vbi & 0xf) << 4) | 979ccbd5bc4SHans Verkuil ((cp_end_vbi >> 8) & 0xf)); 980ccbd5bc4SHans Verkuil cp_write(sd, 0xa7, cp_end_vbi & 0xff); 9814a31a93aSMats Randgaard } else if (is_digital_input(sd)) { 982ccbd5bc4SHans Verkuil /* set default prim_mode/vid_std for HDMI 98339c1cb2bSJonathan McCrohan according to [REF_03, c. 4.2] */ 984ccbd5bc4SHans Verkuil io_write(sd, 0x00, 0x02); /* video std */ 985ccbd5bc4SHans Verkuil io_write(sd, 0x01, 0x06); /* prim mode */ 9864a31a93aSMats Randgaard } else { 9874a31a93aSMats Randgaard v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n", 9884a31a93aSMats Randgaard __func__, state->selected_input); 989ccbd5bc4SHans Verkuil } 990ccbd5bc4SHans Verkuil 991ccbd5bc4SHans Verkuil cp_write(sd, 0x8f, (ch1_fr_ll >> 8) & 0x7); 992ccbd5bc4SHans Verkuil cp_write(sd, 0x90, ch1_fr_ll & 0xff); 993ccbd5bc4SHans Verkuil cp_write(sd, 0xab, (height >> 4) & 0xff); 994ccbd5bc4SHans Verkuil cp_write(sd, 0xac, (height & 0x0f) << 4); 995ccbd5bc4SHans Verkuil } 996ccbd5bc4SHans Verkuil 997b44b2e06SPablo Anton static void adv76xx_set_offset(struct v4l2_subdev *sd, bool auto_offset, u16 offset_a, u16 offset_b, u16 offset_c) 9985c6c6349SMats Randgaard { 999b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 10005c6c6349SMats Randgaard u8 offset_buf[4]; 10015c6c6349SMats Randgaard 10025c6c6349SMats Randgaard if (auto_offset) { 10035c6c6349SMats Randgaard offset_a = 0x3ff; 10045c6c6349SMats Randgaard offset_b = 0x3ff; 10055c6c6349SMats Randgaard offset_c = 0x3ff; 10065c6c6349SMats Randgaard } 10075c6c6349SMats Randgaard 10085c6c6349SMats Randgaard v4l2_dbg(2, debug, sd, "%s: %s offset: a = 0x%x, b = 0x%x, c = 0x%x\n", 10095c6c6349SMats Randgaard __func__, auto_offset ? "Auto" : "Manual", 10105c6c6349SMats Randgaard offset_a, offset_b, offset_c); 10115c6c6349SMats Randgaard 10125c6c6349SMats Randgaard offset_buf[0] = (cp_read(sd, 0x77) & 0xc0) | ((offset_a & 0x3f0) >> 4); 10135c6c6349SMats Randgaard offset_buf[1] = ((offset_a & 0x00f) << 4) | ((offset_b & 0x3c0) >> 6); 10145c6c6349SMats Randgaard offset_buf[2] = ((offset_b & 0x03f) << 2) | ((offset_c & 0x300) >> 8); 10155c6c6349SMats Randgaard offset_buf[3] = offset_c & 0x0ff; 10165c6c6349SMats Randgaard 10175c6c6349SMats Randgaard /* Registers must be written in this order with no i2c access in between */ 1018b44b2e06SPablo Anton if (adv_smbus_write_i2c_block_data(state, ADV76XX_PAGE_CP, 101905cacb17SLaurent Pinchart 0x77, 4, offset_buf)) 10205c6c6349SMats Randgaard v4l2_err(sd, "%s: i2c error writing to CP reg 0x77, 0x78, 0x79, 0x7a\n", __func__); 10215c6c6349SMats Randgaard } 10225c6c6349SMats Randgaard 1023b44b2e06SPablo Anton static void adv76xx_set_gain(struct v4l2_subdev *sd, bool auto_gain, u16 gain_a, u16 gain_b, u16 gain_c) 10245c6c6349SMats Randgaard { 1025b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 10265c6c6349SMats Randgaard u8 gain_buf[4]; 10275c6c6349SMats Randgaard u8 gain_man = 1; 10285c6c6349SMats Randgaard u8 agc_mode_man = 1; 10295c6c6349SMats Randgaard 10305c6c6349SMats Randgaard if (auto_gain) { 10315c6c6349SMats Randgaard gain_man = 0; 10325c6c6349SMats Randgaard agc_mode_man = 0; 10335c6c6349SMats Randgaard gain_a = 0x100; 10345c6c6349SMats Randgaard gain_b = 0x100; 10355c6c6349SMats Randgaard gain_c = 0x100; 10365c6c6349SMats Randgaard } 10375c6c6349SMats Randgaard 10385c6c6349SMats Randgaard v4l2_dbg(2, debug, sd, "%s: %s gain: a = 0x%x, b = 0x%x, c = 0x%x\n", 10395c6c6349SMats Randgaard __func__, auto_gain ? "Auto" : "Manual", 10405c6c6349SMats Randgaard gain_a, gain_b, gain_c); 10415c6c6349SMats Randgaard 10425c6c6349SMats Randgaard gain_buf[0] = ((gain_man << 7) | (agc_mode_man << 6) | ((gain_a & 0x3f0) >> 4)); 10435c6c6349SMats Randgaard gain_buf[1] = (((gain_a & 0x00f) << 4) | ((gain_b & 0x3c0) >> 6)); 10445c6c6349SMats Randgaard gain_buf[2] = (((gain_b & 0x03f) << 2) | ((gain_c & 0x300) >> 8)); 10455c6c6349SMats Randgaard gain_buf[3] = ((gain_c & 0x0ff)); 10465c6c6349SMats Randgaard 10475c6c6349SMats Randgaard /* Registers must be written in this order with no i2c access in between */ 1048b44b2e06SPablo Anton if (adv_smbus_write_i2c_block_data(state, ADV76XX_PAGE_CP, 104905cacb17SLaurent Pinchart 0x73, 4, gain_buf)) 10505c6c6349SMats Randgaard v4l2_err(sd, "%s: i2c error writing to CP reg 0x73, 0x74, 0x75, 0x76\n", __func__); 10515c6c6349SMats Randgaard } 10525c6c6349SMats Randgaard 105354450f59SHans Verkuil static void set_rgb_quantization_range(struct v4l2_subdev *sd) 105454450f59SHans Verkuil { 1055b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 10565c6c6349SMats Randgaard bool rgb_output = io_read(sd, 0x02) & 0x02; 10575c6c6349SMats Randgaard bool hdmi_signal = hdmi_read(sd, 0x05) & 0x80; 105854450f59SHans Verkuil 10595c6c6349SMats Randgaard v4l2_dbg(2, debug, sd, "%s: RGB quantization range: %d, RGB out: %d, HDMI: %d\n", 10605c6c6349SMats Randgaard __func__, state->rgb_quantization_range, 10615c6c6349SMats Randgaard rgb_output, hdmi_signal); 10625c6c6349SMats Randgaard 1063b44b2e06SPablo Anton adv76xx_set_gain(sd, true, 0x0, 0x0, 0x0); 1064b44b2e06SPablo Anton adv76xx_set_offset(sd, true, 0x0, 0x0, 0x0); 10659833239eSMats Randgaard 106654450f59SHans Verkuil switch (state->rgb_quantization_range) { 106754450f59SHans Verkuil case V4L2_DV_RGB_RANGE_AUTO: 1068c784b1e2SLaurent Pinchart if (state->selected_input == ADV7604_PAD_VGA_RGB) { 10699833239eSMats Randgaard /* Receiving analog RGB signal 10709833239eSMats Randgaard * Set RGB full range (0-255) */ 107122d97e56SLaurent Pinchart io_write_clr_set(sd, 0x02, 0xf0, 0x10); 10729833239eSMats Randgaard break; 10739833239eSMats Randgaard } 107454450f59SHans Verkuil 1075c784b1e2SLaurent Pinchart if (state->selected_input == ADV7604_PAD_VGA_COMP) { 10769833239eSMats Randgaard /* Receiving analog YPbPr signal 10779833239eSMats Randgaard * Set automode */ 107822d97e56SLaurent Pinchart io_write_clr_set(sd, 0x02, 0xf0, 0xf0); 10799833239eSMats Randgaard break; 10809833239eSMats Randgaard } 10819833239eSMats Randgaard 10825c6c6349SMats Randgaard if (hdmi_signal) { 10839833239eSMats Randgaard /* Receiving HDMI signal 10849833239eSMats Randgaard * Set automode */ 108522d97e56SLaurent Pinchart io_write_clr_set(sd, 0x02, 0xf0, 0xf0); 10869833239eSMats Randgaard break; 10879833239eSMats Randgaard } 10889833239eSMats Randgaard 10899833239eSMats Randgaard /* Receiving DVI-D signal 10909833239eSMats Randgaard * ADV7604 selects RGB limited range regardless of 10919833239eSMats Randgaard * input format (CE/IT) in automatic mode */ 1092680fee04SHans Verkuil if (state->timings.bt.flags & V4L2_DV_FL_IS_CE_VIDEO) { 109354450f59SHans Verkuil /* RGB limited range (16-235) */ 109422d97e56SLaurent Pinchart io_write_clr_set(sd, 0x02, 0xf0, 0x00); 109554450f59SHans Verkuil } else { 109654450f59SHans Verkuil /* RGB full range (0-255) */ 109722d97e56SLaurent Pinchart io_write_clr_set(sd, 0x02, 0xf0, 0x10); 10985c6c6349SMats Randgaard 10995c6c6349SMats Randgaard if (is_digital_input(sd) && rgb_output) { 1100b44b2e06SPablo Anton adv76xx_set_offset(sd, false, 0x40, 0x40, 0x40); 11015c6c6349SMats Randgaard } else { 1102b44b2e06SPablo Anton adv76xx_set_gain(sd, false, 0xe0, 0xe0, 0xe0); 1103b44b2e06SPablo Anton adv76xx_set_offset(sd, false, 0x70, 0x70, 0x70); 11045c6c6349SMats Randgaard } 110554450f59SHans Verkuil } 110654450f59SHans Verkuil break; 110754450f59SHans Verkuil case V4L2_DV_RGB_RANGE_LIMITED: 1108c784b1e2SLaurent Pinchart if (state->selected_input == ADV7604_PAD_VGA_COMP) { 1109d261e842SMats Randgaard /* YCrCb limited range (16-235) */ 111022d97e56SLaurent Pinchart io_write_clr_set(sd, 0x02, 0xf0, 0x20); 11115c6c6349SMats Randgaard break; 11125c6c6349SMats Randgaard } 11135c6c6349SMats Randgaard 111454450f59SHans Verkuil /* RGB limited range (16-235) */ 111522d97e56SLaurent Pinchart io_write_clr_set(sd, 0x02, 0xf0, 0x00); 11165c6c6349SMats Randgaard 111754450f59SHans Verkuil break; 111854450f59SHans Verkuil case V4L2_DV_RGB_RANGE_FULL: 1119c784b1e2SLaurent Pinchart if (state->selected_input == ADV7604_PAD_VGA_COMP) { 1120d261e842SMats Randgaard /* YCrCb full range (0-255) */ 112122d97e56SLaurent Pinchart io_write_clr_set(sd, 0x02, 0xf0, 0x60); 11225c6c6349SMats Randgaard break; 11235c6c6349SMats Randgaard } 11245c6c6349SMats Randgaard 112554450f59SHans Verkuil /* RGB full range (0-255) */ 112622d97e56SLaurent Pinchart io_write_clr_set(sd, 0x02, 0xf0, 0x10); 11275c6c6349SMats Randgaard 11285c6c6349SMats Randgaard if (is_analog_input(sd) || hdmi_signal) 11295c6c6349SMats Randgaard break; 11305c6c6349SMats Randgaard 11315c6c6349SMats Randgaard /* Adjust gain/offset for DVI-D signals only */ 11325c6c6349SMats Randgaard if (rgb_output) { 1133b44b2e06SPablo Anton adv76xx_set_offset(sd, false, 0x40, 0x40, 0x40); 11345c6c6349SMats Randgaard } else { 1135b44b2e06SPablo Anton adv76xx_set_gain(sd, false, 0xe0, 0xe0, 0xe0); 1136b44b2e06SPablo Anton adv76xx_set_offset(sd, false, 0x70, 0x70, 0x70); 1137d261e842SMats Randgaard } 113854450f59SHans Verkuil break; 113954450f59SHans Verkuil } 114054450f59SHans Verkuil } 114154450f59SHans Verkuil 1142b44b2e06SPablo Anton static int adv76xx_s_ctrl(struct v4l2_ctrl *ctrl) 114354450f59SHans Verkuil { 1144c269887cSLaurent Pinchart struct v4l2_subdev *sd = 1145b44b2e06SPablo Anton &container_of(ctrl->handler, struct adv76xx_state, hdl)->sd; 1146c269887cSLaurent Pinchart 1147b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 114854450f59SHans Verkuil 114954450f59SHans Verkuil switch (ctrl->id) { 115054450f59SHans Verkuil case V4L2_CID_BRIGHTNESS: 115154450f59SHans Verkuil cp_write(sd, 0x3c, ctrl->val); 115254450f59SHans Verkuil return 0; 115354450f59SHans Verkuil case V4L2_CID_CONTRAST: 115454450f59SHans Verkuil cp_write(sd, 0x3a, ctrl->val); 115554450f59SHans Verkuil return 0; 115654450f59SHans Verkuil case V4L2_CID_SATURATION: 115754450f59SHans Verkuil cp_write(sd, 0x3b, ctrl->val); 115854450f59SHans Verkuil return 0; 115954450f59SHans Verkuil case V4L2_CID_HUE: 116054450f59SHans Verkuil cp_write(sd, 0x3d, ctrl->val); 116154450f59SHans Verkuil return 0; 116254450f59SHans Verkuil case V4L2_CID_DV_RX_RGB_RANGE: 116354450f59SHans Verkuil state->rgb_quantization_range = ctrl->val; 116454450f59SHans Verkuil set_rgb_quantization_range(sd); 116554450f59SHans Verkuil return 0; 116654450f59SHans Verkuil case V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE: 1167b44b2e06SPablo Anton if (!adv76xx_has_afe(state)) 1168d42010a1SLars-Peter Clausen return -EINVAL; 116954450f59SHans Verkuil /* Set the analog sampling phase. This is needed to find the 117054450f59SHans Verkuil best sampling phase for analog video: an application or 117154450f59SHans Verkuil driver has to try a number of phases and analyze the picture 117254450f59SHans Verkuil quality before settling on the best performing phase. */ 117354450f59SHans Verkuil afe_write(sd, 0xc8, ctrl->val); 117454450f59SHans Verkuil return 0; 117554450f59SHans Verkuil case V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL: 117654450f59SHans Verkuil /* Use the default blue color for free running mode, 117754450f59SHans Verkuil or supply your own. */ 117822d97e56SLaurent Pinchart cp_write_clr_set(sd, 0xbf, 0x04, ctrl->val << 2); 117954450f59SHans Verkuil return 0; 118054450f59SHans Verkuil case V4L2_CID_ADV_RX_FREE_RUN_COLOR: 118154450f59SHans Verkuil cp_write(sd, 0xc0, (ctrl->val & 0xff0000) >> 16); 118254450f59SHans Verkuil cp_write(sd, 0xc1, (ctrl->val & 0x00ff00) >> 8); 118354450f59SHans Verkuil cp_write(sd, 0xc2, (u8)(ctrl->val & 0x0000ff)); 118454450f59SHans Verkuil return 0; 118554450f59SHans Verkuil } 118654450f59SHans Verkuil return -EINVAL; 118754450f59SHans Verkuil } 118854450f59SHans Verkuil 118954450f59SHans Verkuil /* ----------------------------------------------------------------------- */ 119054450f59SHans Verkuil 119154450f59SHans Verkuil static inline bool no_power(struct v4l2_subdev *sd) 119254450f59SHans Verkuil { 119354450f59SHans Verkuil /* Entire chip or CP powered off */ 119454450f59SHans Verkuil return io_read(sd, 0x0c) & 0x24; 119554450f59SHans Verkuil } 119654450f59SHans Verkuil 119754450f59SHans Verkuil static inline bool no_signal_tmds(struct v4l2_subdev *sd) 119854450f59SHans Verkuil { 1199b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 12004a31a93aSMats Randgaard 12014a31a93aSMats Randgaard return !(io_read(sd, 0x6a) & (0x10 >> state->selected_input)); 120254450f59SHans Verkuil } 120354450f59SHans Verkuil 120454450f59SHans Verkuil static inline bool no_lock_tmds(struct v4l2_subdev *sd) 120554450f59SHans Verkuil { 1206b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 1207b44b2e06SPablo Anton const struct adv76xx_chip_info *info = state->info; 1208d42010a1SLars-Peter Clausen 1209d42010a1SLars-Peter Clausen return (io_read(sd, 0x6a) & info->tdms_lock_mask) != info->tdms_lock_mask; 121054450f59SHans Verkuil } 121154450f59SHans Verkuil 1212bb88f325SMartin Bugge static inline bool is_hdmi(struct v4l2_subdev *sd) 1213bb88f325SMartin Bugge { 1214bb88f325SMartin Bugge return hdmi_read(sd, 0x05) & 0x80; 1215bb88f325SMartin Bugge } 1216bb88f325SMartin Bugge 121754450f59SHans Verkuil static inline bool no_lock_sspd(struct v4l2_subdev *sd) 121854450f59SHans Verkuil { 1219b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 1220d42010a1SLars-Peter Clausen 1221d42010a1SLars-Peter Clausen /* 1222d42010a1SLars-Peter Clausen * Chips without a AFE don't expose registers for the SSPD, so just assume 1223d42010a1SLars-Peter Clausen * that we have a lock. 1224d42010a1SLars-Peter Clausen */ 1225b44b2e06SPablo Anton if (adv76xx_has_afe(state)) 1226d42010a1SLars-Peter Clausen return false; 1227d42010a1SLars-Peter Clausen 122854450f59SHans Verkuil /* TODO channel 2 */ 122954450f59SHans Verkuil return ((cp_read(sd, 0xb5) & 0xd0) != 0xd0); 123054450f59SHans Verkuil } 123154450f59SHans Verkuil 123254450f59SHans Verkuil static inline bool no_lock_stdi(struct v4l2_subdev *sd) 123354450f59SHans Verkuil { 123454450f59SHans Verkuil /* TODO channel 2 */ 123554450f59SHans Verkuil return !(cp_read(sd, 0xb1) & 0x80); 123654450f59SHans Verkuil } 123754450f59SHans Verkuil 123854450f59SHans Verkuil static inline bool no_signal(struct v4l2_subdev *sd) 123954450f59SHans Verkuil { 124054450f59SHans Verkuil bool ret; 124154450f59SHans Verkuil 124254450f59SHans Verkuil ret = no_power(sd); 124354450f59SHans Verkuil 124454450f59SHans Verkuil ret |= no_lock_stdi(sd); 124554450f59SHans Verkuil ret |= no_lock_sspd(sd); 124654450f59SHans Verkuil 12474a31a93aSMats Randgaard if (is_digital_input(sd)) { 124854450f59SHans Verkuil ret |= no_lock_tmds(sd); 124954450f59SHans Verkuil ret |= no_signal_tmds(sd); 125054450f59SHans Verkuil } 125154450f59SHans Verkuil 125254450f59SHans Verkuil return ret; 125354450f59SHans Verkuil } 125454450f59SHans Verkuil 125554450f59SHans Verkuil static inline bool no_lock_cp(struct v4l2_subdev *sd) 125654450f59SHans Verkuil { 1257b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 1258d42010a1SLars-Peter Clausen 1259b44b2e06SPablo Anton if (!adv76xx_has_afe(state)) 1260d42010a1SLars-Peter Clausen return false; 1261d42010a1SLars-Peter Clausen 126254450f59SHans Verkuil /* CP has detected a non standard number of lines on the incoming 126354450f59SHans Verkuil video compared to what it is configured to receive by s_dv_timings */ 126454450f59SHans Verkuil return io_read(sd, 0x12) & 0x01; 126554450f59SHans Verkuil } 126654450f59SHans Verkuil 126758514625Sjean-michel.hautbois@vodalys.com static inline bool in_free_run(struct v4l2_subdev *sd) 126858514625Sjean-michel.hautbois@vodalys.com { 126958514625Sjean-michel.hautbois@vodalys.com return cp_read(sd, 0xff) & 0x10; 127058514625Sjean-michel.hautbois@vodalys.com } 127158514625Sjean-michel.hautbois@vodalys.com 1272b44b2e06SPablo Anton static int adv76xx_g_input_status(struct v4l2_subdev *sd, u32 *status) 127354450f59SHans Verkuil { 127454450f59SHans Verkuil *status = 0; 127554450f59SHans Verkuil *status |= no_power(sd) ? V4L2_IN_ST_NO_POWER : 0; 127654450f59SHans Verkuil *status |= no_signal(sd) ? V4L2_IN_ST_NO_SIGNAL : 0; 127758514625Sjean-michel.hautbois@vodalys.com if (!in_free_run(sd) && no_lock_cp(sd)) 127858514625Sjean-michel.hautbois@vodalys.com *status |= is_digital_input(sd) ? 127958514625Sjean-michel.hautbois@vodalys.com V4L2_IN_ST_NO_SYNC : V4L2_IN_ST_NO_H_LOCK; 128054450f59SHans Verkuil 128154450f59SHans Verkuil v4l2_dbg(1, debug, sd, "%s: status = 0x%x\n", __func__, *status); 128254450f59SHans Verkuil 128354450f59SHans Verkuil return 0; 128454450f59SHans Verkuil } 128554450f59SHans Verkuil 128654450f59SHans Verkuil /* ----------------------------------------------------------------------- */ 128754450f59SHans Verkuil 128854450f59SHans Verkuil struct stdi_readback { 128954450f59SHans Verkuil u16 bl, lcf, lcvs; 129054450f59SHans Verkuil u8 hs_pol, vs_pol; 129154450f59SHans Verkuil bool interlaced; 129254450f59SHans Verkuil }; 129354450f59SHans Verkuil 129454450f59SHans Verkuil static int stdi2dv_timings(struct v4l2_subdev *sd, 129554450f59SHans Verkuil struct stdi_readback *stdi, 129654450f59SHans Verkuil struct v4l2_dv_timings *timings) 129754450f59SHans Verkuil { 1298b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 1299b44b2e06SPablo Anton u32 hfreq = (ADV76XX_FSC * 8) / stdi->bl; 130054450f59SHans Verkuil u32 pix_clk; 130154450f59SHans Verkuil int i; 130254450f59SHans Verkuil 1303b44b2e06SPablo Anton for (i = 0; adv76xx_timings[i].bt.height; i++) { 1304b44b2e06SPablo Anton if (vtotal(&adv76xx_timings[i].bt) != stdi->lcf + 1) 130554450f59SHans Verkuil continue; 1306b44b2e06SPablo Anton if (adv76xx_timings[i].bt.vsync != stdi->lcvs) 130754450f59SHans Verkuil continue; 130854450f59SHans Verkuil 1309b44b2e06SPablo Anton pix_clk = hfreq * htotal(&adv76xx_timings[i].bt); 131054450f59SHans Verkuil 1311b44b2e06SPablo Anton if ((pix_clk < adv76xx_timings[i].bt.pixelclock + 1000000) && 1312b44b2e06SPablo Anton (pix_clk > adv76xx_timings[i].bt.pixelclock - 1000000)) { 1313b44b2e06SPablo Anton *timings = adv76xx_timings[i]; 131454450f59SHans Verkuil return 0; 131554450f59SHans Verkuil } 131654450f59SHans Verkuil } 131754450f59SHans Verkuil 131854450f59SHans Verkuil if (v4l2_detect_cvt(stdi->lcf + 1, hfreq, stdi->lcvs, 131954450f59SHans Verkuil (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) | 132054450f59SHans Verkuil (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0), 132154450f59SHans Verkuil timings)) 132254450f59SHans Verkuil return 0; 132354450f59SHans Verkuil if (v4l2_detect_gtf(stdi->lcf + 1, hfreq, stdi->lcvs, 132454450f59SHans Verkuil (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) | 132554450f59SHans Verkuil (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0), 132654450f59SHans Verkuil state->aspect_ratio, timings)) 132754450f59SHans Verkuil return 0; 132854450f59SHans Verkuil 1329ccbd5bc4SHans Verkuil v4l2_dbg(2, debug, sd, 1330ccbd5bc4SHans Verkuil "%s: No format candidate found for lcvs = %d, lcf=%d, bl = %d, %chsync, %cvsync\n", 1331ccbd5bc4SHans Verkuil __func__, stdi->lcvs, stdi->lcf, stdi->bl, 1332ccbd5bc4SHans Verkuil stdi->hs_pol, stdi->vs_pol); 133354450f59SHans Verkuil return -1; 133454450f59SHans Verkuil } 133554450f59SHans Verkuil 1336d42010a1SLars-Peter Clausen 133754450f59SHans Verkuil static int read_stdi(struct v4l2_subdev *sd, struct stdi_readback *stdi) 133854450f59SHans Verkuil { 1339b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 1340b44b2e06SPablo Anton const struct adv76xx_chip_info *info = state->info; 13414a2ccdd2SLaurent Pinchart u8 polarity; 13424a2ccdd2SLaurent Pinchart 134354450f59SHans Verkuil if (no_lock_stdi(sd) || no_lock_sspd(sd)) { 134454450f59SHans Verkuil v4l2_dbg(2, debug, sd, "%s: STDI and/or SSPD not locked\n", __func__); 134554450f59SHans Verkuil return -1; 134654450f59SHans Verkuil } 134754450f59SHans Verkuil 134854450f59SHans Verkuil /* read STDI */ 134951182a94SLaurent Pinchart stdi->bl = cp_read16(sd, 0xb1, 0x3fff); 1350d42010a1SLars-Peter Clausen stdi->lcf = cp_read16(sd, info->lcf_reg, 0x7ff); 135154450f59SHans Verkuil stdi->lcvs = cp_read(sd, 0xb3) >> 3; 135254450f59SHans Verkuil stdi->interlaced = io_read(sd, 0x12) & 0x10; 135354450f59SHans Verkuil 1354b44b2e06SPablo Anton if (adv76xx_has_afe(state)) { 135554450f59SHans Verkuil /* read SSPD */ 13564a2ccdd2SLaurent Pinchart polarity = cp_read(sd, 0xb5); 13574a2ccdd2SLaurent Pinchart if ((polarity & 0x03) == 0x01) { 13584a2ccdd2SLaurent Pinchart stdi->hs_pol = polarity & 0x10 13594a2ccdd2SLaurent Pinchart ? (polarity & 0x08 ? '+' : '-') : 'x'; 13604a2ccdd2SLaurent Pinchart stdi->vs_pol = polarity & 0x40 13614a2ccdd2SLaurent Pinchart ? (polarity & 0x20 ? '+' : '-') : 'x'; 136254450f59SHans Verkuil } else { 136354450f59SHans Verkuil stdi->hs_pol = 'x'; 136454450f59SHans Verkuil stdi->vs_pol = 'x'; 136554450f59SHans Verkuil } 1366d42010a1SLars-Peter Clausen } else { 1367d42010a1SLars-Peter Clausen polarity = hdmi_read(sd, 0x05); 1368d42010a1SLars-Peter Clausen stdi->hs_pol = polarity & 0x20 ? '+' : '-'; 1369d42010a1SLars-Peter Clausen stdi->vs_pol = polarity & 0x10 ? '+' : '-'; 1370d42010a1SLars-Peter Clausen } 137154450f59SHans Verkuil 137254450f59SHans Verkuil if (no_lock_stdi(sd) || no_lock_sspd(sd)) { 137354450f59SHans Verkuil v4l2_dbg(2, debug, sd, 137454450f59SHans Verkuil "%s: signal lost during readout of STDI/SSPD\n", __func__); 137554450f59SHans Verkuil return -1; 137654450f59SHans Verkuil } 137754450f59SHans Verkuil 137854450f59SHans Verkuil if (stdi->lcf < 239 || stdi->bl < 8 || stdi->bl == 0x3fff) { 137954450f59SHans Verkuil v4l2_dbg(2, debug, sd, "%s: invalid signal\n", __func__); 138054450f59SHans Verkuil memset(stdi, 0, sizeof(struct stdi_readback)); 138154450f59SHans Verkuil return -1; 138254450f59SHans Verkuil } 138354450f59SHans Verkuil 138454450f59SHans Verkuil v4l2_dbg(2, debug, sd, 138554450f59SHans Verkuil "%s: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %chsync, %cvsync, %s\n", 138654450f59SHans Verkuil __func__, stdi->lcf, stdi->bl, stdi->lcvs, 138754450f59SHans Verkuil stdi->hs_pol, stdi->vs_pol, 138854450f59SHans Verkuil stdi->interlaced ? "interlaced" : "progressive"); 138954450f59SHans Verkuil 139054450f59SHans Verkuil return 0; 139154450f59SHans Verkuil } 139254450f59SHans Verkuil 1393b44b2e06SPablo Anton static int adv76xx_enum_dv_timings(struct v4l2_subdev *sd, 139454450f59SHans Verkuil struct v4l2_enum_dv_timings *timings) 139554450f59SHans Verkuil { 1396b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 1397afec5599SLaurent Pinchart 1398b44b2e06SPablo Anton if (timings->index >= ARRAY_SIZE(adv76xx_timings) - 1) 139954450f59SHans Verkuil return -EINVAL; 1400afec5599SLaurent Pinchart 1401afec5599SLaurent Pinchart if (timings->pad >= state->source_pad) 1402afec5599SLaurent Pinchart return -EINVAL; 1403afec5599SLaurent Pinchart 140454450f59SHans Verkuil memset(timings->reserved, 0, sizeof(timings->reserved)); 1405b44b2e06SPablo Anton timings->timings = adv76xx_timings[timings->index]; 140654450f59SHans Verkuil return 0; 140754450f59SHans Verkuil } 140854450f59SHans Verkuil 1409b44b2e06SPablo Anton static int adv76xx_dv_timings_cap(struct v4l2_subdev *sd, 14107515e096SLaurent Pinchart struct v4l2_dv_timings_cap *cap) 1411afec5599SLaurent Pinchart { 1412b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 14137515e096SLaurent Pinchart 14147515e096SLaurent Pinchart if (cap->pad >= state->source_pad) 14157515e096SLaurent Pinchart return -EINVAL; 14167515e096SLaurent Pinchart 1417afec5599SLaurent Pinchart cap->type = V4L2_DV_BT_656_1120; 1418afec5599SLaurent Pinchart cap->bt.max_width = 1920; 1419afec5599SLaurent Pinchart cap->bt.max_height = 1200; 1420afec5599SLaurent Pinchart cap->bt.min_pixelclock = 25000000; 1421afec5599SLaurent Pinchart 14227515e096SLaurent Pinchart switch (cap->pad) { 1423b44b2e06SPablo Anton case ADV76XX_PAD_HDMI_PORT_A: 1424afec5599SLaurent Pinchart case ADV7604_PAD_HDMI_PORT_B: 1425afec5599SLaurent Pinchart case ADV7604_PAD_HDMI_PORT_C: 1426afec5599SLaurent Pinchart case ADV7604_PAD_HDMI_PORT_D: 1427afec5599SLaurent Pinchart cap->bt.max_pixelclock = 225000000; 1428afec5599SLaurent Pinchart break; 1429afec5599SLaurent Pinchart case ADV7604_PAD_VGA_RGB: 1430afec5599SLaurent Pinchart case ADV7604_PAD_VGA_COMP: 1431afec5599SLaurent Pinchart default: 1432afec5599SLaurent Pinchart cap->bt.max_pixelclock = 170000000; 1433afec5599SLaurent Pinchart break; 1434afec5599SLaurent Pinchart } 1435afec5599SLaurent Pinchart 1436afec5599SLaurent Pinchart cap->bt.standards = V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT | 1437afec5599SLaurent Pinchart V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT; 1438afec5599SLaurent Pinchart cap->bt.capabilities = V4L2_DV_BT_CAP_PROGRESSIVE | 1439afec5599SLaurent Pinchart V4L2_DV_BT_CAP_REDUCED_BLANKING | V4L2_DV_BT_CAP_CUSTOM; 1440afec5599SLaurent Pinchart return 0; 1441afec5599SLaurent Pinchart } 1442afec5599SLaurent Pinchart 144354450f59SHans Verkuil /* Fill the optional fields .standards and .flags in struct v4l2_dv_timings 1444b44b2e06SPablo Anton if the format is listed in adv76xx_timings[] */ 1445b44b2e06SPablo Anton static void adv76xx_fill_optional_dv_timings_fields(struct v4l2_subdev *sd, 144654450f59SHans Verkuil struct v4l2_dv_timings *timings) 144754450f59SHans Verkuil { 144854450f59SHans Verkuil int i; 144954450f59SHans Verkuil 1450b44b2e06SPablo Anton for (i = 0; adv76xx_timings[i].bt.width; i++) { 1451b44b2e06SPablo Anton if (v4l2_match_dv_timings(timings, &adv76xx_timings[i], 14524a31a93aSMats Randgaard is_digital_input(sd) ? 250000 : 1000000)) { 1453b44b2e06SPablo Anton *timings = adv76xx_timings[i]; 145454450f59SHans Verkuil break; 145554450f59SHans Verkuil } 145654450f59SHans Verkuil } 145754450f59SHans Verkuil } 145854450f59SHans Verkuil 1459d42010a1SLars-Peter Clausen static unsigned int adv7604_read_hdmi_pixelclock(struct v4l2_subdev *sd) 1460d42010a1SLars-Peter Clausen { 1461d42010a1SLars-Peter Clausen unsigned int freq; 1462d42010a1SLars-Peter Clausen int a, b; 1463d42010a1SLars-Peter Clausen 1464d42010a1SLars-Peter Clausen a = hdmi_read(sd, 0x06); 1465d42010a1SLars-Peter Clausen b = hdmi_read(sd, 0x3b); 1466d42010a1SLars-Peter Clausen if (a < 0 || b < 0) 1467d42010a1SLars-Peter Clausen return 0; 1468d42010a1SLars-Peter Clausen freq = a * 1000000 + ((b & 0x30) >> 4) * 250000; 1469d42010a1SLars-Peter Clausen 1470d42010a1SLars-Peter Clausen if (is_hdmi(sd)) { 1471d42010a1SLars-Peter Clausen /* adjust for deep color mode */ 1472d42010a1SLars-Peter Clausen unsigned bits_per_channel = ((hdmi_read(sd, 0x0b) & 0x60) >> 4) + 8; 1473d42010a1SLars-Peter Clausen 1474d42010a1SLars-Peter Clausen freq = freq * 8 / bits_per_channel; 1475d42010a1SLars-Peter Clausen } 1476d42010a1SLars-Peter Clausen 1477d42010a1SLars-Peter Clausen return freq; 1478d42010a1SLars-Peter Clausen } 1479d42010a1SLars-Peter Clausen 1480d42010a1SLars-Peter Clausen static unsigned int adv7611_read_hdmi_pixelclock(struct v4l2_subdev *sd) 1481d42010a1SLars-Peter Clausen { 1482d42010a1SLars-Peter Clausen int a, b; 1483d42010a1SLars-Peter Clausen 1484d42010a1SLars-Peter Clausen a = hdmi_read(sd, 0x51); 1485d42010a1SLars-Peter Clausen b = hdmi_read(sd, 0x52); 1486d42010a1SLars-Peter Clausen if (a < 0 || b < 0) 1487d42010a1SLars-Peter Clausen return 0; 1488d42010a1SLars-Peter Clausen return ((a << 1) | (b >> 7)) * 1000000 + (b & 0x7f) * 1000000 / 128; 1489d42010a1SLars-Peter Clausen } 1490d42010a1SLars-Peter Clausen 1491b44b2e06SPablo Anton static int adv76xx_query_dv_timings(struct v4l2_subdev *sd, 149254450f59SHans Verkuil struct v4l2_dv_timings *timings) 149354450f59SHans Verkuil { 1494b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 1495b44b2e06SPablo Anton const struct adv76xx_chip_info *info = state->info; 149654450f59SHans Verkuil struct v4l2_bt_timings *bt = &timings->bt; 149754450f59SHans Verkuil struct stdi_readback stdi; 149854450f59SHans Verkuil 149954450f59SHans Verkuil if (!timings) 150054450f59SHans Verkuil return -EINVAL; 150154450f59SHans Verkuil 150254450f59SHans Verkuil memset(timings, 0, sizeof(struct v4l2_dv_timings)); 150354450f59SHans Verkuil 150454450f59SHans Verkuil if (no_signal(sd)) { 15051e0b9156SMartin Bugge state->restart_stdi_once = true; 150654450f59SHans Verkuil v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__); 150754450f59SHans Verkuil return -ENOLINK; 150854450f59SHans Verkuil } 150954450f59SHans Verkuil 151054450f59SHans Verkuil /* read STDI */ 151154450f59SHans Verkuil if (read_stdi(sd, &stdi)) { 151254450f59SHans Verkuil v4l2_dbg(1, debug, sd, "%s: STDI/SSPD not locked\n", __func__); 151354450f59SHans Verkuil return -ENOLINK; 151454450f59SHans Verkuil } 151554450f59SHans Verkuil bt->interlaced = stdi.interlaced ? 151654450f59SHans Verkuil V4L2_DV_INTERLACED : V4L2_DV_PROGRESSIVE; 151754450f59SHans Verkuil 15184a31a93aSMats Randgaard if (is_digital_input(sd)) { 151954450f59SHans Verkuil timings->type = V4L2_DV_BT_656_1120; 152054450f59SHans Verkuil 15215380baafSjean-michel.hautbois@vodalys.com bt->width = hdmi_read16(sd, 0x07, info->linewidth_mask); 15225380baafSjean-michel.hautbois@vodalys.com bt->height = hdmi_read16(sd, 0x09, info->field0_height_mask); 1523d42010a1SLars-Peter Clausen bt->pixelclock = info->read_hdmi_pixelclock(sd); 15245380baafSjean-michel.hautbois@vodalys.com bt->hfrontporch = hdmi_read16(sd, 0x20, info->hfrontporch_mask); 15255380baafSjean-michel.hautbois@vodalys.com bt->hsync = hdmi_read16(sd, 0x22, info->hsync_mask); 15265380baafSjean-michel.hautbois@vodalys.com bt->hbackporch = hdmi_read16(sd, 0x24, info->hbackporch_mask); 15275380baafSjean-michel.hautbois@vodalys.com bt->vfrontporch = hdmi_read16(sd, 0x2a, 15285380baafSjean-michel.hautbois@vodalys.com info->field0_vfrontporch_mask) / 2; 15295380baafSjean-michel.hautbois@vodalys.com bt->vsync = hdmi_read16(sd, 0x2e, info->field0_vsync_mask) / 2; 15305380baafSjean-michel.hautbois@vodalys.com bt->vbackporch = hdmi_read16(sd, 0x32, 15315380baafSjean-michel.hautbois@vodalys.com info->field0_vbackporch_mask) / 2; 153254450f59SHans Verkuil bt->polarities = ((hdmi_read(sd, 0x05) & 0x10) ? V4L2_DV_VSYNC_POS_POL : 0) | 153354450f59SHans Verkuil ((hdmi_read(sd, 0x05) & 0x20) ? V4L2_DV_HSYNC_POS_POL : 0); 153454450f59SHans Verkuil if (bt->interlaced == V4L2_DV_INTERLACED) { 15355380baafSjean-michel.hautbois@vodalys.com bt->height += hdmi_read16(sd, 0x0b, 15365380baafSjean-michel.hautbois@vodalys.com info->field1_height_mask); 15375380baafSjean-michel.hautbois@vodalys.com bt->il_vfrontporch = hdmi_read16(sd, 0x2c, 15385380baafSjean-michel.hautbois@vodalys.com info->field1_vfrontporch_mask) / 2; 15395380baafSjean-michel.hautbois@vodalys.com bt->il_vsync = hdmi_read16(sd, 0x30, 15405380baafSjean-michel.hautbois@vodalys.com info->field1_vsync_mask) / 2; 15415380baafSjean-michel.hautbois@vodalys.com bt->il_vbackporch = hdmi_read16(sd, 0x34, 15425380baafSjean-michel.hautbois@vodalys.com info->field1_vbackporch_mask) / 2; 154354450f59SHans Verkuil } 1544b44b2e06SPablo Anton adv76xx_fill_optional_dv_timings_fields(sd, timings); 154554450f59SHans Verkuil } else { 154654450f59SHans Verkuil /* find format 154780939647SHans Verkuil * Since LCVS values are inaccurate [REF_03, p. 275-276], 154854450f59SHans Verkuil * stdi2dv_timings() is called with lcvs +-1 if the first attempt fails. 154954450f59SHans Verkuil */ 155054450f59SHans Verkuil if (!stdi2dv_timings(sd, &stdi, timings)) 155154450f59SHans Verkuil goto found; 155254450f59SHans Verkuil stdi.lcvs += 1; 155354450f59SHans Verkuil v4l2_dbg(1, debug, sd, "%s: lcvs + 1 = %d\n", __func__, stdi.lcvs); 155454450f59SHans Verkuil if (!stdi2dv_timings(sd, &stdi, timings)) 155554450f59SHans Verkuil goto found; 155654450f59SHans Verkuil stdi.lcvs -= 2; 155754450f59SHans Verkuil v4l2_dbg(1, debug, sd, "%s: lcvs - 1 = %d\n", __func__, stdi.lcvs); 155854450f59SHans Verkuil if (stdi2dv_timings(sd, &stdi, timings)) { 1559cf9afb1dSHans Verkuil /* 1560cf9afb1dSHans Verkuil * The STDI block may measure wrong values, especially 1561cf9afb1dSHans Verkuil * for lcvs and lcf. If the driver can not find any 1562cf9afb1dSHans Verkuil * valid timing, the STDI block is restarted to measure 1563cf9afb1dSHans Verkuil * the video timings again. The function will return an 1564cf9afb1dSHans Verkuil * error, but the restart of STDI will generate a new 1565cf9afb1dSHans Verkuil * STDI interrupt and the format detection process will 1566cf9afb1dSHans Verkuil * restart. 1567cf9afb1dSHans Verkuil */ 1568cf9afb1dSHans Verkuil if (state->restart_stdi_once) { 1569cf9afb1dSHans Verkuil v4l2_dbg(1, debug, sd, "%s: restart STDI\n", __func__); 1570cf9afb1dSHans Verkuil /* TODO restart STDI for Sync Channel 2 */ 1571cf9afb1dSHans Verkuil /* enter one-shot mode */ 157222d97e56SLaurent Pinchart cp_write_clr_set(sd, 0x86, 0x06, 0x00); 1573cf9afb1dSHans Verkuil /* trigger STDI restart */ 157422d97e56SLaurent Pinchart cp_write_clr_set(sd, 0x86, 0x06, 0x04); 1575cf9afb1dSHans Verkuil /* reset to continuous mode */ 157622d97e56SLaurent Pinchart cp_write_clr_set(sd, 0x86, 0x06, 0x02); 1577cf9afb1dSHans Verkuil state->restart_stdi_once = false; 1578cf9afb1dSHans Verkuil return -ENOLINK; 1579cf9afb1dSHans Verkuil } 158054450f59SHans Verkuil v4l2_dbg(1, debug, sd, "%s: format not supported\n", __func__); 158154450f59SHans Verkuil return -ERANGE; 158254450f59SHans Verkuil } 1583cf9afb1dSHans Verkuil state->restart_stdi_once = true; 158454450f59SHans Verkuil } 158554450f59SHans Verkuil found: 158654450f59SHans Verkuil 158754450f59SHans Verkuil if (no_signal(sd)) { 158854450f59SHans Verkuil v4l2_dbg(1, debug, sd, "%s: signal lost during readout\n", __func__); 158954450f59SHans Verkuil memset(timings, 0, sizeof(struct v4l2_dv_timings)); 159054450f59SHans Verkuil return -ENOLINK; 159154450f59SHans Verkuil } 159254450f59SHans Verkuil 15934a31a93aSMats Randgaard if ((is_analog_input(sd) && bt->pixelclock > 170000000) || 15944a31a93aSMats Randgaard (is_digital_input(sd) && bt->pixelclock > 225000000)) { 159554450f59SHans Verkuil v4l2_dbg(1, debug, sd, "%s: pixelclock out of range %d\n", 159654450f59SHans Verkuil __func__, (u32)bt->pixelclock); 159754450f59SHans Verkuil return -ERANGE; 159854450f59SHans Verkuil } 159954450f59SHans Verkuil 160054450f59SHans Verkuil if (debug > 1) 1601b44b2e06SPablo Anton v4l2_print_dv_timings(sd->name, "adv76xx_query_dv_timings: ", 160211d034c8SHans Verkuil timings, true); 160354450f59SHans Verkuil 160454450f59SHans Verkuil return 0; 160554450f59SHans Verkuil } 160654450f59SHans Verkuil 1607b44b2e06SPablo Anton static int adv76xx_s_dv_timings(struct v4l2_subdev *sd, 160854450f59SHans Verkuil struct v4l2_dv_timings *timings) 160954450f59SHans Verkuil { 1610b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 161154450f59SHans Verkuil struct v4l2_bt_timings *bt; 1612ccbd5bc4SHans Verkuil int err; 161354450f59SHans Verkuil 161454450f59SHans Verkuil if (!timings) 161554450f59SHans Verkuil return -EINVAL; 161654450f59SHans Verkuil 1617d48eb48cSMats Randgaard if (v4l2_match_dv_timings(&state->timings, timings, 0)) { 1618d48eb48cSMats Randgaard v4l2_dbg(1, debug, sd, "%s: no change\n", __func__); 1619d48eb48cSMats Randgaard return 0; 1620d48eb48cSMats Randgaard } 1621d48eb48cSMats Randgaard 162254450f59SHans Verkuil bt = &timings->bt; 162354450f59SHans Verkuil 16244a31a93aSMats Randgaard if ((is_analog_input(sd) && bt->pixelclock > 170000000) || 16254a31a93aSMats Randgaard (is_digital_input(sd) && bt->pixelclock > 225000000)) { 162654450f59SHans Verkuil v4l2_dbg(1, debug, sd, "%s: pixelclock out of range %d\n", 162754450f59SHans Verkuil __func__, (u32)bt->pixelclock); 162854450f59SHans Verkuil return -ERANGE; 162954450f59SHans Verkuil } 1630ccbd5bc4SHans Verkuil 1631b44b2e06SPablo Anton adv76xx_fill_optional_dv_timings_fields(sd, timings); 163254450f59SHans Verkuil 163354450f59SHans Verkuil state->timings = *timings; 163454450f59SHans Verkuil 163522d97e56SLaurent Pinchart cp_write_clr_set(sd, 0x91, 0x40, bt->interlaced ? 0x40 : 0x00); 1636ccbd5bc4SHans Verkuil 1637ccbd5bc4SHans Verkuil /* Use prim_mode and vid_std when available */ 1638ccbd5bc4SHans Verkuil err = configure_predefined_video_timings(sd, timings); 1639ccbd5bc4SHans Verkuil if (err) { 1640ccbd5bc4SHans Verkuil /* custom settings when the video format 1641ccbd5bc4SHans Verkuil does not have prim_mode/vid_std */ 1642ccbd5bc4SHans Verkuil configure_custom_video_timings(sd, bt); 1643ccbd5bc4SHans Verkuil } 164454450f59SHans Verkuil 164554450f59SHans Verkuil set_rgb_quantization_range(sd); 164654450f59SHans Verkuil 164754450f59SHans Verkuil if (debug > 1) 1648b44b2e06SPablo Anton v4l2_print_dv_timings(sd->name, "adv76xx_s_dv_timings: ", 164911d034c8SHans Verkuil timings, true); 165054450f59SHans Verkuil return 0; 165154450f59SHans Verkuil } 165254450f59SHans Verkuil 1653b44b2e06SPablo Anton static int adv76xx_g_dv_timings(struct v4l2_subdev *sd, 165454450f59SHans Verkuil struct v4l2_dv_timings *timings) 165554450f59SHans Verkuil { 1656b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 165754450f59SHans Verkuil 165854450f59SHans Verkuil *timings = state->timings; 165954450f59SHans Verkuil return 0; 166054450f59SHans Verkuil } 166154450f59SHans Verkuil 1662d42010a1SLars-Peter Clausen static void adv7604_set_termination(struct v4l2_subdev *sd, bool enable) 1663d42010a1SLars-Peter Clausen { 1664d42010a1SLars-Peter Clausen hdmi_write(sd, 0x01, enable ? 0x00 : 0x78); 1665d42010a1SLars-Peter Clausen } 1666d42010a1SLars-Peter Clausen 1667d42010a1SLars-Peter Clausen static void adv7611_set_termination(struct v4l2_subdev *sd, bool enable) 1668d42010a1SLars-Peter Clausen { 1669d42010a1SLars-Peter Clausen hdmi_write(sd, 0x83, enable ? 0xfe : 0xff); 1670d42010a1SLars-Peter Clausen } 1671d42010a1SLars-Peter Clausen 16726b0d5d34SHans Verkuil static void enable_input(struct v4l2_subdev *sd) 167354450f59SHans Verkuil { 1674b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 16756b0d5d34SHans Verkuil 16764a31a93aSMats Randgaard if (is_analog_input(sd)) { 167754450f59SHans Verkuil io_write(sd, 0x15, 0xb0); /* Disable Tristate of Pins (no audio) */ 16784a31a93aSMats Randgaard } else if (is_digital_input(sd)) { 167922d97e56SLaurent Pinchart hdmi_write_clr_set(sd, 0x00, 0x03, state->selected_input); 1680d42010a1SLars-Peter Clausen state->info->set_termination(sd, true); 168154450f59SHans Verkuil io_write(sd, 0x15, 0xa0); /* Disable Tristate of Pins */ 168222d97e56SLaurent Pinchart hdmi_write_clr_set(sd, 0x1a, 0x10, 0x00); /* Unmute audio */ 16834a31a93aSMats Randgaard } else { 16844a31a93aSMats Randgaard v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n", 16854a31a93aSMats Randgaard __func__, state->selected_input); 168654450f59SHans Verkuil } 168754450f59SHans Verkuil } 168854450f59SHans Verkuil 168954450f59SHans Verkuil static void disable_input(struct v4l2_subdev *sd) 169054450f59SHans Verkuil { 1691b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 1692d42010a1SLars-Peter Clausen 169322d97e56SLaurent Pinchart hdmi_write_clr_set(sd, 0x1a, 0x10, 0x10); /* Mute audio */ 16945474b983SMats Randgaard msleep(16); /* 512 samples with >= 32 kHz sample rate [REF_03, c. 7.16.10] */ 169554450f59SHans Verkuil io_write(sd, 0x15, 0xbe); /* Tristate all outputs from video core */ 1696d42010a1SLars-Peter Clausen state->info->set_termination(sd, false); 169754450f59SHans Verkuil } 169854450f59SHans Verkuil 16996b0d5d34SHans Verkuil static void select_input(struct v4l2_subdev *sd) 170054450f59SHans Verkuil { 1701b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 1702b44b2e06SPablo Anton const struct adv76xx_chip_info *info = state->info; 170354450f59SHans Verkuil 17044a31a93aSMats Randgaard if (is_analog_input(sd)) { 1705b44b2e06SPablo Anton adv76xx_write_reg_seq(sd, info->recommended_settings[0]); 170654450f59SHans Verkuil 170754450f59SHans Verkuil afe_write(sd, 0x00, 0x08); /* power up ADC */ 170854450f59SHans Verkuil afe_write(sd, 0x01, 0x06); /* power up Analog Front End */ 170954450f59SHans Verkuil afe_write(sd, 0xc8, 0x00); /* phase control */ 17104a31a93aSMats Randgaard } else if (is_digital_input(sd)) { 17114a31a93aSMats Randgaard hdmi_write(sd, 0x00, state->selected_input & 0x03); 171254450f59SHans Verkuil 1713b44b2e06SPablo Anton adv76xx_write_reg_seq(sd, info->recommended_settings[1]); 171454450f59SHans Verkuil 1715b44b2e06SPablo Anton if (adv76xx_has_afe(state)) { 171654450f59SHans Verkuil afe_write(sd, 0x00, 0xff); /* power down ADC */ 171754450f59SHans Verkuil afe_write(sd, 0x01, 0xfe); /* power down Analog Front End */ 171854450f59SHans Verkuil afe_write(sd, 0xc8, 0x40); /* phase control */ 1719d42010a1SLars-Peter Clausen } 172054450f59SHans Verkuil 172154450f59SHans Verkuil cp_write(sd, 0x3e, 0x00); /* CP core pre-gain control */ 172254450f59SHans Verkuil cp_write(sd, 0xc3, 0x39); /* CP coast control. Graphics mode */ 172354450f59SHans Verkuil cp_write(sd, 0x40, 0x80); /* CP core pre-gain control. Graphics mode */ 17244a31a93aSMats Randgaard } else { 17254a31a93aSMats Randgaard v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n", 17264a31a93aSMats Randgaard __func__, state->selected_input); 172754450f59SHans Verkuil } 172854450f59SHans Verkuil } 172954450f59SHans Verkuil 1730b44b2e06SPablo Anton static int adv76xx_s_routing(struct v4l2_subdev *sd, 173154450f59SHans Verkuil u32 input, u32 output, u32 config) 173254450f59SHans Verkuil { 1733b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 173454450f59SHans Verkuil 1735ff4f80fdSMats Randgaard v4l2_dbg(2, debug, sd, "%s: input %d, selected input %d", 1736ff4f80fdSMats Randgaard __func__, input, state->selected_input); 1737ff4f80fdSMats Randgaard 1738ff4f80fdSMats Randgaard if (input == state->selected_input) 1739ff4f80fdSMats Randgaard return 0; 174054450f59SHans Verkuil 1741d42010a1SLars-Peter Clausen if (input > state->info->max_port) 1742d42010a1SLars-Peter Clausen return -EINVAL; 1743d42010a1SLars-Peter Clausen 17444a31a93aSMats Randgaard state->selected_input = input; 174554450f59SHans Verkuil 174654450f59SHans Verkuil disable_input(sd); 174754450f59SHans Verkuil 17486b0d5d34SHans Verkuil select_input(sd); 174954450f59SHans Verkuil 17506b0d5d34SHans Verkuil enable_input(sd); 175154450f59SHans Verkuil 175254450f59SHans Verkuil return 0; 175354450f59SHans Verkuil } 175454450f59SHans Verkuil 1755b44b2e06SPablo Anton static int adv76xx_enum_mbus_code(struct v4l2_subdev *sd, 1756f7234138SHans Verkuil struct v4l2_subdev_pad_config *cfg, 1757539b33b0SLaurent Pinchart struct v4l2_subdev_mbus_code_enum *code) 175854450f59SHans Verkuil { 1759b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 176054450f59SHans Verkuil 1761539b33b0SLaurent Pinchart if (code->index >= state->info->nformats) 1762539b33b0SLaurent Pinchart return -EINVAL; 1763539b33b0SLaurent Pinchart 1764539b33b0SLaurent Pinchart code->code = state->info->formats[code->index].code; 1765539b33b0SLaurent Pinchart 1766539b33b0SLaurent Pinchart return 0; 1767539b33b0SLaurent Pinchart } 1768539b33b0SLaurent Pinchart 1769b44b2e06SPablo Anton static void adv76xx_fill_format(struct adv76xx_state *state, 1770539b33b0SLaurent Pinchart struct v4l2_mbus_framefmt *format) 1771539b33b0SLaurent Pinchart { 1772539b33b0SLaurent Pinchart memset(format, 0, sizeof(*format)); 1773539b33b0SLaurent Pinchart 1774539b33b0SLaurent Pinchart format->width = state->timings.bt.width; 1775539b33b0SLaurent Pinchart format->height = state->timings.bt.height; 1776539b33b0SLaurent Pinchart format->field = V4L2_FIELD_NONE; 1777680fee04SHans Verkuil format->colorspace = V4L2_COLORSPACE_SRGB; 1778539b33b0SLaurent Pinchart 1779680fee04SHans Verkuil if (state->timings.bt.flags & V4L2_DV_FL_IS_CE_VIDEO) 1780539b33b0SLaurent Pinchart format->colorspace = (state->timings.bt.height <= 576) ? 178154450f59SHans Verkuil V4L2_COLORSPACE_SMPTE170M : V4L2_COLORSPACE_REC709; 178254450f59SHans Verkuil } 1783539b33b0SLaurent Pinchart 1784539b33b0SLaurent Pinchart /* 1785539b33b0SLaurent Pinchart * Compute the op_ch_sel value required to obtain on the bus the component order 1786539b33b0SLaurent Pinchart * corresponding to the selected format taking into account bus reordering 1787539b33b0SLaurent Pinchart * applied by the board at the output of the device. 1788539b33b0SLaurent Pinchart * 1789539b33b0SLaurent Pinchart * The following table gives the op_ch_value from the format component order 1790539b33b0SLaurent Pinchart * (expressed as op_ch_sel value in column) and the bus reordering (expressed as 1791b44b2e06SPablo Anton * adv76xx_bus_order value in row). 1792539b33b0SLaurent Pinchart * 1793539b33b0SLaurent Pinchart * | GBR(0) GRB(1) BGR(2) RGB(3) BRG(4) RBG(5) 1794539b33b0SLaurent Pinchart * ----------+------------------------------------------------- 1795539b33b0SLaurent Pinchart * RGB (NOP) | GBR GRB BGR RGB BRG RBG 1796539b33b0SLaurent Pinchart * GRB (1-2) | BGR RGB GBR GRB RBG BRG 1797539b33b0SLaurent Pinchart * RBG (2-3) | GRB GBR BRG RBG BGR RGB 1798539b33b0SLaurent Pinchart * BGR (1-3) | RBG BRG RGB BGR GRB GBR 1799539b33b0SLaurent Pinchart * BRG (ROR) | BRG RBG GRB GBR RGB BGR 1800539b33b0SLaurent Pinchart * GBR (ROL) | RGB BGR RBG BRG GBR GRB 1801539b33b0SLaurent Pinchart */ 1802b44b2e06SPablo Anton static unsigned int adv76xx_op_ch_sel(struct adv76xx_state *state) 1803539b33b0SLaurent Pinchart { 1804539b33b0SLaurent Pinchart #define _SEL(a,b,c,d,e,f) { \ 1805b44b2e06SPablo Anton ADV76XX_OP_CH_SEL_##a, ADV76XX_OP_CH_SEL_##b, ADV76XX_OP_CH_SEL_##c, \ 1806b44b2e06SPablo Anton ADV76XX_OP_CH_SEL_##d, ADV76XX_OP_CH_SEL_##e, ADV76XX_OP_CH_SEL_##f } 1807539b33b0SLaurent Pinchart #define _BUS(x) [ADV7604_BUS_ORDER_##x] 1808539b33b0SLaurent Pinchart 1809539b33b0SLaurent Pinchart static const unsigned int op_ch_sel[6][6] = { 1810539b33b0SLaurent Pinchart _BUS(RGB) /* NOP */ = _SEL(GBR, GRB, BGR, RGB, BRG, RBG), 1811539b33b0SLaurent Pinchart _BUS(GRB) /* 1-2 */ = _SEL(BGR, RGB, GBR, GRB, RBG, BRG), 1812539b33b0SLaurent Pinchart _BUS(RBG) /* 2-3 */ = _SEL(GRB, GBR, BRG, RBG, BGR, RGB), 1813539b33b0SLaurent Pinchart _BUS(BGR) /* 1-3 */ = _SEL(RBG, BRG, RGB, BGR, GRB, GBR), 1814539b33b0SLaurent Pinchart _BUS(BRG) /* ROR */ = _SEL(BRG, RBG, GRB, GBR, RGB, BGR), 1815539b33b0SLaurent Pinchart _BUS(GBR) /* ROL */ = _SEL(RGB, BGR, RBG, BRG, GBR, GRB), 1816539b33b0SLaurent Pinchart }; 1817539b33b0SLaurent Pinchart 1818539b33b0SLaurent Pinchart return op_ch_sel[state->pdata.bus_order][state->format->op_ch_sel >> 5]; 1819539b33b0SLaurent Pinchart } 1820539b33b0SLaurent Pinchart 1821b44b2e06SPablo Anton static void adv76xx_setup_format(struct adv76xx_state *state) 1822539b33b0SLaurent Pinchart { 1823539b33b0SLaurent Pinchart struct v4l2_subdev *sd = &state->sd; 1824539b33b0SLaurent Pinchart 182522d97e56SLaurent Pinchart io_write_clr_set(sd, 0x02, 0x02, 1826b44b2e06SPablo Anton state->format->rgb_out ? ADV76XX_RGB_OUT : 0); 1827539b33b0SLaurent Pinchart io_write(sd, 0x03, state->format->op_format_sel | 1828539b33b0SLaurent Pinchart state->pdata.op_format_mode_sel); 1829b44b2e06SPablo Anton io_write_clr_set(sd, 0x04, 0xe0, adv76xx_op_ch_sel(state)); 183022d97e56SLaurent Pinchart io_write_clr_set(sd, 0x05, 0x01, 1831b44b2e06SPablo Anton state->format->swap_cb_cr ? ADV76XX_OP_SWAP_CB_CR : 0); 1832539b33b0SLaurent Pinchart } 1833539b33b0SLaurent Pinchart 1834f7234138SHans Verkuil static int adv76xx_get_format(struct v4l2_subdev *sd, 1835f7234138SHans Verkuil struct v4l2_subdev_pad_config *cfg, 1836539b33b0SLaurent Pinchart struct v4l2_subdev_format *format) 1837539b33b0SLaurent Pinchart { 1838b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 1839539b33b0SLaurent Pinchart 1840539b33b0SLaurent Pinchart if (format->pad != state->source_pad) 1841539b33b0SLaurent Pinchart return -EINVAL; 1842539b33b0SLaurent Pinchart 1843b44b2e06SPablo Anton adv76xx_fill_format(state, &format->format); 1844539b33b0SLaurent Pinchart 1845539b33b0SLaurent Pinchart if (format->which == V4L2_SUBDEV_FORMAT_TRY) { 1846539b33b0SLaurent Pinchart struct v4l2_mbus_framefmt *fmt; 1847539b33b0SLaurent Pinchart 1848f7234138SHans Verkuil fmt = v4l2_subdev_get_try_format(sd, cfg, format->pad); 1849539b33b0SLaurent Pinchart format->format.code = fmt->code; 1850539b33b0SLaurent Pinchart } else { 1851539b33b0SLaurent Pinchart format->format.code = state->format->code; 1852539b33b0SLaurent Pinchart } 1853539b33b0SLaurent Pinchart 1854539b33b0SLaurent Pinchart return 0; 1855539b33b0SLaurent Pinchart } 1856539b33b0SLaurent Pinchart 1857f7234138SHans Verkuil static int adv76xx_set_format(struct v4l2_subdev *sd, 1858f7234138SHans Verkuil struct v4l2_subdev_pad_config *cfg, 1859539b33b0SLaurent Pinchart struct v4l2_subdev_format *format) 1860539b33b0SLaurent Pinchart { 1861b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 1862b44b2e06SPablo Anton const struct adv76xx_format_info *info; 1863539b33b0SLaurent Pinchart 1864539b33b0SLaurent Pinchart if (format->pad != state->source_pad) 1865539b33b0SLaurent Pinchart return -EINVAL; 1866539b33b0SLaurent Pinchart 1867b44b2e06SPablo Anton info = adv76xx_format_info(state, format->format.code); 1868539b33b0SLaurent Pinchart if (info == NULL) 1869b44b2e06SPablo Anton info = adv76xx_format_info(state, MEDIA_BUS_FMT_YUYV8_2X8); 1870539b33b0SLaurent Pinchart 1871b44b2e06SPablo Anton adv76xx_fill_format(state, &format->format); 1872539b33b0SLaurent Pinchart format->format.code = info->code; 1873539b33b0SLaurent Pinchart 1874539b33b0SLaurent Pinchart if (format->which == V4L2_SUBDEV_FORMAT_TRY) { 1875539b33b0SLaurent Pinchart struct v4l2_mbus_framefmt *fmt; 1876539b33b0SLaurent Pinchart 1877f7234138SHans Verkuil fmt = v4l2_subdev_get_try_format(sd, cfg, format->pad); 1878539b33b0SLaurent Pinchart fmt->code = format->format.code; 1879539b33b0SLaurent Pinchart } else { 1880539b33b0SLaurent Pinchart state->format = info; 1881b44b2e06SPablo Anton adv76xx_setup_format(state); 1882539b33b0SLaurent Pinchart } 1883539b33b0SLaurent Pinchart 188454450f59SHans Verkuil return 0; 188554450f59SHans Verkuil } 188654450f59SHans Verkuil 1887b44b2e06SPablo Anton static int adv76xx_isr(struct v4l2_subdev *sd, u32 status, bool *handled) 188854450f59SHans Verkuil { 1889b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 1890b44b2e06SPablo Anton const struct adv76xx_chip_info *info = state->info; 1891f24d229cSMats Randgaard const u8 irq_reg_0x43 = io_read(sd, 0x43); 1892f24d229cSMats Randgaard const u8 irq_reg_0x6b = io_read(sd, 0x6b); 1893f24d229cSMats Randgaard const u8 irq_reg_0x70 = io_read(sd, 0x70); 1894f24d229cSMats Randgaard u8 fmt_change_digital; 1895f24d229cSMats Randgaard u8 fmt_change; 1896f24d229cSMats Randgaard u8 tx_5v; 1897f24d229cSMats Randgaard 1898f24d229cSMats Randgaard if (irq_reg_0x43) 1899f24d229cSMats Randgaard io_write(sd, 0x44, irq_reg_0x43); 1900f24d229cSMats Randgaard if (irq_reg_0x70) 1901f24d229cSMats Randgaard io_write(sd, 0x71, irq_reg_0x70); 1902f24d229cSMats Randgaard if (irq_reg_0x6b) 1903f24d229cSMats Randgaard io_write(sd, 0x6c, irq_reg_0x6b); 190454450f59SHans Verkuil 1905ff4f80fdSMats Randgaard v4l2_dbg(2, debug, sd, "%s: ", __func__); 1906ff4f80fdSMats Randgaard 190754450f59SHans Verkuil /* format change */ 1908f24d229cSMats Randgaard fmt_change = irq_reg_0x43 & 0x98; 1909d42010a1SLars-Peter Clausen fmt_change_digital = is_digital_input(sd) 1910d42010a1SLars-Peter Clausen ? irq_reg_0x6b & info->fmt_change_digital_mask 1911d42010a1SLars-Peter Clausen : 0; 191214d03233SMats Randgaard 191354450f59SHans Verkuil if (fmt_change || fmt_change_digital) { 191454450f59SHans Verkuil v4l2_dbg(1, debug, sd, 191525a64ac9SMats Randgaard "%s: fmt_change = 0x%x, fmt_change_digital = 0x%x\n", 191654450f59SHans Verkuil __func__, fmt_change, fmt_change_digital); 191725a64ac9SMats Randgaard 1918b44b2e06SPablo Anton v4l2_subdev_notify(sd, ADV76XX_FMT_CHANGE, NULL); 191925a64ac9SMats Randgaard 192054450f59SHans Verkuil if (handled) 192154450f59SHans Verkuil *handled = true; 192254450f59SHans Verkuil } 1923f24d229cSMats Randgaard /* HDMI/DVI mode */ 1924f24d229cSMats Randgaard if (irq_reg_0x6b & 0x01) { 1925f24d229cSMats Randgaard v4l2_dbg(1, debug, sd, "%s: irq %s mode\n", __func__, 1926f24d229cSMats Randgaard (io_read(sd, 0x6a) & 0x01) ? "HDMI" : "DVI"); 1927f24d229cSMats Randgaard set_rgb_quantization_range(sd); 1928f24d229cSMats Randgaard if (handled) 1929f24d229cSMats Randgaard *handled = true; 1930f24d229cSMats Randgaard } 1931f24d229cSMats Randgaard 193254450f59SHans Verkuil /* tx 5v detect */ 1933d42010a1SLars-Peter Clausen tx_5v = io_read(sd, 0x70) & info->cable_det_mask; 193454450f59SHans Verkuil if (tx_5v) { 193554450f59SHans Verkuil v4l2_dbg(1, debug, sd, "%s: tx_5v: 0x%x\n", __func__, tx_5v); 193654450f59SHans Verkuil io_write(sd, 0x71, tx_5v); 1937b44b2e06SPablo Anton adv76xx_s_detect_tx_5v_ctrl(sd); 193854450f59SHans Verkuil if (handled) 193954450f59SHans Verkuil *handled = true; 194054450f59SHans Verkuil } 194154450f59SHans Verkuil return 0; 194254450f59SHans Verkuil } 194354450f59SHans Verkuil 1944b44b2e06SPablo Anton static int adv76xx_get_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid) 194554450f59SHans Verkuil { 1946b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 19474a31a93aSMats Randgaard u8 *data = NULL; 194854450f59SHans Verkuil 1949dd9ac11aSHans Verkuil memset(edid->reserved, 0, sizeof(edid->reserved)); 19504a31a93aSMats Randgaard 19514a31a93aSMats Randgaard switch (edid->pad) { 1952b44b2e06SPablo Anton case ADV76XX_PAD_HDMI_PORT_A: 1953c784b1e2SLaurent Pinchart case ADV7604_PAD_HDMI_PORT_B: 1954c784b1e2SLaurent Pinchart case ADV7604_PAD_HDMI_PORT_C: 1955c784b1e2SLaurent Pinchart case ADV7604_PAD_HDMI_PORT_D: 19564a31a93aSMats Randgaard if (state->edid.present & (1 << edid->pad)) 19574a31a93aSMats Randgaard data = state->edid.edid; 19584a31a93aSMats Randgaard break; 19594a31a93aSMats Randgaard default: 19604a31a93aSMats Randgaard return -EINVAL; 19614a31a93aSMats Randgaard } 1962dd9ac11aSHans Verkuil 1963dd9ac11aSHans Verkuil if (edid->start_block == 0 && edid->blocks == 0) { 1964dd9ac11aSHans Verkuil edid->blocks = data ? state->edid.blocks : 0; 1965dd9ac11aSHans Verkuil return 0; 1966dd9ac11aSHans Verkuil } 1967dd9ac11aSHans Verkuil 1968dd9ac11aSHans Verkuil if (data == NULL) 19694a31a93aSMats Randgaard return -ENODATA; 19704a31a93aSMats Randgaard 1971dd9ac11aSHans Verkuil if (edid->start_block >= state->edid.blocks) 1972dd9ac11aSHans Verkuil return -EINVAL; 1973dd9ac11aSHans Verkuil 1974dd9ac11aSHans Verkuil if (edid->start_block + edid->blocks > state->edid.blocks) 1975dd9ac11aSHans Verkuil edid->blocks = state->edid.blocks - edid->start_block; 1976dd9ac11aSHans Verkuil 1977dd9ac11aSHans Verkuil memcpy(edid->edid, data + edid->start_block * 128, edid->blocks * 128); 1978dd9ac11aSHans Verkuil 197954450f59SHans Verkuil return 0; 198054450f59SHans Verkuil } 198154450f59SHans Verkuil 1982dd08beb9SMats Randgaard static int get_edid_spa_location(const u8 *edid) 19833e86aa85SMats Randgaard { 19843e86aa85SMats Randgaard u8 d; 19853e86aa85SMats Randgaard 19863e86aa85SMats Randgaard if ((edid[0x7e] != 1) || 19873e86aa85SMats Randgaard (edid[0x80] != 0x02) || 19883e86aa85SMats Randgaard (edid[0x81] != 0x03)) { 19893e86aa85SMats Randgaard return -1; 19903e86aa85SMats Randgaard } 19913e86aa85SMats Randgaard 19923e86aa85SMats Randgaard /* search Vendor Specific Data Block (tag 3) */ 19933e86aa85SMats Randgaard d = edid[0x82] & 0x7f; 19943e86aa85SMats Randgaard if (d > 4) { 19953e86aa85SMats Randgaard int i = 0x84; 19963e86aa85SMats Randgaard int end = 0x80 + d; 19973e86aa85SMats Randgaard 19983e86aa85SMats Randgaard do { 19993e86aa85SMats Randgaard u8 tag = edid[i] >> 5; 20003e86aa85SMats Randgaard u8 len = edid[i] & 0x1f; 20013e86aa85SMats Randgaard 20023e86aa85SMats Randgaard if ((tag == 3) && (len >= 5)) 20033e86aa85SMats Randgaard return i + 4; 20043e86aa85SMats Randgaard i += len + 1; 20053e86aa85SMats Randgaard } while (i < end); 20063e86aa85SMats Randgaard } 20073e86aa85SMats Randgaard return -1; 20083e86aa85SMats Randgaard } 20093e86aa85SMats Randgaard 2010b44b2e06SPablo Anton static int adv76xx_set_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid) 201154450f59SHans Verkuil { 2012b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 2013b44b2e06SPablo Anton const struct adv76xx_chip_info *info = state->info; 2014dd08beb9SMats Randgaard int spa_loc; 201554450f59SHans Verkuil int err; 2016dd08beb9SMats Randgaard int i; 201754450f59SHans Verkuil 2018dd9ac11aSHans Verkuil memset(edid->reserved, 0, sizeof(edid->reserved)); 2019dd9ac11aSHans Verkuil 2020c784b1e2SLaurent Pinchart if (edid->pad > ADV7604_PAD_HDMI_PORT_D) 202154450f59SHans Verkuil return -EINVAL; 202254450f59SHans Verkuil if (edid->start_block != 0) 202354450f59SHans Verkuil return -EINVAL; 202454450f59SHans Verkuil if (edid->blocks == 0) { 20253e86aa85SMats Randgaard /* Disable hotplug and I2C access to EDID RAM from DDC port */ 20264a31a93aSMats Randgaard state->edid.present &= ~(1 << edid->pad); 2027b44b2e06SPablo Anton adv76xx_set_hpd(state, state->edid.present); 202822d97e56SLaurent Pinchart rep_write_clr_set(sd, info->edid_enable_reg, 0x0f, state->edid.present); 20293e86aa85SMats Randgaard 203054450f59SHans Verkuil /* Fall back to a 16:9 aspect ratio */ 203154450f59SHans Verkuil state->aspect_ratio.numerator = 16; 203254450f59SHans Verkuil state->aspect_ratio.denominator = 9; 20333e86aa85SMats Randgaard 20343e86aa85SMats Randgaard if (!state->edid.present) 20353e86aa85SMats Randgaard state->edid.blocks = 0; 20363e86aa85SMats Randgaard 20373e86aa85SMats Randgaard v4l2_dbg(2, debug, sd, "%s: clear EDID pad %d, edid.present = 0x%x\n", 20383e86aa85SMats Randgaard __func__, edid->pad, state->edid.present); 203954450f59SHans Verkuil return 0; 204054450f59SHans Verkuil } 20414a31a93aSMats Randgaard if (edid->blocks > 2) { 20424a31a93aSMats Randgaard edid->blocks = 2; 204354450f59SHans Verkuil return -E2BIG; 20444a31a93aSMats Randgaard } 20454a31a93aSMats Randgaard 2046dd08beb9SMats Randgaard v4l2_dbg(2, debug, sd, "%s: write EDID pad %d, edid.present = 0x%x\n", 2047dd08beb9SMats Randgaard __func__, edid->pad, state->edid.present); 2048dd08beb9SMats Randgaard 20493e86aa85SMats Randgaard /* Disable hotplug and I2C access to EDID RAM from DDC port */ 20504a31a93aSMats Randgaard cancel_delayed_work_sync(&state->delayed_work_enable_hotplug); 2051b44b2e06SPablo Anton adv76xx_set_hpd(state, 0); 205222d97e56SLaurent Pinchart rep_write_clr_set(sd, info->edid_enable_reg, 0x0f, 0x00); 20533e86aa85SMats Randgaard 2054dd08beb9SMats Randgaard spa_loc = get_edid_spa_location(edid->edid); 2055dd08beb9SMats Randgaard if (spa_loc < 0) 2056dd08beb9SMats Randgaard spa_loc = 0xc0; /* Default value [REF_02, p. 116] */ 2057dd08beb9SMats Randgaard 20583e86aa85SMats Randgaard switch (edid->pad) { 2059b44b2e06SPablo Anton case ADV76XX_PAD_HDMI_PORT_A: 2060dd08beb9SMats Randgaard state->spa_port_a[0] = edid->edid[spa_loc]; 2061dd08beb9SMats Randgaard state->spa_port_a[1] = edid->edid[spa_loc + 1]; 20623e86aa85SMats Randgaard break; 2063c784b1e2SLaurent Pinchart case ADV7604_PAD_HDMI_PORT_B: 2064dd08beb9SMats Randgaard rep_write(sd, 0x70, edid->edid[spa_loc]); 2065dd08beb9SMats Randgaard rep_write(sd, 0x71, edid->edid[spa_loc + 1]); 20663e86aa85SMats Randgaard break; 2067c784b1e2SLaurent Pinchart case ADV7604_PAD_HDMI_PORT_C: 2068dd08beb9SMats Randgaard rep_write(sd, 0x72, edid->edid[spa_loc]); 2069dd08beb9SMats Randgaard rep_write(sd, 0x73, edid->edid[spa_loc + 1]); 20703e86aa85SMats Randgaard break; 2071c784b1e2SLaurent Pinchart case ADV7604_PAD_HDMI_PORT_D: 2072dd08beb9SMats Randgaard rep_write(sd, 0x74, edid->edid[spa_loc]); 2073dd08beb9SMats Randgaard rep_write(sd, 0x75, edid->edid[spa_loc + 1]); 20743e86aa85SMats Randgaard break; 2075dd08beb9SMats Randgaard default: 2076dd08beb9SMats Randgaard return -EINVAL; 20773e86aa85SMats Randgaard } 2078d42010a1SLars-Peter Clausen 2079d42010a1SLars-Peter Clausen if (info->type == ADV7604) { 2080dd08beb9SMats Randgaard rep_write(sd, 0x76, spa_loc & 0xff); 208122d97e56SLaurent Pinchart rep_write_clr_set(sd, 0x77, 0x40, (spa_loc & 0x100) >> 2); 2082d42010a1SLars-Peter Clausen } else { 2083d42010a1SLars-Peter Clausen /* FIXME: Where is the SPA location LSB register ? */ 208422d97e56SLaurent Pinchart rep_write_clr_set(sd, 0x71, 0x01, (spa_loc & 0x100) >> 8); 2085d42010a1SLars-Peter Clausen } 20863e86aa85SMats Randgaard 2087dd08beb9SMats Randgaard edid->edid[spa_loc] = state->spa_port_a[0]; 2088dd08beb9SMats Randgaard edid->edid[spa_loc + 1] = state->spa_port_a[1]; 20894a31a93aSMats Randgaard 20904a31a93aSMats Randgaard memcpy(state->edid.edid, edid->edid, 128 * edid->blocks); 20914a31a93aSMats Randgaard state->edid.blocks = edid->blocks; 209254450f59SHans Verkuil state->aspect_ratio = v4l2_calc_aspect_ratio(edid->edid[0x15], 209354450f59SHans Verkuil edid->edid[0x16]); 20943e86aa85SMats Randgaard state->edid.present |= 1 << edid->pad; 20954a31a93aSMats Randgaard 20964a31a93aSMats Randgaard err = edid_write_block(sd, 128 * edid->blocks, state->edid.edid); 20974a31a93aSMats Randgaard if (err < 0) { 20983e86aa85SMats Randgaard v4l2_err(sd, "error %d writing edid pad %d\n", err, edid->pad); 209954450f59SHans Verkuil return err; 210054450f59SHans Verkuil } 210154450f59SHans Verkuil 2102b44b2e06SPablo Anton /* adv76xx calculates the checksums and enables I2C access to internal 2103dd08beb9SMats Randgaard EDID RAM from DDC port. */ 210422d97e56SLaurent Pinchart rep_write_clr_set(sd, info->edid_enable_reg, 0x0f, state->edid.present); 2105dd08beb9SMats Randgaard 2106dd08beb9SMats Randgaard for (i = 0; i < 1000; i++) { 2107d42010a1SLars-Peter Clausen if (rep_read(sd, info->edid_status_reg) & state->edid.present) 2108dd08beb9SMats Randgaard break; 2109dd08beb9SMats Randgaard mdelay(1); 2110dd08beb9SMats Randgaard } 2111dd08beb9SMats Randgaard if (i == 1000) { 2112dd08beb9SMats Randgaard v4l2_err(sd, "error enabling edid (0x%x)\n", state->edid.present); 2113dd08beb9SMats Randgaard return -EIO; 2114dd08beb9SMats Randgaard } 2115dd08beb9SMats Randgaard 21164a31a93aSMats Randgaard /* enable hotplug after 100 ms */ 21174a31a93aSMats Randgaard queue_delayed_work(state->work_queues, 21184a31a93aSMats Randgaard &state->delayed_work_enable_hotplug, HZ / 10); 21194a31a93aSMats Randgaard return 0; 21204a31a93aSMats Randgaard } 21214a31a93aSMats Randgaard 212254450f59SHans Verkuil /*********** avi info frame CEA-861-E **************/ 212354450f59SHans Verkuil 212454450f59SHans Verkuil static void print_avi_infoframe(struct v4l2_subdev *sd) 212554450f59SHans Verkuil { 212654450f59SHans Verkuil int i; 212754450f59SHans Verkuil u8 buf[14]; 212854450f59SHans Verkuil u8 avi_len; 212954450f59SHans Verkuil u8 avi_ver; 213054450f59SHans Verkuil 2131bb88f325SMartin Bugge if (!is_hdmi(sd)) { 213254450f59SHans Verkuil v4l2_info(sd, "receive DVI-D signal (AVI infoframe not supported)\n"); 213354450f59SHans Verkuil return; 213454450f59SHans Verkuil } 213554450f59SHans Verkuil if (!(io_read(sd, 0x60) & 0x01)) { 213654450f59SHans Verkuil v4l2_info(sd, "AVI infoframe not received\n"); 213754450f59SHans Verkuil return; 213854450f59SHans Verkuil } 213954450f59SHans Verkuil 214054450f59SHans Verkuil if (io_read(sd, 0x83) & 0x01) { 214154450f59SHans Verkuil v4l2_info(sd, "AVI infoframe checksum error has occurred earlier\n"); 214254450f59SHans Verkuil io_write(sd, 0x85, 0x01); /* clear AVI_INF_CKS_ERR_RAW */ 214354450f59SHans Verkuil if (io_read(sd, 0x83) & 0x01) { 214454450f59SHans Verkuil v4l2_info(sd, "AVI infoframe checksum error still present\n"); 214554450f59SHans Verkuil io_write(sd, 0x85, 0x01); /* clear AVI_INF_CKS_ERR_RAW */ 214654450f59SHans Verkuil } 214754450f59SHans Verkuil } 214854450f59SHans Verkuil 214954450f59SHans Verkuil avi_len = infoframe_read(sd, 0xe2); 215054450f59SHans Verkuil avi_ver = infoframe_read(sd, 0xe1); 215154450f59SHans Verkuil v4l2_info(sd, "AVI infoframe version %d (%d byte)\n", 215254450f59SHans Verkuil avi_ver, avi_len); 215354450f59SHans Verkuil 215454450f59SHans Verkuil if (avi_ver != 0x02) 215554450f59SHans Verkuil return; 215654450f59SHans Verkuil 215754450f59SHans Verkuil for (i = 0; i < 14; i++) 215854450f59SHans Verkuil buf[i] = infoframe_read(sd, i); 215954450f59SHans Verkuil 216054450f59SHans Verkuil v4l2_info(sd, 216154450f59SHans Verkuil "\t%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n", 216254450f59SHans Verkuil buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6], buf[7], 216354450f59SHans Verkuil buf[8], buf[9], buf[10], buf[11], buf[12], buf[13]); 216454450f59SHans Verkuil } 216554450f59SHans Verkuil 2166b44b2e06SPablo Anton static int adv76xx_log_status(struct v4l2_subdev *sd) 216754450f59SHans Verkuil { 2168b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 2169b44b2e06SPablo Anton const struct adv76xx_chip_info *info = state->info; 217054450f59SHans Verkuil struct v4l2_dv_timings timings; 217154450f59SHans Verkuil struct stdi_readback stdi; 217254450f59SHans Verkuil u8 reg_io_0x02 = io_read(sd, 0x02); 21734a2ccdd2SLaurent Pinchart u8 edid_enabled; 21744a2ccdd2SLaurent Pinchart u8 cable_det; 217554450f59SHans Verkuil 2176f216ccb3SLars-Peter Clausen static const char * const csc_coeff_sel_rb[16] = { 217754450f59SHans Verkuil "bypassed", "YPbPr601 -> RGB", "reserved", "YPbPr709 -> RGB", 217854450f59SHans Verkuil "reserved", "RGB -> YPbPr601", "reserved", "RGB -> YPbPr709", 217954450f59SHans Verkuil "reserved", "YPbPr709 -> YPbPr601", "YPbPr601 -> YPbPr709", 218054450f59SHans Verkuil "reserved", "reserved", "reserved", "reserved", "manual" 218154450f59SHans Verkuil }; 2182f216ccb3SLars-Peter Clausen static const char * const input_color_space_txt[16] = { 218354450f59SHans Verkuil "RGB limited range (16-235)", "RGB full range (0-255)", 218454450f59SHans Verkuil "YCbCr Bt.601 (16-235)", "YCbCr Bt.709 (16-235)", 21859833239eSMats Randgaard "xvYCC Bt.601", "xvYCC Bt.709", 218654450f59SHans Verkuil "YCbCr Bt.601 (0-255)", "YCbCr Bt.709 (0-255)", 218754450f59SHans Verkuil "invalid", "invalid", "invalid", "invalid", "invalid", 218854450f59SHans Verkuil "invalid", "invalid", "automatic" 218954450f59SHans Verkuil }; 2190f216ccb3SLars-Peter Clausen static const char * const rgb_quantization_range_txt[] = { 219154450f59SHans Verkuil "Automatic", 219254450f59SHans Verkuil "RGB limited range (16-235)", 219354450f59SHans Verkuil "RGB full range (0-255)", 219454450f59SHans Verkuil }; 2195f216ccb3SLars-Peter Clausen static const char * const deep_color_mode_txt[4] = { 2196bb88f325SMartin Bugge "8-bits per channel", 2197bb88f325SMartin Bugge "10-bits per channel", 2198bb88f325SMartin Bugge "12-bits per channel", 2199bb88f325SMartin Bugge "16-bits per channel (not supported)" 2200bb88f325SMartin Bugge }; 220154450f59SHans Verkuil 220254450f59SHans Verkuil v4l2_info(sd, "-----Chip status-----\n"); 220354450f59SHans Verkuil v4l2_info(sd, "Chip power: %s\n", no_power(sd) ? "off" : "on"); 2204d42010a1SLars-Peter Clausen edid_enabled = rep_read(sd, info->edid_status_reg); 22054a31a93aSMats Randgaard v4l2_info(sd, "EDID enabled port A: %s, B: %s, C: %s, D: %s\n", 22064a2ccdd2SLaurent Pinchart ((edid_enabled & 0x01) ? "Yes" : "No"), 22074a2ccdd2SLaurent Pinchart ((edid_enabled & 0x02) ? "Yes" : "No"), 22084a2ccdd2SLaurent Pinchart ((edid_enabled & 0x04) ? "Yes" : "No"), 22094a2ccdd2SLaurent Pinchart ((edid_enabled & 0x08) ? "Yes" : "No")); 221054450f59SHans Verkuil v4l2_info(sd, "CEC: %s\n", !!(cec_read(sd, 0x2a) & 0x01) ? 221154450f59SHans Verkuil "enabled" : "disabled"); 221254450f59SHans Verkuil 221354450f59SHans Verkuil v4l2_info(sd, "-----Signal status-----\n"); 2214d42010a1SLars-Peter Clausen cable_det = info->read_cable_det(sd); 22154a31a93aSMats Randgaard v4l2_info(sd, "Cable detected (+5V power) port A: %s, B: %s, C: %s, D: %s\n", 2216d42010a1SLars-Peter Clausen ((cable_det & 0x01) ? "Yes" : "No"), 2217d42010a1SLars-Peter Clausen ((cable_det & 0x02) ? "Yes" : "No"), 22184a2ccdd2SLaurent Pinchart ((cable_det & 0x04) ? "Yes" : "No"), 2219d42010a1SLars-Peter Clausen ((cable_det & 0x08) ? "Yes" : "No")); 222054450f59SHans Verkuil v4l2_info(sd, "TMDS signal detected: %s\n", 222154450f59SHans Verkuil no_signal_tmds(sd) ? "false" : "true"); 222254450f59SHans Verkuil v4l2_info(sd, "TMDS signal locked: %s\n", 222354450f59SHans Verkuil no_lock_tmds(sd) ? "false" : "true"); 222454450f59SHans Verkuil v4l2_info(sd, "SSPD locked: %s\n", no_lock_sspd(sd) ? "false" : "true"); 222554450f59SHans Verkuil v4l2_info(sd, "STDI locked: %s\n", no_lock_stdi(sd) ? "false" : "true"); 222654450f59SHans Verkuil v4l2_info(sd, "CP locked: %s\n", no_lock_cp(sd) ? "false" : "true"); 222754450f59SHans Verkuil v4l2_info(sd, "CP free run: %s\n", 222858514625Sjean-michel.hautbois@vodalys.com (in_free_run(sd)) ? "on" : "off"); 2229ccbd5bc4SHans Verkuil v4l2_info(sd, "Prim-mode = 0x%x, video std = 0x%x, v_freq = 0x%x\n", 2230ccbd5bc4SHans Verkuil io_read(sd, 0x01) & 0x0f, io_read(sd, 0x00) & 0x3f, 2231ccbd5bc4SHans Verkuil (io_read(sd, 0x01) & 0x70) >> 4); 223254450f59SHans Verkuil 223354450f59SHans Verkuil v4l2_info(sd, "-----Video Timings-----\n"); 223454450f59SHans Verkuil if (read_stdi(sd, &stdi)) 223554450f59SHans Verkuil v4l2_info(sd, "STDI: not locked\n"); 223654450f59SHans Verkuil else 223754450f59SHans Verkuil v4l2_info(sd, "STDI: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %s, %chsync, %cvsync\n", 223854450f59SHans Verkuil stdi.lcf, stdi.bl, stdi.lcvs, 223954450f59SHans Verkuil stdi.interlaced ? "interlaced" : "progressive", 224054450f59SHans Verkuil stdi.hs_pol, stdi.vs_pol); 2241b44b2e06SPablo Anton if (adv76xx_query_dv_timings(sd, &timings)) 224254450f59SHans Verkuil v4l2_info(sd, "No video detected\n"); 224354450f59SHans Verkuil else 224411d034c8SHans Verkuil v4l2_print_dv_timings(sd->name, "Detected format: ", 224511d034c8SHans Verkuil &timings, true); 224611d034c8SHans Verkuil v4l2_print_dv_timings(sd->name, "Configured format: ", 224711d034c8SHans Verkuil &state->timings, true); 224854450f59SHans Verkuil 224976eb2d30SMats Randgaard if (no_signal(sd)) 225076eb2d30SMats Randgaard return 0; 225176eb2d30SMats Randgaard 225254450f59SHans Verkuil v4l2_info(sd, "-----Color space-----\n"); 225354450f59SHans Verkuil v4l2_info(sd, "RGB quantization range ctrl: %s\n", 225454450f59SHans Verkuil rgb_quantization_range_txt[state->rgb_quantization_range]); 225554450f59SHans Verkuil v4l2_info(sd, "Input color space: %s\n", 225654450f59SHans Verkuil input_color_space_txt[reg_io_0x02 >> 4]); 225754450f59SHans Verkuil v4l2_info(sd, "Output color space: %s %s, saturator %s\n", 225854450f59SHans Verkuil (reg_io_0x02 & 0x02) ? "RGB" : "YCbCr", 225954450f59SHans Verkuil (reg_io_0x02 & 0x04) ? "(16-235)" : "(0-255)", 226054450f59SHans Verkuil ((reg_io_0x02 & 0x04) ^ (reg_io_0x02 & 0x01)) ? 226154450f59SHans Verkuil "enabled" : "disabled"); 226254450f59SHans Verkuil v4l2_info(sd, "Color space conversion: %s\n", 226380f4944eSjean-michel.hautbois@vodalys.com csc_coeff_sel_rb[cp_read(sd, info->cp_csc) >> 4]); 226454450f59SHans Verkuil 22654a31a93aSMats Randgaard if (!is_digital_input(sd)) 226676eb2d30SMats Randgaard return 0; 226776eb2d30SMats Randgaard 226876eb2d30SMats Randgaard v4l2_info(sd, "-----%s status-----\n", is_hdmi(sd) ? "HDMI" : "DVI-D"); 22694a31a93aSMats Randgaard v4l2_info(sd, "Digital video port selected: %c\n", 22704a31a93aSMats Randgaard (hdmi_read(sd, 0x00) & 0x03) + 'A'); 22714a31a93aSMats Randgaard v4l2_info(sd, "HDCP encrypted content: %s\n", 22724a31a93aSMats Randgaard (hdmi_read(sd, 0x05) & 0x40) ? "true" : "false"); 227376eb2d30SMats Randgaard v4l2_info(sd, "HDCP keys read: %s%s\n", 227476eb2d30SMats Randgaard (hdmi_read(sd, 0x04) & 0x20) ? "yes" : "no", 227576eb2d30SMats Randgaard (hdmi_read(sd, 0x04) & 0x10) ? "ERROR" : ""); 227677639ff2SHans Verkuil if (is_hdmi(sd)) { 227776eb2d30SMats Randgaard bool audio_pll_locked = hdmi_read(sd, 0x04) & 0x01; 227876eb2d30SMats Randgaard bool audio_sample_packet_detect = hdmi_read(sd, 0x18) & 0x01; 227976eb2d30SMats Randgaard bool audio_mute = io_read(sd, 0x65) & 0x40; 228076eb2d30SMats Randgaard 228176eb2d30SMats Randgaard v4l2_info(sd, "Audio: pll %s, samples %s, %s\n", 228276eb2d30SMats Randgaard audio_pll_locked ? "locked" : "not locked", 228376eb2d30SMats Randgaard audio_sample_packet_detect ? "detected" : "not detected", 228476eb2d30SMats Randgaard audio_mute ? "muted" : "enabled"); 228576eb2d30SMats Randgaard if (audio_pll_locked && audio_sample_packet_detect) { 228676eb2d30SMats Randgaard v4l2_info(sd, "Audio format: %s\n", 228776eb2d30SMats Randgaard (hdmi_read(sd, 0x07) & 0x20) ? "multi-channel" : "stereo"); 228876eb2d30SMats Randgaard } 228976eb2d30SMats Randgaard v4l2_info(sd, "Audio CTS: %u\n", (hdmi_read(sd, 0x5b) << 12) + 229076eb2d30SMats Randgaard (hdmi_read(sd, 0x5c) << 8) + 229176eb2d30SMats Randgaard (hdmi_read(sd, 0x5d) & 0xf0)); 229276eb2d30SMats Randgaard v4l2_info(sd, "Audio N: %u\n", ((hdmi_read(sd, 0x5d) & 0x0f) << 16) + 229376eb2d30SMats Randgaard (hdmi_read(sd, 0x5e) << 8) + 229476eb2d30SMats Randgaard hdmi_read(sd, 0x5f)); 229576eb2d30SMats Randgaard v4l2_info(sd, "AV Mute: %s\n", (hdmi_read(sd, 0x04) & 0x40) ? "on" : "off"); 229676eb2d30SMats Randgaard 229776eb2d30SMats Randgaard v4l2_info(sd, "Deep color mode: %s\n", deep_color_mode_txt[(hdmi_read(sd, 0x0b) & 0x60) >> 5]); 229876eb2d30SMats Randgaard 229954450f59SHans Verkuil print_avi_infoframe(sd); 230054450f59SHans Verkuil } 230154450f59SHans Verkuil 230254450f59SHans Verkuil return 0; 230354450f59SHans Verkuil } 230454450f59SHans Verkuil 230554450f59SHans Verkuil /* ----------------------------------------------------------------------- */ 230654450f59SHans Verkuil 2307b44b2e06SPablo Anton static const struct v4l2_ctrl_ops adv76xx_ctrl_ops = { 2308b44b2e06SPablo Anton .s_ctrl = adv76xx_s_ctrl, 230954450f59SHans Verkuil }; 231054450f59SHans Verkuil 2311b44b2e06SPablo Anton static const struct v4l2_subdev_core_ops adv76xx_core_ops = { 2312b44b2e06SPablo Anton .log_status = adv76xx_log_status, 2313b44b2e06SPablo Anton .interrupt_service_routine = adv76xx_isr, 231454450f59SHans Verkuil #ifdef CONFIG_VIDEO_ADV_DEBUG 2315b44b2e06SPablo Anton .g_register = adv76xx_g_register, 2316b44b2e06SPablo Anton .s_register = adv76xx_s_register, 231754450f59SHans Verkuil #endif 231854450f59SHans Verkuil }; 231954450f59SHans Verkuil 2320b44b2e06SPablo Anton static const struct v4l2_subdev_video_ops adv76xx_video_ops = { 2321b44b2e06SPablo Anton .s_routing = adv76xx_s_routing, 2322b44b2e06SPablo Anton .g_input_status = adv76xx_g_input_status, 2323b44b2e06SPablo Anton .s_dv_timings = adv76xx_s_dv_timings, 2324b44b2e06SPablo Anton .g_dv_timings = adv76xx_g_dv_timings, 2325b44b2e06SPablo Anton .query_dv_timings = adv76xx_query_dv_timings, 232654450f59SHans Verkuil }; 232754450f59SHans Verkuil 2328b44b2e06SPablo Anton static const struct v4l2_subdev_pad_ops adv76xx_pad_ops = { 2329b44b2e06SPablo Anton .enum_mbus_code = adv76xx_enum_mbus_code, 2330b44b2e06SPablo Anton .get_fmt = adv76xx_get_format, 2331b44b2e06SPablo Anton .set_fmt = adv76xx_set_format, 2332b44b2e06SPablo Anton .get_edid = adv76xx_get_edid, 2333b44b2e06SPablo Anton .set_edid = adv76xx_set_edid, 2334b44b2e06SPablo Anton .dv_timings_cap = adv76xx_dv_timings_cap, 2335b44b2e06SPablo Anton .enum_dv_timings = adv76xx_enum_dv_timings, 233654450f59SHans Verkuil }; 233754450f59SHans Verkuil 2338b44b2e06SPablo Anton static const struct v4l2_subdev_ops adv76xx_ops = { 2339b44b2e06SPablo Anton .core = &adv76xx_core_ops, 2340b44b2e06SPablo Anton .video = &adv76xx_video_ops, 2341b44b2e06SPablo Anton .pad = &adv76xx_pad_ops, 234254450f59SHans Verkuil }; 234354450f59SHans Verkuil 234454450f59SHans Verkuil /* -------------------------- custom ctrls ---------------------------------- */ 234554450f59SHans Verkuil 234654450f59SHans Verkuil static const struct v4l2_ctrl_config adv7604_ctrl_analog_sampling_phase = { 2347b44b2e06SPablo Anton .ops = &adv76xx_ctrl_ops, 234854450f59SHans Verkuil .id = V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE, 234954450f59SHans Verkuil .name = "Analog Sampling Phase", 235054450f59SHans Verkuil .type = V4L2_CTRL_TYPE_INTEGER, 235154450f59SHans Verkuil .min = 0, 235254450f59SHans Verkuil .max = 0x1f, 235354450f59SHans Verkuil .step = 1, 235454450f59SHans Verkuil .def = 0, 235554450f59SHans Verkuil }; 235654450f59SHans Verkuil 2357b44b2e06SPablo Anton static const struct v4l2_ctrl_config adv76xx_ctrl_free_run_color_manual = { 2358b44b2e06SPablo Anton .ops = &adv76xx_ctrl_ops, 235954450f59SHans Verkuil .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL, 236054450f59SHans Verkuil .name = "Free Running Color, Manual", 236154450f59SHans Verkuil .type = V4L2_CTRL_TYPE_BOOLEAN, 236254450f59SHans Verkuil .min = false, 236354450f59SHans Verkuil .max = true, 236454450f59SHans Verkuil .step = 1, 236554450f59SHans Verkuil .def = false, 236654450f59SHans Verkuil }; 236754450f59SHans Verkuil 2368b44b2e06SPablo Anton static const struct v4l2_ctrl_config adv76xx_ctrl_free_run_color = { 2369b44b2e06SPablo Anton .ops = &adv76xx_ctrl_ops, 237054450f59SHans Verkuil .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR, 237154450f59SHans Verkuil .name = "Free Running Color", 237254450f59SHans Verkuil .type = V4L2_CTRL_TYPE_INTEGER, 237354450f59SHans Verkuil .min = 0x0, 237454450f59SHans Verkuil .max = 0xffffff, 237554450f59SHans Verkuil .step = 0x1, 237654450f59SHans Verkuil .def = 0x0, 237754450f59SHans Verkuil }; 237854450f59SHans Verkuil 237954450f59SHans Verkuil /* ----------------------------------------------------------------------- */ 238054450f59SHans Verkuil 2381b44b2e06SPablo Anton static int adv76xx_core_init(struct v4l2_subdev *sd) 238254450f59SHans Verkuil { 2383b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 2384b44b2e06SPablo Anton const struct adv76xx_chip_info *info = state->info; 2385b44b2e06SPablo Anton struct adv76xx_platform_data *pdata = &state->pdata; 238654450f59SHans Verkuil 238754450f59SHans Verkuil hdmi_write(sd, 0x48, 238854450f59SHans Verkuil (pdata->disable_pwrdnb ? 0x80 : 0) | 238954450f59SHans Verkuil (pdata->disable_cable_det_rst ? 0x40 : 0)); 239054450f59SHans Verkuil 239154450f59SHans Verkuil disable_input(sd); 239254450f59SHans Verkuil 23935ef54b59SLaurent Pinchart if (pdata->default_input >= 0 && 23945ef54b59SLaurent Pinchart pdata->default_input < state->source_pad) { 23955ef54b59SLaurent Pinchart state->selected_input = pdata->default_input; 23965ef54b59SLaurent Pinchart select_input(sd); 23975ef54b59SLaurent Pinchart enable_input(sd); 23985ef54b59SLaurent Pinchart } 23995ef54b59SLaurent Pinchart 240054450f59SHans Verkuil /* power */ 240154450f59SHans Verkuil io_write(sd, 0x0c, 0x42); /* Power up part and power down VDP */ 240254450f59SHans Verkuil io_write(sd, 0x0b, 0x44); /* Power down ESDP block */ 240354450f59SHans Verkuil cp_write(sd, 0xcf, 0x01); /* Power down macrovision */ 240454450f59SHans Verkuil 240554450f59SHans Verkuil /* video format */ 240622d97e56SLaurent Pinchart io_write_clr_set(sd, 0x02, 0x0f, 240754450f59SHans Verkuil pdata->alt_gamma << 3 | 240854450f59SHans Verkuil pdata->op_656_range << 2 | 240954450f59SHans Verkuil pdata->alt_data_sat << 0); 241022d97e56SLaurent Pinchart io_write_clr_set(sd, 0x05, 0x0e, pdata->blank_data << 3 | 241154450f59SHans Verkuil pdata->insert_av_codes << 2 | 2412539b33b0SLaurent Pinchart pdata->replicate_av_codes << 1); 2413b44b2e06SPablo Anton adv76xx_setup_format(state); 241454450f59SHans Verkuil 241554450f59SHans Verkuil cp_write(sd, 0x69, 0x30); /* Enable CP CSC */ 241698908696SMartin Bugge 241798908696SMartin Bugge /* VS, HS polarities */ 24181b5ab875SLaurent Pinchart io_write(sd, 0x06, 0xa0 | pdata->inv_vs_pol << 2 | 24191b5ab875SLaurent Pinchart pdata->inv_hs_pol << 1 | pdata->inv_llc_pol); 2420f31b62e1SMikhail Khelik 2421f31b62e1SMikhail Khelik /* Adjust drive strength */ 2422f31b62e1SMikhail Khelik io_write(sd, 0x14, 0x40 | pdata->dr_str_data << 4 | 2423f31b62e1SMikhail Khelik pdata->dr_str_clk << 2 | 2424f31b62e1SMikhail Khelik pdata->dr_str_sync); 2425f31b62e1SMikhail Khelik 242654450f59SHans Verkuil cp_write(sd, 0xba, (pdata->hdmi_free_run_mode << 1) | 0x01); /* HDMI free run */ 242754450f59SHans Verkuil cp_write(sd, 0xf3, 0xdc); /* Low threshold to enter/exit free run mode */ 242854450f59SHans Verkuil cp_write(sd, 0xf9, 0x23); /* STDI ch. 1 - LCVS change threshold - 242980939647SHans Verkuil ADI recommended setting [REF_01, c. 2.3.3] */ 243054450f59SHans Verkuil cp_write(sd, 0x45, 0x23); /* STDI ch. 2 - LCVS change threshold - 243180939647SHans Verkuil ADI recommended setting [REF_01, c. 2.3.3] */ 243254450f59SHans Verkuil cp_write(sd, 0xc9, 0x2d); /* use prim_mode and vid_std as free run resolution 243354450f59SHans Verkuil for digital formats */ 243454450f59SHans Verkuil 24355474b983SMats Randgaard /* HDMI audio */ 243622d97e56SLaurent Pinchart hdmi_write_clr_set(sd, 0x15, 0x03, 0x03); /* Mute on FIFO over-/underflow [REF_01, c. 1.2.18] */ 243722d97e56SLaurent Pinchart hdmi_write_clr_set(sd, 0x1a, 0x0e, 0x08); /* Wait 1 s before unmute */ 243822d97e56SLaurent Pinchart hdmi_write_clr_set(sd, 0x68, 0x06, 0x06); /* FIFO reset on over-/underflow [REF_01, c. 1.2.19] */ 24395474b983SMats Randgaard 244054450f59SHans Verkuil /* TODO from platform data */ 244154450f59SHans Verkuil afe_write(sd, 0xb5, 0x01); /* Setting MCLK to 256Fs */ 244254450f59SHans Verkuil 2443b44b2e06SPablo Anton if (adv76xx_has_afe(state)) { 244454450f59SHans Verkuil afe_write(sd, 0x02, pdata->ain_sel); /* Select analog input muxing mode */ 244522d97e56SLaurent Pinchart io_write_clr_set(sd, 0x30, 1 << 4, pdata->output_bus_lsb_to_msb << 4); 2446d42010a1SLars-Peter Clausen } 244754450f59SHans Verkuil 244854450f59SHans Verkuil /* interrupts */ 2449d42010a1SLars-Peter Clausen io_write(sd, 0x40, 0xc0 | pdata->int1_config); /* Configure INT1 */ 245054450f59SHans Verkuil io_write(sd, 0x46, 0x98); /* Enable SSPD, STDI and CP unlocked interrupts */ 2451d42010a1SLars-Peter Clausen io_write(sd, 0x6e, info->fmt_change_digital_mask); /* Enable V_LOCKED and DE_REGEN_LCK interrupts */ 2452d42010a1SLars-Peter Clausen io_write(sd, 0x73, info->cable_det_mask); /* Enable cable detection (+5v) interrupts */ 2453d42010a1SLars-Peter Clausen info->setup_irqs(sd); 245454450f59SHans Verkuil 245554450f59SHans Verkuil return v4l2_ctrl_handler_setup(sd->ctrl_handler); 245654450f59SHans Verkuil } 245754450f59SHans Verkuil 2458d42010a1SLars-Peter Clausen static void adv7604_setup_irqs(struct v4l2_subdev *sd) 2459d42010a1SLars-Peter Clausen { 2460d42010a1SLars-Peter Clausen io_write(sd, 0x41, 0xd7); /* STDI irq for any change, disable INT2 */ 2461d42010a1SLars-Peter Clausen } 2462d42010a1SLars-Peter Clausen 2463d42010a1SLars-Peter Clausen static void adv7611_setup_irqs(struct v4l2_subdev *sd) 2464d42010a1SLars-Peter Clausen { 2465d42010a1SLars-Peter Clausen io_write(sd, 0x41, 0xd0); /* STDI irq for any change, disable INT2 */ 2466d42010a1SLars-Peter Clausen } 2467d42010a1SLars-Peter Clausen 2468b44b2e06SPablo Anton static void adv76xx_unregister_clients(struct adv76xx_state *state) 246954450f59SHans Verkuil { 247005cacb17SLaurent Pinchart unsigned int i; 247105cacb17SLaurent Pinchart 247205cacb17SLaurent Pinchart for (i = 1; i < ARRAY_SIZE(state->i2c_clients); ++i) { 247305cacb17SLaurent Pinchart if (state->i2c_clients[i]) 247405cacb17SLaurent Pinchart i2c_unregister_device(state->i2c_clients[i]); 247505cacb17SLaurent Pinchart } 247654450f59SHans Verkuil } 247754450f59SHans Verkuil 2478b44b2e06SPablo Anton static struct i2c_client *adv76xx_dummy_client(struct v4l2_subdev *sd, 247954450f59SHans Verkuil u8 addr, u8 io_reg) 248054450f59SHans Verkuil { 248154450f59SHans Verkuil struct i2c_client *client = v4l2_get_subdevdata(sd); 248254450f59SHans Verkuil 248354450f59SHans Verkuil if (addr) 248454450f59SHans Verkuil io_write(sd, io_reg, addr << 1); 248554450f59SHans Verkuil return i2c_new_dummy(client->adapter, io_read(sd, io_reg) >> 1); 248654450f59SHans Verkuil } 248754450f59SHans Verkuil 2488b44b2e06SPablo Anton static const struct adv76xx_reg_seq adv7604_recommended_settings_afe[] = { 2489d42010a1SLars-Peter Clausen /* reset ADI recommended settings for HDMI: */ 2490d42010a1SLars-Peter Clausen /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 4. */ 2491b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x0d), 0x04 }, /* HDMI filter optimization */ 2492b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x0d), 0x04 }, /* HDMI filter optimization */ 2493b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x3d), 0x00 }, /* DDC bus active pull-up control */ 2494b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x3e), 0x74 }, /* TMDS PLL optimization */ 2495b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x4e), 0x3b }, /* TMDS PLL optimization */ 2496b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x57), 0x74 }, /* TMDS PLL optimization */ 2497b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x58), 0x63 }, /* TMDS PLL optimization */ 2498b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8d), 0x18 }, /* equaliser */ 2499b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8e), 0x34 }, /* equaliser */ 2500b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x93), 0x88 }, /* equaliser */ 2501b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x94), 0x2e }, /* equaliser */ 2502b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x96), 0x00 }, /* enable automatic EQ changing */ 2503d42010a1SLars-Peter Clausen 2504d42010a1SLars-Peter Clausen /* set ADI recommended settings for digitizer */ 2505d42010a1SLars-Peter Clausen /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 17. */ 2506b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_AFE, 0x12), 0x7b }, /* ADC noise shaping filter controls */ 2507b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_AFE, 0x0c), 0x1f }, /* CP core gain controls */ 2508b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_CP, 0x3e), 0x04 }, /* CP core pre-gain control */ 2509b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_CP, 0xc3), 0x39 }, /* CP coast control. Graphics mode */ 2510b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_CP, 0x40), 0x5c }, /* CP core pre-gain control. Graphics mode */ 2511d42010a1SLars-Peter Clausen 2512b44b2e06SPablo Anton { ADV76XX_REG_SEQ_TERM, 0 }, 2513d42010a1SLars-Peter Clausen }; 2514d42010a1SLars-Peter Clausen 2515b44b2e06SPablo Anton static const struct adv76xx_reg_seq adv7604_recommended_settings_hdmi[] = { 2516d42010a1SLars-Peter Clausen /* set ADI recommended settings for HDMI: */ 2517d42010a1SLars-Peter Clausen /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 4. */ 2518b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x0d), 0x84 }, /* HDMI filter optimization */ 2519b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x3d), 0x10 }, /* DDC bus active pull-up control */ 2520b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x3e), 0x39 }, /* TMDS PLL optimization */ 2521b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x4e), 0x3b }, /* TMDS PLL optimization */ 2522b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x57), 0xb6 }, /* TMDS PLL optimization */ 2523b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x58), 0x03 }, /* TMDS PLL optimization */ 2524b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8d), 0x18 }, /* equaliser */ 2525b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8e), 0x34 }, /* equaliser */ 2526b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x93), 0x8b }, /* equaliser */ 2527b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x94), 0x2d }, /* equaliser */ 2528b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x96), 0x01 }, /* enable automatic EQ changing */ 2529d42010a1SLars-Peter Clausen 2530d42010a1SLars-Peter Clausen /* reset ADI recommended settings for digitizer */ 2531d42010a1SLars-Peter Clausen /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 17. */ 2532b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_AFE, 0x12), 0xfb }, /* ADC noise shaping filter controls */ 2533b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_AFE, 0x0c), 0x0d }, /* CP core gain controls */ 2534d42010a1SLars-Peter Clausen 2535b44b2e06SPablo Anton { ADV76XX_REG_SEQ_TERM, 0 }, 2536d42010a1SLars-Peter Clausen }; 2537d42010a1SLars-Peter Clausen 2538b44b2e06SPablo Anton static const struct adv76xx_reg_seq adv7611_recommended_settings_hdmi[] = { 2539c41ad9c3SLars-Peter Clausen /* ADV7611 Register Settings Recommendations Rev 1.5, May 2014 */ 2540b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_CP, 0x6c), 0x00 }, 2541b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x9b), 0x03 }, 2542b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x6f), 0x08 }, 2543b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x85), 0x1f }, 2544b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x87), 0x70 }, 2545b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x57), 0xda }, 2546b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x58), 0x01 }, 2547b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x03), 0x98 }, 2548b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x4c), 0x44 }, 2549b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8d), 0x04 }, 2550b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8e), 0x1e }, 2551d42010a1SLars-Peter Clausen 2552b44b2e06SPablo Anton { ADV76XX_REG_SEQ_TERM, 0 }, 2553d42010a1SLars-Peter Clausen }; 2554d42010a1SLars-Peter Clausen 2555b44b2e06SPablo Anton static const struct adv76xx_chip_info adv76xx_chip_info[] = { 2556d42010a1SLars-Peter Clausen [ADV7604] = { 2557d42010a1SLars-Peter Clausen .type = ADV7604, 2558d42010a1SLars-Peter Clausen .has_afe = true, 2559c784b1e2SLaurent Pinchart .max_port = ADV7604_PAD_VGA_COMP, 2560d42010a1SLars-Peter Clausen .num_dv_ports = 4, 2561d42010a1SLars-Peter Clausen .edid_enable_reg = 0x77, 2562d42010a1SLars-Peter Clausen .edid_status_reg = 0x7d, 2563d42010a1SLars-Peter Clausen .lcf_reg = 0xb3, 2564d42010a1SLars-Peter Clausen .tdms_lock_mask = 0xe0, 2565d42010a1SLars-Peter Clausen .cable_det_mask = 0x1e, 2566d42010a1SLars-Peter Clausen .fmt_change_digital_mask = 0xc1, 256780f4944eSjean-michel.hautbois@vodalys.com .cp_csc = 0xfc, 2568539b33b0SLaurent Pinchart .formats = adv7604_formats, 2569539b33b0SLaurent Pinchart .nformats = ARRAY_SIZE(adv7604_formats), 2570d42010a1SLars-Peter Clausen .set_termination = adv7604_set_termination, 2571d42010a1SLars-Peter Clausen .setup_irqs = adv7604_setup_irqs, 2572d42010a1SLars-Peter Clausen .read_hdmi_pixelclock = adv7604_read_hdmi_pixelclock, 2573d42010a1SLars-Peter Clausen .read_cable_det = adv7604_read_cable_det, 2574d42010a1SLars-Peter Clausen .recommended_settings = { 2575d42010a1SLars-Peter Clausen [0] = adv7604_recommended_settings_afe, 2576d42010a1SLars-Peter Clausen [1] = adv7604_recommended_settings_hdmi, 2577d42010a1SLars-Peter Clausen }, 2578d42010a1SLars-Peter Clausen .num_recommended_settings = { 2579d42010a1SLars-Peter Clausen [0] = ARRAY_SIZE(adv7604_recommended_settings_afe), 2580d42010a1SLars-Peter Clausen [1] = ARRAY_SIZE(adv7604_recommended_settings_hdmi), 2581d42010a1SLars-Peter Clausen }, 2582b44b2e06SPablo Anton .page_mask = BIT(ADV76XX_PAGE_IO) | BIT(ADV7604_PAGE_AVLINK) | 2583b44b2e06SPablo Anton BIT(ADV76XX_PAGE_CEC) | BIT(ADV76XX_PAGE_INFOFRAME) | 2584d42010a1SLars-Peter Clausen BIT(ADV7604_PAGE_ESDP) | BIT(ADV7604_PAGE_DPP) | 2585b44b2e06SPablo Anton BIT(ADV76XX_PAGE_AFE) | BIT(ADV76XX_PAGE_REP) | 2586b44b2e06SPablo Anton BIT(ADV76XX_PAGE_EDID) | BIT(ADV76XX_PAGE_HDMI) | 2587b44b2e06SPablo Anton BIT(ADV76XX_PAGE_TEST) | BIT(ADV76XX_PAGE_CP) | 2588d42010a1SLars-Peter Clausen BIT(ADV7604_PAGE_VDP), 25895380baafSjean-michel.hautbois@vodalys.com .linewidth_mask = 0xfff, 25905380baafSjean-michel.hautbois@vodalys.com .field0_height_mask = 0xfff, 25915380baafSjean-michel.hautbois@vodalys.com .field1_height_mask = 0xfff, 25925380baafSjean-michel.hautbois@vodalys.com .hfrontporch_mask = 0x3ff, 25935380baafSjean-michel.hautbois@vodalys.com .hsync_mask = 0x3ff, 25945380baafSjean-michel.hautbois@vodalys.com .hbackporch_mask = 0x3ff, 25955380baafSjean-michel.hautbois@vodalys.com .field0_vfrontporch_mask = 0x1fff, 25965380baafSjean-michel.hautbois@vodalys.com .field0_vsync_mask = 0x1fff, 25975380baafSjean-michel.hautbois@vodalys.com .field0_vbackporch_mask = 0x1fff, 25985380baafSjean-michel.hautbois@vodalys.com .field1_vfrontporch_mask = 0x1fff, 25995380baafSjean-michel.hautbois@vodalys.com .field1_vsync_mask = 0x1fff, 26005380baafSjean-michel.hautbois@vodalys.com .field1_vbackporch_mask = 0x1fff, 2601d42010a1SLars-Peter Clausen }, 2602d42010a1SLars-Peter Clausen [ADV7611] = { 2603d42010a1SLars-Peter Clausen .type = ADV7611, 2604d42010a1SLars-Peter Clausen .has_afe = false, 2605b44b2e06SPablo Anton .max_port = ADV76XX_PAD_HDMI_PORT_A, 2606d42010a1SLars-Peter Clausen .num_dv_ports = 1, 2607d42010a1SLars-Peter Clausen .edid_enable_reg = 0x74, 2608d42010a1SLars-Peter Clausen .edid_status_reg = 0x76, 2609d42010a1SLars-Peter Clausen .lcf_reg = 0xa3, 2610d42010a1SLars-Peter Clausen .tdms_lock_mask = 0x43, 2611d42010a1SLars-Peter Clausen .cable_det_mask = 0x01, 2612d42010a1SLars-Peter Clausen .fmt_change_digital_mask = 0x03, 261380f4944eSjean-michel.hautbois@vodalys.com .cp_csc = 0xf4, 2614539b33b0SLaurent Pinchart .formats = adv7611_formats, 2615539b33b0SLaurent Pinchart .nformats = ARRAY_SIZE(adv7611_formats), 2616d42010a1SLars-Peter Clausen .set_termination = adv7611_set_termination, 2617d42010a1SLars-Peter Clausen .setup_irqs = adv7611_setup_irqs, 2618d42010a1SLars-Peter Clausen .read_hdmi_pixelclock = adv7611_read_hdmi_pixelclock, 2619d42010a1SLars-Peter Clausen .read_cable_det = adv7611_read_cable_det, 2620d42010a1SLars-Peter Clausen .recommended_settings = { 2621d42010a1SLars-Peter Clausen [1] = adv7611_recommended_settings_hdmi, 2622d42010a1SLars-Peter Clausen }, 2623d42010a1SLars-Peter Clausen .num_recommended_settings = { 2624d42010a1SLars-Peter Clausen [1] = ARRAY_SIZE(adv7611_recommended_settings_hdmi), 2625d42010a1SLars-Peter Clausen }, 2626b44b2e06SPablo Anton .page_mask = BIT(ADV76XX_PAGE_IO) | BIT(ADV76XX_PAGE_CEC) | 2627b44b2e06SPablo Anton BIT(ADV76XX_PAGE_INFOFRAME) | BIT(ADV76XX_PAGE_AFE) | 2628b44b2e06SPablo Anton BIT(ADV76XX_PAGE_REP) | BIT(ADV76XX_PAGE_EDID) | 2629b44b2e06SPablo Anton BIT(ADV76XX_PAGE_HDMI) | BIT(ADV76XX_PAGE_CP), 26305380baafSjean-michel.hautbois@vodalys.com .linewidth_mask = 0x1fff, 26315380baafSjean-michel.hautbois@vodalys.com .field0_height_mask = 0x1fff, 26325380baafSjean-michel.hautbois@vodalys.com .field1_height_mask = 0x1fff, 26335380baafSjean-michel.hautbois@vodalys.com .hfrontporch_mask = 0x1fff, 26345380baafSjean-michel.hautbois@vodalys.com .hsync_mask = 0x1fff, 26355380baafSjean-michel.hautbois@vodalys.com .hbackporch_mask = 0x1fff, 26365380baafSjean-michel.hautbois@vodalys.com .field0_vfrontporch_mask = 0x3fff, 26375380baafSjean-michel.hautbois@vodalys.com .field0_vsync_mask = 0x3fff, 26385380baafSjean-michel.hautbois@vodalys.com .field0_vbackporch_mask = 0x3fff, 26395380baafSjean-michel.hautbois@vodalys.com .field1_vfrontporch_mask = 0x3fff, 26405380baafSjean-michel.hautbois@vodalys.com .field1_vsync_mask = 0x3fff, 26415380baafSjean-michel.hautbois@vodalys.com .field1_vbackporch_mask = 0x3fff, 2642d42010a1SLars-Peter Clausen }, 2643d42010a1SLars-Peter Clausen }; 2644d42010a1SLars-Peter Clausen 2645b44b2e06SPablo Anton static struct i2c_device_id adv76xx_i2c_id[] = { 2646b44b2e06SPablo Anton { "adv7604", (kernel_ulong_t)&adv76xx_chip_info[ADV7604] }, 2647b44b2e06SPablo Anton { "adv7611", (kernel_ulong_t)&adv76xx_chip_info[ADV7611] }, 2648f82f313eSLaurent Pinchart { } 2649f82f313eSLaurent Pinchart }; 2650b44b2e06SPablo Anton MODULE_DEVICE_TABLE(i2c, adv76xx_i2c_id); 2651f82f313eSLaurent Pinchart 2652b44b2e06SPablo Anton static struct of_device_id adv76xx_of_id[] __maybe_unused = { 2653b44b2e06SPablo Anton { .compatible = "adi,adv7611", .data = &adv76xx_chip_info[ADV7611] }, 2654f82f313eSLaurent Pinchart { } 2655f82f313eSLaurent Pinchart }; 2656b44b2e06SPablo Anton MODULE_DEVICE_TABLE(of, adv76xx_of_id); 2657f82f313eSLaurent Pinchart 2658b44b2e06SPablo Anton static int adv76xx_parse_dt(struct adv76xx_state *state) 2659f82f313eSLaurent Pinchart { 26606fa88045SLaurent Pinchart struct v4l2_of_endpoint bus_cfg; 26616fa88045SLaurent Pinchart struct device_node *endpoint; 26626fa88045SLaurent Pinchart struct device_node *np; 26636fa88045SLaurent Pinchart unsigned int flags; 26646fa88045SLaurent Pinchart 2665b44b2e06SPablo Anton np = state->i2c_clients[ADV76XX_PAGE_IO]->dev.of_node; 26666fa88045SLaurent Pinchart 26676fa88045SLaurent Pinchart /* Parse the endpoint. */ 26686fa88045SLaurent Pinchart endpoint = of_graph_get_next_endpoint(np, NULL); 26696fa88045SLaurent Pinchart if (!endpoint) 26706fa88045SLaurent Pinchart return -EINVAL; 26716fa88045SLaurent Pinchart 26726fa88045SLaurent Pinchart v4l2_of_parse_endpoint(endpoint, &bus_cfg); 26736fa88045SLaurent Pinchart of_node_put(endpoint); 26746fa88045SLaurent Pinchart 26756fa88045SLaurent Pinchart flags = bus_cfg.bus.parallel.flags; 26766fa88045SLaurent Pinchart 26776fa88045SLaurent Pinchart if (flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH) 26786fa88045SLaurent Pinchart state->pdata.inv_hs_pol = 1; 26796fa88045SLaurent Pinchart 26806fa88045SLaurent Pinchart if (flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH) 26816fa88045SLaurent Pinchart state->pdata.inv_vs_pol = 1; 26826fa88045SLaurent Pinchart 26836fa88045SLaurent Pinchart if (flags & V4L2_MBUS_PCLK_SAMPLE_RISING) 26846fa88045SLaurent Pinchart state->pdata.inv_llc_pol = 1; 26856fa88045SLaurent Pinchart 26866fa88045SLaurent Pinchart if (bus_cfg.bus_type == V4L2_MBUS_BT656) { 26876fa88045SLaurent Pinchart state->pdata.insert_av_codes = 1; 26886fa88045SLaurent Pinchart state->pdata.op_656_range = 1; 26896fa88045SLaurent Pinchart } 26906fa88045SLaurent Pinchart 2691f82f313eSLaurent Pinchart /* Disable the interrupt for now as no DT-based board uses it. */ 2692b44b2e06SPablo Anton state->pdata.int1_config = ADV76XX_INT1_CONFIG_DISABLED; 2693f82f313eSLaurent Pinchart 2694f82f313eSLaurent Pinchart /* Use the default I2C addresses. */ 2695f82f313eSLaurent Pinchart state->pdata.i2c_addresses[ADV7604_PAGE_AVLINK] = 0x42; 2696b44b2e06SPablo Anton state->pdata.i2c_addresses[ADV76XX_PAGE_CEC] = 0x40; 2697b44b2e06SPablo Anton state->pdata.i2c_addresses[ADV76XX_PAGE_INFOFRAME] = 0x3e; 2698f82f313eSLaurent Pinchart state->pdata.i2c_addresses[ADV7604_PAGE_ESDP] = 0x38; 2699f82f313eSLaurent Pinchart state->pdata.i2c_addresses[ADV7604_PAGE_DPP] = 0x3c; 2700b44b2e06SPablo Anton state->pdata.i2c_addresses[ADV76XX_PAGE_AFE] = 0x26; 2701b44b2e06SPablo Anton state->pdata.i2c_addresses[ADV76XX_PAGE_REP] = 0x32; 2702b44b2e06SPablo Anton state->pdata.i2c_addresses[ADV76XX_PAGE_EDID] = 0x36; 2703b44b2e06SPablo Anton state->pdata.i2c_addresses[ADV76XX_PAGE_HDMI] = 0x34; 2704b44b2e06SPablo Anton state->pdata.i2c_addresses[ADV76XX_PAGE_TEST] = 0x30; 2705b44b2e06SPablo Anton state->pdata.i2c_addresses[ADV76XX_PAGE_CP] = 0x22; 2706f82f313eSLaurent Pinchart state->pdata.i2c_addresses[ADV7604_PAGE_VDP] = 0x24; 2707f82f313eSLaurent Pinchart 2708f82f313eSLaurent Pinchart /* Hardcode the remaining platform data fields. */ 2709f82f313eSLaurent Pinchart state->pdata.disable_pwrdnb = 0; 2710f82f313eSLaurent Pinchart state->pdata.disable_cable_det_rst = 0; 2711f82f313eSLaurent Pinchart state->pdata.default_input = -1; 2712f82f313eSLaurent Pinchart state->pdata.blank_data = 1; 2713f82f313eSLaurent Pinchart state->pdata.alt_data_sat = 1; 2714f82f313eSLaurent Pinchart state->pdata.op_format_mode_sel = ADV7604_OP_FORMAT_MODE0; 2715f82f313eSLaurent Pinchart state->pdata.bus_order = ADV7604_BUS_ORDER_RGB; 2716f82f313eSLaurent Pinchart 2717f82f313eSLaurent Pinchart return 0; 2718f82f313eSLaurent Pinchart } 2719f82f313eSLaurent Pinchart 2720b44b2e06SPablo Anton static int adv76xx_probe(struct i2c_client *client, 272154450f59SHans Verkuil const struct i2c_device_id *id) 272254450f59SHans Verkuil { 2723591b72feSHans Verkuil static const struct v4l2_dv_timings cea640x480 = 2724591b72feSHans Verkuil V4L2_DV_BT_CEA_640X480P59_94; 2725b44b2e06SPablo Anton struct adv76xx_state *state; 272654450f59SHans Verkuil struct v4l2_ctrl_handler *hdl; 272754450f59SHans Verkuil struct v4l2_subdev *sd; 2728c784b1e2SLaurent Pinchart unsigned int i; 2729d42010a1SLars-Peter Clausen u16 val; 273054450f59SHans Verkuil int err; 273154450f59SHans Verkuil 273254450f59SHans Verkuil /* Check if the adapter supports the needed features */ 273354450f59SHans Verkuil if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA)) 273454450f59SHans Verkuil return -EIO; 2735b44b2e06SPablo Anton v4l_dbg(1, debug, client, "detecting adv76xx client on address 0x%x\n", 273654450f59SHans Verkuil client->addr << 1); 273754450f59SHans Verkuil 2738c02b211dSLaurent Pinchart state = devm_kzalloc(&client->dev, sizeof(*state), GFP_KERNEL); 273954450f59SHans Verkuil if (!state) { 2740b44b2e06SPablo Anton v4l_err(client, "Could not allocate adv76xx_state memory!\n"); 274154450f59SHans Verkuil return -ENOMEM; 274254450f59SHans Verkuil } 274354450f59SHans Verkuil 2744b44b2e06SPablo Anton state->i2c_clients[ADV76XX_PAGE_IO] = client; 2745d42010a1SLars-Peter Clausen 274625a64ac9SMats Randgaard /* initialize variables */ 274725a64ac9SMats Randgaard state->restart_stdi_once = true; 2748ff4f80fdSMats Randgaard state->selected_input = ~0; 274925a64ac9SMats Randgaard 2750f82f313eSLaurent Pinchart if (IS_ENABLED(CONFIG_OF) && client->dev.of_node) { 2751f82f313eSLaurent Pinchart const struct of_device_id *oid; 2752f82f313eSLaurent Pinchart 2753b44b2e06SPablo Anton oid = of_match_node(adv76xx_of_id, client->dev.of_node); 2754f82f313eSLaurent Pinchart state->info = oid->data; 2755f82f313eSLaurent Pinchart 2756b44b2e06SPablo Anton err = adv76xx_parse_dt(state); 2757f82f313eSLaurent Pinchart if (err < 0) { 2758f82f313eSLaurent Pinchart v4l_err(client, "DT parsing error\n"); 2759f82f313eSLaurent Pinchart return err; 2760f82f313eSLaurent Pinchart } 2761f82f313eSLaurent Pinchart } else if (client->dev.platform_data) { 2762b44b2e06SPablo Anton struct adv76xx_platform_data *pdata = client->dev.platform_data; 2763f82f313eSLaurent Pinchart 2764b44b2e06SPablo Anton state->info = (const struct adv76xx_chip_info *)id->driver_data; 2765f82f313eSLaurent Pinchart state->pdata = *pdata; 2766f82f313eSLaurent Pinchart } else { 276754450f59SHans Verkuil v4l_err(client, "No platform data!\n"); 2768c02b211dSLaurent Pinchart return -ENODEV; 276954450f59SHans Verkuil } 2770e9d50e9eSLaurent Pinchart 2771e9d50e9eSLaurent Pinchart /* Request GPIOs. */ 2772e9d50e9eSLaurent Pinchart for (i = 0; i < state->info->num_dv_ports; ++i) { 2773e9d50e9eSLaurent Pinchart state->hpd_gpio[i] = 2774269bd132SUwe Kleine-König devm_gpiod_get_index_optional(&client->dev, "hpd", i, 2775269bd132SUwe Kleine-König GPIOD_OUT_LOW); 2776e9d50e9eSLaurent Pinchart if (IS_ERR(state->hpd_gpio[i])) 2777269bd132SUwe Kleine-König return PTR_ERR(state->hpd_gpio[i]); 2778e9d50e9eSLaurent Pinchart 2779269bd132SUwe Kleine-König if (state->hpd_gpio[i]) 2780e9d50e9eSLaurent Pinchart v4l_info(client, "Handling HPD %u GPIO\n", i); 2781e9d50e9eSLaurent Pinchart } 2782e9d50e9eSLaurent Pinchart 2783591b72feSHans Verkuil state->timings = cea640x480; 2784b44b2e06SPablo Anton state->format = adv76xx_format_info(state, MEDIA_BUS_FMT_YUYV8_2X8); 278554450f59SHans Verkuil 278654450f59SHans Verkuil sd = &state->sd; 2787b44b2e06SPablo Anton v4l2_i2c_subdev_init(sd, client, &adv76xx_ops); 2788d42010a1SLars-Peter Clausen snprintf(sd->name, sizeof(sd->name), "%s %d-%04x", 2789d42010a1SLars-Peter Clausen id->name, i2c_adapter_id(client->adapter), 2790d42010a1SLars-Peter Clausen client->addr); 279154450f59SHans Verkuil sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; 279254450f59SHans Verkuil 2793d42010a1SLars-Peter Clausen /* 2794d42010a1SLars-Peter Clausen * Verify that the chip is present. On ADV7604 the RD_INFO register only 2795d42010a1SLars-Peter Clausen * identifies the revision, while on ADV7611 it identifies the model as 2796d42010a1SLars-Peter Clausen * well. Use the HDMI slave address on ADV7604 and RD_INFO on ADV7611. 2797d42010a1SLars-Peter Clausen */ 2798d42010a1SLars-Peter Clausen if (state->info->type == ADV7604) { 2799d42010a1SLars-Peter Clausen val = adv_smbus_read_byte_data_check(client, 0xfb, false); 2800d42010a1SLars-Peter Clausen if (val != 0x68) { 280154450f59SHans Verkuil v4l2_info(sd, "not an adv7604 on address 0x%x\n", 280254450f59SHans Verkuil client->addr << 1); 2803c02b211dSLaurent Pinchart return -ENODEV; 280454450f59SHans Verkuil } 2805d42010a1SLars-Peter Clausen } else { 2806d42010a1SLars-Peter Clausen val = (adv_smbus_read_byte_data_check(client, 0xea, false) << 8) 2807d42010a1SLars-Peter Clausen | (adv_smbus_read_byte_data_check(client, 0xeb, false) << 0); 2808d42010a1SLars-Peter Clausen if (val != 0x2051) { 2809d42010a1SLars-Peter Clausen v4l2_info(sd, "not an adv7611 on address 0x%x\n", 2810d42010a1SLars-Peter Clausen client->addr << 1); 2811d42010a1SLars-Peter Clausen return -ENODEV; 2812d42010a1SLars-Peter Clausen } 2813d42010a1SLars-Peter Clausen } 281454450f59SHans Verkuil 281554450f59SHans Verkuil /* control handlers */ 281654450f59SHans Verkuil hdl = &state->hdl; 2817b44b2e06SPablo Anton v4l2_ctrl_handler_init(hdl, adv76xx_has_afe(state) ? 9 : 8); 281854450f59SHans Verkuil 2819b44b2e06SPablo Anton v4l2_ctrl_new_std(hdl, &adv76xx_ctrl_ops, 282054450f59SHans Verkuil V4L2_CID_BRIGHTNESS, -128, 127, 1, 0); 2821b44b2e06SPablo Anton v4l2_ctrl_new_std(hdl, &adv76xx_ctrl_ops, 282254450f59SHans Verkuil V4L2_CID_CONTRAST, 0, 255, 1, 128); 2823b44b2e06SPablo Anton v4l2_ctrl_new_std(hdl, &adv76xx_ctrl_ops, 282454450f59SHans Verkuil V4L2_CID_SATURATION, 0, 255, 1, 128); 2825b44b2e06SPablo Anton v4l2_ctrl_new_std(hdl, &adv76xx_ctrl_ops, 282654450f59SHans Verkuil V4L2_CID_HUE, 0, 128, 1, 0); 282754450f59SHans Verkuil 282854450f59SHans Verkuil /* private controls */ 282954450f59SHans Verkuil state->detect_tx_5v_ctrl = v4l2_ctrl_new_std(hdl, NULL, 2830d42010a1SLars-Peter Clausen V4L2_CID_DV_RX_POWER_PRESENT, 0, 2831d42010a1SLars-Peter Clausen (1 << state->info->num_dv_ports) - 1, 0, 0); 283254450f59SHans Verkuil state->rgb_quantization_range_ctrl = 2833b44b2e06SPablo Anton v4l2_ctrl_new_std_menu(hdl, &adv76xx_ctrl_ops, 283454450f59SHans Verkuil V4L2_CID_DV_RX_RGB_RANGE, V4L2_DV_RGB_RANGE_FULL, 283554450f59SHans Verkuil 0, V4L2_DV_RGB_RANGE_AUTO); 283654450f59SHans Verkuil 283754450f59SHans Verkuil /* custom controls */ 2838b44b2e06SPablo Anton if (adv76xx_has_afe(state)) 283954450f59SHans Verkuil state->analog_sampling_phase_ctrl = 284054450f59SHans Verkuil v4l2_ctrl_new_custom(hdl, &adv7604_ctrl_analog_sampling_phase, NULL); 284154450f59SHans Verkuil state->free_run_color_manual_ctrl = 2842b44b2e06SPablo Anton v4l2_ctrl_new_custom(hdl, &adv76xx_ctrl_free_run_color_manual, NULL); 284354450f59SHans Verkuil state->free_run_color_ctrl = 2844b44b2e06SPablo Anton v4l2_ctrl_new_custom(hdl, &adv76xx_ctrl_free_run_color, NULL); 284554450f59SHans Verkuil 284654450f59SHans Verkuil sd->ctrl_handler = hdl; 284754450f59SHans Verkuil if (hdl->error) { 284854450f59SHans Verkuil err = hdl->error; 284954450f59SHans Verkuil goto err_hdl; 285054450f59SHans Verkuil } 28518c0eadb8SHans Verkuil state->detect_tx_5v_ctrl->is_private = true; 28528c0eadb8SHans Verkuil state->rgb_quantization_range_ctrl->is_private = true; 2853b44b2e06SPablo Anton if (adv76xx_has_afe(state)) 28548c0eadb8SHans Verkuil state->analog_sampling_phase_ctrl->is_private = true; 28558c0eadb8SHans Verkuil state->free_run_color_manual_ctrl->is_private = true; 28568c0eadb8SHans Verkuil state->free_run_color_ctrl->is_private = true; 28578c0eadb8SHans Verkuil 2858b44b2e06SPablo Anton if (adv76xx_s_detect_tx_5v_ctrl(sd)) { 285954450f59SHans Verkuil err = -ENODEV; 286054450f59SHans Verkuil goto err_hdl; 286154450f59SHans Verkuil } 286254450f59SHans Verkuil 2863b44b2e06SPablo Anton for (i = 1; i < ADV76XX_PAGE_MAX; ++i) { 286405cacb17SLaurent Pinchart if (!(BIT(i) & state->info->page_mask)) 286505cacb17SLaurent Pinchart continue; 286605cacb17SLaurent Pinchart 286705cacb17SLaurent Pinchart state->i2c_clients[i] = 2868b44b2e06SPablo Anton adv76xx_dummy_client(sd, state->pdata.i2c_addresses[i], 286905cacb17SLaurent Pinchart 0xf2 + i); 287005cacb17SLaurent Pinchart if (state->i2c_clients[i] == NULL) { 287154450f59SHans Verkuil err = -ENOMEM; 287205cacb17SLaurent Pinchart v4l2_err(sd, "failed to create i2c client %u\n", i); 287354450f59SHans Verkuil goto err_i2c; 287454450f59SHans Verkuil } 287505cacb17SLaurent Pinchart } 287654450f59SHans Verkuil 287754450f59SHans Verkuil /* work queues */ 287854450f59SHans Verkuil state->work_queues = create_singlethread_workqueue(client->name); 287954450f59SHans Verkuil if (!state->work_queues) { 288054450f59SHans Verkuil v4l2_err(sd, "Could not create work queue\n"); 288154450f59SHans Verkuil err = -ENOMEM; 288254450f59SHans Verkuil goto err_i2c; 288354450f59SHans Verkuil } 288454450f59SHans Verkuil 288554450f59SHans Verkuil INIT_DELAYED_WORK(&state->delayed_work_enable_hotplug, 2886b44b2e06SPablo Anton adv76xx_delayed_work_enable_hotplug); 288754450f59SHans Verkuil 2888c784b1e2SLaurent Pinchart state->source_pad = state->info->num_dv_ports 2889c784b1e2SLaurent Pinchart + (state->info->has_afe ? 2 : 0); 2890c784b1e2SLaurent Pinchart for (i = 0; i < state->source_pad; ++i) 2891c784b1e2SLaurent Pinchart state->pads[i].flags = MEDIA_PAD_FL_SINK; 2892c784b1e2SLaurent Pinchart state->pads[state->source_pad].flags = MEDIA_PAD_FL_SOURCE; 2893c784b1e2SLaurent Pinchart 2894c784b1e2SLaurent Pinchart err = media_entity_init(&sd->entity, state->source_pad + 1, 2895c784b1e2SLaurent Pinchart state->pads, 0); 289654450f59SHans Verkuil if (err) 289754450f59SHans Verkuil goto err_work_queues; 289854450f59SHans Verkuil 2899b44b2e06SPablo Anton err = adv76xx_core_init(sd); 290054450f59SHans Verkuil if (err) 290154450f59SHans Verkuil goto err_entity; 290254450f59SHans Verkuil v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name, 290354450f59SHans Verkuil client->addr << 1, client->adapter->name); 2904bedc3939SLars-Peter Clausen 2905bedc3939SLars-Peter Clausen err = v4l2_async_register_subdev(sd); 2906bedc3939SLars-Peter Clausen if (err) 2907bedc3939SLars-Peter Clausen goto err_entity; 2908bedc3939SLars-Peter Clausen 290954450f59SHans Verkuil return 0; 291054450f59SHans Verkuil 291154450f59SHans Verkuil err_entity: 291254450f59SHans Verkuil media_entity_cleanup(&sd->entity); 291354450f59SHans Verkuil err_work_queues: 291454450f59SHans Verkuil cancel_delayed_work(&state->delayed_work_enable_hotplug); 291554450f59SHans Verkuil destroy_workqueue(state->work_queues); 291654450f59SHans Verkuil err_i2c: 2917b44b2e06SPablo Anton adv76xx_unregister_clients(state); 291854450f59SHans Verkuil err_hdl: 291954450f59SHans Verkuil v4l2_ctrl_handler_free(hdl); 292054450f59SHans Verkuil return err; 292154450f59SHans Verkuil } 292254450f59SHans Verkuil 292354450f59SHans Verkuil /* ----------------------------------------------------------------------- */ 292454450f59SHans Verkuil 2925b44b2e06SPablo Anton static int adv76xx_remove(struct i2c_client *client) 292654450f59SHans Verkuil { 292754450f59SHans Verkuil struct v4l2_subdev *sd = i2c_get_clientdata(client); 2928b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd); 292954450f59SHans Verkuil 293054450f59SHans Verkuil cancel_delayed_work(&state->delayed_work_enable_hotplug); 293154450f59SHans Verkuil destroy_workqueue(state->work_queues); 2932bedc3939SLars-Peter Clausen v4l2_async_unregister_subdev(sd); 293354450f59SHans Verkuil media_entity_cleanup(&sd->entity); 2934b44b2e06SPablo Anton adv76xx_unregister_clients(to_state(sd)); 293554450f59SHans Verkuil v4l2_ctrl_handler_free(sd->ctrl_handler); 293654450f59SHans Verkuil return 0; 293754450f59SHans Verkuil } 293854450f59SHans Verkuil 293954450f59SHans Verkuil /* ----------------------------------------------------------------------- */ 294054450f59SHans Verkuil 2941b44b2e06SPablo Anton static struct i2c_driver adv76xx_driver = { 294254450f59SHans Verkuil .driver = { 294354450f59SHans Verkuil .owner = THIS_MODULE, 294454450f59SHans Verkuil .name = "adv7604", 2945b44b2e06SPablo Anton .of_match_table = of_match_ptr(adv76xx_of_id), 294654450f59SHans Verkuil }, 2947b44b2e06SPablo Anton .probe = adv76xx_probe, 2948b44b2e06SPablo Anton .remove = adv76xx_remove, 2949b44b2e06SPablo Anton .id_table = adv76xx_i2c_id, 295054450f59SHans Verkuil }; 295154450f59SHans Verkuil 2952b44b2e06SPablo Anton module_i2c_driver(adv76xx_driver); 2953