154450f59SHans Verkuil /* 254450f59SHans Verkuil * adv7604 - Analog Devices ADV7604 video decoder driver 354450f59SHans Verkuil * 454450f59SHans Verkuil * Copyright 2012 Cisco Systems, Inc. and/or its affiliates. All rights reserved. 554450f59SHans Verkuil * 654450f59SHans Verkuil * This program is free software; you may redistribute it and/or modify 754450f59SHans Verkuil * it under the terms of the GNU General Public License as published by 854450f59SHans Verkuil * the Free Software Foundation; version 2 of the License. 954450f59SHans Verkuil * 1054450f59SHans Verkuil * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 1154450f59SHans Verkuil * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 1254450f59SHans Verkuil * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 1354450f59SHans Verkuil * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 1454450f59SHans Verkuil * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 1554450f59SHans Verkuil * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 1654450f59SHans Verkuil * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 1754450f59SHans Verkuil * SOFTWARE. 1854450f59SHans Verkuil * 1954450f59SHans Verkuil */ 2054450f59SHans Verkuil 2154450f59SHans Verkuil /* 2254450f59SHans Verkuil * References (c = chapter, p = page): 2354450f59SHans Verkuil * REF_01 - Analog devices, ADV7604, Register Settings Recommendations, 2454450f59SHans Verkuil * Revision 2.5, June 2010 2554450f59SHans Verkuil * REF_02 - Analog devices, Register map documentation, Documentation of 2654450f59SHans Verkuil * the register maps, Software manual, Rev. F, June 2010 2754450f59SHans Verkuil * REF_03 - Analog devices, ADV7604, Hardware Manual, Rev. F, August 2010 2854450f59SHans Verkuil */ 2954450f59SHans Verkuil 3054450f59SHans Verkuil 3154450f59SHans Verkuil #include <linux/kernel.h> 3254450f59SHans Verkuil #include <linux/module.h> 3354450f59SHans Verkuil #include <linux/slab.h> 3454450f59SHans Verkuil #include <linux/i2c.h> 3554450f59SHans Verkuil #include <linux/delay.h> 3654450f59SHans Verkuil #include <linux/videodev2.h> 3754450f59SHans Verkuil #include <linux/workqueue.h> 3854450f59SHans Verkuil #include <linux/v4l2-dv-timings.h> 3954450f59SHans Verkuil #include <media/v4l2-device.h> 4054450f59SHans Verkuil #include <media/v4l2-ctrls.h> 4125764158SHans Verkuil #include <media/v4l2-dv-timings.h> 4254450f59SHans Verkuil #include <media/adv7604.h> 4354450f59SHans Verkuil 4454450f59SHans Verkuil static int debug; 4554450f59SHans Verkuil module_param(debug, int, 0644); 4654450f59SHans Verkuil MODULE_PARM_DESC(debug, "debug level (0-2)"); 4754450f59SHans Verkuil 4854450f59SHans Verkuil MODULE_DESCRIPTION("Analog Devices ADV7604 video decoder driver"); 4954450f59SHans Verkuil MODULE_AUTHOR("Hans Verkuil <hans.verkuil@cisco.com>"); 5054450f59SHans Verkuil MODULE_AUTHOR("Mats Randgaard <mats.randgaard@cisco.com>"); 5154450f59SHans Verkuil MODULE_LICENSE("GPL"); 5254450f59SHans Verkuil 5354450f59SHans Verkuil /* ADV7604 system clock frequency */ 5454450f59SHans Verkuil #define ADV7604_fsc (28636360) 5554450f59SHans Verkuil 56539b33b0SLaurent Pinchart #define ADV7604_RGB_OUT (1 << 1) 57539b33b0SLaurent Pinchart 58539b33b0SLaurent Pinchart #define ADV7604_OP_FORMAT_SEL_8BIT (0 << 0) 59539b33b0SLaurent Pinchart #define ADV7604_OP_FORMAT_SEL_10BIT (1 << 0) 60539b33b0SLaurent Pinchart #define ADV7604_OP_FORMAT_SEL_12BIT (2 << 0) 61539b33b0SLaurent Pinchart 62539b33b0SLaurent Pinchart #define ADV7604_OP_MODE_SEL_SDR_422 (0 << 5) 63539b33b0SLaurent Pinchart #define ADV7604_OP_MODE_SEL_DDR_422 (1 << 5) 64539b33b0SLaurent Pinchart #define ADV7604_OP_MODE_SEL_SDR_444 (2 << 5) 65539b33b0SLaurent Pinchart #define ADV7604_OP_MODE_SEL_DDR_444 (3 << 5) 66539b33b0SLaurent Pinchart #define ADV7604_OP_MODE_SEL_SDR_422_2X (4 << 5) 67539b33b0SLaurent Pinchart #define ADV7604_OP_MODE_SEL_ADI_CM (5 << 5) 68539b33b0SLaurent Pinchart 69539b33b0SLaurent Pinchart #define ADV7604_OP_CH_SEL_GBR (0 << 5) 70539b33b0SLaurent Pinchart #define ADV7604_OP_CH_SEL_GRB (1 << 5) 71539b33b0SLaurent Pinchart #define ADV7604_OP_CH_SEL_BGR (2 << 5) 72539b33b0SLaurent Pinchart #define ADV7604_OP_CH_SEL_RGB (3 << 5) 73539b33b0SLaurent Pinchart #define ADV7604_OP_CH_SEL_BRG (4 << 5) 74539b33b0SLaurent Pinchart #define ADV7604_OP_CH_SEL_RBG (5 << 5) 75539b33b0SLaurent Pinchart 76539b33b0SLaurent Pinchart #define ADV7604_OP_SWAP_CB_CR (1 << 0) 77539b33b0SLaurent Pinchart 78d42010a1SLars-Peter Clausen enum adv7604_type { 79d42010a1SLars-Peter Clausen ADV7604, 80d42010a1SLars-Peter Clausen ADV7611, 81d42010a1SLars-Peter Clausen }; 82d42010a1SLars-Peter Clausen 83d42010a1SLars-Peter Clausen struct adv7604_reg_seq { 84d42010a1SLars-Peter Clausen unsigned int reg; 85d42010a1SLars-Peter Clausen u8 val; 86d42010a1SLars-Peter Clausen }; 87d42010a1SLars-Peter Clausen 88539b33b0SLaurent Pinchart struct adv7604_format_info { 89539b33b0SLaurent Pinchart enum v4l2_mbus_pixelcode code; 90539b33b0SLaurent Pinchart u8 op_ch_sel; 91539b33b0SLaurent Pinchart bool rgb_out; 92539b33b0SLaurent Pinchart bool swap_cb_cr; 93539b33b0SLaurent Pinchart u8 op_format_sel; 94539b33b0SLaurent Pinchart }; 95539b33b0SLaurent Pinchart 96d42010a1SLars-Peter Clausen struct adv7604_chip_info { 97d42010a1SLars-Peter Clausen enum adv7604_type type; 98d42010a1SLars-Peter Clausen 99d42010a1SLars-Peter Clausen bool has_afe; 100d42010a1SLars-Peter Clausen unsigned int max_port; 101d42010a1SLars-Peter Clausen unsigned int num_dv_ports; 102d42010a1SLars-Peter Clausen 103d42010a1SLars-Peter Clausen unsigned int edid_enable_reg; 104d42010a1SLars-Peter Clausen unsigned int edid_status_reg; 105d42010a1SLars-Peter Clausen unsigned int lcf_reg; 106d42010a1SLars-Peter Clausen 107d42010a1SLars-Peter Clausen unsigned int cable_det_mask; 108d42010a1SLars-Peter Clausen unsigned int tdms_lock_mask; 109d42010a1SLars-Peter Clausen unsigned int fmt_change_digital_mask; 110d42010a1SLars-Peter Clausen 111539b33b0SLaurent Pinchart const struct adv7604_format_info *formats; 112539b33b0SLaurent Pinchart unsigned int nformats; 113539b33b0SLaurent Pinchart 114d42010a1SLars-Peter Clausen void (*set_termination)(struct v4l2_subdev *sd, bool enable); 115d42010a1SLars-Peter Clausen void (*setup_irqs)(struct v4l2_subdev *sd); 116d42010a1SLars-Peter Clausen unsigned int (*read_hdmi_pixelclock)(struct v4l2_subdev *sd); 117d42010a1SLars-Peter Clausen unsigned int (*read_cable_det)(struct v4l2_subdev *sd); 118d42010a1SLars-Peter Clausen 119d42010a1SLars-Peter Clausen /* 0 = AFE, 1 = HDMI */ 120d42010a1SLars-Peter Clausen const struct adv7604_reg_seq *recommended_settings[2]; 121d42010a1SLars-Peter Clausen unsigned int num_recommended_settings[2]; 122d42010a1SLars-Peter Clausen 123d42010a1SLars-Peter Clausen unsigned long page_mask; 124d42010a1SLars-Peter Clausen }; 125d42010a1SLars-Peter Clausen 12654450f59SHans Verkuil /* 12754450f59SHans Verkuil ********************************************************************** 12854450f59SHans Verkuil * 12954450f59SHans Verkuil * Arrays with configuration parameters for the ADV7604 13054450f59SHans Verkuil * 13154450f59SHans Verkuil ********************************************************************** 13254450f59SHans Verkuil */ 133c784b1e2SLaurent Pinchart 13454450f59SHans Verkuil struct adv7604_state { 135d42010a1SLars-Peter Clausen const struct adv7604_chip_info *info; 13654450f59SHans Verkuil struct adv7604_platform_data pdata; 137539b33b0SLaurent Pinchart 13854450f59SHans Verkuil struct v4l2_subdev sd; 139c784b1e2SLaurent Pinchart struct media_pad pads[ADV7604_PAD_MAX]; 140c784b1e2SLaurent Pinchart unsigned int source_pad; 141539b33b0SLaurent Pinchart 14254450f59SHans Verkuil struct v4l2_ctrl_handler hdl; 143539b33b0SLaurent Pinchart 144c784b1e2SLaurent Pinchart enum adv7604_pad selected_input; 145539b33b0SLaurent Pinchart 14654450f59SHans Verkuil struct v4l2_dv_timings timings; 147539b33b0SLaurent Pinchart const struct adv7604_format_info *format; 148539b33b0SLaurent Pinchart 1494a31a93aSMats Randgaard struct { 15054450f59SHans Verkuil u8 edid[256]; 1514a31a93aSMats Randgaard u32 present; 1524a31a93aSMats Randgaard unsigned blocks; 1534a31a93aSMats Randgaard } edid; 154dd08beb9SMats Randgaard u16 spa_port_a[2]; 15554450f59SHans Verkuil struct v4l2_fract aspect_ratio; 15654450f59SHans Verkuil u32 rgb_quantization_range; 15754450f59SHans Verkuil struct workqueue_struct *work_queues; 15854450f59SHans Verkuil struct delayed_work delayed_work_enable_hotplug; 159cf9afb1dSHans Verkuil bool restart_stdi_once; 16054450f59SHans Verkuil 16154450f59SHans Verkuil /* i2c clients */ 16205cacb17SLaurent Pinchart struct i2c_client *i2c_clients[ADV7604_PAGE_MAX]; 16354450f59SHans Verkuil 16454450f59SHans Verkuil /* controls */ 16554450f59SHans Verkuil struct v4l2_ctrl *detect_tx_5v_ctrl; 16654450f59SHans Verkuil struct v4l2_ctrl *analog_sampling_phase_ctrl; 16754450f59SHans Verkuil struct v4l2_ctrl *free_run_color_manual_ctrl; 16854450f59SHans Verkuil struct v4l2_ctrl *free_run_color_ctrl; 16954450f59SHans Verkuil struct v4l2_ctrl *rgb_quantization_range_ctrl; 17054450f59SHans Verkuil }; 17154450f59SHans Verkuil 172d42010a1SLars-Peter Clausen static bool adv7604_has_afe(struct adv7604_state *state) 173d42010a1SLars-Peter Clausen { 174d42010a1SLars-Peter Clausen return state->info->has_afe; 175d42010a1SLars-Peter Clausen } 176d42010a1SLars-Peter Clausen 17754450f59SHans Verkuil /* Supported CEA and DMT timings */ 17854450f59SHans Verkuil static const struct v4l2_dv_timings adv7604_timings[] = { 17954450f59SHans Verkuil V4L2_DV_BT_CEA_720X480P59_94, 18054450f59SHans Verkuil V4L2_DV_BT_CEA_720X576P50, 18154450f59SHans Verkuil V4L2_DV_BT_CEA_1280X720P24, 18254450f59SHans Verkuil V4L2_DV_BT_CEA_1280X720P25, 18354450f59SHans Verkuil V4L2_DV_BT_CEA_1280X720P50, 18454450f59SHans Verkuil V4L2_DV_BT_CEA_1280X720P60, 18554450f59SHans Verkuil V4L2_DV_BT_CEA_1920X1080P24, 18654450f59SHans Verkuil V4L2_DV_BT_CEA_1920X1080P25, 18754450f59SHans Verkuil V4L2_DV_BT_CEA_1920X1080P30, 18854450f59SHans Verkuil V4L2_DV_BT_CEA_1920X1080P50, 18954450f59SHans Verkuil V4L2_DV_BT_CEA_1920X1080P60, 19054450f59SHans Verkuil 191ccbd5bc4SHans Verkuil /* sorted by DMT ID */ 19254450f59SHans Verkuil V4L2_DV_BT_DMT_640X350P85, 19354450f59SHans Verkuil V4L2_DV_BT_DMT_640X400P85, 19454450f59SHans Verkuil V4L2_DV_BT_DMT_720X400P85, 19554450f59SHans Verkuil V4L2_DV_BT_DMT_640X480P60, 19654450f59SHans Verkuil V4L2_DV_BT_DMT_640X480P72, 19754450f59SHans Verkuil V4L2_DV_BT_DMT_640X480P75, 19854450f59SHans Verkuil V4L2_DV_BT_DMT_640X480P85, 19954450f59SHans Verkuil V4L2_DV_BT_DMT_800X600P56, 20054450f59SHans Verkuil V4L2_DV_BT_DMT_800X600P60, 20154450f59SHans Verkuil V4L2_DV_BT_DMT_800X600P72, 20254450f59SHans Verkuil V4L2_DV_BT_DMT_800X600P75, 20354450f59SHans Verkuil V4L2_DV_BT_DMT_800X600P85, 20454450f59SHans Verkuil V4L2_DV_BT_DMT_848X480P60, 20554450f59SHans Verkuil V4L2_DV_BT_DMT_1024X768P60, 20654450f59SHans Verkuil V4L2_DV_BT_DMT_1024X768P70, 20754450f59SHans Verkuil V4L2_DV_BT_DMT_1024X768P75, 20854450f59SHans Verkuil V4L2_DV_BT_DMT_1024X768P85, 20954450f59SHans Verkuil V4L2_DV_BT_DMT_1152X864P75, 21054450f59SHans Verkuil V4L2_DV_BT_DMT_1280X768P60_RB, 21154450f59SHans Verkuil V4L2_DV_BT_DMT_1280X768P60, 21254450f59SHans Verkuil V4L2_DV_BT_DMT_1280X768P75, 21354450f59SHans Verkuil V4L2_DV_BT_DMT_1280X768P85, 21454450f59SHans Verkuil V4L2_DV_BT_DMT_1280X800P60_RB, 21554450f59SHans Verkuil V4L2_DV_BT_DMT_1280X800P60, 21654450f59SHans Verkuil V4L2_DV_BT_DMT_1280X800P75, 21754450f59SHans Verkuil V4L2_DV_BT_DMT_1280X800P85, 21854450f59SHans Verkuil V4L2_DV_BT_DMT_1280X960P60, 21954450f59SHans Verkuil V4L2_DV_BT_DMT_1280X960P85, 22054450f59SHans Verkuil V4L2_DV_BT_DMT_1280X1024P60, 22154450f59SHans Verkuil V4L2_DV_BT_DMT_1280X1024P75, 22254450f59SHans Verkuil V4L2_DV_BT_DMT_1280X1024P85, 22354450f59SHans Verkuil V4L2_DV_BT_DMT_1360X768P60, 22454450f59SHans Verkuil V4L2_DV_BT_DMT_1400X1050P60_RB, 22554450f59SHans Verkuil V4L2_DV_BT_DMT_1400X1050P60, 22654450f59SHans Verkuil V4L2_DV_BT_DMT_1400X1050P75, 22754450f59SHans Verkuil V4L2_DV_BT_DMT_1400X1050P85, 22854450f59SHans Verkuil V4L2_DV_BT_DMT_1440X900P60_RB, 22954450f59SHans Verkuil V4L2_DV_BT_DMT_1440X900P60, 23054450f59SHans Verkuil V4L2_DV_BT_DMT_1600X1200P60, 23154450f59SHans Verkuil V4L2_DV_BT_DMT_1680X1050P60_RB, 23254450f59SHans Verkuil V4L2_DV_BT_DMT_1680X1050P60, 23354450f59SHans Verkuil V4L2_DV_BT_DMT_1792X1344P60, 23454450f59SHans Verkuil V4L2_DV_BT_DMT_1856X1392P60, 23554450f59SHans Verkuil V4L2_DV_BT_DMT_1920X1200P60_RB, 236547ed542SMartin Bugge V4L2_DV_BT_DMT_1366X768P60_RB, 23754450f59SHans Verkuil V4L2_DV_BT_DMT_1366X768P60, 23854450f59SHans Verkuil V4L2_DV_BT_DMT_1920X1080P60, 23954450f59SHans Verkuil { }, 24054450f59SHans Verkuil }; 24154450f59SHans Verkuil 242ccbd5bc4SHans Verkuil struct adv7604_video_standards { 243ccbd5bc4SHans Verkuil struct v4l2_dv_timings timings; 244ccbd5bc4SHans Verkuil u8 vid_std; 245ccbd5bc4SHans Verkuil u8 v_freq; 246ccbd5bc4SHans Verkuil }; 247ccbd5bc4SHans Verkuil 248ccbd5bc4SHans Verkuil /* sorted by number of lines */ 249ccbd5bc4SHans Verkuil static const struct adv7604_video_standards adv7604_prim_mode_comp[] = { 250ccbd5bc4SHans Verkuil /* { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 }, TODO flickering */ 251ccbd5bc4SHans Verkuil { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 }, 252ccbd5bc4SHans Verkuil { V4L2_DV_BT_CEA_1280X720P50, 0x19, 0x01 }, 253ccbd5bc4SHans Verkuil { V4L2_DV_BT_CEA_1280X720P60, 0x19, 0x00 }, 254ccbd5bc4SHans Verkuil { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 }, 255ccbd5bc4SHans Verkuil { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 }, 256ccbd5bc4SHans Verkuil { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 }, 257ccbd5bc4SHans Verkuil { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 }, 258ccbd5bc4SHans Verkuil { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 }, 259ccbd5bc4SHans Verkuil /* TODO add 1920x1080P60_RB (CVT timing) */ 260ccbd5bc4SHans Verkuil { }, 261ccbd5bc4SHans Verkuil }; 262ccbd5bc4SHans Verkuil 263ccbd5bc4SHans Verkuil /* sorted by number of lines */ 264ccbd5bc4SHans Verkuil static const struct adv7604_video_standards adv7604_prim_mode_gr[] = { 265ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 }, 266ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 }, 267ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 }, 268ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 }, 269ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 }, 270ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 }, 271ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 }, 272ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 }, 273ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 }, 274ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 }, 275ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 }, 276ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 }, 277ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 }, 278ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 }, 279ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 }, 280ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_1360X768P60, 0x12, 0x00 }, 281ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_1366X768P60, 0x13, 0x00 }, 282ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_1400X1050P60, 0x14, 0x00 }, 283ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_1400X1050P75, 0x15, 0x00 }, 284ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_1600X1200P60, 0x16, 0x00 }, /* TODO not tested */ 285ccbd5bc4SHans Verkuil /* TODO add 1600X1200P60_RB (not a DMT timing) */ 286ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_1680X1050P60, 0x18, 0x00 }, 287ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_1920X1200P60_RB, 0x19, 0x00 }, /* TODO not tested */ 288ccbd5bc4SHans Verkuil { }, 289ccbd5bc4SHans Verkuil }; 290ccbd5bc4SHans Verkuil 291ccbd5bc4SHans Verkuil /* sorted by number of lines */ 292ccbd5bc4SHans Verkuil static const struct adv7604_video_standards adv7604_prim_mode_hdmi_comp[] = { 293ccbd5bc4SHans Verkuil { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 }, 294ccbd5bc4SHans Verkuil { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 }, 295ccbd5bc4SHans Verkuil { V4L2_DV_BT_CEA_1280X720P50, 0x13, 0x01 }, 296ccbd5bc4SHans Verkuil { V4L2_DV_BT_CEA_1280X720P60, 0x13, 0x00 }, 297ccbd5bc4SHans Verkuil { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 }, 298ccbd5bc4SHans Verkuil { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 }, 299ccbd5bc4SHans Verkuil { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 }, 300ccbd5bc4SHans Verkuil { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 }, 301ccbd5bc4SHans Verkuil { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 }, 302ccbd5bc4SHans Verkuil { }, 303ccbd5bc4SHans Verkuil }; 304ccbd5bc4SHans Verkuil 305ccbd5bc4SHans Verkuil /* sorted by number of lines */ 306ccbd5bc4SHans Verkuil static const struct adv7604_video_standards adv7604_prim_mode_hdmi_gr[] = { 307ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 }, 308ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 }, 309ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 }, 310ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 }, 311ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 }, 312ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 }, 313ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 }, 314ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 }, 315ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 }, 316ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 }, 317ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 }, 318ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 }, 319ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 }, 320ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 }, 321ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 }, 322ccbd5bc4SHans Verkuil { }, 323ccbd5bc4SHans Verkuil }; 324ccbd5bc4SHans Verkuil 32554450f59SHans Verkuil /* ----------------------------------------------------------------------- */ 32654450f59SHans Verkuil 32754450f59SHans Verkuil static inline struct adv7604_state *to_state(struct v4l2_subdev *sd) 32854450f59SHans Verkuil { 32954450f59SHans Verkuil return container_of(sd, struct adv7604_state, sd); 33054450f59SHans Verkuil } 33154450f59SHans Verkuil 33254450f59SHans Verkuil static inline unsigned hblanking(const struct v4l2_bt_timings *t) 33354450f59SHans Verkuil { 334eacf8f9aSHans Verkuil return V4L2_DV_BT_BLANKING_WIDTH(t); 33554450f59SHans Verkuil } 33654450f59SHans Verkuil 33754450f59SHans Verkuil static inline unsigned htotal(const struct v4l2_bt_timings *t) 33854450f59SHans Verkuil { 339eacf8f9aSHans Verkuil return V4L2_DV_BT_FRAME_WIDTH(t); 34054450f59SHans Verkuil } 34154450f59SHans Verkuil 34254450f59SHans Verkuil static inline unsigned vblanking(const struct v4l2_bt_timings *t) 34354450f59SHans Verkuil { 344eacf8f9aSHans Verkuil return V4L2_DV_BT_BLANKING_HEIGHT(t); 34554450f59SHans Verkuil } 34654450f59SHans Verkuil 34754450f59SHans Verkuil static inline unsigned vtotal(const struct v4l2_bt_timings *t) 34854450f59SHans Verkuil { 349eacf8f9aSHans Verkuil return V4L2_DV_BT_FRAME_HEIGHT(t); 35054450f59SHans Verkuil } 35154450f59SHans Verkuil 35254450f59SHans Verkuil /* ----------------------------------------------------------------------- */ 35354450f59SHans Verkuil 35454450f59SHans Verkuil static s32 adv_smbus_read_byte_data_check(struct i2c_client *client, 35554450f59SHans Verkuil u8 command, bool check) 35654450f59SHans Verkuil { 35754450f59SHans Verkuil union i2c_smbus_data data; 35854450f59SHans Verkuil 35954450f59SHans Verkuil if (!i2c_smbus_xfer(client->adapter, client->addr, client->flags, 36054450f59SHans Verkuil I2C_SMBUS_READ, command, 36154450f59SHans Verkuil I2C_SMBUS_BYTE_DATA, &data)) 36254450f59SHans Verkuil return data.byte; 36354450f59SHans Verkuil if (check) 36454450f59SHans Verkuil v4l_err(client, "error reading %02x, %02x\n", 36554450f59SHans Verkuil client->addr, command); 36654450f59SHans Verkuil return -EIO; 36754450f59SHans Verkuil } 36854450f59SHans Verkuil 36905cacb17SLaurent Pinchart static s32 adv_smbus_read_byte_data(struct adv7604_state *state, 37005cacb17SLaurent Pinchart enum adv7604_page page, u8 command) 37154450f59SHans Verkuil { 37205cacb17SLaurent Pinchart return adv_smbus_read_byte_data_check(state->i2c_clients[page], 37305cacb17SLaurent Pinchart command, true); 37454450f59SHans Verkuil } 37554450f59SHans Verkuil 37605cacb17SLaurent Pinchart static s32 adv_smbus_write_byte_data(struct adv7604_state *state, 37705cacb17SLaurent Pinchart enum adv7604_page page, u8 command, 37805cacb17SLaurent Pinchart u8 value) 37954450f59SHans Verkuil { 38005cacb17SLaurent Pinchart struct i2c_client *client = state->i2c_clients[page]; 38154450f59SHans Verkuil union i2c_smbus_data data; 38254450f59SHans Verkuil int err; 38354450f59SHans Verkuil int i; 38454450f59SHans Verkuil 38554450f59SHans Verkuil data.byte = value; 38654450f59SHans Verkuil for (i = 0; i < 3; i++) { 38754450f59SHans Verkuil err = i2c_smbus_xfer(client->adapter, client->addr, 38854450f59SHans Verkuil client->flags, 38954450f59SHans Verkuil I2C_SMBUS_WRITE, command, 39054450f59SHans Verkuil I2C_SMBUS_BYTE_DATA, &data); 39154450f59SHans Verkuil if (!err) 39254450f59SHans Verkuil break; 39354450f59SHans Verkuil } 39454450f59SHans Verkuil if (err < 0) 39554450f59SHans Verkuil v4l_err(client, "error writing %02x, %02x, %02x\n", 39654450f59SHans Verkuil client->addr, command, value); 39754450f59SHans Verkuil return err; 39854450f59SHans Verkuil } 39954450f59SHans Verkuil 40005cacb17SLaurent Pinchart static s32 adv_smbus_write_i2c_block_data(struct adv7604_state *state, 40105cacb17SLaurent Pinchart enum adv7604_page page, u8 command, 40205cacb17SLaurent Pinchart unsigned length, const u8 *values) 40354450f59SHans Verkuil { 40405cacb17SLaurent Pinchart struct i2c_client *client = state->i2c_clients[page]; 40554450f59SHans Verkuil union i2c_smbus_data data; 40654450f59SHans Verkuil 40754450f59SHans Verkuil if (length > I2C_SMBUS_BLOCK_MAX) 40854450f59SHans Verkuil length = I2C_SMBUS_BLOCK_MAX; 40954450f59SHans Verkuil data.block[0] = length; 41054450f59SHans Verkuil memcpy(data.block + 1, values, length); 41154450f59SHans Verkuil return i2c_smbus_xfer(client->adapter, client->addr, client->flags, 41254450f59SHans Verkuil I2C_SMBUS_WRITE, command, 41354450f59SHans Verkuil I2C_SMBUS_I2C_BLOCK_DATA, &data); 41454450f59SHans Verkuil } 41554450f59SHans Verkuil 41654450f59SHans Verkuil /* ----------------------------------------------------------------------- */ 41754450f59SHans Verkuil 41854450f59SHans Verkuil static inline int io_read(struct v4l2_subdev *sd, u8 reg) 41954450f59SHans Verkuil { 42005cacb17SLaurent Pinchart struct adv7604_state *state = to_state(sd); 42154450f59SHans Verkuil 42205cacb17SLaurent Pinchart return adv_smbus_read_byte_data(state, ADV7604_PAGE_IO, reg); 42354450f59SHans Verkuil } 42454450f59SHans Verkuil 42554450f59SHans Verkuil static inline int io_write(struct v4l2_subdev *sd, u8 reg, u8 val) 42654450f59SHans Verkuil { 42705cacb17SLaurent Pinchart struct adv7604_state *state = to_state(sd); 42854450f59SHans Verkuil 42905cacb17SLaurent Pinchart return adv_smbus_write_byte_data(state, ADV7604_PAGE_IO, reg, val); 43054450f59SHans Verkuil } 43154450f59SHans Verkuil 43222d97e56SLaurent Pinchart static inline int io_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) 43354450f59SHans Verkuil { 43422d97e56SLaurent Pinchart return io_write(sd, reg, (io_read(sd, reg) & ~mask) | val); 43554450f59SHans Verkuil } 43654450f59SHans Verkuil 43754450f59SHans Verkuil static inline int avlink_read(struct v4l2_subdev *sd, u8 reg) 43854450f59SHans Verkuil { 43954450f59SHans Verkuil struct adv7604_state *state = to_state(sd); 44054450f59SHans Verkuil 44105cacb17SLaurent Pinchart return adv_smbus_read_byte_data(state, ADV7604_PAGE_AVLINK, reg); 44254450f59SHans Verkuil } 44354450f59SHans Verkuil 44454450f59SHans Verkuil static inline int avlink_write(struct v4l2_subdev *sd, u8 reg, u8 val) 44554450f59SHans Verkuil { 44654450f59SHans Verkuil struct adv7604_state *state = to_state(sd); 44754450f59SHans Verkuil 44805cacb17SLaurent Pinchart return adv_smbus_write_byte_data(state, ADV7604_PAGE_AVLINK, reg, val); 44954450f59SHans Verkuil } 45054450f59SHans Verkuil 45154450f59SHans Verkuil static inline int cec_read(struct v4l2_subdev *sd, u8 reg) 45254450f59SHans Verkuil { 45354450f59SHans Verkuil struct adv7604_state *state = to_state(sd); 45454450f59SHans Verkuil 45505cacb17SLaurent Pinchart return adv_smbus_read_byte_data(state, ADV7604_PAGE_CEC, reg); 45654450f59SHans Verkuil } 45754450f59SHans Verkuil 45854450f59SHans Verkuil static inline int cec_write(struct v4l2_subdev *sd, u8 reg, u8 val) 45954450f59SHans Verkuil { 46054450f59SHans Verkuil struct adv7604_state *state = to_state(sd); 46154450f59SHans Verkuil 46205cacb17SLaurent Pinchart return adv_smbus_write_byte_data(state, ADV7604_PAGE_CEC, reg, val); 46354450f59SHans Verkuil } 46454450f59SHans Verkuil 46522d97e56SLaurent Pinchart static inline int cec_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) 46654450f59SHans Verkuil { 46722d97e56SLaurent Pinchart return cec_write(sd, reg, (cec_read(sd, reg) & ~mask) | val); 46854450f59SHans Verkuil } 46954450f59SHans Verkuil 47054450f59SHans Verkuil static inline int infoframe_read(struct v4l2_subdev *sd, u8 reg) 47154450f59SHans Verkuil { 47254450f59SHans Verkuil struct adv7604_state *state = to_state(sd); 47354450f59SHans Verkuil 47405cacb17SLaurent Pinchart return adv_smbus_read_byte_data(state, ADV7604_PAGE_INFOFRAME, reg); 47554450f59SHans Verkuil } 47654450f59SHans Verkuil 47754450f59SHans Verkuil static inline int infoframe_write(struct v4l2_subdev *sd, u8 reg, u8 val) 47854450f59SHans Verkuil { 47954450f59SHans Verkuil struct adv7604_state *state = to_state(sd); 48054450f59SHans Verkuil 48105cacb17SLaurent Pinchart return adv_smbus_write_byte_data(state, ADV7604_PAGE_INFOFRAME, 48205cacb17SLaurent Pinchart reg, val); 48354450f59SHans Verkuil } 48454450f59SHans Verkuil 48554450f59SHans Verkuil static inline int esdp_read(struct v4l2_subdev *sd, u8 reg) 48654450f59SHans Verkuil { 48754450f59SHans Verkuil struct adv7604_state *state = to_state(sd); 48854450f59SHans Verkuil 48905cacb17SLaurent Pinchart return adv_smbus_read_byte_data(state, ADV7604_PAGE_ESDP, reg); 49054450f59SHans Verkuil } 49154450f59SHans Verkuil 49254450f59SHans Verkuil static inline int esdp_write(struct v4l2_subdev *sd, u8 reg, u8 val) 49354450f59SHans Verkuil { 49454450f59SHans Verkuil struct adv7604_state *state = to_state(sd); 49554450f59SHans Verkuil 49605cacb17SLaurent Pinchart return adv_smbus_write_byte_data(state, ADV7604_PAGE_ESDP, reg, val); 49754450f59SHans Verkuil } 49854450f59SHans Verkuil 49954450f59SHans Verkuil static inline int dpp_read(struct v4l2_subdev *sd, u8 reg) 50054450f59SHans Verkuil { 50154450f59SHans Verkuil struct adv7604_state *state = to_state(sd); 50254450f59SHans Verkuil 50305cacb17SLaurent Pinchart return adv_smbus_read_byte_data(state, ADV7604_PAGE_DPP, reg); 50454450f59SHans Verkuil } 50554450f59SHans Verkuil 50654450f59SHans Verkuil static inline int dpp_write(struct v4l2_subdev *sd, u8 reg, u8 val) 50754450f59SHans Verkuil { 50854450f59SHans Verkuil struct adv7604_state *state = to_state(sd); 50954450f59SHans Verkuil 51005cacb17SLaurent Pinchart return adv_smbus_write_byte_data(state, ADV7604_PAGE_DPP, reg, val); 51154450f59SHans Verkuil } 51254450f59SHans Verkuil 51354450f59SHans Verkuil static inline int afe_read(struct v4l2_subdev *sd, u8 reg) 51454450f59SHans Verkuil { 51554450f59SHans Verkuil struct adv7604_state *state = to_state(sd); 51654450f59SHans Verkuil 51705cacb17SLaurent Pinchart return adv_smbus_read_byte_data(state, ADV7604_PAGE_AFE, reg); 51854450f59SHans Verkuil } 51954450f59SHans Verkuil 52054450f59SHans Verkuil static inline int afe_write(struct v4l2_subdev *sd, u8 reg, u8 val) 52154450f59SHans Verkuil { 52254450f59SHans Verkuil struct adv7604_state *state = to_state(sd); 52354450f59SHans Verkuil 52405cacb17SLaurent Pinchart return adv_smbus_write_byte_data(state, ADV7604_PAGE_AFE, reg, val); 52554450f59SHans Verkuil } 52654450f59SHans Verkuil 52754450f59SHans Verkuil static inline int rep_read(struct v4l2_subdev *sd, u8 reg) 52854450f59SHans Verkuil { 52954450f59SHans Verkuil struct adv7604_state *state = to_state(sd); 53054450f59SHans Verkuil 53105cacb17SLaurent Pinchart return adv_smbus_read_byte_data(state, ADV7604_PAGE_REP, reg); 53254450f59SHans Verkuil } 53354450f59SHans Verkuil 53454450f59SHans Verkuil static inline int rep_write(struct v4l2_subdev *sd, u8 reg, u8 val) 53554450f59SHans Verkuil { 53654450f59SHans Verkuil struct adv7604_state *state = to_state(sd); 53754450f59SHans Verkuil 53805cacb17SLaurent Pinchart return adv_smbus_write_byte_data(state, ADV7604_PAGE_REP, reg, val); 53954450f59SHans Verkuil } 54054450f59SHans Verkuil 54122d97e56SLaurent Pinchart static inline int rep_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) 54254450f59SHans Verkuil { 54322d97e56SLaurent Pinchart return rep_write(sd, reg, (rep_read(sd, reg) & ~mask) | val); 54454450f59SHans Verkuil } 54554450f59SHans Verkuil 54654450f59SHans Verkuil static inline int edid_read(struct v4l2_subdev *sd, u8 reg) 54754450f59SHans Verkuil { 54854450f59SHans Verkuil struct adv7604_state *state = to_state(sd); 54954450f59SHans Verkuil 55005cacb17SLaurent Pinchart return adv_smbus_read_byte_data(state, ADV7604_PAGE_EDID, reg); 55154450f59SHans Verkuil } 55254450f59SHans Verkuil 55354450f59SHans Verkuil static inline int edid_write(struct v4l2_subdev *sd, u8 reg, u8 val) 55454450f59SHans Verkuil { 55554450f59SHans Verkuil struct adv7604_state *state = to_state(sd); 55654450f59SHans Verkuil 55705cacb17SLaurent Pinchart return adv_smbus_write_byte_data(state, ADV7604_PAGE_EDID, reg, val); 55854450f59SHans Verkuil } 55954450f59SHans Verkuil 56054450f59SHans Verkuil static inline int edid_read_block(struct v4l2_subdev *sd, unsigned len, u8 *val) 56154450f59SHans Verkuil { 56254450f59SHans Verkuil struct adv7604_state *state = to_state(sd); 56305cacb17SLaurent Pinchart struct i2c_client *client = state->i2c_clients[ADV7604_PAGE_EDID]; 56454450f59SHans Verkuil u8 msgbuf0[1] = { 0 }; 56554450f59SHans Verkuil u8 msgbuf1[256]; 56609f29673SShubhrajyoti D struct i2c_msg msg[2] = { 56709f29673SShubhrajyoti D { 56809f29673SShubhrajyoti D .addr = client->addr, 56909f29673SShubhrajyoti D .len = 1, 57009f29673SShubhrajyoti D .buf = msgbuf0 57109f29673SShubhrajyoti D }, 57209f29673SShubhrajyoti D { 57309f29673SShubhrajyoti D .addr = client->addr, 57409f29673SShubhrajyoti D .flags = I2C_M_RD, 57509f29673SShubhrajyoti D .len = len, 57609f29673SShubhrajyoti D .buf = msgbuf1 57709f29673SShubhrajyoti D }, 57854450f59SHans Verkuil }; 57954450f59SHans Verkuil 58054450f59SHans Verkuil if (i2c_transfer(client->adapter, msg, 2) < 0) 58154450f59SHans Verkuil return -EIO; 58254450f59SHans Verkuil memcpy(val, msgbuf1, len); 58354450f59SHans Verkuil return 0; 58454450f59SHans Verkuil } 58554450f59SHans Verkuil 586dd08beb9SMats Randgaard static inline int edid_write_block(struct v4l2_subdev *sd, 587dd08beb9SMats Randgaard unsigned len, const u8 *val) 588dd08beb9SMats Randgaard { 589dd08beb9SMats Randgaard struct adv7604_state *state = to_state(sd); 590dd08beb9SMats Randgaard int err = 0; 591dd08beb9SMats Randgaard int i; 592dd08beb9SMats Randgaard 593dd08beb9SMats Randgaard v4l2_dbg(2, debug, sd, "%s: write EDID block (%d byte)\n", __func__, len); 594dd08beb9SMats Randgaard 595dd08beb9SMats Randgaard for (i = 0; !err && i < len; i += I2C_SMBUS_BLOCK_MAX) 59605cacb17SLaurent Pinchart err = adv_smbus_write_i2c_block_data(state, ADV7604_PAGE_EDID, 59705cacb17SLaurent Pinchart i, I2C_SMBUS_BLOCK_MAX, val + i); 598dd08beb9SMats Randgaard return err; 599dd08beb9SMats Randgaard } 600dd08beb9SMats Randgaard 60154450f59SHans Verkuil static void adv7604_delayed_work_enable_hotplug(struct work_struct *work) 60254450f59SHans Verkuil { 60354450f59SHans Verkuil struct delayed_work *dwork = to_delayed_work(work); 60454450f59SHans Verkuil struct adv7604_state *state = container_of(dwork, struct adv7604_state, 60554450f59SHans Verkuil delayed_work_enable_hotplug); 60654450f59SHans Verkuil struct v4l2_subdev *sd = &state->sd; 60754450f59SHans Verkuil 60854450f59SHans Verkuil v4l2_dbg(2, debug, sd, "%s: enable hotplug\n", __func__); 60954450f59SHans Verkuil 6104a31a93aSMats Randgaard v4l2_subdev_notify(sd, ADV7604_HOTPLUG, (void *)&state->edid.present); 61154450f59SHans Verkuil } 61254450f59SHans Verkuil 61354450f59SHans Verkuil static inline int hdmi_read(struct v4l2_subdev *sd, u8 reg) 61454450f59SHans Verkuil { 61554450f59SHans Verkuil struct adv7604_state *state = to_state(sd); 61654450f59SHans Verkuil 61705cacb17SLaurent Pinchart return adv_smbus_read_byte_data(state, ADV7604_PAGE_HDMI, reg); 61854450f59SHans Verkuil } 61954450f59SHans Verkuil 62051182a94SLaurent Pinchart static u16 hdmi_read16(struct v4l2_subdev *sd, u8 reg, u16 mask) 62151182a94SLaurent Pinchart { 62251182a94SLaurent Pinchart return ((hdmi_read(sd, reg) << 8) | hdmi_read(sd, reg + 1)) & mask; 62351182a94SLaurent Pinchart } 62451182a94SLaurent Pinchart 62554450f59SHans Verkuil static inline int hdmi_write(struct v4l2_subdev *sd, u8 reg, u8 val) 62654450f59SHans Verkuil { 62754450f59SHans Verkuil struct adv7604_state *state = to_state(sd); 62854450f59SHans Verkuil 62905cacb17SLaurent Pinchart return adv_smbus_write_byte_data(state, ADV7604_PAGE_HDMI, reg, val); 63054450f59SHans Verkuil } 63154450f59SHans Verkuil 63222d97e56SLaurent Pinchart static inline int hdmi_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) 6334a31a93aSMats Randgaard { 63422d97e56SLaurent Pinchart return hdmi_write(sd, reg, (hdmi_read(sd, reg) & ~mask) | val); 6354a31a93aSMats Randgaard } 6364a31a93aSMats Randgaard 63754450f59SHans Verkuil static inline int test_read(struct v4l2_subdev *sd, u8 reg) 63854450f59SHans Verkuil { 63954450f59SHans Verkuil struct adv7604_state *state = to_state(sd); 64054450f59SHans Verkuil 64105cacb17SLaurent Pinchart return adv_smbus_read_byte_data(state, ADV7604_PAGE_TEST, reg); 64254450f59SHans Verkuil } 64354450f59SHans Verkuil 64454450f59SHans Verkuil static inline int test_write(struct v4l2_subdev *sd, u8 reg, u8 val) 64554450f59SHans Verkuil { 64654450f59SHans Verkuil struct adv7604_state *state = to_state(sd); 64754450f59SHans Verkuil 64805cacb17SLaurent Pinchart return adv_smbus_write_byte_data(state, ADV7604_PAGE_TEST, reg, val); 64954450f59SHans Verkuil } 65054450f59SHans Verkuil 65154450f59SHans Verkuil static inline int cp_read(struct v4l2_subdev *sd, u8 reg) 65254450f59SHans Verkuil { 65354450f59SHans Verkuil struct adv7604_state *state = to_state(sd); 65454450f59SHans Verkuil 65505cacb17SLaurent Pinchart return adv_smbus_read_byte_data(state, ADV7604_PAGE_CP, reg); 65654450f59SHans Verkuil } 65754450f59SHans Verkuil 65851182a94SLaurent Pinchart static u16 cp_read16(struct v4l2_subdev *sd, u8 reg, u16 mask) 65951182a94SLaurent Pinchart { 66051182a94SLaurent Pinchart return ((cp_read(sd, reg) << 8) | cp_read(sd, reg + 1)) & mask; 66151182a94SLaurent Pinchart } 66251182a94SLaurent Pinchart 66354450f59SHans Verkuil static inline int cp_write(struct v4l2_subdev *sd, u8 reg, u8 val) 66454450f59SHans Verkuil { 66554450f59SHans Verkuil struct adv7604_state *state = to_state(sd); 66654450f59SHans Verkuil 66705cacb17SLaurent Pinchart return adv_smbus_write_byte_data(state, ADV7604_PAGE_CP, reg, val); 66854450f59SHans Verkuil } 66954450f59SHans Verkuil 67022d97e56SLaurent Pinchart static inline int cp_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) 67154450f59SHans Verkuil { 67222d97e56SLaurent Pinchart return cp_write(sd, reg, (cp_read(sd, reg) & ~mask) | val); 67354450f59SHans Verkuil } 67454450f59SHans Verkuil 67554450f59SHans Verkuil static inline int vdp_read(struct v4l2_subdev *sd, u8 reg) 67654450f59SHans Verkuil { 67754450f59SHans Verkuil struct adv7604_state *state = to_state(sd); 67854450f59SHans Verkuil 67905cacb17SLaurent Pinchart return adv_smbus_read_byte_data(state, ADV7604_PAGE_VDP, reg); 68054450f59SHans Verkuil } 68154450f59SHans Verkuil 68254450f59SHans Verkuil static inline int vdp_write(struct v4l2_subdev *sd, u8 reg, u8 val) 68354450f59SHans Verkuil { 68454450f59SHans Verkuil struct adv7604_state *state = to_state(sd); 68554450f59SHans Verkuil 68605cacb17SLaurent Pinchart return adv_smbus_write_byte_data(state, ADV7604_PAGE_VDP, reg, val); 68754450f59SHans Verkuil } 68854450f59SHans Verkuil 689d42010a1SLars-Peter Clausen #define ADV7604_REG(page, offset) (((page) << 8) | (offset)) 690d42010a1SLars-Peter Clausen #define ADV7604_REG_SEQ_TERM 0xffff 691d42010a1SLars-Peter Clausen 692d42010a1SLars-Peter Clausen #ifdef CONFIG_VIDEO_ADV_DEBUG 693d42010a1SLars-Peter Clausen static int adv7604_read_reg(struct v4l2_subdev *sd, unsigned int reg) 694d42010a1SLars-Peter Clausen { 695d42010a1SLars-Peter Clausen struct adv7604_state *state = to_state(sd); 696d42010a1SLars-Peter Clausen unsigned int page = reg >> 8; 697d42010a1SLars-Peter Clausen 698d42010a1SLars-Peter Clausen if (!(BIT(page) & state->info->page_mask)) 699d42010a1SLars-Peter Clausen return -EINVAL; 700d42010a1SLars-Peter Clausen 701d42010a1SLars-Peter Clausen reg &= 0xff; 702d42010a1SLars-Peter Clausen 70305cacb17SLaurent Pinchart return adv_smbus_read_byte_data(state, page, reg); 704d42010a1SLars-Peter Clausen } 705d42010a1SLars-Peter Clausen #endif 706d42010a1SLars-Peter Clausen 707d42010a1SLars-Peter Clausen static int adv7604_write_reg(struct v4l2_subdev *sd, unsigned int reg, u8 val) 708d42010a1SLars-Peter Clausen { 709d42010a1SLars-Peter Clausen struct adv7604_state *state = to_state(sd); 710d42010a1SLars-Peter Clausen unsigned int page = reg >> 8; 711d42010a1SLars-Peter Clausen 712d42010a1SLars-Peter Clausen if (!(BIT(page) & state->info->page_mask)) 713d42010a1SLars-Peter Clausen return -EINVAL; 714d42010a1SLars-Peter Clausen 715d42010a1SLars-Peter Clausen reg &= 0xff; 716d42010a1SLars-Peter Clausen 71705cacb17SLaurent Pinchart return adv_smbus_write_byte_data(state, page, reg, val); 718d42010a1SLars-Peter Clausen } 719d42010a1SLars-Peter Clausen 720d42010a1SLars-Peter Clausen static void adv7604_write_reg_seq(struct v4l2_subdev *sd, 721d42010a1SLars-Peter Clausen const struct adv7604_reg_seq *reg_seq) 722d42010a1SLars-Peter Clausen { 723d42010a1SLars-Peter Clausen unsigned int i; 724d42010a1SLars-Peter Clausen 725d42010a1SLars-Peter Clausen for (i = 0; reg_seq[i].reg != ADV7604_REG_SEQ_TERM; i++) 726d42010a1SLars-Peter Clausen adv7604_write_reg(sd, reg_seq[i].reg, reg_seq[i].val); 727d42010a1SLars-Peter Clausen } 728d42010a1SLars-Peter Clausen 729539b33b0SLaurent Pinchart /* ----------------------------------------------------------------------------- 730539b33b0SLaurent Pinchart * Format helpers 731539b33b0SLaurent Pinchart */ 732539b33b0SLaurent Pinchart 733539b33b0SLaurent Pinchart static const struct adv7604_format_info adv7604_formats[] = { 734539b33b0SLaurent Pinchart { V4L2_MBUS_FMT_RGB888_1X24, ADV7604_OP_CH_SEL_RGB, true, false, 735539b33b0SLaurent Pinchart ADV7604_OP_MODE_SEL_SDR_444 | ADV7604_OP_FORMAT_SEL_8BIT }, 736539b33b0SLaurent Pinchart { V4L2_MBUS_FMT_YUYV8_2X8, ADV7604_OP_CH_SEL_RGB, false, false, 737539b33b0SLaurent Pinchart ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_8BIT }, 738539b33b0SLaurent Pinchart { V4L2_MBUS_FMT_YVYU8_2X8, ADV7604_OP_CH_SEL_RGB, false, true, 739539b33b0SLaurent Pinchart ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_8BIT }, 740539b33b0SLaurent Pinchart { V4L2_MBUS_FMT_YUYV10_2X10, ADV7604_OP_CH_SEL_RGB, false, false, 741539b33b0SLaurent Pinchart ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_10BIT }, 742539b33b0SLaurent Pinchart { V4L2_MBUS_FMT_YVYU10_2X10, ADV7604_OP_CH_SEL_RGB, false, true, 743539b33b0SLaurent Pinchart ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_10BIT }, 744539b33b0SLaurent Pinchart { V4L2_MBUS_FMT_YUYV12_2X12, ADV7604_OP_CH_SEL_RGB, false, false, 745539b33b0SLaurent Pinchart ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_12BIT }, 746539b33b0SLaurent Pinchart { V4L2_MBUS_FMT_YVYU12_2X12, ADV7604_OP_CH_SEL_RGB, false, true, 747539b33b0SLaurent Pinchart ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_12BIT }, 748539b33b0SLaurent Pinchart { V4L2_MBUS_FMT_UYVY8_1X16, ADV7604_OP_CH_SEL_RBG, false, false, 749539b33b0SLaurent Pinchart ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_8BIT }, 750539b33b0SLaurent Pinchart { V4L2_MBUS_FMT_VYUY8_1X16, ADV7604_OP_CH_SEL_RBG, false, true, 751539b33b0SLaurent Pinchart ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_8BIT }, 752539b33b0SLaurent Pinchart { V4L2_MBUS_FMT_YUYV8_1X16, ADV7604_OP_CH_SEL_RGB, false, false, 753539b33b0SLaurent Pinchart ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_8BIT }, 754539b33b0SLaurent Pinchart { V4L2_MBUS_FMT_YVYU8_1X16, ADV7604_OP_CH_SEL_RGB, false, true, 755539b33b0SLaurent Pinchart ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_8BIT }, 756539b33b0SLaurent Pinchart { V4L2_MBUS_FMT_UYVY10_1X20, ADV7604_OP_CH_SEL_RBG, false, false, 757539b33b0SLaurent Pinchart ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT }, 758539b33b0SLaurent Pinchart { V4L2_MBUS_FMT_VYUY10_1X20, ADV7604_OP_CH_SEL_RBG, false, true, 759539b33b0SLaurent Pinchart ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT }, 760539b33b0SLaurent Pinchart { V4L2_MBUS_FMT_YUYV10_1X20, ADV7604_OP_CH_SEL_RGB, false, false, 761539b33b0SLaurent Pinchart ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT }, 762539b33b0SLaurent Pinchart { V4L2_MBUS_FMT_YVYU10_1X20, ADV7604_OP_CH_SEL_RGB, false, true, 763539b33b0SLaurent Pinchart ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT }, 764539b33b0SLaurent Pinchart { V4L2_MBUS_FMT_UYVY12_1X24, ADV7604_OP_CH_SEL_RBG, false, false, 765539b33b0SLaurent Pinchart ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_12BIT }, 766539b33b0SLaurent Pinchart { V4L2_MBUS_FMT_VYUY12_1X24, ADV7604_OP_CH_SEL_RBG, false, true, 767539b33b0SLaurent Pinchart ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_12BIT }, 768539b33b0SLaurent Pinchart { V4L2_MBUS_FMT_YUYV12_1X24, ADV7604_OP_CH_SEL_RGB, false, false, 769539b33b0SLaurent Pinchart ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_12BIT }, 770539b33b0SLaurent Pinchart { V4L2_MBUS_FMT_YVYU12_1X24, ADV7604_OP_CH_SEL_RGB, false, true, 771539b33b0SLaurent Pinchart ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_12BIT }, 772539b33b0SLaurent Pinchart }; 773539b33b0SLaurent Pinchart 774539b33b0SLaurent Pinchart static const struct adv7604_format_info adv7611_formats[] = { 775539b33b0SLaurent Pinchart { V4L2_MBUS_FMT_RGB888_1X24, ADV7604_OP_CH_SEL_RGB, true, false, 776539b33b0SLaurent Pinchart ADV7604_OP_MODE_SEL_SDR_444 | ADV7604_OP_FORMAT_SEL_8BIT }, 777539b33b0SLaurent Pinchart { V4L2_MBUS_FMT_YUYV8_2X8, ADV7604_OP_CH_SEL_RGB, false, false, 778539b33b0SLaurent Pinchart ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_8BIT }, 779539b33b0SLaurent Pinchart { V4L2_MBUS_FMT_YVYU8_2X8, ADV7604_OP_CH_SEL_RGB, false, true, 780539b33b0SLaurent Pinchart ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_8BIT }, 781539b33b0SLaurent Pinchart { V4L2_MBUS_FMT_YUYV12_2X12, ADV7604_OP_CH_SEL_RGB, false, false, 782539b33b0SLaurent Pinchart ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_12BIT }, 783539b33b0SLaurent Pinchart { V4L2_MBUS_FMT_YVYU12_2X12, ADV7604_OP_CH_SEL_RGB, false, true, 784539b33b0SLaurent Pinchart ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_12BIT }, 785539b33b0SLaurent Pinchart { V4L2_MBUS_FMT_UYVY8_1X16, ADV7604_OP_CH_SEL_RBG, false, false, 786539b33b0SLaurent Pinchart ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_8BIT }, 787539b33b0SLaurent Pinchart { V4L2_MBUS_FMT_VYUY8_1X16, ADV7604_OP_CH_SEL_RBG, false, true, 788539b33b0SLaurent Pinchart ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_8BIT }, 789539b33b0SLaurent Pinchart { V4L2_MBUS_FMT_YUYV8_1X16, ADV7604_OP_CH_SEL_RGB, false, false, 790539b33b0SLaurent Pinchart ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_8BIT }, 791539b33b0SLaurent Pinchart { V4L2_MBUS_FMT_YVYU8_1X16, ADV7604_OP_CH_SEL_RGB, false, true, 792539b33b0SLaurent Pinchart ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_8BIT }, 793539b33b0SLaurent Pinchart { V4L2_MBUS_FMT_UYVY12_1X24, ADV7604_OP_CH_SEL_RBG, false, false, 794539b33b0SLaurent Pinchart ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_12BIT }, 795539b33b0SLaurent Pinchart { V4L2_MBUS_FMT_VYUY12_1X24, ADV7604_OP_CH_SEL_RBG, false, true, 796539b33b0SLaurent Pinchart ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_12BIT }, 797539b33b0SLaurent Pinchart { V4L2_MBUS_FMT_YUYV12_1X24, ADV7604_OP_CH_SEL_RGB, false, false, 798539b33b0SLaurent Pinchart ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_12BIT }, 799539b33b0SLaurent Pinchart { V4L2_MBUS_FMT_YVYU12_1X24, ADV7604_OP_CH_SEL_RGB, false, true, 800539b33b0SLaurent Pinchart ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_12BIT }, 801539b33b0SLaurent Pinchart }; 802539b33b0SLaurent Pinchart 803539b33b0SLaurent Pinchart static const struct adv7604_format_info * 804539b33b0SLaurent Pinchart adv7604_format_info(struct adv7604_state *state, enum v4l2_mbus_pixelcode code) 805539b33b0SLaurent Pinchart { 806539b33b0SLaurent Pinchart unsigned int i; 807539b33b0SLaurent Pinchart 808539b33b0SLaurent Pinchart for (i = 0; i < state->info->nformats; ++i) { 809539b33b0SLaurent Pinchart if (state->info->formats[i].code == code) 810539b33b0SLaurent Pinchart return &state->info->formats[i]; 811539b33b0SLaurent Pinchart } 812539b33b0SLaurent Pinchart 813539b33b0SLaurent Pinchart return NULL; 814539b33b0SLaurent Pinchart } 815539b33b0SLaurent Pinchart 81654450f59SHans Verkuil /* ----------------------------------------------------------------------- */ 81754450f59SHans Verkuil 8184a31a93aSMats Randgaard static inline bool is_analog_input(struct v4l2_subdev *sd) 8194a31a93aSMats Randgaard { 8204a31a93aSMats Randgaard struct adv7604_state *state = to_state(sd); 8214a31a93aSMats Randgaard 822c784b1e2SLaurent Pinchart return state->selected_input == ADV7604_PAD_VGA_RGB || 823c784b1e2SLaurent Pinchart state->selected_input == ADV7604_PAD_VGA_COMP; 8244a31a93aSMats Randgaard } 8254a31a93aSMats Randgaard 8264a31a93aSMats Randgaard static inline bool is_digital_input(struct v4l2_subdev *sd) 8274a31a93aSMats Randgaard { 8284a31a93aSMats Randgaard struct adv7604_state *state = to_state(sd); 8294a31a93aSMats Randgaard 830c784b1e2SLaurent Pinchart return state->selected_input == ADV7604_PAD_HDMI_PORT_A || 831c784b1e2SLaurent Pinchart state->selected_input == ADV7604_PAD_HDMI_PORT_B || 832c784b1e2SLaurent Pinchart state->selected_input == ADV7604_PAD_HDMI_PORT_C || 833c784b1e2SLaurent Pinchart state->selected_input == ADV7604_PAD_HDMI_PORT_D; 8344a31a93aSMats Randgaard } 8354a31a93aSMats Randgaard 8364a31a93aSMats Randgaard /* ----------------------------------------------------------------------- */ 8374a31a93aSMats Randgaard 83854450f59SHans Verkuil #ifdef CONFIG_VIDEO_ADV_DEBUG 83954450f59SHans Verkuil static void adv7604_inv_register(struct v4l2_subdev *sd) 84054450f59SHans Verkuil { 84154450f59SHans Verkuil v4l2_info(sd, "0x000-0x0ff: IO Map\n"); 84254450f59SHans Verkuil v4l2_info(sd, "0x100-0x1ff: AVLink Map\n"); 84354450f59SHans Verkuil v4l2_info(sd, "0x200-0x2ff: CEC Map\n"); 84454450f59SHans Verkuil v4l2_info(sd, "0x300-0x3ff: InfoFrame Map\n"); 84554450f59SHans Verkuil v4l2_info(sd, "0x400-0x4ff: ESDP Map\n"); 84654450f59SHans Verkuil v4l2_info(sd, "0x500-0x5ff: DPP Map\n"); 84754450f59SHans Verkuil v4l2_info(sd, "0x600-0x6ff: AFE Map\n"); 84854450f59SHans Verkuil v4l2_info(sd, "0x700-0x7ff: Repeater Map\n"); 84954450f59SHans Verkuil v4l2_info(sd, "0x800-0x8ff: EDID Map\n"); 85054450f59SHans Verkuil v4l2_info(sd, "0x900-0x9ff: HDMI Map\n"); 85154450f59SHans Verkuil v4l2_info(sd, "0xa00-0xaff: Test Map\n"); 85254450f59SHans Verkuil v4l2_info(sd, "0xb00-0xbff: CP Map\n"); 85354450f59SHans Verkuil v4l2_info(sd, "0xc00-0xcff: VDP Map\n"); 85454450f59SHans Verkuil } 85554450f59SHans Verkuil 85654450f59SHans Verkuil static int adv7604_g_register(struct v4l2_subdev *sd, 85754450f59SHans Verkuil struct v4l2_dbg_register *reg) 85854450f59SHans Verkuil { 859d42010a1SLars-Peter Clausen int ret; 860d42010a1SLars-Peter Clausen 861d42010a1SLars-Peter Clausen ret = adv7604_read_reg(sd, reg->reg); 862d42010a1SLars-Peter Clausen if (ret < 0) { 86354450f59SHans Verkuil v4l2_info(sd, "Register %03llx not supported\n", reg->reg); 86454450f59SHans Verkuil adv7604_inv_register(sd); 865d42010a1SLars-Peter Clausen return ret; 86654450f59SHans Verkuil } 867d42010a1SLars-Peter Clausen 868d42010a1SLars-Peter Clausen reg->size = 1; 869d42010a1SLars-Peter Clausen reg->val = ret; 870d42010a1SLars-Peter Clausen 87154450f59SHans Verkuil return 0; 87254450f59SHans Verkuil } 87354450f59SHans Verkuil 87454450f59SHans Verkuil static int adv7604_s_register(struct v4l2_subdev *sd, 875977ba3b1SHans Verkuil const struct v4l2_dbg_register *reg) 87654450f59SHans Verkuil { 877d42010a1SLars-Peter Clausen int ret; 8781577461bSHans Verkuil 879d42010a1SLars-Peter Clausen ret = adv7604_write_reg(sd, reg->reg, reg->val); 880d42010a1SLars-Peter Clausen if (ret < 0) { 88154450f59SHans Verkuil v4l2_info(sd, "Register %03llx not supported\n", reg->reg); 88254450f59SHans Verkuil adv7604_inv_register(sd); 883d42010a1SLars-Peter Clausen return ret; 88454450f59SHans Verkuil } 885d42010a1SLars-Peter Clausen 88654450f59SHans Verkuil return 0; 88754450f59SHans Verkuil } 88854450f59SHans Verkuil #endif 88954450f59SHans Verkuil 890d42010a1SLars-Peter Clausen static unsigned int adv7604_read_cable_det(struct v4l2_subdev *sd) 891d42010a1SLars-Peter Clausen { 892d42010a1SLars-Peter Clausen u8 value = io_read(sd, 0x6f); 893d42010a1SLars-Peter Clausen 894d42010a1SLars-Peter Clausen return ((value & 0x10) >> 4) 895d42010a1SLars-Peter Clausen | ((value & 0x08) >> 2) 896d42010a1SLars-Peter Clausen | ((value & 0x04) << 0) 897d42010a1SLars-Peter Clausen | ((value & 0x02) << 2); 898d42010a1SLars-Peter Clausen } 899d42010a1SLars-Peter Clausen 900d42010a1SLars-Peter Clausen static unsigned int adv7611_read_cable_det(struct v4l2_subdev *sd) 901d42010a1SLars-Peter Clausen { 902d42010a1SLars-Peter Clausen u8 value = io_read(sd, 0x6f); 903d42010a1SLars-Peter Clausen 904d42010a1SLars-Peter Clausen return value & 1; 905d42010a1SLars-Peter Clausen } 906d42010a1SLars-Peter Clausen 90754450f59SHans Verkuil static int adv7604_s_detect_tx_5v_ctrl(struct v4l2_subdev *sd) 90854450f59SHans Verkuil { 90954450f59SHans Verkuil struct adv7604_state *state = to_state(sd); 910d42010a1SLars-Peter Clausen const struct adv7604_chip_info *info = state->info; 91154450f59SHans Verkuil 91254450f59SHans Verkuil return v4l2_ctrl_s_ctrl(state->detect_tx_5v_ctrl, 913d42010a1SLars-Peter Clausen info->read_cable_det(sd)); 91454450f59SHans Verkuil } 91554450f59SHans Verkuil 916ccbd5bc4SHans Verkuil static int find_and_set_predefined_video_timings(struct v4l2_subdev *sd, 917ccbd5bc4SHans Verkuil u8 prim_mode, 918ccbd5bc4SHans Verkuil const struct adv7604_video_standards *predef_vid_timings, 919ccbd5bc4SHans Verkuil const struct v4l2_dv_timings *timings) 92054450f59SHans Verkuil { 921ccbd5bc4SHans Verkuil int i; 92254450f59SHans Verkuil 923ccbd5bc4SHans Verkuil for (i = 0; predef_vid_timings[i].timings.bt.width; i++) { 924ef1ed8f5SHans Verkuil if (!v4l2_match_dv_timings(timings, &predef_vid_timings[i].timings, 9254a31a93aSMats Randgaard is_digital_input(sd) ? 250000 : 1000000)) 926ccbd5bc4SHans Verkuil continue; 927ccbd5bc4SHans Verkuil io_write(sd, 0x00, predef_vid_timings[i].vid_std); /* video std */ 928ccbd5bc4SHans Verkuil io_write(sd, 0x01, (predef_vid_timings[i].v_freq << 4) + 929ccbd5bc4SHans Verkuil prim_mode); /* v_freq and prim mode */ 930ccbd5bc4SHans Verkuil return 0; 93154450f59SHans Verkuil } 93254450f59SHans Verkuil 933ccbd5bc4SHans Verkuil return -1; 934ccbd5bc4SHans Verkuil } 93554450f59SHans Verkuil 936ccbd5bc4SHans Verkuil static int configure_predefined_video_timings(struct v4l2_subdev *sd, 937ccbd5bc4SHans Verkuil struct v4l2_dv_timings *timings) 938ccbd5bc4SHans Verkuil { 939ccbd5bc4SHans Verkuil struct adv7604_state *state = to_state(sd); 940ccbd5bc4SHans Verkuil int err; 941ccbd5bc4SHans Verkuil 942ccbd5bc4SHans Verkuil v4l2_dbg(1, debug, sd, "%s", __func__); 943ccbd5bc4SHans Verkuil 944d42010a1SLars-Peter Clausen if (adv7604_has_afe(state)) { 94554450f59SHans Verkuil /* reset to default values */ 94654450f59SHans Verkuil io_write(sd, 0x16, 0x43); 94754450f59SHans Verkuil io_write(sd, 0x17, 0x5a); 948d42010a1SLars-Peter Clausen } 949ccbd5bc4SHans Verkuil /* disable embedded syncs for auto graphics mode */ 95022d97e56SLaurent Pinchart cp_write_clr_set(sd, 0x81, 0x10, 0x00); 951ccbd5bc4SHans Verkuil cp_write(sd, 0x8f, 0x00); 952ccbd5bc4SHans Verkuil cp_write(sd, 0x90, 0x00); 95354450f59SHans Verkuil cp_write(sd, 0xa2, 0x00); 95454450f59SHans Verkuil cp_write(sd, 0xa3, 0x00); 95554450f59SHans Verkuil cp_write(sd, 0xa4, 0x00); 95654450f59SHans Verkuil cp_write(sd, 0xa5, 0x00); 95754450f59SHans Verkuil cp_write(sd, 0xa6, 0x00); 95854450f59SHans Verkuil cp_write(sd, 0xa7, 0x00); 959ccbd5bc4SHans Verkuil cp_write(sd, 0xab, 0x00); 960ccbd5bc4SHans Verkuil cp_write(sd, 0xac, 0x00); 961ccbd5bc4SHans Verkuil 9624a31a93aSMats Randgaard if (is_analog_input(sd)) { 963ccbd5bc4SHans Verkuil err = find_and_set_predefined_video_timings(sd, 964ccbd5bc4SHans Verkuil 0x01, adv7604_prim_mode_comp, timings); 965ccbd5bc4SHans Verkuil if (err) 966ccbd5bc4SHans Verkuil err = find_and_set_predefined_video_timings(sd, 967ccbd5bc4SHans Verkuil 0x02, adv7604_prim_mode_gr, timings); 9684a31a93aSMats Randgaard } else if (is_digital_input(sd)) { 969ccbd5bc4SHans Verkuil err = find_and_set_predefined_video_timings(sd, 970ccbd5bc4SHans Verkuil 0x05, adv7604_prim_mode_hdmi_comp, timings); 971ccbd5bc4SHans Verkuil if (err) 972ccbd5bc4SHans Verkuil err = find_and_set_predefined_video_timings(sd, 973ccbd5bc4SHans Verkuil 0x06, adv7604_prim_mode_hdmi_gr, timings); 9744a31a93aSMats Randgaard } else { 9754a31a93aSMats Randgaard v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n", 9764a31a93aSMats Randgaard __func__, state->selected_input); 977ccbd5bc4SHans Verkuil err = -1; 97854450f59SHans Verkuil } 97954450f59SHans Verkuil 98054450f59SHans Verkuil 981ccbd5bc4SHans Verkuil return err; 982ccbd5bc4SHans Verkuil } 983ccbd5bc4SHans Verkuil 984ccbd5bc4SHans Verkuil static void configure_custom_video_timings(struct v4l2_subdev *sd, 985ccbd5bc4SHans Verkuil const struct v4l2_bt_timings *bt) 986ccbd5bc4SHans Verkuil { 987ccbd5bc4SHans Verkuil struct adv7604_state *state = to_state(sd); 988ccbd5bc4SHans Verkuil u32 width = htotal(bt); 989ccbd5bc4SHans Verkuil u32 height = vtotal(bt); 990ccbd5bc4SHans Verkuil u16 cp_start_sav = bt->hsync + bt->hbackporch - 4; 991ccbd5bc4SHans Verkuil u16 cp_start_eav = width - bt->hfrontporch; 992ccbd5bc4SHans Verkuil u16 cp_start_vbi = height - bt->vfrontporch; 993ccbd5bc4SHans Verkuil u16 cp_end_vbi = bt->vsync + bt->vbackporch; 994ccbd5bc4SHans Verkuil u16 ch1_fr_ll = (((u32)bt->pixelclock / 100) > 0) ? 995ccbd5bc4SHans Verkuil ((width * (ADV7604_fsc / 100)) / ((u32)bt->pixelclock / 100)) : 0; 996ccbd5bc4SHans Verkuil const u8 pll[2] = { 997ccbd5bc4SHans Verkuil 0xc0 | ((width >> 8) & 0x1f), 998ccbd5bc4SHans Verkuil width & 0xff 999ccbd5bc4SHans Verkuil }; 1000ccbd5bc4SHans Verkuil 1001ccbd5bc4SHans Verkuil v4l2_dbg(2, debug, sd, "%s\n", __func__); 1002ccbd5bc4SHans Verkuil 10034a31a93aSMats Randgaard if (is_analog_input(sd)) { 1004ccbd5bc4SHans Verkuil /* auto graphics */ 1005ccbd5bc4SHans Verkuil io_write(sd, 0x00, 0x07); /* video std */ 1006ccbd5bc4SHans Verkuil io_write(sd, 0x01, 0x02); /* prim mode */ 1007ccbd5bc4SHans Verkuil /* enable embedded syncs for auto graphics mode */ 100822d97e56SLaurent Pinchart cp_write_clr_set(sd, 0x81, 0x10, 0x10); 1009ccbd5bc4SHans Verkuil 1010ccbd5bc4SHans Verkuil /* Should only be set in auto-graphics mode [REF_02, p. 91-92] */ 1011ccbd5bc4SHans Verkuil /* setup PLL_DIV_MAN_EN and PLL_DIV_RATIO */ 1012ccbd5bc4SHans Verkuil /* IO-map reg. 0x16 and 0x17 should be written in sequence */ 101305cacb17SLaurent Pinchart if (adv_smbus_write_i2c_block_data(state, ADV7604_PAGE_IO, 101405cacb17SLaurent Pinchart 0x16, 2, pll)) 1015ccbd5bc4SHans Verkuil v4l2_err(sd, "writing to reg 0x16 and 0x17 failed\n"); 1016ccbd5bc4SHans Verkuil 1017ccbd5bc4SHans Verkuil /* active video - horizontal timing */ 1018ccbd5bc4SHans Verkuil cp_write(sd, 0xa2, (cp_start_sav >> 4) & 0xff); 1019ccbd5bc4SHans Verkuil cp_write(sd, 0xa3, ((cp_start_sav & 0x0f) << 4) | 1020ccbd5bc4SHans Verkuil ((cp_start_eav >> 8) & 0x0f)); 1021ccbd5bc4SHans Verkuil cp_write(sd, 0xa4, cp_start_eav & 0xff); 1022ccbd5bc4SHans Verkuil 1023ccbd5bc4SHans Verkuil /* active video - vertical timing */ 1024ccbd5bc4SHans Verkuil cp_write(sd, 0xa5, (cp_start_vbi >> 4) & 0xff); 1025ccbd5bc4SHans Verkuil cp_write(sd, 0xa6, ((cp_start_vbi & 0xf) << 4) | 1026ccbd5bc4SHans Verkuil ((cp_end_vbi >> 8) & 0xf)); 1027ccbd5bc4SHans Verkuil cp_write(sd, 0xa7, cp_end_vbi & 0xff); 10284a31a93aSMats Randgaard } else if (is_digital_input(sd)) { 1029ccbd5bc4SHans Verkuil /* set default prim_mode/vid_std for HDMI 103039c1cb2bSJonathan McCrohan according to [REF_03, c. 4.2] */ 1031ccbd5bc4SHans Verkuil io_write(sd, 0x00, 0x02); /* video std */ 1032ccbd5bc4SHans Verkuil io_write(sd, 0x01, 0x06); /* prim mode */ 10334a31a93aSMats Randgaard } else { 10344a31a93aSMats Randgaard v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n", 10354a31a93aSMats Randgaard __func__, state->selected_input); 1036ccbd5bc4SHans Verkuil } 1037ccbd5bc4SHans Verkuil 1038ccbd5bc4SHans Verkuil cp_write(sd, 0x8f, (ch1_fr_ll >> 8) & 0x7); 1039ccbd5bc4SHans Verkuil cp_write(sd, 0x90, ch1_fr_ll & 0xff); 1040ccbd5bc4SHans Verkuil cp_write(sd, 0xab, (height >> 4) & 0xff); 1041ccbd5bc4SHans Verkuil cp_write(sd, 0xac, (height & 0x0f) << 4); 1042ccbd5bc4SHans Verkuil } 1043ccbd5bc4SHans Verkuil 10445c6c6349SMats Randgaard static void adv7604_set_offset(struct v4l2_subdev *sd, bool auto_offset, u16 offset_a, u16 offset_b, u16 offset_c) 10455c6c6349SMats Randgaard { 10465c6c6349SMats Randgaard struct adv7604_state *state = to_state(sd); 10475c6c6349SMats Randgaard u8 offset_buf[4]; 10485c6c6349SMats Randgaard 10495c6c6349SMats Randgaard if (auto_offset) { 10505c6c6349SMats Randgaard offset_a = 0x3ff; 10515c6c6349SMats Randgaard offset_b = 0x3ff; 10525c6c6349SMats Randgaard offset_c = 0x3ff; 10535c6c6349SMats Randgaard } 10545c6c6349SMats Randgaard 10555c6c6349SMats Randgaard v4l2_dbg(2, debug, sd, "%s: %s offset: a = 0x%x, b = 0x%x, c = 0x%x\n", 10565c6c6349SMats Randgaard __func__, auto_offset ? "Auto" : "Manual", 10575c6c6349SMats Randgaard offset_a, offset_b, offset_c); 10585c6c6349SMats Randgaard 10595c6c6349SMats Randgaard offset_buf[0] = (cp_read(sd, 0x77) & 0xc0) | ((offset_a & 0x3f0) >> 4); 10605c6c6349SMats Randgaard offset_buf[1] = ((offset_a & 0x00f) << 4) | ((offset_b & 0x3c0) >> 6); 10615c6c6349SMats Randgaard offset_buf[2] = ((offset_b & 0x03f) << 2) | ((offset_c & 0x300) >> 8); 10625c6c6349SMats Randgaard offset_buf[3] = offset_c & 0x0ff; 10635c6c6349SMats Randgaard 10645c6c6349SMats Randgaard /* Registers must be written in this order with no i2c access in between */ 106505cacb17SLaurent Pinchart if (adv_smbus_write_i2c_block_data(state, ADV7604_PAGE_CP, 106605cacb17SLaurent Pinchart 0x77, 4, offset_buf)) 10675c6c6349SMats Randgaard v4l2_err(sd, "%s: i2c error writing to CP reg 0x77, 0x78, 0x79, 0x7a\n", __func__); 10685c6c6349SMats Randgaard } 10695c6c6349SMats Randgaard 10705c6c6349SMats Randgaard static void adv7604_set_gain(struct v4l2_subdev *sd, bool auto_gain, u16 gain_a, u16 gain_b, u16 gain_c) 10715c6c6349SMats Randgaard { 10725c6c6349SMats Randgaard struct adv7604_state *state = to_state(sd); 10735c6c6349SMats Randgaard u8 gain_buf[4]; 10745c6c6349SMats Randgaard u8 gain_man = 1; 10755c6c6349SMats Randgaard u8 agc_mode_man = 1; 10765c6c6349SMats Randgaard 10775c6c6349SMats Randgaard if (auto_gain) { 10785c6c6349SMats Randgaard gain_man = 0; 10795c6c6349SMats Randgaard agc_mode_man = 0; 10805c6c6349SMats Randgaard gain_a = 0x100; 10815c6c6349SMats Randgaard gain_b = 0x100; 10825c6c6349SMats Randgaard gain_c = 0x100; 10835c6c6349SMats Randgaard } 10845c6c6349SMats Randgaard 10855c6c6349SMats Randgaard v4l2_dbg(2, debug, sd, "%s: %s gain: a = 0x%x, b = 0x%x, c = 0x%x\n", 10865c6c6349SMats Randgaard __func__, auto_gain ? "Auto" : "Manual", 10875c6c6349SMats Randgaard gain_a, gain_b, gain_c); 10885c6c6349SMats Randgaard 10895c6c6349SMats Randgaard gain_buf[0] = ((gain_man << 7) | (agc_mode_man << 6) | ((gain_a & 0x3f0) >> 4)); 10905c6c6349SMats Randgaard gain_buf[1] = (((gain_a & 0x00f) << 4) | ((gain_b & 0x3c0) >> 6)); 10915c6c6349SMats Randgaard gain_buf[2] = (((gain_b & 0x03f) << 2) | ((gain_c & 0x300) >> 8)); 10925c6c6349SMats Randgaard gain_buf[3] = ((gain_c & 0x0ff)); 10935c6c6349SMats Randgaard 10945c6c6349SMats Randgaard /* Registers must be written in this order with no i2c access in between */ 109505cacb17SLaurent Pinchart if (adv_smbus_write_i2c_block_data(state, ADV7604_PAGE_CP, 109605cacb17SLaurent Pinchart 0x73, 4, gain_buf)) 10975c6c6349SMats Randgaard v4l2_err(sd, "%s: i2c error writing to CP reg 0x73, 0x74, 0x75, 0x76\n", __func__); 10985c6c6349SMats Randgaard } 10995c6c6349SMats Randgaard 110054450f59SHans Verkuil static void set_rgb_quantization_range(struct v4l2_subdev *sd) 110154450f59SHans Verkuil { 110254450f59SHans Verkuil struct adv7604_state *state = to_state(sd); 11035c6c6349SMats Randgaard bool rgb_output = io_read(sd, 0x02) & 0x02; 11045c6c6349SMats Randgaard bool hdmi_signal = hdmi_read(sd, 0x05) & 0x80; 110554450f59SHans Verkuil 11065c6c6349SMats Randgaard v4l2_dbg(2, debug, sd, "%s: RGB quantization range: %d, RGB out: %d, HDMI: %d\n", 11075c6c6349SMats Randgaard __func__, state->rgb_quantization_range, 11085c6c6349SMats Randgaard rgb_output, hdmi_signal); 11095c6c6349SMats Randgaard 11105c6c6349SMats Randgaard adv7604_set_gain(sd, true, 0x0, 0x0, 0x0); 11115c6c6349SMats Randgaard adv7604_set_offset(sd, true, 0x0, 0x0, 0x0); 11129833239eSMats Randgaard 111354450f59SHans Verkuil switch (state->rgb_quantization_range) { 111454450f59SHans Verkuil case V4L2_DV_RGB_RANGE_AUTO: 1115c784b1e2SLaurent Pinchart if (state->selected_input == ADV7604_PAD_VGA_RGB) { 11169833239eSMats Randgaard /* Receiving analog RGB signal 11179833239eSMats Randgaard * Set RGB full range (0-255) */ 111822d97e56SLaurent Pinchart io_write_clr_set(sd, 0x02, 0xf0, 0x10); 11199833239eSMats Randgaard break; 11209833239eSMats Randgaard } 112154450f59SHans Verkuil 1122c784b1e2SLaurent Pinchart if (state->selected_input == ADV7604_PAD_VGA_COMP) { 11239833239eSMats Randgaard /* Receiving analog YPbPr signal 11249833239eSMats Randgaard * Set automode */ 112522d97e56SLaurent Pinchart io_write_clr_set(sd, 0x02, 0xf0, 0xf0); 11269833239eSMats Randgaard break; 11279833239eSMats Randgaard } 11289833239eSMats Randgaard 11295c6c6349SMats Randgaard if (hdmi_signal) { 11309833239eSMats Randgaard /* Receiving HDMI signal 11319833239eSMats Randgaard * Set automode */ 113222d97e56SLaurent Pinchart io_write_clr_set(sd, 0x02, 0xf0, 0xf0); 11339833239eSMats Randgaard break; 11349833239eSMats Randgaard } 11359833239eSMats Randgaard 11369833239eSMats Randgaard /* Receiving DVI-D signal 11379833239eSMats Randgaard * ADV7604 selects RGB limited range regardless of 11389833239eSMats Randgaard * input format (CE/IT) in automatic mode */ 113954450f59SHans Verkuil if (state->timings.bt.standards & V4L2_DV_BT_STD_CEA861) { 114054450f59SHans Verkuil /* RGB limited range (16-235) */ 114122d97e56SLaurent Pinchart io_write_clr_set(sd, 0x02, 0xf0, 0x00); 114254450f59SHans Verkuil } else { 114354450f59SHans Verkuil /* RGB full range (0-255) */ 114422d97e56SLaurent Pinchart io_write_clr_set(sd, 0x02, 0xf0, 0x10); 11455c6c6349SMats Randgaard 11465c6c6349SMats Randgaard if (is_digital_input(sd) && rgb_output) { 11475c6c6349SMats Randgaard adv7604_set_offset(sd, false, 0x40, 0x40, 0x40); 11485c6c6349SMats Randgaard } else { 11495c6c6349SMats Randgaard adv7604_set_gain(sd, false, 0xe0, 0xe0, 0xe0); 11505c6c6349SMats Randgaard adv7604_set_offset(sd, false, 0x70, 0x70, 0x70); 11515c6c6349SMats Randgaard } 115254450f59SHans Verkuil } 115354450f59SHans Verkuil break; 115454450f59SHans Verkuil case V4L2_DV_RGB_RANGE_LIMITED: 1155c784b1e2SLaurent Pinchart if (state->selected_input == ADV7604_PAD_VGA_COMP) { 1156d261e842SMats Randgaard /* YCrCb limited range (16-235) */ 115722d97e56SLaurent Pinchart io_write_clr_set(sd, 0x02, 0xf0, 0x20); 11585c6c6349SMats Randgaard break; 11595c6c6349SMats Randgaard } 11605c6c6349SMats Randgaard 116154450f59SHans Verkuil /* RGB limited range (16-235) */ 116222d97e56SLaurent Pinchart io_write_clr_set(sd, 0x02, 0xf0, 0x00); 11635c6c6349SMats Randgaard 116454450f59SHans Verkuil break; 116554450f59SHans Verkuil case V4L2_DV_RGB_RANGE_FULL: 1166c784b1e2SLaurent Pinchart if (state->selected_input == ADV7604_PAD_VGA_COMP) { 1167d261e842SMats Randgaard /* YCrCb full range (0-255) */ 116822d97e56SLaurent Pinchart io_write_clr_set(sd, 0x02, 0xf0, 0x60); 11695c6c6349SMats Randgaard break; 11705c6c6349SMats Randgaard } 11715c6c6349SMats Randgaard 117254450f59SHans Verkuil /* RGB full range (0-255) */ 117322d97e56SLaurent Pinchart io_write_clr_set(sd, 0x02, 0xf0, 0x10); 11745c6c6349SMats Randgaard 11755c6c6349SMats Randgaard if (is_analog_input(sd) || hdmi_signal) 11765c6c6349SMats Randgaard break; 11775c6c6349SMats Randgaard 11785c6c6349SMats Randgaard /* Adjust gain/offset for DVI-D signals only */ 11795c6c6349SMats Randgaard if (rgb_output) { 11805c6c6349SMats Randgaard adv7604_set_offset(sd, false, 0x40, 0x40, 0x40); 11815c6c6349SMats Randgaard } else { 11825c6c6349SMats Randgaard adv7604_set_gain(sd, false, 0xe0, 0xe0, 0xe0); 11835c6c6349SMats Randgaard adv7604_set_offset(sd, false, 0x70, 0x70, 0x70); 1184d261e842SMats Randgaard } 118554450f59SHans Verkuil break; 118654450f59SHans Verkuil } 118754450f59SHans Verkuil } 118854450f59SHans Verkuil 118954450f59SHans Verkuil static int adv7604_s_ctrl(struct v4l2_ctrl *ctrl) 119054450f59SHans Verkuil { 1191c269887cSLaurent Pinchart struct v4l2_subdev *sd = 1192c269887cSLaurent Pinchart &container_of(ctrl->handler, struct adv7604_state, hdl)->sd; 1193c269887cSLaurent Pinchart 119454450f59SHans Verkuil struct adv7604_state *state = to_state(sd); 119554450f59SHans Verkuil 119654450f59SHans Verkuil switch (ctrl->id) { 119754450f59SHans Verkuil case V4L2_CID_BRIGHTNESS: 119854450f59SHans Verkuil cp_write(sd, 0x3c, ctrl->val); 119954450f59SHans Verkuil return 0; 120054450f59SHans Verkuil case V4L2_CID_CONTRAST: 120154450f59SHans Verkuil cp_write(sd, 0x3a, ctrl->val); 120254450f59SHans Verkuil return 0; 120354450f59SHans Verkuil case V4L2_CID_SATURATION: 120454450f59SHans Verkuil cp_write(sd, 0x3b, ctrl->val); 120554450f59SHans Verkuil return 0; 120654450f59SHans Verkuil case V4L2_CID_HUE: 120754450f59SHans Verkuil cp_write(sd, 0x3d, ctrl->val); 120854450f59SHans Verkuil return 0; 120954450f59SHans Verkuil case V4L2_CID_DV_RX_RGB_RANGE: 121054450f59SHans Verkuil state->rgb_quantization_range = ctrl->val; 121154450f59SHans Verkuil set_rgb_quantization_range(sd); 121254450f59SHans Verkuil return 0; 121354450f59SHans Verkuil case V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE: 1214d42010a1SLars-Peter Clausen if (!adv7604_has_afe(state)) 1215d42010a1SLars-Peter Clausen return -EINVAL; 121654450f59SHans Verkuil /* Set the analog sampling phase. This is needed to find the 121754450f59SHans Verkuil best sampling phase for analog video: an application or 121854450f59SHans Verkuil driver has to try a number of phases and analyze the picture 121954450f59SHans Verkuil quality before settling on the best performing phase. */ 122054450f59SHans Verkuil afe_write(sd, 0xc8, ctrl->val); 122154450f59SHans Verkuil return 0; 122254450f59SHans Verkuil case V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL: 122354450f59SHans Verkuil /* Use the default blue color for free running mode, 122454450f59SHans Verkuil or supply your own. */ 122522d97e56SLaurent Pinchart cp_write_clr_set(sd, 0xbf, 0x04, ctrl->val << 2); 122654450f59SHans Verkuil return 0; 122754450f59SHans Verkuil case V4L2_CID_ADV_RX_FREE_RUN_COLOR: 122854450f59SHans Verkuil cp_write(sd, 0xc0, (ctrl->val & 0xff0000) >> 16); 122954450f59SHans Verkuil cp_write(sd, 0xc1, (ctrl->val & 0x00ff00) >> 8); 123054450f59SHans Verkuil cp_write(sd, 0xc2, (u8)(ctrl->val & 0x0000ff)); 123154450f59SHans Verkuil return 0; 123254450f59SHans Verkuil } 123354450f59SHans Verkuil return -EINVAL; 123454450f59SHans Verkuil } 123554450f59SHans Verkuil 123654450f59SHans Verkuil /* ----------------------------------------------------------------------- */ 123754450f59SHans Verkuil 123854450f59SHans Verkuil static inline bool no_power(struct v4l2_subdev *sd) 123954450f59SHans Verkuil { 124054450f59SHans Verkuil /* Entire chip or CP powered off */ 124154450f59SHans Verkuil return io_read(sd, 0x0c) & 0x24; 124254450f59SHans Verkuil } 124354450f59SHans Verkuil 124454450f59SHans Verkuil static inline bool no_signal_tmds(struct v4l2_subdev *sd) 124554450f59SHans Verkuil { 12464a31a93aSMats Randgaard struct adv7604_state *state = to_state(sd); 12474a31a93aSMats Randgaard 12484a31a93aSMats Randgaard return !(io_read(sd, 0x6a) & (0x10 >> state->selected_input)); 124954450f59SHans Verkuil } 125054450f59SHans Verkuil 125154450f59SHans Verkuil static inline bool no_lock_tmds(struct v4l2_subdev *sd) 125254450f59SHans Verkuil { 1253d42010a1SLars-Peter Clausen struct adv7604_state *state = to_state(sd); 1254d42010a1SLars-Peter Clausen const struct adv7604_chip_info *info = state->info; 1255d42010a1SLars-Peter Clausen 1256d42010a1SLars-Peter Clausen return (io_read(sd, 0x6a) & info->tdms_lock_mask) != info->tdms_lock_mask; 125754450f59SHans Verkuil } 125854450f59SHans Verkuil 1259bb88f325SMartin Bugge static inline bool is_hdmi(struct v4l2_subdev *sd) 1260bb88f325SMartin Bugge { 1261bb88f325SMartin Bugge return hdmi_read(sd, 0x05) & 0x80; 1262bb88f325SMartin Bugge } 1263bb88f325SMartin Bugge 126454450f59SHans Verkuil static inline bool no_lock_sspd(struct v4l2_subdev *sd) 126554450f59SHans Verkuil { 1266d42010a1SLars-Peter Clausen struct adv7604_state *state = to_state(sd); 1267d42010a1SLars-Peter Clausen 1268d42010a1SLars-Peter Clausen /* 1269d42010a1SLars-Peter Clausen * Chips without a AFE don't expose registers for the SSPD, so just assume 1270d42010a1SLars-Peter Clausen * that we have a lock. 1271d42010a1SLars-Peter Clausen */ 1272d42010a1SLars-Peter Clausen if (adv7604_has_afe(state)) 1273d42010a1SLars-Peter Clausen return false; 1274d42010a1SLars-Peter Clausen 127554450f59SHans Verkuil /* TODO channel 2 */ 127654450f59SHans Verkuil return ((cp_read(sd, 0xb5) & 0xd0) != 0xd0); 127754450f59SHans Verkuil } 127854450f59SHans Verkuil 127954450f59SHans Verkuil static inline bool no_lock_stdi(struct v4l2_subdev *sd) 128054450f59SHans Verkuil { 128154450f59SHans Verkuil /* TODO channel 2 */ 128254450f59SHans Verkuil return !(cp_read(sd, 0xb1) & 0x80); 128354450f59SHans Verkuil } 128454450f59SHans Verkuil 128554450f59SHans Verkuil static inline bool no_signal(struct v4l2_subdev *sd) 128654450f59SHans Verkuil { 128754450f59SHans Verkuil bool ret; 128854450f59SHans Verkuil 128954450f59SHans Verkuil ret = no_power(sd); 129054450f59SHans Verkuil 129154450f59SHans Verkuil ret |= no_lock_stdi(sd); 129254450f59SHans Verkuil ret |= no_lock_sspd(sd); 129354450f59SHans Verkuil 12944a31a93aSMats Randgaard if (is_digital_input(sd)) { 129554450f59SHans Verkuil ret |= no_lock_tmds(sd); 129654450f59SHans Verkuil ret |= no_signal_tmds(sd); 129754450f59SHans Verkuil } 129854450f59SHans Verkuil 129954450f59SHans Verkuil return ret; 130054450f59SHans Verkuil } 130154450f59SHans Verkuil 130254450f59SHans Verkuil static inline bool no_lock_cp(struct v4l2_subdev *sd) 130354450f59SHans Verkuil { 1304d42010a1SLars-Peter Clausen struct adv7604_state *state = to_state(sd); 1305d42010a1SLars-Peter Clausen 1306d42010a1SLars-Peter Clausen if (!adv7604_has_afe(state)) 1307d42010a1SLars-Peter Clausen return false; 1308d42010a1SLars-Peter Clausen 130954450f59SHans Verkuil /* CP has detected a non standard number of lines on the incoming 131054450f59SHans Verkuil video compared to what it is configured to receive by s_dv_timings */ 131154450f59SHans Verkuil return io_read(sd, 0x12) & 0x01; 131254450f59SHans Verkuil } 131354450f59SHans Verkuil 131454450f59SHans Verkuil static int adv7604_g_input_status(struct v4l2_subdev *sd, u32 *status) 131554450f59SHans Verkuil { 131654450f59SHans Verkuil *status = 0; 131754450f59SHans Verkuil *status |= no_power(sd) ? V4L2_IN_ST_NO_POWER : 0; 131854450f59SHans Verkuil *status |= no_signal(sd) ? V4L2_IN_ST_NO_SIGNAL : 0; 131954450f59SHans Verkuil if (no_lock_cp(sd)) 13204a31a93aSMats Randgaard *status |= is_digital_input(sd) ? V4L2_IN_ST_NO_SYNC : V4L2_IN_ST_NO_H_LOCK; 132154450f59SHans Verkuil 132254450f59SHans Verkuil v4l2_dbg(1, debug, sd, "%s: status = 0x%x\n", __func__, *status); 132354450f59SHans Verkuil 132454450f59SHans Verkuil return 0; 132554450f59SHans Verkuil } 132654450f59SHans Verkuil 132754450f59SHans Verkuil /* ----------------------------------------------------------------------- */ 132854450f59SHans Verkuil 132954450f59SHans Verkuil struct stdi_readback { 133054450f59SHans Verkuil u16 bl, lcf, lcvs; 133154450f59SHans Verkuil u8 hs_pol, vs_pol; 133254450f59SHans Verkuil bool interlaced; 133354450f59SHans Verkuil }; 133454450f59SHans Verkuil 133554450f59SHans Verkuil static int stdi2dv_timings(struct v4l2_subdev *sd, 133654450f59SHans Verkuil struct stdi_readback *stdi, 133754450f59SHans Verkuil struct v4l2_dv_timings *timings) 133854450f59SHans Verkuil { 133954450f59SHans Verkuil struct adv7604_state *state = to_state(sd); 134054450f59SHans Verkuil u32 hfreq = (ADV7604_fsc * 8) / stdi->bl; 134154450f59SHans Verkuil u32 pix_clk; 134254450f59SHans Verkuil int i; 134354450f59SHans Verkuil 134454450f59SHans Verkuil for (i = 0; adv7604_timings[i].bt.height; i++) { 134554450f59SHans Verkuil if (vtotal(&adv7604_timings[i].bt) != stdi->lcf + 1) 134654450f59SHans Verkuil continue; 134754450f59SHans Verkuil if (adv7604_timings[i].bt.vsync != stdi->lcvs) 134854450f59SHans Verkuil continue; 134954450f59SHans Verkuil 135054450f59SHans Verkuil pix_clk = hfreq * htotal(&adv7604_timings[i].bt); 135154450f59SHans Verkuil 135254450f59SHans Verkuil if ((pix_clk < adv7604_timings[i].bt.pixelclock + 1000000) && 135354450f59SHans Verkuil (pix_clk > adv7604_timings[i].bt.pixelclock - 1000000)) { 135454450f59SHans Verkuil *timings = adv7604_timings[i]; 135554450f59SHans Verkuil return 0; 135654450f59SHans Verkuil } 135754450f59SHans Verkuil } 135854450f59SHans Verkuil 135954450f59SHans Verkuil if (v4l2_detect_cvt(stdi->lcf + 1, hfreq, stdi->lcvs, 136054450f59SHans Verkuil (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) | 136154450f59SHans Verkuil (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0), 136254450f59SHans Verkuil timings)) 136354450f59SHans Verkuil return 0; 136454450f59SHans Verkuil if (v4l2_detect_gtf(stdi->lcf + 1, hfreq, stdi->lcvs, 136554450f59SHans Verkuil (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) | 136654450f59SHans Verkuil (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0), 136754450f59SHans Verkuil state->aspect_ratio, timings)) 136854450f59SHans Verkuil return 0; 136954450f59SHans Verkuil 1370ccbd5bc4SHans Verkuil v4l2_dbg(2, debug, sd, 1371ccbd5bc4SHans Verkuil "%s: No format candidate found for lcvs = %d, lcf=%d, bl = %d, %chsync, %cvsync\n", 1372ccbd5bc4SHans Verkuil __func__, stdi->lcvs, stdi->lcf, stdi->bl, 1373ccbd5bc4SHans Verkuil stdi->hs_pol, stdi->vs_pol); 137454450f59SHans Verkuil return -1; 137554450f59SHans Verkuil } 137654450f59SHans Verkuil 1377d42010a1SLars-Peter Clausen 137854450f59SHans Verkuil static int read_stdi(struct v4l2_subdev *sd, struct stdi_readback *stdi) 137954450f59SHans Verkuil { 1380d42010a1SLars-Peter Clausen struct adv7604_state *state = to_state(sd); 1381d42010a1SLars-Peter Clausen const struct adv7604_chip_info *info = state->info; 13824a2ccdd2SLaurent Pinchart u8 polarity; 13834a2ccdd2SLaurent Pinchart 138454450f59SHans Verkuil if (no_lock_stdi(sd) || no_lock_sspd(sd)) { 138554450f59SHans Verkuil v4l2_dbg(2, debug, sd, "%s: STDI and/or SSPD not locked\n", __func__); 138654450f59SHans Verkuil return -1; 138754450f59SHans Verkuil } 138854450f59SHans Verkuil 138954450f59SHans Verkuil /* read STDI */ 139051182a94SLaurent Pinchart stdi->bl = cp_read16(sd, 0xb1, 0x3fff); 1391d42010a1SLars-Peter Clausen stdi->lcf = cp_read16(sd, info->lcf_reg, 0x7ff); 139254450f59SHans Verkuil stdi->lcvs = cp_read(sd, 0xb3) >> 3; 139354450f59SHans Verkuil stdi->interlaced = io_read(sd, 0x12) & 0x10; 139454450f59SHans Verkuil 1395d42010a1SLars-Peter Clausen if (adv7604_has_afe(state)) { 139654450f59SHans Verkuil /* read SSPD */ 13974a2ccdd2SLaurent Pinchart polarity = cp_read(sd, 0xb5); 13984a2ccdd2SLaurent Pinchart if ((polarity & 0x03) == 0x01) { 13994a2ccdd2SLaurent Pinchart stdi->hs_pol = polarity & 0x10 14004a2ccdd2SLaurent Pinchart ? (polarity & 0x08 ? '+' : '-') : 'x'; 14014a2ccdd2SLaurent Pinchart stdi->vs_pol = polarity & 0x40 14024a2ccdd2SLaurent Pinchart ? (polarity & 0x20 ? '+' : '-') : 'x'; 140354450f59SHans Verkuil } else { 140454450f59SHans Verkuil stdi->hs_pol = 'x'; 140554450f59SHans Verkuil stdi->vs_pol = 'x'; 140654450f59SHans Verkuil } 1407d42010a1SLars-Peter Clausen } else { 1408d42010a1SLars-Peter Clausen polarity = hdmi_read(sd, 0x05); 1409d42010a1SLars-Peter Clausen stdi->hs_pol = polarity & 0x20 ? '+' : '-'; 1410d42010a1SLars-Peter Clausen stdi->vs_pol = polarity & 0x10 ? '+' : '-'; 1411d42010a1SLars-Peter Clausen } 141254450f59SHans Verkuil 141354450f59SHans Verkuil if (no_lock_stdi(sd) || no_lock_sspd(sd)) { 141454450f59SHans Verkuil v4l2_dbg(2, debug, sd, 141554450f59SHans Verkuil "%s: signal lost during readout of STDI/SSPD\n", __func__); 141654450f59SHans Verkuil return -1; 141754450f59SHans Verkuil } 141854450f59SHans Verkuil 141954450f59SHans Verkuil if (stdi->lcf < 239 || stdi->bl < 8 || stdi->bl == 0x3fff) { 142054450f59SHans Verkuil v4l2_dbg(2, debug, sd, "%s: invalid signal\n", __func__); 142154450f59SHans Verkuil memset(stdi, 0, sizeof(struct stdi_readback)); 142254450f59SHans Verkuil return -1; 142354450f59SHans Verkuil } 142454450f59SHans Verkuil 142554450f59SHans Verkuil v4l2_dbg(2, debug, sd, 142654450f59SHans Verkuil "%s: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %chsync, %cvsync, %s\n", 142754450f59SHans Verkuil __func__, stdi->lcf, stdi->bl, stdi->lcvs, 142854450f59SHans Verkuil stdi->hs_pol, stdi->vs_pol, 142954450f59SHans Verkuil stdi->interlaced ? "interlaced" : "progressive"); 143054450f59SHans Verkuil 143154450f59SHans Verkuil return 0; 143254450f59SHans Verkuil } 143354450f59SHans Verkuil 143454450f59SHans Verkuil static int adv7604_enum_dv_timings(struct v4l2_subdev *sd, 143554450f59SHans Verkuil struct v4l2_enum_dv_timings *timings) 143654450f59SHans Verkuil { 1437afec5599SLaurent Pinchart struct adv7604_state *state = to_state(sd); 1438afec5599SLaurent Pinchart 143954450f59SHans Verkuil if (timings->index >= ARRAY_SIZE(adv7604_timings) - 1) 144054450f59SHans Verkuil return -EINVAL; 1441afec5599SLaurent Pinchart 1442afec5599SLaurent Pinchart if (timings->pad >= state->source_pad) 1443afec5599SLaurent Pinchart return -EINVAL; 1444afec5599SLaurent Pinchart 144554450f59SHans Verkuil memset(timings->reserved, 0, sizeof(timings->reserved)); 144654450f59SHans Verkuil timings->timings = adv7604_timings[timings->index]; 144754450f59SHans Verkuil return 0; 144854450f59SHans Verkuil } 144954450f59SHans Verkuil 14507515e096SLaurent Pinchart static int adv7604_dv_timings_cap(struct v4l2_subdev *sd, 14517515e096SLaurent Pinchart struct v4l2_dv_timings_cap *cap) 1452afec5599SLaurent Pinchart { 14537515e096SLaurent Pinchart struct adv7604_state *state = to_state(sd); 14547515e096SLaurent Pinchart 14557515e096SLaurent Pinchart if (cap->pad >= state->source_pad) 14567515e096SLaurent Pinchart return -EINVAL; 14577515e096SLaurent Pinchart 1458afec5599SLaurent Pinchart cap->type = V4L2_DV_BT_656_1120; 1459afec5599SLaurent Pinchart cap->bt.max_width = 1920; 1460afec5599SLaurent Pinchart cap->bt.max_height = 1200; 1461afec5599SLaurent Pinchart cap->bt.min_pixelclock = 25000000; 1462afec5599SLaurent Pinchart 14637515e096SLaurent Pinchart switch (cap->pad) { 1464afec5599SLaurent Pinchart case ADV7604_PAD_HDMI_PORT_A: 1465afec5599SLaurent Pinchart case ADV7604_PAD_HDMI_PORT_B: 1466afec5599SLaurent Pinchart case ADV7604_PAD_HDMI_PORT_C: 1467afec5599SLaurent Pinchart case ADV7604_PAD_HDMI_PORT_D: 1468afec5599SLaurent Pinchart cap->bt.max_pixelclock = 225000000; 1469afec5599SLaurent Pinchart break; 1470afec5599SLaurent Pinchart case ADV7604_PAD_VGA_RGB: 1471afec5599SLaurent Pinchart case ADV7604_PAD_VGA_COMP: 1472afec5599SLaurent Pinchart default: 1473afec5599SLaurent Pinchart cap->bt.max_pixelclock = 170000000; 1474afec5599SLaurent Pinchart break; 1475afec5599SLaurent Pinchart } 1476afec5599SLaurent Pinchart 1477afec5599SLaurent Pinchart cap->bt.standards = V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT | 1478afec5599SLaurent Pinchart V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT; 1479afec5599SLaurent Pinchart cap->bt.capabilities = V4L2_DV_BT_CAP_PROGRESSIVE | 1480afec5599SLaurent Pinchart V4L2_DV_BT_CAP_REDUCED_BLANKING | V4L2_DV_BT_CAP_CUSTOM; 1481afec5599SLaurent Pinchart return 0; 1482afec5599SLaurent Pinchart } 1483afec5599SLaurent Pinchart 148454450f59SHans Verkuil /* Fill the optional fields .standards and .flags in struct v4l2_dv_timings 148554450f59SHans Verkuil if the format is listed in adv7604_timings[] */ 148654450f59SHans Verkuil static void adv7604_fill_optional_dv_timings_fields(struct v4l2_subdev *sd, 148754450f59SHans Verkuil struct v4l2_dv_timings *timings) 148854450f59SHans Verkuil { 148954450f59SHans Verkuil int i; 149054450f59SHans Verkuil 149154450f59SHans Verkuil for (i = 0; adv7604_timings[i].bt.width; i++) { 1492ef1ed8f5SHans Verkuil if (v4l2_match_dv_timings(timings, &adv7604_timings[i], 14934a31a93aSMats Randgaard is_digital_input(sd) ? 250000 : 1000000)) { 149454450f59SHans Verkuil *timings = adv7604_timings[i]; 149554450f59SHans Verkuil break; 149654450f59SHans Verkuil } 149754450f59SHans Verkuil } 149854450f59SHans Verkuil } 149954450f59SHans Verkuil 1500d42010a1SLars-Peter Clausen static unsigned int adv7604_read_hdmi_pixelclock(struct v4l2_subdev *sd) 1501d42010a1SLars-Peter Clausen { 1502d42010a1SLars-Peter Clausen unsigned int freq; 1503d42010a1SLars-Peter Clausen int a, b; 1504d42010a1SLars-Peter Clausen 1505d42010a1SLars-Peter Clausen a = hdmi_read(sd, 0x06); 1506d42010a1SLars-Peter Clausen b = hdmi_read(sd, 0x3b); 1507d42010a1SLars-Peter Clausen if (a < 0 || b < 0) 1508d42010a1SLars-Peter Clausen return 0; 1509d42010a1SLars-Peter Clausen freq = a * 1000000 + ((b & 0x30) >> 4) * 250000; 1510d42010a1SLars-Peter Clausen 1511d42010a1SLars-Peter Clausen if (is_hdmi(sd)) { 1512d42010a1SLars-Peter Clausen /* adjust for deep color mode */ 1513d42010a1SLars-Peter Clausen unsigned bits_per_channel = ((hdmi_read(sd, 0x0b) & 0x60) >> 4) + 8; 1514d42010a1SLars-Peter Clausen 1515d42010a1SLars-Peter Clausen freq = freq * 8 / bits_per_channel; 1516d42010a1SLars-Peter Clausen } 1517d42010a1SLars-Peter Clausen 1518d42010a1SLars-Peter Clausen return freq; 1519d42010a1SLars-Peter Clausen } 1520d42010a1SLars-Peter Clausen 1521d42010a1SLars-Peter Clausen static unsigned int adv7611_read_hdmi_pixelclock(struct v4l2_subdev *sd) 1522d42010a1SLars-Peter Clausen { 1523d42010a1SLars-Peter Clausen int a, b; 1524d42010a1SLars-Peter Clausen 1525d42010a1SLars-Peter Clausen a = hdmi_read(sd, 0x51); 1526d42010a1SLars-Peter Clausen b = hdmi_read(sd, 0x52); 1527d42010a1SLars-Peter Clausen if (a < 0 || b < 0) 1528d42010a1SLars-Peter Clausen return 0; 1529d42010a1SLars-Peter Clausen return ((a << 1) | (b >> 7)) * 1000000 + (b & 0x7f) * 1000000 / 128; 1530d42010a1SLars-Peter Clausen } 1531d42010a1SLars-Peter Clausen 153254450f59SHans Verkuil static int adv7604_query_dv_timings(struct v4l2_subdev *sd, 153354450f59SHans Verkuil struct v4l2_dv_timings *timings) 153454450f59SHans Verkuil { 153554450f59SHans Verkuil struct adv7604_state *state = to_state(sd); 1536d42010a1SLars-Peter Clausen const struct adv7604_chip_info *info = state->info; 153754450f59SHans Verkuil struct v4l2_bt_timings *bt = &timings->bt; 153854450f59SHans Verkuil struct stdi_readback stdi; 153954450f59SHans Verkuil 154054450f59SHans Verkuil if (!timings) 154154450f59SHans Verkuil return -EINVAL; 154254450f59SHans Verkuil 154354450f59SHans Verkuil memset(timings, 0, sizeof(struct v4l2_dv_timings)); 154454450f59SHans Verkuil 154554450f59SHans Verkuil if (no_signal(sd)) { 15461e0b9156SMartin Bugge state->restart_stdi_once = true; 154754450f59SHans Verkuil v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__); 154854450f59SHans Verkuil return -ENOLINK; 154954450f59SHans Verkuil } 155054450f59SHans Verkuil 155154450f59SHans Verkuil /* read STDI */ 155254450f59SHans Verkuil if (read_stdi(sd, &stdi)) { 155354450f59SHans Verkuil v4l2_dbg(1, debug, sd, "%s: STDI/SSPD not locked\n", __func__); 155454450f59SHans Verkuil return -ENOLINK; 155554450f59SHans Verkuil } 155654450f59SHans Verkuil bt->interlaced = stdi.interlaced ? 155754450f59SHans Verkuil V4L2_DV_INTERLACED : V4L2_DV_PROGRESSIVE; 155854450f59SHans Verkuil 15594a31a93aSMats Randgaard if (is_digital_input(sd)) { 156054450f59SHans Verkuil timings->type = V4L2_DV_BT_656_1120; 156154450f59SHans Verkuil 1562d42010a1SLars-Peter Clausen /* FIXME: All masks are incorrect for ADV7611 */ 156351182a94SLaurent Pinchart bt->width = hdmi_read16(sd, 0x07, 0xfff); 156451182a94SLaurent Pinchart bt->height = hdmi_read16(sd, 0x09, 0xfff); 1565d42010a1SLars-Peter Clausen bt->pixelclock = info->read_hdmi_pixelclock(sd); 156651182a94SLaurent Pinchart bt->hfrontporch = hdmi_read16(sd, 0x20, 0x3ff); 156751182a94SLaurent Pinchart bt->hsync = hdmi_read16(sd, 0x22, 0x3ff); 156851182a94SLaurent Pinchart bt->hbackporch = hdmi_read16(sd, 0x24, 0x3ff); 156951182a94SLaurent Pinchart bt->vfrontporch = hdmi_read16(sd, 0x2a, 0x1fff) / 2; 157051182a94SLaurent Pinchart bt->vsync = hdmi_read16(sd, 0x2e, 0x1fff) / 2; 157151182a94SLaurent Pinchart bt->vbackporch = hdmi_read16(sd, 0x32, 0x1fff) / 2; 157254450f59SHans Verkuil bt->polarities = ((hdmi_read(sd, 0x05) & 0x10) ? V4L2_DV_VSYNC_POS_POL : 0) | 157354450f59SHans Verkuil ((hdmi_read(sd, 0x05) & 0x20) ? V4L2_DV_HSYNC_POS_POL : 0); 157454450f59SHans Verkuil if (bt->interlaced == V4L2_DV_INTERLACED) { 157551182a94SLaurent Pinchart bt->height += hdmi_read16(sd, 0x0b, 0xfff); 157651182a94SLaurent Pinchart bt->il_vfrontporch = hdmi_read16(sd, 0x2c, 0x1fff) / 2; 157751182a94SLaurent Pinchart bt->il_vsync = hdmi_read16(sd, 0x30, 0x1fff) / 2; 157851182a94SLaurent Pinchart bt->vbackporch = hdmi_read16(sd, 0x34, 0x1fff) / 2; 157954450f59SHans Verkuil } 158054450f59SHans Verkuil adv7604_fill_optional_dv_timings_fields(sd, timings); 158154450f59SHans Verkuil } else { 158254450f59SHans Verkuil /* find format 158380939647SHans Verkuil * Since LCVS values are inaccurate [REF_03, p. 275-276], 158454450f59SHans Verkuil * stdi2dv_timings() is called with lcvs +-1 if the first attempt fails. 158554450f59SHans Verkuil */ 158654450f59SHans Verkuil if (!stdi2dv_timings(sd, &stdi, timings)) 158754450f59SHans Verkuil goto found; 158854450f59SHans Verkuil stdi.lcvs += 1; 158954450f59SHans Verkuil v4l2_dbg(1, debug, sd, "%s: lcvs + 1 = %d\n", __func__, stdi.lcvs); 159054450f59SHans Verkuil if (!stdi2dv_timings(sd, &stdi, timings)) 159154450f59SHans Verkuil goto found; 159254450f59SHans Verkuil stdi.lcvs -= 2; 159354450f59SHans Verkuil v4l2_dbg(1, debug, sd, "%s: lcvs - 1 = %d\n", __func__, stdi.lcvs); 159454450f59SHans Verkuil if (stdi2dv_timings(sd, &stdi, timings)) { 1595cf9afb1dSHans Verkuil /* 1596cf9afb1dSHans Verkuil * The STDI block may measure wrong values, especially 1597cf9afb1dSHans Verkuil * for lcvs and lcf. If the driver can not find any 1598cf9afb1dSHans Verkuil * valid timing, the STDI block is restarted to measure 1599cf9afb1dSHans Verkuil * the video timings again. The function will return an 1600cf9afb1dSHans Verkuil * error, but the restart of STDI will generate a new 1601cf9afb1dSHans Verkuil * STDI interrupt and the format detection process will 1602cf9afb1dSHans Verkuil * restart. 1603cf9afb1dSHans Verkuil */ 1604cf9afb1dSHans Verkuil if (state->restart_stdi_once) { 1605cf9afb1dSHans Verkuil v4l2_dbg(1, debug, sd, "%s: restart STDI\n", __func__); 1606cf9afb1dSHans Verkuil /* TODO restart STDI for Sync Channel 2 */ 1607cf9afb1dSHans Verkuil /* enter one-shot mode */ 160822d97e56SLaurent Pinchart cp_write_clr_set(sd, 0x86, 0x06, 0x00); 1609cf9afb1dSHans Verkuil /* trigger STDI restart */ 161022d97e56SLaurent Pinchart cp_write_clr_set(sd, 0x86, 0x06, 0x04); 1611cf9afb1dSHans Verkuil /* reset to continuous mode */ 161222d97e56SLaurent Pinchart cp_write_clr_set(sd, 0x86, 0x06, 0x02); 1613cf9afb1dSHans Verkuil state->restart_stdi_once = false; 1614cf9afb1dSHans Verkuil return -ENOLINK; 1615cf9afb1dSHans Verkuil } 161654450f59SHans Verkuil v4l2_dbg(1, debug, sd, "%s: format not supported\n", __func__); 161754450f59SHans Verkuil return -ERANGE; 161854450f59SHans Verkuil } 1619cf9afb1dSHans Verkuil state->restart_stdi_once = true; 162054450f59SHans Verkuil } 162154450f59SHans Verkuil found: 162254450f59SHans Verkuil 162354450f59SHans Verkuil if (no_signal(sd)) { 162454450f59SHans Verkuil v4l2_dbg(1, debug, sd, "%s: signal lost during readout\n", __func__); 162554450f59SHans Verkuil memset(timings, 0, sizeof(struct v4l2_dv_timings)); 162654450f59SHans Verkuil return -ENOLINK; 162754450f59SHans Verkuil } 162854450f59SHans Verkuil 16294a31a93aSMats Randgaard if ((is_analog_input(sd) && bt->pixelclock > 170000000) || 16304a31a93aSMats Randgaard (is_digital_input(sd) && bt->pixelclock > 225000000)) { 163154450f59SHans Verkuil v4l2_dbg(1, debug, sd, "%s: pixelclock out of range %d\n", 163254450f59SHans Verkuil __func__, (u32)bt->pixelclock); 163354450f59SHans Verkuil return -ERANGE; 163454450f59SHans Verkuil } 163554450f59SHans Verkuil 163654450f59SHans Verkuil if (debug > 1) 163711d034c8SHans Verkuil v4l2_print_dv_timings(sd->name, "adv7604_query_dv_timings: ", 163811d034c8SHans Verkuil timings, true); 163954450f59SHans Verkuil 164054450f59SHans Verkuil return 0; 164154450f59SHans Verkuil } 164254450f59SHans Verkuil 164354450f59SHans Verkuil static int adv7604_s_dv_timings(struct v4l2_subdev *sd, 164454450f59SHans Verkuil struct v4l2_dv_timings *timings) 164554450f59SHans Verkuil { 164654450f59SHans Verkuil struct adv7604_state *state = to_state(sd); 164754450f59SHans Verkuil struct v4l2_bt_timings *bt; 1648ccbd5bc4SHans Verkuil int err; 164954450f59SHans Verkuil 165054450f59SHans Verkuil if (!timings) 165154450f59SHans Verkuil return -EINVAL; 165254450f59SHans Verkuil 1653d48eb48cSMats Randgaard if (v4l2_match_dv_timings(&state->timings, timings, 0)) { 1654d48eb48cSMats Randgaard v4l2_dbg(1, debug, sd, "%s: no change\n", __func__); 1655d48eb48cSMats Randgaard return 0; 1656d48eb48cSMats Randgaard } 1657d48eb48cSMats Randgaard 165854450f59SHans Verkuil bt = &timings->bt; 165954450f59SHans Verkuil 16604a31a93aSMats Randgaard if ((is_analog_input(sd) && bt->pixelclock > 170000000) || 16614a31a93aSMats Randgaard (is_digital_input(sd) && bt->pixelclock > 225000000)) { 166254450f59SHans Verkuil v4l2_dbg(1, debug, sd, "%s: pixelclock out of range %d\n", 166354450f59SHans Verkuil __func__, (u32)bt->pixelclock); 166454450f59SHans Verkuil return -ERANGE; 166554450f59SHans Verkuil } 1666ccbd5bc4SHans Verkuil 166754450f59SHans Verkuil adv7604_fill_optional_dv_timings_fields(sd, timings); 166854450f59SHans Verkuil 166954450f59SHans Verkuil state->timings = *timings; 167054450f59SHans Verkuil 167122d97e56SLaurent Pinchart cp_write_clr_set(sd, 0x91, 0x40, bt->interlaced ? 0x40 : 0x00); 1672ccbd5bc4SHans Verkuil 1673ccbd5bc4SHans Verkuil /* Use prim_mode and vid_std when available */ 1674ccbd5bc4SHans Verkuil err = configure_predefined_video_timings(sd, timings); 1675ccbd5bc4SHans Verkuil if (err) { 1676ccbd5bc4SHans Verkuil /* custom settings when the video format 1677ccbd5bc4SHans Verkuil does not have prim_mode/vid_std */ 1678ccbd5bc4SHans Verkuil configure_custom_video_timings(sd, bt); 1679ccbd5bc4SHans Verkuil } 168054450f59SHans Verkuil 168154450f59SHans Verkuil set_rgb_quantization_range(sd); 168254450f59SHans Verkuil 168354450f59SHans Verkuil if (debug > 1) 168411d034c8SHans Verkuil v4l2_print_dv_timings(sd->name, "adv7604_s_dv_timings: ", 168511d034c8SHans Verkuil timings, true); 168654450f59SHans Verkuil return 0; 168754450f59SHans Verkuil } 168854450f59SHans Verkuil 168954450f59SHans Verkuil static int adv7604_g_dv_timings(struct v4l2_subdev *sd, 169054450f59SHans Verkuil struct v4l2_dv_timings *timings) 169154450f59SHans Verkuil { 169254450f59SHans Verkuil struct adv7604_state *state = to_state(sd); 169354450f59SHans Verkuil 169454450f59SHans Verkuil *timings = state->timings; 169554450f59SHans Verkuil return 0; 169654450f59SHans Verkuil } 169754450f59SHans Verkuil 1698d42010a1SLars-Peter Clausen static void adv7604_set_termination(struct v4l2_subdev *sd, bool enable) 1699d42010a1SLars-Peter Clausen { 1700d42010a1SLars-Peter Clausen hdmi_write(sd, 0x01, enable ? 0x00 : 0x78); 1701d42010a1SLars-Peter Clausen } 1702d42010a1SLars-Peter Clausen 1703d42010a1SLars-Peter Clausen static void adv7611_set_termination(struct v4l2_subdev *sd, bool enable) 1704d42010a1SLars-Peter Clausen { 1705d42010a1SLars-Peter Clausen hdmi_write(sd, 0x83, enable ? 0xfe : 0xff); 1706d42010a1SLars-Peter Clausen } 1707d42010a1SLars-Peter Clausen 17086b0d5d34SHans Verkuil static void enable_input(struct v4l2_subdev *sd) 170954450f59SHans Verkuil { 17106b0d5d34SHans Verkuil struct adv7604_state *state = to_state(sd); 17116b0d5d34SHans Verkuil 17124a31a93aSMats Randgaard if (is_analog_input(sd)) { 171354450f59SHans Verkuil io_write(sd, 0x15, 0xb0); /* Disable Tristate of Pins (no audio) */ 17144a31a93aSMats Randgaard } else if (is_digital_input(sd)) { 171522d97e56SLaurent Pinchart hdmi_write_clr_set(sd, 0x00, 0x03, state->selected_input); 1716d42010a1SLars-Peter Clausen state->info->set_termination(sd, true); 171754450f59SHans Verkuil io_write(sd, 0x15, 0xa0); /* Disable Tristate of Pins */ 171822d97e56SLaurent Pinchart hdmi_write_clr_set(sd, 0x1a, 0x10, 0x00); /* Unmute audio */ 17194a31a93aSMats Randgaard } else { 17204a31a93aSMats Randgaard v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n", 17214a31a93aSMats Randgaard __func__, state->selected_input); 172254450f59SHans Verkuil } 172354450f59SHans Verkuil } 172454450f59SHans Verkuil 172554450f59SHans Verkuil static void disable_input(struct v4l2_subdev *sd) 172654450f59SHans Verkuil { 1727d42010a1SLars-Peter Clausen struct adv7604_state *state = to_state(sd); 1728d42010a1SLars-Peter Clausen 172922d97e56SLaurent Pinchart hdmi_write_clr_set(sd, 0x1a, 0x10, 0x10); /* Mute audio */ 17305474b983SMats Randgaard msleep(16); /* 512 samples with >= 32 kHz sample rate [REF_03, c. 7.16.10] */ 173154450f59SHans Verkuil io_write(sd, 0x15, 0xbe); /* Tristate all outputs from video core */ 1732d42010a1SLars-Peter Clausen state->info->set_termination(sd, false); 173354450f59SHans Verkuil } 173454450f59SHans Verkuil 17356b0d5d34SHans Verkuil static void select_input(struct v4l2_subdev *sd) 173654450f59SHans Verkuil { 17376b0d5d34SHans Verkuil struct adv7604_state *state = to_state(sd); 1738d42010a1SLars-Peter Clausen const struct adv7604_chip_info *info = state->info; 173954450f59SHans Verkuil 17404a31a93aSMats Randgaard if (is_analog_input(sd)) { 1741d42010a1SLars-Peter Clausen adv7604_write_reg_seq(sd, info->recommended_settings[0]); 174254450f59SHans Verkuil 174354450f59SHans Verkuil afe_write(sd, 0x00, 0x08); /* power up ADC */ 174454450f59SHans Verkuil afe_write(sd, 0x01, 0x06); /* power up Analog Front End */ 174554450f59SHans Verkuil afe_write(sd, 0xc8, 0x00); /* phase control */ 17464a31a93aSMats Randgaard } else if (is_digital_input(sd)) { 17474a31a93aSMats Randgaard hdmi_write(sd, 0x00, state->selected_input & 0x03); 174854450f59SHans Verkuil 1749d42010a1SLars-Peter Clausen adv7604_write_reg_seq(sd, info->recommended_settings[1]); 175054450f59SHans Verkuil 1751d42010a1SLars-Peter Clausen if (adv7604_has_afe(state)) { 175254450f59SHans Verkuil afe_write(sd, 0x00, 0xff); /* power down ADC */ 175354450f59SHans Verkuil afe_write(sd, 0x01, 0xfe); /* power down Analog Front End */ 175454450f59SHans Verkuil afe_write(sd, 0xc8, 0x40); /* phase control */ 1755d42010a1SLars-Peter Clausen } 175654450f59SHans Verkuil 175754450f59SHans Verkuil cp_write(sd, 0x3e, 0x00); /* CP core pre-gain control */ 175854450f59SHans Verkuil cp_write(sd, 0xc3, 0x39); /* CP coast control. Graphics mode */ 175954450f59SHans Verkuil cp_write(sd, 0x40, 0x80); /* CP core pre-gain control. Graphics mode */ 17604a31a93aSMats Randgaard } else { 17614a31a93aSMats Randgaard v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n", 17624a31a93aSMats Randgaard __func__, state->selected_input); 176354450f59SHans Verkuil } 176454450f59SHans Verkuil } 176554450f59SHans Verkuil 176654450f59SHans Verkuil static int adv7604_s_routing(struct v4l2_subdev *sd, 176754450f59SHans Verkuil u32 input, u32 output, u32 config) 176854450f59SHans Verkuil { 176954450f59SHans Verkuil struct adv7604_state *state = to_state(sd); 177054450f59SHans Verkuil 1771ff4f80fdSMats Randgaard v4l2_dbg(2, debug, sd, "%s: input %d, selected input %d", 1772ff4f80fdSMats Randgaard __func__, input, state->selected_input); 1773ff4f80fdSMats Randgaard 1774ff4f80fdSMats Randgaard if (input == state->selected_input) 1775ff4f80fdSMats Randgaard return 0; 177654450f59SHans Verkuil 1777d42010a1SLars-Peter Clausen if (input > state->info->max_port) 1778d42010a1SLars-Peter Clausen return -EINVAL; 1779d42010a1SLars-Peter Clausen 17804a31a93aSMats Randgaard state->selected_input = input; 178154450f59SHans Verkuil 178254450f59SHans Verkuil disable_input(sd); 178354450f59SHans Verkuil 17846b0d5d34SHans Verkuil select_input(sd); 178554450f59SHans Verkuil 17866b0d5d34SHans Verkuil enable_input(sd); 178754450f59SHans Verkuil 178854450f59SHans Verkuil return 0; 178954450f59SHans Verkuil } 179054450f59SHans Verkuil 1791539b33b0SLaurent Pinchart static int adv7604_enum_mbus_code(struct v4l2_subdev *sd, 1792539b33b0SLaurent Pinchart struct v4l2_subdev_fh *fh, 1793539b33b0SLaurent Pinchart struct v4l2_subdev_mbus_code_enum *code) 179454450f59SHans Verkuil { 179554450f59SHans Verkuil struct adv7604_state *state = to_state(sd); 179654450f59SHans Verkuil 1797539b33b0SLaurent Pinchart if (code->index >= state->info->nformats) 1798539b33b0SLaurent Pinchart return -EINVAL; 1799539b33b0SLaurent Pinchart 1800539b33b0SLaurent Pinchart code->code = state->info->formats[code->index].code; 1801539b33b0SLaurent Pinchart 1802539b33b0SLaurent Pinchart return 0; 1803539b33b0SLaurent Pinchart } 1804539b33b0SLaurent Pinchart 1805539b33b0SLaurent Pinchart static void adv7604_fill_format(struct adv7604_state *state, 1806539b33b0SLaurent Pinchart struct v4l2_mbus_framefmt *format) 1807539b33b0SLaurent Pinchart { 1808539b33b0SLaurent Pinchart memset(format, 0, sizeof(*format)); 1809539b33b0SLaurent Pinchart 1810539b33b0SLaurent Pinchart format->width = state->timings.bt.width; 1811539b33b0SLaurent Pinchart format->height = state->timings.bt.height; 1812539b33b0SLaurent Pinchart format->field = V4L2_FIELD_NONE; 1813539b33b0SLaurent Pinchart 1814539b33b0SLaurent Pinchart if (state->timings.bt.standards & V4L2_DV_BT_STD_CEA861) 1815539b33b0SLaurent Pinchart format->colorspace = (state->timings.bt.height <= 576) ? 181654450f59SHans Verkuil V4L2_COLORSPACE_SMPTE170M : V4L2_COLORSPACE_REC709; 181754450f59SHans Verkuil } 1818539b33b0SLaurent Pinchart 1819539b33b0SLaurent Pinchart /* 1820539b33b0SLaurent Pinchart * Compute the op_ch_sel value required to obtain on the bus the component order 1821539b33b0SLaurent Pinchart * corresponding to the selected format taking into account bus reordering 1822539b33b0SLaurent Pinchart * applied by the board at the output of the device. 1823539b33b0SLaurent Pinchart * 1824539b33b0SLaurent Pinchart * The following table gives the op_ch_value from the format component order 1825539b33b0SLaurent Pinchart * (expressed as op_ch_sel value in column) and the bus reordering (expressed as 1826539b33b0SLaurent Pinchart * adv7604_bus_order value in row). 1827539b33b0SLaurent Pinchart * 1828539b33b0SLaurent Pinchart * | GBR(0) GRB(1) BGR(2) RGB(3) BRG(4) RBG(5) 1829539b33b0SLaurent Pinchart * ----------+------------------------------------------------- 1830539b33b0SLaurent Pinchart * RGB (NOP) | GBR GRB BGR RGB BRG RBG 1831539b33b0SLaurent Pinchart * GRB (1-2) | BGR RGB GBR GRB RBG BRG 1832539b33b0SLaurent Pinchart * RBG (2-3) | GRB GBR BRG RBG BGR RGB 1833539b33b0SLaurent Pinchart * BGR (1-3) | RBG BRG RGB BGR GRB GBR 1834539b33b0SLaurent Pinchart * BRG (ROR) | BRG RBG GRB GBR RGB BGR 1835539b33b0SLaurent Pinchart * GBR (ROL) | RGB BGR RBG BRG GBR GRB 1836539b33b0SLaurent Pinchart */ 1837539b33b0SLaurent Pinchart static unsigned int adv7604_op_ch_sel(struct adv7604_state *state) 1838539b33b0SLaurent Pinchart { 1839539b33b0SLaurent Pinchart #define _SEL(a,b,c,d,e,f) { \ 1840539b33b0SLaurent Pinchart ADV7604_OP_CH_SEL_##a, ADV7604_OP_CH_SEL_##b, ADV7604_OP_CH_SEL_##c, \ 1841539b33b0SLaurent Pinchart ADV7604_OP_CH_SEL_##d, ADV7604_OP_CH_SEL_##e, ADV7604_OP_CH_SEL_##f } 1842539b33b0SLaurent Pinchart #define _BUS(x) [ADV7604_BUS_ORDER_##x] 1843539b33b0SLaurent Pinchart 1844539b33b0SLaurent Pinchart static const unsigned int op_ch_sel[6][6] = { 1845539b33b0SLaurent Pinchart _BUS(RGB) /* NOP */ = _SEL(GBR, GRB, BGR, RGB, BRG, RBG), 1846539b33b0SLaurent Pinchart _BUS(GRB) /* 1-2 */ = _SEL(BGR, RGB, GBR, GRB, RBG, BRG), 1847539b33b0SLaurent Pinchart _BUS(RBG) /* 2-3 */ = _SEL(GRB, GBR, BRG, RBG, BGR, RGB), 1848539b33b0SLaurent Pinchart _BUS(BGR) /* 1-3 */ = _SEL(RBG, BRG, RGB, BGR, GRB, GBR), 1849539b33b0SLaurent Pinchart _BUS(BRG) /* ROR */ = _SEL(BRG, RBG, GRB, GBR, RGB, BGR), 1850539b33b0SLaurent Pinchart _BUS(GBR) /* ROL */ = _SEL(RGB, BGR, RBG, BRG, GBR, GRB), 1851539b33b0SLaurent Pinchart }; 1852539b33b0SLaurent Pinchart 1853539b33b0SLaurent Pinchart return op_ch_sel[state->pdata.bus_order][state->format->op_ch_sel >> 5]; 1854539b33b0SLaurent Pinchart } 1855539b33b0SLaurent Pinchart 1856539b33b0SLaurent Pinchart static void adv7604_setup_format(struct adv7604_state *state) 1857539b33b0SLaurent Pinchart { 1858539b33b0SLaurent Pinchart struct v4l2_subdev *sd = &state->sd; 1859539b33b0SLaurent Pinchart 186022d97e56SLaurent Pinchart io_write_clr_set(sd, 0x02, 0x02, 1861539b33b0SLaurent Pinchart state->format->rgb_out ? ADV7604_RGB_OUT : 0); 1862539b33b0SLaurent Pinchart io_write(sd, 0x03, state->format->op_format_sel | 1863539b33b0SLaurent Pinchart state->pdata.op_format_mode_sel); 186422d97e56SLaurent Pinchart io_write_clr_set(sd, 0x04, 0xe0, adv7604_op_ch_sel(state)); 186522d97e56SLaurent Pinchart io_write_clr_set(sd, 0x05, 0x01, 1866539b33b0SLaurent Pinchart state->format->swap_cb_cr ? ADV7604_OP_SWAP_CB_CR : 0); 1867539b33b0SLaurent Pinchart } 1868539b33b0SLaurent Pinchart 1869539b33b0SLaurent Pinchart static int adv7604_get_format(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh, 1870539b33b0SLaurent Pinchart struct v4l2_subdev_format *format) 1871539b33b0SLaurent Pinchart { 1872539b33b0SLaurent Pinchart struct adv7604_state *state = to_state(sd); 1873539b33b0SLaurent Pinchart 1874539b33b0SLaurent Pinchart if (format->pad != state->source_pad) 1875539b33b0SLaurent Pinchart return -EINVAL; 1876539b33b0SLaurent Pinchart 1877539b33b0SLaurent Pinchart adv7604_fill_format(state, &format->format); 1878539b33b0SLaurent Pinchart 1879539b33b0SLaurent Pinchart if (format->which == V4L2_SUBDEV_FORMAT_TRY) { 1880539b33b0SLaurent Pinchart struct v4l2_mbus_framefmt *fmt; 1881539b33b0SLaurent Pinchart 1882539b33b0SLaurent Pinchart fmt = v4l2_subdev_get_try_format(fh, format->pad); 1883539b33b0SLaurent Pinchart format->format.code = fmt->code; 1884539b33b0SLaurent Pinchart } else { 1885539b33b0SLaurent Pinchart format->format.code = state->format->code; 1886539b33b0SLaurent Pinchart } 1887539b33b0SLaurent Pinchart 1888539b33b0SLaurent Pinchart return 0; 1889539b33b0SLaurent Pinchart } 1890539b33b0SLaurent Pinchart 1891539b33b0SLaurent Pinchart static int adv7604_set_format(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh, 1892539b33b0SLaurent Pinchart struct v4l2_subdev_format *format) 1893539b33b0SLaurent Pinchart { 1894539b33b0SLaurent Pinchart struct adv7604_state *state = to_state(sd); 1895539b33b0SLaurent Pinchart const struct adv7604_format_info *info; 1896539b33b0SLaurent Pinchart 1897539b33b0SLaurent Pinchart if (format->pad != state->source_pad) 1898539b33b0SLaurent Pinchart return -EINVAL; 1899539b33b0SLaurent Pinchart 1900539b33b0SLaurent Pinchart info = adv7604_format_info(state, format->format.code); 1901539b33b0SLaurent Pinchart if (info == NULL) 1902539b33b0SLaurent Pinchart info = adv7604_format_info(state, V4L2_MBUS_FMT_YUYV8_2X8); 1903539b33b0SLaurent Pinchart 1904539b33b0SLaurent Pinchart adv7604_fill_format(state, &format->format); 1905539b33b0SLaurent Pinchart format->format.code = info->code; 1906539b33b0SLaurent Pinchart 1907539b33b0SLaurent Pinchart if (format->which == V4L2_SUBDEV_FORMAT_TRY) { 1908539b33b0SLaurent Pinchart struct v4l2_mbus_framefmt *fmt; 1909539b33b0SLaurent Pinchart 1910539b33b0SLaurent Pinchart fmt = v4l2_subdev_get_try_format(fh, format->pad); 1911539b33b0SLaurent Pinchart fmt->code = format->format.code; 1912539b33b0SLaurent Pinchart } else { 1913539b33b0SLaurent Pinchart state->format = info; 1914539b33b0SLaurent Pinchart adv7604_setup_format(state); 1915539b33b0SLaurent Pinchart } 1916539b33b0SLaurent Pinchart 191754450f59SHans Verkuil return 0; 191854450f59SHans Verkuil } 191954450f59SHans Verkuil 192054450f59SHans Verkuil static int adv7604_isr(struct v4l2_subdev *sd, u32 status, bool *handled) 192154450f59SHans Verkuil { 1922d42010a1SLars-Peter Clausen struct adv7604_state *state = to_state(sd); 1923d42010a1SLars-Peter Clausen const struct adv7604_chip_info *info = state->info; 1924f24d229cSMats Randgaard const u8 irq_reg_0x43 = io_read(sd, 0x43); 1925f24d229cSMats Randgaard const u8 irq_reg_0x6b = io_read(sd, 0x6b); 1926f24d229cSMats Randgaard const u8 irq_reg_0x70 = io_read(sd, 0x70); 1927f24d229cSMats Randgaard u8 fmt_change_digital; 1928f24d229cSMats Randgaard u8 fmt_change; 1929f24d229cSMats Randgaard u8 tx_5v; 1930f24d229cSMats Randgaard 1931f24d229cSMats Randgaard if (irq_reg_0x43) 1932f24d229cSMats Randgaard io_write(sd, 0x44, irq_reg_0x43); 1933f24d229cSMats Randgaard if (irq_reg_0x70) 1934f24d229cSMats Randgaard io_write(sd, 0x71, irq_reg_0x70); 1935f24d229cSMats Randgaard if (irq_reg_0x6b) 1936f24d229cSMats Randgaard io_write(sd, 0x6c, irq_reg_0x6b); 193754450f59SHans Verkuil 1938ff4f80fdSMats Randgaard v4l2_dbg(2, debug, sd, "%s: ", __func__); 1939ff4f80fdSMats Randgaard 194054450f59SHans Verkuil /* format change */ 1941f24d229cSMats Randgaard fmt_change = irq_reg_0x43 & 0x98; 1942d42010a1SLars-Peter Clausen fmt_change_digital = is_digital_input(sd) 1943d42010a1SLars-Peter Clausen ? irq_reg_0x6b & info->fmt_change_digital_mask 1944d42010a1SLars-Peter Clausen : 0; 194514d03233SMats Randgaard 194654450f59SHans Verkuil if (fmt_change || fmt_change_digital) { 194754450f59SHans Verkuil v4l2_dbg(1, debug, sd, 194825a64ac9SMats Randgaard "%s: fmt_change = 0x%x, fmt_change_digital = 0x%x\n", 194954450f59SHans Verkuil __func__, fmt_change, fmt_change_digital); 195025a64ac9SMats Randgaard 195154450f59SHans Verkuil v4l2_subdev_notify(sd, ADV7604_FMT_CHANGE, NULL); 195225a64ac9SMats Randgaard 195354450f59SHans Verkuil if (handled) 195454450f59SHans Verkuil *handled = true; 195554450f59SHans Verkuil } 1956f24d229cSMats Randgaard /* HDMI/DVI mode */ 1957f24d229cSMats Randgaard if (irq_reg_0x6b & 0x01) { 1958f24d229cSMats Randgaard v4l2_dbg(1, debug, sd, "%s: irq %s mode\n", __func__, 1959f24d229cSMats Randgaard (io_read(sd, 0x6a) & 0x01) ? "HDMI" : "DVI"); 1960f24d229cSMats Randgaard set_rgb_quantization_range(sd); 1961f24d229cSMats Randgaard if (handled) 1962f24d229cSMats Randgaard *handled = true; 1963f24d229cSMats Randgaard } 1964f24d229cSMats Randgaard 196554450f59SHans Verkuil /* tx 5v detect */ 1966d42010a1SLars-Peter Clausen tx_5v = io_read(sd, 0x70) & info->cable_det_mask; 196754450f59SHans Verkuil if (tx_5v) { 196854450f59SHans Verkuil v4l2_dbg(1, debug, sd, "%s: tx_5v: 0x%x\n", __func__, tx_5v); 196954450f59SHans Verkuil io_write(sd, 0x71, tx_5v); 197054450f59SHans Verkuil adv7604_s_detect_tx_5v_ctrl(sd); 197154450f59SHans Verkuil if (handled) 197254450f59SHans Verkuil *handled = true; 197354450f59SHans Verkuil } 197454450f59SHans Verkuil return 0; 197554450f59SHans Verkuil } 197654450f59SHans Verkuil 1977b09dfac8SHans Verkuil static int adv7604_get_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid) 197854450f59SHans Verkuil { 197954450f59SHans Verkuil struct adv7604_state *state = to_state(sd); 19804a31a93aSMats Randgaard u8 *data = NULL; 198154450f59SHans Verkuil 1982c784b1e2SLaurent Pinchart if (edid->pad > ADV7604_PAD_HDMI_PORT_D) 198354450f59SHans Verkuil return -EINVAL; 198454450f59SHans Verkuil if (edid->blocks == 0) 198554450f59SHans Verkuil return -EINVAL; 19864a31a93aSMats Randgaard if (edid->blocks > 2) 198754450f59SHans Verkuil return -EINVAL; 19884a31a93aSMats Randgaard if (edid->start_block > 1) 19894a31a93aSMats Randgaard return -EINVAL; 19904a31a93aSMats Randgaard if (edid->start_block == 1) 19914a31a93aSMats Randgaard edid->blocks = 1; 19924a31a93aSMats Randgaard 19934a31a93aSMats Randgaard if (edid->blocks > state->edid.blocks) 19944a31a93aSMats Randgaard edid->blocks = state->edid.blocks; 19954a31a93aSMats Randgaard 19964a31a93aSMats Randgaard switch (edid->pad) { 1997c784b1e2SLaurent Pinchart case ADV7604_PAD_HDMI_PORT_A: 1998c784b1e2SLaurent Pinchart case ADV7604_PAD_HDMI_PORT_B: 1999c784b1e2SLaurent Pinchart case ADV7604_PAD_HDMI_PORT_C: 2000c784b1e2SLaurent Pinchart case ADV7604_PAD_HDMI_PORT_D: 20014a31a93aSMats Randgaard if (state->edid.present & (1 << edid->pad)) 20024a31a93aSMats Randgaard data = state->edid.edid; 20034a31a93aSMats Randgaard break; 20044a31a93aSMats Randgaard default: 20054a31a93aSMats Randgaard return -EINVAL; 20064a31a93aSMats Randgaard break; 20074a31a93aSMats Randgaard } 20084a31a93aSMats Randgaard if (!data) 20094a31a93aSMats Randgaard return -ENODATA; 20104a31a93aSMats Randgaard 20114a31a93aSMats Randgaard memcpy(edid->edid, 20124a31a93aSMats Randgaard data + edid->start_block * 128, 201354450f59SHans Verkuil edid->blocks * 128); 201454450f59SHans Verkuil return 0; 201554450f59SHans Verkuil } 201654450f59SHans Verkuil 2017dd08beb9SMats Randgaard static int get_edid_spa_location(const u8 *edid) 20183e86aa85SMats Randgaard { 20193e86aa85SMats Randgaard u8 d; 20203e86aa85SMats Randgaard 20213e86aa85SMats Randgaard if ((edid[0x7e] != 1) || 20223e86aa85SMats Randgaard (edid[0x80] != 0x02) || 20233e86aa85SMats Randgaard (edid[0x81] != 0x03)) { 20243e86aa85SMats Randgaard return -1; 20253e86aa85SMats Randgaard } 20263e86aa85SMats Randgaard 20273e86aa85SMats Randgaard /* search Vendor Specific Data Block (tag 3) */ 20283e86aa85SMats Randgaard d = edid[0x82] & 0x7f; 20293e86aa85SMats Randgaard if (d > 4) { 20303e86aa85SMats Randgaard int i = 0x84; 20313e86aa85SMats Randgaard int end = 0x80 + d; 20323e86aa85SMats Randgaard 20333e86aa85SMats Randgaard do { 20343e86aa85SMats Randgaard u8 tag = edid[i] >> 5; 20353e86aa85SMats Randgaard u8 len = edid[i] & 0x1f; 20363e86aa85SMats Randgaard 20373e86aa85SMats Randgaard if ((tag == 3) && (len >= 5)) 20383e86aa85SMats Randgaard return i + 4; 20393e86aa85SMats Randgaard i += len + 1; 20403e86aa85SMats Randgaard } while (i < end); 20413e86aa85SMats Randgaard } 20423e86aa85SMats Randgaard return -1; 20433e86aa85SMats Randgaard } 20443e86aa85SMats Randgaard 2045b09dfac8SHans Verkuil static int adv7604_set_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid) 204654450f59SHans Verkuil { 204754450f59SHans Verkuil struct adv7604_state *state = to_state(sd); 2048d42010a1SLars-Peter Clausen const struct adv7604_chip_info *info = state->info; 2049dd08beb9SMats Randgaard int spa_loc; 20503e86aa85SMats Randgaard int tmp = 0; 205154450f59SHans Verkuil int err; 2052dd08beb9SMats Randgaard int i; 205354450f59SHans Verkuil 2054c784b1e2SLaurent Pinchart if (edid->pad > ADV7604_PAD_HDMI_PORT_D) 205554450f59SHans Verkuil return -EINVAL; 205654450f59SHans Verkuil if (edid->start_block != 0) 205754450f59SHans Verkuil return -EINVAL; 205854450f59SHans Verkuil if (edid->blocks == 0) { 20593e86aa85SMats Randgaard /* Disable hotplug and I2C access to EDID RAM from DDC port */ 20604a31a93aSMats Randgaard state->edid.present &= ~(1 << edid->pad); 20614a31a93aSMats Randgaard v4l2_subdev_notify(sd, ADV7604_HOTPLUG, (void *)&state->edid.present); 206222d97e56SLaurent Pinchart rep_write_clr_set(sd, info->edid_enable_reg, 0x0f, state->edid.present); 20633e86aa85SMats Randgaard 206454450f59SHans Verkuil /* Fall back to a 16:9 aspect ratio */ 206554450f59SHans Verkuil state->aspect_ratio.numerator = 16; 206654450f59SHans Verkuil state->aspect_ratio.denominator = 9; 20673e86aa85SMats Randgaard 20683e86aa85SMats Randgaard if (!state->edid.present) 20693e86aa85SMats Randgaard state->edid.blocks = 0; 20703e86aa85SMats Randgaard 20713e86aa85SMats Randgaard v4l2_dbg(2, debug, sd, "%s: clear EDID pad %d, edid.present = 0x%x\n", 20723e86aa85SMats Randgaard __func__, edid->pad, state->edid.present); 207354450f59SHans Verkuil return 0; 207454450f59SHans Verkuil } 20754a31a93aSMats Randgaard if (edid->blocks > 2) { 20764a31a93aSMats Randgaard edid->blocks = 2; 207754450f59SHans Verkuil return -E2BIG; 20784a31a93aSMats Randgaard } 20794a31a93aSMats Randgaard 2080dd08beb9SMats Randgaard v4l2_dbg(2, debug, sd, "%s: write EDID pad %d, edid.present = 0x%x\n", 2081dd08beb9SMats Randgaard __func__, edid->pad, state->edid.present); 2082dd08beb9SMats Randgaard 20833e86aa85SMats Randgaard /* Disable hotplug and I2C access to EDID RAM from DDC port */ 20844a31a93aSMats Randgaard cancel_delayed_work_sync(&state->delayed_work_enable_hotplug); 20853e86aa85SMats Randgaard v4l2_subdev_notify(sd, ADV7604_HOTPLUG, (void *)&tmp); 208622d97e56SLaurent Pinchart rep_write_clr_set(sd, info->edid_enable_reg, 0x0f, 0x00); 20873e86aa85SMats Randgaard 2088dd08beb9SMats Randgaard spa_loc = get_edid_spa_location(edid->edid); 2089dd08beb9SMats Randgaard if (spa_loc < 0) 2090dd08beb9SMats Randgaard spa_loc = 0xc0; /* Default value [REF_02, p. 116] */ 2091dd08beb9SMats Randgaard 20923e86aa85SMats Randgaard switch (edid->pad) { 2093c784b1e2SLaurent Pinchart case ADV7604_PAD_HDMI_PORT_A: 2094dd08beb9SMats Randgaard state->spa_port_a[0] = edid->edid[spa_loc]; 2095dd08beb9SMats Randgaard state->spa_port_a[1] = edid->edid[spa_loc + 1]; 20963e86aa85SMats Randgaard break; 2097c784b1e2SLaurent Pinchart case ADV7604_PAD_HDMI_PORT_B: 2098dd08beb9SMats Randgaard rep_write(sd, 0x70, edid->edid[spa_loc]); 2099dd08beb9SMats Randgaard rep_write(sd, 0x71, edid->edid[spa_loc + 1]); 21003e86aa85SMats Randgaard break; 2101c784b1e2SLaurent Pinchart case ADV7604_PAD_HDMI_PORT_C: 2102dd08beb9SMats Randgaard rep_write(sd, 0x72, edid->edid[spa_loc]); 2103dd08beb9SMats Randgaard rep_write(sd, 0x73, edid->edid[spa_loc + 1]); 21043e86aa85SMats Randgaard break; 2105c784b1e2SLaurent Pinchart case ADV7604_PAD_HDMI_PORT_D: 2106dd08beb9SMats Randgaard rep_write(sd, 0x74, edid->edid[spa_loc]); 2107dd08beb9SMats Randgaard rep_write(sd, 0x75, edid->edid[spa_loc + 1]); 21083e86aa85SMats Randgaard break; 2109dd08beb9SMats Randgaard default: 2110dd08beb9SMats Randgaard return -EINVAL; 21113e86aa85SMats Randgaard } 2112d42010a1SLars-Peter Clausen 2113d42010a1SLars-Peter Clausen if (info->type == ADV7604) { 2114dd08beb9SMats Randgaard rep_write(sd, 0x76, spa_loc & 0xff); 211522d97e56SLaurent Pinchart rep_write_clr_set(sd, 0x77, 0x40, (spa_loc & 0x100) >> 2); 2116d42010a1SLars-Peter Clausen } else { 2117d42010a1SLars-Peter Clausen /* FIXME: Where is the SPA location LSB register ? */ 211822d97e56SLaurent Pinchart rep_write_clr_set(sd, 0x71, 0x01, (spa_loc & 0x100) >> 8); 2119d42010a1SLars-Peter Clausen } 21203e86aa85SMats Randgaard 2121dd08beb9SMats Randgaard edid->edid[spa_loc] = state->spa_port_a[0]; 2122dd08beb9SMats Randgaard edid->edid[spa_loc + 1] = state->spa_port_a[1]; 21234a31a93aSMats Randgaard 21244a31a93aSMats Randgaard memcpy(state->edid.edid, edid->edid, 128 * edid->blocks); 21254a31a93aSMats Randgaard state->edid.blocks = edid->blocks; 212654450f59SHans Verkuil state->aspect_ratio = v4l2_calc_aspect_ratio(edid->edid[0x15], 212754450f59SHans Verkuil edid->edid[0x16]); 21283e86aa85SMats Randgaard state->edid.present |= 1 << edid->pad; 21294a31a93aSMats Randgaard 21304a31a93aSMats Randgaard err = edid_write_block(sd, 128 * edid->blocks, state->edid.edid); 21314a31a93aSMats Randgaard if (err < 0) { 21323e86aa85SMats Randgaard v4l2_err(sd, "error %d writing edid pad %d\n", err, edid->pad); 213354450f59SHans Verkuil return err; 213454450f59SHans Verkuil } 213554450f59SHans Verkuil 2136dd08beb9SMats Randgaard /* adv7604 calculates the checksums and enables I2C access to internal 2137dd08beb9SMats Randgaard EDID RAM from DDC port. */ 213822d97e56SLaurent Pinchart rep_write_clr_set(sd, info->edid_enable_reg, 0x0f, state->edid.present); 2139dd08beb9SMats Randgaard 2140dd08beb9SMats Randgaard for (i = 0; i < 1000; i++) { 2141d42010a1SLars-Peter Clausen if (rep_read(sd, info->edid_status_reg) & state->edid.present) 2142dd08beb9SMats Randgaard break; 2143dd08beb9SMats Randgaard mdelay(1); 2144dd08beb9SMats Randgaard } 2145dd08beb9SMats Randgaard if (i == 1000) { 2146dd08beb9SMats Randgaard v4l2_err(sd, "error enabling edid (0x%x)\n", state->edid.present); 2147dd08beb9SMats Randgaard return -EIO; 2148dd08beb9SMats Randgaard } 2149dd08beb9SMats Randgaard 2150dd08beb9SMats Randgaard 21514a31a93aSMats Randgaard /* enable hotplug after 100 ms */ 21524a31a93aSMats Randgaard queue_delayed_work(state->work_queues, 21534a31a93aSMats Randgaard &state->delayed_work_enable_hotplug, HZ / 10); 21544a31a93aSMats Randgaard return 0; 21554a31a93aSMats Randgaard } 21564a31a93aSMats Randgaard 215754450f59SHans Verkuil /*********** avi info frame CEA-861-E **************/ 215854450f59SHans Verkuil 215954450f59SHans Verkuil static void print_avi_infoframe(struct v4l2_subdev *sd) 216054450f59SHans Verkuil { 216154450f59SHans Verkuil int i; 216254450f59SHans Verkuil u8 buf[14]; 216354450f59SHans Verkuil u8 avi_len; 216454450f59SHans Verkuil u8 avi_ver; 216554450f59SHans Verkuil 2166bb88f325SMartin Bugge if (!is_hdmi(sd)) { 216754450f59SHans Verkuil v4l2_info(sd, "receive DVI-D signal (AVI infoframe not supported)\n"); 216854450f59SHans Verkuil return; 216954450f59SHans Verkuil } 217054450f59SHans Verkuil if (!(io_read(sd, 0x60) & 0x01)) { 217154450f59SHans Verkuil v4l2_info(sd, "AVI infoframe not received\n"); 217254450f59SHans Verkuil return; 217354450f59SHans Verkuil } 217454450f59SHans Verkuil 217554450f59SHans Verkuil if (io_read(sd, 0x83) & 0x01) { 217654450f59SHans Verkuil v4l2_info(sd, "AVI infoframe checksum error has occurred earlier\n"); 217754450f59SHans Verkuil io_write(sd, 0x85, 0x01); /* clear AVI_INF_CKS_ERR_RAW */ 217854450f59SHans Verkuil if (io_read(sd, 0x83) & 0x01) { 217954450f59SHans Verkuil v4l2_info(sd, "AVI infoframe checksum error still present\n"); 218054450f59SHans Verkuil io_write(sd, 0x85, 0x01); /* clear AVI_INF_CKS_ERR_RAW */ 218154450f59SHans Verkuil } 218254450f59SHans Verkuil } 218354450f59SHans Verkuil 218454450f59SHans Verkuil avi_len = infoframe_read(sd, 0xe2); 218554450f59SHans Verkuil avi_ver = infoframe_read(sd, 0xe1); 218654450f59SHans Verkuil v4l2_info(sd, "AVI infoframe version %d (%d byte)\n", 218754450f59SHans Verkuil avi_ver, avi_len); 218854450f59SHans Verkuil 218954450f59SHans Verkuil if (avi_ver != 0x02) 219054450f59SHans Verkuil return; 219154450f59SHans Verkuil 219254450f59SHans Verkuil for (i = 0; i < 14; i++) 219354450f59SHans Verkuil buf[i] = infoframe_read(sd, i); 219454450f59SHans Verkuil 219554450f59SHans Verkuil v4l2_info(sd, 219654450f59SHans Verkuil "\t%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n", 219754450f59SHans Verkuil buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6], buf[7], 219854450f59SHans Verkuil buf[8], buf[9], buf[10], buf[11], buf[12], buf[13]); 219954450f59SHans Verkuil } 220054450f59SHans Verkuil 220154450f59SHans Verkuil static int adv7604_log_status(struct v4l2_subdev *sd) 220254450f59SHans Verkuil { 220354450f59SHans Verkuil struct adv7604_state *state = to_state(sd); 2204d42010a1SLars-Peter Clausen const struct adv7604_chip_info *info = state->info; 220554450f59SHans Verkuil struct v4l2_dv_timings timings; 220654450f59SHans Verkuil struct stdi_readback stdi; 220754450f59SHans Verkuil u8 reg_io_0x02 = io_read(sd, 0x02); 22084a2ccdd2SLaurent Pinchart u8 edid_enabled; 22094a2ccdd2SLaurent Pinchart u8 cable_det; 221054450f59SHans Verkuil 2211f216ccb3SLars-Peter Clausen static const char * const csc_coeff_sel_rb[16] = { 221254450f59SHans Verkuil "bypassed", "YPbPr601 -> RGB", "reserved", "YPbPr709 -> RGB", 221354450f59SHans Verkuil "reserved", "RGB -> YPbPr601", "reserved", "RGB -> YPbPr709", 221454450f59SHans Verkuil "reserved", "YPbPr709 -> YPbPr601", "YPbPr601 -> YPbPr709", 221554450f59SHans Verkuil "reserved", "reserved", "reserved", "reserved", "manual" 221654450f59SHans Verkuil }; 2217f216ccb3SLars-Peter Clausen static const char * const input_color_space_txt[16] = { 221854450f59SHans Verkuil "RGB limited range (16-235)", "RGB full range (0-255)", 221954450f59SHans Verkuil "YCbCr Bt.601 (16-235)", "YCbCr Bt.709 (16-235)", 22209833239eSMats Randgaard "xvYCC Bt.601", "xvYCC Bt.709", 222154450f59SHans Verkuil "YCbCr Bt.601 (0-255)", "YCbCr Bt.709 (0-255)", 222254450f59SHans Verkuil "invalid", "invalid", "invalid", "invalid", "invalid", 222354450f59SHans Verkuil "invalid", "invalid", "automatic" 222454450f59SHans Verkuil }; 2225f216ccb3SLars-Peter Clausen static const char * const rgb_quantization_range_txt[] = { 222654450f59SHans Verkuil "Automatic", 222754450f59SHans Verkuil "RGB limited range (16-235)", 222854450f59SHans Verkuil "RGB full range (0-255)", 222954450f59SHans Verkuil }; 2230f216ccb3SLars-Peter Clausen static const char * const deep_color_mode_txt[4] = { 2231bb88f325SMartin Bugge "8-bits per channel", 2232bb88f325SMartin Bugge "10-bits per channel", 2233bb88f325SMartin Bugge "12-bits per channel", 2234bb88f325SMartin Bugge "16-bits per channel (not supported)" 2235bb88f325SMartin Bugge }; 223654450f59SHans Verkuil 223754450f59SHans Verkuil v4l2_info(sd, "-----Chip status-----\n"); 223854450f59SHans Verkuil v4l2_info(sd, "Chip power: %s\n", no_power(sd) ? "off" : "on"); 2239d42010a1SLars-Peter Clausen edid_enabled = rep_read(sd, info->edid_status_reg); 22404a31a93aSMats Randgaard v4l2_info(sd, "EDID enabled port A: %s, B: %s, C: %s, D: %s\n", 22414a2ccdd2SLaurent Pinchart ((edid_enabled & 0x01) ? "Yes" : "No"), 22424a2ccdd2SLaurent Pinchart ((edid_enabled & 0x02) ? "Yes" : "No"), 22434a2ccdd2SLaurent Pinchart ((edid_enabled & 0x04) ? "Yes" : "No"), 22444a2ccdd2SLaurent Pinchart ((edid_enabled & 0x08) ? "Yes" : "No")); 224554450f59SHans Verkuil v4l2_info(sd, "CEC: %s\n", !!(cec_read(sd, 0x2a) & 0x01) ? 224654450f59SHans Verkuil "enabled" : "disabled"); 224754450f59SHans Verkuil 224854450f59SHans Verkuil v4l2_info(sd, "-----Signal status-----\n"); 2249d42010a1SLars-Peter Clausen cable_det = info->read_cable_det(sd); 22504a31a93aSMats Randgaard v4l2_info(sd, "Cable detected (+5V power) port A: %s, B: %s, C: %s, D: %s\n", 2251d42010a1SLars-Peter Clausen ((cable_det & 0x01) ? "Yes" : "No"), 2252d42010a1SLars-Peter Clausen ((cable_det & 0x02) ? "Yes" : "No"), 22534a2ccdd2SLaurent Pinchart ((cable_det & 0x04) ? "Yes" : "No"), 2254d42010a1SLars-Peter Clausen ((cable_det & 0x08) ? "Yes" : "No")); 225554450f59SHans Verkuil v4l2_info(sd, "TMDS signal detected: %s\n", 225654450f59SHans Verkuil no_signal_tmds(sd) ? "false" : "true"); 225754450f59SHans Verkuil v4l2_info(sd, "TMDS signal locked: %s\n", 225854450f59SHans Verkuil no_lock_tmds(sd) ? "false" : "true"); 225954450f59SHans Verkuil v4l2_info(sd, "SSPD locked: %s\n", no_lock_sspd(sd) ? "false" : "true"); 226054450f59SHans Verkuil v4l2_info(sd, "STDI locked: %s\n", no_lock_stdi(sd) ? "false" : "true"); 226154450f59SHans Verkuil v4l2_info(sd, "CP locked: %s\n", no_lock_cp(sd) ? "false" : "true"); 226254450f59SHans Verkuil v4l2_info(sd, "CP free run: %s\n", 226354450f59SHans Verkuil (!!(cp_read(sd, 0xff) & 0x10) ? "on" : "off")); 2264ccbd5bc4SHans Verkuil v4l2_info(sd, "Prim-mode = 0x%x, video std = 0x%x, v_freq = 0x%x\n", 2265ccbd5bc4SHans Verkuil io_read(sd, 0x01) & 0x0f, io_read(sd, 0x00) & 0x3f, 2266ccbd5bc4SHans Verkuil (io_read(sd, 0x01) & 0x70) >> 4); 226754450f59SHans Verkuil 226854450f59SHans Verkuil v4l2_info(sd, "-----Video Timings-----\n"); 226954450f59SHans Verkuil if (read_stdi(sd, &stdi)) 227054450f59SHans Verkuil v4l2_info(sd, "STDI: not locked\n"); 227154450f59SHans Verkuil else 227254450f59SHans Verkuil v4l2_info(sd, "STDI: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %s, %chsync, %cvsync\n", 227354450f59SHans Verkuil stdi.lcf, stdi.bl, stdi.lcvs, 227454450f59SHans Verkuil stdi.interlaced ? "interlaced" : "progressive", 227554450f59SHans Verkuil stdi.hs_pol, stdi.vs_pol); 227654450f59SHans Verkuil if (adv7604_query_dv_timings(sd, &timings)) 227754450f59SHans Verkuil v4l2_info(sd, "No video detected\n"); 227854450f59SHans Verkuil else 227911d034c8SHans Verkuil v4l2_print_dv_timings(sd->name, "Detected format: ", 228011d034c8SHans Verkuil &timings, true); 228111d034c8SHans Verkuil v4l2_print_dv_timings(sd->name, "Configured format: ", 228211d034c8SHans Verkuil &state->timings, true); 228354450f59SHans Verkuil 228476eb2d30SMats Randgaard if (no_signal(sd)) 228576eb2d30SMats Randgaard return 0; 228676eb2d30SMats Randgaard 228754450f59SHans Verkuil v4l2_info(sd, "-----Color space-----\n"); 228854450f59SHans Verkuil v4l2_info(sd, "RGB quantization range ctrl: %s\n", 228954450f59SHans Verkuil rgb_quantization_range_txt[state->rgb_quantization_range]); 229054450f59SHans Verkuil v4l2_info(sd, "Input color space: %s\n", 229154450f59SHans Verkuil input_color_space_txt[reg_io_0x02 >> 4]); 229254450f59SHans Verkuil v4l2_info(sd, "Output color space: %s %s, saturator %s\n", 229354450f59SHans Verkuil (reg_io_0x02 & 0x02) ? "RGB" : "YCbCr", 229454450f59SHans Verkuil (reg_io_0x02 & 0x04) ? "(16-235)" : "(0-255)", 229554450f59SHans Verkuil ((reg_io_0x02 & 0x04) ^ (reg_io_0x02 & 0x01)) ? 229654450f59SHans Verkuil "enabled" : "disabled"); 229754450f59SHans Verkuil v4l2_info(sd, "Color space conversion: %s\n", 229854450f59SHans Verkuil csc_coeff_sel_rb[cp_read(sd, 0xfc) >> 4]); 229954450f59SHans Verkuil 23004a31a93aSMats Randgaard if (!is_digital_input(sd)) 230176eb2d30SMats Randgaard return 0; 230276eb2d30SMats Randgaard 230376eb2d30SMats Randgaard v4l2_info(sd, "-----%s status-----\n", is_hdmi(sd) ? "HDMI" : "DVI-D"); 23044a31a93aSMats Randgaard v4l2_info(sd, "Digital video port selected: %c\n", 23054a31a93aSMats Randgaard (hdmi_read(sd, 0x00) & 0x03) + 'A'); 23064a31a93aSMats Randgaard v4l2_info(sd, "HDCP encrypted content: %s\n", 23074a31a93aSMats Randgaard (hdmi_read(sd, 0x05) & 0x40) ? "true" : "false"); 230876eb2d30SMats Randgaard v4l2_info(sd, "HDCP keys read: %s%s\n", 230976eb2d30SMats Randgaard (hdmi_read(sd, 0x04) & 0x20) ? "yes" : "no", 231076eb2d30SMats Randgaard (hdmi_read(sd, 0x04) & 0x10) ? "ERROR" : ""); 231176eb2d30SMats Randgaard if (!is_hdmi(sd)) { 231276eb2d30SMats Randgaard bool audio_pll_locked = hdmi_read(sd, 0x04) & 0x01; 231376eb2d30SMats Randgaard bool audio_sample_packet_detect = hdmi_read(sd, 0x18) & 0x01; 231476eb2d30SMats Randgaard bool audio_mute = io_read(sd, 0x65) & 0x40; 231576eb2d30SMats Randgaard 231676eb2d30SMats Randgaard v4l2_info(sd, "Audio: pll %s, samples %s, %s\n", 231776eb2d30SMats Randgaard audio_pll_locked ? "locked" : "not locked", 231876eb2d30SMats Randgaard audio_sample_packet_detect ? "detected" : "not detected", 231976eb2d30SMats Randgaard audio_mute ? "muted" : "enabled"); 232076eb2d30SMats Randgaard if (audio_pll_locked && audio_sample_packet_detect) { 232176eb2d30SMats Randgaard v4l2_info(sd, "Audio format: %s\n", 232276eb2d30SMats Randgaard (hdmi_read(sd, 0x07) & 0x20) ? "multi-channel" : "stereo"); 232376eb2d30SMats Randgaard } 232476eb2d30SMats Randgaard v4l2_info(sd, "Audio CTS: %u\n", (hdmi_read(sd, 0x5b) << 12) + 232576eb2d30SMats Randgaard (hdmi_read(sd, 0x5c) << 8) + 232676eb2d30SMats Randgaard (hdmi_read(sd, 0x5d) & 0xf0)); 232776eb2d30SMats Randgaard v4l2_info(sd, "Audio N: %u\n", ((hdmi_read(sd, 0x5d) & 0x0f) << 16) + 232876eb2d30SMats Randgaard (hdmi_read(sd, 0x5e) << 8) + 232976eb2d30SMats Randgaard hdmi_read(sd, 0x5f)); 233076eb2d30SMats Randgaard v4l2_info(sd, "AV Mute: %s\n", (hdmi_read(sd, 0x04) & 0x40) ? "on" : "off"); 233176eb2d30SMats Randgaard 233276eb2d30SMats Randgaard v4l2_info(sd, "Deep color mode: %s\n", deep_color_mode_txt[(hdmi_read(sd, 0x0b) & 0x60) >> 5]); 233376eb2d30SMats Randgaard 233454450f59SHans Verkuil print_avi_infoframe(sd); 233554450f59SHans Verkuil } 233654450f59SHans Verkuil 233754450f59SHans Verkuil return 0; 233854450f59SHans Verkuil } 233954450f59SHans Verkuil 234054450f59SHans Verkuil /* ----------------------------------------------------------------------- */ 234154450f59SHans Verkuil 234254450f59SHans Verkuil static const struct v4l2_ctrl_ops adv7604_ctrl_ops = { 234354450f59SHans Verkuil .s_ctrl = adv7604_s_ctrl, 234454450f59SHans Verkuil }; 234554450f59SHans Verkuil 234654450f59SHans Verkuil static const struct v4l2_subdev_core_ops adv7604_core_ops = { 234754450f59SHans Verkuil .log_status = adv7604_log_status, 234854450f59SHans Verkuil .interrupt_service_routine = adv7604_isr, 234954450f59SHans Verkuil #ifdef CONFIG_VIDEO_ADV_DEBUG 235054450f59SHans Verkuil .g_register = adv7604_g_register, 235154450f59SHans Verkuil .s_register = adv7604_s_register, 235254450f59SHans Verkuil #endif 235354450f59SHans Verkuil }; 235454450f59SHans Verkuil 235554450f59SHans Verkuil static const struct v4l2_subdev_video_ops adv7604_video_ops = { 235654450f59SHans Verkuil .s_routing = adv7604_s_routing, 235754450f59SHans Verkuil .g_input_status = adv7604_g_input_status, 235854450f59SHans Verkuil .s_dv_timings = adv7604_s_dv_timings, 235954450f59SHans Verkuil .g_dv_timings = adv7604_g_dv_timings, 236054450f59SHans Verkuil .query_dv_timings = adv7604_query_dv_timings, 236154450f59SHans Verkuil }; 236254450f59SHans Verkuil 236354450f59SHans Verkuil static const struct v4l2_subdev_pad_ops adv7604_pad_ops = { 2364539b33b0SLaurent Pinchart .enum_mbus_code = adv7604_enum_mbus_code, 2365539b33b0SLaurent Pinchart .get_fmt = adv7604_get_format, 2366539b33b0SLaurent Pinchart .set_fmt = adv7604_set_format, 236754450f59SHans Verkuil .get_edid = adv7604_get_edid, 236854450f59SHans Verkuil .set_edid = adv7604_set_edid, 23697515e096SLaurent Pinchart .dv_timings_cap = adv7604_dv_timings_cap, 2370afec5599SLaurent Pinchart .enum_dv_timings = adv7604_enum_dv_timings, 237154450f59SHans Verkuil }; 237254450f59SHans Verkuil 237354450f59SHans Verkuil static const struct v4l2_subdev_ops adv7604_ops = { 237454450f59SHans Verkuil .core = &adv7604_core_ops, 237554450f59SHans Verkuil .video = &adv7604_video_ops, 237654450f59SHans Verkuil .pad = &adv7604_pad_ops, 237754450f59SHans Verkuil }; 237854450f59SHans Verkuil 237954450f59SHans Verkuil /* -------------------------- custom ctrls ---------------------------------- */ 238054450f59SHans Verkuil 238154450f59SHans Verkuil static const struct v4l2_ctrl_config adv7604_ctrl_analog_sampling_phase = { 238254450f59SHans Verkuil .ops = &adv7604_ctrl_ops, 238354450f59SHans Verkuil .id = V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE, 238454450f59SHans Verkuil .name = "Analog Sampling Phase", 238554450f59SHans Verkuil .type = V4L2_CTRL_TYPE_INTEGER, 238654450f59SHans Verkuil .min = 0, 238754450f59SHans Verkuil .max = 0x1f, 238854450f59SHans Verkuil .step = 1, 238954450f59SHans Verkuil .def = 0, 239054450f59SHans Verkuil }; 239154450f59SHans Verkuil 239254450f59SHans Verkuil static const struct v4l2_ctrl_config adv7604_ctrl_free_run_color_manual = { 239354450f59SHans Verkuil .ops = &adv7604_ctrl_ops, 239454450f59SHans Verkuil .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL, 239554450f59SHans Verkuil .name = "Free Running Color, Manual", 239654450f59SHans Verkuil .type = V4L2_CTRL_TYPE_BOOLEAN, 239754450f59SHans Verkuil .min = false, 239854450f59SHans Verkuil .max = true, 239954450f59SHans Verkuil .step = 1, 240054450f59SHans Verkuil .def = false, 240154450f59SHans Verkuil }; 240254450f59SHans Verkuil 240354450f59SHans Verkuil static const struct v4l2_ctrl_config adv7604_ctrl_free_run_color = { 240454450f59SHans Verkuil .ops = &adv7604_ctrl_ops, 240554450f59SHans Verkuil .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR, 240654450f59SHans Verkuil .name = "Free Running Color", 240754450f59SHans Verkuil .type = V4L2_CTRL_TYPE_INTEGER, 240854450f59SHans Verkuil .min = 0x0, 240954450f59SHans Verkuil .max = 0xffffff, 241054450f59SHans Verkuil .step = 0x1, 241154450f59SHans Verkuil .def = 0x0, 241254450f59SHans Verkuil }; 241354450f59SHans Verkuil 241454450f59SHans Verkuil /* ----------------------------------------------------------------------- */ 241554450f59SHans Verkuil 241654450f59SHans Verkuil static int adv7604_core_init(struct v4l2_subdev *sd) 241754450f59SHans Verkuil { 241854450f59SHans Verkuil struct adv7604_state *state = to_state(sd); 2419d42010a1SLars-Peter Clausen const struct adv7604_chip_info *info = state->info; 242054450f59SHans Verkuil struct adv7604_platform_data *pdata = &state->pdata; 242154450f59SHans Verkuil 242254450f59SHans Verkuil hdmi_write(sd, 0x48, 242354450f59SHans Verkuil (pdata->disable_pwrdnb ? 0x80 : 0) | 242454450f59SHans Verkuil (pdata->disable_cable_det_rst ? 0x40 : 0)); 242554450f59SHans Verkuil 242654450f59SHans Verkuil disable_input(sd); 242754450f59SHans Verkuil 242854450f59SHans Verkuil /* power */ 242954450f59SHans Verkuil io_write(sd, 0x0c, 0x42); /* Power up part and power down VDP */ 243054450f59SHans Verkuil io_write(sd, 0x0b, 0x44); /* Power down ESDP block */ 243154450f59SHans Verkuil cp_write(sd, 0xcf, 0x01); /* Power down macrovision */ 243254450f59SHans Verkuil 243354450f59SHans Verkuil /* video format */ 243422d97e56SLaurent Pinchart io_write_clr_set(sd, 0x02, 0x0f, 243554450f59SHans Verkuil pdata->alt_gamma << 3 | 243654450f59SHans Verkuil pdata->op_656_range << 2 | 243754450f59SHans Verkuil pdata->alt_data_sat << 0); 243822d97e56SLaurent Pinchart io_write_clr_set(sd, 0x05, 0x0e, pdata->blank_data << 3 | 243954450f59SHans Verkuil pdata->insert_av_codes << 2 | 2440539b33b0SLaurent Pinchart pdata->replicate_av_codes << 1); 2441539b33b0SLaurent Pinchart adv7604_setup_format(state); 244254450f59SHans Verkuil 244354450f59SHans Verkuil cp_write(sd, 0x69, 0x30); /* Enable CP CSC */ 244498908696SMartin Bugge 244598908696SMartin Bugge /* VS, HS polarities */ 244698908696SMartin Bugge io_write(sd, 0x06, 0xa0 | pdata->inv_vs_pol << 2 | pdata->inv_hs_pol << 1); 2447f31b62e1SMikhail Khelik 2448f31b62e1SMikhail Khelik /* Adjust drive strength */ 2449f31b62e1SMikhail Khelik io_write(sd, 0x14, 0x40 | pdata->dr_str_data << 4 | 2450f31b62e1SMikhail Khelik pdata->dr_str_clk << 2 | 2451f31b62e1SMikhail Khelik pdata->dr_str_sync); 2452f31b62e1SMikhail Khelik 245354450f59SHans Verkuil cp_write(sd, 0xba, (pdata->hdmi_free_run_mode << 1) | 0x01); /* HDMI free run */ 245454450f59SHans Verkuil cp_write(sd, 0xf3, 0xdc); /* Low threshold to enter/exit free run mode */ 245554450f59SHans Verkuil cp_write(sd, 0xf9, 0x23); /* STDI ch. 1 - LCVS change threshold - 245680939647SHans Verkuil ADI recommended setting [REF_01, c. 2.3.3] */ 245754450f59SHans Verkuil cp_write(sd, 0x45, 0x23); /* STDI ch. 2 - LCVS change threshold - 245880939647SHans Verkuil ADI recommended setting [REF_01, c. 2.3.3] */ 245954450f59SHans Verkuil cp_write(sd, 0xc9, 0x2d); /* use prim_mode and vid_std as free run resolution 246054450f59SHans Verkuil for digital formats */ 246154450f59SHans Verkuil 24625474b983SMats Randgaard /* HDMI audio */ 246322d97e56SLaurent Pinchart hdmi_write_clr_set(sd, 0x15, 0x03, 0x03); /* Mute on FIFO over-/underflow [REF_01, c. 1.2.18] */ 246422d97e56SLaurent Pinchart hdmi_write_clr_set(sd, 0x1a, 0x0e, 0x08); /* Wait 1 s before unmute */ 246522d97e56SLaurent Pinchart hdmi_write_clr_set(sd, 0x68, 0x06, 0x06); /* FIFO reset on over-/underflow [REF_01, c. 1.2.19] */ 24665474b983SMats Randgaard 246754450f59SHans Verkuil /* TODO from platform data */ 246854450f59SHans Verkuil afe_write(sd, 0xb5, 0x01); /* Setting MCLK to 256Fs */ 246954450f59SHans Verkuil 2470d42010a1SLars-Peter Clausen if (adv7604_has_afe(state)) { 247154450f59SHans Verkuil afe_write(sd, 0x02, pdata->ain_sel); /* Select analog input muxing mode */ 247222d97e56SLaurent Pinchart io_write_clr_set(sd, 0x30, 1 << 4, pdata->output_bus_lsb_to_msb << 4); 2473d42010a1SLars-Peter Clausen } 247454450f59SHans Verkuil 247554450f59SHans Verkuil /* interrupts */ 2476d42010a1SLars-Peter Clausen io_write(sd, 0x40, 0xc0 | pdata->int1_config); /* Configure INT1 */ 247754450f59SHans Verkuil io_write(sd, 0x46, 0x98); /* Enable SSPD, STDI and CP unlocked interrupts */ 2478d42010a1SLars-Peter Clausen io_write(sd, 0x6e, info->fmt_change_digital_mask); /* Enable V_LOCKED and DE_REGEN_LCK interrupts */ 2479d42010a1SLars-Peter Clausen io_write(sd, 0x73, info->cable_det_mask); /* Enable cable detection (+5v) interrupts */ 2480d42010a1SLars-Peter Clausen info->setup_irqs(sd); 248154450f59SHans Verkuil 248254450f59SHans Verkuil return v4l2_ctrl_handler_setup(sd->ctrl_handler); 248354450f59SHans Verkuil } 248454450f59SHans Verkuil 2485d42010a1SLars-Peter Clausen static void adv7604_setup_irqs(struct v4l2_subdev *sd) 2486d42010a1SLars-Peter Clausen { 2487d42010a1SLars-Peter Clausen io_write(sd, 0x41, 0xd7); /* STDI irq for any change, disable INT2 */ 2488d42010a1SLars-Peter Clausen } 2489d42010a1SLars-Peter Clausen 2490d42010a1SLars-Peter Clausen static void adv7611_setup_irqs(struct v4l2_subdev *sd) 2491d42010a1SLars-Peter Clausen { 2492d42010a1SLars-Peter Clausen io_write(sd, 0x41, 0xd0); /* STDI irq for any change, disable INT2 */ 2493d42010a1SLars-Peter Clausen } 2494d42010a1SLars-Peter Clausen 249554450f59SHans Verkuil static void adv7604_unregister_clients(struct adv7604_state *state) 249654450f59SHans Verkuil { 249705cacb17SLaurent Pinchart unsigned int i; 249805cacb17SLaurent Pinchart 249905cacb17SLaurent Pinchart for (i = 1; i < ARRAY_SIZE(state->i2c_clients); ++i) { 250005cacb17SLaurent Pinchart if (state->i2c_clients[i]) 250105cacb17SLaurent Pinchart i2c_unregister_device(state->i2c_clients[i]); 250205cacb17SLaurent Pinchart } 250354450f59SHans Verkuil } 250454450f59SHans Verkuil 250554450f59SHans Verkuil static struct i2c_client *adv7604_dummy_client(struct v4l2_subdev *sd, 250654450f59SHans Verkuil u8 addr, u8 io_reg) 250754450f59SHans Verkuil { 250854450f59SHans Verkuil struct i2c_client *client = v4l2_get_subdevdata(sd); 250954450f59SHans Verkuil 251054450f59SHans Verkuil if (addr) 251154450f59SHans Verkuil io_write(sd, io_reg, addr << 1); 251254450f59SHans Verkuil return i2c_new_dummy(client->adapter, io_read(sd, io_reg) >> 1); 251354450f59SHans Verkuil } 251454450f59SHans Verkuil 2515d42010a1SLars-Peter Clausen static const struct adv7604_reg_seq adv7604_recommended_settings_afe[] = { 2516d42010a1SLars-Peter Clausen /* reset ADI recommended settings for HDMI: */ 2517d42010a1SLars-Peter Clausen /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 4. */ 2518d42010a1SLars-Peter Clausen { ADV7604_REG(ADV7604_PAGE_HDMI, 0x0d), 0x04 }, /* HDMI filter optimization */ 2519d42010a1SLars-Peter Clausen { ADV7604_REG(ADV7604_PAGE_HDMI, 0x0d), 0x04 }, /* HDMI filter optimization */ 2520d42010a1SLars-Peter Clausen { ADV7604_REG(ADV7604_PAGE_HDMI, 0x3d), 0x00 }, /* DDC bus active pull-up control */ 2521d42010a1SLars-Peter Clausen { ADV7604_REG(ADV7604_PAGE_HDMI, 0x3e), 0x74 }, /* TMDS PLL optimization */ 2522d42010a1SLars-Peter Clausen { ADV7604_REG(ADV7604_PAGE_HDMI, 0x4e), 0x3b }, /* TMDS PLL optimization */ 2523d42010a1SLars-Peter Clausen { ADV7604_REG(ADV7604_PAGE_HDMI, 0x57), 0x74 }, /* TMDS PLL optimization */ 2524d42010a1SLars-Peter Clausen { ADV7604_REG(ADV7604_PAGE_HDMI, 0x58), 0x63 }, /* TMDS PLL optimization */ 2525d42010a1SLars-Peter Clausen { ADV7604_REG(ADV7604_PAGE_HDMI, 0x8d), 0x18 }, /* equaliser */ 2526d42010a1SLars-Peter Clausen { ADV7604_REG(ADV7604_PAGE_HDMI, 0x8e), 0x34 }, /* equaliser */ 2527d42010a1SLars-Peter Clausen { ADV7604_REG(ADV7604_PAGE_HDMI, 0x93), 0x88 }, /* equaliser */ 2528d42010a1SLars-Peter Clausen { ADV7604_REG(ADV7604_PAGE_HDMI, 0x94), 0x2e }, /* equaliser */ 2529d42010a1SLars-Peter Clausen { ADV7604_REG(ADV7604_PAGE_HDMI, 0x96), 0x00 }, /* enable automatic EQ changing */ 2530d42010a1SLars-Peter Clausen 2531d42010a1SLars-Peter Clausen /* set ADI recommended settings for digitizer */ 2532d42010a1SLars-Peter Clausen /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 17. */ 2533d42010a1SLars-Peter Clausen { ADV7604_REG(ADV7604_PAGE_AFE, 0x12), 0x7b }, /* ADC noise shaping filter controls */ 2534d42010a1SLars-Peter Clausen { ADV7604_REG(ADV7604_PAGE_AFE, 0x0c), 0x1f }, /* CP core gain controls */ 2535d42010a1SLars-Peter Clausen { ADV7604_REG(ADV7604_PAGE_CP, 0x3e), 0x04 }, /* CP core pre-gain control */ 2536d42010a1SLars-Peter Clausen { ADV7604_REG(ADV7604_PAGE_CP, 0xc3), 0x39 }, /* CP coast control. Graphics mode */ 2537d42010a1SLars-Peter Clausen { ADV7604_REG(ADV7604_PAGE_CP, 0x40), 0x5c }, /* CP core pre-gain control. Graphics mode */ 2538d42010a1SLars-Peter Clausen 2539d42010a1SLars-Peter Clausen { ADV7604_REG_SEQ_TERM, 0 }, 2540d42010a1SLars-Peter Clausen }; 2541d42010a1SLars-Peter Clausen 2542d42010a1SLars-Peter Clausen static const struct adv7604_reg_seq adv7604_recommended_settings_hdmi[] = { 2543d42010a1SLars-Peter Clausen /* set ADI recommended settings for HDMI: */ 2544d42010a1SLars-Peter Clausen /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 4. */ 2545d42010a1SLars-Peter Clausen { ADV7604_REG(ADV7604_PAGE_HDMI, 0x0d), 0x84 }, /* HDMI filter optimization */ 2546d42010a1SLars-Peter Clausen { ADV7604_REG(ADV7604_PAGE_HDMI, 0x3d), 0x10 }, /* DDC bus active pull-up control */ 2547d42010a1SLars-Peter Clausen { ADV7604_REG(ADV7604_PAGE_HDMI, 0x3e), 0x39 }, /* TMDS PLL optimization */ 2548d42010a1SLars-Peter Clausen { ADV7604_REG(ADV7604_PAGE_HDMI, 0x4e), 0x3b }, /* TMDS PLL optimization */ 2549d42010a1SLars-Peter Clausen { ADV7604_REG(ADV7604_PAGE_HDMI, 0x57), 0xb6 }, /* TMDS PLL optimization */ 2550d42010a1SLars-Peter Clausen { ADV7604_REG(ADV7604_PAGE_HDMI, 0x58), 0x03 }, /* TMDS PLL optimization */ 2551d42010a1SLars-Peter Clausen { ADV7604_REG(ADV7604_PAGE_HDMI, 0x8d), 0x18 }, /* equaliser */ 2552d42010a1SLars-Peter Clausen { ADV7604_REG(ADV7604_PAGE_HDMI, 0x8e), 0x34 }, /* equaliser */ 2553d42010a1SLars-Peter Clausen { ADV7604_REG(ADV7604_PAGE_HDMI, 0x93), 0x8b }, /* equaliser */ 2554d42010a1SLars-Peter Clausen { ADV7604_REG(ADV7604_PAGE_HDMI, 0x94), 0x2d }, /* equaliser */ 2555d42010a1SLars-Peter Clausen { ADV7604_REG(ADV7604_PAGE_HDMI, 0x96), 0x01 }, /* enable automatic EQ changing */ 2556d42010a1SLars-Peter Clausen 2557d42010a1SLars-Peter Clausen /* reset ADI recommended settings for digitizer */ 2558d42010a1SLars-Peter Clausen /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 17. */ 2559d42010a1SLars-Peter Clausen { ADV7604_REG(ADV7604_PAGE_AFE, 0x12), 0xfb }, /* ADC noise shaping filter controls */ 2560d42010a1SLars-Peter Clausen { ADV7604_REG(ADV7604_PAGE_AFE, 0x0c), 0x0d }, /* CP core gain controls */ 2561d42010a1SLars-Peter Clausen 2562d42010a1SLars-Peter Clausen { ADV7604_REG_SEQ_TERM, 0 }, 2563d42010a1SLars-Peter Clausen }; 2564d42010a1SLars-Peter Clausen 2565d42010a1SLars-Peter Clausen static const struct adv7604_reg_seq adv7611_recommended_settings_hdmi[] = { 2566d42010a1SLars-Peter Clausen { ADV7604_REG(ADV7604_PAGE_CP, 0x6c), 0x00 }, 2567d42010a1SLars-Peter Clausen { ADV7604_REG(ADV7604_PAGE_HDMI, 0x6f), 0x0c }, 2568d42010a1SLars-Peter Clausen { ADV7604_REG(ADV7604_PAGE_HDMI, 0x87), 0x70 }, 2569d42010a1SLars-Peter Clausen { ADV7604_REG(ADV7604_PAGE_HDMI, 0x57), 0xda }, 2570d42010a1SLars-Peter Clausen { ADV7604_REG(ADV7604_PAGE_HDMI, 0x58), 0x01 }, 2571d42010a1SLars-Peter Clausen { ADV7604_REG(ADV7604_PAGE_HDMI, 0x03), 0x98 }, 2572d42010a1SLars-Peter Clausen { ADV7604_REG(ADV7604_PAGE_HDMI, 0x4c), 0x44 }, 2573d42010a1SLars-Peter Clausen { ADV7604_REG(ADV7604_PAGE_HDMI, 0x8d), 0x04 }, 2574d42010a1SLars-Peter Clausen { ADV7604_REG(ADV7604_PAGE_HDMI, 0x8e), 0x1e }, 2575d42010a1SLars-Peter Clausen 2576d42010a1SLars-Peter Clausen { ADV7604_REG_SEQ_TERM, 0 }, 2577d42010a1SLars-Peter Clausen }; 2578d42010a1SLars-Peter Clausen 2579d42010a1SLars-Peter Clausen static const struct adv7604_chip_info adv7604_chip_info[] = { 2580d42010a1SLars-Peter Clausen [ADV7604] = { 2581d42010a1SLars-Peter Clausen .type = ADV7604, 2582d42010a1SLars-Peter Clausen .has_afe = true, 2583c784b1e2SLaurent Pinchart .max_port = ADV7604_PAD_VGA_COMP, 2584d42010a1SLars-Peter Clausen .num_dv_ports = 4, 2585d42010a1SLars-Peter Clausen .edid_enable_reg = 0x77, 2586d42010a1SLars-Peter Clausen .edid_status_reg = 0x7d, 2587d42010a1SLars-Peter Clausen .lcf_reg = 0xb3, 2588d42010a1SLars-Peter Clausen .tdms_lock_mask = 0xe0, 2589d42010a1SLars-Peter Clausen .cable_det_mask = 0x1e, 2590d42010a1SLars-Peter Clausen .fmt_change_digital_mask = 0xc1, 2591539b33b0SLaurent Pinchart .formats = adv7604_formats, 2592539b33b0SLaurent Pinchart .nformats = ARRAY_SIZE(adv7604_formats), 2593d42010a1SLars-Peter Clausen .set_termination = adv7604_set_termination, 2594d42010a1SLars-Peter Clausen .setup_irqs = adv7604_setup_irqs, 2595d42010a1SLars-Peter Clausen .read_hdmi_pixelclock = adv7604_read_hdmi_pixelclock, 2596d42010a1SLars-Peter Clausen .read_cable_det = adv7604_read_cable_det, 2597d42010a1SLars-Peter Clausen .recommended_settings = { 2598d42010a1SLars-Peter Clausen [0] = adv7604_recommended_settings_afe, 2599d42010a1SLars-Peter Clausen [1] = adv7604_recommended_settings_hdmi, 2600d42010a1SLars-Peter Clausen }, 2601d42010a1SLars-Peter Clausen .num_recommended_settings = { 2602d42010a1SLars-Peter Clausen [0] = ARRAY_SIZE(adv7604_recommended_settings_afe), 2603d42010a1SLars-Peter Clausen [1] = ARRAY_SIZE(adv7604_recommended_settings_hdmi), 2604d42010a1SLars-Peter Clausen }, 2605d42010a1SLars-Peter Clausen .page_mask = BIT(ADV7604_PAGE_IO) | BIT(ADV7604_PAGE_AVLINK) | 2606d42010a1SLars-Peter Clausen BIT(ADV7604_PAGE_CEC) | BIT(ADV7604_PAGE_INFOFRAME) | 2607d42010a1SLars-Peter Clausen BIT(ADV7604_PAGE_ESDP) | BIT(ADV7604_PAGE_DPP) | 2608d42010a1SLars-Peter Clausen BIT(ADV7604_PAGE_AFE) | BIT(ADV7604_PAGE_REP) | 2609d42010a1SLars-Peter Clausen BIT(ADV7604_PAGE_EDID) | BIT(ADV7604_PAGE_HDMI) | 2610d42010a1SLars-Peter Clausen BIT(ADV7604_PAGE_TEST) | BIT(ADV7604_PAGE_CP) | 2611d42010a1SLars-Peter Clausen BIT(ADV7604_PAGE_VDP), 2612d42010a1SLars-Peter Clausen }, 2613d42010a1SLars-Peter Clausen [ADV7611] = { 2614d42010a1SLars-Peter Clausen .type = ADV7611, 2615d42010a1SLars-Peter Clausen .has_afe = false, 2616c784b1e2SLaurent Pinchart .max_port = ADV7604_PAD_HDMI_PORT_A, 2617d42010a1SLars-Peter Clausen .num_dv_ports = 1, 2618d42010a1SLars-Peter Clausen .edid_enable_reg = 0x74, 2619d42010a1SLars-Peter Clausen .edid_status_reg = 0x76, 2620d42010a1SLars-Peter Clausen .lcf_reg = 0xa3, 2621d42010a1SLars-Peter Clausen .tdms_lock_mask = 0x43, 2622d42010a1SLars-Peter Clausen .cable_det_mask = 0x01, 2623d42010a1SLars-Peter Clausen .fmt_change_digital_mask = 0x03, 2624539b33b0SLaurent Pinchart .formats = adv7611_formats, 2625539b33b0SLaurent Pinchart .nformats = ARRAY_SIZE(adv7611_formats), 2626d42010a1SLars-Peter Clausen .set_termination = adv7611_set_termination, 2627d42010a1SLars-Peter Clausen .setup_irqs = adv7611_setup_irqs, 2628d42010a1SLars-Peter Clausen .read_hdmi_pixelclock = adv7611_read_hdmi_pixelclock, 2629d42010a1SLars-Peter Clausen .read_cable_det = adv7611_read_cable_det, 2630d42010a1SLars-Peter Clausen .recommended_settings = { 2631d42010a1SLars-Peter Clausen [1] = adv7611_recommended_settings_hdmi, 2632d42010a1SLars-Peter Clausen }, 2633d42010a1SLars-Peter Clausen .num_recommended_settings = { 2634d42010a1SLars-Peter Clausen [1] = ARRAY_SIZE(adv7611_recommended_settings_hdmi), 2635d42010a1SLars-Peter Clausen }, 2636d42010a1SLars-Peter Clausen .page_mask = BIT(ADV7604_PAGE_IO) | BIT(ADV7604_PAGE_CEC) | 2637d42010a1SLars-Peter Clausen BIT(ADV7604_PAGE_INFOFRAME) | BIT(ADV7604_PAGE_AFE) | 2638d42010a1SLars-Peter Clausen BIT(ADV7604_PAGE_REP) | BIT(ADV7604_PAGE_EDID) | 2639d42010a1SLars-Peter Clausen BIT(ADV7604_PAGE_HDMI) | BIT(ADV7604_PAGE_CP), 2640d42010a1SLars-Peter Clausen }, 2641d42010a1SLars-Peter Clausen }; 2642d42010a1SLars-Peter Clausen 264354450f59SHans Verkuil static int adv7604_probe(struct i2c_client *client, 264454450f59SHans Verkuil const struct i2c_device_id *id) 264554450f59SHans Verkuil { 2646591b72feSHans Verkuil static const struct v4l2_dv_timings cea640x480 = 2647591b72feSHans Verkuil V4L2_DV_BT_CEA_640X480P59_94; 264854450f59SHans Verkuil struct adv7604_state *state; 264954450f59SHans Verkuil struct adv7604_platform_data *pdata = client->dev.platform_data; 265054450f59SHans Verkuil struct v4l2_ctrl_handler *hdl; 265154450f59SHans Verkuil struct v4l2_subdev *sd; 2652c784b1e2SLaurent Pinchart unsigned int i; 2653d42010a1SLars-Peter Clausen u16 val; 265454450f59SHans Verkuil int err; 265554450f59SHans Verkuil 265654450f59SHans Verkuil /* Check if the adapter supports the needed features */ 265754450f59SHans Verkuil if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA)) 265854450f59SHans Verkuil return -EIO; 265954450f59SHans Verkuil v4l_dbg(1, debug, client, "detecting adv7604 client on address 0x%x\n", 266054450f59SHans Verkuil client->addr << 1); 266154450f59SHans Verkuil 2662c02b211dSLaurent Pinchart state = devm_kzalloc(&client->dev, sizeof(*state), GFP_KERNEL); 266354450f59SHans Verkuil if (!state) { 266454450f59SHans Verkuil v4l_err(client, "Could not allocate adv7604_state memory!\n"); 266554450f59SHans Verkuil return -ENOMEM; 266654450f59SHans Verkuil } 266754450f59SHans Verkuil 2668d42010a1SLars-Peter Clausen state->info = &adv7604_chip_info[id->driver_data]; 266905cacb17SLaurent Pinchart state->i2c_clients[ADV7604_PAGE_IO] = client; 2670d42010a1SLars-Peter Clausen 267125a64ac9SMats Randgaard /* initialize variables */ 267225a64ac9SMats Randgaard state->restart_stdi_once = true; 2673ff4f80fdSMats Randgaard state->selected_input = ~0; 267425a64ac9SMats Randgaard 267554450f59SHans Verkuil /* platform data */ 267654450f59SHans Verkuil if (!pdata) { 267754450f59SHans Verkuil v4l_err(client, "No platform data!\n"); 2678c02b211dSLaurent Pinchart return -ENODEV; 267954450f59SHans Verkuil } 2680591b72feSHans Verkuil state->pdata = *pdata; 2681591b72feSHans Verkuil state->timings = cea640x480; 2682539b33b0SLaurent Pinchart state->format = adv7604_format_info(state, V4L2_MBUS_FMT_YUYV8_2X8); 268354450f59SHans Verkuil 268454450f59SHans Verkuil sd = &state->sd; 268554450f59SHans Verkuil v4l2_i2c_subdev_init(sd, client, &adv7604_ops); 2686d42010a1SLars-Peter Clausen snprintf(sd->name, sizeof(sd->name), "%s %d-%04x", 2687d42010a1SLars-Peter Clausen id->name, i2c_adapter_id(client->adapter), 2688d42010a1SLars-Peter Clausen client->addr); 268954450f59SHans Verkuil sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; 269054450f59SHans Verkuil 2691d42010a1SLars-Peter Clausen /* 2692d42010a1SLars-Peter Clausen * Verify that the chip is present. On ADV7604 the RD_INFO register only 2693d42010a1SLars-Peter Clausen * identifies the revision, while on ADV7611 it identifies the model as 2694d42010a1SLars-Peter Clausen * well. Use the HDMI slave address on ADV7604 and RD_INFO on ADV7611. 2695d42010a1SLars-Peter Clausen */ 2696d42010a1SLars-Peter Clausen if (state->info->type == ADV7604) { 2697d42010a1SLars-Peter Clausen val = adv_smbus_read_byte_data_check(client, 0xfb, false); 2698d42010a1SLars-Peter Clausen if (val != 0x68) { 269954450f59SHans Verkuil v4l2_info(sd, "not an adv7604 on address 0x%x\n", 270054450f59SHans Verkuil client->addr << 1); 2701c02b211dSLaurent Pinchart return -ENODEV; 270254450f59SHans Verkuil } 2703d42010a1SLars-Peter Clausen } else { 2704d42010a1SLars-Peter Clausen val = (adv_smbus_read_byte_data_check(client, 0xea, false) << 8) 2705d42010a1SLars-Peter Clausen | (adv_smbus_read_byte_data_check(client, 0xeb, false) << 0); 2706d42010a1SLars-Peter Clausen if (val != 0x2051) { 2707d42010a1SLars-Peter Clausen v4l2_info(sd, "not an adv7611 on address 0x%x\n", 2708d42010a1SLars-Peter Clausen client->addr << 1); 2709d42010a1SLars-Peter Clausen return -ENODEV; 2710d42010a1SLars-Peter Clausen } 2711d42010a1SLars-Peter Clausen } 271254450f59SHans Verkuil 271354450f59SHans Verkuil /* control handlers */ 271454450f59SHans Verkuil hdl = &state->hdl; 2715d42010a1SLars-Peter Clausen v4l2_ctrl_handler_init(hdl, adv7604_has_afe(state) ? 9 : 8); 271654450f59SHans Verkuil 271754450f59SHans Verkuil v4l2_ctrl_new_std(hdl, &adv7604_ctrl_ops, 271854450f59SHans Verkuil V4L2_CID_BRIGHTNESS, -128, 127, 1, 0); 271954450f59SHans Verkuil v4l2_ctrl_new_std(hdl, &adv7604_ctrl_ops, 272054450f59SHans Verkuil V4L2_CID_CONTRAST, 0, 255, 1, 128); 272154450f59SHans Verkuil v4l2_ctrl_new_std(hdl, &adv7604_ctrl_ops, 272254450f59SHans Verkuil V4L2_CID_SATURATION, 0, 255, 1, 128); 272354450f59SHans Verkuil v4l2_ctrl_new_std(hdl, &adv7604_ctrl_ops, 272454450f59SHans Verkuil V4L2_CID_HUE, 0, 128, 1, 0); 272554450f59SHans Verkuil 272654450f59SHans Verkuil /* private controls */ 272754450f59SHans Verkuil state->detect_tx_5v_ctrl = v4l2_ctrl_new_std(hdl, NULL, 2728d42010a1SLars-Peter Clausen V4L2_CID_DV_RX_POWER_PRESENT, 0, 2729d42010a1SLars-Peter Clausen (1 << state->info->num_dv_ports) - 1, 0, 0); 273054450f59SHans Verkuil state->rgb_quantization_range_ctrl = 273154450f59SHans Verkuil v4l2_ctrl_new_std_menu(hdl, &adv7604_ctrl_ops, 273254450f59SHans Verkuil V4L2_CID_DV_RX_RGB_RANGE, V4L2_DV_RGB_RANGE_FULL, 273354450f59SHans Verkuil 0, V4L2_DV_RGB_RANGE_AUTO); 273454450f59SHans Verkuil 273554450f59SHans Verkuil /* custom controls */ 2736d42010a1SLars-Peter Clausen if (adv7604_has_afe(state)) 273754450f59SHans Verkuil state->analog_sampling_phase_ctrl = 273854450f59SHans Verkuil v4l2_ctrl_new_custom(hdl, &adv7604_ctrl_analog_sampling_phase, NULL); 273954450f59SHans Verkuil state->free_run_color_manual_ctrl = 274054450f59SHans Verkuil v4l2_ctrl_new_custom(hdl, &adv7604_ctrl_free_run_color_manual, NULL); 274154450f59SHans Verkuil state->free_run_color_ctrl = 274254450f59SHans Verkuil v4l2_ctrl_new_custom(hdl, &adv7604_ctrl_free_run_color, NULL); 274354450f59SHans Verkuil 274454450f59SHans Verkuil sd->ctrl_handler = hdl; 274554450f59SHans Verkuil if (hdl->error) { 274654450f59SHans Verkuil err = hdl->error; 274754450f59SHans Verkuil goto err_hdl; 274854450f59SHans Verkuil } 27498c0eadb8SHans Verkuil state->detect_tx_5v_ctrl->is_private = true; 27508c0eadb8SHans Verkuil state->rgb_quantization_range_ctrl->is_private = true; 2751d42010a1SLars-Peter Clausen if (adv7604_has_afe(state)) 27528c0eadb8SHans Verkuil state->analog_sampling_phase_ctrl->is_private = true; 27538c0eadb8SHans Verkuil state->free_run_color_manual_ctrl->is_private = true; 27548c0eadb8SHans Verkuil state->free_run_color_ctrl->is_private = true; 27558c0eadb8SHans Verkuil 275654450f59SHans Verkuil if (adv7604_s_detect_tx_5v_ctrl(sd)) { 275754450f59SHans Verkuil err = -ENODEV; 275854450f59SHans Verkuil goto err_hdl; 275954450f59SHans Verkuil } 276054450f59SHans Verkuil 276105cacb17SLaurent Pinchart for (i = 1; i < ADV7604_PAGE_MAX; ++i) { 276205cacb17SLaurent Pinchart if (!(BIT(i) & state->info->page_mask)) 276305cacb17SLaurent Pinchart continue; 276405cacb17SLaurent Pinchart 276505cacb17SLaurent Pinchart state->i2c_clients[i] = 276605cacb17SLaurent Pinchart adv7604_dummy_client(sd, pdata->i2c_addresses[i], 276705cacb17SLaurent Pinchart 0xf2 + i); 276805cacb17SLaurent Pinchart if (state->i2c_clients[i] == NULL) { 276954450f59SHans Verkuil err = -ENOMEM; 277005cacb17SLaurent Pinchart v4l2_err(sd, "failed to create i2c client %u\n", i); 277154450f59SHans Verkuil goto err_i2c; 277254450f59SHans Verkuil } 277305cacb17SLaurent Pinchart } 277454450f59SHans Verkuil 277554450f59SHans Verkuil /* work queues */ 277654450f59SHans Verkuil state->work_queues = create_singlethread_workqueue(client->name); 277754450f59SHans Verkuil if (!state->work_queues) { 277854450f59SHans Verkuil v4l2_err(sd, "Could not create work queue\n"); 277954450f59SHans Verkuil err = -ENOMEM; 278054450f59SHans Verkuil goto err_i2c; 278154450f59SHans Verkuil } 278254450f59SHans Verkuil 278354450f59SHans Verkuil INIT_DELAYED_WORK(&state->delayed_work_enable_hotplug, 278454450f59SHans Verkuil adv7604_delayed_work_enable_hotplug); 278554450f59SHans Verkuil 2786c784b1e2SLaurent Pinchart state->source_pad = state->info->num_dv_ports 2787c784b1e2SLaurent Pinchart + (state->info->has_afe ? 2 : 0); 2788c784b1e2SLaurent Pinchart for (i = 0; i < state->source_pad; ++i) 2789c784b1e2SLaurent Pinchart state->pads[i].flags = MEDIA_PAD_FL_SINK; 2790c784b1e2SLaurent Pinchart state->pads[state->source_pad].flags = MEDIA_PAD_FL_SOURCE; 2791c784b1e2SLaurent Pinchart 2792c784b1e2SLaurent Pinchart err = media_entity_init(&sd->entity, state->source_pad + 1, 2793c784b1e2SLaurent Pinchart state->pads, 0); 279454450f59SHans Verkuil if (err) 279554450f59SHans Verkuil goto err_work_queues; 279654450f59SHans Verkuil 279754450f59SHans Verkuil err = adv7604_core_init(sd); 279854450f59SHans Verkuil if (err) 279954450f59SHans Verkuil goto err_entity; 280054450f59SHans Verkuil v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name, 280154450f59SHans Verkuil client->addr << 1, client->adapter->name); 2802bedc3939SLars-Peter Clausen 2803bedc3939SLars-Peter Clausen err = v4l2_async_register_subdev(sd); 2804bedc3939SLars-Peter Clausen if (err) 2805bedc3939SLars-Peter Clausen goto err_entity; 2806bedc3939SLars-Peter Clausen 280754450f59SHans Verkuil return 0; 280854450f59SHans Verkuil 280954450f59SHans Verkuil err_entity: 281054450f59SHans Verkuil media_entity_cleanup(&sd->entity); 281154450f59SHans Verkuil err_work_queues: 281254450f59SHans Verkuil cancel_delayed_work(&state->delayed_work_enable_hotplug); 281354450f59SHans Verkuil destroy_workqueue(state->work_queues); 281454450f59SHans Verkuil err_i2c: 281554450f59SHans Verkuil adv7604_unregister_clients(state); 281654450f59SHans Verkuil err_hdl: 281754450f59SHans Verkuil v4l2_ctrl_handler_free(hdl); 281854450f59SHans Verkuil return err; 281954450f59SHans Verkuil } 282054450f59SHans Verkuil 282154450f59SHans Verkuil /* ----------------------------------------------------------------------- */ 282254450f59SHans Verkuil 282354450f59SHans Verkuil static int adv7604_remove(struct i2c_client *client) 282454450f59SHans Verkuil { 282554450f59SHans Verkuil struct v4l2_subdev *sd = i2c_get_clientdata(client); 282654450f59SHans Verkuil struct adv7604_state *state = to_state(sd); 282754450f59SHans Verkuil 282854450f59SHans Verkuil cancel_delayed_work(&state->delayed_work_enable_hotplug); 282954450f59SHans Verkuil destroy_workqueue(state->work_queues); 2830bedc3939SLars-Peter Clausen v4l2_async_unregister_subdev(sd); 283154450f59SHans Verkuil v4l2_device_unregister_subdev(sd); 283254450f59SHans Verkuil media_entity_cleanup(&sd->entity); 283354450f59SHans Verkuil adv7604_unregister_clients(to_state(sd)); 283454450f59SHans Verkuil v4l2_ctrl_handler_free(sd->ctrl_handler); 283554450f59SHans Verkuil return 0; 283654450f59SHans Verkuil } 283754450f59SHans Verkuil 283854450f59SHans Verkuil /* ----------------------------------------------------------------------- */ 283954450f59SHans Verkuil 284054450f59SHans Verkuil static struct i2c_device_id adv7604_id[] = { 2841d42010a1SLars-Peter Clausen { "adv7604", ADV7604 }, 2842d42010a1SLars-Peter Clausen { "adv7611", ADV7611 }, 284354450f59SHans Verkuil { } 284454450f59SHans Verkuil }; 284554450f59SHans Verkuil MODULE_DEVICE_TABLE(i2c, adv7604_id); 284654450f59SHans Verkuil 284754450f59SHans Verkuil static struct i2c_driver adv7604_driver = { 284854450f59SHans Verkuil .driver = { 284954450f59SHans Verkuil .owner = THIS_MODULE, 285054450f59SHans Verkuil .name = "adv7604", 285154450f59SHans Verkuil }, 285254450f59SHans Verkuil .probe = adv7604_probe, 285354450f59SHans Verkuil .remove = adv7604_remove, 285454450f59SHans Verkuil .id_table = adv7604_id, 285554450f59SHans Verkuil }; 285654450f59SHans Verkuil 285754450f59SHans Verkuil module_i2c_driver(adv7604_driver); 2858