155e5927eSHans Verkuil // SPDX-License-Identifier: GPL-2.0-only
254450f59SHans Verkuil /*
354450f59SHans Verkuil * adv7604 - Analog Devices ADV7604 video decoder driver
454450f59SHans Verkuil *
554450f59SHans Verkuil * Copyright 2012 Cisco Systems, Inc. and/or its affiliates. All rights reserved.
654450f59SHans Verkuil *
754450f59SHans Verkuil */
854450f59SHans Verkuil
954450f59SHans Verkuil /*
1054450f59SHans Verkuil * References (c = chapter, p = page):
1154450f59SHans Verkuil * REF_01 - Analog devices, ADV7604, Register Settings Recommendations,
1254450f59SHans Verkuil * Revision 2.5, June 2010
1354450f59SHans Verkuil * REF_02 - Analog devices, Register map documentation, Documentation of
1454450f59SHans Verkuil * the register maps, Software manual, Rev. F, June 2010
1554450f59SHans Verkuil * REF_03 - Analog devices, ADV7604, Hardware Manual, Rev. F, August 2010
1654450f59SHans Verkuil */
1754450f59SHans Verkuil
18c72a53ceSLaurent Pinchart #include <linux/delay.h>
19e9d50e9eSLaurent Pinchart #include <linux/gpio/consumer.h>
20516613c1SHans Verkuil #include <linux/hdmi.h>
21c72a53ceSLaurent Pinchart #include <linux/i2c.h>
2254450f59SHans Verkuil #include <linux/kernel.h>
2354450f59SHans Verkuil #include <linux/module.h>
24859969b3SSakari Ailus #include <linux/of_graph.h>
2554450f59SHans Verkuil #include <linux/slab.h>
26c72a53ceSLaurent Pinchart #include <linux/v4l2-dv-timings.h>
2754450f59SHans Verkuil #include <linux/videodev2.h>
2854450f59SHans Verkuil #include <linux/workqueue.h>
29f862f57dSPablo Anton #include <linux/regmap.h>
30191cf8b0SJasmin Jessich #include <linux/interrupt.h>
31c72a53ceSLaurent Pinchart
32b5dcee22SMauro Carvalho Chehab #include <media/i2c/adv7604.h>
3341a52373SHans Verkuil #include <media/cec.h>
34c72a53ceSLaurent Pinchart #include <media/v4l2-ctrls.h>
35c72a53ceSLaurent Pinchart #include <media/v4l2-device.h>
360975626dSLars-Peter Clausen #include <media/v4l2-event.h>
37c72a53ceSLaurent Pinchart #include <media/v4l2-dv-timings.h>
38859969b3SSakari Ailus #include <media/v4l2-fwnode.h>
3954450f59SHans Verkuil
4054450f59SHans Verkuil static int debug;
4154450f59SHans Verkuil module_param(debug, int, 0644);
4254450f59SHans Verkuil MODULE_PARM_DESC(debug, "debug level (0-2)");
4354450f59SHans Verkuil
44c2c88a07SKrzysztof Hałasa MODULE_DESCRIPTION("Analog Devices ADV7604/10/11/12 video decoder driver");
4554450f59SHans Verkuil MODULE_AUTHOR("Hans Verkuil <hans.verkuil@cisco.com>");
4654450f59SHans Verkuil MODULE_AUTHOR("Mats Randgaard <mats.randgaard@cisco.com>");
4754450f59SHans Verkuil MODULE_LICENSE("GPL");
4854450f59SHans Verkuil
4954450f59SHans Verkuil /* ADV7604 system clock frequency */
50b44b2e06SPablo Anton #define ADV76XX_FSC (28636360)
5154450f59SHans Verkuil
52b44b2e06SPablo Anton #define ADV76XX_RGB_OUT (1 << 1)
53539b33b0SLaurent Pinchart
54b44b2e06SPablo Anton #define ADV76XX_OP_FORMAT_SEL_8BIT (0 << 0)
55539b33b0SLaurent Pinchart #define ADV7604_OP_FORMAT_SEL_10BIT (1 << 0)
56b44b2e06SPablo Anton #define ADV76XX_OP_FORMAT_SEL_12BIT (2 << 0)
57539b33b0SLaurent Pinchart
58b44b2e06SPablo Anton #define ADV76XX_OP_MODE_SEL_SDR_422 (0 << 5)
59539b33b0SLaurent Pinchart #define ADV7604_OP_MODE_SEL_DDR_422 (1 << 5)
60b44b2e06SPablo Anton #define ADV76XX_OP_MODE_SEL_SDR_444 (2 << 5)
61539b33b0SLaurent Pinchart #define ADV7604_OP_MODE_SEL_DDR_444 (3 << 5)
62b44b2e06SPablo Anton #define ADV76XX_OP_MODE_SEL_SDR_422_2X (4 << 5)
63539b33b0SLaurent Pinchart #define ADV7604_OP_MODE_SEL_ADI_CM (5 << 5)
64539b33b0SLaurent Pinchart
65b44b2e06SPablo Anton #define ADV76XX_OP_CH_SEL_GBR (0 << 5)
66b44b2e06SPablo Anton #define ADV76XX_OP_CH_SEL_GRB (1 << 5)
67b44b2e06SPablo Anton #define ADV76XX_OP_CH_SEL_BGR (2 << 5)
68b44b2e06SPablo Anton #define ADV76XX_OP_CH_SEL_RGB (3 << 5)
69b44b2e06SPablo Anton #define ADV76XX_OP_CH_SEL_BRG (4 << 5)
70b44b2e06SPablo Anton #define ADV76XX_OP_CH_SEL_RBG (5 << 5)
71539b33b0SLaurent Pinchart
72b44b2e06SPablo Anton #define ADV76XX_OP_SWAP_CB_CR (1 << 0)
73539b33b0SLaurent Pinchart
7441a52373SHans Verkuil #define ADV76XX_MAX_ADDRS (3)
7541a52373SHans Verkuil
76c730ff32SHans Verkuil #define ADV76XX_MAX_EDID_BLOCKS 4
77c730ff32SHans Verkuil
78b44b2e06SPablo Anton enum adv76xx_type {
79d42010a1SLars-Peter Clausen ADV7604,
80c2c88a07SKrzysztof Hałasa ADV7611, // including ADV7610
818331d30bSWilliam Towle ADV7612,
82d42010a1SLars-Peter Clausen };
83d42010a1SLars-Peter Clausen
84b44b2e06SPablo Anton struct adv76xx_reg_seq {
85d42010a1SLars-Peter Clausen unsigned int reg;
86d42010a1SLars-Peter Clausen u8 val;
87d42010a1SLars-Peter Clausen };
88d42010a1SLars-Peter Clausen
89b44b2e06SPablo Anton struct adv76xx_format_info {
90f5fe58fdSBoris BREZILLON u32 code;
91539b33b0SLaurent Pinchart u8 op_ch_sel;
92539b33b0SLaurent Pinchart bool rgb_out;
93539b33b0SLaurent Pinchart bool swap_cb_cr;
94539b33b0SLaurent Pinchart u8 op_format_sel;
95539b33b0SLaurent Pinchart };
96539b33b0SLaurent Pinchart
97516613c1SHans Verkuil struct adv76xx_cfg_read_infoframe {
98516613c1SHans Verkuil const char *desc;
99516613c1SHans Verkuil u8 present_mask;
100516613c1SHans Verkuil u8 head_addr;
101516613c1SHans Verkuil u8 payload_addr;
102516613c1SHans Verkuil };
103516613c1SHans Verkuil
104b44b2e06SPablo Anton struct adv76xx_chip_info {
105b44b2e06SPablo Anton enum adv76xx_type type;
106d42010a1SLars-Peter Clausen
107d42010a1SLars-Peter Clausen bool has_afe;
108d42010a1SLars-Peter Clausen unsigned int max_port;
109d42010a1SLars-Peter Clausen unsigned int num_dv_ports;
110d42010a1SLars-Peter Clausen
111d42010a1SLars-Peter Clausen unsigned int edid_enable_reg;
112d42010a1SLars-Peter Clausen unsigned int edid_status_reg;
113c730ff32SHans Verkuil unsigned int edid_segment_reg;
114c730ff32SHans Verkuil unsigned int edid_segment_mask;
115c730ff32SHans Verkuil unsigned int edid_spa_loc_reg;
116c730ff32SHans Verkuil unsigned int edid_spa_loc_msb_mask;
117c730ff32SHans Verkuil unsigned int edid_spa_port_b_reg;
118d42010a1SLars-Peter Clausen unsigned int lcf_reg;
119d42010a1SLars-Peter Clausen
120d42010a1SLars-Peter Clausen unsigned int cable_det_mask;
121d42010a1SLars-Peter Clausen unsigned int tdms_lock_mask;
122d42010a1SLars-Peter Clausen unsigned int fmt_change_digital_mask;
12380f4944eSjean-michel.hautbois@vodalys.com unsigned int cp_csc;
124d42010a1SLars-Peter Clausen
12540d91c99SHans Verkuil unsigned int cec_irq_status;
12640d91c99SHans Verkuil unsigned int cec_rx_enable;
12740d91c99SHans Verkuil unsigned int cec_rx_enable_mask;
12840d91c99SHans Verkuil bool cec_irq_swap;
12940d91c99SHans Verkuil
130b44b2e06SPablo Anton const struct adv76xx_format_info *formats;
131539b33b0SLaurent Pinchart unsigned int nformats;
132539b33b0SLaurent Pinchart
133d42010a1SLars-Peter Clausen void (*set_termination)(struct v4l2_subdev *sd, bool enable);
134d42010a1SLars-Peter Clausen void (*setup_irqs)(struct v4l2_subdev *sd);
135d42010a1SLars-Peter Clausen unsigned int (*read_hdmi_pixelclock)(struct v4l2_subdev *sd);
136d42010a1SLars-Peter Clausen unsigned int (*read_cable_det)(struct v4l2_subdev *sd);
137d42010a1SLars-Peter Clausen
138d42010a1SLars-Peter Clausen /* 0 = AFE, 1 = HDMI */
139b44b2e06SPablo Anton const struct adv76xx_reg_seq *recommended_settings[2];
140d42010a1SLars-Peter Clausen unsigned int num_recommended_settings[2];
141d42010a1SLars-Peter Clausen
142d42010a1SLars-Peter Clausen unsigned long page_mask;
1435380baafSjean-michel.hautbois@vodalys.com
1445380baafSjean-michel.hautbois@vodalys.com /* Masks for timings */
1455380baafSjean-michel.hautbois@vodalys.com unsigned int linewidth_mask;
1465380baafSjean-michel.hautbois@vodalys.com unsigned int field0_height_mask;
1475380baafSjean-michel.hautbois@vodalys.com unsigned int field1_height_mask;
1485380baafSjean-michel.hautbois@vodalys.com unsigned int hfrontporch_mask;
1495380baafSjean-michel.hautbois@vodalys.com unsigned int hsync_mask;
1505380baafSjean-michel.hautbois@vodalys.com unsigned int hbackporch_mask;
1515380baafSjean-michel.hautbois@vodalys.com unsigned int field0_vfrontporch_mask;
1525380baafSjean-michel.hautbois@vodalys.com unsigned int field1_vfrontporch_mask;
1535380baafSjean-michel.hautbois@vodalys.com unsigned int field0_vsync_mask;
1545380baafSjean-michel.hautbois@vodalys.com unsigned int field1_vsync_mask;
1555380baafSjean-michel.hautbois@vodalys.com unsigned int field0_vbackporch_mask;
1565380baafSjean-michel.hautbois@vodalys.com unsigned int field1_vbackporch_mask;
157d42010a1SLars-Peter Clausen };
158d42010a1SLars-Peter Clausen
15954450f59SHans Verkuil /*
16054450f59SHans Verkuil **********************************************************************
16154450f59SHans Verkuil *
16254450f59SHans Verkuil * Arrays with configuration parameters for the ADV7604
16354450f59SHans Verkuil *
16454450f59SHans Verkuil **********************************************************************
16554450f59SHans Verkuil */
166c784b1e2SLaurent Pinchart
167b44b2e06SPablo Anton struct adv76xx_state {
168b44b2e06SPablo Anton const struct adv76xx_chip_info *info;
169b44b2e06SPablo Anton struct adv76xx_platform_data pdata;
170539b33b0SLaurent Pinchart
171e9d50e9eSLaurent Pinchart struct gpio_desc *hpd_gpio[4];
172f5591da9SDragos Bogdan struct gpio_desc *reset_gpio;
173e9d50e9eSLaurent Pinchart
17454450f59SHans Verkuil struct v4l2_subdev sd;
175b44b2e06SPablo Anton struct media_pad pads[ADV76XX_PAD_MAX];
176c784b1e2SLaurent Pinchart unsigned int source_pad;
177539b33b0SLaurent Pinchart
17854450f59SHans Verkuil struct v4l2_ctrl_handler hdl;
179539b33b0SLaurent Pinchart
180b44b2e06SPablo Anton enum adv76xx_pad selected_input;
181539b33b0SLaurent Pinchart
18254450f59SHans Verkuil struct v4l2_dv_timings timings;
183b44b2e06SPablo Anton const struct adv76xx_format_info *format;
184539b33b0SLaurent Pinchart
1854a31a93aSMats Randgaard struct {
186c730ff32SHans Verkuil u8 edid[ADV76XX_MAX_EDID_BLOCKS * 128];
1874a31a93aSMats Randgaard u32 present;
1884a31a93aSMats Randgaard unsigned blocks;
1894a31a93aSMats Randgaard } edid;
190dd08beb9SMats Randgaard u16 spa_port_a[2];
19154450f59SHans Verkuil struct v4l2_fract aspect_ratio;
19254450f59SHans Verkuil u32 rgb_quantization_range;
19354450f59SHans Verkuil struct delayed_work delayed_work_enable_hotplug;
194cf9afb1dSHans Verkuil bool restart_stdi_once;
19554450f59SHans Verkuil
196cbb5c835SMauro Carvalho Chehab /* CEC */
19741a52373SHans Verkuil struct cec_adapter *cec_adap;
19841a52373SHans Verkuil u8 cec_addr[ADV76XX_MAX_ADDRS];
19941a52373SHans Verkuil u8 cec_valid_addrs;
20041a52373SHans Verkuil bool cec_enabled_adap;
20141a52373SHans Verkuil
20254450f59SHans Verkuil /* i2c clients */
203b44b2e06SPablo Anton struct i2c_client *i2c_clients[ADV76XX_PAGE_MAX];
20454450f59SHans Verkuil
205f862f57dSPablo Anton /* Regmaps */
206f862f57dSPablo Anton struct regmap *regmap[ADV76XX_PAGE_MAX];
207f862f57dSPablo Anton
20854450f59SHans Verkuil /* controls */
20954450f59SHans Verkuil struct v4l2_ctrl *detect_tx_5v_ctrl;
21054450f59SHans Verkuil struct v4l2_ctrl *analog_sampling_phase_ctrl;
21154450f59SHans Verkuil struct v4l2_ctrl *free_run_color_manual_ctrl;
21254450f59SHans Verkuil struct v4l2_ctrl *free_run_color_ctrl;
21354450f59SHans Verkuil struct v4l2_ctrl *rgb_quantization_range_ctrl;
21454450f59SHans Verkuil };
21554450f59SHans Verkuil
adv76xx_has_afe(struct adv76xx_state * state)216b44b2e06SPablo Anton static bool adv76xx_has_afe(struct adv76xx_state *state)
217d42010a1SLars-Peter Clausen {
218d42010a1SLars-Peter Clausen return state->info->has_afe;
219d42010a1SLars-Peter Clausen }
220d42010a1SLars-Peter Clausen
221bd3e275fSJean-Michel Hautbois /* Unsupported timings. This device cannot support 720p30. */
222bd3e275fSJean-Michel Hautbois static const struct v4l2_dv_timings adv76xx_timings_exceptions[] = {
223bd3e275fSJean-Michel Hautbois V4L2_DV_BT_CEA_1280X720P30,
224bd3e275fSJean-Michel Hautbois { }
22554450f59SHans Verkuil };
22654450f59SHans Verkuil
adv76xx_check_dv_timings(const struct v4l2_dv_timings * t,void * hdl)227bd3e275fSJean-Michel Hautbois static bool adv76xx_check_dv_timings(const struct v4l2_dv_timings *t, void *hdl)
228bd3e275fSJean-Michel Hautbois {
229bd3e275fSJean-Michel Hautbois int i;
230bd3e275fSJean-Michel Hautbois
231bd3e275fSJean-Michel Hautbois for (i = 0; adv76xx_timings_exceptions[i].bt.width; i++)
232bd3e275fSJean-Michel Hautbois if (v4l2_match_dv_timings(t, adv76xx_timings_exceptions + i, 0, false))
233bd3e275fSJean-Michel Hautbois return false;
234bd3e275fSJean-Michel Hautbois return true;
235bd3e275fSJean-Michel Hautbois }
236bd3e275fSJean-Michel Hautbois
237b44b2e06SPablo Anton struct adv76xx_video_standards {
238ccbd5bc4SHans Verkuil struct v4l2_dv_timings timings;
239ccbd5bc4SHans Verkuil u8 vid_std;
240ccbd5bc4SHans Verkuil u8 v_freq;
241ccbd5bc4SHans Verkuil };
242ccbd5bc4SHans Verkuil
243ccbd5bc4SHans Verkuil /* sorted by number of lines */
244b44b2e06SPablo Anton static const struct adv76xx_video_standards adv7604_prim_mode_comp[] = {
245ccbd5bc4SHans Verkuil /* { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 }, TODO flickering */
246ccbd5bc4SHans Verkuil { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 },
247ccbd5bc4SHans Verkuil { V4L2_DV_BT_CEA_1280X720P50, 0x19, 0x01 },
248ccbd5bc4SHans Verkuil { V4L2_DV_BT_CEA_1280X720P60, 0x19, 0x00 },
249ccbd5bc4SHans Verkuil { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 },
250ccbd5bc4SHans Verkuil { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 },
251ccbd5bc4SHans Verkuil { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 },
252ccbd5bc4SHans Verkuil { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 },
253ccbd5bc4SHans Verkuil { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 },
254ccbd5bc4SHans Verkuil /* TODO add 1920x1080P60_RB (CVT timing) */
255ccbd5bc4SHans Verkuil { },
256ccbd5bc4SHans Verkuil };
257ccbd5bc4SHans Verkuil
258ccbd5bc4SHans Verkuil /* sorted by number of lines */
259b44b2e06SPablo Anton static const struct adv76xx_video_standards adv7604_prim_mode_gr[] = {
260ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 },
261ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 },
262ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 },
263ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 },
264ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 },
265ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 },
266ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 },
267ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 },
268ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 },
269ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 },
270ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 },
271ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 },
272ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 },
273ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 },
274ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 },
275ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_1360X768P60, 0x12, 0x00 },
276ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_1366X768P60, 0x13, 0x00 },
277ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_1400X1050P60, 0x14, 0x00 },
278ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_1400X1050P75, 0x15, 0x00 },
279ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_1600X1200P60, 0x16, 0x00 }, /* TODO not tested */
280ccbd5bc4SHans Verkuil /* TODO add 1600X1200P60_RB (not a DMT timing) */
281ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_1680X1050P60, 0x18, 0x00 },
282ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_1920X1200P60_RB, 0x19, 0x00 }, /* TODO not tested */
283ccbd5bc4SHans Verkuil { },
284ccbd5bc4SHans Verkuil };
285ccbd5bc4SHans Verkuil
286ccbd5bc4SHans Verkuil /* sorted by number of lines */
287b44b2e06SPablo Anton static const struct adv76xx_video_standards adv76xx_prim_mode_hdmi_comp[] = {
288ccbd5bc4SHans Verkuil { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 },
289ccbd5bc4SHans Verkuil { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 },
290ccbd5bc4SHans Verkuil { V4L2_DV_BT_CEA_1280X720P50, 0x13, 0x01 },
291ccbd5bc4SHans Verkuil { V4L2_DV_BT_CEA_1280X720P60, 0x13, 0x00 },
292ccbd5bc4SHans Verkuil { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 },
293ccbd5bc4SHans Verkuil { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 },
294ccbd5bc4SHans Verkuil { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 },
295ccbd5bc4SHans Verkuil { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 },
296ccbd5bc4SHans Verkuil { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 },
297ccbd5bc4SHans Verkuil { },
298ccbd5bc4SHans Verkuil };
299ccbd5bc4SHans Verkuil
300ccbd5bc4SHans Verkuil /* sorted by number of lines */
301b44b2e06SPablo Anton static const struct adv76xx_video_standards adv76xx_prim_mode_hdmi_gr[] = {
302ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 },
303ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 },
304ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 },
305ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 },
306ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 },
307ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 },
308ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 },
309ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 },
310ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 },
311ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 },
312ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 },
313ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 },
314ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 },
315ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 },
316ccbd5bc4SHans Verkuil { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 },
317ccbd5bc4SHans Verkuil { },
318ccbd5bc4SHans Verkuil };
319ccbd5bc4SHans Verkuil
32048519838SHans Verkuil static const struct v4l2_event adv76xx_ev_fmt = {
32148519838SHans Verkuil .type = V4L2_EVENT_SOURCE_CHANGE,
32248519838SHans Verkuil .u.src_change.changes = V4L2_EVENT_SRC_CH_RESOLUTION,
32348519838SHans Verkuil };
32448519838SHans Verkuil
32554450f59SHans Verkuil /* ----------------------------------------------------------------------- */
32654450f59SHans Verkuil
to_state(struct v4l2_subdev * sd)327b44b2e06SPablo Anton static inline struct adv76xx_state *to_state(struct v4l2_subdev *sd)
32854450f59SHans Verkuil {
329b44b2e06SPablo Anton return container_of(sd, struct adv76xx_state, sd);
33054450f59SHans Verkuil }
33154450f59SHans Verkuil
htotal(const struct v4l2_bt_timings * t)33254450f59SHans Verkuil static inline unsigned htotal(const struct v4l2_bt_timings *t)
33354450f59SHans Verkuil {
334eacf8f9aSHans Verkuil return V4L2_DV_BT_FRAME_WIDTH(t);
33554450f59SHans Verkuil }
33654450f59SHans Verkuil
vtotal(const struct v4l2_bt_timings * t)33754450f59SHans Verkuil static inline unsigned vtotal(const struct v4l2_bt_timings *t)
33854450f59SHans Verkuil {
339eacf8f9aSHans Verkuil return V4L2_DV_BT_FRAME_HEIGHT(t);
34054450f59SHans Verkuil }
34154450f59SHans Verkuil
34254450f59SHans Verkuil /* ----------------------------------------------------------------------- */
34354450f59SHans Verkuil
adv76xx_read_check(struct adv76xx_state * state,int client_page,u8 reg)344f862f57dSPablo Anton static int adv76xx_read_check(struct adv76xx_state *state,
345f862f57dSPablo Anton int client_page, u8 reg)
34654450f59SHans Verkuil {
347f862f57dSPablo Anton struct i2c_client *client = state->i2c_clients[client_page];
34854450f59SHans Verkuil int err;
349f862f57dSPablo Anton unsigned int val;
35054450f59SHans Verkuil
351f862f57dSPablo Anton err = regmap_read(state->regmap[client_page], reg, &val);
352f862f57dSPablo Anton
353f862f57dSPablo Anton if (err) {
354f862f57dSPablo Anton v4l_err(client, "error reading %02x, %02x\n",
355f862f57dSPablo Anton client->addr, reg);
35654450f59SHans Verkuil return err;
35754450f59SHans Verkuil }
358f862f57dSPablo Anton return val;
359f862f57dSPablo Anton }
36054450f59SHans Verkuil
361f862f57dSPablo Anton /* adv76xx_write_block(): Write raw data with a maximum of I2C_SMBUS_BLOCK_MAX
362f862f57dSPablo Anton * size to one or more registers.
363f862f57dSPablo Anton *
364f862f57dSPablo Anton * A value of zero will be returned on success, a negative errno will
365f862f57dSPablo Anton * be returned in error cases.
366f862f57dSPablo Anton */
adv76xx_write_block(struct adv76xx_state * state,int client_page,unsigned int init_reg,const void * val,size_t val_len)367f862f57dSPablo Anton static int adv76xx_write_block(struct adv76xx_state *state, int client_page,
368f862f57dSPablo Anton unsigned int init_reg, const void *val,
369f862f57dSPablo Anton size_t val_len)
37054450f59SHans Verkuil {
371f862f57dSPablo Anton struct regmap *regmap = state->regmap[client_page];
37254450f59SHans Verkuil
373f862f57dSPablo Anton if (val_len > I2C_SMBUS_BLOCK_MAX)
374f862f57dSPablo Anton val_len = I2C_SMBUS_BLOCK_MAX;
375f862f57dSPablo Anton
376f862f57dSPablo Anton return regmap_raw_write(regmap, init_reg, val, val_len);
37754450f59SHans Verkuil }
37854450f59SHans Verkuil
37954450f59SHans Verkuil /* ----------------------------------------------------------------------- */
38054450f59SHans Verkuil
io_read(struct v4l2_subdev * sd,u8 reg)38154450f59SHans Verkuil static inline int io_read(struct v4l2_subdev *sd, u8 reg)
38254450f59SHans Verkuil {
383b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd);
38454450f59SHans Verkuil
385f862f57dSPablo Anton return adv76xx_read_check(state, ADV76XX_PAGE_IO, reg);
38654450f59SHans Verkuil }
38754450f59SHans Verkuil
io_write(struct v4l2_subdev * sd,u8 reg,u8 val)38854450f59SHans Verkuil static inline int io_write(struct v4l2_subdev *sd, u8 reg, u8 val)
38954450f59SHans Verkuil {
390b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd);
39154450f59SHans Verkuil
392f862f57dSPablo Anton return regmap_write(state->regmap[ADV76XX_PAGE_IO], reg, val);
39354450f59SHans Verkuil }
39454450f59SHans Verkuil
io_write_clr_set(struct v4l2_subdev * sd,u8 reg,u8 mask,u8 val)39541a52373SHans Verkuil static inline int io_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask,
39641a52373SHans Verkuil u8 val)
39754450f59SHans Verkuil {
39822d97e56SLaurent Pinchart return io_write(sd, reg, (io_read(sd, reg) & ~mask) | val);
39954450f59SHans Verkuil }
40054450f59SHans Verkuil
avlink_read(struct v4l2_subdev * sd,u8 reg)40112f3d836SMauro Carvalho Chehab static inline int __always_unused avlink_read(struct v4l2_subdev *sd, u8 reg)
40254450f59SHans Verkuil {
403b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd);
40454450f59SHans Verkuil
405f862f57dSPablo Anton return adv76xx_read_check(state, ADV7604_PAGE_AVLINK, reg);
40654450f59SHans Verkuil }
40754450f59SHans Verkuil
avlink_write(struct v4l2_subdev * sd,u8 reg,u8 val)40812f3d836SMauro Carvalho Chehab static inline int __always_unused avlink_write(struct v4l2_subdev *sd, u8 reg, u8 val)
40954450f59SHans Verkuil {
410b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd);
41154450f59SHans Verkuil
412f862f57dSPablo Anton return regmap_write(state->regmap[ADV7604_PAGE_AVLINK], reg, val);
41354450f59SHans Verkuil }
41454450f59SHans Verkuil
cec_read(struct v4l2_subdev * sd,u8 reg)41554450f59SHans Verkuil static inline int cec_read(struct v4l2_subdev *sd, u8 reg)
41654450f59SHans Verkuil {
417b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd);
41854450f59SHans Verkuil
419f862f57dSPablo Anton return adv76xx_read_check(state, ADV76XX_PAGE_CEC, reg);
42054450f59SHans Verkuil }
42154450f59SHans Verkuil
cec_write(struct v4l2_subdev * sd,u8 reg,u8 val)42254450f59SHans Verkuil static inline int cec_write(struct v4l2_subdev *sd, u8 reg, u8 val)
42354450f59SHans Verkuil {
424b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd);
42554450f59SHans Verkuil
426f862f57dSPablo Anton return regmap_write(state->regmap[ADV76XX_PAGE_CEC], reg, val);
42754450f59SHans Verkuil }
42854450f59SHans Verkuil
cec_write_clr_set(struct v4l2_subdev * sd,u8 reg,u8 mask,u8 val)42941a52373SHans Verkuil static inline int cec_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask,
43041a52373SHans Verkuil u8 val)
43141a52373SHans Verkuil {
43241a52373SHans Verkuil return cec_write(sd, reg, (cec_read(sd, reg) & ~mask) | val);
43341a52373SHans Verkuil }
43441a52373SHans Verkuil
infoframe_read(struct v4l2_subdev * sd,u8 reg)43554450f59SHans Verkuil static inline int infoframe_read(struct v4l2_subdev *sd, u8 reg)
43654450f59SHans Verkuil {
437b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd);
43854450f59SHans Verkuil
439f862f57dSPablo Anton return adv76xx_read_check(state, ADV76XX_PAGE_INFOFRAME, reg);
44054450f59SHans Verkuil }
44154450f59SHans Verkuil
infoframe_write(struct v4l2_subdev * sd,u8 reg,u8 val)44212f3d836SMauro Carvalho Chehab static inline int __always_unused infoframe_write(struct v4l2_subdev *sd, u8 reg, u8 val)
44354450f59SHans Verkuil {
444b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd);
44554450f59SHans Verkuil
446f862f57dSPablo Anton return regmap_write(state->regmap[ADV76XX_PAGE_INFOFRAME], reg, val);
44754450f59SHans Verkuil }
44854450f59SHans Verkuil
afe_read(struct v4l2_subdev * sd,u8 reg)44912f3d836SMauro Carvalho Chehab static inline int __always_unused afe_read(struct v4l2_subdev *sd, u8 reg)
45054450f59SHans Verkuil {
451b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd);
45254450f59SHans Verkuil
453f862f57dSPablo Anton return adv76xx_read_check(state, ADV76XX_PAGE_AFE, reg);
45454450f59SHans Verkuil }
45554450f59SHans Verkuil
afe_write(struct v4l2_subdev * sd,u8 reg,u8 val)45654450f59SHans Verkuil static inline int afe_write(struct v4l2_subdev *sd, u8 reg, u8 val)
45754450f59SHans Verkuil {
458b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd);
45954450f59SHans Verkuil
460f862f57dSPablo Anton return regmap_write(state->regmap[ADV76XX_PAGE_AFE], reg, val);
46154450f59SHans Verkuil }
46254450f59SHans Verkuil
rep_read(struct v4l2_subdev * sd,u8 reg)46354450f59SHans Verkuil static inline int rep_read(struct v4l2_subdev *sd, u8 reg)
46454450f59SHans Verkuil {
465b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd);
46654450f59SHans Verkuil
467f862f57dSPablo Anton return adv76xx_read_check(state, ADV76XX_PAGE_REP, reg);
46854450f59SHans Verkuil }
46954450f59SHans Verkuil
rep_write(struct v4l2_subdev * sd,u8 reg,u8 val)47054450f59SHans Verkuil static inline int rep_write(struct v4l2_subdev *sd, u8 reg, u8 val)
47154450f59SHans Verkuil {
472b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd);
47354450f59SHans Verkuil
474f862f57dSPablo Anton return regmap_write(state->regmap[ADV76XX_PAGE_REP], reg, val);
47554450f59SHans Verkuil }
47654450f59SHans Verkuil
rep_write_clr_set(struct v4l2_subdev * sd,u8 reg,u8 mask,u8 val)47722d97e56SLaurent Pinchart static inline int rep_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
47854450f59SHans Verkuil {
47922d97e56SLaurent Pinchart return rep_write(sd, reg, (rep_read(sd, reg) & ~mask) | val);
48054450f59SHans Verkuil }
48154450f59SHans Verkuil
edid_read(struct v4l2_subdev * sd,u8 reg)48212f3d836SMauro Carvalho Chehab static inline int __always_unused edid_read(struct v4l2_subdev *sd, u8 reg)
48354450f59SHans Verkuil {
484b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd);
48554450f59SHans Verkuil
486f862f57dSPablo Anton return adv76xx_read_check(state, ADV76XX_PAGE_EDID, reg);
48754450f59SHans Verkuil }
48854450f59SHans Verkuil
edid_write(struct v4l2_subdev * sd,u8 reg,u8 val)48912f3d836SMauro Carvalho Chehab static inline int __always_unused edid_write(struct v4l2_subdev *sd, u8 reg, u8 val)
49054450f59SHans Verkuil {
491b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd);
49254450f59SHans Verkuil
493f862f57dSPablo Anton return regmap_write(state->regmap[ADV76XX_PAGE_EDID], reg, val);
49454450f59SHans Verkuil }
49554450f59SHans Verkuil
edid_write_block(struct v4l2_subdev * sd,unsigned int total_len,const u8 * val)496dd08beb9SMats Randgaard static inline int edid_write_block(struct v4l2_subdev *sd,
497f862f57dSPablo Anton unsigned int total_len, const u8 *val)
498dd08beb9SMats Randgaard {
499b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd);
500dd08beb9SMats Randgaard int err = 0;
501f862f57dSPablo Anton int i = 0;
502f862f57dSPablo Anton int len = 0;
503dd08beb9SMats Randgaard
504f862f57dSPablo Anton v4l2_dbg(2, debug, sd, "%s: write EDID block (%d byte)\n",
505f862f57dSPablo Anton __func__, total_len);
506dd08beb9SMats Randgaard
507f862f57dSPablo Anton while (!err && i < total_len) {
508f862f57dSPablo Anton len = (total_len - i) > I2C_SMBUS_BLOCK_MAX ?
509f862f57dSPablo Anton I2C_SMBUS_BLOCK_MAX :
510f862f57dSPablo Anton (total_len - i);
511f862f57dSPablo Anton
512f862f57dSPablo Anton err = adv76xx_write_block(state, ADV76XX_PAGE_EDID,
513f862f57dSPablo Anton i, val + i, len);
514f862f57dSPablo Anton i += len;
515f862f57dSPablo Anton }
516f862f57dSPablo Anton
517dd08beb9SMats Randgaard return err;
518dd08beb9SMats Randgaard }
519dd08beb9SMats Randgaard
adv76xx_set_hpd(struct adv76xx_state * state,unsigned int hpd)520b44b2e06SPablo Anton static void adv76xx_set_hpd(struct adv76xx_state *state, unsigned int hpd)
521e9d50e9eSLaurent Pinchart {
5221cf233d8SHans Verkuil const struct adv76xx_chip_info *info = state->info;
523e9d50e9eSLaurent Pinchart unsigned int i;
524e9d50e9eSLaurent Pinchart
5251cf233d8SHans Verkuil if (info->type == ADV7604) {
526269bd132SUwe Kleine-König for (i = 0; i < state->info->num_dv_ports; ++i)
527e9d50e9eSLaurent Pinchart gpiod_set_value_cansleep(state->hpd_gpio[i], hpd & BIT(i));
5281cf233d8SHans Verkuil } else {
5291cf233d8SHans Verkuil for (i = 0; i < state->info->num_dv_ports; ++i)
5301cf233d8SHans Verkuil io_write_clr_set(&state->sd, 0x20, 0x80 >> i,
5311cf233d8SHans Verkuil (!!(hpd & BIT(i))) << (7 - i));
5321cf233d8SHans Verkuil }
533e9d50e9eSLaurent Pinchart
534b44b2e06SPablo Anton v4l2_subdev_notify(&state->sd, ADV76XX_HOTPLUG, &hpd);
535e9d50e9eSLaurent Pinchart }
536e9d50e9eSLaurent Pinchart
adv76xx_delayed_work_enable_hotplug(struct work_struct * work)537b44b2e06SPablo Anton static void adv76xx_delayed_work_enable_hotplug(struct work_struct *work)
53854450f59SHans Verkuil {
53954450f59SHans Verkuil struct delayed_work *dwork = to_delayed_work(work);
540b44b2e06SPablo Anton struct adv76xx_state *state = container_of(dwork, struct adv76xx_state,
54154450f59SHans Verkuil delayed_work_enable_hotplug);
54254450f59SHans Verkuil struct v4l2_subdev *sd = &state->sd;
54354450f59SHans Verkuil
54454450f59SHans Verkuil v4l2_dbg(2, debug, sd, "%s: enable hotplug\n", __func__);
54554450f59SHans Verkuil
546b44b2e06SPablo Anton adv76xx_set_hpd(state, state->edid.present);
54754450f59SHans Verkuil }
54854450f59SHans Verkuil
hdmi_read(struct v4l2_subdev * sd,u8 reg)54954450f59SHans Verkuil static inline int hdmi_read(struct v4l2_subdev *sd, u8 reg)
55054450f59SHans Verkuil {
551b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd);
55254450f59SHans Verkuil
553f862f57dSPablo Anton return adv76xx_read_check(state, ADV76XX_PAGE_HDMI, reg);
55454450f59SHans Verkuil }
55554450f59SHans Verkuil
hdmi_read16(struct v4l2_subdev * sd,u8 reg,u16 mask)55651182a94SLaurent Pinchart static u16 hdmi_read16(struct v4l2_subdev *sd, u8 reg, u16 mask)
55751182a94SLaurent Pinchart {
55851182a94SLaurent Pinchart return ((hdmi_read(sd, reg) << 8) | hdmi_read(sd, reg + 1)) & mask;
55951182a94SLaurent Pinchart }
56051182a94SLaurent Pinchart
hdmi_write(struct v4l2_subdev * sd,u8 reg,u8 val)56154450f59SHans Verkuil static inline int hdmi_write(struct v4l2_subdev *sd, u8 reg, u8 val)
56254450f59SHans Verkuil {
563b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd);
56454450f59SHans Verkuil
565f862f57dSPablo Anton return regmap_write(state->regmap[ADV76XX_PAGE_HDMI], reg, val);
56654450f59SHans Verkuil }
56754450f59SHans Verkuil
hdmi_write_clr_set(struct v4l2_subdev * sd,u8 reg,u8 mask,u8 val)56822d97e56SLaurent Pinchart static inline int hdmi_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
5694a31a93aSMats Randgaard {
57022d97e56SLaurent Pinchart return hdmi_write(sd, reg, (hdmi_read(sd, reg) & ~mask) | val);
5714a31a93aSMats Randgaard }
5724a31a93aSMats Randgaard
test_write(struct v4l2_subdev * sd,u8 reg,u8 val)57312f3d836SMauro Carvalho Chehab static inline int __always_unused test_write(struct v4l2_subdev *sd, u8 reg, u8 val)
57454450f59SHans Verkuil {
575b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd);
57654450f59SHans Verkuil
577f862f57dSPablo Anton return regmap_write(state->regmap[ADV76XX_PAGE_TEST], reg, val);
57854450f59SHans Verkuil }
57954450f59SHans Verkuil
cp_read(struct v4l2_subdev * sd,u8 reg)58054450f59SHans Verkuil static inline int cp_read(struct v4l2_subdev *sd, u8 reg)
58154450f59SHans Verkuil {
582b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd);
58354450f59SHans Verkuil
584f862f57dSPablo Anton return adv76xx_read_check(state, ADV76XX_PAGE_CP, reg);
58554450f59SHans Verkuil }
58654450f59SHans Verkuil
cp_read16(struct v4l2_subdev * sd,u8 reg,u16 mask)58751182a94SLaurent Pinchart static u16 cp_read16(struct v4l2_subdev *sd, u8 reg, u16 mask)
58851182a94SLaurent Pinchart {
58951182a94SLaurent Pinchart return ((cp_read(sd, reg) << 8) | cp_read(sd, reg + 1)) & mask;
59051182a94SLaurent Pinchart }
59151182a94SLaurent Pinchart
cp_write(struct v4l2_subdev * sd,u8 reg,u8 val)59254450f59SHans Verkuil static inline int cp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
59354450f59SHans Verkuil {
594b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd);
59554450f59SHans Verkuil
596f862f57dSPablo Anton return regmap_write(state->regmap[ADV76XX_PAGE_CP], reg, val);
59754450f59SHans Verkuil }
59854450f59SHans Verkuil
cp_write_clr_set(struct v4l2_subdev * sd,u8 reg,u8 mask,u8 val)59922d97e56SLaurent Pinchart static inline int cp_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
60054450f59SHans Verkuil {
60122d97e56SLaurent Pinchart return cp_write(sd, reg, (cp_read(sd, reg) & ~mask) | val);
60254450f59SHans Verkuil }
60354450f59SHans Verkuil
vdp_read(struct v4l2_subdev * sd,u8 reg)60412f3d836SMauro Carvalho Chehab static inline int __always_unused vdp_read(struct v4l2_subdev *sd, u8 reg)
60554450f59SHans Verkuil {
606b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd);
60754450f59SHans Verkuil
608f862f57dSPablo Anton return adv76xx_read_check(state, ADV7604_PAGE_VDP, reg);
60954450f59SHans Verkuil }
61054450f59SHans Verkuil
vdp_write(struct v4l2_subdev * sd,u8 reg,u8 val)61112f3d836SMauro Carvalho Chehab static inline int __always_unused vdp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
61254450f59SHans Verkuil {
613b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd);
61454450f59SHans Verkuil
615f862f57dSPablo Anton return regmap_write(state->regmap[ADV7604_PAGE_VDP], reg, val);
61654450f59SHans Verkuil }
61754450f59SHans Verkuil
618b44b2e06SPablo Anton #define ADV76XX_REG(page, offset) (((page) << 8) | (offset))
619b44b2e06SPablo Anton #define ADV76XX_REG_SEQ_TERM 0xffff
620d42010a1SLars-Peter Clausen
621d42010a1SLars-Peter Clausen #ifdef CONFIG_VIDEO_ADV_DEBUG
adv76xx_read_reg(struct v4l2_subdev * sd,unsigned int reg)622b44b2e06SPablo Anton static int adv76xx_read_reg(struct v4l2_subdev *sd, unsigned int reg)
623d42010a1SLars-Peter Clausen {
624b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd);
625d42010a1SLars-Peter Clausen unsigned int page = reg >> 8;
626f862f57dSPablo Anton unsigned int val;
627f862f57dSPablo Anton int err;
628d42010a1SLars-Peter Clausen
6297cc7a833SDan Carpenter if (page >= ADV76XX_PAGE_MAX || !(BIT(page) & state->info->page_mask))
630d42010a1SLars-Peter Clausen return -EINVAL;
631d42010a1SLars-Peter Clausen
632d42010a1SLars-Peter Clausen reg &= 0xff;
633f862f57dSPablo Anton err = regmap_read(state->regmap[page], reg, &val);
634d42010a1SLars-Peter Clausen
635f862f57dSPablo Anton return err ? err : val;
636d42010a1SLars-Peter Clausen }
637d42010a1SLars-Peter Clausen #endif
638d42010a1SLars-Peter Clausen
adv76xx_write_reg(struct v4l2_subdev * sd,unsigned int reg,u8 val)639b44b2e06SPablo Anton static int adv76xx_write_reg(struct v4l2_subdev *sd, unsigned int reg, u8 val)
640d42010a1SLars-Peter Clausen {
641b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd);
642d42010a1SLars-Peter Clausen unsigned int page = reg >> 8;
643d42010a1SLars-Peter Clausen
6447cc7a833SDan Carpenter if (page >= ADV76XX_PAGE_MAX || !(BIT(page) & state->info->page_mask))
645d42010a1SLars-Peter Clausen return -EINVAL;
646d42010a1SLars-Peter Clausen
647d42010a1SLars-Peter Clausen reg &= 0xff;
648d42010a1SLars-Peter Clausen
649f862f57dSPablo Anton return regmap_write(state->regmap[page], reg, val);
650d42010a1SLars-Peter Clausen }
651d42010a1SLars-Peter Clausen
adv76xx_write_reg_seq(struct v4l2_subdev * sd,const struct adv76xx_reg_seq * reg_seq)652b44b2e06SPablo Anton static void adv76xx_write_reg_seq(struct v4l2_subdev *sd,
653b44b2e06SPablo Anton const struct adv76xx_reg_seq *reg_seq)
654d42010a1SLars-Peter Clausen {
655d42010a1SLars-Peter Clausen unsigned int i;
656d42010a1SLars-Peter Clausen
657b44b2e06SPablo Anton for (i = 0; reg_seq[i].reg != ADV76XX_REG_SEQ_TERM; i++)
658b44b2e06SPablo Anton adv76xx_write_reg(sd, reg_seq[i].reg, reg_seq[i].val);
659d42010a1SLars-Peter Clausen }
660d42010a1SLars-Peter Clausen
661539b33b0SLaurent Pinchart /* -----------------------------------------------------------------------------
662539b33b0SLaurent Pinchart * Format helpers
663539b33b0SLaurent Pinchart */
664539b33b0SLaurent Pinchart
665b44b2e06SPablo Anton static const struct adv76xx_format_info adv7604_formats[] = {
666b44b2e06SPablo Anton { MEDIA_BUS_FMT_RGB888_1X24, ADV76XX_OP_CH_SEL_RGB, true, false,
667b44b2e06SPablo Anton ADV76XX_OP_MODE_SEL_SDR_444 | ADV76XX_OP_FORMAT_SEL_8BIT },
668b44b2e06SPablo Anton { MEDIA_BUS_FMT_YUYV8_2X8, ADV76XX_OP_CH_SEL_RGB, false, false,
669b44b2e06SPablo Anton ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT },
670b44b2e06SPablo Anton { MEDIA_BUS_FMT_YVYU8_2X8, ADV76XX_OP_CH_SEL_RGB, false, true,
671b44b2e06SPablo Anton ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT },
672b44b2e06SPablo Anton { MEDIA_BUS_FMT_YUYV10_2X10, ADV76XX_OP_CH_SEL_RGB, false, false,
673b44b2e06SPablo Anton ADV76XX_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_10BIT },
674b44b2e06SPablo Anton { MEDIA_BUS_FMT_YVYU10_2X10, ADV76XX_OP_CH_SEL_RGB, false, true,
675b44b2e06SPablo Anton ADV76XX_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_10BIT },
676b44b2e06SPablo Anton { MEDIA_BUS_FMT_YUYV12_2X12, ADV76XX_OP_CH_SEL_RGB, false, false,
677b44b2e06SPablo Anton ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_12BIT },
678b44b2e06SPablo Anton { MEDIA_BUS_FMT_YVYU12_2X12, ADV76XX_OP_CH_SEL_RGB, false, true,
679b44b2e06SPablo Anton ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_12BIT },
680b44b2e06SPablo Anton { MEDIA_BUS_FMT_UYVY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, false,
681b44b2e06SPablo Anton ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
682b44b2e06SPablo Anton { MEDIA_BUS_FMT_VYUY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, true,
683b44b2e06SPablo Anton ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
684b44b2e06SPablo Anton { MEDIA_BUS_FMT_YUYV8_1X16, ADV76XX_OP_CH_SEL_RGB, false, false,
685b44b2e06SPablo Anton ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
686b44b2e06SPablo Anton { MEDIA_BUS_FMT_YVYU8_1X16, ADV76XX_OP_CH_SEL_RGB, false, true,
687b44b2e06SPablo Anton ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
688b44b2e06SPablo Anton { MEDIA_BUS_FMT_UYVY10_1X20, ADV76XX_OP_CH_SEL_RBG, false, false,
689b44b2e06SPablo Anton ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT },
690b44b2e06SPablo Anton { MEDIA_BUS_FMT_VYUY10_1X20, ADV76XX_OP_CH_SEL_RBG, false, true,
691b44b2e06SPablo Anton ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT },
692b44b2e06SPablo Anton { MEDIA_BUS_FMT_YUYV10_1X20, ADV76XX_OP_CH_SEL_RGB, false, false,
693b44b2e06SPablo Anton ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT },
694b44b2e06SPablo Anton { MEDIA_BUS_FMT_YVYU10_1X20, ADV76XX_OP_CH_SEL_RGB, false, true,
695b44b2e06SPablo Anton ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT },
696b44b2e06SPablo Anton { MEDIA_BUS_FMT_UYVY12_1X24, ADV76XX_OP_CH_SEL_RBG, false, false,
697b44b2e06SPablo Anton ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
698b44b2e06SPablo Anton { MEDIA_BUS_FMT_VYUY12_1X24, ADV76XX_OP_CH_SEL_RBG, false, true,
699b44b2e06SPablo Anton ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
700b44b2e06SPablo Anton { MEDIA_BUS_FMT_YUYV12_1X24, ADV76XX_OP_CH_SEL_RGB, false, false,
701b44b2e06SPablo Anton ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
702b44b2e06SPablo Anton { MEDIA_BUS_FMT_YVYU12_1X24, ADV76XX_OP_CH_SEL_RGB, false, true,
703b44b2e06SPablo Anton ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
704539b33b0SLaurent Pinchart };
705539b33b0SLaurent Pinchart
706b44b2e06SPablo Anton static const struct adv76xx_format_info adv7611_formats[] = {
707b44b2e06SPablo Anton { MEDIA_BUS_FMT_RGB888_1X24, ADV76XX_OP_CH_SEL_RGB, true, false,
708b44b2e06SPablo Anton ADV76XX_OP_MODE_SEL_SDR_444 | ADV76XX_OP_FORMAT_SEL_8BIT },
709b44b2e06SPablo Anton { MEDIA_BUS_FMT_YUYV8_2X8, ADV76XX_OP_CH_SEL_RGB, false, false,
710b44b2e06SPablo Anton ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT },
711b44b2e06SPablo Anton { MEDIA_BUS_FMT_YVYU8_2X8, ADV76XX_OP_CH_SEL_RGB, false, true,
712b44b2e06SPablo Anton ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT },
713b44b2e06SPablo Anton { MEDIA_BUS_FMT_YUYV12_2X12, ADV76XX_OP_CH_SEL_RGB, false, false,
714b44b2e06SPablo Anton ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_12BIT },
715b44b2e06SPablo Anton { MEDIA_BUS_FMT_YVYU12_2X12, ADV76XX_OP_CH_SEL_RGB, false, true,
716b44b2e06SPablo Anton ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_12BIT },
717b44b2e06SPablo Anton { MEDIA_BUS_FMT_UYVY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, false,
718b44b2e06SPablo Anton ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
719b44b2e06SPablo Anton { MEDIA_BUS_FMT_VYUY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, true,
720b44b2e06SPablo Anton ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
721b44b2e06SPablo Anton { MEDIA_BUS_FMT_YUYV8_1X16, ADV76XX_OP_CH_SEL_RGB, false, false,
722b44b2e06SPablo Anton ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
723b44b2e06SPablo Anton { MEDIA_BUS_FMT_YVYU8_1X16, ADV76XX_OP_CH_SEL_RGB, false, true,
724b44b2e06SPablo Anton ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
725b44b2e06SPablo Anton { MEDIA_BUS_FMT_UYVY12_1X24, ADV76XX_OP_CH_SEL_RBG, false, false,
726b44b2e06SPablo Anton ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
727b44b2e06SPablo Anton { MEDIA_BUS_FMT_VYUY12_1X24, ADV76XX_OP_CH_SEL_RBG, false, true,
728b44b2e06SPablo Anton ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
729b44b2e06SPablo Anton { MEDIA_BUS_FMT_YUYV12_1X24, ADV76XX_OP_CH_SEL_RGB, false, false,
730b44b2e06SPablo Anton ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
731b44b2e06SPablo Anton { MEDIA_BUS_FMT_YVYU12_1X24, ADV76XX_OP_CH_SEL_RGB, false, true,
732b44b2e06SPablo Anton ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
733539b33b0SLaurent Pinchart };
734539b33b0SLaurent Pinchart
7358331d30bSWilliam Towle static const struct adv76xx_format_info adv7612_formats[] = {
7368331d30bSWilliam Towle { MEDIA_BUS_FMT_RGB888_1X24, ADV76XX_OP_CH_SEL_RGB, true, false,
7378331d30bSWilliam Towle ADV76XX_OP_MODE_SEL_SDR_444 | ADV76XX_OP_FORMAT_SEL_8BIT },
7388331d30bSWilliam Towle { MEDIA_BUS_FMT_YUYV8_2X8, ADV76XX_OP_CH_SEL_RGB, false, false,
7398331d30bSWilliam Towle ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT },
7408331d30bSWilliam Towle { MEDIA_BUS_FMT_YVYU8_2X8, ADV76XX_OP_CH_SEL_RGB, false, true,
7418331d30bSWilliam Towle ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT },
7428331d30bSWilliam Towle { MEDIA_BUS_FMT_UYVY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, false,
7438331d30bSWilliam Towle ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
7448331d30bSWilliam Towle { MEDIA_BUS_FMT_VYUY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, true,
7458331d30bSWilliam Towle ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
7468331d30bSWilliam Towle { MEDIA_BUS_FMT_YUYV8_1X16, ADV76XX_OP_CH_SEL_RGB, false, false,
7478331d30bSWilliam Towle ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
7488331d30bSWilliam Towle { MEDIA_BUS_FMT_YVYU8_1X16, ADV76XX_OP_CH_SEL_RGB, false, true,
7498331d30bSWilliam Towle ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
7508331d30bSWilliam Towle };
7518331d30bSWilliam Towle
752b44b2e06SPablo Anton static const struct adv76xx_format_info *
adv76xx_format_info(struct adv76xx_state * state,u32 code)753b44b2e06SPablo Anton adv76xx_format_info(struct adv76xx_state *state, u32 code)
754539b33b0SLaurent Pinchart {
755539b33b0SLaurent Pinchart unsigned int i;
756539b33b0SLaurent Pinchart
757539b33b0SLaurent Pinchart for (i = 0; i < state->info->nformats; ++i) {
758539b33b0SLaurent Pinchart if (state->info->formats[i].code == code)
759539b33b0SLaurent Pinchart return &state->info->formats[i];
760539b33b0SLaurent Pinchart }
761539b33b0SLaurent Pinchart
762539b33b0SLaurent Pinchart return NULL;
763539b33b0SLaurent Pinchart }
764539b33b0SLaurent Pinchart
76554450f59SHans Verkuil /* ----------------------------------------------------------------------- */
76654450f59SHans Verkuil
is_analog_input(struct v4l2_subdev * sd)7674a31a93aSMats Randgaard static inline bool is_analog_input(struct v4l2_subdev *sd)
7684a31a93aSMats Randgaard {
769b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd);
7704a31a93aSMats Randgaard
771c784b1e2SLaurent Pinchart return state->selected_input == ADV7604_PAD_VGA_RGB ||
772c784b1e2SLaurent Pinchart state->selected_input == ADV7604_PAD_VGA_COMP;
7734a31a93aSMats Randgaard }
7744a31a93aSMats Randgaard
is_digital_input(struct v4l2_subdev * sd)7754a31a93aSMats Randgaard static inline bool is_digital_input(struct v4l2_subdev *sd)
7764a31a93aSMats Randgaard {
777b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd);
7784a31a93aSMats Randgaard
779b44b2e06SPablo Anton return state->selected_input == ADV76XX_PAD_HDMI_PORT_A ||
780c784b1e2SLaurent Pinchart state->selected_input == ADV7604_PAD_HDMI_PORT_B ||
781c784b1e2SLaurent Pinchart state->selected_input == ADV7604_PAD_HDMI_PORT_C ||
782c784b1e2SLaurent Pinchart state->selected_input == ADV7604_PAD_HDMI_PORT_D;
7834a31a93aSMats Randgaard }
7844a31a93aSMats Randgaard
785bd3e275fSJean-Michel Hautbois static const struct v4l2_dv_timings_cap adv7604_timings_cap_analog = {
786bd3e275fSJean-Michel Hautbois .type = V4L2_DV_BT_656_1120,
787bd3e275fSJean-Michel Hautbois /* keep this initialization for compatibility with GCC < 4.4.6 */
788bd3e275fSJean-Michel Hautbois .reserved = { 0 },
7892912289aSHans Verkuil V4L2_INIT_BT_TIMINGS(640, 1920, 350, 1200, 25000000, 170000000,
790bd3e275fSJean-Michel Hautbois V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
791bd3e275fSJean-Michel Hautbois V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT,
792bd3e275fSJean-Michel Hautbois V4L2_DV_BT_CAP_PROGRESSIVE | V4L2_DV_BT_CAP_REDUCED_BLANKING |
793bd3e275fSJean-Michel Hautbois V4L2_DV_BT_CAP_CUSTOM)
794bd3e275fSJean-Michel Hautbois };
795bd3e275fSJean-Michel Hautbois
796bd3e275fSJean-Michel Hautbois static const struct v4l2_dv_timings_cap adv76xx_timings_cap_digital = {
797bd3e275fSJean-Michel Hautbois .type = V4L2_DV_BT_656_1120,
798bd3e275fSJean-Michel Hautbois /* keep this initialization for compatibility with GCC < 4.4.6 */
799bd3e275fSJean-Michel Hautbois .reserved = { 0 },
8002912289aSHans Verkuil V4L2_INIT_BT_TIMINGS(640, 1920, 350, 1200, 25000000, 225000000,
801bd3e275fSJean-Michel Hautbois V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
802bd3e275fSJean-Michel Hautbois V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT,
803bd3e275fSJean-Michel Hautbois V4L2_DV_BT_CAP_PROGRESSIVE | V4L2_DV_BT_CAP_REDUCED_BLANKING |
804bd3e275fSJean-Michel Hautbois V4L2_DV_BT_CAP_CUSTOM)
805bd3e275fSJean-Michel Hautbois };
806bd3e275fSJean-Michel Hautbois
8079c41e690SLaurent Pinchart /*
8089c41e690SLaurent Pinchart * Return the DV timings capabilities for the requested sink pad. As a special
8099c41e690SLaurent Pinchart * case, pad value -1 returns the capabilities for the currently selected input.
8109c41e690SLaurent Pinchart */
8119c41e690SLaurent Pinchart static const struct v4l2_dv_timings_cap *
adv76xx_get_dv_timings_cap(struct v4l2_subdev * sd,int pad)8129c41e690SLaurent Pinchart adv76xx_get_dv_timings_cap(struct v4l2_subdev *sd, int pad)
813bd3e275fSJean-Michel Hautbois {
8149c41e690SLaurent Pinchart if (pad == -1) {
8159c41e690SLaurent Pinchart struct adv76xx_state *state = to_state(sd);
8169c41e690SLaurent Pinchart
8179c41e690SLaurent Pinchart pad = state->selected_input;
8189c41e690SLaurent Pinchart }
8199c41e690SLaurent Pinchart
8209c41e690SLaurent Pinchart switch (pad) {
8219c41e690SLaurent Pinchart case ADV76XX_PAD_HDMI_PORT_A:
8229c41e690SLaurent Pinchart case ADV7604_PAD_HDMI_PORT_B:
8239c41e690SLaurent Pinchart case ADV7604_PAD_HDMI_PORT_C:
8249c41e690SLaurent Pinchart case ADV7604_PAD_HDMI_PORT_D:
8259c41e690SLaurent Pinchart return &adv76xx_timings_cap_digital;
8269c41e690SLaurent Pinchart
8279c41e690SLaurent Pinchart case ADV7604_PAD_VGA_RGB:
8289c41e690SLaurent Pinchart case ADV7604_PAD_VGA_COMP:
8299c41e690SLaurent Pinchart default:
8309c41e690SLaurent Pinchart return &adv7604_timings_cap_analog;
8319c41e690SLaurent Pinchart }
832bd3e275fSJean-Michel Hautbois }
833bd3e275fSJean-Michel Hautbois
834bd3e275fSJean-Michel Hautbois
8354a31a93aSMats Randgaard /* ----------------------------------------------------------------------- */
8364a31a93aSMats Randgaard
83754450f59SHans Verkuil #ifdef CONFIG_VIDEO_ADV_DEBUG
adv76xx_inv_register(struct v4l2_subdev * sd)838b44b2e06SPablo Anton static void adv76xx_inv_register(struct v4l2_subdev *sd)
83954450f59SHans Verkuil {
84054450f59SHans Verkuil v4l2_info(sd, "0x000-0x0ff: IO Map\n");
84154450f59SHans Verkuil v4l2_info(sd, "0x100-0x1ff: AVLink Map\n");
84254450f59SHans Verkuil v4l2_info(sd, "0x200-0x2ff: CEC Map\n");
84354450f59SHans Verkuil v4l2_info(sd, "0x300-0x3ff: InfoFrame Map\n");
84454450f59SHans Verkuil v4l2_info(sd, "0x400-0x4ff: ESDP Map\n");
84554450f59SHans Verkuil v4l2_info(sd, "0x500-0x5ff: DPP Map\n");
84654450f59SHans Verkuil v4l2_info(sd, "0x600-0x6ff: AFE Map\n");
84754450f59SHans Verkuil v4l2_info(sd, "0x700-0x7ff: Repeater Map\n");
84854450f59SHans Verkuil v4l2_info(sd, "0x800-0x8ff: EDID Map\n");
84954450f59SHans Verkuil v4l2_info(sd, "0x900-0x9ff: HDMI Map\n");
85054450f59SHans Verkuil v4l2_info(sd, "0xa00-0xaff: Test Map\n");
85154450f59SHans Verkuil v4l2_info(sd, "0xb00-0xbff: CP Map\n");
85254450f59SHans Verkuil v4l2_info(sd, "0xc00-0xcff: VDP Map\n");
85354450f59SHans Verkuil }
85454450f59SHans Verkuil
adv76xx_g_register(struct v4l2_subdev * sd,struct v4l2_dbg_register * reg)855b44b2e06SPablo Anton static int adv76xx_g_register(struct v4l2_subdev *sd,
85654450f59SHans Verkuil struct v4l2_dbg_register *reg)
85754450f59SHans Verkuil {
858d42010a1SLars-Peter Clausen int ret;
859d42010a1SLars-Peter Clausen
860b44b2e06SPablo Anton ret = adv76xx_read_reg(sd, reg->reg);
861d42010a1SLars-Peter Clausen if (ret < 0) {
86254450f59SHans Verkuil v4l2_info(sd, "Register %03llx not supported\n", reg->reg);
863b44b2e06SPablo Anton adv76xx_inv_register(sd);
864d42010a1SLars-Peter Clausen return ret;
86554450f59SHans Verkuil }
866d42010a1SLars-Peter Clausen
867d42010a1SLars-Peter Clausen reg->size = 1;
868d42010a1SLars-Peter Clausen reg->val = ret;
869d42010a1SLars-Peter Clausen
87054450f59SHans Verkuil return 0;
87154450f59SHans Verkuil }
87254450f59SHans Verkuil
adv76xx_s_register(struct v4l2_subdev * sd,const struct v4l2_dbg_register * reg)873b44b2e06SPablo Anton static int adv76xx_s_register(struct v4l2_subdev *sd,
874977ba3b1SHans Verkuil const struct v4l2_dbg_register *reg)
87554450f59SHans Verkuil {
876d42010a1SLars-Peter Clausen int ret;
8771577461bSHans Verkuil
878b44b2e06SPablo Anton ret = adv76xx_write_reg(sd, reg->reg, reg->val);
879d42010a1SLars-Peter Clausen if (ret < 0) {
88054450f59SHans Verkuil v4l2_info(sd, "Register %03llx not supported\n", reg->reg);
881b44b2e06SPablo Anton adv76xx_inv_register(sd);
882d42010a1SLars-Peter Clausen return ret;
88354450f59SHans Verkuil }
884d42010a1SLars-Peter Clausen
88554450f59SHans Verkuil return 0;
88654450f59SHans Verkuil }
88754450f59SHans Verkuil #endif
88854450f59SHans Verkuil
adv7604_read_cable_det(struct v4l2_subdev * sd)889d42010a1SLars-Peter Clausen static unsigned int adv7604_read_cable_det(struct v4l2_subdev *sd)
890d42010a1SLars-Peter Clausen {
891d42010a1SLars-Peter Clausen u8 value = io_read(sd, 0x6f);
892d42010a1SLars-Peter Clausen
893d42010a1SLars-Peter Clausen return ((value & 0x10) >> 4)
894d42010a1SLars-Peter Clausen | ((value & 0x08) >> 2)
895d42010a1SLars-Peter Clausen | ((value & 0x04) << 0)
896d42010a1SLars-Peter Clausen | ((value & 0x02) << 2);
897d42010a1SLars-Peter Clausen }
898d42010a1SLars-Peter Clausen
adv7611_read_cable_det(struct v4l2_subdev * sd)899d42010a1SLars-Peter Clausen static unsigned int adv7611_read_cable_det(struct v4l2_subdev *sd)
900d42010a1SLars-Peter Clausen {
901d42010a1SLars-Peter Clausen u8 value = io_read(sd, 0x6f);
902d42010a1SLars-Peter Clausen
903d42010a1SLars-Peter Clausen return value & 1;
904d42010a1SLars-Peter Clausen }
905d42010a1SLars-Peter Clausen
adv7612_read_cable_det(struct v4l2_subdev * sd)9067111cdddSWilliam Towle static unsigned int adv7612_read_cable_det(struct v4l2_subdev *sd)
9077111cdddSWilliam Towle {
9087111cdddSWilliam Towle /* Reads CABLE_DET_A_RAW. For input B support, need to
9097111cdddSWilliam Towle * account for bit 7 [MSB] of 0x6a (ie. CABLE_DET_B_RAW)
9107111cdddSWilliam Towle */
9117111cdddSWilliam Towle u8 value = io_read(sd, 0x6f);
9127111cdddSWilliam Towle
9137111cdddSWilliam Towle return value & 1;
9147111cdddSWilliam Towle }
9157111cdddSWilliam Towle
adv76xx_s_detect_tx_5v_ctrl(struct v4l2_subdev * sd)916b44b2e06SPablo Anton static int adv76xx_s_detect_tx_5v_ctrl(struct v4l2_subdev *sd)
91754450f59SHans Verkuil {
918b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd);
919b44b2e06SPablo Anton const struct adv76xx_chip_info *info = state->info;
92041a52373SHans Verkuil u16 cable_det = info->read_cable_det(sd);
92154450f59SHans Verkuil
92241a52373SHans Verkuil return v4l2_ctrl_s_ctrl(state->detect_tx_5v_ctrl, cable_det);
92354450f59SHans Verkuil }
92454450f59SHans Verkuil
find_and_set_predefined_video_timings(struct v4l2_subdev * sd,u8 prim_mode,const struct adv76xx_video_standards * predef_vid_timings,const struct v4l2_dv_timings * timings)925ccbd5bc4SHans Verkuil static int find_and_set_predefined_video_timings(struct v4l2_subdev *sd,
926ccbd5bc4SHans Verkuil u8 prim_mode,
927b44b2e06SPablo Anton const struct adv76xx_video_standards *predef_vid_timings,
928ccbd5bc4SHans Verkuil const struct v4l2_dv_timings *timings)
92954450f59SHans Verkuil {
930ccbd5bc4SHans Verkuil int i;
93154450f59SHans Verkuil
932ccbd5bc4SHans Verkuil for (i = 0; predef_vid_timings[i].timings.bt.width; i++) {
933ef1ed8f5SHans Verkuil if (!v4l2_match_dv_timings(timings, &predef_vid_timings[i].timings,
93485f9e06cSHans Verkuil is_digital_input(sd) ? 250000 : 1000000, false))
935ccbd5bc4SHans Verkuil continue;
936ccbd5bc4SHans Verkuil io_write(sd, 0x00, predef_vid_timings[i].vid_std); /* video std */
937ccbd5bc4SHans Verkuil io_write(sd, 0x01, (predef_vid_timings[i].v_freq << 4) +
938ccbd5bc4SHans Verkuil prim_mode); /* v_freq and prim mode */
939ccbd5bc4SHans Verkuil return 0;
94054450f59SHans Verkuil }
94154450f59SHans Verkuil
942ccbd5bc4SHans Verkuil return -1;
943ccbd5bc4SHans Verkuil }
94454450f59SHans Verkuil
configure_predefined_video_timings(struct v4l2_subdev * sd,struct v4l2_dv_timings * timings)945ccbd5bc4SHans Verkuil static int configure_predefined_video_timings(struct v4l2_subdev *sd,
946ccbd5bc4SHans Verkuil struct v4l2_dv_timings *timings)
947ccbd5bc4SHans Verkuil {
948b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd);
949ccbd5bc4SHans Verkuil int err;
950ccbd5bc4SHans Verkuil
951ccbd5bc4SHans Verkuil v4l2_dbg(1, debug, sd, "%s", __func__);
952ccbd5bc4SHans Verkuil
953b44b2e06SPablo Anton if (adv76xx_has_afe(state)) {
95454450f59SHans Verkuil /* reset to default values */
95554450f59SHans Verkuil io_write(sd, 0x16, 0x43);
95654450f59SHans Verkuil io_write(sd, 0x17, 0x5a);
957d42010a1SLars-Peter Clausen }
958ccbd5bc4SHans Verkuil /* disable embedded syncs for auto graphics mode */
95922d97e56SLaurent Pinchart cp_write_clr_set(sd, 0x81, 0x10, 0x00);
960ccbd5bc4SHans Verkuil cp_write(sd, 0x8f, 0x00);
961ccbd5bc4SHans Verkuil cp_write(sd, 0x90, 0x00);
96254450f59SHans Verkuil cp_write(sd, 0xa2, 0x00);
96354450f59SHans Verkuil cp_write(sd, 0xa3, 0x00);
96454450f59SHans Verkuil cp_write(sd, 0xa4, 0x00);
96554450f59SHans Verkuil cp_write(sd, 0xa5, 0x00);
96654450f59SHans Verkuil cp_write(sd, 0xa6, 0x00);
96754450f59SHans Verkuil cp_write(sd, 0xa7, 0x00);
968ccbd5bc4SHans Verkuil cp_write(sd, 0xab, 0x00);
969ccbd5bc4SHans Verkuil cp_write(sd, 0xac, 0x00);
970ccbd5bc4SHans Verkuil
9714a31a93aSMats Randgaard if (is_analog_input(sd)) {
972ccbd5bc4SHans Verkuil err = find_and_set_predefined_video_timings(sd,
973ccbd5bc4SHans Verkuil 0x01, adv7604_prim_mode_comp, timings);
974ccbd5bc4SHans Verkuil if (err)
975ccbd5bc4SHans Verkuil err = find_and_set_predefined_video_timings(sd,
976ccbd5bc4SHans Verkuil 0x02, adv7604_prim_mode_gr, timings);
9774a31a93aSMats Randgaard } else if (is_digital_input(sd)) {
978ccbd5bc4SHans Verkuil err = find_and_set_predefined_video_timings(sd,
979b44b2e06SPablo Anton 0x05, adv76xx_prim_mode_hdmi_comp, timings);
980ccbd5bc4SHans Verkuil if (err)
981ccbd5bc4SHans Verkuil err = find_and_set_predefined_video_timings(sd,
982b44b2e06SPablo Anton 0x06, adv76xx_prim_mode_hdmi_gr, timings);
9834a31a93aSMats Randgaard } else {
9844a31a93aSMats Randgaard v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n",
9854a31a93aSMats Randgaard __func__, state->selected_input);
986ccbd5bc4SHans Verkuil err = -1;
98754450f59SHans Verkuil }
98854450f59SHans Verkuil
98954450f59SHans Verkuil
990ccbd5bc4SHans Verkuil return err;
991ccbd5bc4SHans Verkuil }
992ccbd5bc4SHans Verkuil
configure_custom_video_timings(struct v4l2_subdev * sd,const struct v4l2_bt_timings * bt)993ccbd5bc4SHans Verkuil static void configure_custom_video_timings(struct v4l2_subdev *sd,
994ccbd5bc4SHans Verkuil const struct v4l2_bt_timings *bt)
995ccbd5bc4SHans Verkuil {
996b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd);
997ccbd5bc4SHans Verkuil u32 width = htotal(bt);
998ccbd5bc4SHans Verkuil u32 height = vtotal(bt);
999ccbd5bc4SHans Verkuil u16 cp_start_sav = bt->hsync + bt->hbackporch - 4;
1000ccbd5bc4SHans Verkuil u16 cp_start_eav = width - bt->hfrontporch;
1001ccbd5bc4SHans Verkuil u16 cp_start_vbi = height - bt->vfrontporch;
1002ccbd5bc4SHans Verkuil u16 cp_end_vbi = bt->vsync + bt->vbackporch;
1003ccbd5bc4SHans Verkuil u16 ch1_fr_ll = (((u32)bt->pixelclock / 100) > 0) ?
1004b44b2e06SPablo Anton ((width * (ADV76XX_FSC / 100)) / ((u32)bt->pixelclock / 100)) : 0;
1005ccbd5bc4SHans Verkuil const u8 pll[2] = {
1006ccbd5bc4SHans Verkuil 0xc0 | ((width >> 8) & 0x1f),
1007ccbd5bc4SHans Verkuil width & 0xff
1008ccbd5bc4SHans Verkuil };
1009ccbd5bc4SHans Verkuil
1010ccbd5bc4SHans Verkuil v4l2_dbg(2, debug, sd, "%s\n", __func__);
1011ccbd5bc4SHans Verkuil
10124a31a93aSMats Randgaard if (is_analog_input(sd)) {
1013ccbd5bc4SHans Verkuil /* auto graphics */
1014ccbd5bc4SHans Verkuil io_write(sd, 0x00, 0x07); /* video std */
1015ccbd5bc4SHans Verkuil io_write(sd, 0x01, 0x02); /* prim mode */
1016ccbd5bc4SHans Verkuil /* enable embedded syncs for auto graphics mode */
101722d97e56SLaurent Pinchart cp_write_clr_set(sd, 0x81, 0x10, 0x10);
1018ccbd5bc4SHans Verkuil
1019ccbd5bc4SHans Verkuil /* Should only be set in auto-graphics mode [REF_02, p. 91-92] */
1020ccbd5bc4SHans Verkuil /* setup PLL_DIV_MAN_EN and PLL_DIV_RATIO */
1021ccbd5bc4SHans Verkuil /* IO-map reg. 0x16 and 0x17 should be written in sequence */
1022f862f57dSPablo Anton if (regmap_raw_write(state->regmap[ADV76XX_PAGE_IO],
1023f862f57dSPablo Anton 0x16, pll, 2))
1024ccbd5bc4SHans Verkuil v4l2_err(sd, "writing to reg 0x16 and 0x17 failed\n");
1025ccbd5bc4SHans Verkuil
1026ccbd5bc4SHans Verkuil /* active video - horizontal timing */
1027ccbd5bc4SHans Verkuil cp_write(sd, 0xa2, (cp_start_sav >> 4) & 0xff);
1028ccbd5bc4SHans Verkuil cp_write(sd, 0xa3, ((cp_start_sav & 0x0f) << 4) |
1029ccbd5bc4SHans Verkuil ((cp_start_eav >> 8) & 0x0f));
1030ccbd5bc4SHans Verkuil cp_write(sd, 0xa4, cp_start_eav & 0xff);
1031ccbd5bc4SHans Verkuil
1032ccbd5bc4SHans Verkuil /* active video - vertical timing */
1033ccbd5bc4SHans Verkuil cp_write(sd, 0xa5, (cp_start_vbi >> 4) & 0xff);
1034ccbd5bc4SHans Verkuil cp_write(sd, 0xa6, ((cp_start_vbi & 0xf) << 4) |
1035ccbd5bc4SHans Verkuil ((cp_end_vbi >> 8) & 0xf));
1036ccbd5bc4SHans Verkuil cp_write(sd, 0xa7, cp_end_vbi & 0xff);
10374a31a93aSMats Randgaard } else if (is_digital_input(sd)) {
1038ccbd5bc4SHans Verkuil /* set default prim_mode/vid_std for HDMI
103939c1cb2bSJonathan McCrohan according to [REF_03, c. 4.2] */
1040ccbd5bc4SHans Verkuil io_write(sd, 0x00, 0x02); /* video std */
1041ccbd5bc4SHans Verkuil io_write(sd, 0x01, 0x06); /* prim mode */
10424a31a93aSMats Randgaard } else {
10434a31a93aSMats Randgaard v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n",
10444a31a93aSMats Randgaard __func__, state->selected_input);
1045ccbd5bc4SHans Verkuil }
1046ccbd5bc4SHans Verkuil
1047ccbd5bc4SHans Verkuil cp_write(sd, 0x8f, (ch1_fr_ll >> 8) & 0x7);
1048ccbd5bc4SHans Verkuil cp_write(sd, 0x90, ch1_fr_ll & 0xff);
1049ccbd5bc4SHans Verkuil cp_write(sd, 0xab, (height >> 4) & 0xff);
1050ccbd5bc4SHans Verkuil cp_write(sd, 0xac, (height & 0x0f) << 4);
1051ccbd5bc4SHans Verkuil }
1052ccbd5bc4SHans Verkuil
adv76xx_set_offset(struct v4l2_subdev * sd,bool auto_offset,u16 offset_a,u16 offset_b,u16 offset_c)1053b44b2e06SPablo Anton static void adv76xx_set_offset(struct v4l2_subdev *sd, bool auto_offset, u16 offset_a, u16 offset_b, u16 offset_c)
10545c6c6349SMats Randgaard {
1055b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd);
10565c6c6349SMats Randgaard u8 offset_buf[4];
10575c6c6349SMats Randgaard
10585c6c6349SMats Randgaard if (auto_offset) {
10595c6c6349SMats Randgaard offset_a = 0x3ff;
10605c6c6349SMats Randgaard offset_b = 0x3ff;
10615c6c6349SMats Randgaard offset_c = 0x3ff;
10625c6c6349SMats Randgaard }
10635c6c6349SMats Randgaard
10645c6c6349SMats Randgaard v4l2_dbg(2, debug, sd, "%s: %s offset: a = 0x%x, b = 0x%x, c = 0x%x\n",
10655c6c6349SMats Randgaard __func__, auto_offset ? "Auto" : "Manual",
10665c6c6349SMats Randgaard offset_a, offset_b, offset_c);
10675c6c6349SMats Randgaard
10685c6c6349SMats Randgaard offset_buf[0] = (cp_read(sd, 0x77) & 0xc0) | ((offset_a & 0x3f0) >> 4);
10695c6c6349SMats Randgaard offset_buf[1] = ((offset_a & 0x00f) << 4) | ((offset_b & 0x3c0) >> 6);
10705c6c6349SMats Randgaard offset_buf[2] = ((offset_b & 0x03f) << 2) | ((offset_c & 0x300) >> 8);
10715c6c6349SMats Randgaard offset_buf[3] = offset_c & 0x0ff;
10725c6c6349SMats Randgaard
10735c6c6349SMats Randgaard /* Registers must be written in this order with no i2c access in between */
1074f862f57dSPablo Anton if (regmap_raw_write(state->regmap[ADV76XX_PAGE_CP],
1075f862f57dSPablo Anton 0x77, offset_buf, 4))
10765c6c6349SMats Randgaard v4l2_err(sd, "%s: i2c error writing to CP reg 0x77, 0x78, 0x79, 0x7a\n", __func__);
10775c6c6349SMats Randgaard }
10785c6c6349SMats Randgaard
adv76xx_set_gain(struct v4l2_subdev * sd,bool auto_gain,u16 gain_a,u16 gain_b,u16 gain_c)1079b44b2e06SPablo Anton static void adv76xx_set_gain(struct v4l2_subdev *sd, bool auto_gain, u16 gain_a, u16 gain_b, u16 gain_c)
10805c6c6349SMats Randgaard {
1081b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd);
10825c6c6349SMats Randgaard u8 gain_buf[4];
10835c6c6349SMats Randgaard u8 gain_man = 1;
10845c6c6349SMats Randgaard u8 agc_mode_man = 1;
10855c6c6349SMats Randgaard
10865c6c6349SMats Randgaard if (auto_gain) {
10875c6c6349SMats Randgaard gain_man = 0;
10885c6c6349SMats Randgaard agc_mode_man = 0;
10895c6c6349SMats Randgaard gain_a = 0x100;
10905c6c6349SMats Randgaard gain_b = 0x100;
10915c6c6349SMats Randgaard gain_c = 0x100;
10925c6c6349SMats Randgaard }
10935c6c6349SMats Randgaard
10945c6c6349SMats Randgaard v4l2_dbg(2, debug, sd, "%s: %s gain: a = 0x%x, b = 0x%x, c = 0x%x\n",
10955c6c6349SMats Randgaard __func__, auto_gain ? "Auto" : "Manual",
10965c6c6349SMats Randgaard gain_a, gain_b, gain_c);
10975c6c6349SMats Randgaard
10985c6c6349SMats Randgaard gain_buf[0] = ((gain_man << 7) | (agc_mode_man << 6) | ((gain_a & 0x3f0) >> 4));
10995c6c6349SMats Randgaard gain_buf[1] = (((gain_a & 0x00f) << 4) | ((gain_b & 0x3c0) >> 6));
11005c6c6349SMats Randgaard gain_buf[2] = (((gain_b & 0x03f) << 2) | ((gain_c & 0x300) >> 8));
11015c6c6349SMats Randgaard gain_buf[3] = ((gain_c & 0x0ff));
11025c6c6349SMats Randgaard
11035c6c6349SMats Randgaard /* Registers must be written in this order with no i2c access in between */
1104f862f57dSPablo Anton if (regmap_raw_write(state->regmap[ADV76XX_PAGE_CP],
1105f862f57dSPablo Anton 0x73, gain_buf, 4))
11065c6c6349SMats Randgaard v4l2_err(sd, "%s: i2c error writing to CP reg 0x73, 0x74, 0x75, 0x76\n", __func__);
11075c6c6349SMats Randgaard }
11085c6c6349SMats Randgaard
set_rgb_quantization_range(struct v4l2_subdev * sd)110954450f59SHans Verkuil static void set_rgb_quantization_range(struct v4l2_subdev *sd)
111054450f59SHans Verkuil {
1111b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd);
11125c6c6349SMats Randgaard bool rgb_output = io_read(sd, 0x02) & 0x02;
11135c6c6349SMats Randgaard bool hdmi_signal = hdmi_read(sd, 0x05) & 0x80;
1114fd74246dSHans Verkuil u8 y = HDMI_COLORSPACE_RGB;
1115fd74246dSHans Verkuil
1116fd74246dSHans Verkuil if (hdmi_signal && (io_read(sd, 0x60) & 1))
1117fd74246dSHans Verkuil y = infoframe_read(sd, 0x01) >> 5;
111854450f59SHans Verkuil
11195c6c6349SMats Randgaard v4l2_dbg(2, debug, sd, "%s: RGB quantization range: %d, RGB out: %d, HDMI: %d\n",
11205c6c6349SMats Randgaard __func__, state->rgb_quantization_range,
11215c6c6349SMats Randgaard rgb_output, hdmi_signal);
11225c6c6349SMats Randgaard
1123b44b2e06SPablo Anton adv76xx_set_gain(sd, true, 0x0, 0x0, 0x0);
1124b44b2e06SPablo Anton adv76xx_set_offset(sd, true, 0x0, 0x0, 0x0);
1125fd74246dSHans Verkuil io_write_clr_set(sd, 0x02, 0x04, rgb_output ? 0 : 4);
11269833239eSMats Randgaard
112754450f59SHans Verkuil switch (state->rgb_quantization_range) {
112854450f59SHans Verkuil case V4L2_DV_RGB_RANGE_AUTO:
1129c784b1e2SLaurent Pinchart if (state->selected_input == ADV7604_PAD_VGA_RGB) {
11309833239eSMats Randgaard /* Receiving analog RGB signal
11319833239eSMats Randgaard * Set RGB full range (0-255) */
113222d97e56SLaurent Pinchart io_write_clr_set(sd, 0x02, 0xf0, 0x10);
11339833239eSMats Randgaard break;
11349833239eSMats Randgaard }
113554450f59SHans Verkuil
1136c784b1e2SLaurent Pinchart if (state->selected_input == ADV7604_PAD_VGA_COMP) {
11379833239eSMats Randgaard /* Receiving analog YPbPr signal
11389833239eSMats Randgaard * Set automode */
113922d97e56SLaurent Pinchart io_write_clr_set(sd, 0x02, 0xf0, 0xf0);
11409833239eSMats Randgaard break;
11419833239eSMats Randgaard }
11429833239eSMats Randgaard
11435c6c6349SMats Randgaard if (hdmi_signal) {
11449833239eSMats Randgaard /* Receiving HDMI signal
11459833239eSMats Randgaard * Set automode */
114622d97e56SLaurent Pinchart io_write_clr_set(sd, 0x02, 0xf0, 0xf0);
11479833239eSMats Randgaard break;
11489833239eSMats Randgaard }
11499833239eSMats Randgaard
11509833239eSMats Randgaard /* Receiving DVI-D signal
11519833239eSMats Randgaard * ADV7604 selects RGB limited range regardless of
11529833239eSMats Randgaard * input format (CE/IT) in automatic mode */
1153680fee04SHans Verkuil if (state->timings.bt.flags & V4L2_DV_FL_IS_CE_VIDEO) {
115454450f59SHans Verkuil /* RGB limited range (16-235) */
115522d97e56SLaurent Pinchart io_write_clr_set(sd, 0x02, 0xf0, 0x00);
115654450f59SHans Verkuil } else {
115754450f59SHans Verkuil /* RGB full range (0-255) */
115822d97e56SLaurent Pinchart io_write_clr_set(sd, 0x02, 0xf0, 0x10);
11595c6c6349SMats Randgaard
11605c6c6349SMats Randgaard if (is_digital_input(sd) && rgb_output) {
1161b44b2e06SPablo Anton adv76xx_set_offset(sd, false, 0x40, 0x40, 0x40);
11625c6c6349SMats Randgaard } else {
1163b44b2e06SPablo Anton adv76xx_set_gain(sd, false, 0xe0, 0xe0, 0xe0);
1164b44b2e06SPablo Anton adv76xx_set_offset(sd, false, 0x70, 0x70, 0x70);
11655c6c6349SMats Randgaard }
116654450f59SHans Verkuil }
116754450f59SHans Verkuil break;
116854450f59SHans Verkuil case V4L2_DV_RGB_RANGE_LIMITED:
1169c784b1e2SLaurent Pinchart if (state->selected_input == ADV7604_PAD_VGA_COMP) {
1170d261e842SMats Randgaard /* YCrCb limited range (16-235) */
117122d97e56SLaurent Pinchart io_write_clr_set(sd, 0x02, 0xf0, 0x20);
11725c6c6349SMats Randgaard break;
11735c6c6349SMats Randgaard }
11745c6c6349SMats Randgaard
1175fd74246dSHans Verkuil if (y != HDMI_COLORSPACE_RGB)
1176fd74246dSHans Verkuil break;
1177fd74246dSHans Verkuil
117854450f59SHans Verkuil /* RGB limited range (16-235) */
117922d97e56SLaurent Pinchart io_write_clr_set(sd, 0x02, 0xf0, 0x00);
11805c6c6349SMats Randgaard
118154450f59SHans Verkuil break;
118254450f59SHans Verkuil case V4L2_DV_RGB_RANGE_FULL:
1183c784b1e2SLaurent Pinchart if (state->selected_input == ADV7604_PAD_VGA_COMP) {
1184d261e842SMats Randgaard /* YCrCb full range (0-255) */
118522d97e56SLaurent Pinchart io_write_clr_set(sd, 0x02, 0xf0, 0x60);
11865c6c6349SMats Randgaard break;
11875c6c6349SMats Randgaard }
11885c6c6349SMats Randgaard
1189fd74246dSHans Verkuil if (y != HDMI_COLORSPACE_RGB)
1190fd74246dSHans Verkuil break;
1191fd74246dSHans Verkuil
119254450f59SHans Verkuil /* RGB full range (0-255) */
119322d97e56SLaurent Pinchart io_write_clr_set(sd, 0x02, 0xf0, 0x10);
11945c6c6349SMats Randgaard
11955c6c6349SMats Randgaard if (is_analog_input(sd) || hdmi_signal)
11965c6c6349SMats Randgaard break;
11975c6c6349SMats Randgaard
11985c6c6349SMats Randgaard /* Adjust gain/offset for DVI-D signals only */
11995c6c6349SMats Randgaard if (rgb_output) {
1200b44b2e06SPablo Anton adv76xx_set_offset(sd, false, 0x40, 0x40, 0x40);
12015c6c6349SMats Randgaard } else {
1202b44b2e06SPablo Anton adv76xx_set_gain(sd, false, 0xe0, 0xe0, 0xe0);
1203b44b2e06SPablo Anton adv76xx_set_offset(sd, false, 0x70, 0x70, 0x70);
1204d261e842SMats Randgaard }
120554450f59SHans Verkuil break;
120654450f59SHans Verkuil }
120754450f59SHans Verkuil }
120854450f59SHans Verkuil
adv76xx_s_ctrl(struct v4l2_ctrl * ctrl)1209b44b2e06SPablo Anton static int adv76xx_s_ctrl(struct v4l2_ctrl *ctrl)
121054450f59SHans Verkuil {
1211c269887cSLaurent Pinchart struct v4l2_subdev *sd =
1212b44b2e06SPablo Anton &container_of(ctrl->handler, struct adv76xx_state, hdl)->sd;
1213c269887cSLaurent Pinchart
1214b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd);
121554450f59SHans Verkuil
121654450f59SHans Verkuil switch (ctrl->id) {
121754450f59SHans Verkuil case V4L2_CID_BRIGHTNESS:
121854450f59SHans Verkuil cp_write(sd, 0x3c, ctrl->val);
121954450f59SHans Verkuil return 0;
122054450f59SHans Verkuil case V4L2_CID_CONTRAST:
122154450f59SHans Verkuil cp_write(sd, 0x3a, ctrl->val);
122254450f59SHans Verkuil return 0;
122354450f59SHans Verkuil case V4L2_CID_SATURATION:
122454450f59SHans Verkuil cp_write(sd, 0x3b, ctrl->val);
122554450f59SHans Verkuil return 0;
122654450f59SHans Verkuil case V4L2_CID_HUE:
122754450f59SHans Verkuil cp_write(sd, 0x3d, ctrl->val);
122854450f59SHans Verkuil return 0;
122954450f59SHans Verkuil case V4L2_CID_DV_RX_RGB_RANGE:
123054450f59SHans Verkuil state->rgb_quantization_range = ctrl->val;
123154450f59SHans Verkuil set_rgb_quantization_range(sd);
123254450f59SHans Verkuil return 0;
123354450f59SHans Verkuil case V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE:
1234b44b2e06SPablo Anton if (!adv76xx_has_afe(state))
1235d42010a1SLars-Peter Clausen return -EINVAL;
123654450f59SHans Verkuil /* Set the analog sampling phase. This is needed to find the
123754450f59SHans Verkuil best sampling phase for analog video: an application or
123854450f59SHans Verkuil driver has to try a number of phases and analyze the picture
123954450f59SHans Verkuil quality before settling on the best performing phase. */
124054450f59SHans Verkuil afe_write(sd, 0xc8, ctrl->val);
124154450f59SHans Verkuil return 0;
124254450f59SHans Verkuil case V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL:
124354450f59SHans Verkuil /* Use the default blue color for free running mode,
124454450f59SHans Verkuil or supply your own. */
124522d97e56SLaurent Pinchart cp_write_clr_set(sd, 0xbf, 0x04, ctrl->val << 2);
124654450f59SHans Verkuil return 0;
124754450f59SHans Verkuil case V4L2_CID_ADV_RX_FREE_RUN_COLOR:
124854450f59SHans Verkuil cp_write(sd, 0xc0, (ctrl->val & 0xff0000) >> 16);
124954450f59SHans Verkuil cp_write(sd, 0xc1, (ctrl->val & 0x00ff00) >> 8);
125054450f59SHans Verkuil cp_write(sd, 0xc2, (u8)(ctrl->val & 0x0000ff));
125154450f59SHans Verkuil return 0;
125254450f59SHans Verkuil }
125354450f59SHans Verkuil return -EINVAL;
125454450f59SHans Verkuil }
125554450f59SHans Verkuil
adv76xx_g_volatile_ctrl(struct v4l2_ctrl * ctrl)1256297a4144SHans Verkuil static int adv76xx_g_volatile_ctrl(struct v4l2_ctrl *ctrl)
1257297a4144SHans Verkuil {
1258297a4144SHans Verkuil struct v4l2_subdev *sd =
1259297a4144SHans Verkuil &container_of(ctrl->handler, struct adv76xx_state, hdl)->sd;
1260297a4144SHans Verkuil
1261297a4144SHans Verkuil if (ctrl->id == V4L2_CID_DV_RX_IT_CONTENT_TYPE) {
1262297a4144SHans Verkuil ctrl->val = V4L2_DV_IT_CONTENT_TYPE_NO_ITC;
1263297a4144SHans Verkuil if ((io_read(sd, 0x60) & 1) && (infoframe_read(sd, 0x03) & 0x80))
1264297a4144SHans Verkuil ctrl->val = (infoframe_read(sd, 0x05) >> 4) & 3;
1265297a4144SHans Verkuil return 0;
1266297a4144SHans Verkuil }
1267297a4144SHans Verkuil return -EINVAL;
1268297a4144SHans Verkuil }
1269297a4144SHans Verkuil
127054450f59SHans Verkuil /* ----------------------------------------------------------------------- */
127154450f59SHans Verkuil
no_power(struct v4l2_subdev * sd)127254450f59SHans Verkuil static inline bool no_power(struct v4l2_subdev *sd)
127354450f59SHans Verkuil {
127454450f59SHans Verkuil /* Entire chip or CP powered off */
127554450f59SHans Verkuil return io_read(sd, 0x0c) & 0x24;
127654450f59SHans Verkuil }
127754450f59SHans Verkuil
no_signal_tmds(struct v4l2_subdev * sd)127854450f59SHans Verkuil static inline bool no_signal_tmds(struct v4l2_subdev *sd)
127954450f59SHans Verkuil {
1280b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd);
12814a31a93aSMats Randgaard
12824a31a93aSMats Randgaard return !(io_read(sd, 0x6a) & (0x10 >> state->selected_input));
128354450f59SHans Verkuil }
128454450f59SHans Verkuil
no_lock_tmds(struct v4l2_subdev * sd)128554450f59SHans Verkuil static inline bool no_lock_tmds(struct v4l2_subdev *sd)
128654450f59SHans Verkuil {
1287b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd);
1288b44b2e06SPablo Anton const struct adv76xx_chip_info *info = state->info;
1289d42010a1SLars-Peter Clausen
1290d42010a1SLars-Peter Clausen return (io_read(sd, 0x6a) & info->tdms_lock_mask) != info->tdms_lock_mask;
129154450f59SHans Verkuil }
129254450f59SHans Verkuil
is_hdmi(struct v4l2_subdev * sd)1293bb88f325SMartin Bugge static inline bool is_hdmi(struct v4l2_subdev *sd)
1294bb88f325SMartin Bugge {
1295bb88f325SMartin Bugge return hdmi_read(sd, 0x05) & 0x80;
1296bb88f325SMartin Bugge }
1297bb88f325SMartin Bugge
no_lock_sspd(struct v4l2_subdev * sd)129854450f59SHans Verkuil static inline bool no_lock_sspd(struct v4l2_subdev *sd)
129954450f59SHans Verkuil {
1300b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd);
1301d42010a1SLars-Peter Clausen
1302d42010a1SLars-Peter Clausen /*
1303d42010a1SLars-Peter Clausen * Chips without a AFE don't expose registers for the SSPD, so just assume
1304d42010a1SLars-Peter Clausen * that we have a lock.
1305d42010a1SLars-Peter Clausen */
1306b44b2e06SPablo Anton if (adv76xx_has_afe(state))
1307d42010a1SLars-Peter Clausen return false;
1308d42010a1SLars-Peter Clausen
130954450f59SHans Verkuil /* TODO channel 2 */
131054450f59SHans Verkuil return ((cp_read(sd, 0xb5) & 0xd0) != 0xd0);
131154450f59SHans Verkuil }
131254450f59SHans Verkuil
no_lock_stdi(struct v4l2_subdev * sd)131354450f59SHans Verkuil static inline bool no_lock_stdi(struct v4l2_subdev *sd)
131454450f59SHans Verkuil {
131554450f59SHans Verkuil /* TODO channel 2 */
131654450f59SHans Verkuil return !(cp_read(sd, 0xb1) & 0x80);
131754450f59SHans Verkuil }
131854450f59SHans Verkuil
no_signal(struct v4l2_subdev * sd)131954450f59SHans Verkuil static inline bool no_signal(struct v4l2_subdev *sd)
132054450f59SHans Verkuil {
132154450f59SHans Verkuil bool ret;
132254450f59SHans Verkuil
132354450f59SHans Verkuil ret = no_power(sd);
132454450f59SHans Verkuil
132554450f59SHans Verkuil ret |= no_lock_stdi(sd);
132654450f59SHans Verkuil ret |= no_lock_sspd(sd);
132754450f59SHans Verkuil
13284a31a93aSMats Randgaard if (is_digital_input(sd)) {
132954450f59SHans Verkuil ret |= no_lock_tmds(sd);
133054450f59SHans Verkuil ret |= no_signal_tmds(sd);
133154450f59SHans Verkuil }
133254450f59SHans Verkuil
133354450f59SHans Verkuil return ret;
133454450f59SHans Verkuil }
133554450f59SHans Verkuil
no_lock_cp(struct v4l2_subdev * sd)133654450f59SHans Verkuil static inline bool no_lock_cp(struct v4l2_subdev *sd)
133754450f59SHans Verkuil {
1338b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd);
1339d42010a1SLars-Peter Clausen
1340b44b2e06SPablo Anton if (!adv76xx_has_afe(state))
1341d42010a1SLars-Peter Clausen return false;
1342d42010a1SLars-Peter Clausen
134354450f59SHans Verkuil /* CP has detected a non standard number of lines on the incoming
134454450f59SHans Verkuil video compared to what it is configured to receive by s_dv_timings */
134554450f59SHans Verkuil return io_read(sd, 0x12) & 0x01;
134654450f59SHans Verkuil }
134754450f59SHans Verkuil
in_free_run(struct v4l2_subdev * sd)134858514625Sjean-michel.hautbois@vodalys.com static inline bool in_free_run(struct v4l2_subdev *sd)
134958514625Sjean-michel.hautbois@vodalys.com {
135058514625Sjean-michel.hautbois@vodalys.com return cp_read(sd, 0xff) & 0x10;
135158514625Sjean-michel.hautbois@vodalys.com }
135258514625Sjean-michel.hautbois@vodalys.com
adv76xx_g_input_status(struct v4l2_subdev * sd,u32 * status)1353b44b2e06SPablo Anton static int adv76xx_g_input_status(struct v4l2_subdev *sd, u32 *status)
135454450f59SHans Verkuil {
135554450f59SHans Verkuil *status = 0;
135654450f59SHans Verkuil *status |= no_power(sd) ? V4L2_IN_ST_NO_POWER : 0;
135754450f59SHans Verkuil *status |= no_signal(sd) ? V4L2_IN_ST_NO_SIGNAL : 0;
135858514625Sjean-michel.hautbois@vodalys.com if (!in_free_run(sd) && no_lock_cp(sd))
135958514625Sjean-michel.hautbois@vodalys.com *status |= is_digital_input(sd) ?
136058514625Sjean-michel.hautbois@vodalys.com V4L2_IN_ST_NO_SYNC : V4L2_IN_ST_NO_H_LOCK;
136154450f59SHans Verkuil
136254450f59SHans Verkuil v4l2_dbg(1, debug, sd, "%s: status = 0x%x\n", __func__, *status);
136354450f59SHans Verkuil
136454450f59SHans Verkuil return 0;
136554450f59SHans Verkuil }
136654450f59SHans Verkuil
136754450f59SHans Verkuil /* ----------------------------------------------------------------------- */
136854450f59SHans Verkuil
136954450f59SHans Verkuil struct stdi_readback {
137054450f59SHans Verkuil u16 bl, lcf, lcvs;
137154450f59SHans Verkuil u8 hs_pol, vs_pol;
137254450f59SHans Verkuil bool interlaced;
137354450f59SHans Verkuil };
137454450f59SHans Verkuil
stdi2dv_timings(struct v4l2_subdev * sd,struct stdi_readback * stdi,struct v4l2_dv_timings * timings)137554450f59SHans Verkuil static int stdi2dv_timings(struct v4l2_subdev *sd,
137654450f59SHans Verkuil struct stdi_readback *stdi,
137754450f59SHans Verkuil struct v4l2_dv_timings *timings)
137854450f59SHans Verkuil {
1379b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd);
1380b44b2e06SPablo Anton u32 hfreq = (ADV76XX_FSC * 8) / stdi->bl;
138154450f59SHans Verkuil u32 pix_clk;
138254450f59SHans Verkuil int i;
138354450f59SHans Verkuil
1384bd3e275fSJean-Michel Hautbois for (i = 0; v4l2_dv_timings_presets[i].bt.width; i++) {
1385bd3e275fSJean-Michel Hautbois const struct v4l2_bt_timings *bt = &v4l2_dv_timings_presets[i].bt;
1386bd3e275fSJean-Michel Hautbois
1387bd3e275fSJean-Michel Hautbois if (!v4l2_valid_dv_timings(&v4l2_dv_timings_presets[i],
13889c41e690SLaurent Pinchart adv76xx_get_dv_timings_cap(sd, -1),
1389bd3e275fSJean-Michel Hautbois adv76xx_check_dv_timings, NULL))
139054450f59SHans Verkuil continue;
1391bd3e275fSJean-Michel Hautbois if (vtotal(bt) != stdi->lcf + 1)
1392bd3e275fSJean-Michel Hautbois continue;
1393bd3e275fSJean-Michel Hautbois if (bt->vsync != stdi->lcvs)
139454450f59SHans Verkuil continue;
139554450f59SHans Verkuil
1396bd3e275fSJean-Michel Hautbois pix_clk = hfreq * htotal(bt);
139754450f59SHans Verkuil
1398bd3e275fSJean-Michel Hautbois if ((pix_clk < bt->pixelclock + 1000000) &&
1399bd3e275fSJean-Michel Hautbois (pix_clk > bt->pixelclock - 1000000)) {
1400bd3e275fSJean-Michel Hautbois *timings = v4l2_dv_timings_presets[i];
140154450f59SHans Verkuil return 0;
140254450f59SHans Verkuil }
140354450f59SHans Verkuil }
140454450f59SHans Verkuil
14055fea1bb7SPrashant Laddha if (v4l2_detect_cvt(stdi->lcf + 1, hfreq, stdi->lcvs, 0,
140654450f59SHans Verkuil (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) |
140754450f59SHans Verkuil (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0),
1408061ddda6SPrashant Laddha false, timings))
140954450f59SHans Verkuil return 0;
141054450f59SHans Verkuil if (v4l2_detect_gtf(stdi->lcf + 1, hfreq, stdi->lcvs,
141154450f59SHans Verkuil (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) |
141254450f59SHans Verkuil (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0),
1413061ddda6SPrashant Laddha false, state->aspect_ratio, timings))
141454450f59SHans Verkuil return 0;
141554450f59SHans Verkuil
1416ccbd5bc4SHans Verkuil v4l2_dbg(2, debug, sd,
1417ccbd5bc4SHans Verkuil "%s: No format candidate found for lcvs = %d, lcf=%d, bl = %d, %chsync, %cvsync\n",
1418ccbd5bc4SHans Verkuil __func__, stdi->lcvs, stdi->lcf, stdi->bl,
1419ccbd5bc4SHans Verkuil stdi->hs_pol, stdi->vs_pol);
142054450f59SHans Verkuil return -1;
142154450f59SHans Verkuil }
142254450f59SHans Verkuil
1423d42010a1SLars-Peter Clausen
read_stdi(struct v4l2_subdev * sd,struct stdi_readback * stdi)142454450f59SHans Verkuil static int read_stdi(struct v4l2_subdev *sd, struct stdi_readback *stdi)
142554450f59SHans Verkuil {
1426b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd);
1427b44b2e06SPablo Anton const struct adv76xx_chip_info *info = state->info;
14284a2ccdd2SLaurent Pinchart u8 polarity;
14294a2ccdd2SLaurent Pinchart
143054450f59SHans Verkuil if (no_lock_stdi(sd) || no_lock_sspd(sd)) {
143154450f59SHans Verkuil v4l2_dbg(2, debug, sd, "%s: STDI and/or SSPD not locked\n", __func__);
143254450f59SHans Verkuil return -1;
143354450f59SHans Verkuil }
143454450f59SHans Verkuil
143554450f59SHans Verkuil /* read STDI */
143651182a94SLaurent Pinchart stdi->bl = cp_read16(sd, 0xb1, 0x3fff);
1437d42010a1SLars-Peter Clausen stdi->lcf = cp_read16(sd, info->lcf_reg, 0x7ff);
143854450f59SHans Verkuil stdi->lcvs = cp_read(sd, 0xb3) >> 3;
143954450f59SHans Verkuil stdi->interlaced = io_read(sd, 0x12) & 0x10;
144054450f59SHans Verkuil
1441b44b2e06SPablo Anton if (adv76xx_has_afe(state)) {
144254450f59SHans Verkuil /* read SSPD */
14434a2ccdd2SLaurent Pinchart polarity = cp_read(sd, 0xb5);
14444a2ccdd2SLaurent Pinchart if ((polarity & 0x03) == 0x01) {
14454a2ccdd2SLaurent Pinchart stdi->hs_pol = polarity & 0x10
14464a2ccdd2SLaurent Pinchart ? (polarity & 0x08 ? '+' : '-') : 'x';
14474a2ccdd2SLaurent Pinchart stdi->vs_pol = polarity & 0x40
14484a2ccdd2SLaurent Pinchart ? (polarity & 0x20 ? '+' : '-') : 'x';
144954450f59SHans Verkuil } else {
145054450f59SHans Verkuil stdi->hs_pol = 'x';
145154450f59SHans Verkuil stdi->vs_pol = 'x';
145254450f59SHans Verkuil }
1453d42010a1SLars-Peter Clausen } else {
1454d42010a1SLars-Peter Clausen polarity = hdmi_read(sd, 0x05);
1455d42010a1SLars-Peter Clausen stdi->hs_pol = polarity & 0x20 ? '+' : '-';
1456d42010a1SLars-Peter Clausen stdi->vs_pol = polarity & 0x10 ? '+' : '-';
1457d42010a1SLars-Peter Clausen }
145854450f59SHans Verkuil
145954450f59SHans Verkuil if (no_lock_stdi(sd) || no_lock_sspd(sd)) {
146054450f59SHans Verkuil v4l2_dbg(2, debug, sd,
146154450f59SHans Verkuil "%s: signal lost during readout of STDI/SSPD\n", __func__);
146254450f59SHans Verkuil return -1;
146354450f59SHans Verkuil }
146454450f59SHans Verkuil
146554450f59SHans Verkuil if (stdi->lcf < 239 || stdi->bl < 8 || stdi->bl == 0x3fff) {
146654450f59SHans Verkuil v4l2_dbg(2, debug, sd, "%s: invalid signal\n", __func__);
146754450f59SHans Verkuil memset(stdi, 0, sizeof(struct stdi_readback));
146854450f59SHans Verkuil return -1;
146954450f59SHans Verkuil }
147054450f59SHans Verkuil
147154450f59SHans Verkuil v4l2_dbg(2, debug, sd,
147254450f59SHans Verkuil "%s: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %chsync, %cvsync, %s\n",
147354450f59SHans Verkuil __func__, stdi->lcf, stdi->bl, stdi->lcvs,
147454450f59SHans Verkuil stdi->hs_pol, stdi->vs_pol,
147554450f59SHans Verkuil stdi->interlaced ? "interlaced" : "progressive");
147654450f59SHans Verkuil
147754450f59SHans Verkuil return 0;
147854450f59SHans Verkuil }
147954450f59SHans Verkuil
adv76xx_enum_dv_timings(struct v4l2_subdev * sd,struct v4l2_enum_dv_timings * timings)1480b44b2e06SPablo Anton static int adv76xx_enum_dv_timings(struct v4l2_subdev *sd,
148154450f59SHans Verkuil struct v4l2_enum_dv_timings *timings)
148254450f59SHans Verkuil {
1483b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd);
1484afec5599SLaurent Pinchart
1485afec5599SLaurent Pinchart if (timings->pad >= state->source_pad)
1486afec5599SLaurent Pinchart return -EINVAL;
1487afec5599SLaurent Pinchart
1488bd3e275fSJean-Michel Hautbois return v4l2_enum_dv_timings_cap(timings,
14899c41e690SLaurent Pinchart adv76xx_get_dv_timings_cap(sd, timings->pad),
14909c41e690SLaurent Pinchart adv76xx_check_dv_timings, NULL);
149154450f59SHans Verkuil }
149254450f59SHans Verkuil
adv76xx_dv_timings_cap(struct v4l2_subdev * sd,struct v4l2_dv_timings_cap * cap)1493b44b2e06SPablo Anton static int adv76xx_dv_timings_cap(struct v4l2_subdev *sd,
14947515e096SLaurent Pinchart struct v4l2_dv_timings_cap *cap)
1495afec5599SLaurent Pinchart {
1496b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd);
14979c41e690SLaurent Pinchart unsigned int pad = cap->pad;
14987515e096SLaurent Pinchart
14997515e096SLaurent Pinchart if (cap->pad >= state->source_pad)
15007515e096SLaurent Pinchart return -EINVAL;
15017515e096SLaurent Pinchart
15029c41e690SLaurent Pinchart *cap = *adv76xx_get_dv_timings_cap(sd, pad);
15039c41e690SLaurent Pinchart cap->pad = pad;
15049c41e690SLaurent Pinchart
1505afec5599SLaurent Pinchart return 0;
1506afec5599SLaurent Pinchart }
1507afec5599SLaurent Pinchart
150854450f59SHans Verkuil /* Fill the optional fields .standards and .flags in struct v4l2_dv_timings
1509b44b2e06SPablo Anton if the format is listed in adv76xx_timings[] */
adv76xx_fill_optional_dv_timings_fields(struct v4l2_subdev * sd,struct v4l2_dv_timings * timings)1510b44b2e06SPablo Anton static void adv76xx_fill_optional_dv_timings_fields(struct v4l2_subdev *sd,
151154450f59SHans Verkuil struct v4l2_dv_timings *timings)
151254450f59SHans Verkuil {
15139c41e690SLaurent Pinchart v4l2_find_dv_timings_cap(timings, adv76xx_get_dv_timings_cap(sd, -1),
1514bd3e275fSJean-Michel Hautbois is_digital_input(sd) ? 250000 : 1000000,
1515bd3e275fSJean-Michel Hautbois adv76xx_check_dv_timings, NULL);
151654450f59SHans Verkuil }
151754450f59SHans Verkuil
adv7604_read_hdmi_pixelclock(struct v4l2_subdev * sd)1518d42010a1SLars-Peter Clausen static unsigned int adv7604_read_hdmi_pixelclock(struct v4l2_subdev *sd)
1519d42010a1SLars-Peter Clausen {
1520d42010a1SLars-Peter Clausen int a, b;
1521d42010a1SLars-Peter Clausen
1522d42010a1SLars-Peter Clausen a = hdmi_read(sd, 0x06);
1523d42010a1SLars-Peter Clausen b = hdmi_read(sd, 0x3b);
1524d42010a1SLars-Peter Clausen if (a < 0 || b < 0)
1525d42010a1SLars-Peter Clausen return 0;
1526d42010a1SLars-Peter Clausen
1527961f97abSDragos Bogdan return a * 1000000 + ((b & 0x30) >> 4) * 250000;
1528d42010a1SLars-Peter Clausen }
1529d42010a1SLars-Peter Clausen
adv7611_read_hdmi_pixelclock(struct v4l2_subdev * sd)1530d42010a1SLars-Peter Clausen static unsigned int adv7611_read_hdmi_pixelclock(struct v4l2_subdev *sd)
1531d42010a1SLars-Peter Clausen {
1532d42010a1SLars-Peter Clausen int a, b;
1533d42010a1SLars-Peter Clausen
1534d42010a1SLars-Peter Clausen a = hdmi_read(sd, 0x51);
1535d42010a1SLars-Peter Clausen b = hdmi_read(sd, 0x52);
1536d42010a1SLars-Peter Clausen if (a < 0 || b < 0)
1537d42010a1SLars-Peter Clausen return 0;
1538961f97abSDragos Bogdan
1539d42010a1SLars-Peter Clausen return ((a << 1) | (b >> 7)) * 1000000 + (b & 0x7f) * 1000000 / 128;
1540d42010a1SLars-Peter Clausen }
1541d42010a1SLars-Peter Clausen
adv76xx_read_hdmi_pixelclock(struct v4l2_subdev * sd)1542961f97abSDragos Bogdan static unsigned int adv76xx_read_hdmi_pixelclock(struct v4l2_subdev *sd)
1543961f97abSDragos Bogdan {
1544961f97abSDragos Bogdan struct adv76xx_state *state = to_state(sd);
1545961f97abSDragos Bogdan const struct adv76xx_chip_info *info = state->info;
1546961f97abSDragos Bogdan unsigned int freq, bits_per_channel, pixelrepetition;
1547961f97abSDragos Bogdan
1548961f97abSDragos Bogdan freq = info->read_hdmi_pixelclock(sd);
1549961f97abSDragos Bogdan if (is_hdmi(sd)) {
1550961f97abSDragos Bogdan /* adjust for deep color mode and pixel repetition */
1551961f97abSDragos Bogdan bits_per_channel = ((hdmi_read(sd, 0x0b) & 0x60) >> 4) + 8;
1552961f97abSDragos Bogdan pixelrepetition = (hdmi_read(sd, 0x05) & 0x0f) + 1;
1553961f97abSDragos Bogdan
1554961f97abSDragos Bogdan freq = freq * 8 / bits_per_channel / pixelrepetition;
1555961f97abSDragos Bogdan }
1556961f97abSDragos Bogdan
1557961f97abSDragos Bogdan return freq;
1558961f97abSDragos Bogdan }
1559961f97abSDragos Bogdan
adv76xx_query_dv_timings(struct v4l2_subdev * sd,struct v4l2_dv_timings * timings)1560b44b2e06SPablo Anton static int adv76xx_query_dv_timings(struct v4l2_subdev *sd,
156154450f59SHans Verkuil struct v4l2_dv_timings *timings)
156254450f59SHans Verkuil {
1563b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd);
1564b44b2e06SPablo Anton const struct adv76xx_chip_info *info = state->info;
156554450f59SHans Verkuil struct v4l2_bt_timings *bt = &timings->bt;
156654450f59SHans Verkuil struct stdi_readback stdi;
156754450f59SHans Verkuil
156854450f59SHans Verkuil if (!timings)
156954450f59SHans Verkuil return -EINVAL;
157054450f59SHans Verkuil
157154450f59SHans Verkuil memset(timings, 0, sizeof(struct v4l2_dv_timings));
157254450f59SHans Verkuil
157354450f59SHans Verkuil if (no_signal(sd)) {
15741e0b9156SMartin Bugge state->restart_stdi_once = true;
157554450f59SHans Verkuil v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__);
157654450f59SHans Verkuil return -ENOLINK;
157754450f59SHans Verkuil }
157854450f59SHans Verkuil
157954450f59SHans Verkuil /* read STDI */
158054450f59SHans Verkuil if (read_stdi(sd, &stdi)) {
158154450f59SHans Verkuil v4l2_dbg(1, debug, sd, "%s: STDI/SSPD not locked\n", __func__);
158254450f59SHans Verkuil return -ENOLINK;
158354450f59SHans Verkuil }
158454450f59SHans Verkuil bt->interlaced = stdi.interlaced ?
158554450f59SHans Verkuil V4L2_DV_INTERLACED : V4L2_DV_PROGRESSIVE;
158654450f59SHans Verkuil
15874a31a93aSMats Randgaard if (is_digital_input(sd)) {
1588827c1f52SHans Verkuil bool hdmi_signal = hdmi_read(sd, 0x05) & 0x80;
1589827c1f52SHans Verkuil u8 vic = 0;
1590827c1f52SHans Verkuil u32 w, h;
1591827c1f52SHans Verkuil
1592827c1f52SHans Verkuil w = hdmi_read16(sd, 0x07, info->linewidth_mask);
1593827c1f52SHans Verkuil h = hdmi_read16(sd, 0x09, info->field0_height_mask);
1594827c1f52SHans Verkuil
1595827c1f52SHans Verkuil if (hdmi_signal && (io_read(sd, 0x60) & 1))
1596827c1f52SHans Verkuil vic = infoframe_read(sd, 0x04);
1597827c1f52SHans Verkuil
1598827c1f52SHans Verkuil if (vic && v4l2_find_dv_timings_cea861_vic(timings, vic) &&
1599827c1f52SHans Verkuil bt->width == w && bt->height == h)
1600827c1f52SHans Verkuil goto found;
1601827c1f52SHans Verkuil
160254450f59SHans Verkuil timings->type = V4L2_DV_BT_656_1120;
160354450f59SHans Verkuil
1604827c1f52SHans Verkuil bt->width = w;
1605827c1f52SHans Verkuil bt->height = h;
1606961f97abSDragos Bogdan bt->pixelclock = adv76xx_read_hdmi_pixelclock(sd);
16075380baafSjean-michel.hautbois@vodalys.com bt->hfrontporch = hdmi_read16(sd, 0x20, info->hfrontporch_mask);
16085380baafSjean-michel.hautbois@vodalys.com bt->hsync = hdmi_read16(sd, 0x22, info->hsync_mask);
16095380baafSjean-michel.hautbois@vodalys.com bt->hbackporch = hdmi_read16(sd, 0x24, info->hbackporch_mask);
16105380baafSjean-michel.hautbois@vodalys.com bt->vfrontporch = hdmi_read16(sd, 0x2a,
16115380baafSjean-michel.hautbois@vodalys.com info->field0_vfrontporch_mask) / 2;
16125380baafSjean-michel.hautbois@vodalys.com bt->vsync = hdmi_read16(sd, 0x2e, info->field0_vsync_mask) / 2;
16135380baafSjean-michel.hautbois@vodalys.com bt->vbackporch = hdmi_read16(sd, 0x32,
16145380baafSjean-michel.hautbois@vodalys.com info->field0_vbackporch_mask) / 2;
161554450f59SHans Verkuil bt->polarities = ((hdmi_read(sd, 0x05) & 0x10) ? V4L2_DV_VSYNC_POS_POL : 0) |
161654450f59SHans Verkuil ((hdmi_read(sd, 0x05) & 0x20) ? V4L2_DV_HSYNC_POS_POL : 0);
161754450f59SHans Verkuil if (bt->interlaced == V4L2_DV_INTERLACED) {
16185380baafSjean-michel.hautbois@vodalys.com bt->height += hdmi_read16(sd, 0x0b,
16195380baafSjean-michel.hautbois@vodalys.com info->field1_height_mask);
16205380baafSjean-michel.hautbois@vodalys.com bt->il_vfrontporch = hdmi_read16(sd, 0x2c,
16215380baafSjean-michel.hautbois@vodalys.com info->field1_vfrontporch_mask) / 2;
16225380baafSjean-michel.hautbois@vodalys.com bt->il_vsync = hdmi_read16(sd, 0x30,
16235380baafSjean-michel.hautbois@vodalys.com info->field1_vsync_mask) / 2;
16245380baafSjean-michel.hautbois@vodalys.com bt->il_vbackporch = hdmi_read16(sd, 0x34,
16255380baafSjean-michel.hautbois@vodalys.com info->field1_vbackporch_mask) / 2;
162654450f59SHans Verkuil }
1627b44b2e06SPablo Anton adv76xx_fill_optional_dv_timings_fields(sd, timings);
162854450f59SHans Verkuil } else {
162954450f59SHans Verkuil /* find format
163080939647SHans Verkuil * Since LCVS values are inaccurate [REF_03, p. 275-276],
163154450f59SHans Verkuil * stdi2dv_timings() is called with lcvs +-1 if the first attempt fails.
163254450f59SHans Verkuil */
163354450f59SHans Verkuil if (!stdi2dv_timings(sd, &stdi, timings))
163454450f59SHans Verkuil goto found;
163554450f59SHans Verkuil stdi.lcvs += 1;
163654450f59SHans Verkuil v4l2_dbg(1, debug, sd, "%s: lcvs + 1 = %d\n", __func__, stdi.lcvs);
163754450f59SHans Verkuil if (!stdi2dv_timings(sd, &stdi, timings))
163854450f59SHans Verkuil goto found;
163954450f59SHans Verkuil stdi.lcvs -= 2;
164054450f59SHans Verkuil v4l2_dbg(1, debug, sd, "%s: lcvs - 1 = %d\n", __func__, stdi.lcvs);
164154450f59SHans Verkuil if (stdi2dv_timings(sd, &stdi, timings)) {
1642cf9afb1dSHans Verkuil /*
1643cf9afb1dSHans Verkuil * The STDI block may measure wrong values, especially
1644cf9afb1dSHans Verkuil * for lcvs and lcf. If the driver can not find any
1645cf9afb1dSHans Verkuil * valid timing, the STDI block is restarted to measure
1646cf9afb1dSHans Verkuil * the video timings again. The function will return an
1647cf9afb1dSHans Verkuil * error, but the restart of STDI will generate a new
1648cf9afb1dSHans Verkuil * STDI interrupt and the format detection process will
1649cf9afb1dSHans Verkuil * restart.
1650cf9afb1dSHans Verkuil */
1651cf9afb1dSHans Verkuil if (state->restart_stdi_once) {
1652cf9afb1dSHans Verkuil v4l2_dbg(1, debug, sd, "%s: restart STDI\n", __func__);
1653cf9afb1dSHans Verkuil /* TODO restart STDI for Sync Channel 2 */
1654cf9afb1dSHans Verkuil /* enter one-shot mode */
165522d97e56SLaurent Pinchart cp_write_clr_set(sd, 0x86, 0x06, 0x00);
1656cf9afb1dSHans Verkuil /* trigger STDI restart */
165722d97e56SLaurent Pinchart cp_write_clr_set(sd, 0x86, 0x06, 0x04);
1658cf9afb1dSHans Verkuil /* reset to continuous mode */
165922d97e56SLaurent Pinchart cp_write_clr_set(sd, 0x86, 0x06, 0x02);
1660cf9afb1dSHans Verkuil state->restart_stdi_once = false;
1661cf9afb1dSHans Verkuil return -ENOLINK;
1662cf9afb1dSHans Verkuil }
166354450f59SHans Verkuil v4l2_dbg(1, debug, sd, "%s: format not supported\n", __func__);
166454450f59SHans Verkuil return -ERANGE;
166554450f59SHans Verkuil }
1666cf9afb1dSHans Verkuil state->restart_stdi_once = true;
166754450f59SHans Verkuil }
166854450f59SHans Verkuil found:
166954450f59SHans Verkuil
167054450f59SHans Verkuil if (no_signal(sd)) {
167154450f59SHans Verkuil v4l2_dbg(1, debug, sd, "%s: signal lost during readout\n", __func__);
167254450f59SHans Verkuil memset(timings, 0, sizeof(struct v4l2_dv_timings));
167354450f59SHans Verkuil return -ENOLINK;
167454450f59SHans Verkuil }
167554450f59SHans Verkuil
16764a31a93aSMats Randgaard if ((is_analog_input(sd) && bt->pixelclock > 170000000) ||
16774a31a93aSMats Randgaard (is_digital_input(sd) && bt->pixelclock > 225000000)) {
167854450f59SHans Verkuil v4l2_dbg(1, debug, sd, "%s: pixelclock out of range %d\n",
167954450f59SHans Verkuil __func__, (u32)bt->pixelclock);
168054450f59SHans Verkuil return -ERANGE;
168154450f59SHans Verkuil }
168254450f59SHans Verkuil
168354450f59SHans Verkuil if (debug > 1)
1684b44b2e06SPablo Anton v4l2_print_dv_timings(sd->name, "adv76xx_query_dv_timings: ",
168511d034c8SHans Verkuil timings, true);
168654450f59SHans Verkuil
168754450f59SHans Verkuil return 0;
168854450f59SHans Verkuil }
168954450f59SHans Verkuil
adv76xx_s_dv_timings(struct v4l2_subdev * sd,struct v4l2_dv_timings * timings)1690b44b2e06SPablo Anton static int adv76xx_s_dv_timings(struct v4l2_subdev *sd,
169154450f59SHans Verkuil struct v4l2_dv_timings *timings)
169254450f59SHans Verkuil {
1693b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd);
169454450f59SHans Verkuil struct v4l2_bt_timings *bt;
1695ccbd5bc4SHans Verkuil int err;
169654450f59SHans Verkuil
169754450f59SHans Verkuil if (!timings)
169854450f59SHans Verkuil return -EINVAL;
169954450f59SHans Verkuil
170085f9e06cSHans Verkuil if (v4l2_match_dv_timings(&state->timings, timings, 0, false)) {
1701d48eb48cSMats Randgaard v4l2_dbg(1, debug, sd, "%s: no change\n", __func__);
1702d48eb48cSMats Randgaard return 0;
1703d48eb48cSMats Randgaard }
1704d48eb48cSMats Randgaard
170554450f59SHans Verkuil bt = &timings->bt;
170654450f59SHans Verkuil
17079c41e690SLaurent Pinchart if (!v4l2_valid_dv_timings(timings, adv76xx_get_dv_timings_cap(sd, -1),
1708bd3e275fSJean-Michel Hautbois adv76xx_check_dv_timings, NULL))
170954450f59SHans Verkuil return -ERANGE;
1710ccbd5bc4SHans Verkuil
1711b44b2e06SPablo Anton adv76xx_fill_optional_dv_timings_fields(sd, timings);
171254450f59SHans Verkuil
171354450f59SHans Verkuil state->timings = *timings;
171454450f59SHans Verkuil
171522d97e56SLaurent Pinchart cp_write_clr_set(sd, 0x91, 0x40, bt->interlaced ? 0x40 : 0x00);
1716ccbd5bc4SHans Verkuil
1717ccbd5bc4SHans Verkuil /* Use prim_mode and vid_std when available */
1718ccbd5bc4SHans Verkuil err = configure_predefined_video_timings(sd, timings);
1719ccbd5bc4SHans Verkuil if (err) {
1720ccbd5bc4SHans Verkuil /* custom settings when the video format
1721ccbd5bc4SHans Verkuil does not have prim_mode/vid_std */
1722ccbd5bc4SHans Verkuil configure_custom_video_timings(sd, bt);
1723ccbd5bc4SHans Verkuil }
172454450f59SHans Verkuil
172554450f59SHans Verkuil set_rgb_quantization_range(sd);
172654450f59SHans Verkuil
172754450f59SHans Verkuil if (debug > 1)
1728b44b2e06SPablo Anton v4l2_print_dv_timings(sd->name, "adv76xx_s_dv_timings: ",
172911d034c8SHans Verkuil timings, true);
173054450f59SHans Verkuil return 0;
173154450f59SHans Verkuil }
173254450f59SHans Verkuil
adv76xx_g_dv_timings(struct v4l2_subdev * sd,struct v4l2_dv_timings * timings)1733b44b2e06SPablo Anton static int adv76xx_g_dv_timings(struct v4l2_subdev *sd,
173454450f59SHans Verkuil struct v4l2_dv_timings *timings)
173554450f59SHans Verkuil {
1736b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd);
173754450f59SHans Verkuil
173854450f59SHans Verkuil *timings = state->timings;
173954450f59SHans Verkuil return 0;
174054450f59SHans Verkuil }
174154450f59SHans Verkuil
adv7604_set_termination(struct v4l2_subdev * sd,bool enable)1742d42010a1SLars-Peter Clausen static void adv7604_set_termination(struct v4l2_subdev *sd, bool enable)
1743d42010a1SLars-Peter Clausen {
1744d42010a1SLars-Peter Clausen hdmi_write(sd, 0x01, enable ? 0x00 : 0x78);
1745d42010a1SLars-Peter Clausen }
1746d42010a1SLars-Peter Clausen
adv7611_set_termination(struct v4l2_subdev * sd,bool enable)1747d42010a1SLars-Peter Clausen static void adv7611_set_termination(struct v4l2_subdev *sd, bool enable)
1748d42010a1SLars-Peter Clausen {
1749d42010a1SLars-Peter Clausen hdmi_write(sd, 0x83, enable ? 0xfe : 0xff);
1750d42010a1SLars-Peter Clausen }
1751d42010a1SLars-Peter Clausen
enable_input(struct v4l2_subdev * sd)17526b0d5d34SHans Verkuil static void enable_input(struct v4l2_subdev *sd)
175354450f59SHans Verkuil {
1754b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd);
17556b0d5d34SHans Verkuil
17564a31a93aSMats Randgaard if (is_analog_input(sd)) {
175754450f59SHans Verkuil io_write(sd, 0x15, 0xb0); /* Disable Tristate of Pins (no audio) */
17584a31a93aSMats Randgaard } else if (is_digital_input(sd)) {
175922d97e56SLaurent Pinchart hdmi_write_clr_set(sd, 0x00, 0x03, state->selected_input);
1760d42010a1SLars-Peter Clausen state->info->set_termination(sd, true);
176154450f59SHans Verkuil io_write(sd, 0x15, 0xa0); /* Disable Tristate of Pins */
176222d97e56SLaurent Pinchart hdmi_write_clr_set(sd, 0x1a, 0x10, 0x00); /* Unmute audio */
17634a31a93aSMats Randgaard } else {
17644a31a93aSMats Randgaard v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n",
17654a31a93aSMats Randgaard __func__, state->selected_input);
176654450f59SHans Verkuil }
176754450f59SHans Verkuil }
176854450f59SHans Verkuil
disable_input(struct v4l2_subdev * sd)176954450f59SHans Verkuil static void disable_input(struct v4l2_subdev *sd)
177054450f59SHans Verkuil {
1771b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd);
1772d42010a1SLars-Peter Clausen
177322d97e56SLaurent Pinchart hdmi_write_clr_set(sd, 0x1a, 0x10, 0x10); /* Mute audio */
17745474b983SMats Randgaard msleep(16); /* 512 samples with >= 32 kHz sample rate [REF_03, c. 7.16.10] */
177554450f59SHans Verkuil io_write(sd, 0x15, 0xbe); /* Tristate all outputs from video core */
1776d42010a1SLars-Peter Clausen state->info->set_termination(sd, false);
177754450f59SHans Verkuil }
177854450f59SHans Verkuil
select_input(struct v4l2_subdev * sd)17796b0d5d34SHans Verkuil static void select_input(struct v4l2_subdev *sd)
178054450f59SHans Verkuil {
1781b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd);
1782b44b2e06SPablo Anton const struct adv76xx_chip_info *info = state->info;
178354450f59SHans Verkuil
17844a31a93aSMats Randgaard if (is_analog_input(sd)) {
1785b44b2e06SPablo Anton adv76xx_write_reg_seq(sd, info->recommended_settings[0]);
178654450f59SHans Verkuil
178754450f59SHans Verkuil afe_write(sd, 0x00, 0x08); /* power up ADC */
178854450f59SHans Verkuil afe_write(sd, 0x01, 0x06); /* power up Analog Front End */
178954450f59SHans Verkuil afe_write(sd, 0xc8, 0x00); /* phase control */
17904a31a93aSMats Randgaard } else if (is_digital_input(sd)) {
17914a31a93aSMats Randgaard hdmi_write(sd, 0x00, state->selected_input & 0x03);
179254450f59SHans Verkuil
1793b44b2e06SPablo Anton adv76xx_write_reg_seq(sd, info->recommended_settings[1]);
179454450f59SHans Verkuil
1795b44b2e06SPablo Anton if (adv76xx_has_afe(state)) {
179654450f59SHans Verkuil afe_write(sd, 0x00, 0xff); /* power down ADC */
179754450f59SHans Verkuil afe_write(sd, 0x01, 0xfe); /* power down Analog Front End */
179854450f59SHans Verkuil afe_write(sd, 0xc8, 0x40); /* phase control */
1799d42010a1SLars-Peter Clausen }
180054450f59SHans Verkuil
180154450f59SHans Verkuil cp_write(sd, 0x3e, 0x00); /* CP core pre-gain control */
180254450f59SHans Verkuil cp_write(sd, 0xc3, 0x39); /* CP coast control. Graphics mode */
180354450f59SHans Verkuil cp_write(sd, 0x40, 0x80); /* CP core pre-gain control. Graphics mode */
18044a31a93aSMats Randgaard } else {
18054a31a93aSMats Randgaard v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n",
18064a31a93aSMats Randgaard __func__, state->selected_input);
180754450f59SHans Verkuil }
18084c5681acSLaurent Pinchart
18094c5681acSLaurent Pinchart /* Enable video adjustment (contrast, saturation, brightness and hue) */
18104c5681acSLaurent Pinchart cp_write_clr_set(sd, 0x3e, 0x80, 0x80);
181154450f59SHans Verkuil }
181254450f59SHans Verkuil
adv76xx_s_routing(struct v4l2_subdev * sd,u32 input,u32 output,u32 config)1813b44b2e06SPablo Anton static int adv76xx_s_routing(struct v4l2_subdev *sd,
181454450f59SHans Verkuil u32 input, u32 output, u32 config)
181554450f59SHans Verkuil {
1816b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd);
181754450f59SHans Verkuil
1818ff4f80fdSMats Randgaard v4l2_dbg(2, debug, sd, "%s: input %d, selected input %d",
1819ff4f80fdSMats Randgaard __func__, input, state->selected_input);
1820ff4f80fdSMats Randgaard
1821ff4f80fdSMats Randgaard if (input == state->selected_input)
1822ff4f80fdSMats Randgaard return 0;
182354450f59SHans Verkuil
1824d42010a1SLars-Peter Clausen if (input > state->info->max_port)
1825d42010a1SLars-Peter Clausen return -EINVAL;
1826d42010a1SLars-Peter Clausen
18274a31a93aSMats Randgaard state->selected_input = input;
182854450f59SHans Verkuil
182954450f59SHans Verkuil disable_input(sd);
18306b0d5d34SHans Verkuil select_input(sd);
18316b0d5d34SHans Verkuil enable_input(sd);
183254450f59SHans Verkuil
18336f5bcfc3SLars-Peter Clausen v4l2_subdev_notify_event(sd, &adv76xx_ev_fmt);
18346f5bcfc3SLars-Peter Clausen
183554450f59SHans Verkuil return 0;
183654450f59SHans Verkuil }
183754450f59SHans Verkuil
adv76xx_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_mbus_code_enum * code)1838b44b2e06SPablo Anton static int adv76xx_enum_mbus_code(struct v4l2_subdev *sd,
18390d346d2aSTomi Valkeinen struct v4l2_subdev_state *sd_state,
1840539b33b0SLaurent Pinchart struct v4l2_subdev_mbus_code_enum *code)
184154450f59SHans Verkuil {
1842b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd);
184354450f59SHans Verkuil
1844539b33b0SLaurent Pinchart if (code->index >= state->info->nformats)
1845539b33b0SLaurent Pinchart return -EINVAL;
1846539b33b0SLaurent Pinchart
1847539b33b0SLaurent Pinchart code->code = state->info->formats[code->index].code;
1848539b33b0SLaurent Pinchart
1849539b33b0SLaurent Pinchart return 0;
1850539b33b0SLaurent Pinchart }
1851539b33b0SLaurent Pinchart
adv76xx_fill_format(struct adv76xx_state * state,struct v4l2_mbus_framefmt * format)1852b44b2e06SPablo Anton static void adv76xx_fill_format(struct adv76xx_state *state,
1853539b33b0SLaurent Pinchart struct v4l2_mbus_framefmt *format)
1854539b33b0SLaurent Pinchart {
1855539b33b0SLaurent Pinchart memset(format, 0, sizeof(*format));
1856539b33b0SLaurent Pinchart
1857539b33b0SLaurent Pinchart format->width = state->timings.bt.width;
1858539b33b0SLaurent Pinchart format->height = state->timings.bt.height;
1859539b33b0SLaurent Pinchart format->field = V4L2_FIELD_NONE;
1860680fee04SHans Verkuil format->colorspace = V4L2_COLORSPACE_SRGB;
1861539b33b0SLaurent Pinchart
1862680fee04SHans Verkuil if (state->timings.bt.flags & V4L2_DV_FL_IS_CE_VIDEO)
1863539b33b0SLaurent Pinchart format->colorspace = (state->timings.bt.height <= 576) ?
186454450f59SHans Verkuil V4L2_COLORSPACE_SMPTE170M : V4L2_COLORSPACE_REC709;
186554450f59SHans Verkuil }
1866539b33b0SLaurent Pinchart
1867539b33b0SLaurent Pinchart /*
1868539b33b0SLaurent Pinchart * Compute the op_ch_sel value required to obtain on the bus the component order
1869539b33b0SLaurent Pinchart * corresponding to the selected format taking into account bus reordering
1870539b33b0SLaurent Pinchart * applied by the board at the output of the device.
1871539b33b0SLaurent Pinchart *
1872539b33b0SLaurent Pinchart * The following table gives the op_ch_value from the format component order
1873539b33b0SLaurent Pinchart * (expressed as op_ch_sel value in column) and the bus reordering (expressed as
1874b44b2e06SPablo Anton * adv76xx_bus_order value in row).
1875539b33b0SLaurent Pinchart *
1876539b33b0SLaurent Pinchart * | GBR(0) GRB(1) BGR(2) RGB(3) BRG(4) RBG(5)
1877539b33b0SLaurent Pinchart * ----------+-------------------------------------------------
1878539b33b0SLaurent Pinchart * RGB (NOP) | GBR GRB BGR RGB BRG RBG
1879539b33b0SLaurent Pinchart * GRB (1-2) | BGR RGB GBR GRB RBG BRG
1880539b33b0SLaurent Pinchart * RBG (2-3) | GRB GBR BRG RBG BGR RGB
1881539b33b0SLaurent Pinchart * BGR (1-3) | RBG BRG RGB BGR GRB GBR
1882539b33b0SLaurent Pinchart * BRG (ROR) | BRG RBG GRB GBR RGB BGR
1883539b33b0SLaurent Pinchart * GBR (ROL) | RGB BGR RBG BRG GBR GRB
1884539b33b0SLaurent Pinchart */
adv76xx_op_ch_sel(struct adv76xx_state * state)1885b44b2e06SPablo Anton static unsigned int adv76xx_op_ch_sel(struct adv76xx_state *state)
1886539b33b0SLaurent Pinchart {
1887539b33b0SLaurent Pinchart #define _SEL(a,b,c,d,e,f) { \
1888b44b2e06SPablo Anton ADV76XX_OP_CH_SEL_##a, ADV76XX_OP_CH_SEL_##b, ADV76XX_OP_CH_SEL_##c, \
1889b44b2e06SPablo Anton ADV76XX_OP_CH_SEL_##d, ADV76XX_OP_CH_SEL_##e, ADV76XX_OP_CH_SEL_##f }
1890539b33b0SLaurent Pinchart #define _BUS(x) [ADV7604_BUS_ORDER_##x]
1891539b33b0SLaurent Pinchart
1892539b33b0SLaurent Pinchart static const unsigned int op_ch_sel[6][6] = {
1893539b33b0SLaurent Pinchart _BUS(RGB) /* NOP */ = _SEL(GBR, GRB, BGR, RGB, BRG, RBG),
1894539b33b0SLaurent Pinchart _BUS(GRB) /* 1-2 */ = _SEL(BGR, RGB, GBR, GRB, RBG, BRG),
1895539b33b0SLaurent Pinchart _BUS(RBG) /* 2-3 */ = _SEL(GRB, GBR, BRG, RBG, BGR, RGB),
1896539b33b0SLaurent Pinchart _BUS(BGR) /* 1-3 */ = _SEL(RBG, BRG, RGB, BGR, GRB, GBR),
1897539b33b0SLaurent Pinchart _BUS(BRG) /* ROR */ = _SEL(BRG, RBG, GRB, GBR, RGB, BGR),
1898539b33b0SLaurent Pinchart _BUS(GBR) /* ROL */ = _SEL(RGB, BGR, RBG, BRG, GBR, GRB),
1899539b33b0SLaurent Pinchart };
1900539b33b0SLaurent Pinchart
1901539b33b0SLaurent Pinchart return op_ch_sel[state->pdata.bus_order][state->format->op_ch_sel >> 5];
1902539b33b0SLaurent Pinchart }
1903539b33b0SLaurent Pinchart
adv76xx_setup_format(struct adv76xx_state * state)1904b44b2e06SPablo Anton static void adv76xx_setup_format(struct adv76xx_state *state)
1905539b33b0SLaurent Pinchart {
1906539b33b0SLaurent Pinchart struct v4l2_subdev *sd = &state->sd;
1907539b33b0SLaurent Pinchart
190822d97e56SLaurent Pinchart io_write_clr_set(sd, 0x02, 0x02,
1909b44b2e06SPablo Anton state->format->rgb_out ? ADV76XX_RGB_OUT : 0);
1910539b33b0SLaurent Pinchart io_write(sd, 0x03, state->format->op_format_sel |
1911539b33b0SLaurent Pinchart state->pdata.op_format_mode_sel);
1912b44b2e06SPablo Anton io_write_clr_set(sd, 0x04, 0xe0, adv76xx_op_ch_sel(state));
191322d97e56SLaurent Pinchart io_write_clr_set(sd, 0x05, 0x01,
1914b44b2e06SPablo Anton state->format->swap_cb_cr ? ADV76XX_OP_SWAP_CB_CR : 0);
1915fd74246dSHans Verkuil set_rgb_quantization_range(sd);
1916539b33b0SLaurent Pinchart }
1917539b33b0SLaurent Pinchart
adv76xx_get_format(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_format * format)1918f7234138SHans Verkuil static int adv76xx_get_format(struct v4l2_subdev *sd,
19190d346d2aSTomi Valkeinen struct v4l2_subdev_state *sd_state,
1920539b33b0SLaurent Pinchart struct v4l2_subdev_format *format)
1921539b33b0SLaurent Pinchart {
1922b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd);
1923539b33b0SLaurent Pinchart
1924539b33b0SLaurent Pinchart if (format->pad != state->source_pad)
1925539b33b0SLaurent Pinchart return -EINVAL;
1926539b33b0SLaurent Pinchart
1927b44b2e06SPablo Anton adv76xx_fill_format(state, &format->format);
1928539b33b0SLaurent Pinchart
1929539b33b0SLaurent Pinchart if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
1930539b33b0SLaurent Pinchart struct v4l2_mbus_framefmt *fmt;
1931539b33b0SLaurent Pinchart
19320d346d2aSTomi Valkeinen fmt = v4l2_subdev_get_try_format(sd, sd_state, format->pad);
1933539b33b0SLaurent Pinchart format->format.code = fmt->code;
1934539b33b0SLaurent Pinchart } else {
1935539b33b0SLaurent Pinchart format->format.code = state->format->code;
1936539b33b0SLaurent Pinchart }
1937539b33b0SLaurent Pinchart
1938539b33b0SLaurent Pinchart return 0;
1939539b33b0SLaurent Pinchart }
1940539b33b0SLaurent Pinchart
adv76xx_get_selection(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_selection * sel)1941b7d4d2f8SUlrich Hecht static int adv76xx_get_selection(struct v4l2_subdev *sd,
19420d346d2aSTomi Valkeinen struct v4l2_subdev_state *sd_state,
1943b7d4d2f8SUlrich Hecht struct v4l2_subdev_selection *sel)
1944b7d4d2f8SUlrich Hecht {
1945b7d4d2f8SUlrich Hecht struct adv76xx_state *state = to_state(sd);
1946b7d4d2f8SUlrich Hecht
1947b7d4d2f8SUlrich Hecht if (sel->which != V4L2_SUBDEV_FORMAT_ACTIVE)
1948b7d4d2f8SUlrich Hecht return -EINVAL;
1949b7d4d2f8SUlrich Hecht /* Only CROP, CROP_DEFAULT and CROP_BOUNDS are supported */
1950b7d4d2f8SUlrich Hecht if (sel->target > V4L2_SEL_TGT_CROP_BOUNDS)
1951b7d4d2f8SUlrich Hecht return -EINVAL;
1952b7d4d2f8SUlrich Hecht
1953b7d4d2f8SUlrich Hecht sel->r.left = 0;
1954b7d4d2f8SUlrich Hecht sel->r.top = 0;
1955b7d4d2f8SUlrich Hecht sel->r.width = state->timings.bt.width;
1956b7d4d2f8SUlrich Hecht sel->r.height = state->timings.bt.height;
1957b7d4d2f8SUlrich Hecht
1958b7d4d2f8SUlrich Hecht return 0;
1959b7d4d2f8SUlrich Hecht }
1960b7d4d2f8SUlrich Hecht
adv76xx_set_format(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_format * format)1961f7234138SHans Verkuil static int adv76xx_set_format(struct v4l2_subdev *sd,
19620d346d2aSTomi Valkeinen struct v4l2_subdev_state *sd_state,
1963539b33b0SLaurent Pinchart struct v4l2_subdev_format *format)
1964539b33b0SLaurent Pinchart {
1965b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd);
1966b44b2e06SPablo Anton const struct adv76xx_format_info *info;
1967539b33b0SLaurent Pinchart
1968539b33b0SLaurent Pinchart if (format->pad != state->source_pad)
1969539b33b0SLaurent Pinchart return -EINVAL;
1970539b33b0SLaurent Pinchart
1971b44b2e06SPablo Anton info = adv76xx_format_info(state, format->format.code);
1972af28c996SMarkus Elfring if (!info)
1973b44b2e06SPablo Anton info = adv76xx_format_info(state, MEDIA_BUS_FMT_YUYV8_2X8);
1974539b33b0SLaurent Pinchart
1975b44b2e06SPablo Anton adv76xx_fill_format(state, &format->format);
1976539b33b0SLaurent Pinchart format->format.code = info->code;
1977539b33b0SLaurent Pinchart
1978539b33b0SLaurent Pinchart if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
1979539b33b0SLaurent Pinchart struct v4l2_mbus_framefmt *fmt;
1980539b33b0SLaurent Pinchart
19810d346d2aSTomi Valkeinen fmt = v4l2_subdev_get_try_format(sd, sd_state, format->pad);
1982539b33b0SLaurent Pinchart fmt->code = format->format.code;
1983539b33b0SLaurent Pinchart } else {
1984539b33b0SLaurent Pinchart state->format = info;
1985b44b2e06SPablo Anton adv76xx_setup_format(state);
1986539b33b0SLaurent Pinchart }
1987539b33b0SLaurent Pinchart
198854450f59SHans Verkuil return 0;
198954450f59SHans Verkuil }
199054450f59SHans Verkuil
199141a52373SHans Verkuil #if IS_ENABLED(CONFIG_VIDEO_ADV7604_CEC)
adv76xx_cec_tx_raw_status(struct v4l2_subdev * sd,u8 tx_raw_status)199241a52373SHans Verkuil static void adv76xx_cec_tx_raw_status(struct v4l2_subdev *sd, u8 tx_raw_status)
199341a52373SHans Verkuil {
199441a52373SHans Verkuil struct adv76xx_state *state = to_state(sd);
199541a52373SHans Verkuil
199641a52373SHans Verkuil if ((cec_read(sd, 0x11) & 0x01) == 0) {
199741a52373SHans Verkuil v4l2_dbg(1, debug, sd, "%s: tx raw: tx disabled\n", __func__);
199841a52373SHans Verkuil return;
199941a52373SHans Verkuil }
200041a52373SHans Verkuil
200141a52373SHans Verkuil if (tx_raw_status & 0x02) {
200241a52373SHans Verkuil v4l2_dbg(1, debug, sd, "%s: tx raw: arbitration lost\n",
200341a52373SHans Verkuil __func__);
200441a52373SHans Verkuil cec_transmit_done(state->cec_adap, CEC_TX_STATUS_ARB_LOST,
200541a52373SHans Verkuil 1, 0, 0, 0);
2006979d33d3SHans Verkuil return;
200741a52373SHans Verkuil }
200841a52373SHans Verkuil if (tx_raw_status & 0x04) {
200941a52373SHans Verkuil u8 status;
201041a52373SHans Verkuil u8 nack_cnt;
201141a52373SHans Verkuil u8 low_drive_cnt;
201241a52373SHans Verkuil
201341a52373SHans Verkuil v4l2_dbg(1, debug, sd, "%s: tx raw: retry failed\n", __func__);
201441a52373SHans Verkuil /*
201541a52373SHans Verkuil * We set this status bit since this hardware performs
201641a52373SHans Verkuil * retransmissions.
201741a52373SHans Verkuil */
201841a52373SHans Verkuil status = CEC_TX_STATUS_MAX_RETRIES;
201941a52373SHans Verkuil nack_cnt = cec_read(sd, 0x14) & 0xf;
202041a52373SHans Verkuil if (nack_cnt)
202141a52373SHans Verkuil status |= CEC_TX_STATUS_NACK;
202241a52373SHans Verkuil low_drive_cnt = cec_read(sd, 0x14) >> 4;
202341a52373SHans Verkuil if (low_drive_cnt)
202441a52373SHans Verkuil status |= CEC_TX_STATUS_LOW_DRIVE;
202541a52373SHans Verkuil cec_transmit_done(state->cec_adap, status,
202641a52373SHans Verkuil 0, nack_cnt, low_drive_cnt, 0);
202741a52373SHans Verkuil return;
202841a52373SHans Verkuil }
202941a52373SHans Verkuil if (tx_raw_status & 0x01) {
203041a52373SHans Verkuil v4l2_dbg(1, debug, sd, "%s: tx raw: ready ok\n", __func__);
203141a52373SHans Verkuil cec_transmit_done(state->cec_adap, CEC_TX_STATUS_OK, 0, 0, 0, 0);
203241a52373SHans Verkuil return;
203341a52373SHans Verkuil }
203441a52373SHans Verkuil }
203541a52373SHans Verkuil
adv76xx_cec_isr(struct v4l2_subdev * sd,bool * handled)203641a52373SHans Verkuil static void adv76xx_cec_isr(struct v4l2_subdev *sd, bool *handled)
203741a52373SHans Verkuil {
203841a52373SHans Verkuil struct adv76xx_state *state = to_state(sd);
203940d91c99SHans Verkuil const struct adv76xx_chip_info *info = state->info;
204041a52373SHans Verkuil u8 cec_irq;
204141a52373SHans Verkuil
204241a52373SHans Verkuil /* cec controller */
204340d91c99SHans Verkuil cec_irq = io_read(sd, info->cec_irq_status) & 0x0f;
204441a52373SHans Verkuil if (!cec_irq)
204541a52373SHans Verkuil return;
204641a52373SHans Verkuil
204741a52373SHans Verkuil v4l2_dbg(1, debug, sd, "%s: cec: irq 0x%x\n", __func__, cec_irq);
204841a52373SHans Verkuil adv76xx_cec_tx_raw_status(sd, cec_irq);
204941a52373SHans Verkuil if (cec_irq & 0x08) {
205041a52373SHans Verkuil struct cec_msg msg;
205141a52373SHans Verkuil
205241a52373SHans Verkuil msg.len = cec_read(sd, 0x25) & 0x1f;
205305c480f4SHans Verkuil if (msg.len > CEC_MAX_MSG_SIZE)
205405c480f4SHans Verkuil msg.len = CEC_MAX_MSG_SIZE;
205541a52373SHans Verkuil
205641a52373SHans Verkuil if (msg.len) {
205741a52373SHans Verkuil u8 i;
205841a52373SHans Verkuil
205941a52373SHans Verkuil for (i = 0; i < msg.len; i++)
206041a52373SHans Verkuil msg.msg[i] = cec_read(sd, i + 0x15);
206140d91c99SHans Verkuil cec_write(sd, info->cec_rx_enable,
206240d91c99SHans Verkuil info->cec_rx_enable_mask); /* re-enable rx */
206341a52373SHans Verkuil cec_received_msg(state->cec_adap, &msg);
206441a52373SHans Verkuil }
206541a52373SHans Verkuil }
206641a52373SHans Verkuil
206740d91c99SHans Verkuil if (info->cec_irq_swap) {
206840d91c99SHans Verkuil /*
206940d91c99SHans Verkuil * Note: the bit order is swapped between 0x4d and 0x4e
207040d91c99SHans Verkuil * on adv7604
207140d91c99SHans Verkuil */
207241a52373SHans Verkuil cec_irq = ((cec_irq & 0x08) >> 3) | ((cec_irq & 0x04) >> 1) |
207341a52373SHans Verkuil ((cec_irq & 0x02) << 1) | ((cec_irq & 0x01) << 3);
207440d91c99SHans Verkuil }
207540d91c99SHans Verkuil io_write(sd, info->cec_irq_status + 1, cec_irq);
207641a52373SHans Verkuil
207741a52373SHans Verkuil if (handled)
207841a52373SHans Verkuil *handled = true;
207941a52373SHans Verkuil }
208041a52373SHans Verkuil
adv76xx_cec_adap_enable(struct cec_adapter * adap,bool enable)208141a52373SHans Verkuil static int adv76xx_cec_adap_enable(struct cec_adapter *adap, bool enable)
208241a52373SHans Verkuil {
2083eb10790fSJose Abreu struct adv76xx_state *state = cec_get_drvdata(adap);
208440d91c99SHans Verkuil const struct adv76xx_chip_info *info = state->info;
208541a52373SHans Verkuil struct v4l2_subdev *sd = &state->sd;
208641a52373SHans Verkuil
208741a52373SHans Verkuil if (!state->cec_enabled_adap && enable) {
208841a52373SHans Verkuil cec_write_clr_set(sd, 0x2a, 0x01, 0x01); /* power up cec */
208941a52373SHans Verkuil cec_write(sd, 0x2c, 0x01); /* cec soft reset */
209041a52373SHans Verkuil cec_write_clr_set(sd, 0x11, 0x01, 0); /* initially disable tx */
209141a52373SHans Verkuil /* enabled irqs: */
209241a52373SHans Verkuil /* tx: ready */
209341a52373SHans Verkuil /* tx: arbitration lost */
209441a52373SHans Verkuil /* tx: retry timeout */
209541a52373SHans Verkuil /* rx: ready */
209640d91c99SHans Verkuil io_write_clr_set(sd, info->cec_irq_status + 3, 0x0f, 0x0f);
209740d91c99SHans Verkuil cec_write(sd, info->cec_rx_enable, info->cec_rx_enable_mask);
209841a52373SHans Verkuil } else if (state->cec_enabled_adap && !enable) {
209941a52373SHans Verkuil /* disable cec interrupts */
210040d91c99SHans Verkuil io_write_clr_set(sd, info->cec_irq_status + 3, 0x0f, 0x00);
210141a52373SHans Verkuil /* disable address mask 1-3 */
210241a52373SHans Verkuil cec_write_clr_set(sd, 0x27, 0x70, 0x00);
210341a52373SHans Verkuil /* power down cec section */
210441a52373SHans Verkuil cec_write_clr_set(sd, 0x2a, 0x01, 0x00);
210541a52373SHans Verkuil state->cec_valid_addrs = 0;
210641a52373SHans Verkuil }
210741a52373SHans Verkuil state->cec_enabled_adap = enable;
210841a52373SHans Verkuil adv76xx_s_detect_tx_5v_ctrl(sd);
210941a52373SHans Verkuil return 0;
211041a52373SHans Verkuil }
211141a52373SHans Verkuil
adv76xx_cec_adap_log_addr(struct cec_adapter * adap,u8 addr)211241a52373SHans Verkuil static int adv76xx_cec_adap_log_addr(struct cec_adapter *adap, u8 addr)
211341a52373SHans Verkuil {
2114eb10790fSJose Abreu struct adv76xx_state *state = cec_get_drvdata(adap);
211541a52373SHans Verkuil struct v4l2_subdev *sd = &state->sd;
211641a52373SHans Verkuil unsigned int i, free_idx = ADV76XX_MAX_ADDRS;
211741a52373SHans Verkuil
211841a52373SHans Verkuil if (!state->cec_enabled_adap)
211941a52373SHans Verkuil return addr == CEC_LOG_ADDR_INVALID ? 0 : -EIO;
212041a52373SHans Verkuil
212141a52373SHans Verkuil if (addr == CEC_LOG_ADDR_INVALID) {
212241a52373SHans Verkuil cec_write_clr_set(sd, 0x27, 0x70, 0);
212341a52373SHans Verkuil state->cec_valid_addrs = 0;
212441a52373SHans Verkuil return 0;
212541a52373SHans Verkuil }
212641a52373SHans Verkuil
212741a52373SHans Verkuil for (i = 0; i < ADV76XX_MAX_ADDRS; i++) {
212841a52373SHans Verkuil bool is_valid = state->cec_valid_addrs & (1 << i);
212941a52373SHans Verkuil
213041a52373SHans Verkuil if (free_idx == ADV76XX_MAX_ADDRS && !is_valid)
213141a52373SHans Verkuil free_idx = i;
213241a52373SHans Verkuil if (is_valid && state->cec_addr[i] == addr)
213341a52373SHans Verkuil return 0;
213441a52373SHans Verkuil }
213541a52373SHans Verkuil if (i == ADV76XX_MAX_ADDRS) {
213641a52373SHans Verkuil i = free_idx;
213741a52373SHans Verkuil if (i == ADV76XX_MAX_ADDRS)
213841a52373SHans Verkuil return -ENXIO;
213941a52373SHans Verkuil }
214041a52373SHans Verkuil state->cec_addr[i] = addr;
214141a52373SHans Verkuil state->cec_valid_addrs |= 1 << i;
214241a52373SHans Verkuil
214341a52373SHans Verkuil switch (i) {
214441a52373SHans Verkuil case 0:
214541a52373SHans Verkuil /* enable address mask 0 */
214641a52373SHans Verkuil cec_write_clr_set(sd, 0x27, 0x10, 0x10);
214741a52373SHans Verkuil /* set address for mask 0 */
214841a52373SHans Verkuil cec_write_clr_set(sd, 0x28, 0x0f, addr);
214941a52373SHans Verkuil break;
215041a52373SHans Verkuil case 1:
215141a52373SHans Verkuil /* enable address mask 1 */
215241a52373SHans Verkuil cec_write_clr_set(sd, 0x27, 0x20, 0x20);
215341a52373SHans Verkuil /* set address for mask 1 */
215441a52373SHans Verkuil cec_write_clr_set(sd, 0x28, 0xf0, addr << 4);
215541a52373SHans Verkuil break;
215641a52373SHans Verkuil case 2:
215741a52373SHans Verkuil /* enable address mask 2 */
215841a52373SHans Verkuil cec_write_clr_set(sd, 0x27, 0x40, 0x40);
215941a52373SHans Verkuil /* set address for mask 1 */
216041a52373SHans Verkuil cec_write_clr_set(sd, 0x29, 0x0f, addr);
216141a52373SHans Verkuil break;
216241a52373SHans Verkuil }
216341a52373SHans Verkuil return 0;
216441a52373SHans Verkuil }
216541a52373SHans Verkuil
adv76xx_cec_adap_transmit(struct cec_adapter * adap,u8 attempts,u32 signal_free_time,struct cec_msg * msg)216641a52373SHans Verkuil static int adv76xx_cec_adap_transmit(struct cec_adapter *adap, u8 attempts,
216741a52373SHans Verkuil u32 signal_free_time, struct cec_msg *msg)
216841a52373SHans Verkuil {
2169eb10790fSJose Abreu struct adv76xx_state *state = cec_get_drvdata(adap);
217041a52373SHans Verkuil struct v4l2_subdev *sd = &state->sd;
217141a52373SHans Verkuil u8 len = msg->len;
217241a52373SHans Verkuil unsigned int i;
217341a52373SHans Verkuil
217441a52373SHans Verkuil /*
217541a52373SHans Verkuil * The number of retries is the number of attempts - 1, but retry
217641a52373SHans Verkuil * at least once. It's not clear if a value of 0 is allowed, so
217741a52373SHans Verkuil * let's do at least one retry.
217841a52373SHans Verkuil */
217941a52373SHans Verkuil cec_write_clr_set(sd, 0x12, 0x70, max(1, attempts - 1) << 4);
218041a52373SHans Verkuil
218141a52373SHans Verkuil if (len > 16) {
218241a52373SHans Verkuil v4l2_err(sd, "%s: len exceeded 16 (%d)\n", __func__, len);
218341a52373SHans Verkuil return -EINVAL;
218441a52373SHans Verkuil }
218541a52373SHans Verkuil
218641a52373SHans Verkuil /* write data */
218741a52373SHans Verkuil for (i = 0; i < len; i++)
218841a52373SHans Verkuil cec_write(sd, i, msg->msg[i]);
218941a52373SHans Verkuil
219041a52373SHans Verkuil /* set length (data + header) */
219141a52373SHans Verkuil cec_write(sd, 0x10, len);
219241a52373SHans Verkuil /* start transmit, enable tx */
219341a52373SHans Verkuil cec_write(sd, 0x11, 0x01);
219441a52373SHans Verkuil return 0;
219541a52373SHans Verkuil }
219641a52373SHans Verkuil
219741a52373SHans Verkuil static const struct cec_adap_ops adv76xx_cec_adap_ops = {
219841a52373SHans Verkuil .adap_enable = adv76xx_cec_adap_enable,
219941a52373SHans Verkuil .adap_log_addr = adv76xx_cec_adap_log_addr,
220041a52373SHans Verkuil .adap_transmit = adv76xx_cec_adap_transmit,
220141a52373SHans Verkuil };
220241a52373SHans Verkuil #endif
220341a52373SHans Verkuil
adv76xx_isr(struct v4l2_subdev * sd,u32 status,bool * handled)2204b44b2e06SPablo Anton static int adv76xx_isr(struct v4l2_subdev *sd, u32 status, bool *handled)
220554450f59SHans Verkuil {
2206b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd);
2207b44b2e06SPablo Anton const struct adv76xx_chip_info *info = state->info;
2208f24d229cSMats Randgaard const u8 irq_reg_0x43 = io_read(sd, 0x43);
2209f24d229cSMats Randgaard const u8 irq_reg_0x6b = io_read(sd, 0x6b);
2210f24d229cSMats Randgaard const u8 irq_reg_0x70 = io_read(sd, 0x70);
2211f24d229cSMats Randgaard u8 fmt_change_digital;
2212f24d229cSMats Randgaard u8 fmt_change;
2213f24d229cSMats Randgaard u8 tx_5v;
2214f24d229cSMats Randgaard
2215f24d229cSMats Randgaard if (irq_reg_0x43)
2216f24d229cSMats Randgaard io_write(sd, 0x44, irq_reg_0x43);
2217f24d229cSMats Randgaard if (irq_reg_0x70)
2218f24d229cSMats Randgaard io_write(sd, 0x71, irq_reg_0x70);
2219f24d229cSMats Randgaard if (irq_reg_0x6b)
2220f24d229cSMats Randgaard io_write(sd, 0x6c, irq_reg_0x6b);
222154450f59SHans Verkuil
2222ff4f80fdSMats Randgaard v4l2_dbg(2, debug, sd, "%s: ", __func__);
2223ff4f80fdSMats Randgaard
222454450f59SHans Verkuil /* format change */
2225f24d229cSMats Randgaard fmt_change = irq_reg_0x43 & 0x98;
2226d42010a1SLars-Peter Clausen fmt_change_digital = is_digital_input(sd)
2227d42010a1SLars-Peter Clausen ? irq_reg_0x6b & info->fmt_change_digital_mask
2228d42010a1SLars-Peter Clausen : 0;
222914d03233SMats Randgaard
223054450f59SHans Verkuil if (fmt_change || fmt_change_digital) {
223154450f59SHans Verkuil v4l2_dbg(1, debug, sd,
223225a64ac9SMats Randgaard "%s: fmt_change = 0x%x, fmt_change_digital = 0x%x\n",
223354450f59SHans Verkuil __func__, fmt_change, fmt_change_digital);
223425a64ac9SMats Randgaard
22356f5bcfc3SLars-Peter Clausen v4l2_subdev_notify_event(sd, &adv76xx_ev_fmt);
223625a64ac9SMats Randgaard
223754450f59SHans Verkuil if (handled)
223854450f59SHans Verkuil *handled = true;
223954450f59SHans Verkuil }
2240f24d229cSMats Randgaard /* HDMI/DVI mode */
2241f24d229cSMats Randgaard if (irq_reg_0x6b & 0x01) {
2242f24d229cSMats Randgaard v4l2_dbg(1, debug, sd, "%s: irq %s mode\n", __func__,
2243f24d229cSMats Randgaard (io_read(sd, 0x6a) & 0x01) ? "HDMI" : "DVI");
2244f24d229cSMats Randgaard set_rgb_quantization_range(sd);
2245f24d229cSMats Randgaard if (handled)
2246f24d229cSMats Randgaard *handled = true;
2247f24d229cSMats Randgaard }
2248f24d229cSMats Randgaard
224941a52373SHans Verkuil #if IS_ENABLED(CONFIG_VIDEO_ADV7604_CEC)
225041a52373SHans Verkuil /* cec */
225141a52373SHans Verkuil adv76xx_cec_isr(sd, handled);
225241a52373SHans Verkuil #endif
225341a52373SHans Verkuil
225454450f59SHans Verkuil /* tx 5v detect */
22550ba4581cSHans Verkuil tx_5v = irq_reg_0x70 & info->cable_det_mask;
225654450f59SHans Verkuil if (tx_5v) {
225754450f59SHans Verkuil v4l2_dbg(1, debug, sd, "%s: tx_5v: 0x%x\n", __func__, tx_5v);
2258b44b2e06SPablo Anton adv76xx_s_detect_tx_5v_ctrl(sd);
225954450f59SHans Verkuil if (handled)
226054450f59SHans Verkuil *handled = true;
226154450f59SHans Verkuil }
226254450f59SHans Verkuil return 0;
226354450f59SHans Verkuil }
226454450f59SHans Verkuil
adv76xx_irq_handler(int irq,void * dev_id)226540d91c99SHans Verkuil static irqreturn_t adv76xx_irq_handler(int irq, void *dev_id)
226640d91c99SHans Verkuil {
226740d91c99SHans Verkuil struct adv76xx_state *state = dev_id;
226840d91c99SHans Verkuil bool handled = false;
226940d91c99SHans Verkuil
227040d91c99SHans Verkuil adv76xx_isr(&state->sd, 0, &handled);
227140d91c99SHans Verkuil
227240d91c99SHans Verkuil return handled ? IRQ_HANDLED : IRQ_NONE;
227340d91c99SHans Verkuil }
227440d91c99SHans Verkuil
adv76xx_get_edid(struct v4l2_subdev * sd,struct v4l2_edid * edid)2275b44b2e06SPablo Anton static int adv76xx_get_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid)
227654450f59SHans Verkuil {
2277b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd);
22784a31a93aSMats Randgaard u8 *data = NULL;
227954450f59SHans Verkuil
2280dd9ac11aSHans Verkuil memset(edid->reserved, 0, sizeof(edid->reserved));
22814a31a93aSMats Randgaard
22824a31a93aSMats Randgaard switch (edid->pad) {
2283b44b2e06SPablo Anton case ADV76XX_PAD_HDMI_PORT_A:
2284c784b1e2SLaurent Pinchart case ADV7604_PAD_HDMI_PORT_B:
2285c784b1e2SLaurent Pinchart case ADV7604_PAD_HDMI_PORT_C:
2286c784b1e2SLaurent Pinchart case ADV7604_PAD_HDMI_PORT_D:
22874a31a93aSMats Randgaard if (state->edid.present & (1 << edid->pad))
22884a31a93aSMats Randgaard data = state->edid.edid;
22894a31a93aSMats Randgaard break;
22904a31a93aSMats Randgaard default:
22914a31a93aSMats Randgaard return -EINVAL;
22924a31a93aSMats Randgaard }
2293dd9ac11aSHans Verkuil
2294dd9ac11aSHans Verkuil if (edid->start_block == 0 && edid->blocks == 0) {
2295dd9ac11aSHans Verkuil edid->blocks = data ? state->edid.blocks : 0;
2296dd9ac11aSHans Verkuil return 0;
2297dd9ac11aSHans Verkuil }
2298dd9ac11aSHans Verkuil
2299af28c996SMarkus Elfring if (!data)
23004a31a93aSMats Randgaard return -ENODATA;
23014a31a93aSMats Randgaard
2302dd9ac11aSHans Verkuil if (edid->start_block >= state->edid.blocks)
2303dd9ac11aSHans Verkuil return -EINVAL;
2304dd9ac11aSHans Verkuil
2305dd9ac11aSHans Verkuil if (edid->start_block + edid->blocks > state->edid.blocks)
2306dd9ac11aSHans Verkuil edid->blocks = state->edid.blocks - edid->start_block;
2307dd9ac11aSHans Verkuil
2308dd9ac11aSHans Verkuil memcpy(edid->edid, data + edid->start_block * 128, edid->blocks * 128);
2309dd9ac11aSHans Verkuil
231054450f59SHans Verkuil return 0;
231154450f59SHans Verkuil }
231254450f59SHans Verkuil
adv76xx_set_edid(struct v4l2_subdev * sd,struct v4l2_edid * edid)2313b44b2e06SPablo Anton static int adv76xx_set_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid)
231454450f59SHans Verkuil {
2315b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd);
2316b44b2e06SPablo Anton const struct adv76xx_chip_info *info = state->info;
231741a52373SHans Verkuil unsigned int spa_loc;
231854b74981SHans Verkuil u16 pa, parent_pa;
231954450f59SHans Verkuil int err;
2320dd08beb9SMats Randgaard int i;
232154450f59SHans Verkuil
2322dd9ac11aSHans Verkuil memset(edid->reserved, 0, sizeof(edid->reserved));
2323dd9ac11aSHans Verkuil
2324c784b1e2SLaurent Pinchart if (edid->pad > ADV7604_PAD_HDMI_PORT_D)
232554450f59SHans Verkuil return -EINVAL;
232654450f59SHans Verkuil if (edid->start_block != 0)
232754450f59SHans Verkuil return -EINVAL;
232854450f59SHans Verkuil if (edid->blocks == 0) {
23293e86aa85SMats Randgaard /* Disable hotplug and I2C access to EDID RAM from DDC port */
23304a31a93aSMats Randgaard state->edid.present &= ~(1 << edid->pad);
2331b44b2e06SPablo Anton adv76xx_set_hpd(state, state->edid.present);
233222d97e56SLaurent Pinchart rep_write_clr_set(sd, info->edid_enable_reg, 0x0f, state->edid.present);
23333e86aa85SMats Randgaard
233454450f59SHans Verkuil /* Fall back to a 16:9 aspect ratio */
233554450f59SHans Verkuil state->aspect_ratio.numerator = 16;
233654450f59SHans Verkuil state->aspect_ratio.denominator = 9;
23373e86aa85SMats Randgaard
2338e7da8992SHans Verkuil if (!state->edid.present) {
23393e86aa85SMats Randgaard state->edid.blocks = 0;
2340e7da8992SHans Verkuil cec_phys_addr_invalidate(state->cec_adap);
2341e7da8992SHans Verkuil }
23423e86aa85SMats Randgaard
23433e86aa85SMats Randgaard v4l2_dbg(2, debug, sd, "%s: clear EDID pad %d, edid.present = 0x%x\n",
23443e86aa85SMats Randgaard __func__, edid->pad, state->edid.present);
234554450f59SHans Verkuil return 0;
234654450f59SHans Verkuil }
2347c730ff32SHans Verkuil if (edid->blocks > ADV76XX_MAX_EDID_BLOCKS) {
2348c730ff32SHans Verkuil edid->blocks = ADV76XX_MAX_EDID_BLOCKS;
234954450f59SHans Verkuil return -E2BIG;
23504a31a93aSMats Randgaard }
2351c730ff32SHans Verkuil
23529cfd2753SHans Verkuil pa = v4l2_get_edid_phys_addr(edid->edid, edid->blocks * 128, &spa_loc);
235354b74981SHans Verkuil err = v4l2_phys_addr_validate(pa, &parent_pa, NULL);
235441a52373SHans Verkuil if (err)
235541a52373SHans Verkuil return err;
23564a31a93aSMats Randgaard
2357c730ff32SHans Verkuil if (!spa_loc) {
2358c730ff32SHans Verkuil /*
2359c730ff32SHans Verkuil * There is no SPA, so just set spa_loc to 128 and pa to whatever
2360c730ff32SHans Verkuil * data is there.
2361c730ff32SHans Verkuil */
2362c730ff32SHans Verkuil spa_loc = 128;
2363c730ff32SHans Verkuil pa = (edid->edid[spa_loc] << 8) | edid->edid[spa_loc + 1];
2364c730ff32SHans Verkuil }
2365c730ff32SHans Verkuil
2366dd08beb9SMats Randgaard v4l2_dbg(2, debug, sd, "%s: write EDID pad %d, edid.present = 0x%x\n",
2367dd08beb9SMats Randgaard __func__, edid->pad, state->edid.present);
2368dd08beb9SMats Randgaard
23693e86aa85SMats Randgaard /* Disable hotplug and I2C access to EDID RAM from DDC port */
23704a31a93aSMats Randgaard cancel_delayed_work_sync(&state->delayed_work_enable_hotplug);
2371b44b2e06SPablo Anton adv76xx_set_hpd(state, 0);
237222d97e56SLaurent Pinchart rep_write_clr_set(sd, info->edid_enable_reg, 0x0f, 0x00);
23733e86aa85SMats Randgaard
23743e86aa85SMats Randgaard switch (edid->pad) {
2375b44b2e06SPablo Anton case ADV76XX_PAD_HDMI_PORT_A:
237654b74981SHans Verkuil state->spa_port_a[0] = pa >> 8;
237754b74981SHans Verkuil state->spa_port_a[1] = pa & 0xff;
23783e86aa85SMats Randgaard break;
2379c784b1e2SLaurent Pinchart case ADV7604_PAD_HDMI_PORT_B:
2380c730ff32SHans Verkuil rep_write(sd, info->edid_spa_port_b_reg, pa >> 8);
2381c730ff32SHans Verkuil rep_write(sd, info->edid_spa_port_b_reg + 1, pa & 0xff);
23823e86aa85SMats Randgaard break;
2383c784b1e2SLaurent Pinchart case ADV7604_PAD_HDMI_PORT_C:
2384c730ff32SHans Verkuil rep_write(sd, info->edid_spa_port_b_reg + 2, pa >> 8);
2385c730ff32SHans Verkuil rep_write(sd, info->edid_spa_port_b_reg + 3, pa & 0xff);
23863e86aa85SMats Randgaard break;
2387c784b1e2SLaurent Pinchart case ADV7604_PAD_HDMI_PORT_D:
2388c730ff32SHans Verkuil rep_write(sd, info->edid_spa_port_b_reg + 4, pa >> 8);
2389c730ff32SHans Verkuil rep_write(sd, info->edid_spa_port_b_reg + 5, pa & 0xff);
23903e86aa85SMats Randgaard break;
2391dd08beb9SMats Randgaard default:
2392dd08beb9SMats Randgaard return -EINVAL;
23933e86aa85SMats Randgaard }
2394d42010a1SLars-Peter Clausen
2395c730ff32SHans Verkuil if (info->edid_spa_loc_reg) {
2396c730ff32SHans Verkuil u8 mask = info->edid_spa_loc_msb_mask;
2397c730ff32SHans Verkuil
2398c730ff32SHans Verkuil rep_write(sd, info->edid_spa_loc_reg, spa_loc & 0xff);
2399c730ff32SHans Verkuil rep_write_clr_set(sd, info->edid_spa_loc_reg + 1,
2400c730ff32SHans Verkuil mask, (spa_loc & 0x100) ? mask : 0);
2401d42010a1SLars-Peter Clausen }
24023e86aa85SMats Randgaard
2403dd08beb9SMats Randgaard edid->edid[spa_loc] = state->spa_port_a[0];
2404dd08beb9SMats Randgaard edid->edid[spa_loc + 1] = state->spa_port_a[1];
24054a31a93aSMats Randgaard
24064a31a93aSMats Randgaard memcpy(state->edid.edid, edid->edid, 128 * edid->blocks);
24074a31a93aSMats Randgaard state->edid.blocks = edid->blocks;
240854450f59SHans Verkuil state->aspect_ratio = v4l2_calc_aspect_ratio(edid->edid[0x15],
240954450f59SHans Verkuil edid->edid[0x16]);
24103e86aa85SMats Randgaard state->edid.present |= 1 << edid->pad;
24114a31a93aSMats Randgaard
2412c730ff32SHans Verkuil rep_write_clr_set(sd, info->edid_segment_reg,
2413c730ff32SHans Verkuil info->edid_segment_mask, 0);
2414c730ff32SHans Verkuil err = edid_write_block(sd, 128 * min(edid->blocks, 2U), state->edid.edid);
24154a31a93aSMats Randgaard if (err < 0) {
24163e86aa85SMats Randgaard v4l2_err(sd, "error %d writing edid pad %d\n", err, edid->pad);
241754450f59SHans Verkuil return err;
241854450f59SHans Verkuil }
2419c730ff32SHans Verkuil if (edid->blocks > 2) {
2420c730ff32SHans Verkuil rep_write_clr_set(sd, info->edid_segment_reg,
2421c730ff32SHans Verkuil info->edid_segment_mask,
2422c730ff32SHans Verkuil info->edid_segment_mask);
2423c730ff32SHans Verkuil err = edid_write_block(sd, 128 * (edid->blocks - 2),
2424c730ff32SHans Verkuil state->edid.edid + 256);
2425c730ff32SHans Verkuil if (err < 0) {
2426c730ff32SHans Verkuil v4l2_err(sd, "error %d writing edid pad %d\n",
2427c730ff32SHans Verkuil err, edid->pad);
2428c730ff32SHans Verkuil return err;
2429c730ff32SHans Verkuil }
2430c730ff32SHans Verkuil }
243154450f59SHans Verkuil
2432b44b2e06SPablo Anton /* adv76xx calculates the checksums and enables I2C access to internal
2433dd08beb9SMats Randgaard EDID RAM from DDC port. */
243422d97e56SLaurent Pinchart rep_write_clr_set(sd, info->edid_enable_reg, 0x0f, state->edid.present);
2435dd08beb9SMats Randgaard
2436dd08beb9SMats Randgaard for (i = 0; i < 1000; i++) {
2437d42010a1SLars-Peter Clausen if (rep_read(sd, info->edid_status_reg) & state->edid.present)
2438dd08beb9SMats Randgaard break;
2439dd08beb9SMats Randgaard mdelay(1);
2440dd08beb9SMats Randgaard }
2441dd08beb9SMats Randgaard if (i == 1000) {
2442dd08beb9SMats Randgaard v4l2_err(sd, "error enabling edid (0x%x)\n", state->edid.present);
2443dd08beb9SMats Randgaard return -EIO;
2444dd08beb9SMats Randgaard }
244554b74981SHans Verkuil cec_s_phys_addr(state->cec_adap, parent_pa, false);
2446dd08beb9SMats Randgaard
24474a31a93aSMats Randgaard /* enable hotplug after 100 ms */
24480423ff9bSBhaktipriya Shridhar schedule_delayed_work(&state->delayed_work_enable_hotplug, HZ / 10);
24494a31a93aSMats Randgaard return 0;
24504a31a93aSMats Randgaard }
24514a31a93aSMats Randgaard
245254450f59SHans Verkuil /*********** avi info frame CEA-861-E **************/
245354450f59SHans Verkuil
2454516613c1SHans Verkuil static const struct adv76xx_cfg_read_infoframe adv76xx_cri[] = {
2455516613c1SHans Verkuil { "AVI", 0x01, 0xe0, 0x00 },
2456516613c1SHans Verkuil { "Audio", 0x02, 0xe3, 0x1c },
2457516613c1SHans Verkuil { "SDP", 0x04, 0xe6, 0x2a },
2458516613c1SHans Verkuil { "Vendor", 0x10, 0xec, 0x54 }
2459516613c1SHans Verkuil };
2460516613c1SHans Verkuil
adv76xx_read_infoframe(struct v4l2_subdev * sd,int index,union hdmi_infoframe * frame)2461516613c1SHans Verkuil static int adv76xx_read_infoframe(struct v4l2_subdev *sd, int index,
2462516613c1SHans Verkuil union hdmi_infoframe *frame)
2463516613c1SHans Verkuil {
2464516613c1SHans Verkuil uint8_t buffer[32];
2465516613c1SHans Verkuil u8 len;
2466516613c1SHans Verkuil int i;
2467516613c1SHans Verkuil
2468516613c1SHans Verkuil if (!(io_read(sd, 0x60) & adv76xx_cri[index].present_mask)) {
2469516613c1SHans Verkuil v4l2_info(sd, "%s infoframe not received\n",
2470516613c1SHans Verkuil adv76xx_cri[index].desc);
2471516613c1SHans Verkuil return -ENOENT;
2472516613c1SHans Verkuil }
2473516613c1SHans Verkuil
2474516613c1SHans Verkuil for (i = 0; i < 3; i++)
2475516613c1SHans Verkuil buffer[i] = infoframe_read(sd,
2476516613c1SHans Verkuil adv76xx_cri[index].head_addr + i);
2477516613c1SHans Verkuil
2478516613c1SHans Verkuil len = buffer[2] + 1;
2479516613c1SHans Verkuil
2480516613c1SHans Verkuil if (len + 3 > sizeof(buffer)) {
2481516613c1SHans Verkuil v4l2_err(sd, "%s: invalid %s infoframe length %d\n", __func__,
2482516613c1SHans Verkuil adv76xx_cri[index].desc, len);
2483516613c1SHans Verkuil return -ENOENT;
2484516613c1SHans Verkuil }
2485516613c1SHans Verkuil
2486516613c1SHans Verkuil for (i = 0; i < len; i++)
2487516613c1SHans Verkuil buffer[i + 3] = infoframe_read(sd,
2488516613c1SHans Verkuil adv76xx_cri[index].payload_addr + i);
2489516613c1SHans Verkuil
24904a92fc6eSTom Rix if (hdmi_infoframe_unpack(frame, buffer, len + 3) < 0) {
2491516613c1SHans Verkuil v4l2_err(sd, "%s: unpack of %s infoframe failed\n", __func__,
2492516613c1SHans Verkuil adv76xx_cri[index].desc);
2493516613c1SHans Verkuil return -ENOENT;
2494516613c1SHans Verkuil }
2495516613c1SHans Verkuil return 0;
2496516613c1SHans Verkuil }
2497516613c1SHans Verkuil
adv76xx_log_infoframes(struct v4l2_subdev * sd)2498516613c1SHans Verkuil static void adv76xx_log_infoframes(struct v4l2_subdev *sd)
249954450f59SHans Verkuil {
250054450f59SHans Verkuil int i;
250154450f59SHans Verkuil
2502bb88f325SMartin Bugge if (!is_hdmi(sd)) {
2503516613c1SHans Verkuil v4l2_info(sd, "receive DVI-D signal, no infoframes\n");
250454450f59SHans Verkuil return;
250554450f59SHans Verkuil }
250654450f59SHans Verkuil
2507516613c1SHans Verkuil for (i = 0; i < ARRAY_SIZE(adv76xx_cri); i++) {
2508516613c1SHans Verkuil union hdmi_infoframe frame;
2509516613c1SHans Verkuil struct i2c_client *client = v4l2_get_subdevdata(sd);
251054450f59SHans Verkuil
2511b9629c55SHans Verkuil if (!adv76xx_read_infoframe(sd, i, &frame))
2512516613c1SHans Verkuil hdmi_infoframe_log(KERN_INFO, &client->dev, &frame);
2513516613c1SHans Verkuil }
251454450f59SHans Verkuil }
251554450f59SHans Verkuil
adv76xx_log_status(struct v4l2_subdev * sd)2516b44b2e06SPablo Anton static int adv76xx_log_status(struct v4l2_subdev *sd)
251754450f59SHans Verkuil {
2518b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd);
2519b44b2e06SPablo Anton const struct adv76xx_chip_info *info = state->info;
252054450f59SHans Verkuil struct v4l2_dv_timings timings;
252154450f59SHans Verkuil struct stdi_readback stdi;
252254450f59SHans Verkuil u8 reg_io_0x02 = io_read(sd, 0x02);
25234a2ccdd2SLaurent Pinchart u8 edid_enabled;
25244a2ccdd2SLaurent Pinchart u8 cable_det;
252554450f59SHans Verkuil
2526f216ccb3SLars-Peter Clausen static const char * const csc_coeff_sel_rb[16] = {
252754450f59SHans Verkuil "bypassed", "YPbPr601 -> RGB", "reserved", "YPbPr709 -> RGB",
252854450f59SHans Verkuil "reserved", "RGB -> YPbPr601", "reserved", "RGB -> YPbPr709",
252954450f59SHans Verkuil "reserved", "YPbPr709 -> YPbPr601", "YPbPr601 -> YPbPr709",
253054450f59SHans Verkuil "reserved", "reserved", "reserved", "reserved", "manual"
253154450f59SHans Verkuil };
2532f216ccb3SLars-Peter Clausen static const char * const input_color_space_txt[16] = {
253354450f59SHans Verkuil "RGB limited range (16-235)", "RGB full range (0-255)",
253454450f59SHans Verkuil "YCbCr Bt.601 (16-235)", "YCbCr Bt.709 (16-235)",
25359833239eSMats Randgaard "xvYCC Bt.601", "xvYCC Bt.709",
253654450f59SHans Verkuil "YCbCr Bt.601 (0-255)", "YCbCr Bt.709 (0-255)",
253754450f59SHans Verkuil "invalid", "invalid", "invalid", "invalid", "invalid",
253854450f59SHans Verkuil "invalid", "invalid", "automatic"
253954450f59SHans Verkuil };
25407a5d99e7SHans Verkuil static const char * const hdmi_color_space_txt[16] = {
25417a5d99e7SHans Verkuil "RGB limited range (16-235)", "RGB full range (0-255)",
25427a5d99e7SHans Verkuil "YCbCr Bt.601 (16-235)", "YCbCr Bt.709 (16-235)",
25437a5d99e7SHans Verkuil "xvYCC Bt.601", "xvYCC Bt.709",
25447a5d99e7SHans Verkuil "YCbCr Bt.601 (0-255)", "YCbCr Bt.709 (0-255)",
2545db034018SHans Verkuil "sYCC", "opYCC 601", "opRGB", "invalid", "invalid",
25467a5d99e7SHans Verkuil "invalid", "invalid", "invalid"
25477a5d99e7SHans Verkuil };
2548f216ccb3SLars-Peter Clausen static const char * const rgb_quantization_range_txt[] = {
254954450f59SHans Verkuil "Automatic",
255054450f59SHans Verkuil "RGB limited range (16-235)",
255154450f59SHans Verkuil "RGB full range (0-255)",
255254450f59SHans Verkuil };
2553f216ccb3SLars-Peter Clausen static const char * const deep_color_mode_txt[4] = {
2554bb88f325SMartin Bugge "8-bits per channel",
2555bb88f325SMartin Bugge "10-bits per channel",
2556bb88f325SMartin Bugge "12-bits per channel",
2557bb88f325SMartin Bugge "16-bits per channel (not supported)"
2558bb88f325SMartin Bugge };
255954450f59SHans Verkuil
256054450f59SHans Verkuil v4l2_info(sd, "-----Chip status-----\n");
256154450f59SHans Verkuil v4l2_info(sd, "Chip power: %s\n", no_power(sd) ? "off" : "on");
2562d42010a1SLars-Peter Clausen edid_enabled = rep_read(sd, info->edid_status_reg);
25634a31a93aSMats Randgaard v4l2_info(sd, "EDID enabled port A: %s, B: %s, C: %s, D: %s\n",
25644a2ccdd2SLaurent Pinchart ((edid_enabled & 0x01) ? "Yes" : "No"),
25654a2ccdd2SLaurent Pinchart ((edid_enabled & 0x02) ? "Yes" : "No"),
25664a2ccdd2SLaurent Pinchart ((edid_enabled & 0x04) ? "Yes" : "No"),
25674a2ccdd2SLaurent Pinchart ((edid_enabled & 0x08) ? "Yes" : "No"));
256841a52373SHans Verkuil v4l2_info(sd, "CEC: %s\n", state->cec_enabled_adap ?
256954450f59SHans Verkuil "enabled" : "disabled");
257041a52373SHans Verkuil if (state->cec_enabled_adap) {
257141a52373SHans Verkuil int i;
257241a52373SHans Verkuil
257341a52373SHans Verkuil for (i = 0; i < ADV76XX_MAX_ADDRS; i++) {
257441a52373SHans Verkuil bool is_valid = state->cec_valid_addrs & (1 << i);
257541a52373SHans Verkuil
257641a52373SHans Verkuil if (is_valid)
257741a52373SHans Verkuil v4l2_info(sd, "CEC Logical Address: 0x%x\n",
257841a52373SHans Verkuil state->cec_addr[i]);
257941a52373SHans Verkuil }
258041a52373SHans Verkuil }
258154450f59SHans Verkuil
258254450f59SHans Verkuil v4l2_info(sd, "-----Signal status-----\n");
2583d42010a1SLars-Peter Clausen cable_det = info->read_cable_det(sd);
25844a31a93aSMats Randgaard v4l2_info(sd, "Cable detected (+5V power) port A: %s, B: %s, C: %s, D: %s\n",
2585d42010a1SLars-Peter Clausen ((cable_det & 0x01) ? "Yes" : "No"),
2586d42010a1SLars-Peter Clausen ((cable_det & 0x02) ? "Yes" : "No"),
25874a2ccdd2SLaurent Pinchart ((cable_det & 0x04) ? "Yes" : "No"),
2588d42010a1SLars-Peter Clausen ((cable_det & 0x08) ? "Yes" : "No"));
258954450f59SHans Verkuil v4l2_info(sd, "TMDS signal detected: %s\n",
259054450f59SHans Verkuil no_signal_tmds(sd) ? "false" : "true");
259154450f59SHans Verkuil v4l2_info(sd, "TMDS signal locked: %s\n",
259254450f59SHans Verkuil no_lock_tmds(sd) ? "false" : "true");
259354450f59SHans Verkuil v4l2_info(sd, "SSPD locked: %s\n", no_lock_sspd(sd) ? "false" : "true");
259454450f59SHans Verkuil v4l2_info(sd, "STDI locked: %s\n", no_lock_stdi(sd) ? "false" : "true");
259554450f59SHans Verkuil v4l2_info(sd, "CP locked: %s\n", no_lock_cp(sd) ? "false" : "true");
259654450f59SHans Verkuil v4l2_info(sd, "CP free run: %s\n",
259758514625Sjean-michel.hautbois@vodalys.com (in_free_run(sd)) ? "on" : "off");
2598ccbd5bc4SHans Verkuil v4l2_info(sd, "Prim-mode = 0x%x, video std = 0x%x, v_freq = 0x%x\n",
2599ccbd5bc4SHans Verkuil io_read(sd, 0x01) & 0x0f, io_read(sd, 0x00) & 0x3f,
2600ccbd5bc4SHans Verkuil (io_read(sd, 0x01) & 0x70) >> 4);
260154450f59SHans Verkuil
260254450f59SHans Verkuil v4l2_info(sd, "-----Video Timings-----\n");
260354450f59SHans Verkuil if (read_stdi(sd, &stdi))
260454450f59SHans Verkuil v4l2_info(sd, "STDI: not locked\n");
260554450f59SHans Verkuil else
260654450f59SHans Verkuil v4l2_info(sd, "STDI: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %s, %chsync, %cvsync\n",
260754450f59SHans Verkuil stdi.lcf, stdi.bl, stdi.lcvs,
260854450f59SHans Verkuil stdi.interlaced ? "interlaced" : "progressive",
260954450f59SHans Verkuil stdi.hs_pol, stdi.vs_pol);
2610b44b2e06SPablo Anton if (adv76xx_query_dv_timings(sd, &timings))
261154450f59SHans Verkuil v4l2_info(sd, "No video detected\n");
261254450f59SHans Verkuil else
261311d034c8SHans Verkuil v4l2_print_dv_timings(sd->name, "Detected format: ",
261411d034c8SHans Verkuil &timings, true);
261511d034c8SHans Verkuil v4l2_print_dv_timings(sd->name, "Configured format: ",
261611d034c8SHans Verkuil &state->timings, true);
261754450f59SHans Verkuil
261876eb2d30SMats Randgaard if (no_signal(sd))
261976eb2d30SMats Randgaard return 0;
262076eb2d30SMats Randgaard
262154450f59SHans Verkuil v4l2_info(sd, "-----Color space-----\n");
262254450f59SHans Verkuil v4l2_info(sd, "RGB quantization range ctrl: %s\n",
262354450f59SHans Verkuil rgb_quantization_range_txt[state->rgb_quantization_range]);
262454450f59SHans Verkuil v4l2_info(sd, "Input color space: %s\n",
262554450f59SHans Verkuil input_color_space_txt[reg_io_0x02 >> 4]);
2626fd74246dSHans Verkuil v4l2_info(sd, "Output color space: %s %s, alt-gamma %s\n",
262754450f59SHans Verkuil (reg_io_0x02 & 0x02) ? "RGB" : "YCbCr",
26285dd7d88aSHans Verkuil (((reg_io_0x02 >> 2) & 0x01) ^ (reg_io_0x02 & 0x01)) ?
2629fd74246dSHans Verkuil "(16-235)" : "(0-255)",
26307a5d99e7SHans Verkuil (reg_io_0x02 & 0x08) ? "enabled" : "disabled");
263154450f59SHans Verkuil v4l2_info(sd, "Color space conversion: %s\n",
263280f4944eSjean-michel.hautbois@vodalys.com csc_coeff_sel_rb[cp_read(sd, info->cp_csc) >> 4]);
263354450f59SHans Verkuil
26344a31a93aSMats Randgaard if (!is_digital_input(sd))
263576eb2d30SMats Randgaard return 0;
263676eb2d30SMats Randgaard
263776eb2d30SMats Randgaard v4l2_info(sd, "-----%s status-----\n", is_hdmi(sd) ? "HDMI" : "DVI-D");
26384a31a93aSMats Randgaard v4l2_info(sd, "Digital video port selected: %c\n",
26394a31a93aSMats Randgaard (hdmi_read(sd, 0x00) & 0x03) + 'A');
26404a31a93aSMats Randgaard v4l2_info(sd, "HDCP encrypted content: %s\n",
26414a31a93aSMats Randgaard (hdmi_read(sd, 0x05) & 0x40) ? "true" : "false");
264276eb2d30SMats Randgaard v4l2_info(sd, "HDCP keys read: %s%s\n",
264376eb2d30SMats Randgaard (hdmi_read(sd, 0x04) & 0x20) ? "yes" : "no",
264476eb2d30SMats Randgaard (hdmi_read(sd, 0x04) & 0x10) ? "ERROR" : "");
264577639ff2SHans Verkuil if (is_hdmi(sd)) {
264676eb2d30SMats Randgaard bool audio_pll_locked = hdmi_read(sd, 0x04) & 0x01;
264776eb2d30SMats Randgaard bool audio_sample_packet_detect = hdmi_read(sd, 0x18) & 0x01;
264876eb2d30SMats Randgaard bool audio_mute = io_read(sd, 0x65) & 0x40;
264976eb2d30SMats Randgaard
265076eb2d30SMats Randgaard v4l2_info(sd, "Audio: pll %s, samples %s, %s\n",
265176eb2d30SMats Randgaard audio_pll_locked ? "locked" : "not locked",
265276eb2d30SMats Randgaard audio_sample_packet_detect ? "detected" : "not detected",
265376eb2d30SMats Randgaard audio_mute ? "muted" : "enabled");
265476eb2d30SMats Randgaard if (audio_pll_locked && audio_sample_packet_detect) {
265576eb2d30SMats Randgaard v4l2_info(sd, "Audio format: %s\n",
265676eb2d30SMats Randgaard (hdmi_read(sd, 0x07) & 0x20) ? "multi-channel" : "stereo");
265776eb2d30SMats Randgaard }
265876eb2d30SMats Randgaard v4l2_info(sd, "Audio CTS: %u\n", (hdmi_read(sd, 0x5b) << 12) +
265976eb2d30SMats Randgaard (hdmi_read(sd, 0x5c) << 8) +
266076eb2d30SMats Randgaard (hdmi_read(sd, 0x5d) & 0xf0));
266176eb2d30SMats Randgaard v4l2_info(sd, "Audio N: %u\n", ((hdmi_read(sd, 0x5d) & 0x0f) << 16) +
266276eb2d30SMats Randgaard (hdmi_read(sd, 0x5e) << 8) +
266376eb2d30SMats Randgaard hdmi_read(sd, 0x5f));
266476eb2d30SMats Randgaard v4l2_info(sd, "AV Mute: %s\n", (hdmi_read(sd, 0x04) & 0x40) ? "on" : "off");
266576eb2d30SMats Randgaard
266676eb2d30SMats Randgaard v4l2_info(sd, "Deep color mode: %s\n", deep_color_mode_txt[(hdmi_read(sd, 0x0b) & 0x60) >> 5]);
26677a5d99e7SHans Verkuil v4l2_info(sd, "HDMI colorspace: %s\n", hdmi_color_space_txt[hdmi_read(sd, 0x53) & 0xf]);
266876eb2d30SMats Randgaard
2669516613c1SHans Verkuil adv76xx_log_infoframes(sd);
267054450f59SHans Verkuil }
267154450f59SHans Verkuil
267254450f59SHans Verkuil return 0;
267354450f59SHans Verkuil }
267454450f59SHans Verkuil
adv76xx_subscribe_event(struct v4l2_subdev * sd,struct v4l2_fh * fh,struct v4l2_event_subscription * sub)26756f5bcfc3SLars-Peter Clausen static int adv76xx_subscribe_event(struct v4l2_subdev *sd,
26766f5bcfc3SLars-Peter Clausen struct v4l2_fh *fh,
26776f5bcfc3SLars-Peter Clausen struct v4l2_event_subscription *sub)
26786f5bcfc3SLars-Peter Clausen {
26796f5bcfc3SLars-Peter Clausen switch (sub->type) {
26806f5bcfc3SLars-Peter Clausen case V4L2_EVENT_SOURCE_CHANGE:
26816f5bcfc3SLars-Peter Clausen return v4l2_src_change_event_subdev_subscribe(sd, fh, sub);
26826f5bcfc3SLars-Peter Clausen case V4L2_EVENT_CTRL:
26836f5bcfc3SLars-Peter Clausen return v4l2_ctrl_subdev_subscribe_event(sd, fh, sub);
26846f5bcfc3SLars-Peter Clausen default:
26856f5bcfc3SLars-Peter Clausen return -EINVAL;
26866f5bcfc3SLars-Peter Clausen }
26876f5bcfc3SLars-Peter Clausen }
26886f5bcfc3SLars-Peter Clausen
adv76xx_registered(struct v4l2_subdev * sd)268941a52373SHans Verkuil static int adv76xx_registered(struct v4l2_subdev *sd)
269041a52373SHans Verkuil {
269141a52373SHans Verkuil struct adv76xx_state *state = to_state(sd);
2692f51e8080SHans Verkuil struct i2c_client *client = v4l2_get_subdevdata(sd);
269341a52373SHans Verkuil int err;
269441a52373SHans Verkuil
2695f51e8080SHans Verkuil err = cec_register_adapter(state->cec_adap, &client->dev);
269641a52373SHans Verkuil if (err)
269741a52373SHans Verkuil cec_delete_adapter(state->cec_adap);
269841a52373SHans Verkuil return err;
269941a52373SHans Verkuil }
270041a52373SHans Verkuil
adv76xx_unregistered(struct v4l2_subdev * sd)270141a52373SHans Verkuil static void adv76xx_unregistered(struct v4l2_subdev *sd)
270241a52373SHans Verkuil {
270341a52373SHans Verkuil struct adv76xx_state *state = to_state(sd);
270441a52373SHans Verkuil
270541a52373SHans Verkuil cec_unregister_adapter(state->cec_adap);
270641a52373SHans Verkuil }
270741a52373SHans Verkuil
270854450f59SHans Verkuil /* ----------------------------------------------------------------------- */
270954450f59SHans Verkuil
2710b44b2e06SPablo Anton static const struct v4l2_ctrl_ops adv76xx_ctrl_ops = {
2711b44b2e06SPablo Anton .s_ctrl = adv76xx_s_ctrl,
2712297a4144SHans Verkuil .g_volatile_ctrl = adv76xx_g_volatile_ctrl,
271354450f59SHans Verkuil };
271454450f59SHans Verkuil
2715b44b2e06SPablo Anton static const struct v4l2_subdev_core_ops adv76xx_core_ops = {
2716b44b2e06SPablo Anton .log_status = adv76xx_log_status,
2717b44b2e06SPablo Anton .interrupt_service_routine = adv76xx_isr,
27186f5bcfc3SLars-Peter Clausen .subscribe_event = adv76xx_subscribe_event,
27190975626dSLars-Peter Clausen .unsubscribe_event = v4l2_event_subdev_unsubscribe,
272054450f59SHans Verkuil #ifdef CONFIG_VIDEO_ADV_DEBUG
2721b44b2e06SPablo Anton .g_register = adv76xx_g_register,
2722b44b2e06SPablo Anton .s_register = adv76xx_s_register,
272354450f59SHans Verkuil #endif
272454450f59SHans Verkuil };
272554450f59SHans Verkuil
2726b44b2e06SPablo Anton static const struct v4l2_subdev_video_ops adv76xx_video_ops = {
2727b44b2e06SPablo Anton .s_routing = adv76xx_s_routing,
2728b44b2e06SPablo Anton .g_input_status = adv76xx_g_input_status,
2729b44b2e06SPablo Anton .s_dv_timings = adv76xx_s_dv_timings,
2730b44b2e06SPablo Anton .g_dv_timings = adv76xx_g_dv_timings,
2731b44b2e06SPablo Anton .query_dv_timings = adv76xx_query_dv_timings,
273254450f59SHans Verkuil };
273354450f59SHans Verkuil
2734b44b2e06SPablo Anton static const struct v4l2_subdev_pad_ops adv76xx_pad_ops = {
2735b44b2e06SPablo Anton .enum_mbus_code = adv76xx_enum_mbus_code,
2736b7d4d2f8SUlrich Hecht .get_selection = adv76xx_get_selection,
2737b44b2e06SPablo Anton .get_fmt = adv76xx_get_format,
2738b44b2e06SPablo Anton .set_fmt = adv76xx_set_format,
2739b44b2e06SPablo Anton .get_edid = adv76xx_get_edid,
2740b44b2e06SPablo Anton .set_edid = adv76xx_set_edid,
2741b44b2e06SPablo Anton .dv_timings_cap = adv76xx_dv_timings_cap,
2742b44b2e06SPablo Anton .enum_dv_timings = adv76xx_enum_dv_timings,
274354450f59SHans Verkuil };
274454450f59SHans Verkuil
2745b44b2e06SPablo Anton static const struct v4l2_subdev_ops adv76xx_ops = {
2746b44b2e06SPablo Anton .core = &adv76xx_core_ops,
2747b44b2e06SPablo Anton .video = &adv76xx_video_ops,
2748b44b2e06SPablo Anton .pad = &adv76xx_pad_ops,
274954450f59SHans Verkuil };
275054450f59SHans Verkuil
275141a52373SHans Verkuil static const struct v4l2_subdev_internal_ops adv76xx_int_ops = {
275241a52373SHans Verkuil .registered = adv76xx_registered,
275341a52373SHans Verkuil .unregistered = adv76xx_unregistered,
275441a52373SHans Verkuil };
275541a52373SHans Verkuil
275654450f59SHans Verkuil /* -------------------------- custom ctrls ---------------------------------- */
275754450f59SHans Verkuil
275854450f59SHans Verkuil static const struct v4l2_ctrl_config adv7604_ctrl_analog_sampling_phase = {
2759b44b2e06SPablo Anton .ops = &adv76xx_ctrl_ops,
276054450f59SHans Verkuil .id = V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE,
276154450f59SHans Verkuil .name = "Analog Sampling Phase",
276254450f59SHans Verkuil .type = V4L2_CTRL_TYPE_INTEGER,
276354450f59SHans Verkuil .min = 0,
276454450f59SHans Verkuil .max = 0x1f,
276554450f59SHans Verkuil .step = 1,
276654450f59SHans Verkuil .def = 0,
276754450f59SHans Verkuil };
276854450f59SHans Verkuil
2769b44b2e06SPablo Anton static const struct v4l2_ctrl_config adv76xx_ctrl_free_run_color_manual = {
2770b44b2e06SPablo Anton .ops = &adv76xx_ctrl_ops,
277154450f59SHans Verkuil .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL,
277254450f59SHans Verkuil .name = "Free Running Color, Manual",
277354450f59SHans Verkuil .type = V4L2_CTRL_TYPE_BOOLEAN,
277454450f59SHans Verkuil .min = false,
277554450f59SHans Verkuil .max = true,
277654450f59SHans Verkuil .step = 1,
277754450f59SHans Verkuil .def = false,
277854450f59SHans Verkuil };
277954450f59SHans Verkuil
2780b44b2e06SPablo Anton static const struct v4l2_ctrl_config adv76xx_ctrl_free_run_color = {
2781b44b2e06SPablo Anton .ops = &adv76xx_ctrl_ops,
278254450f59SHans Verkuil .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR,
278354450f59SHans Verkuil .name = "Free Running Color",
278454450f59SHans Verkuil .type = V4L2_CTRL_TYPE_INTEGER,
278554450f59SHans Verkuil .min = 0x0,
278654450f59SHans Verkuil .max = 0xffffff,
278754450f59SHans Verkuil .step = 0x1,
278854450f59SHans Verkuil .def = 0x0,
278954450f59SHans Verkuil };
279054450f59SHans Verkuil
279154450f59SHans Verkuil /* ----------------------------------------------------------------------- */
279254450f59SHans Verkuil
2793be2068bfSJean-Michel Hautbois struct adv76xx_register_map {
2794be2068bfSJean-Michel Hautbois const char *name;
2795be2068bfSJean-Michel Hautbois u8 default_addr;
2796be2068bfSJean-Michel Hautbois };
2797be2068bfSJean-Michel Hautbois
2798be2068bfSJean-Michel Hautbois static const struct adv76xx_register_map adv76xx_default_addresses[] = {
2799be2068bfSJean-Michel Hautbois [ADV76XX_PAGE_IO] = { "main", 0x4c },
2800be2068bfSJean-Michel Hautbois [ADV7604_PAGE_AVLINK] = { "avlink", 0x42 },
2801be2068bfSJean-Michel Hautbois [ADV76XX_PAGE_CEC] = { "cec", 0x40 },
2802be2068bfSJean-Michel Hautbois [ADV76XX_PAGE_INFOFRAME] = { "infoframe", 0x3e },
2803be2068bfSJean-Michel Hautbois [ADV7604_PAGE_ESDP] = { "esdp", 0x38 },
2804be2068bfSJean-Michel Hautbois [ADV7604_PAGE_DPP] = { "dpp", 0x3c },
2805be2068bfSJean-Michel Hautbois [ADV76XX_PAGE_AFE] = { "afe", 0x26 },
2806be2068bfSJean-Michel Hautbois [ADV76XX_PAGE_REP] = { "rep", 0x32 },
2807be2068bfSJean-Michel Hautbois [ADV76XX_PAGE_EDID] = { "edid", 0x36 },
2808be2068bfSJean-Michel Hautbois [ADV76XX_PAGE_HDMI] = { "hdmi", 0x34 },
2809be2068bfSJean-Michel Hautbois [ADV76XX_PAGE_TEST] = { "test", 0x30 },
2810be2068bfSJean-Michel Hautbois [ADV76XX_PAGE_CP] = { "cp", 0x22 },
2811be2068bfSJean-Michel Hautbois [ADV7604_PAGE_VDP] = { "vdp", 0x24 },
2812be2068bfSJean-Michel Hautbois };
2813be2068bfSJean-Michel Hautbois
adv76xx_core_init(struct v4l2_subdev * sd)2814b44b2e06SPablo Anton static int adv76xx_core_init(struct v4l2_subdev *sd)
281554450f59SHans Verkuil {
2816b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd);
2817b44b2e06SPablo Anton const struct adv76xx_chip_info *info = state->info;
2818b44b2e06SPablo Anton struct adv76xx_platform_data *pdata = &state->pdata;
281954450f59SHans Verkuil
282054450f59SHans Verkuil hdmi_write(sd, 0x48,
282154450f59SHans Verkuil (pdata->disable_pwrdnb ? 0x80 : 0) |
282254450f59SHans Verkuil (pdata->disable_cable_det_rst ? 0x40 : 0));
282354450f59SHans Verkuil
282454450f59SHans Verkuil disable_input(sd);
282554450f59SHans Verkuil
28265ef54b59SLaurent Pinchart if (pdata->default_input >= 0 &&
28275ef54b59SLaurent Pinchart pdata->default_input < state->source_pad) {
28285ef54b59SLaurent Pinchart state->selected_input = pdata->default_input;
28295ef54b59SLaurent Pinchart select_input(sd);
28305ef54b59SLaurent Pinchart enable_input(sd);
28315ef54b59SLaurent Pinchart }
28325ef54b59SLaurent Pinchart
283354450f59SHans Verkuil /* power */
283454450f59SHans Verkuil io_write(sd, 0x0c, 0x42); /* Power up part and power down VDP */
283554450f59SHans Verkuil io_write(sd, 0x0b, 0x44); /* Power down ESDP block */
283654450f59SHans Verkuil cp_write(sd, 0xcf, 0x01); /* Power down macrovision */
283754450f59SHans Verkuil
28381cf233d8SHans Verkuil /* HPD */
28391cf233d8SHans Verkuil if (info->type != ADV7604) {
28401cf233d8SHans Verkuil /* Set manual HPD values to 0 */
28411cf233d8SHans Verkuil io_write_clr_set(sd, 0x20, 0xc0, 0);
28421cf233d8SHans Verkuil /*
28431cf233d8SHans Verkuil * Set HPA_DELAY to 200 ms and set automatic HPD control
28441cf233d8SHans Verkuil * to: internal EDID is active AND a cable is detected
28451cf233d8SHans Verkuil * AND the manual HPD control is set to 1.
28461cf233d8SHans Verkuil */
28471cf233d8SHans Verkuil hdmi_write_clr_set(sd, 0x6c, 0xf6, 0x26);
28481cf233d8SHans Verkuil }
28491cf233d8SHans Verkuil
285054450f59SHans Verkuil /* video format */
2851fd74246dSHans Verkuil io_write_clr_set(sd, 0x02, 0x0f, pdata->alt_gamma << 3);
285222d97e56SLaurent Pinchart io_write_clr_set(sd, 0x05, 0x0e, pdata->blank_data << 3 |
285354450f59SHans Verkuil pdata->insert_av_codes << 2 |
2854539b33b0SLaurent Pinchart pdata->replicate_av_codes << 1);
2855b44b2e06SPablo Anton adv76xx_setup_format(state);
285654450f59SHans Verkuil
285754450f59SHans Verkuil cp_write(sd, 0x69, 0x30); /* Enable CP CSC */
285898908696SMartin Bugge
285998908696SMartin Bugge /* VS, HS polarities */
28601b5ab875SLaurent Pinchart io_write(sd, 0x06, 0xa0 | pdata->inv_vs_pol << 2 |
28611b5ab875SLaurent Pinchart pdata->inv_hs_pol << 1 | pdata->inv_llc_pol);
2862f31b62e1SMikhail Khelik
2863f31b62e1SMikhail Khelik /* Adjust drive strength */
2864f31b62e1SMikhail Khelik io_write(sd, 0x14, 0x40 | pdata->dr_str_data << 4 |
2865f31b62e1SMikhail Khelik pdata->dr_str_clk << 2 |
2866f31b62e1SMikhail Khelik pdata->dr_str_sync);
2867f31b62e1SMikhail Khelik
286854450f59SHans Verkuil cp_write(sd, 0xba, (pdata->hdmi_free_run_mode << 1) | 0x01); /* HDMI free run */
286954450f59SHans Verkuil cp_write(sd, 0xf3, 0xdc); /* Low threshold to enter/exit free run mode */
287054450f59SHans Verkuil cp_write(sd, 0xf9, 0x23); /* STDI ch. 1 - LCVS change threshold -
287180939647SHans Verkuil ADI recommended setting [REF_01, c. 2.3.3] */
287254450f59SHans Verkuil cp_write(sd, 0x45, 0x23); /* STDI ch. 2 - LCVS change threshold -
287380939647SHans Verkuil ADI recommended setting [REF_01, c. 2.3.3] */
287454450f59SHans Verkuil cp_write(sd, 0xc9, 0x2d); /* use prim_mode and vid_std as free run resolution
287554450f59SHans Verkuil for digital formats */
287654450f59SHans Verkuil
28775474b983SMats Randgaard /* HDMI audio */
287822d97e56SLaurent Pinchart hdmi_write_clr_set(sd, 0x15, 0x03, 0x03); /* Mute on FIFO over-/underflow [REF_01, c. 1.2.18] */
287922d97e56SLaurent Pinchart hdmi_write_clr_set(sd, 0x1a, 0x0e, 0x08); /* Wait 1 s before unmute */
288022d97e56SLaurent Pinchart hdmi_write_clr_set(sd, 0x68, 0x06, 0x06); /* FIFO reset on over-/underflow [REF_01, c. 1.2.19] */
28815474b983SMats Randgaard
288254450f59SHans Verkuil /* TODO from platform data */
288354450f59SHans Verkuil afe_write(sd, 0xb5, 0x01); /* Setting MCLK to 256Fs */
288454450f59SHans Verkuil
2885b44b2e06SPablo Anton if (adv76xx_has_afe(state)) {
288654450f59SHans Verkuil afe_write(sd, 0x02, pdata->ain_sel); /* Select analog input muxing mode */
288722d97e56SLaurent Pinchart io_write_clr_set(sd, 0x30, 1 << 4, pdata->output_bus_lsb_to_msb << 4);
2888d42010a1SLars-Peter Clausen }
288954450f59SHans Verkuil
289054450f59SHans Verkuil /* interrupts */
2891d42010a1SLars-Peter Clausen io_write(sd, 0x40, 0xc0 | pdata->int1_config); /* Configure INT1 */
289254450f59SHans Verkuil io_write(sd, 0x46, 0x98); /* Enable SSPD, STDI and CP unlocked interrupts */
2893d42010a1SLars-Peter Clausen io_write(sd, 0x6e, info->fmt_change_digital_mask); /* Enable V_LOCKED and DE_REGEN_LCK interrupts */
2894d42010a1SLars-Peter Clausen io_write(sd, 0x73, info->cable_det_mask); /* Enable cable detection (+5v) interrupts */
2895d42010a1SLars-Peter Clausen info->setup_irqs(sd);
289654450f59SHans Verkuil
289754450f59SHans Verkuil return v4l2_ctrl_handler_setup(sd->ctrl_handler);
289854450f59SHans Verkuil }
289954450f59SHans Verkuil
adv7604_setup_irqs(struct v4l2_subdev * sd)2900d42010a1SLars-Peter Clausen static void adv7604_setup_irqs(struct v4l2_subdev *sd)
2901d42010a1SLars-Peter Clausen {
2902d42010a1SLars-Peter Clausen io_write(sd, 0x41, 0xd7); /* STDI irq for any change, disable INT2 */
2903d42010a1SLars-Peter Clausen }
2904d42010a1SLars-Peter Clausen
adv7611_setup_irqs(struct v4l2_subdev * sd)2905d42010a1SLars-Peter Clausen static void adv7611_setup_irqs(struct v4l2_subdev *sd)
2906d42010a1SLars-Peter Clausen {
2907d42010a1SLars-Peter Clausen io_write(sd, 0x41, 0xd0); /* STDI irq for any change, disable INT2 */
2908d42010a1SLars-Peter Clausen }
2909d42010a1SLars-Peter Clausen
adv7612_setup_irqs(struct v4l2_subdev * sd)29108331d30bSWilliam Towle static void adv7612_setup_irqs(struct v4l2_subdev *sd)
29118331d30bSWilliam Towle {
29128331d30bSWilliam Towle io_write(sd, 0x41, 0xd0); /* disable INT2 */
29138331d30bSWilliam Towle }
29148331d30bSWilliam Towle
adv76xx_unregister_clients(struct adv76xx_state * state)2915b44b2e06SPablo Anton static void adv76xx_unregister_clients(struct adv76xx_state *state)
291654450f59SHans Verkuil {
291705cacb17SLaurent Pinchart unsigned int i;
291805cacb17SLaurent Pinchart
2919af80559bSWolfram Sang for (i = 1; i < ARRAY_SIZE(state->i2c_clients); ++i)
292005cacb17SLaurent Pinchart i2c_unregister_device(state->i2c_clients[i]);
292105cacb17SLaurent Pinchart }
292254450f59SHans Verkuil
adv76xx_dummy_client(struct v4l2_subdev * sd,unsigned int page)2923b44b2e06SPablo Anton static struct i2c_client *adv76xx_dummy_client(struct v4l2_subdev *sd,
2924be2068bfSJean-Michel Hautbois unsigned int page)
292554450f59SHans Verkuil {
292654450f59SHans Verkuil struct i2c_client *client = v4l2_get_subdevdata(sd);
2927be2068bfSJean-Michel Hautbois struct adv76xx_state *state = to_state(sd);
2928be2068bfSJean-Michel Hautbois struct adv76xx_platform_data *pdata = &state->pdata;
2929be2068bfSJean-Michel Hautbois unsigned int io_reg = 0xf2 + page;
2930be2068bfSJean-Michel Hautbois struct i2c_client *new_client;
293154450f59SHans Verkuil
2932be2068bfSJean-Michel Hautbois if (pdata && pdata->i2c_addresses[page])
2933af80559bSWolfram Sang new_client = i2c_new_dummy_device(client->adapter,
2934be2068bfSJean-Michel Hautbois pdata->i2c_addresses[page]);
2935be2068bfSJean-Michel Hautbois else
2936af80559bSWolfram Sang new_client = i2c_new_ancillary_device(client,
2937be2068bfSJean-Michel Hautbois adv76xx_default_addresses[page].name,
2938be2068bfSJean-Michel Hautbois adv76xx_default_addresses[page].default_addr);
2939be2068bfSJean-Michel Hautbois
2940af80559bSWolfram Sang if (!IS_ERR(new_client))
2941be2068bfSJean-Michel Hautbois io_write(sd, io_reg, new_client->addr << 1);
2942be2068bfSJean-Michel Hautbois
2943be2068bfSJean-Michel Hautbois return new_client;
294454450f59SHans Verkuil }
294554450f59SHans Verkuil
2946b44b2e06SPablo Anton static const struct adv76xx_reg_seq adv7604_recommended_settings_afe[] = {
2947d42010a1SLars-Peter Clausen /* reset ADI recommended settings for HDMI: */
2948d42010a1SLars-Peter Clausen /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 4. */
2949b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x0d), 0x04 }, /* HDMI filter optimization */
2950b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x0d), 0x04 }, /* HDMI filter optimization */
2951b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x3d), 0x00 }, /* DDC bus active pull-up control */
2952b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x3e), 0x74 }, /* TMDS PLL optimization */
2953b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x4e), 0x3b }, /* TMDS PLL optimization */
2954b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x57), 0x74 }, /* TMDS PLL optimization */
2955b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x58), 0x63 }, /* TMDS PLL optimization */
2956b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8d), 0x18 }, /* equaliser */
2957b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8e), 0x34 }, /* equaliser */
2958b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x93), 0x88 }, /* equaliser */
2959b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x94), 0x2e }, /* equaliser */
2960b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x96), 0x00 }, /* enable automatic EQ changing */
2961d42010a1SLars-Peter Clausen
2962d42010a1SLars-Peter Clausen /* set ADI recommended settings for digitizer */
2963d42010a1SLars-Peter Clausen /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 17. */
2964b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_AFE, 0x12), 0x7b }, /* ADC noise shaping filter controls */
2965b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_AFE, 0x0c), 0x1f }, /* CP core gain controls */
2966b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_CP, 0x3e), 0x04 }, /* CP core pre-gain control */
2967b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_CP, 0xc3), 0x39 }, /* CP coast control. Graphics mode */
2968b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_CP, 0x40), 0x5c }, /* CP core pre-gain control. Graphics mode */
2969d42010a1SLars-Peter Clausen
2970b44b2e06SPablo Anton { ADV76XX_REG_SEQ_TERM, 0 },
2971d42010a1SLars-Peter Clausen };
2972d42010a1SLars-Peter Clausen
2973b44b2e06SPablo Anton static const struct adv76xx_reg_seq adv7604_recommended_settings_hdmi[] = {
2974d42010a1SLars-Peter Clausen /* set ADI recommended settings for HDMI: */
2975d42010a1SLars-Peter Clausen /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 4. */
2976b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x0d), 0x84 }, /* HDMI filter optimization */
2977b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x3d), 0x10 }, /* DDC bus active pull-up control */
2978b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x3e), 0x39 }, /* TMDS PLL optimization */
2979b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x4e), 0x3b }, /* TMDS PLL optimization */
2980b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x57), 0xb6 }, /* TMDS PLL optimization */
2981b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x58), 0x03 }, /* TMDS PLL optimization */
2982b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8d), 0x18 }, /* equaliser */
2983b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8e), 0x34 }, /* equaliser */
2984b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x93), 0x8b }, /* equaliser */
2985b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x94), 0x2d }, /* equaliser */
2986b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x96), 0x01 }, /* enable automatic EQ changing */
2987d42010a1SLars-Peter Clausen
2988d42010a1SLars-Peter Clausen /* reset ADI recommended settings for digitizer */
2989d42010a1SLars-Peter Clausen /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 17. */
2990b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_AFE, 0x12), 0xfb }, /* ADC noise shaping filter controls */
2991b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_AFE, 0x0c), 0x0d }, /* CP core gain controls */
2992d42010a1SLars-Peter Clausen
2993b44b2e06SPablo Anton { ADV76XX_REG_SEQ_TERM, 0 },
2994d42010a1SLars-Peter Clausen };
2995d42010a1SLars-Peter Clausen
2996b44b2e06SPablo Anton static const struct adv76xx_reg_seq adv7611_recommended_settings_hdmi[] = {
2997c41ad9c3SLars-Peter Clausen /* ADV7611 Register Settings Recommendations Rev 1.5, May 2014 */
2998b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_CP, 0x6c), 0x00 },
2999b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x9b), 0x03 },
3000b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x6f), 0x08 },
3001b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x85), 0x1f },
3002b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x87), 0x70 },
3003b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x57), 0xda },
3004b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x58), 0x01 },
3005b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x03), 0x98 },
3006b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x4c), 0x44 },
3007b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8d), 0x04 },
3008b44b2e06SPablo Anton { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8e), 0x1e },
3009d42010a1SLars-Peter Clausen
3010b44b2e06SPablo Anton { ADV76XX_REG_SEQ_TERM, 0 },
3011d42010a1SLars-Peter Clausen };
3012d42010a1SLars-Peter Clausen
30138331d30bSWilliam Towle static const struct adv76xx_reg_seq adv7612_recommended_settings_hdmi[] = {
30148331d30bSWilliam Towle { ADV76XX_REG(ADV76XX_PAGE_CP, 0x6c), 0x00 },
30158331d30bSWilliam Towle { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x9b), 0x03 },
30168331d30bSWilliam Towle { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x6f), 0x08 },
30178331d30bSWilliam Towle { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x85), 0x1f },
30188331d30bSWilliam Towle { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x87), 0x70 },
30198331d30bSWilliam Towle { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x57), 0xda },
30208331d30bSWilliam Towle { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x58), 0x01 },
30218331d30bSWilliam Towle { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x03), 0x98 },
30228331d30bSWilliam Towle { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x4c), 0x44 },
30238331d30bSWilliam Towle { ADV76XX_REG_SEQ_TERM, 0 },
30248331d30bSWilliam Towle };
30258331d30bSWilliam Towle
3026b44b2e06SPablo Anton static const struct adv76xx_chip_info adv76xx_chip_info[] = {
3027d42010a1SLars-Peter Clausen [ADV7604] = {
3028d42010a1SLars-Peter Clausen .type = ADV7604,
3029d42010a1SLars-Peter Clausen .has_afe = true,
3030c784b1e2SLaurent Pinchart .max_port = ADV7604_PAD_VGA_COMP,
3031d42010a1SLars-Peter Clausen .num_dv_ports = 4,
3032d42010a1SLars-Peter Clausen .edid_enable_reg = 0x77,
3033d42010a1SLars-Peter Clausen .edid_status_reg = 0x7d,
3034c730ff32SHans Verkuil .edid_segment_reg = 0x77,
3035c730ff32SHans Verkuil .edid_segment_mask = 0x10,
3036c730ff32SHans Verkuil .edid_spa_loc_reg = 0x76,
3037c730ff32SHans Verkuil .edid_spa_loc_msb_mask = 0x40,
3038c730ff32SHans Verkuil .edid_spa_port_b_reg = 0x70,
3039d42010a1SLars-Peter Clausen .lcf_reg = 0xb3,
3040d42010a1SLars-Peter Clausen .tdms_lock_mask = 0xe0,
3041d42010a1SLars-Peter Clausen .cable_det_mask = 0x1e,
3042d42010a1SLars-Peter Clausen .fmt_change_digital_mask = 0xc1,
304380f4944eSjean-michel.hautbois@vodalys.com .cp_csc = 0xfc,
304440d91c99SHans Verkuil .cec_irq_status = 0x4d,
304540d91c99SHans Verkuil .cec_rx_enable = 0x26,
304640d91c99SHans Verkuil .cec_rx_enable_mask = 0x01,
304740d91c99SHans Verkuil .cec_irq_swap = true,
3048539b33b0SLaurent Pinchart .formats = adv7604_formats,
3049539b33b0SLaurent Pinchart .nformats = ARRAY_SIZE(adv7604_formats),
3050d42010a1SLars-Peter Clausen .set_termination = adv7604_set_termination,
3051d42010a1SLars-Peter Clausen .setup_irqs = adv7604_setup_irqs,
3052d42010a1SLars-Peter Clausen .read_hdmi_pixelclock = adv7604_read_hdmi_pixelclock,
3053d42010a1SLars-Peter Clausen .read_cable_det = adv7604_read_cable_det,
3054d42010a1SLars-Peter Clausen .recommended_settings = {
3055d42010a1SLars-Peter Clausen [0] = adv7604_recommended_settings_afe,
3056d42010a1SLars-Peter Clausen [1] = adv7604_recommended_settings_hdmi,
3057d42010a1SLars-Peter Clausen },
3058d42010a1SLars-Peter Clausen .num_recommended_settings = {
3059d42010a1SLars-Peter Clausen [0] = ARRAY_SIZE(adv7604_recommended_settings_afe),
3060d42010a1SLars-Peter Clausen [1] = ARRAY_SIZE(adv7604_recommended_settings_hdmi),
3061d42010a1SLars-Peter Clausen },
3062b44b2e06SPablo Anton .page_mask = BIT(ADV76XX_PAGE_IO) | BIT(ADV7604_PAGE_AVLINK) |
3063b44b2e06SPablo Anton BIT(ADV76XX_PAGE_CEC) | BIT(ADV76XX_PAGE_INFOFRAME) |
3064d42010a1SLars-Peter Clausen BIT(ADV7604_PAGE_ESDP) | BIT(ADV7604_PAGE_DPP) |
3065b44b2e06SPablo Anton BIT(ADV76XX_PAGE_AFE) | BIT(ADV76XX_PAGE_REP) |
3066b44b2e06SPablo Anton BIT(ADV76XX_PAGE_EDID) | BIT(ADV76XX_PAGE_HDMI) |
3067b44b2e06SPablo Anton BIT(ADV76XX_PAGE_TEST) | BIT(ADV76XX_PAGE_CP) |
3068d42010a1SLars-Peter Clausen BIT(ADV7604_PAGE_VDP),
30695380baafSjean-michel.hautbois@vodalys.com .linewidth_mask = 0xfff,
30705380baafSjean-michel.hautbois@vodalys.com .field0_height_mask = 0xfff,
30715380baafSjean-michel.hautbois@vodalys.com .field1_height_mask = 0xfff,
30725380baafSjean-michel.hautbois@vodalys.com .hfrontporch_mask = 0x3ff,
30735380baafSjean-michel.hautbois@vodalys.com .hsync_mask = 0x3ff,
30745380baafSjean-michel.hautbois@vodalys.com .hbackporch_mask = 0x3ff,
30755380baafSjean-michel.hautbois@vodalys.com .field0_vfrontporch_mask = 0x1fff,
30765380baafSjean-michel.hautbois@vodalys.com .field0_vsync_mask = 0x1fff,
30775380baafSjean-michel.hautbois@vodalys.com .field0_vbackporch_mask = 0x1fff,
30785380baafSjean-michel.hautbois@vodalys.com .field1_vfrontporch_mask = 0x1fff,
30795380baafSjean-michel.hautbois@vodalys.com .field1_vsync_mask = 0x1fff,
30805380baafSjean-michel.hautbois@vodalys.com .field1_vbackporch_mask = 0x1fff,
3081d42010a1SLars-Peter Clausen },
3082d42010a1SLars-Peter Clausen [ADV7611] = {
3083d42010a1SLars-Peter Clausen .type = ADV7611,
3084d42010a1SLars-Peter Clausen .has_afe = false,
3085b44b2e06SPablo Anton .max_port = ADV76XX_PAD_HDMI_PORT_A,
3086d42010a1SLars-Peter Clausen .num_dv_ports = 1,
3087d42010a1SLars-Peter Clausen .edid_enable_reg = 0x74,
3088d42010a1SLars-Peter Clausen .edid_status_reg = 0x76,
3089c730ff32SHans Verkuil .edid_segment_reg = 0x7a,
3090c730ff32SHans Verkuil .edid_segment_mask = 0x01,
3091d42010a1SLars-Peter Clausen .lcf_reg = 0xa3,
3092d42010a1SLars-Peter Clausen .tdms_lock_mask = 0x43,
3093d42010a1SLars-Peter Clausen .cable_det_mask = 0x01,
3094d42010a1SLars-Peter Clausen .fmt_change_digital_mask = 0x03,
309580f4944eSjean-michel.hautbois@vodalys.com .cp_csc = 0xf4,
309640d91c99SHans Verkuil .cec_irq_status = 0x93,
309740d91c99SHans Verkuil .cec_rx_enable = 0x2c,
309840d91c99SHans Verkuil .cec_rx_enable_mask = 0x02,
3099539b33b0SLaurent Pinchart .formats = adv7611_formats,
3100539b33b0SLaurent Pinchart .nformats = ARRAY_SIZE(adv7611_formats),
3101d42010a1SLars-Peter Clausen .set_termination = adv7611_set_termination,
3102d42010a1SLars-Peter Clausen .setup_irqs = adv7611_setup_irqs,
3103d42010a1SLars-Peter Clausen .read_hdmi_pixelclock = adv7611_read_hdmi_pixelclock,
3104d42010a1SLars-Peter Clausen .read_cable_det = adv7611_read_cable_det,
3105d42010a1SLars-Peter Clausen .recommended_settings = {
3106d42010a1SLars-Peter Clausen [1] = adv7611_recommended_settings_hdmi,
3107d42010a1SLars-Peter Clausen },
3108d42010a1SLars-Peter Clausen .num_recommended_settings = {
3109d42010a1SLars-Peter Clausen [1] = ARRAY_SIZE(adv7611_recommended_settings_hdmi),
3110d42010a1SLars-Peter Clausen },
3111b44b2e06SPablo Anton .page_mask = BIT(ADV76XX_PAGE_IO) | BIT(ADV76XX_PAGE_CEC) |
3112b44b2e06SPablo Anton BIT(ADV76XX_PAGE_INFOFRAME) | BIT(ADV76XX_PAGE_AFE) |
3113b44b2e06SPablo Anton BIT(ADV76XX_PAGE_REP) | BIT(ADV76XX_PAGE_EDID) |
3114b44b2e06SPablo Anton BIT(ADV76XX_PAGE_HDMI) | BIT(ADV76XX_PAGE_CP),
31155380baafSjean-michel.hautbois@vodalys.com .linewidth_mask = 0x1fff,
31165380baafSjean-michel.hautbois@vodalys.com .field0_height_mask = 0x1fff,
31175380baafSjean-michel.hautbois@vodalys.com .field1_height_mask = 0x1fff,
31185380baafSjean-michel.hautbois@vodalys.com .hfrontporch_mask = 0x1fff,
31195380baafSjean-michel.hautbois@vodalys.com .hsync_mask = 0x1fff,
31205380baafSjean-michel.hautbois@vodalys.com .hbackporch_mask = 0x1fff,
31215380baafSjean-michel.hautbois@vodalys.com .field0_vfrontporch_mask = 0x3fff,
31225380baafSjean-michel.hautbois@vodalys.com .field0_vsync_mask = 0x3fff,
31235380baafSjean-michel.hautbois@vodalys.com .field0_vbackporch_mask = 0x3fff,
31245380baafSjean-michel.hautbois@vodalys.com .field1_vfrontporch_mask = 0x3fff,
31255380baafSjean-michel.hautbois@vodalys.com .field1_vsync_mask = 0x3fff,
31265380baafSjean-michel.hautbois@vodalys.com .field1_vbackporch_mask = 0x3fff,
3127d42010a1SLars-Peter Clausen },
31288331d30bSWilliam Towle [ADV7612] = {
31298331d30bSWilliam Towle .type = ADV7612,
31308331d30bSWilliam Towle .has_afe = false,
31317111cdddSWilliam Towle .max_port = ADV76XX_PAD_HDMI_PORT_A, /* B not supported */
31327111cdddSWilliam Towle .num_dv_ports = 1, /* normally 2 */
31338331d30bSWilliam Towle .edid_enable_reg = 0x74,
31348331d30bSWilliam Towle .edid_status_reg = 0x76,
3135c730ff32SHans Verkuil .edid_segment_reg = 0x7a,
3136c730ff32SHans Verkuil .edid_segment_mask = 0x01,
3137c730ff32SHans Verkuil .edid_spa_loc_reg = 0x70,
3138c730ff32SHans Verkuil .edid_spa_loc_msb_mask = 0x01,
3139c730ff32SHans Verkuil .edid_spa_port_b_reg = 0x52,
31408331d30bSWilliam Towle .lcf_reg = 0xa3,
31418331d30bSWilliam Towle .tdms_lock_mask = 0x43,
31428331d30bSWilliam Towle .cable_det_mask = 0x01,
31438331d30bSWilliam Towle .fmt_change_digital_mask = 0x03,
31447111cdddSWilliam Towle .cp_csc = 0xf4,
314540d91c99SHans Verkuil .cec_irq_status = 0x93,
314640d91c99SHans Verkuil .cec_rx_enable = 0x2c,
314740d91c99SHans Verkuil .cec_rx_enable_mask = 0x02,
31488331d30bSWilliam Towle .formats = adv7612_formats,
31498331d30bSWilliam Towle .nformats = ARRAY_SIZE(adv7612_formats),
31508331d30bSWilliam Towle .set_termination = adv7611_set_termination,
31518331d30bSWilliam Towle .setup_irqs = adv7612_setup_irqs,
31528331d30bSWilliam Towle .read_hdmi_pixelclock = adv7611_read_hdmi_pixelclock,
31537111cdddSWilliam Towle .read_cable_det = adv7612_read_cable_det,
31548331d30bSWilliam Towle .recommended_settings = {
31558331d30bSWilliam Towle [1] = adv7612_recommended_settings_hdmi,
31568331d30bSWilliam Towle },
31578331d30bSWilliam Towle .num_recommended_settings = {
31588331d30bSWilliam Towle [1] = ARRAY_SIZE(adv7612_recommended_settings_hdmi),
31598331d30bSWilliam Towle },
31608331d30bSWilliam Towle .page_mask = BIT(ADV76XX_PAGE_IO) | BIT(ADV76XX_PAGE_CEC) |
31618331d30bSWilliam Towle BIT(ADV76XX_PAGE_INFOFRAME) | BIT(ADV76XX_PAGE_AFE) |
31628331d30bSWilliam Towle BIT(ADV76XX_PAGE_REP) | BIT(ADV76XX_PAGE_EDID) |
31638331d30bSWilliam Towle BIT(ADV76XX_PAGE_HDMI) | BIT(ADV76XX_PAGE_CP),
31648331d30bSWilliam Towle .linewidth_mask = 0x1fff,
31658331d30bSWilliam Towle .field0_height_mask = 0x1fff,
31668331d30bSWilliam Towle .field1_height_mask = 0x1fff,
31678331d30bSWilliam Towle .hfrontporch_mask = 0x1fff,
31688331d30bSWilliam Towle .hsync_mask = 0x1fff,
31698331d30bSWilliam Towle .hbackporch_mask = 0x1fff,
31708331d30bSWilliam Towle .field0_vfrontporch_mask = 0x3fff,
31718331d30bSWilliam Towle .field0_vsync_mask = 0x3fff,
31728331d30bSWilliam Towle .field0_vbackporch_mask = 0x3fff,
31738331d30bSWilliam Towle .field1_vfrontporch_mask = 0x3fff,
31748331d30bSWilliam Towle .field1_vsync_mask = 0x3fff,
31758331d30bSWilliam Towle .field1_vbackporch_mask = 0x3fff,
31768331d30bSWilliam Towle },
3177d42010a1SLars-Peter Clausen };
3178d42010a1SLars-Peter Clausen
31797f099a75SFabian Frederick static const struct i2c_device_id adv76xx_i2c_id[] = {
3180b44b2e06SPablo Anton { "adv7604", (kernel_ulong_t)&adv76xx_chip_info[ADV7604] },
3181c2c88a07SKrzysztof Hałasa { "adv7610", (kernel_ulong_t)&adv76xx_chip_info[ADV7611] },
3182b44b2e06SPablo Anton { "adv7611", (kernel_ulong_t)&adv76xx_chip_info[ADV7611] },
31838331d30bSWilliam Towle { "adv7612", (kernel_ulong_t)&adv76xx_chip_info[ADV7612] },
3184f82f313eSLaurent Pinchart { }
3185f82f313eSLaurent Pinchart };
3186b44b2e06SPablo Anton MODULE_DEVICE_TABLE(i2c, adv76xx_i2c_id);
3187f82f313eSLaurent Pinchart
31887f099a75SFabian Frederick static const struct of_device_id adv76xx_of_id[] __maybe_unused = {
3189c2c88a07SKrzysztof Hałasa { .compatible = "adi,adv7610", .data = &adv76xx_chip_info[ADV7611] },
3190b44b2e06SPablo Anton { .compatible = "adi,adv7611", .data = &adv76xx_chip_info[ADV7611] },
31918331d30bSWilliam Towle { .compatible = "adi,adv7612", .data = &adv76xx_chip_info[ADV7612] },
3192f82f313eSLaurent Pinchart { }
3193f82f313eSLaurent Pinchart };
3194b44b2e06SPablo Anton MODULE_DEVICE_TABLE(of, adv76xx_of_id);
3195f82f313eSLaurent Pinchart
adv76xx_parse_dt(struct adv76xx_state * state)3196b44b2e06SPablo Anton static int adv76xx_parse_dt(struct adv76xx_state *state)
3197f82f313eSLaurent Pinchart {
319860359a28SSakari Ailus struct v4l2_fwnode_endpoint bus_cfg = { .bus_type = 0 };
31996fa88045SLaurent Pinchart struct device_node *endpoint;
32006fa88045SLaurent Pinchart struct device_node *np;
32016fa88045SLaurent Pinchart unsigned int flags;
32027f6cd6c4SJavier Martinez Canillas int ret;
3203bf9c8227SIan Molton u32 v;
32046fa88045SLaurent Pinchart
3205b44b2e06SPablo Anton np = state->i2c_clients[ADV76XX_PAGE_IO]->dev.of_node;
32066fa88045SLaurent Pinchart
32076fa88045SLaurent Pinchart /* Parse the endpoint. */
32086fa88045SLaurent Pinchart endpoint = of_graph_get_next_endpoint(np, NULL);
32096fa88045SLaurent Pinchart if (!endpoint)
32106fa88045SLaurent Pinchart return -EINVAL;
32116fa88045SLaurent Pinchart
3212859969b3SSakari Ailus ret = v4l2_fwnode_endpoint_parse(of_fwnode_handle(endpoint), &bus_cfg);
32137f6cd6c4SJavier Martinez Canillas of_node_put(endpoint);
3214e32eb0d8SNicholas Mc Guire if (ret)
32157f6cd6c4SJavier Martinez Canillas return ret;
3216c57a68a1SUlrich Hecht
3217c57a68a1SUlrich Hecht if (!of_property_read_u32(np, "default-input", &v))
3218bf9c8227SIan Molton state->pdata.default_input = v;
3219bf9c8227SIan Molton else
3220bf9c8227SIan Molton state->pdata.default_input = -1;
3221bf9c8227SIan Molton
32226fa88045SLaurent Pinchart flags = bus_cfg.bus.parallel.flags;
32236fa88045SLaurent Pinchart
32246fa88045SLaurent Pinchart if (flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH)
32256fa88045SLaurent Pinchart state->pdata.inv_hs_pol = 1;
32266fa88045SLaurent Pinchart
32276fa88045SLaurent Pinchart if (flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH)
32286fa88045SLaurent Pinchart state->pdata.inv_vs_pol = 1;
32296fa88045SLaurent Pinchart
32306fa88045SLaurent Pinchart if (flags & V4L2_MBUS_PCLK_SAMPLE_RISING)
32316fa88045SLaurent Pinchart state->pdata.inv_llc_pol = 1;
32326fa88045SLaurent Pinchart
3233fd74246dSHans Verkuil if (bus_cfg.bus_type == V4L2_MBUS_BT656)
32346fa88045SLaurent Pinchart state->pdata.insert_av_codes = 1;
32356fa88045SLaurent Pinchart
3236f82f313eSLaurent Pinchart /* Disable the interrupt for now as no DT-based board uses it. */
323740d91c99SHans Verkuil state->pdata.int1_config = ADV76XX_INT1_CONFIG_ACTIVE_HIGH;
3238f82f313eSLaurent Pinchart
3239f82f313eSLaurent Pinchart /* Hardcode the remaining platform data fields. */
3240f82f313eSLaurent Pinchart state->pdata.disable_pwrdnb = 0;
3241f82f313eSLaurent Pinchart state->pdata.disable_cable_det_rst = 0;
3242f82f313eSLaurent Pinchart state->pdata.blank_data = 1;
3243f82f313eSLaurent Pinchart state->pdata.op_format_mode_sel = ADV7604_OP_FORMAT_MODE0;
3244f82f313eSLaurent Pinchart state->pdata.bus_order = ADV7604_BUS_ORDER_RGB;
3245da8892d4SLars-Peter Clausen state->pdata.dr_str_data = ADV76XX_DR_STR_MEDIUM_HIGH;
3246da8892d4SLars-Peter Clausen state->pdata.dr_str_clk = ADV76XX_DR_STR_MEDIUM_HIGH;
3247da8892d4SLars-Peter Clausen state->pdata.dr_str_sync = ADV76XX_DR_STR_MEDIUM_HIGH;
3248f82f313eSLaurent Pinchart
3249f82f313eSLaurent Pinchart return 0;
3250f82f313eSLaurent Pinchart }
3251f82f313eSLaurent Pinchart
3252f862f57dSPablo Anton static const struct regmap_config adv76xx_regmap_cnf[] = {
3253f862f57dSPablo Anton {
3254f862f57dSPablo Anton .name = "io",
3255f862f57dSPablo Anton .reg_bits = 8,
3256f862f57dSPablo Anton .val_bits = 8,
3257f862f57dSPablo Anton
3258f862f57dSPablo Anton .max_register = 0xff,
3259f862f57dSPablo Anton .cache_type = REGCACHE_NONE,
3260f862f57dSPablo Anton },
3261f862f57dSPablo Anton {
3262f862f57dSPablo Anton .name = "avlink",
3263f862f57dSPablo Anton .reg_bits = 8,
3264f862f57dSPablo Anton .val_bits = 8,
3265f862f57dSPablo Anton
3266f862f57dSPablo Anton .max_register = 0xff,
3267f862f57dSPablo Anton .cache_type = REGCACHE_NONE,
3268f862f57dSPablo Anton },
3269f862f57dSPablo Anton {
3270f862f57dSPablo Anton .name = "cec",
3271f862f57dSPablo Anton .reg_bits = 8,
3272f862f57dSPablo Anton .val_bits = 8,
3273f862f57dSPablo Anton
3274f862f57dSPablo Anton .max_register = 0xff,
3275f862f57dSPablo Anton .cache_type = REGCACHE_NONE,
3276f862f57dSPablo Anton },
3277f862f57dSPablo Anton {
3278f862f57dSPablo Anton .name = "infoframe",
3279f862f57dSPablo Anton .reg_bits = 8,
3280f862f57dSPablo Anton .val_bits = 8,
3281f862f57dSPablo Anton
3282f862f57dSPablo Anton .max_register = 0xff,
3283f862f57dSPablo Anton .cache_type = REGCACHE_NONE,
3284f862f57dSPablo Anton },
3285f862f57dSPablo Anton {
3286f862f57dSPablo Anton .name = "esdp",
3287f862f57dSPablo Anton .reg_bits = 8,
3288f862f57dSPablo Anton .val_bits = 8,
3289f862f57dSPablo Anton
3290f862f57dSPablo Anton .max_register = 0xff,
3291f862f57dSPablo Anton .cache_type = REGCACHE_NONE,
3292f862f57dSPablo Anton },
3293f862f57dSPablo Anton {
3294f862f57dSPablo Anton .name = "epp",
3295f862f57dSPablo Anton .reg_bits = 8,
3296f862f57dSPablo Anton .val_bits = 8,
3297f862f57dSPablo Anton
3298f862f57dSPablo Anton .max_register = 0xff,
3299f862f57dSPablo Anton .cache_type = REGCACHE_NONE,
3300f862f57dSPablo Anton },
3301f862f57dSPablo Anton {
3302f862f57dSPablo Anton .name = "afe",
3303f862f57dSPablo Anton .reg_bits = 8,
3304f862f57dSPablo Anton .val_bits = 8,
3305f862f57dSPablo Anton
3306f862f57dSPablo Anton .max_register = 0xff,
3307f862f57dSPablo Anton .cache_type = REGCACHE_NONE,
3308f862f57dSPablo Anton },
3309f862f57dSPablo Anton {
3310f862f57dSPablo Anton .name = "rep",
3311f862f57dSPablo Anton .reg_bits = 8,
3312f862f57dSPablo Anton .val_bits = 8,
3313f862f57dSPablo Anton
3314f862f57dSPablo Anton .max_register = 0xff,
3315f862f57dSPablo Anton .cache_type = REGCACHE_NONE,
3316f862f57dSPablo Anton },
3317f862f57dSPablo Anton {
3318f862f57dSPablo Anton .name = "edid",
3319f862f57dSPablo Anton .reg_bits = 8,
3320f862f57dSPablo Anton .val_bits = 8,
3321f862f57dSPablo Anton
3322f862f57dSPablo Anton .max_register = 0xff,
3323f862f57dSPablo Anton .cache_type = REGCACHE_NONE,
3324f862f57dSPablo Anton },
3325f862f57dSPablo Anton
3326f862f57dSPablo Anton {
3327f862f57dSPablo Anton .name = "hdmi",
3328f862f57dSPablo Anton .reg_bits = 8,
3329f862f57dSPablo Anton .val_bits = 8,
3330f862f57dSPablo Anton
3331f862f57dSPablo Anton .max_register = 0xff,
3332f862f57dSPablo Anton .cache_type = REGCACHE_NONE,
3333f862f57dSPablo Anton },
3334f862f57dSPablo Anton {
3335f862f57dSPablo Anton .name = "test",
3336f862f57dSPablo Anton .reg_bits = 8,
3337f862f57dSPablo Anton .val_bits = 8,
3338f862f57dSPablo Anton
3339f862f57dSPablo Anton .max_register = 0xff,
3340f862f57dSPablo Anton .cache_type = REGCACHE_NONE,
3341f862f57dSPablo Anton },
3342f862f57dSPablo Anton {
3343f862f57dSPablo Anton .name = "cp",
3344f862f57dSPablo Anton .reg_bits = 8,
3345f862f57dSPablo Anton .val_bits = 8,
3346f862f57dSPablo Anton
3347f862f57dSPablo Anton .max_register = 0xff,
3348f862f57dSPablo Anton .cache_type = REGCACHE_NONE,
3349f862f57dSPablo Anton },
3350f862f57dSPablo Anton {
3351f862f57dSPablo Anton .name = "vdp",
3352f862f57dSPablo Anton .reg_bits = 8,
3353f862f57dSPablo Anton .val_bits = 8,
3354f862f57dSPablo Anton
3355f862f57dSPablo Anton .max_register = 0xff,
3356f862f57dSPablo Anton .cache_type = REGCACHE_NONE,
3357f862f57dSPablo Anton },
3358f862f57dSPablo Anton };
3359f862f57dSPablo Anton
configure_regmap(struct adv76xx_state * state,int region)3360f862f57dSPablo Anton static int configure_regmap(struct adv76xx_state *state, int region)
3361f862f57dSPablo Anton {
3362f862f57dSPablo Anton int err;
3363f862f57dSPablo Anton
3364f862f57dSPablo Anton if (!state->i2c_clients[region])
3365f862f57dSPablo Anton return -ENODEV;
3366f862f57dSPablo Anton
3367f862f57dSPablo Anton state->regmap[region] =
3368f862f57dSPablo Anton devm_regmap_init_i2c(state->i2c_clients[region],
3369f862f57dSPablo Anton &adv76xx_regmap_cnf[region]);
3370f862f57dSPablo Anton
3371f862f57dSPablo Anton if (IS_ERR(state->regmap[region])) {
3372f862f57dSPablo Anton err = PTR_ERR(state->regmap[region]);
3373f862f57dSPablo Anton v4l_err(state->i2c_clients[region],
3374f862f57dSPablo Anton "Error initializing regmap %d with error %d\n",
3375f862f57dSPablo Anton region, err);
3376f862f57dSPablo Anton return -EINVAL;
3377f862f57dSPablo Anton }
3378f862f57dSPablo Anton
3379f862f57dSPablo Anton return 0;
3380f862f57dSPablo Anton }
3381f862f57dSPablo Anton
configure_regmaps(struct adv76xx_state * state)3382f862f57dSPablo Anton static int configure_regmaps(struct adv76xx_state *state)
3383f862f57dSPablo Anton {
3384f862f57dSPablo Anton int i, err;
3385f862f57dSPablo Anton
3386f862f57dSPablo Anton for (i = ADV7604_PAGE_AVLINK ; i < ADV76XX_PAGE_MAX; i++) {
3387f862f57dSPablo Anton err = configure_regmap(state, i);
3388f862f57dSPablo Anton if (err && (err != -ENODEV))
3389f862f57dSPablo Anton return err;
3390f862f57dSPablo Anton }
3391f862f57dSPablo Anton return 0;
3392f862f57dSPablo Anton }
3393f862f57dSPablo Anton
adv76xx_reset(struct adv76xx_state * state)3394f5591da9SDragos Bogdan static void adv76xx_reset(struct adv76xx_state *state)
3395f5591da9SDragos Bogdan {
3396f5591da9SDragos Bogdan if (state->reset_gpio) {
3397f5591da9SDragos Bogdan /* ADV76XX can be reset by a low reset pulse of minimum 5 ms. */
3398f5591da9SDragos Bogdan gpiod_set_value_cansleep(state->reset_gpio, 0);
3399f5591da9SDragos Bogdan usleep_range(5000, 10000);
3400f5591da9SDragos Bogdan gpiod_set_value_cansleep(state->reset_gpio, 1);
3401f5591da9SDragos Bogdan /* It is recommended to wait 5 ms after the low pulse before */
3402f5591da9SDragos Bogdan /* an I2C write is performed to the ADV76XX. */
3403f5591da9SDragos Bogdan usleep_range(5000, 10000);
3404f5591da9SDragos Bogdan }
3405f5591da9SDragos Bogdan }
3406f5591da9SDragos Bogdan
adv76xx_probe(struct i2c_client * client)3407220ac14bSUwe Kleine-König static int adv76xx_probe(struct i2c_client *client)
340854450f59SHans Verkuil {
3409220ac14bSUwe Kleine-König const struct i2c_device_id *id = i2c_client_get_device_id(client);
3410591b72feSHans Verkuil static const struct v4l2_dv_timings cea640x480 =
3411591b72feSHans Verkuil V4L2_DV_BT_CEA_640X480P59_94;
3412b44b2e06SPablo Anton struct adv76xx_state *state;
341354450f59SHans Verkuil struct v4l2_ctrl_handler *hdl;
3414297a4144SHans Verkuil struct v4l2_ctrl *ctrl;
341554450f59SHans Verkuil struct v4l2_subdev *sd;
3416c784b1e2SLaurent Pinchart unsigned int i;
3417f862f57dSPablo Anton unsigned int val, val2;
341854450f59SHans Verkuil int err;
341954450f59SHans Verkuil
342054450f59SHans Verkuil /* Check if the adapter supports the needed features */
342154450f59SHans Verkuil if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
342254450f59SHans Verkuil return -EIO;
3423b44b2e06SPablo Anton v4l_dbg(1, debug, client, "detecting adv76xx client on address 0x%x\n",
342454450f59SHans Verkuil client->addr << 1);
342554450f59SHans Verkuil
3426c02b211dSLaurent Pinchart state = devm_kzalloc(&client->dev, sizeof(*state), GFP_KERNEL);
3427c38e8657SMarkus Elfring if (!state)
342854450f59SHans Verkuil return -ENOMEM;
342954450f59SHans Verkuil
3430b44b2e06SPablo Anton state->i2c_clients[ADV76XX_PAGE_IO] = client;
3431d42010a1SLars-Peter Clausen
343225a64ac9SMats Randgaard /* initialize variables */
343325a64ac9SMats Randgaard state->restart_stdi_once = true;
3434ff4f80fdSMats Randgaard state->selected_input = ~0;
343525a64ac9SMats Randgaard
3436f82f313eSLaurent Pinchart if (IS_ENABLED(CONFIG_OF) && client->dev.of_node) {
3437f82f313eSLaurent Pinchart const struct of_device_id *oid;
3438f82f313eSLaurent Pinchart
3439b44b2e06SPablo Anton oid = of_match_node(adv76xx_of_id, client->dev.of_node);
3440f82f313eSLaurent Pinchart state->info = oid->data;
3441f82f313eSLaurent Pinchart
3442b44b2e06SPablo Anton err = adv76xx_parse_dt(state);
3443f82f313eSLaurent Pinchart if (err < 0) {
3444f82f313eSLaurent Pinchart v4l_err(client, "DT parsing error\n");
3445f82f313eSLaurent Pinchart return err;
3446f82f313eSLaurent Pinchart }
3447f82f313eSLaurent Pinchart } else if (client->dev.platform_data) {
3448b44b2e06SPablo Anton struct adv76xx_platform_data *pdata = client->dev.platform_data;
3449f82f313eSLaurent Pinchart
3450b44b2e06SPablo Anton state->info = (const struct adv76xx_chip_info *)id->driver_data;
3451f82f313eSLaurent Pinchart state->pdata = *pdata;
3452f82f313eSLaurent Pinchart } else {
345354450f59SHans Verkuil v4l_err(client, "No platform data!\n");
3454c02b211dSLaurent Pinchart return -ENODEV;
345554450f59SHans Verkuil }
3456e9d50e9eSLaurent Pinchart
3457e9d50e9eSLaurent Pinchart /* Request GPIOs. */
3458e9d50e9eSLaurent Pinchart for (i = 0; i < state->info->num_dv_ports; ++i) {
3459e9d50e9eSLaurent Pinchart state->hpd_gpio[i] =
3460269bd132SUwe Kleine-König devm_gpiod_get_index_optional(&client->dev, "hpd", i,
3461269bd132SUwe Kleine-König GPIOD_OUT_LOW);
3462e9d50e9eSLaurent Pinchart if (IS_ERR(state->hpd_gpio[i]))
3463269bd132SUwe Kleine-König return PTR_ERR(state->hpd_gpio[i]);
3464e9d50e9eSLaurent Pinchart
3465269bd132SUwe Kleine-König if (state->hpd_gpio[i])
3466e9d50e9eSLaurent Pinchart v4l_info(client, "Handling HPD %u GPIO\n", i);
3467e9d50e9eSLaurent Pinchart }
3468f5591da9SDragos Bogdan state->reset_gpio = devm_gpiod_get_optional(&client->dev, "reset",
3469f5591da9SDragos Bogdan GPIOD_OUT_HIGH);
3470f5591da9SDragos Bogdan if (IS_ERR(state->reset_gpio))
3471f5591da9SDragos Bogdan return PTR_ERR(state->reset_gpio);
3472f5591da9SDragos Bogdan
3473f5591da9SDragos Bogdan adv76xx_reset(state);
3474e9d50e9eSLaurent Pinchart
3475591b72feSHans Verkuil state->timings = cea640x480;
3476b44b2e06SPablo Anton state->format = adv76xx_format_info(state, MEDIA_BUS_FMT_YUYV8_2X8);
347754450f59SHans Verkuil
347854450f59SHans Verkuil sd = &state->sd;
3479b44b2e06SPablo Anton v4l2_i2c_subdev_init(sd, client, &adv76xx_ops);
3480d42010a1SLars-Peter Clausen snprintf(sd->name, sizeof(sd->name), "%s %d-%04x",
3481d42010a1SLars-Peter Clausen id->name, i2c_adapter_id(client->adapter),
3482d42010a1SLars-Peter Clausen client->addr);
34830975626dSLars-Peter Clausen sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS;
348441a52373SHans Verkuil sd->internal_ops = &adv76xx_int_ops;
348554450f59SHans Verkuil
3486f862f57dSPablo Anton /* Configure IO Regmap region */
3487f862f57dSPablo Anton err = configure_regmap(state, ADV76XX_PAGE_IO);
3488f862f57dSPablo Anton
3489f862f57dSPablo Anton if (err) {
3490f862f57dSPablo Anton v4l2_err(sd, "Error configuring IO regmap region\n");
3491f862f57dSPablo Anton return -ENODEV;
3492f862f57dSPablo Anton }
3493f862f57dSPablo Anton
3494d42010a1SLars-Peter Clausen /*
3495d42010a1SLars-Peter Clausen * Verify that the chip is present. On ADV7604 the RD_INFO register only
3496d42010a1SLars-Peter Clausen * identifies the revision, while on ADV7611 it identifies the model as
3497d42010a1SLars-Peter Clausen * well. Use the HDMI slave address on ADV7604 and RD_INFO on ADV7611.
3498d42010a1SLars-Peter Clausen */
34998331d30bSWilliam Towle switch (state->info->type) {
35008331d30bSWilliam Towle case ADV7604:
3501f862f57dSPablo Anton err = regmap_read(state->regmap[ADV76XX_PAGE_IO], 0xfb, &val);
3502f862f57dSPablo Anton if (err) {
3503f862f57dSPablo Anton v4l2_err(sd, "Error %d reading IO Regmap\n", err);
3504f862f57dSPablo Anton return -ENODEV;
3505f862f57dSPablo Anton }
3506d42010a1SLars-Peter Clausen if (val != 0x68) {
3507c2c88a07SKrzysztof Hałasa v4l2_err(sd, "not an ADV7604 on address 0x%x\n",
350854450f59SHans Verkuil client->addr << 1);
3509c02b211dSLaurent Pinchart return -ENODEV;
351054450f59SHans Verkuil }
35118331d30bSWilliam Towle break;
35128331d30bSWilliam Towle case ADV7611:
35138331d30bSWilliam Towle case ADV7612:
3514f862f57dSPablo Anton err = regmap_read(state->regmap[ADV76XX_PAGE_IO],
3515f862f57dSPablo Anton 0xea,
3516f862f57dSPablo Anton &val);
3517f862f57dSPablo Anton if (err) {
3518f862f57dSPablo Anton v4l2_err(sd, "Error %d reading IO Regmap\n", err);
3519f862f57dSPablo Anton return -ENODEV;
3520f862f57dSPablo Anton }
3521f862f57dSPablo Anton val2 = val << 8;
3522f862f57dSPablo Anton err = regmap_read(state->regmap[ADV76XX_PAGE_IO],
3523f862f57dSPablo Anton 0xeb,
3524f862f57dSPablo Anton &val);
3525f862f57dSPablo Anton if (err) {
3526f862f57dSPablo Anton v4l2_err(sd, "Error %d reading IO Regmap\n", err);
3527f862f57dSPablo Anton return -ENODEV;
3528f862f57dSPablo Anton }
3529c1362384SWilliam Towle val |= val2;
35308331d30bSWilliam Towle if ((state->info->type == ADV7611 && val != 0x2051) ||
35318331d30bSWilliam Towle (state->info->type == ADV7612 && val != 0x2041)) {
3532c2c88a07SKrzysztof Hałasa v4l2_err(sd, "not an %s on address 0x%x\n",
3533c2c88a07SKrzysztof Hałasa state->info->type == ADV7611 ? "ADV7610/11" : "ADV7612",
3534d42010a1SLars-Peter Clausen client->addr << 1);
3535d42010a1SLars-Peter Clausen return -ENODEV;
3536d42010a1SLars-Peter Clausen }
35378331d30bSWilliam Towle break;
3538d42010a1SLars-Peter Clausen }
353954450f59SHans Verkuil
354054450f59SHans Verkuil /* control handlers */
354154450f59SHans Verkuil hdl = &state->hdl;
3542b44b2e06SPablo Anton v4l2_ctrl_handler_init(hdl, adv76xx_has_afe(state) ? 9 : 8);
354354450f59SHans Verkuil
3544b44b2e06SPablo Anton v4l2_ctrl_new_std(hdl, &adv76xx_ctrl_ops,
354554450f59SHans Verkuil V4L2_CID_BRIGHTNESS, -128, 127, 1, 0);
3546b44b2e06SPablo Anton v4l2_ctrl_new_std(hdl, &adv76xx_ctrl_ops,
354754450f59SHans Verkuil V4L2_CID_CONTRAST, 0, 255, 1, 128);
3548b44b2e06SPablo Anton v4l2_ctrl_new_std(hdl, &adv76xx_ctrl_ops,
354954450f59SHans Verkuil V4L2_CID_SATURATION, 0, 255, 1, 128);
3550b44b2e06SPablo Anton v4l2_ctrl_new_std(hdl, &adv76xx_ctrl_ops,
355168a9ca45SLaurent Pinchart V4L2_CID_HUE, 0, 255, 1, 0);
3552297a4144SHans Verkuil ctrl = v4l2_ctrl_new_std_menu(hdl, &adv76xx_ctrl_ops,
3553297a4144SHans Verkuil V4L2_CID_DV_RX_IT_CONTENT_TYPE, V4L2_DV_IT_CONTENT_TYPE_NO_ITC,
3554297a4144SHans Verkuil 0, V4L2_DV_IT_CONTENT_TYPE_NO_ITC);
3555297a4144SHans Verkuil if (ctrl)
3556297a4144SHans Verkuil ctrl->flags |= V4L2_CTRL_FLAG_VOLATILE;
355754450f59SHans Verkuil
355854450f59SHans Verkuil state->detect_tx_5v_ctrl = v4l2_ctrl_new_std(hdl, NULL,
3559d42010a1SLars-Peter Clausen V4L2_CID_DV_RX_POWER_PRESENT, 0,
3560d42010a1SLars-Peter Clausen (1 << state->info->num_dv_ports) - 1, 0, 0);
356154450f59SHans Verkuil state->rgb_quantization_range_ctrl =
3562b44b2e06SPablo Anton v4l2_ctrl_new_std_menu(hdl, &adv76xx_ctrl_ops,
356354450f59SHans Verkuil V4L2_CID_DV_RX_RGB_RANGE, V4L2_DV_RGB_RANGE_FULL,
356454450f59SHans Verkuil 0, V4L2_DV_RGB_RANGE_AUTO);
356554450f59SHans Verkuil
356654450f59SHans Verkuil /* custom controls */
3567b44b2e06SPablo Anton if (adv76xx_has_afe(state))
356854450f59SHans Verkuil state->analog_sampling_phase_ctrl =
356954450f59SHans Verkuil v4l2_ctrl_new_custom(hdl, &adv7604_ctrl_analog_sampling_phase, NULL);
357054450f59SHans Verkuil state->free_run_color_manual_ctrl =
3571b44b2e06SPablo Anton v4l2_ctrl_new_custom(hdl, &adv76xx_ctrl_free_run_color_manual, NULL);
357254450f59SHans Verkuil state->free_run_color_ctrl =
3573b44b2e06SPablo Anton v4l2_ctrl_new_custom(hdl, &adv76xx_ctrl_free_run_color, NULL);
357454450f59SHans Verkuil
357554450f59SHans Verkuil sd->ctrl_handler = hdl;
357654450f59SHans Verkuil if (hdl->error) {
357754450f59SHans Verkuil err = hdl->error;
357854450f59SHans Verkuil goto err_hdl;
357954450f59SHans Verkuil }
3580b44b2e06SPablo Anton if (adv76xx_s_detect_tx_5v_ctrl(sd)) {
358154450f59SHans Verkuil err = -ENODEV;
358254450f59SHans Verkuil goto err_hdl;
358354450f59SHans Verkuil }
358454450f59SHans Verkuil
3585b44b2e06SPablo Anton for (i = 1; i < ADV76XX_PAGE_MAX; ++i) {
3586af80559bSWolfram Sang struct i2c_client *dummy_client;
3587af80559bSWolfram Sang
358805cacb17SLaurent Pinchart if (!(BIT(i) & state->info->page_mask))
358905cacb17SLaurent Pinchart continue;
359005cacb17SLaurent Pinchart
3591af80559bSWolfram Sang dummy_client = adv76xx_dummy_client(sd, i);
3592af80559bSWolfram Sang if (IS_ERR(dummy_client)) {
3593af80559bSWolfram Sang err = PTR_ERR(dummy_client);
359405cacb17SLaurent Pinchart v4l2_err(sd, "failed to create i2c client %u\n", i);
359554450f59SHans Verkuil goto err_i2c;
359654450f59SHans Verkuil }
3597af80559bSWolfram Sang
3598af80559bSWolfram Sang state->i2c_clients[i] = dummy_client;
359905cacb17SLaurent Pinchart }
360054450f59SHans Verkuil
360154450f59SHans Verkuil INIT_DELAYED_WORK(&state->delayed_work_enable_hotplug,
3602b44b2e06SPablo Anton adv76xx_delayed_work_enable_hotplug);
360354450f59SHans Verkuil
3604c784b1e2SLaurent Pinchart state->source_pad = state->info->num_dv_ports
3605c784b1e2SLaurent Pinchart + (state->info->has_afe ? 2 : 0);
3606c784b1e2SLaurent Pinchart for (i = 0; i < state->source_pad; ++i)
3607c784b1e2SLaurent Pinchart state->pads[i].flags = MEDIA_PAD_FL_SINK;
3608c784b1e2SLaurent Pinchart state->pads[state->source_pad].flags = MEDIA_PAD_FL_SOURCE;
3609d272bc92SHans Verkuil sd->entity.function = MEDIA_ENT_F_DV_DECODER;
3610c784b1e2SLaurent Pinchart
3611ab22e77cSMauro Carvalho Chehab err = media_entity_pads_init(&sd->entity, state->source_pad + 1,
361218095107SMauro Carvalho Chehab state->pads);
361354450f59SHans Verkuil if (err)
361454450f59SHans Verkuil goto err_work_queues;
361554450f59SHans Verkuil
3616f862f57dSPablo Anton /* Configure regmaps */
3617f862f57dSPablo Anton err = configure_regmaps(state);
3618f862f57dSPablo Anton if (err)
3619f862f57dSPablo Anton goto err_entity;
3620f862f57dSPablo Anton
3621b44b2e06SPablo Anton err = adv76xx_core_init(sd);
362254450f59SHans Verkuil if (err)
362354450f59SHans Verkuil goto err_entity;
362441a52373SHans Verkuil
362540d91c99SHans Verkuil if (client->irq) {
362640d91c99SHans Verkuil err = devm_request_threaded_irq(&client->dev,
362740d91c99SHans Verkuil client->irq,
362840d91c99SHans Verkuil NULL, adv76xx_irq_handler,
362940d91c99SHans Verkuil IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
363040d91c99SHans Verkuil client->name, state);
363140d91c99SHans Verkuil if (err)
363240d91c99SHans Verkuil goto err_entity;
363340d91c99SHans Verkuil }
363440d91c99SHans Verkuil
363541a52373SHans Verkuil #if IS_ENABLED(CONFIG_VIDEO_ADV7604_CEC)
363641a52373SHans Verkuil state->cec_adap = cec_allocate_adapter(&adv76xx_cec_adap_ops,
363741a52373SHans Verkuil state, dev_name(&client->dev),
363857b79636SHans Verkuil CEC_CAP_DEFAULTS, ADV76XX_MAX_ADDRS);
363941a52373SHans Verkuil err = PTR_ERR_OR_ZERO(state->cec_adap);
364041a52373SHans Verkuil if (err)
364141a52373SHans Verkuil goto err_entity;
364241a52373SHans Verkuil #endif
364341a52373SHans Verkuil
364454450f59SHans Verkuil v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name,
364554450f59SHans Verkuil client->addr << 1, client->adapter->name);
3646bedc3939SLars-Peter Clausen
3647bedc3939SLars-Peter Clausen err = v4l2_async_register_subdev(sd);
3648bedc3939SLars-Peter Clausen if (err)
3649bedc3939SLars-Peter Clausen goto err_entity;
3650bedc3939SLars-Peter Clausen
365154450f59SHans Verkuil return 0;
365254450f59SHans Verkuil
365354450f59SHans Verkuil err_entity:
365454450f59SHans Verkuil media_entity_cleanup(&sd->entity);
365554450f59SHans Verkuil err_work_queues:
365654450f59SHans Verkuil cancel_delayed_work(&state->delayed_work_enable_hotplug);
365754450f59SHans Verkuil err_i2c:
3658b44b2e06SPablo Anton adv76xx_unregister_clients(state);
365954450f59SHans Verkuil err_hdl:
366054450f59SHans Verkuil v4l2_ctrl_handler_free(hdl);
366154450f59SHans Verkuil return err;
366254450f59SHans Verkuil }
366354450f59SHans Verkuil
366454450f59SHans Verkuil /* ----------------------------------------------------------------------- */
366554450f59SHans Verkuil
adv76xx_remove(struct i2c_client * client)3666ed5c2f5fSUwe Kleine-König static void adv76xx_remove(struct i2c_client *client)
366754450f59SHans Verkuil {
366854450f59SHans Verkuil struct v4l2_subdev *sd = i2c_get_clientdata(client);
3669b44b2e06SPablo Anton struct adv76xx_state *state = to_state(sd);
367054450f59SHans Verkuil
367141a52373SHans Verkuil /* disable interrupts */
367241a52373SHans Verkuil io_write(sd, 0x40, 0);
367341a52373SHans Verkuil io_write(sd, 0x41, 0);
367441a52373SHans Verkuil io_write(sd, 0x46, 0);
367541a52373SHans Verkuil io_write(sd, 0x6e, 0);
367641a52373SHans Verkuil io_write(sd, 0x73, 0);
367741a52373SHans Verkuil
3678fa56f5f1SYang Yingliang cancel_delayed_work_sync(&state->delayed_work_enable_hotplug);
3679bedc3939SLars-Peter Clausen v4l2_async_unregister_subdev(sd);
368054450f59SHans Verkuil media_entity_cleanup(&sd->entity);
3681b44b2e06SPablo Anton adv76xx_unregister_clients(to_state(sd));
368254450f59SHans Verkuil v4l2_ctrl_handler_free(sd->ctrl_handler);
368354450f59SHans Verkuil }
368454450f59SHans Verkuil
368554450f59SHans Verkuil /* ----------------------------------------------------------------------- */
368654450f59SHans Verkuil
3687b44b2e06SPablo Anton static struct i2c_driver adv76xx_driver = {
368854450f59SHans Verkuil .driver = {
368954450f59SHans Verkuil .name = "adv7604",
3690b44b2e06SPablo Anton .of_match_table = of_match_ptr(adv76xx_of_id),
369154450f59SHans Verkuil },
3692*aaeb31c0SUwe Kleine-König .probe = adv76xx_probe,
3693b44b2e06SPablo Anton .remove = adv76xx_remove,
3694b44b2e06SPablo Anton .id_table = adv76xx_i2c_id,
369554450f59SHans Verkuil };
369654450f59SHans Verkuil
3697b44b2e06SPablo Anton module_i2c_driver(adv76xx_driver);
3698