1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Analog Devices ADV7511 HDMI Transmitter Device Driver 4 * 5 * Copyright 2013 Cisco Systems, Inc. and/or its affiliates. All rights reserved. 6 */ 7 8 /* 9 * This file is named adv7511-v4l2.c so it doesn't conflict with the Analog 10 * Device ADV7511 (config fragment CONFIG_DRM_I2C_ADV7511). 11 */ 12 13 14 #include <linux/kernel.h> 15 #include <linux/module.h> 16 #include <linux/slab.h> 17 #include <linux/i2c.h> 18 #include <linux/delay.h> 19 #include <linux/videodev2.h> 20 #include <linux/gpio.h> 21 #include <linux/workqueue.h> 22 #include <linux/hdmi.h> 23 #include <linux/v4l2-dv-timings.h> 24 #include <media/v4l2-device.h> 25 #include <media/v4l2-common.h> 26 #include <media/v4l2-ctrls.h> 27 #include <media/v4l2-dv-timings.h> 28 #include <media/i2c/adv7511.h> 29 #include <media/cec.h> 30 31 static int debug; 32 module_param(debug, int, 0644); 33 MODULE_PARM_DESC(debug, "debug level (0-2)"); 34 35 MODULE_DESCRIPTION("Analog Devices ADV7511 HDMI Transmitter Device Driver"); 36 MODULE_AUTHOR("Hans Verkuil"); 37 MODULE_LICENSE("GPL v2"); 38 39 #define MASK_ADV7511_EDID_RDY_INT 0x04 40 #define MASK_ADV7511_MSEN_INT 0x40 41 #define MASK_ADV7511_HPD_INT 0x80 42 43 #define MASK_ADV7511_HPD_DETECT 0x40 44 #define MASK_ADV7511_MSEN_DETECT 0x20 45 #define MASK_ADV7511_EDID_RDY 0x10 46 47 #define EDID_MAX_RETRIES (8) 48 #define EDID_DELAY 250 49 #define EDID_MAX_SEGM 8 50 51 #define ADV7511_MAX_WIDTH 1920 52 #define ADV7511_MAX_HEIGHT 1200 53 #define ADV7511_MIN_PIXELCLOCK 20000000 54 #define ADV7511_MAX_PIXELCLOCK 225000000 55 56 #define ADV7511_MAX_ADDRS (3) 57 58 /* 59 ********************************************************************** 60 * 61 * Arrays with configuration parameters for the ADV7511 62 * 63 ********************************************************************** 64 */ 65 66 struct i2c_reg_value { 67 unsigned char reg; 68 unsigned char value; 69 }; 70 71 struct adv7511_state_edid { 72 /* total number of blocks */ 73 u32 blocks; 74 /* Number of segments read */ 75 u32 segments; 76 u8 data[EDID_MAX_SEGM * 256]; 77 /* Number of EDID read retries left */ 78 unsigned read_retries; 79 bool complete; 80 }; 81 82 struct adv7511_state { 83 struct adv7511_platform_data pdata; 84 struct v4l2_subdev sd; 85 struct media_pad pad; 86 struct v4l2_ctrl_handler hdl; 87 int chip_revision; 88 u8 i2c_edid_addr; 89 u8 i2c_pktmem_addr; 90 u8 i2c_cec_addr; 91 92 struct i2c_client *i2c_cec; 93 struct cec_adapter *cec_adap; 94 u8 cec_addr[ADV7511_MAX_ADDRS]; 95 u8 cec_valid_addrs; 96 bool cec_enabled_adap; 97 98 /* Is the adv7511 powered on? */ 99 bool power_on; 100 /* Did we receive hotplug and rx-sense signals? */ 101 bool have_monitor; 102 bool enabled_irq; 103 /* timings from s_dv_timings */ 104 struct v4l2_dv_timings dv_timings; 105 u32 fmt_code; 106 u32 colorspace; 107 u32 ycbcr_enc; 108 u32 quantization; 109 u32 xfer_func; 110 u32 content_type; 111 /* controls */ 112 struct v4l2_ctrl *hdmi_mode_ctrl; 113 struct v4l2_ctrl *hotplug_ctrl; 114 struct v4l2_ctrl *rx_sense_ctrl; 115 struct v4l2_ctrl *have_edid0_ctrl; 116 struct v4l2_ctrl *rgb_quantization_range_ctrl; 117 struct v4l2_ctrl *content_type_ctrl; 118 struct i2c_client *i2c_edid; 119 struct i2c_client *i2c_pktmem; 120 struct adv7511_state_edid edid; 121 /* Running counter of the number of detected EDIDs (for debugging) */ 122 unsigned edid_detect_counter; 123 struct workqueue_struct *work_queue; 124 struct delayed_work edid_handler; /* work entry */ 125 }; 126 127 static void adv7511_check_monitor_present_status(struct v4l2_subdev *sd); 128 static bool adv7511_check_edid_status(struct v4l2_subdev *sd); 129 static void adv7511_setup(struct v4l2_subdev *sd); 130 static int adv7511_s_i2s_clock_freq(struct v4l2_subdev *sd, u32 freq); 131 static int adv7511_s_clock_freq(struct v4l2_subdev *sd, u32 freq); 132 133 134 static const struct v4l2_dv_timings_cap adv7511_timings_cap = { 135 .type = V4L2_DV_BT_656_1120, 136 /* keep this initialization for compatibility with GCC < 4.4.6 */ 137 .reserved = { 0 }, 138 V4L2_INIT_BT_TIMINGS(640, ADV7511_MAX_WIDTH, 350, ADV7511_MAX_HEIGHT, 139 ADV7511_MIN_PIXELCLOCK, ADV7511_MAX_PIXELCLOCK, 140 V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT | 141 V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT, 142 V4L2_DV_BT_CAP_PROGRESSIVE | V4L2_DV_BT_CAP_REDUCED_BLANKING | 143 V4L2_DV_BT_CAP_CUSTOM) 144 }; 145 146 static inline struct adv7511_state *get_adv7511_state(struct v4l2_subdev *sd) 147 { 148 return container_of(sd, struct adv7511_state, sd); 149 } 150 151 static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl) 152 { 153 return &container_of(ctrl->handler, struct adv7511_state, hdl)->sd; 154 } 155 156 /* ------------------------ I2C ----------------------------------------------- */ 157 158 static s32 adv_smbus_read_byte_data_check(struct i2c_client *client, 159 u8 command, bool check) 160 { 161 union i2c_smbus_data data; 162 163 if (!i2c_smbus_xfer(client->adapter, client->addr, client->flags, 164 I2C_SMBUS_READ, command, 165 I2C_SMBUS_BYTE_DATA, &data)) 166 return data.byte; 167 if (check) 168 v4l_err(client, "error reading %02x, %02x\n", 169 client->addr, command); 170 return -1; 171 } 172 173 static s32 adv_smbus_read_byte_data(struct i2c_client *client, u8 command) 174 { 175 int i; 176 for (i = 0; i < 3; i++) { 177 int ret = adv_smbus_read_byte_data_check(client, command, true); 178 if (ret >= 0) { 179 if (i) 180 v4l_err(client, "read ok after %d retries\n", i); 181 return ret; 182 } 183 } 184 v4l_err(client, "read failed\n"); 185 return -1; 186 } 187 188 static int adv7511_rd(struct v4l2_subdev *sd, u8 reg) 189 { 190 struct i2c_client *client = v4l2_get_subdevdata(sd); 191 192 return adv_smbus_read_byte_data(client, reg); 193 } 194 195 static int adv7511_wr(struct v4l2_subdev *sd, u8 reg, u8 val) 196 { 197 struct i2c_client *client = v4l2_get_subdevdata(sd); 198 int ret; 199 int i; 200 201 for (i = 0; i < 3; i++) { 202 ret = i2c_smbus_write_byte_data(client, reg, val); 203 if (ret == 0) 204 return 0; 205 } 206 v4l2_err(sd, "%s: i2c write error\n", __func__); 207 return ret; 208 } 209 210 /* To set specific bits in the register, a clear-mask is given (to be AND-ed), 211 and then the value-mask (to be OR-ed). */ 212 static inline void adv7511_wr_and_or(struct v4l2_subdev *sd, u8 reg, u8 clr_mask, u8 val_mask) 213 { 214 adv7511_wr(sd, reg, (adv7511_rd(sd, reg) & clr_mask) | val_mask); 215 } 216 217 static int adv_smbus_read_i2c_block_data(struct i2c_client *client, 218 u8 command, unsigned length, u8 *values) 219 { 220 union i2c_smbus_data data; 221 int ret; 222 223 if (length > I2C_SMBUS_BLOCK_MAX) 224 length = I2C_SMBUS_BLOCK_MAX; 225 data.block[0] = length; 226 227 ret = i2c_smbus_xfer(client->adapter, client->addr, client->flags, 228 I2C_SMBUS_READ, command, 229 I2C_SMBUS_I2C_BLOCK_DATA, &data); 230 memcpy(values, data.block + 1, length); 231 return ret; 232 } 233 234 static void adv7511_edid_rd(struct v4l2_subdev *sd, uint16_t len, uint8_t *buf) 235 { 236 struct adv7511_state *state = get_adv7511_state(sd); 237 int i; 238 int err = 0; 239 240 v4l2_dbg(1, debug, sd, "%s:\n", __func__); 241 242 for (i = 0; !err && i < len; i += I2C_SMBUS_BLOCK_MAX) 243 err = adv_smbus_read_i2c_block_data(state->i2c_edid, i, 244 I2C_SMBUS_BLOCK_MAX, buf + i); 245 if (err) 246 v4l2_err(sd, "%s: i2c read error\n", __func__); 247 } 248 249 static inline int adv7511_cec_read(struct v4l2_subdev *sd, u8 reg) 250 { 251 struct adv7511_state *state = get_adv7511_state(sd); 252 253 return i2c_smbus_read_byte_data(state->i2c_cec, reg); 254 } 255 256 static int adv7511_cec_write(struct v4l2_subdev *sd, u8 reg, u8 val) 257 { 258 struct adv7511_state *state = get_adv7511_state(sd); 259 int ret; 260 int i; 261 262 for (i = 0; i < 3; i++) { 263 ret = i2c_smbus_write_byte_data(state->i2c_cec, reg, val); 264 if (ret == 0) 265 return 0; 266 } 267 v4l2_err(sd, "%s: I2C Write Problem\n", __func__); 268 return ret; 269 } 270 271 static inline int adv7511_cec_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, 272 u8 val) 273 { 274 return adv7511_cec_write(sd, reg, (adv7511_cec_read(sd, reg) & mask) | val); 275 } 276 277 static int adv7511_pktmem_rd(struct v4l2_subdev *sd, u8 reg) 278 { 279 struct adv7511_state *state = get_adv7511_state(sd); 280 281 return adv_smbus_read_byte_data(state->i2c_pktmem, reg); 282 } 283 284 static int adv7511_pktmem_wr(struct v4l2_subdev *sd, u8 reg, u8 val) 285 { 286 struct adv7511_state *state = get_adv7511_state(sd); 287 int ret; 288 int i; 289 290 for (i = 0; i < 3; i++) { 291 ret = i2c_smbus_write_byte_data(state->i2c_pktmem, reg, val); 292 if (ret == 0) 293 return 0; 294 } 295 v4l2_err(sd, "%s: i2c write error\n", __func__); 296 return ret; 297 } 298 299 /* To set specific bits in the register, a clear-mask is given (to be AND-ed), 300 and then the value-mask (to be OR-ed). */ 301 static inline void adv7511_pktmem_wr_and_or(struct v4l2_subdev *sd, u8 reg, u8 clr_mask, u8 val_mask) 302 { 303 adv7511_pktmem_wr(sd, reg, (adv7511_pktmem_rd(sd, reg) & clr_mask) | val_mask); 304 } 305 306 static inline bool adv7511_have_hotplug(struct v4l2_subdev *sd) 307 { 308 return adv7511_rd(sd, 0x42) & MASK_ADV7511_HPD_DETECT; 309 } 310 311 static inline bool adv7511_have_rx_sense(struct v4l2_subdev *sd) 312 { 313 return adv7511_rd(sd, 0x42) & MASK_ADV7511_MSEN_DETECT; 314 } 315 316 static void adv7511_csc_conversion_mode(struct v4l2_subdev *sd, u8 mode) 317 { 318 adv7511_wr_and_or(sd, 0x18, 0x9f, (mode & 0x3)<<5); 319 } 320 321 static void adv7511_csc_coeff(struct v4l2_subdev *sd, 322 u16 A1, u16 A2, u16 A3, u16 A4, 323 u16 B1, u16 B2, u16 B3, u16 B4, 324 u16 C1, u16 C2, u16 C3, u16 C4) 325 { 326 /* A */ 327 adv7511_wr_and_or(sd, 0x18, 0xe0, A1>>8); 328 adv7511_wr(sd, 0x19, A1); 329 adv7511_wr_and_or(sd, 0x1A, 0xe0, A2>>8); 330 adv7511_wr(sd, 0x1B, A2); 331 adv7511_wr_and_or(sd, 0x1c, 0xe0, A3>>8); 332 adv7511_wr(sd, 0x1d, A3); 333 adv7511_wr_and_or(sd, 0x1e, 0xe0, A4>>8); 334 adv7511_wr(sd, 0x1f, A4); 335 336 /* B */ 337 adv7511_wr_and_or(sd, 0x20, 0xe0, B1>>8); 338 adv7511_wr(sd, 0x21, B1); 339 adv7511_wr_and_or(sd, 0x22, 0xe0, B2>>8); 340 adv7511_wr(sd, 0x23, B2); 341 adv7511_wr_and_or(sd, 0x24, 0xe0, B3>>8); 342 adv7511_wr(sd, 0x25, B3); 343 adv7511_wr_and_or(sd, 0x26, 0xe0, B4>>8); 344 adv7511_wr(sd, 0x27, B4); 345 346 /* C */ 347 adv7511_wr_and_or(sd, 0x28, 0xe0, C1>>8); 348 adv7511_wr(sd, 0x29, C1); 349 adv7511_wr_and_or(sd, 0x2A, 0xe0, C2>>8); 350 adv7511_wr(sd, 0x2B, C2); 351 adv7511_wr_and_or(sd, 0x2C, 0xe0, C3>>8); 352 adv7511_wr(sd, 0x2D, C3); 353 adv7511_wr_and_or(sd, 0x2E, 0xe0, C4>>8); 354 adv7511_wr(sd, 0x2F, C4); 355 } 356 357 static void adv7511_csc_rgb_full2limit(struct v4l2_subdev *sd, bool enable) 358 { 359 if (enable) { 360 u8 csc_mode = 0; 361 adv7511_csc_conversion_mode(sd, csc_mode); 362 adv7511_csc_coeff(sd, 363 4096-564, 0, 0, 256, 364 0, 4096-564, 0, 256, 365 0, 0, 4096-564, 256); 366 /* enable CSC */ 367 adv7511_wr_and_or(sd, 0x18, 0x7f, 0x80); 368 /* AVI infoframe: Limited range RGB (16-235) */ 369 adv7511_wr_and_or(sd, 0x57, 0xf3, 0x04); 370 } else { 371 /* disable CSC */ 372 adv7511_wr_and_or(sd, 0x18, 0x7f, 0x0); 373 /* AVI infoframe: Full range RGB (0-255) */ 374 adv7511_wr_and_or(sd, 0x57, 0xf3, 0x08); 375 } 376 } 377 378 static void adv7511_set_rgb_quantization_mode(struct v4l2_subdev *sd, struct v4l2_ctrl *ctrl) 379 { 380 struct adv7511_state *state = get_adv7511_state(sd); 381 382 /* Only makes sense for RGB formats */ 383 if (state->fmt_code != MEDIA_BUS_FMT_RGB888_1X24) { 384 /* so just keep quantization */ 385 adv7511_csc_rgb_full2limit(sd, false); 386 return; 387 } 388 389 switch (ctrl->val) { 390 case V4L2_DV_RGB_RANGE_AUTO: 391 /* automatic */ 392 if (state->dv_timings.bt.flags & V4L2_DV_FL_IS_CE_VIDEO) { 393 /* CE format, RGB limited range (16-235) */ 394 adv7511_csc_rgb_full2limit(sd, true); 395 } else { 396 /* not CE format, RGB full range (0-255) */ 397 adv7511_csc_rgb_full2limit(sd, false); 398 } 399 break; 400 case V4L2_DV_RGB_RANGE_LIMITED: 401 /* RGB limited range (16-235) */ 402 adv7511_csc_rgb_full2limit(sd, true); 403 break; 404 case V4L2_DV_RGB_RANGE_FULL: 405 /* RGB full range (0-255) */ 406 adv7511_csc_rgb_full2limit(sd, false); 407 break; 408 } 409 } 410 411 /* ------------------------------ CTRL OPS ------------------------------ */ 412 413 static int adv7511_s_ctrl(struct v4l2_ctrl *ctrl) 414 { 415 struct v4l2_subdev *sd = to_sd(ctrl); 416 struct adv7511_state *state = get_adv7511_state(sd); 417 418 v4l2_dbg(1, debug, sd, "%s: ctrl id: %d, ctrl->val %d\n", __func__, ctrl->id, ctrl->val); 419 420 if (state->hdmi_mode_ctrl == ctrl) { 421 /* Set HDMI or DVI-D */ 422 adv7511_wr_and_or(sd, 0xaf, 0xfd, ctrl->val == V4L2_DV_TX_MODE_HDMI ? 0x02 : 0x00); 423 return 0; 424 } 425 if (state->rgb_quantization_range_ctrl == ctrl) { 426 adv7511_set_rgb_quantization_mode(sd, ctrl); 427 return 0; 428 } 429 if (state->content_type_ctrl == ctrl) { 430 u8 itc, cn; 431 432 state->content_type = ctrl->val; 433 itc = state->content_type != V4L2_DV_IT_CONTENT_TYPE_NO_ITC; 434 cn = itc ? state->content_type : V4L2_DV_IT_CONTENT_TYPE_GRAPHICS; 435 adv7511_wr_and_or(sd, 0x57, 0x7f, itc << 7); 436 adv7511_wr_and_or(sd, 0x59, 0xcf, cn << 4); 437 return 0; 438 } 439 440 return -EINVAL; 441 } 442 443 static const struct v4l2_ctrl_ops adv7511_ctrl_ops = { 444 .s_ctrl = adv7511_s_ctrl, 445 }; 446 447 /* ---------------------------- CORE OPS ------------------------------------------- */ 448 449 #ifdef CONFIG_VIDEO_ADV_DEBUG 450 static void adv7511_inv_register(struct v4l2_subdev *sd) 451 { 452 struct adv7511_state *state = get_adv7511_state(sd); 453 454 v4l2_info(sd, "0x000-0x0ff: Main Map\n"); 455 if (state->i2c_cec) 456 v4l2_info(sd, "0x100-0x1ff: CEC Map\n"); 457 } 458 459 static int adv7511_g_register(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg) 460 { 461 struct adv7511_state *state = get_adv7511_state(sd); 462 463 reg->size = 1; 464 switch (reg->reg >> 8) { 465 case 0: 466 reg->val = adv7511_rd(sd, reg->reg & 0xff); 467 break; 468 case 1: 469 if (state->i2c_cec) { 470 reg->val = adv7511_cec_read(sd, reg->reg & 0xff); 471 break; 472 } 473 /* fall through */ 474 default: 475 v4l2_info(sd, "Register %03llx not supported\n", reg->reg); 476 adv7511_inv_register(sd); 477 break; 478 } 479 return 0; 480 } 481 482 static int adv7511_s_register(struct v4l2_subdev *sd, const struct v4l2_dbg_register *reg) 483 { 484 struct adv7511_state *state = get_adv7511_state(sd); 485 486 switch (reg->reg >> 8) { 487 case 0: 488 adv7511_wr(sd, reg->reg & 0xff, reg->val & 0xff); 489 break; 490 case 1: 491 if (state->i2c_cec) { 492 adv7511_cec_write(sd, reg->reg & 0xff, reg->val & 0xff); 493 break; 494 } 495 /* fall through */ 496 default: 497 v4l2_info(sd, "Register %03llx not supported\n", reg->reg); 498 adv7511_inv_register(sd); 499 break; 500 } 501 return 0; 502 } 503 #endif 504 505 struct adv7511_cfg_read_infoframe { 506 const char *desc; 507 u8 present_reg; 508 u8 present_mask; 509 u8 header[3]; 510 u16 payload_addr; 511 }; 512 513 static u8 hdmi_infoframe_checksum(u8 *ptr, size_t size) 514 { 515 u8 csum = 0; 516 size_t i; 517 518 /* compute checksum */ 519 for (i = 0; i < size; i++) 520 csum += ptr[i]; 521 522 return 256 - csum; 523 } 524 525 static void log_infoframe(struct v4l2_subdev *sd, const struct adv7511_cfg_read_infoframe *cri) 526 { 527 struct i2c_client *client = v4l2_get_subdevdata(sd); 528 struct device *dev = &client->dev; 529 union hdmi_infoframe frame; 530 u8 buffer[32]; 531 u8 len; 532 int i; 533 534 if (!(adv7511_rd(sd, cri->present_reg) & cri->present_mask)) { 535 v4l2_info(sd, "%s infoframe not transmitted\n", cri->desc); 536 return; 537 } 538 539 memcpy(buffer, cri->header, sizeof(cri->header)); 540 541 len = buffer[2]; 542 543 if (len + 4 > sizeof(buffer)) { 544 v4l2_err(sd, "%s: invalid %s infoframe length %d\n", __func__, cri->desc, len); 545 return; 546 } 547 548 if (cri->payload_addr >= 0x100) { 549 for (i = 0; i < len; i++) 550 buffer[i + 4] = adv7511_pktmem_rd(sd, cri->payload_addr + i - 0x100); 551 } else { 552 for (i = 0; i < len; i++) 553 buffer[i + 4] = adv7511_rd(sd, cri->payload_addr + i); 554 } 555 buffer[3] = 0; 556 buffer[3] = hdmi_infoframe_checksum(buffer, len + 4); 557 558 if (hdmi_infoframe_unpack(&frame, buffer, sizeof(buffer)) < 0) { 559 v4l2_err(sd, "%s: unpack of %s infoframe failed\n", __func__, cri->desc); 560 return; 561 } 562 563 hdmi_infoframe_log(KERN_INFO, dev, &frame); 564 } 565 566 static void adv7511_log_infoframes(struct v4l2_subdev *sd) 567 { 568 static const struct adv7511_cfg_read_infoframe cri[] = { 569 { "AVI", 0x44, 0x10, { 0x82, 2, 13 }, 0x55 }, 570 { "Audio", 0x44, 0x08, { 0x84, 1, 10 }, 0x73 }, 571 { "SDP", 0x40, 0x40, { 0x83, 1, 25 }, 0x103 }, 572 }; 573 int i; 574 575 for (i = 0; i < ARRAY_SIZE(cri); i++) 576 log_infoframe(sd, &cri[i]); 577 } 578 579 static int adv7511_log_status(struct v4l2_subdev *sd) 580 { 581 struct adv7511_state *state = get_adv7511_state(sd); 582 struct adv7511_state_edid *edid = &state->edid; 583 int i; 584 585 static const char * const states[] = { 586 "in reset", 587 "reading EDID", 588 "idle", 589 "initializing HDCP", 590 "HDCP enabled", 591 "initializing HDCP repeater", 592 "6", "7", "8", "9", "A", "B", "C", "D", "E", "F" 593 }; 594 static const char * const errors[] = { 595 "no error", 596 "bad receiver BKSV", 597 "Ri mismatch", 598 "Pj mismatch", 599 "i2c error", 600 "timed out", 601 "max repeater cascade exceeded", 602 "hash check failed", 603 "too many devices", 604 "9", "A", "B", "C", "D", "E", "F" 605 }; 606 607 v4l2_info(sd, "power %s\n", state->power_on ? "on" : "off"); 608 v4l2_info(sd, "%s hotplug, %s Rx Sense, %s EDID (%d block(s))\n", 609 (adv7511_rd(sd, 0x42) & MASK_ADV7511_HPD_DETECT) ? "detected" : "no", 610 (adv7511_rd(sd, 0x42) & MASK_ADV7511_MSEN_DETECT) ? "detected" : "no", 611 edid->segments ? "found" : "no", 612 edid->blocks); 613 v4l2_info(sd, "%s output %s\n", 614 (adv7511_rd(sd, 0xaf) & 0x02) ? 615 "HDMI" : "DVI-D", 616 (adv7511_rd(sd, 0xa1) & 0x3c) ? 617 "disabled" : "enabled"); 618 v4l2_info(sd, "state: %s, error: %s, detect count: %u, msk/irq: %02x/%02x\n", 619 states[adv7511_rd(sd, 0xc8) & 0xf], 620 errors[adv7511_rd(sd, 0xc8) >> 4], state->edid_detect_counter, 621 adv7511_rd(sd, 0x94), adv7511_rd(sd, 0x96)); 622 v4l2_info(sd, "RGB quantization: %s range\n", adv7511_rd(sd, 0x18) & 0x80 ? "limited" : "full"); 623 if (adv7511_rd(sd, 0xaf) & 0x02) { 624 /* HDMI only */ 625 u8 manual_cts = adv7511_rd(sd, 0x0a) & 0x80; 626 u32 N = (adv7511_rd(sd, 0x01) & 0xf) << 16 | 627 adv7511_rd(sd, 0x02) << 8 | 628 adv7511_rd(sd, 0x03); 629 u8 vic_detect = adv7511_rd(sd, 0x3e) >> 2; 630 u8 vic_sent = adv7511_rd(sd, 0x3d) & 0x3f; 631 u32 CTS; 632 633 if (manual_cts) 634 CTS = (adv7511_rd(sd, 0x07) & 0xf) << 16 | 635 adv7511_rd(sd, 0x08) << 8 | 636 adv7511_rd(sd, 0x09); 637 else 638 CTS = (adv7511_rd(sd, 0x04) & 0xf) << 16 | 639 adv7511_rd(sd, 0x05) << 8 | 640 adv7511_rd(sd, 0x06); 641 v4l2_info(sd, "CTS %s mode: N %d, CTS %d\n", 642 manual_cts ? "manual" : "automatic", N, CTS); 643 v4l2_info(sd, "VIC: detected %d, sent %d\n", 644 vic_detect, vic_sent); 645 adv7511_log_infoframes(sd); 646 } 647 if (state->dv_timings.type == V4L2_DV_BT_656_1120) 648 v4l2_print_dv_timings(sd->name, "timings: ", 649 &state->dv_timings, false); 650 else 651 v4l2_info(sd, "no timings set\n"); 652 v4l2_info(sd, "i2c edid addr: 0x%x\n", state->i2c_edid_addr); 653 654 if (state->i2c_cec == NULL) 655 return 0; 656 657 v4l2_info(sd, "i2c cec addr: 0x%x\n", state->i2c_cec_addr); 658 659 v4l2_info(sd, "CEC: %s\n", state->cec_enabled_adap ? 660 "enabled" : "disabled"); 661 if (state->cec_enabled_adap) { 662 for (i = 0; i < ADV7511_MAX_ADDRS; i++) { 663 bool is_valid = state->cec_valid_addrs & (1 << i); 664 665 if (is_valid) 666 v4l2_info(sd, "CEC Logical Address: 0x%x\n", 667 state->cec_addr[i]); 668 } 669 } 670 v4l2_info(sd, "i2c pktmem addr: 0x%x\n", state->i2c_pktmem_addr); 671 return 0; 672 } 673 674 /* Power up/down adv7511 */ 675 static int adv7511_s_power(struct v4l2_subdev *sd, int on) 676 { 677 struct adv7511_state *state = get_adv7511_state(sd); 678 const int retries = 20; 679 int i; 680 681 v4l2_dbg(1, debug, sd, "%s: power %s\n", __func__, on ? "on" : "off"); 682 683 state->power_on = on; 684 685 if (!on) { 686 /* Power down */ 687 adv7511_wr_and_or(sd, 0x41, 0xbf, 0x40); 688 return true; 689 } 690 691 /* Power up */ 692 /* The adv7511 does not always come up immediately. 693 Retry multiple times. */ 694 for (i = 0; i < retries; i++) { 695 adv7511_wr_and_or(sd, 0x41, 0xbf, 0x0); 696 if ((adv7511_rd(sd, 0x41) & 0x40) == 0) 697 break; 698 adv7511_wr_and_or(sd, 0x41, 0xbf, 0x40); 699 msleep(10); 700 } 701 if (i == retries) { 702 v4l2_dbg(1, debug, sd, "%s: failed to powerup the adv7511!\n", __func__); 703 adv7511_s_power(sd, 0); 704 return false; 705 } 706 if (i > 1) 707 v4l2_dbg(1, debug, sd, "%s: needed %d retries to powerup the adv7511\n", __func__, i); 708 709 /* Reserved registers that must be set */ 710 adv7511_wr(sd, 0x98, 0x03); 711 adv7511_wr_and_or(sd, 0x9a, 0xfe, 0x70); 712 adv7511_wr(sd, 0x9c, 0x30); 713 adv7511_wr_and_or(sd, 0x9d, 0xfc, 0x01); 714 adv7511_wr(sd, 0xa2, 0xa4); 715 adv7511_wr(sd, 0xa3, 0xa4); 716 adv7511_wr(sd, 0xe0, 0xd0); 717 adv7511_wr(sd, 0xf9, 0x00); 718 719 adv7511_wr(sd, 0x43, state->i2c_edid_addr); 720 adv7511_wr(sd, 0x45, state->i2c_pktmem_addr); 721 722 /* Set number of attempts to read the EDID */ 723 adv7511_wr(sd, 0xc9, 0xf); 724 return true; 725 } 726 727 #if IS_ENABLED(CONFIG_VIDEO_ADV7511_CEC) 728 static int adv7511_cec_adap_enable(struct cec_adapter *adap, bool enable) 729 { 730 struct adv7511_state *state = cec_get_drvdata(adap); 731 struct v4l2_subdev *sd = &state->sd; 732 733 if (state->i2c_cec == NULL) 734 return -EIO; 735 736 if (!state->cec_enabled_adap && enable) { 737 /* power up cec section */ 738 adv7511_cec_write_and_or(sd, 0x4e, 0xfc, 0x01); 739 /* legacy mode and clear all rx buffers */ 740 adv7511_cec_write(sd, 0x4a, 0x00); 741 adv7511_cec_write(sd, 0x4a, 0x07); 742 adv7511_cec_write_and_or(sd, 0x11, 0xfe, 0); /* initially disable tx */ 743 /* enabled irqs: */ 744 /* tx: ready */ 745 /* tx: arbitration lost */ 746 /* tx: retry timeout */ 747 /* rx: ready 1 */ 748 if (state->enabled_irq) 749 adv7511_wr_and_or(sd, 0x95, 0xc0, 0x39); 750 } else if (state->cec_enabled_adap && !enable) { 751 if (state->enabled_irq) 752 adv7511_wr_and_or(sd, 0x95, 0xc0, 0x00); 753 /* disable address mask 1-3 */ 754 adv7511_cec_write_and_or(sd, 0x4b, 0x8f, 0x00); 755 /* power down cec section */ 756 adv7511_cec_write_and_or(sd, 0x4e, 0xfc, 0x00); 757 state->cec_valid_addrs = 0; 758 } 759 state->cec_enabled_adap = enable; 760 return 0; 761 } 762 763 static int adv7511_cec_adap_log_addr(struct cec_adapter *adap, u8 addr) 764 { 765 struct adv7511_state *state = cec_get_drvdata(adap); 766 struct v4l2_subdev *sd = &state->sd; 767 unsigned int i, free_idx = ADV7511_MAX_ADDRS; 768 769 if (!state->cec_enabled_adap) 770 return addr == CEC_LOG_ADDR_INVALID ? 0 : -EIO; 771 772 if (addr == CEC_LOG_ADDR_INVALID) { 773 adv7511_cec_write_and_or(sd, 0x4b, 0x8f, 0); 774 state->cec_valid_addrs = 0; 775 return 0; 776 } 777 778 for (i = 0; i < ADV7511_MAX_ADDRS; i++) { 779 bool is_valid = state->cec_valid_addrs & (1 << i); 780 781 if (free_idx == ADV7511_MAX_ADDRS && !is_valid) 782 free_idx = i; 783 if (is_valid && state->cec_addr[i] == addr) 784 return 0; 785 } 786 if (i == ADV7511_MAX_ADDRS) { 787 i = free_idx; 788 if (i == ADV7511_MAX_ADDRS) 789 return -ENXIO; 790 } 791 state->cec_addr[i] = addr; 792 state->cec_valid_addrs |= 1 << i; 793 794 switch (i) { 795 case 0: 796 /* enable address mask 0 */ 797 adv7511_cec_write_and_or(sd, 0x4b, 0xef, 0x10); 798 /* set address for mask 0 */ 799 adv7511_cec_write_and_or(sd, 0x4c, 0xf0, addr); 800 break; 801 case 1: 802 /* enable address mask 1 */ 803 adv7511_cec_write_and_or(sd, 0x4b, 0xdf, 0x20); 804 /* set address for mask 1 */ 805 adv7511_cec_write_and_or(sd, 0x4c, 0x0f, addr << 4); 806 break; 807 case 2: 808 /* enable address mask 2 */ 809 adv7511_cec_write_and_or(sd, 0x4b, 0xbf, 0x40); 810 /* set address for mask 1 */ 811 adv7511_cec_write_and_or(sd, 0x4d, 0xf0, addr); 812 break; 813 } 814 return 0; 815 } 816 817 static int adv7511_cec_adap_transmit(struct cec_adapter *adap, u8 attempts, 818 u32 signal_free_time, struct cec_msg *msg) 819 { 820 struct adv7511_state *state = cec_get_drvdata(adap); 821 struct v4l2_subdev *sd = &state->sd; 822 u8 len = msg->len; 823 unsigned int i; 824 825 v4l2_dbg(1, debug, sd, "%s: len %d\n", __func__, len); 826 827 if (len > 16) { 828 v4l2_err(sd, "%s: len exceeded 16 (%d)\n", __func__, len); 829 return -EINVAL; 830 } 831 832 /* 833 * The number of retries is the number of attempts - 1, but retry 834 * at least once. It's not clear if a value of 0 is allowed, so 835 * let's do at least one retry. 836 */ 837 adv7511_cec_write_and_or(sd, 0x12, ~0x70, max(1, attempts - 1) << 4); 838 839 /* clear cec tx irq status */ 840 adv7511_wr(sd, 0x97, 0x38); 841 842 /* write data */ 843 for (i = 0; i < len; i++) 844 adv7511_cec_write(sd, i, msg->msg[i]); 845 846 /* set length (data + header) */ 847 adv7511_cec_write(sd, 0x10, len); 848 /* start transmit, enable tx */ 849 adv7511_cec_write(sd, 0x11, 0x01); 850 return 0; 851 } 852 853 static void adv_cec_tx_raw_status(struct v4l2_subdev *sd, u8 tx_raw_status) 854 { 855 struct adv7511_state *state = get_adv7511_state(sd); 856 857 if ((adv7511_cec_read(sd, 0x11) & 0x01) == 0) { 858 v4l2_dbg(1, debug, sd, "%s: tx raw: tx disabled\n", __func__); 859 return; 860 } 861 862 if (tx_raw_status & 0x10) { 863 v4l2_dbg(1, debug, sd, 864 "%s: tx raw: arbitration lost\n", __func__); 865 cec_transmit_done(state->cec_adap, CEC_TX_STATUS_ARB_LOST, 866 1, 0, 0, 0); 867 return; 868 } 869 if (tx_raw_status & 0x08) { 870 u8 status; 871 u8 nack_cnt; 872 u8 low_drive_cnt; 873 874 v4l2_dbg(1, debug, sd, "%s: tx raw: retry failed\n", __func__); 875 /* 876 * We set this status bit since this hardware performs 877 * retransmissions. 878 */ 879 status = CEC_TX_STATUS_MAX_RETRIES; 880 nack_cnt = adv7511_cec_read(sd, 0x14) & 0xf; 881 if (nack_cnt) 882 status |= CEC_TX_STATUS_NACK; 883 low_drive_cnt = adv7511_cec_read(sd, 0x14) >> 4; 884 if (low_drive_cnt) 885 status |= CEC_TX_STATUS_LOW_DRIVE; 886 cec_transmit_done(state->cec_adap, status, 887 0, nack_cnt, low_drive_cnt, 0); 888 return; 889 } 890 if (tx_raw_status & 0x20) { 891 v4l2_dbg(1, debug, sd, "%s: tx raw: ready ok\n", __func__); 892 cec_transmit_done(state->cec_adap, CEC_TX_STATUS_OK, 0, 0, 0, 0); 893 return; 894 } 895 } 896 897 static const struct cec_adap_ops adv7511_cec_adap_ops = { 898 .adap_enable = adv7511_cec_adap_enable, 899 .adap_log_addr = adv7511_cec_adap_log_addr, 900 .adap_transmit = adv7511_cec_adap_transmit, 901 }; 902 #endif 903 904 /* Enable interrupts */ 905 static void adv7511_set_isr(struct v4l2_subdev *sd, bool enable) 906 { 907 struct adv7511_state *state = get_adv7511_state(sd); 908 u8 irqs = MASK_ADV7511_HPD_INT | MASK_ADV7511_MSEN_INT; 909 u8 irqs_rd; 910 int retries = 100; 911 912 v4l2_dbg(2, debug, sd, "%s: %s\n", __func__, enable ? "enable" : "disable"); 913 914 if (state->enabled_irq == enable) 915 return; 916 state->enabled_irq = enable; 917 918 /* The datasheet says that the EDID ready interrupt should be 919 disabled if there is no hotplug. */ 920 if (!enable) 921 irqs = 0; 922 else if (adv7511_have_hotplug(sd)) 923 irqs |= MASK_ADV7511_EDID_RDY_INT; 924 925 /* 926 * This i2c write can fail (approx. 1 in 1000 writes). But it 927 * is essential that this register is correct, so retry it 928 * multiple times. 929 * 930 * Note that the i2c write does not report an error, but the readback 931 * clearly shows the wrong value. 932 */ 933 do { 934 adv7511_wr(sd, 0x94, irqs); 935 irqs_rd = adv7511_rd(sd, 0x94); 936 } while (retries-- && irqs_rd != irqs); 937 938 if (irqs_rd != irqs) 939 v4l2_err(sd, "Could not set interrupts: hw failure?\n"); 940 941 adv7511_wr_and_or(sd, 0x95, 0xc0, 942 (state->cec_enabled_adap && enable) ? 0x39 : 0x00); 943 } 944 945 /* Interrupt handler */ 946 static int adv7511_isr(struct v4l2_subdev *sd, u32 status, bool *handled) 947 { 948 u8 irq_status; 949 u8 cec_irq; 950 951 /* disable interrupts to prevent a race condition */ 952 adv7511_set_isr(sd, false); 953 irq_status = adv7511_rd(sd, 0x96); 954 cec_irq = adv7511_rd(sd, 0x97); 955 /* clear detected interrupts */ 956 adv7511_wr(sd, 0x96, irq_status); 957 adv7511_wr(sd, 0x97, cec_irq); 958 959 v4l2_dbg(1, debug, sd, "%s: irq 0x%x, cec-irq 0x%x\n", __func__, 960 irq_status, cec_irq); 961 962 if (irq_status & (MASK_ADV7511_HPD_INT | MASK_ADV7511_MSEN_INT)) 963 adv7511_check_monitor_present_status(sd); 964 if (irq_status & MASK_ADV7511_EDID_RDY_INT) 965 adv7511_check_edid_status(sd); 966 967 #if IS_ENABLED(CONFIG_VIDEO_ADV7511_CEC) 968 if (cec_irq & 0x38) 969 adv_cec_tx_raw_status(sd, cec_irq); 970 971 if (cec_irq & 1) { 972 struct adv7511_state *state = get_adv7511_state(sd); 973 struct cec_msg msg; 974 975 msg.len = adv7511_cec_read(sd, 0x25) & 0x1f; 976 977 v4l2_dbg(1, debug, sd, "%s: cec msg len %d\n", __func__, 978 msg.len); 979 980 if (msg.len > 16) 981 msg.len = 16; 982 983 if (msg.len) { 984 u8 i; 985 986 for (i = 0; i < msg.len; i++) 987 msg.msg[i] = adv7511_cec_read(sd, i + 0x15); 988 989 adv7511_cec_write(sd, 0x4a, 0); /* toggle to re-enable rx 1 */ 990 adv7511_cec_write(sd, 0x4a, 1); 991 cec_received_msg(state->cec_adap, &msg); 992 } 993 } 994 #endif 995 996 /* enable interrupts */ 997 adv7511_set_isr(sd, true); 998 999 if (handled) 1000 *handled = true; 1001 return 0; 1002 } 1003 1004 static const struct v4l2_subdev_core_ops adv7511_core_ops = { 1005 .log_status = adv7511_log_status, 1006 #ifdef CONFIG_VIDEO_ADV_DEBUG 1007 .g_register = adv7511_g_register, 1008 .s_register = adv7511_s_register, 1009 #endif 1010 .s_power = adv7511_s_power, 1011 .interrupt_service_routine = adv7511_isr, 1012 }; 1013 1014 /* ------------------------------ VIDEO OPS ------------------------------ */ 1015 1016 /* Enable/disable adv7511 output */ 1017 static int adv7511_s_stream(struct v4l2_subdev *sd, int enable) 1018 { 1019 struct adv7511_state *state = get_adv7511_state(sd); 1020 1021 v4l2_dbg(1, debug, sd, "%s: %sable\n", __func__, (enable ? "en" : "dis")); 1022 adv7511_wr_and_or(sd, 0xa1, ~0x3c, (enable ? 0 : 0x3c)); 1023 if (enable) { 1024 adv7511_check_monitor_present_status(sd); 1025 } else { 1026 adv7511_s_power(sd, 0); 1027 state->have_monitor = false; 1028 } 1029 return 0; 1030 } 1031 1032 static int adv7511_s_dv_timings(struct v4l2_subdev *sd, 1033 struct v4l2_dv_timings *timings) 1034 { 1035 struct adv7511_state *state = get_adv7511_state(sd); 1036 struct v4l2_bt_timings *bt = &timings->bt; 1037 u32 fps; 1038 1039 v4l2_dbg(1, debug, sd, "%s:\n", __func__); 1040 1041 /* quick sanity check */ 1042 if (!v4l2_valid_dv_timings(timings, &adv7511_timings_cap, NULL, NULL)) 1043 return -EINVAL; 1044 1045 /* Fill the optional fields .standards and .flags in struct v4l2_dv_timings 1046 if the format is one of the CEA or DMT timings. */ 1047 v4l2_find_dv_timings_cap(timings, &adv7511_timings_cap, 0, NULL, NULL); 1048 1049 /* save timings */ 1050 state->dv_timings = *timings; 1051 1052 /* set h/vsync polarities */ 1053 adv7511_wr_and_or(sd, 0x17, 0x9f, 1054 ((bt->polarities & V4L2_DV_VSYNC_POS_POL) ? 0 : 0x40) | 1055 ((bt->polarities & V4L2_DV_HSYNC_POS_POL) ? 0 : 0x20)); 1056 1057 fps = (u32)bt->pixelclock / (V4L2_DV_BT_FRAME_WIDTH(bt) * V4L2_DV_BT_FRAME_HEIGHT(bt)); 1058 switch (fps) { 1059 case 24: 1060 adv7511_wr_and_or(sd, 0xfb, 0xf9, 1 << 1); 1061 break; 1062 case 25: 1063 adv7511_wr_and_or(sd, 0xfb, 0xf9, 2 << 1); 1064 break; 1065 case 30: 1066 adv7511_wr_and_or(sd, 0xfb, 0xf9, 3 << 1); 1067 break; 1068 default: 1069 adv7511_wr_and_or(sd, 0xfb, 0xf9, 0); 1070 break; 1071 } 1072 1073 /* update quantization range based on new dv_timings */ 1074 adv7511_set_rgb_quantization_mode(sd, state->rgb_quantization_range_ctrl); 1075 1076 return 0; 1077 } 1078 1079 static int adv7511_g_dv_timings(struct v4l2_subdev *sd, 1080 struct v4l2_dv_timings *timings) 1081 { 1082 struct adv7511_state *state = get_adv7511_state(sd); 1083 1084 v4l2_dbg(1, debug, sd, "%s:\n", __func__); 1085 1086 if (!timings) 1087 return -EINVAL; 1088 1089 *timings = state->dv_timings; 1090 1091 return 0; 1092 } 1093 1094 static int adv7511_enum_dv_timings(struct v4l2_subdev *sd, 1095 struct v4l2_enum_dv_timings *timings) 1096 { 1097 if (timings->pad != 0) 1098 return -EINVAL; 1099 1100 return v4l2_enum_dv_timings_cap(timings, &adv7511_timings_cap, NULL, NULL); 1101 } 1102 1103 static int adv7511_dv_timings_cap(struct v4l2_subdev *sd, 1104 struct v4l2_dv_timings_cap *cap) 1105 { 1106 if (cap->pad != 0) 1107 return -EINVAL; 1108 1109 *cap = adv7511_timings_cap; 1110 return 0; 1111 } 1112 1113 static const struct v4l2_subdev_video_ops adv7511_video_ops = { 1114 .s_stream = adv7511_s_stream, 1115 .s_dv_timings = adv7511_s_dv_timings, 1116 .g_dv_timings = adv7511_g_dv_timings, 1117 }; 1118 1119 /* ------------------------------ AUDIO OPS ------------------------------ */ 1120 static int adv7511_s_audio_stream(struct v4l2_subdev *sd, int enable) 1121 { 1122 v4l2_dbg(1, debug, sd, "%s: %sable\n", __func__, (enable ? "en" : "dis")); 1123 1124 if (enable) 1125 adv7511_wr_and_or(sd, 0x4b, 0x3f, 0x80); 1126 else 1127 adv7511_wr_and_or(sd, 0x4b, 0x3f, 0x40); 1128 1129 return 0; 1130 } 1131 1132 static int adv7511_s_clock_freq(struct v4l2_subdev *sd, u32 freq) 1133 { 1134 u32 N; 1135 1136 switch (freq) { 1137 case 32000: N = 4096; break; 1138 case 44100: N = 6272; break; 1139 case 48000: N = 6144; break; 1140 case 88200: N = 12544; break; 1141 case 96000: N = 12288; break; 1142 case 176400: N = 25088; break; 1143 case 192000: N = 24576; break; 1144 default: 1145 return -EINVAL; 1146 } 1147 1148 /* Set N (used with CTS to regenerate the audio clock) */ 1149 adv7511_wr(sd, 0x01, (N >> 16) & 0xf); 1150 adv7511_wr(sd, 0x02, (N >> 8) & 0xff); 1151 adv7511_wr(sd, 0x03, N & 0xff); 1152 1153 return 0; 1154 } 1155 1156 static int adv7511_s_i2s_clock_freq(struct v4l2_subdev *sd, u32 freq) 1157 { 1158 u32 i2s_sf; 1159 1160 switch (freq) { 1161 case 32000: i2s_sf = 0x30; break; 1162 case 44100: i2s_sf = 0x00; break; 1163 case 48000: i2s_sf = 0x20; break; 1164 case 88200: i2s_sf = 0x80; break; 1165 case 96000: i2s_sf = 0xa0; break; 1166 case 176400: i2s_sf = 0xc0; break; 1167 case 192000: i2s_sf = 0xe0; break; 1168 default: 1169 return -EINVAL; 1170 } 1171 1172 /* Set sampling frequency for I2S audio to 48 kHz */ 1173 adv7511_wr_and_or(sd, 0x15, 0xf, i2s_sf); 1174 1175 return 0; 1176 } 1177 1178 static int adv7511_s_routing(struct v4l2_subdev *sd, u32 input, u32 output, u32 config) 1179 { 1180 /* Only 2 channels in use for application */ 1181 adv7511_wr_and_or(sd, 0x73, 0xf8, 0x1); 1182 /* Speaker mapping */ 1183 adv7511_wr(sd, 0x76, 0x00); 1184 1185 /* 16 bit audio word length */ 1186 adv7511_wr_and_or(sd, 0x14, 0xf0, 0x02); 1187 1188 return 0; 1189 } 1190 1191 static const struct v4l2_subdev_audio_ops adv7511_audio_ops = { 1192 .s_stream = adv7511_s_audio_stream, 1193 .s_clock_freq = adv7511_s_clock_freq, 1194 .s_i2s_clock_freq = adv7511_s_i2s_clock_freq, 1195 .s_routing = adv7511_s_routing, 1196 }; 1197 1198 /* ---------------------------- PAD OPS ------------------------------------- */ 1199 1200 static int adv7511_get_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid) 1201 { 1202 struct adv7511_state *state = get_adv7511_state(sd); 1203 1204 memset(edid->reserved, 0, sizeof(edid->reserved)); 1205 1206 if (edid->pad != 0) 1207 return -EINVAL; 1208 1209 if (edid->start_block == 0 && edid->blocks == 0) { 1210 edid->blocks = state->edid.segments * 2; 1211 return 0; 1212 } 1213 1214 if (state->edid.segments == 0) 1215 return -ENODATA; 1216 1217 if (edid->start_block >= state->edid.segments * 2) 1218 return -EINVAL; 1219 1220 if (edid->start_block + edid->blocks > state->edid.segments * 2) 1221 edid->blocks = state->edid.segments * 2 - edid->start_block; 1222 1223 memcpy(edid->edid, &state->edid.data[edid->start_block * 128], 1224 128 * edid->blocks); 1225 1226 return 0; 1227 } 1228 1229 static int adv7511_enum_mbus_code(struct v4l2_subdev *sd, 1230 struct v4l2_subdev_pad_config *cfg, 1231 struct v4l2_subdev_mbus_code_enum *code) 1232 { 1233 if (code->pad != 0) 1234 return -EINVAL; 1235 1236 switch (code->index) { 1237 case 0: 1238 code->code = MEDIA_BUS_FMT_RGB888_1X24; 1239 break; 1240 case 1: 1241 code->code = MEDIA_BUS_FMT_YUYV8_1X16; 1242 break; 1243 case 2: 1244 code->code = MEDIA_BUS_FMT_UYVY8_1X16; 1245 break; 1246 default: 1247 return -EINVAL; 1248 } 1249 return 0; 1250 } 1251 1252 static void adv7511_fill_format(struct adv7511_state *state, 1253 struct v4l2_mbus_framefmt *format) 1254 { 1255 format->width = state->dv_timings.bt.width; 1256 format->height = state->dv_timings.bt.height; 1257 format->field = V4L2_FIELD_NONE; 1258 } 1259 1260 static int adv7511_get_fmt(struct v4l2_subdev *sd, 1261 struct v4l2_subdev_pad_config *cfg, 1262 struct v4l2_subdev_format *format) 1263 { 1264 struct adv7511_state *state = get_adv7511_state(sd); 1265 1266 if (format->pad != 0) 1267 return -EINVAL; 1268 1269 memset(&format->format, 0, sizeof(format->format)); 1270 adv7511_fill_format(state, &format->format); 1271 1272 if (format->which == V4L2_SUBDEV_FORMAT_TRY) { 1273 struct v4l2_mbus_framefmt *fmt; 1274 1275 fmt = v4l2_subdev_get_try_format(sd, cfg, format->pad); 1276 format->format.code = fmt->code; 1277 format->format.colorspace = fmt->colorspace; 1278 format->format.ycbcr_enc = fmt->ycbcr_enc; 1279 format->format.quantization = fmt->quantization; 1280 format->format.xfer_func = fmt->xfer_func; 1281 } else { 1282 format->format.code = state->fmt_code; 1283 format->format.colorspace = state->colorspace; 1284 format->format.ycbcr_enc = state->ycbcr_enc; 1285 format->format.quantization = state->quantization; 1286 format->format.xfer_func = state->xfer_func; 1287 } 1288 1289 return 0; 1290 } 1291 1292 static int adv7511_set_fmt(struct v4l2_subdev *sd, 1293 struct v4l2_subdev_pad_config *cfg, 1294 struct v4l2_subdev_format *format) 1295 { 1296 struct adv7511_state *state = get_adv7511_state(sd); 1297 /* 1298 * Bitfield namings come the CEA-861-F standard, table 8 "Auxiliary 1299 * Video Information (AVI) InfoFrame Format" 1300 * 1301 * c = Colorimetry 1302 * ec = Extended Colorimetry 1303 * y = RGB or YCbCr 1304 * q = RGB Quantization Range 1305 * yq = YCC Quantization Range 1306 */ 1307 u8 c = HDMI_COLORIMETRY_NONE; 1308 u8 ec = HDMI_EXTENDED_COLORIMETRY_XV_YCC_601; 1309 u8 y = HDMI_COLORSPACE_RGB; 1310 u8 q = HDMI_QUANTIZATION_RANGE_DEFAULT; 1311 u8 yq = HDMI_YCC_QUANTIZATION_RANGE_LIMITED; 1312 u8 itc = state->content_type != V4L2_DV_IT_CONTENT_TYPE_NO_ITC; 1313 u8 cn = itc ? state->content_type : V4L2_DV_IT_CONTENT_TYPE_GRAPHICS; 1314 1315 if (format->pad != 0) 1316 return -EINVAL; 1317 switch (format->format.code) { 1318 case MEDIA_BUS_FMT_UYVY8_1X16: 1319 case MEDIA_BUS_FMT_YUYV8_1X16: 1320 case MEDIA_BUS_FMT_RGB888_1X24: 1321 break; 1322 default: 1323 return -EINVAL; 1324 } 1325 1326 adv7511_fill_format(state, &format->format); 1327 if (format->which == V4L2_SUBDEV_FORMAT_TRY) { 1328 struct v4l2_mbus_framefmt *fmt; 1329 1330 fmt = v4l2_subdev_get_try_format(sd, cfg, format->pad); 1331 fmt->code = format->format.code; 1332 fmt->colorspace = format->format.colorspace; 1333 fmt->ycbcr_enc = format->format.ycbcr_enc; 1334 fmt->quantization = format->format.quantization; 1335 fmt->xfer_func = format->format.xfer_func; 1336 return 0; 1337 } 1338 1339 switch (format->format.code) { 1340 case MEDIA_BUS_FMT_UYVY8_1X16: 1341 adv7511_wr_and_or(sd, 0x15, 0xf0, 0x01); 1342 adv7511_wr_and_or(sd, 0x16, 0x03, 0xb8); 1343 y = HDMI_COLORSPACE_YUV422; 1344 break; 1345 case MEDIA_BUS_FMT_YUYV8_1X16: 1346 adv7511_wr_and_or(sd, 0x15, 0xf0, 0x01); 1347 adv7511_wr_and_or(sd, 0x16, 0x03, 0xbc); 1348 y = HDMI_COLORSPACE_YUV422; 1349 break; 1350 case MEDIA_BUS_FMT_RGB888_1X24: 1351 default: 1352 adv7511_wr_and_or(sd, 0x15, 0xf0, 0x00); 1353 adv7511_wr_and_or(sd, 0x16, 0x03, 0x00); 1354 break; 1355 } 1356 state->fmt_code = format->format.code; 1357 state->colorspace = format->format.colorspace; 1358 state->ycbcr_enc = format->format.ycbcr_enc; 1359 state->quantization = format->format.quantization; 1360 state->xfer_func = format->format.xfer_func; 1361 1362 switch (format->format.colorspace) { 1363 case V4L2_COLORSPACE_OPRGB: 1364 c = HDMI_COLORIMETRY_EXTENDED; 1365 ec = y ? HDMI_EXTENDED_COLORIMETRY_OPYCC_601 : 1366 HDMI_EXTENDED_COLORIMETRY_OPRGB; 1367 break; 1368 case V4L2_COLORSPACE_SMPTE170M: 1369 c = y ? HDMI_COLORIMETRY_ITU_601 : HDMI_COLORIMETRY_NONE; 1370 if (y && format->format.ycbcr_enc == V4L2_YCBCR_ENC_XV601) { 1371 c = HDMI_COLORIMETRY_EXTENDED; 1372 ec = HDMI_EXTENDED_COLORIMETRY_XV_YCC_601; 1373 } 1374 break; 1375 case V4L2_COLORSPACE_REC709: 1376 c = y ? HDMI_COLORIMETRY_ITU_709 : HDMI_COLORIMETRY_NONE; 1377 if (y && format->format.ycbcr_enc == V4L2_YCBCR_ENC_XV709) { 1378 c = HDMI_COLORIMETRY_EXTENDED; 1379 ec = HDMI_EXTENDED_COLORIMETRY_XV_YCC_709; 1380 } 1381 break; 1382 case V4L2_COLORSPACE_SRGB: 1383 c = y ? HDMI_COLORIMETRY_EXTENDED : HDMI_COLORIMETRY_NONE; 1384 ec = y ? HDMI_EXTENDED_COLORIMETRY_S_YCC_601 : 1385 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601; 1386 break; 1387 case V4L2_COLORSPACE_BT2020: 1388 c = HDMI_COLORIMETRY_EXTENDED; 1389 if (y && format->format.ycbcr_enc == V4L2_YCBCR_ENC_BT2020_CONST_LUM) 1390 ec = 5; /* Not yet available in hdmi.h */ 1391 else 1392 ec = 6; /* Not yet available in hdmi.h */ 1393 break; 1394 default: 1395 break; 1396 } 1397 1398 /* 1399 * CEA-861-F says that for RGB formats the YCC range must match the 1400 * RGB range, although sources should ignore the YCC range. 1401 * 1402 * The RGB quantization range shouldn't be non-zero if the EDID doesn't 1403 * have the Q bit set in the Video Capabilities Data Block, however this 1404 * isn't checked at the moment. The assumption is that the application 1405 * knows the EDID and can detect this. 1406 * 1407 * The same is true for the YCC quantization range: non-standard YCC 1408 * quantization ranges should only be sent if the EDID has the YQ bit 1409 * set in the Video Capabilities Data Block. 1410 */ 1411 switch (format->format.quantization) { 1412 case V4L2_QUANTIZATION_FULL_RANGE: 1413 q = y ? HDMI_QUANTIZATION_RANGE_DEFAULT : 1414 HDMI_QUANTIZATION_RANGE_FULL; 1415 yq = q ? q - 1 : HDMI_YCC_QUANTIZATION_RANGE_FULL; 1416 break; 1417 case V4L2_QUANTIZATION_LIM_RANGE: 1418 q = y ? HDMI_QUANTIZATION_RANGE_DEFAULT : 1419 HDMI_QUANTIZATION_RANGE_LIMITED; 1420 yq = q ? q - 1 : HDMI_YCC_QUANTIZATION_RANGE_LIMITED; 1421 break; 1422 } 1423 1424 adv7511_wr_and_or(sd, 0x4a, 0xbf, 0); 1425 adv7511_wr_and_or(sd, 0x55, 0x9f, y << 5); 1426 adv7511_wr_and_or(sd, 0x56, 0x3f, c << 6); 1427 adv7511_wr_and_or(sd, 0x57, 0x83, (ec << 4) | (q << 2) | (itc << 7)); 1428 adv7511_wr_and_or(sd, 0x59, 0x0f, (yq << 6) | (cn << 4)); 1429 adv7511_wr_and_or(sd, 0x4a, 0xff, 1); 1430 adv7511_set_rgb_quantization_mode(sd, state->rgb_quantization_range_ctrl); 1431 1432 return 0; 1433 } 1434 1435 static const struct v4l2_subdev_pad_ops adv7511_pad_ops = { 1436 .get_edid = adv7511_get_edid, 1437 .enum_mbus_code = adv7511_enum_mbus_code, 1438 .get_fmt = adv7511_get_fmt, 1439 .set_fmt = adv7511_set_fmt, 1440 .enum_dv_timings = adv7511_enum_dv_timings, 1441 .dv_timings_cap = adv7511_dv_timings_cap, 1442 }; 1443 1444 /* --------------------- SUBDEV OPS --------------------------------------- */ 1445 1446 static const struct v4l2_subdev_ops adv7511_ops = { 1447 .core = &adv7511_core_ops, 1448 .pad = &adv7511_pad_ops, 1449 .video = &adv7511_video_ops, 1450 .audio = &adv7511_audio_ops, 1451 }; 1452 1453 /* ----------------------------------------------------------------------- */ 1454 static void adv7511_dbg_dump_edid(int lvl, int debug, struct v4l2_subdev *sd, int segment, u8 *buf) 1455 { 1456 if (debug >= lvl) { 1457 int i, j; 1458 v4l2_dbg(lvl, debug, sd, "edid segment %d\n", segment); 1459 for (i = 0; i < 256; i += 16) { 1460 u8 b[128]; 1461 u8 *bp = b; 1462 if (i == 128) 1463 v4l2_dbg(lvl, debug, sd, "\n"); 1464 for (j = i; j < i + 16; j++) { 1465 sprintf(bp, "0x%02x, ", buf[j]); 1466 bp += 6; 1467 } 1468 bp[0] = '\0'; 1469 v4l2_dbg(lvl, debug, sd, "%s\n", b); 1470 } 1471 } 1472 } 1473 1474 static void adv7511_notify_no_edid(struct v4l2_subdev *sd) 1475 { 1476 struct adv7511_state *state = get_adv7511_state(sd); 1477 struct adv7511_edid_detect ed; 1478 1479 /* We failed to read the EDID, so send an event for this. */ 1480 ed.present = false; 1481 ed.segment = adv7511_rd(sd, 0xc4); 1482 ed.phys_addr = CEC_PHYS_ADDR_INVALID; 1483 cec_s_phys_addr(state->cec_adap, ed.phys_addr, false); 1484 v4l2_subdev_notify(sd, ADV7511_EDID_DETECT, (void *)&ed); 1485 v4l2_ctrl_s_ctrl(state->have_edid0_ctrl, 0x0); 1486 } 1487 1488 static void adv7511_edid_handler(struct work_struct *work) 1489 { 1490 struct delayed_work *dwork = to_delayed_work(work); 1491 struct adv7511_state *state = container_of(dwork, struct adv7511_state, edid_handler); 1492 struct v4l2_subdev *sd = &state->sd; 1493 1494 v4l2_dbg(1, debug, sd, "%s:\n", __func__); 1495 1496 if (adv7511_check_edid_status(sd)) { 1497 /* Return if we received the EDID. */ 1498 return; 1499 } 1500 1501 if (adv7511_have_hotplug(sd)) { 1502 /* We must retry reading the EDID several times, it is possible 1503 * that initially the EDID couldn't be read due to i2c errors 1504 * (DVI connectors are particularly prone to this problem). */ 1505 if (state->edid.read_retries) { 1506 state->edid.read_retries--; 1507 v4l2_dbg(1, debug, sd, "%s: edid read failed\n", __func__); 1508 state->have_monitor = false; 1509 adv7511_s_power(sd, false); 1510 adv7511_s_power(sd, true); 1511 queue_delayed_work(state->work_queue, &state->edid_handler, EDID_DELAY); 1512 return; 1513 } 1514 } 1515 1516 /* We failed to read the EDID, so send an event for this. */ 1517 adv7511_notify_no_edid(sd); 1518 v4l2_dbg(1, debug, sd, "%s: no edid found\n", __func__); 1519 } 1520 1521 static void adv7511_audio_setup(struct v4l2_subdev *sd) 1522 { 1523 v4l2_dbg(1, debug, sd, "%s\n", __func__); 1524 1525 adv7511_s_i2s_clock_freq(sd, 48000); 1526 adv7511_s_clock_freq(sd, 48000); 1527 adv7511_s_routing(sd, 0, 0, 0); 1528 } 1529 1530 /* Configure hdmi transmitter. */ 1531 static void adv7511_setup(struct v4l2_subdev *sd) 1532 { 1533 struct adv7511_state *state = get_adv7511_state(sd); 1534 v4l2_dbg(1, debug, sd, "%s\n", __func__); 1535 1536 /* Input format: RGB 4:4:4 */ 1537 adv7511_wr_and_or(sd, 0x15, 0xf0, 0x0); 1538 /* Output format: RGB 4:4:4 */ 1539 adv7511_wr_and_or(sd, 0x16, 0x7f, 0x0); 1540 /* 1st order interpolation 4:2:2 -> 4:4:4 up conversion, Aspect ratio: 16:9 */ 1541 adv7511_wr_and_or(sd, 0x17, 0xf9, 0x06); 1542 /* Disable pixel repetition */ 1543 adv7511_wr_and_or(sd, 0x3b, 0x9f, 0x0); 1544 /* Disable CSC */ 1545 adv7511_wr_and_or(sd, 0x18, 0x7f, 0x0); 1546 /* Output format: RGB 4:4:4, Active Format Information is valid, 1547 * underscanned */ 1548 adv7511_wr_and_or(sd, 0x55, 0x9c, 0x12); 1549 /* AVI Info frame packet enable, Audio Info frame disable */ 1550 adv7511_wr_and_or(sd, 0x44, 0xe7, 0x10); 1551 /* Colorimetry, Active format aspect ratio: same as picure. */ 1552 adv7511_wr(sd, 0x56, 0xa8); 1553 /* No encryption */ 1554 adv7511_wr_and_or(sd, 0xaf, 0xed, 0x0); 1555 1556 /* Positive clk edge capture for input video clock */ 1557 adv7511_wr_and_or(sd, 0xba, 0x1f, 0x60); 1558 1559 adv7511_audio_setup(sd); 1560 1561 v4l2_ctrl_handler_setup(&state->hdl); 1562 } 1563 1564 static void adv7511_notify_monitor_detect(struct v4l2_subdev *sd) 1565 { 1566 struct adv7511_monitor_detect mdt; 1567 struct adv7511_state *state = get_adv7511_state(sd); 1568 1569 mdt.present = state->have_monitor; 1570 v4l2_subdev_notify(sd, ADV7511_MONITOR_DETECT, (void *)&mdt); 1571 } 1572 1573 static void adv7511_check_monitor_present_status(struct v4l2_subdev *sd) 1574 { 1575 struct adv7511_state *state = get_adv7511_state(sd); 1576 /* read hotplug and rx-sense state */ 1577 u8 status = adv7511_rd(sd, 0x42); 1578 1579 v4l2_dbg(1, debug, sd, "%s: status: 0x%x%s%s\n", 1580 __func__, 1581 status, 1582 status & MASK_ADV7511_HPD_DETECT ? ", hotplug" : "", 1583 status & MASK_ADV7511_MSEN_DETECT ? ", rx-sense" : ""); 1584 1585 /* update read only ctrls */ 1586 v4l2_ctrl_s_ctrl(state->hotplug_ctrl, adv7511_have_hotplug(sd) ? 0x1 : 0x0); 1587 v4l2_ctrl_s_ctrl(state->rx_sense_ctrl, adv7511_have_rx_sense(sd) ? 0x1 : 0x0); 1588 1589 if ((status & MASK_ADV7511_HPD_DETECT) && ((status & MASK_ADV7511_MSEN_DETECT) || state->edid.segments)) { 1590 v4l2_dbg(1, debug, sd, "%s: hotplug and (rx-sense or edid)\n", __func__); 1591 if (!state->have_monitor) { 1592 v4l2_dbg(1, debug, sd, "%s: monitor detected\n", __func__); 1593 state->have_monitor = true; 1594 adv7511_set_isr(sd, true); 1595 if (!adv7511_s_power(sd, true)) { 1596 v4l2_dbg(1, debug, sd, "%s: monitor detected, powerup failed\n", __func__); 1597 return; 1598 } 1599 adv7511_setup(sd); 1600 adv7511_notify_monitor_detect(sd); 1601 state->edid.read_retries = EDID_MAX_RETRIES; 1602 queue_delayed_work(state->work_queue, &state->edid_handler, EDID_DELAY); 1603 } 1604 } else if (status & MASK_ADV7511_HPD_DETECT) { 1605 v4l2_dbg(1, debug, sd, "%s: hotplug detected\n", __func__); 1606 state->edid.read_retries = EDID_MAX_RETRIES; 1607 queue_delayed_work(state->work_queue, &state->edid_handler, EDID_DELAY); 1608 } else if (!(status & MASK_ADV7511_HPD_DETECT)) { 1609 v4l2_dbg(1, debug, sd, "%s: hotplug not detected\n", __func__); 1610 if (state->have_monitor) { 1611 v4l2_dbg(1, debug, sd, "%s: monitor not detected\n", __func__); 1612 state->have_monitor = false; 1613 adv7511_notify_monitor_detect(sd); 1614 } 1615 adv7511_s_power(sd, false); 1616 memset(&state->edid, 0, sizeof(struct adv7511_state_edid)); 1617 adv7511_notify_no_edid(sd); 1618 } 1619 } 1620 1621 static bool edid_block_verify_crc(u8 *edid_block) 1622 { 1623 u8 sum = 0; 1624 int i; 1625 1626 for (i = 0; i < 128; i++) 1627 sum += edid_block[i]; 1628 return sum == 0; 1629 } 1630 1631 static bool edid_verify_crc(struct v4l2_subdev *sd, u32 segment) 1632 { 1633 struct adv7511_state *state = get_adv7511_state(sd); 1634 u32 blocks = state->edid.blocks; 1635 u8 *data = state->edid.data; 1636 1637 if (!edid_block_verify_crc(&data[segment * 256])) 1638 return false; 1639 if ((segment + 1) * 2 <= blocks) 1640 return edid_block_verify_crc(&data[segment * 256 + 128]); 1641 return true; 1642 } 1643 1644 static bool edid_verify_header(struct v4l2_subdev *sd, u32 segment) 1645 { 1646 static const u8 hdmi_header[] = { 1647 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 1648 }; 1649 struct adv7511_state *state = get_adv7511_state(sd); 1650 u8 *data = state->edid.data; 1651 1652 if (segment != 0) 1653 return true; 1654 return !memcmp(data, hdmi_header, sizeof(hdmi_header)); 1655 } 1656 1657 static bool adv7511_check_edid_status(struct v4l2_subdev *sd) 1658 { 1659 struct adv7511_state *state = get_adv7511_state(sd); 1660 u8 edidRdy = adv7511_rd(sd, 0xc5); 1661 1662 v4l2_dbg(1, debug, sd, "%s: edid ready (retries: %d)\n", 1663 __func__, EDID_MAX_RETRIES - state->edid.read_retries); 1664 1665 if (state->edid.complete) 1666 return true; 1667 1668 if (edidRdy & MASK_ADV7511_EDID_RDY) { 1669 int segment = adv7511_rd(sd, 0xc4); 1670 struct adv7511_edid_detect ed; 1671 1672 if (segment >= EDID_MAX_SEGM) { 1673 v4l2_err(sd, "edid segment number too big\n"); 1674 return false; 1675 } 1676 v4l2_dbg(1, debug, sd, "%s: got segment %d\n", __func__, segment); 1677 adv7511_edid_rd(sd, 256, &state->edid.data[segment * 256]); 1678 adv7511_dbg_dump_edid(2, debug, sd, segment, &state->edid.data[segment * 256]); 1679 if (segment == 0) { 1680 state->edid.blocks = state->edid.data[0x7e] + 1; 1681 v4l2_dbg(1, debug, sd, "%s: %d blocks in total\n", __func__, state->edid.blocks); 1682 } 1683 if (!edid_verify_crc(sd, segment) || 1684 !edid_verify_header(sd, segment)) { 1685 /* edid crc error, force reread of edid segment */ 1686 v4l2_err(sd, "%s: edid crc or header error\n", __func__); 1687 state->have_monitor = false; 1688 adv7511_s_power(sd, false); 1689 adv7511_s_power(sd, true); 1690 return false; 1691 } 1692 /* one more segment read ok */ 1693 state->edid.segments = segment + 1; 1694 v4l2_ctrl_s_ctrl(state->have_edid0_ctrl, 0x1); 1695 if (((state->edid.data[0x7e] >> 1) + 1) > state->edid.segments) { 1696 /* Request next EDID segment */ 1697 v4l2_dbg(1, debug, sd, "%s: request segment %d\n", __func__, state->edid.segments); 1698 adv7511_wr(sd, 0xc9, 0xf); 1699 adv7511_wr(sd, 0xc4, state->edid.segments); 1700 state->edid.read_retries = EDID_MAX_RETRIES; 1701 queue_delayed_work(state->work_queue, &state->edid_handler, EDID_DELAY); 1702 return false; 1703 } 1704 1705 v4l2_dbg(1, debug, sd, "%s: edid complete with %d segment(s)\n", __func__, state->edid.segments); 1706 state->edid.complete = true; 1707 ed.phys_addr = cec_get_edid_phys_addr(state->edid.data, 1708 state->edid.segments * 256, 1709 NULL); 1710 /* report when we have all segments 1711 but report only for segment 0 1712 */ 1713 ed.present = true; 1714 ed.segment = 0; 1715 state->edid_detect_counter++; 1716 cec_s_phys_addr(state->cec_adap, ed.phys_addr, false); 1717 v4l2_subdev_notify(sd, ADV7511_EDID_DETECT, (void *)&ed); 1718 return ed.present; 1719 } 1720 1721 return false; 1722 } 1723 1724 static int adv7511_registered(struct v4l2_subdev *sd) 1725 { 1726 struct adv7511_state *state = get_adv7511_state(sd); 1727 struct i2c_client *client = v4l2_get_subdevdata(sd); 1728 int err; 1729 1730 err = cec_register_adapter(state->cec_adap, &client->dev); 1731 if (err) 1732 cec_delete_adapter(state->cec_adap); 1733 return err; 1734 } 1735 1736 static void adv7511_unregistered(struct v4l2_subdev *sd) 1737 { 1738 struct adv7511_state *state = get_adv7511_state(sd); 1739 1740 cec_unregister_adapter(state->cec_adap); 1741 } 1742 1743 static const struct v4l2_subdev_internal_ops adv7511_int_ops = { 1744 .registered = adv7511_registered, 1745 .unregistered = adv7511_unregistered, 1746 }; 1747 1748 /* ----------------------------------------------------------------------- */ 1749 /* Setup ADV7511 */ 1750 static void adv7511_init_setup(struct v4l2_subdev *sd) 1751 { 1752 struct adv7511_state *state = get_adv7511_state(sd); 1753 struct adv7511_state_edid *edid = &state->edid; 1754 u32 cec_clk = state->pdata.cec_clk; 1755 u8 ratio; 1756 1757 v4l2_dbg(1, debug, sd, "%s\n", __func__); 1758 1759 /* clear all interrupts */ 1760 adv7511_wr(sd, 0x96, 0xff); 1761 adv7511_wr(sd, 0x97, 0xff); 1762 /* 1763 * Stop HPD from resetting a lot of registers. 1764 * It might leave the chip in a partly un-initialized state, 1765 * in particular with regards to hotplug bounces. 1766 */ 1767 adv7511_wr_and_or(sd, 0xd6, 0x3f, 0xc0); 1768 memset(edid, 0, sizeof(struct adv7511_state_edid)); 1769 state->have_monitor = false; 1770 adv7511_set_isr(sd, false); 1771 adv7511_s_stream(sd, false); 1772 adv7511_s_audio_stream(sd, false); 1773 1774 if (state->i2c_cec == NULL) 1775 return; 1776 1777 v4l2_dbg(1, debug, sd, "%s: cec_clk %d\n", __func__, cec_clk); 1778 1779 /* cec soft reset */ 1780 adv7511_cec_write(sd, 0x50, 0x01); 1781 adv7511_cec_write(sd, 0x50, 0x00); 1782 1783 /* legacy mode */ 1784 adv7511_cec_write(sd, 0x4a, 0x00); 1785 adv7511_cec_write(sd, 0x4a, 0x07); 1786 1787 if (cec_clk % 750000 != 0) 1788 v4l2_err(sd, "%s: cec_clk %d, not multiple of 750 Khz\n", 1789 __func__, cec_clk); 1790 1791 ratio = (cec_clk / 750000) - 1; 1792 adv7511_cec_write(sd, 0x4e, ratio << 2); 1793 } 1794 1795 static int adv7511_probe(struct i2c_client *client, const struct i2c_device_id *id) 1796 { 1797 struct adv7511_state *state; 1798 struct adv7511_platform_data *pdata = client->dev.platform_data; 1799 struct v4l2_ctrl_handler *hdl; 1800 struct v4l2_subdev *sd; 1801 u8 chip_id[2]; 1802 int err = -EIO; 1803 1804 /* Check if the adapter supports the needed features */ 1805 if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA)) 1806 return -EIO; 1807 1808 state = devm_kzalloc(&client->dev, sizeof(struct adv7511_state), GFP_KERNEL); 1809 if (!state) 1810 return -ENOMEM; 1811 1812 /* Platform data */ 1813 if (!pdata) { 1814 v4l_err(client, "No platform data!\n"); 1815 return -ENODEV; 1816 } 1817 memcpy(&state->pdata, pdata, sizeof(state->pdata)); 1818 state->fmt_code = MEDIA_BUS_FMT_RGB888_1X24; 1819 state->colorspace = V4L2_COLORSPACE_SRGB; 1820 1821 sd = &state->sd; 1822 1823 v4l2_dbg(1, debug, sd, "detecting adv7511 client on address 0x%x\n", 1824 client->addr << 1); 1825 1826 v4l2_i2c_subdev_init(sd, client, &adv7511_ops); 1827 sd->internal_ops = &adv7511_int_ops; 1828 1829 hdl = &state->hdl; 1830 v4l2_ctrl_handler_init(hdl, 10); 1831 /* add in ascending ID order */ 1832 state->hdmi_mode_ctrl = v4l2_ctrl_new_std_menu(hdl, &adv7511_ctrl_ops, 1833 V4L2_CID_DV_TX_MODE, V4L2_DV_TX_MODE_HDMI, 1834 0, V4L2_DV_TX_MODE_DVI_D); 1835 state->hotplug_ctrl = v4l2_ctrl_new_std(hdl, NULL, 1836 V4L2_CID_DV_TX_HOTPLUG, 0, 1, 0, 0); 1837 state->rx_sense_ctrl = v4l2_ctrl_new_std(hdl, NULL, 1838 V4L2_CID_DV_TX_RXSENSE, 0, 1, 0, 0); 1839 state->have_edid0_ctrl = v4l2_ctrl_new_std(hdl, NULL, 1840 V4L2_CID_DV_TX_EDID_PRESENT, 0, 1, 0, 0); 1841 state->rgb_quantization_range_ctrl = 1842 v4l2_ctrl_new_std_menu(hdl, &adv7511_ctrl_ops, 1843 V4L2_CID_DV_TX_RGB_RANGE, V4L2_DV_RGB_RANGE_FULL, 1844 0, V4L2_DV_RGB_RANGE_AUTO); 1845 state->content_type_ctrl = 1846 v4l2_ctrl_new_std_menu(hdl, &adv7511_ctrl_ops, 1847 V4L2_CID_DV_TX_IT_CONTENT_TYPE, V4L2_DV_IT_CONTENT_TYPE_NO_ITC, 1848 0, V4L2_DV_IT_CONTENT_TYPE_NO_ITC); 1849 sd->ctrl_handler = hdl; 1850 if (hdl->error) { 1851 err = hdl->error; 1852 goto err_hdl; 1853 } 1854 state->pad.flags = MEDIA_PAD_FL_SINK; 1855 sd->entity.function = MEDIA_ENT_F_DV_ENCODER; 1856 err = media_entity_pads_init(&sd->entity, 1, &state->pad); 1857 if (err) 1858 goto err_hdl; 1859 1860 /* EDID and CEC i2c addr */ 1861 state->i2c_edid_addr = state->pdata.i2c_edid << 1; 1862 state->i2c_cec_addr = state->pdata.i2c_cec << 1; 1863 state->i2c_pktmem_addr = state->pdata.i2c_pktmem << 1; 1864 1865 state->chip_revision = adv7511_rd(sd, 0x0); 1866 chip_id[0] = adv7511_rd(sd, 0xf5); 1867 chip_id[1] = adv7511_rd(sd, 0xf6); 1868 if (chip_id[0] != 0x75 || chip_id[1] != 0x11) { 1869 v4l2_err(sd, "chip_id != 0x7511, read 0x%02x%02x\n", chip_id[0], 1870 chip_id[1]); 1871 err = -EIO; 1872 goto err_entity; 1873 } 1874 1875 state->i2c_edid = i2c_new_dummy_device(client->adapter, 1876 state->i2c_edid_addr >> 1); 1877 if (IS_ERR(state->i2c_edid)) { 1878 v4l2_err(sd, "failed to register edid i2c client\n"); 1879 err = PTR_ERR(state->i2c_edid); 1880 goto err_entity; 1881 } 1882 1883 adv7511_wr(sd, 0xe1, state->i2c_cec_addr); 1884 if (state->pdata.cec_clk < 3000000 || 1885 state->pdata.cec_clk > 100000000) { 1886 v4l2_err(sd, "%s: cec_clk %u outside range, disabling cec\n", 1887 __func__, state->pdata.cec_clk); 1888 state->pdata.cec_clk = 0; 1889 } 1890 1891 if (state->pdata.cec_clk) { 1892 state->i2c_cec = i2c_new_dummy_device(client->adapter, 1893 state->i2c_cec_addr >> 1); 1894 if (IS_ERR(state->i2c_cec)) { 1895 v4l2_err(sd, "failed to register cec i2c client\n"); 1896 err = PTR_ERR(state->i2c_cec); 1897 goto err_unreg_edid; 1898 } 1899 adv7511_wr(sd, 0xe2, 0x00); /* power up cec section */ 1900 } else { 1901 adv7511_wr(sd, 0xe2, 0x01); /* power down cec section */ 1902 } 1903 1904 state->i2c_pktmem = i2c_new_dummy_device(client->adapter, state->i2c_pktmem_addr >> 1); 1905 if (IS_ERR(state->i2c_pktmem)) { 1906 v4l2_err(sd, "failed to register pktmem i2c client\n"); 1907 err = PTR_ERR(state->i2c_pktmem); 1908 goto err_unreg_cec; 1909 } 1910 1911 state->work_queue = create_singlethread_workqueue(sd->name); 1912 if (state->work_queue == NULL) { 1913 v4l2_err(sd, "could not create workqueue\n"); 1914 err = -ENOMEM; 1915 goto err_unreg_pktmem; 1916 } 1917 1918 INIT_DELAYED_WORK(&state->edid_handler, adv7511_edid_handler); 1919 1920 adv7511_init_setup(sd); 1921 1922 #if IS_ENABLED(CONFIG_VIDEO_ADV7511_CEC) 1923 state->cec_adap = cec_allocate_adapter(&adv7511_cec_adap_ops, 1924 state, dev_name(&client->dev), CEC_CAP_DEFAULTS, 1925 ADV7511_MAX_ADDRS); 1926 err = PTR_ERR_OR_ZERO(state->cec_adap); 1927 if (err) { 1928 destroy_workqueue(state->work_queue); 1929 goto err_unreg_pktmem; 1930 } 1931 #endif 1932 1933 adv7511_set_isr(sd, true); 1934 adv7511_check_monitor_present_status(sd); 1935 1936 v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name, 1937 client->addr << 1, client->adapter->name); 1938 return 0; 1939 1940 err_unreg_pktmem: 1941 i2c_unregister_device(state->i2c_pktmem); 1942 err_unreg_cec: 1943 i2c_unregister_device(state->i2c_cec); 1944 err_unreg_edid: 1945 i2c_unregister_device(state->i2c_edid); 1946 err_entity: 1947 media_entity_cleanup(&sd->entity); 1948 err_hdl: 1949 v4l2_ctrl_handler_free(&state->hdl); 1950 return err; 1951 } 1952 1953 /* ----------------------------------------------------------------------- */ 1954 1955 static int adv7511_remove(struct i2c_client *client) 1956 { 1957 struct v4l2_subdev *sd = i2c_get_clientdata(client); 1958 struct adv7511_state *state = get_adv7511_state(sd); 1959 1960 state->chip_revision = -1; 1961 1962 v4l2_dbg(1, debug, sd, "%s removed @ 0x%x (%s)\n", client->name, 1963 client->addr << 1, client->adapter->name); 1964 1965 adv7511_set_isr(sd, false); 1966 adv7511_init_setup(sd); 1967 cancel_delayed_work(&state->edid_handler); 1968 i2c_unregister_device(state->i2c_edid); 1969 i2c_unregister_device(state->i2c_cec); 1970 i2c_unregister_device(state->i2c_pktmem); 1971 destroy_workqueue(state->work_queue); 1972 v4l2_device_unregister_subdev(sd); 1973 media_entity_cleanup(&sd->entity); 1974 v4l2_ctrl_handler_free(sd->ctrl_handler); 1975 return 0; 1976 } 1977 1978 /* ----------------------------------------------------------------------- */ 1979 1980 static const struct i2c_device_id adv7511_id[] = { 1981 { "adv7511-v4l2", 0 }, 1982 { } 1983 }; 1984 MODULE_DEVICE_TABLE(i2c, adv7511_id); 1985 1986 static struct i2c_driver adv7511_driver = { 1987 .driver = { 1988 .name = "adv7511-v4l2", 1989 }, 1990 .probe = adv7511_probe, 1991 .remove = adv7511_remove, 1992 .id_table = adv7511_id, 1993 }; 1994 1995 module_i2c_driver(adv7511_driver); 1996