1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Driver for Analog Devices ADV748X video decoder and HDMI receiver 4 * 5 * Copyright (C) 2017 Renesas Electronics Corp. 6 * 7 * Authors: 8 * Koji Matsuoka <koji.matsuoka.xm@renesas.com> 9 * Niklas Söderlund <niklas.soderlund@ragnatech.se> 10 * Kieran Bingham <kieran.bingham@ideasonboard.com> 11 * 12 * The ADV748x range of receivers have the following configurations: 13 * 14 * Analog HDMI MHL 4-Lane 1-Lane 15 * In In CSI CSI 16 * ADV7480 X X X 17 * ADV7481 X X X X X 18 * ADV7482 X X X X 19 */ 20 21 #include <linux/i2c.h> 22 23 #ifndef _ADV748X_H_ 24 #define _ADV748X_H_ 25 26 enum adv748x_page { 27 ADV748X_PAGE_IO, 28 ADV748X_PAGE_DPLL, 29 ADV748X_PAGE_CP, 30 ADV748X_PAGE_HDMI, 31 ADV748X_PAGE_EDID, 32 ADV748X_PAGE_REPEATER, 33 ADV748X_PAGE_INFOFRAME, 34 ADV748X_PAGE_CBUS, 35 ADV748X_PAGE_CEC, 36 ADV748X_PAGE_SDP, 37 ADV748X_PAGE_TXB, 38 ADV748X_PAGE_TXA, 39 ADV748X_PAGE_MAX, 40 41 /* Fake pages for register sequences */ 42 ADV748X_PAGE_WAIT, /* Wait x msec */ 43 ADV748X_PAGE_EOR, /* End Mark */ 44 }; 45 46 /** 47 * enum adv748x_ports - Device tree port number definitions 48 * 49 * The ADV748X ports define the mapping between subdevices 50 * and the device tree specification 51 */ 52 enum adv748x_ports { 53 ADV748X_PORT_AIN0 = 0, 54 ADV748X_PORT_AIN1 = 1, 55 ADV748X_PORT_AIN2 = 2, 56 ADV748X_PORT_AIN3 = 3, 57 ADV748X_PORT_AIN4 = 4, 58 ADV748X_PORT_AIN5 = 5, 59 ADV748X_PORT_AIN6 = 6, 60 ADV748X_PORT_AIN7 = 7, 61 ADV748X_PORT_HDMI = 8, 62 ADV748X_PORT_TTL = 9, 63 ADV748X_PORT_TXA = 10, 64 ADV748X_PORT_TXB = 11, 65 ADV748X_PORT_MAX = 12, 66 }; 67 68 enum adv748x_csi2_pads { 69 ADV748X_CSI2_SINK, 70 ADV748X_CSI2_SOURCE, 71 ADV748X_CSI2_NR_PADS, 72 }; 73 74 /* CSI2 transmitters can have 2 internal connections, HDMI/AFE */ 75 #define ADV748X_CSI2_MAX_SUBDEVS 2 76 77 struct adv748x_csi2 { 78 struct adv748x_state *state; 79 struct v4l2_mbus_framefmt format; 80 unsigned int page; 81 unsigned int port; 82 83 struct media_pad pads[ADV748X_CSI2_NR_PADS]; 84 struct v4l2_ctrl_handler ctrl_hdl; 85 struct v4l2_ctrl *pixel_rate; 86 struct v4l2_subdev sd; 87 }; 88 89 #define notifier_to_csi2(n) container_of(n, struct adv748x_csi2, notifier) 90 #define adv748x_sd_to_csi2(sd) container_of(sd, struct adv748x_csi2, sd) 91 #define is_tx_enabled(_tx) ((_tx)->state->endpoints[(_tx)->port] != NULL) 92 #define is_txa(_tx) ((_tx) == &(_tx)->state->txa) 93 #define is_afe_enabled(_state) \ 94 ((_state)->endpoints[ADV748X_PORT_AIN0] != NULL || \ 95 (_state)->endpoints[ADV748X_PORT_AIN1] != NULL || \ 96 (_state)->endpoints[ADV748X_PORT_AIN2] != NULL || \ 97 (_state)->endpoints[ADV748X_PORT_AIN3] != NULL || \ 98 (_state)->endpoints[ADV748X_PORT_AIN4] != NULL || \ 99 (_state)->endpoints[ADV748X_PORT_AIN5] != NULL || \ 100 (_state)->endpoints[ADV748X_PORT_AIN6] != NULL || \ 101 (_state)->endpoints[ADV748X_PORT_AIN7] != NULL) 102 #define is_hdmi_enabled(_state) ((_state)->endpoints[ADV748X_PORT_HDMI] != NULL) 103 104 enum adv748x_hdmi_pads { 105 ADV748X_HDMI_SINK, 106 ADV748X_HDMI_SOURCE, 107 ADV748X_HDMI_NR_PADS, 108 }; 109 110 struct adv748x_hdmi { 111 struct media_pad pads[ADV748X_HDMI_NR_PADS]; 112 struct v4l2_ctrl_handler ctrl_hdl; 113 struct v4l2_subdev sd; 114 struct v4l2_mbus_framefmt format; 115 116 struct v4l2_dv_timings timings; 117 struct v4l2_fract aspect_ratio; 118 119 struct { 120 u8 edid[512]; 121 u32 present; 122 unsigned int blocks; 123 } edid; 124 }; 125 126 #define adv748x_ctrl_to_hdmi(ctrl) \ 127 container_of(ctrl->handler, struct adv748x_hdmi, ctrl_hdl) 128 #define adv748x_sd_to_hdmi(sd) container_of(sd, struct adv748x_hdmi, sd) 129 130 enum adv748x_afe_pads { 131 ADV748X_AFE_SINK_AIN0, 132 ADV748X_AFE_SINK_AIN1, 133 ADV748X_AFE_SINK_AIN2, 134 ADV748X_AFE_SINK_AIN3, 135 ADV748X_AFE_SINK_AIN4, 136 ADV748X_AFE_SINK_AIN5, 137 ADV748X_AFE_SINK_AIN6, 138 ADV748X_AFE_SINK_AIN7, 139 ADV748X_AFE_SOURCE, 140 ADV748X_AFE_NR_PADS, 141 }; 142 143 struct adv748x_afe { 144 struct media_pad pads[ADV748X_AFE_NR_PADS]; 145 struct v4l2_ctrl_handler ctrl_hdl; 146 struct v4l2_subdev sd; 147 struct v4l2_mbus_framefmt format; 148 149 bool streaming; 150 v4l2_std_id curr_norm; 151 unsigned int input; 152 }; 153 154 #define adv748x_ctrl_to_afe(ctrl) \ 155 container_of(ctrl->handler, struct adv748x_afe, ctrl_hdl) 156 #define adv748x_sd_to_afe(sd) container_of(sd, struct adv748x_afe, sd) 157 158 /** 159 * struct adv748x_state - State of ADV748X 160 * @dev: (OF) device 161 * @client: I2C client 162 * @mutex: protect global state 163 * 164 * @endpoints: parsed device node endpoints for each port 165 * 166 * @i2c_addresses I2C Page addresses 167 * @i2c_clients I2C clients for the page accesses 168 * @regmap regmap configuration pages. 169 * 170 * @hdmi: state of HDMI receiver context 171 * @afe: state of AFE receiver context 172 * @txa: state of TXA transmitter context 173 * @txb: state of TXB transmitter context 174 */ 175 struct adv748x_state { 176 struct device *dev; 177 struct i2c_client *client; 178 struct mutex mutex; 179 180 struct device_node *endpoints[ADV748X_PORT_MAX]; 181 182 struct i2c_client *i2c_clients[ADV748X_PAGE_MAX]; 183 struct regmap *regmap[ADV748X_PAGE_MAX]; 184 185 struct adv748x_hdmi hdmi; 186 struct adv748x_afe afe; 187 struct adv748x_csi2 txa; 188 struct adv748x_csi2 txb; 189 }; 190 191 #define adv748x_hdmi_to_state(h) container_of(h, struct adv748x_state, hdmi) 192 #define adv748x_afe_to_state(a) container_of(a, struct adv748x_state, afe) 193 194 #define adv_err(a, fmt, arg...) dev_err(a->dev, fmt, ##arg) 195 #define adv_info(a, fmt, arg...) dev_info(a->dev, fmt, ##arg) 196 #define adv_dbg(a, fmt, arg...) dev_dbg(a->dev, fmt, ##arg) 197 198 /* Register Mappings */ 199 200 /* IO Map */ 201 #define ADV748X_IO_PD 0x00 /* power down controls */ 202 #define ADV748X_IO_PD_RX_EN BIT(6) 203 204 #define ADV748X_IO_REG_04 0x04 205 #define ADV748X_IO_REG_04_FORCE_FR BIT(0) /* Force CP free-run */ 206 207 #define ADV748X_IO_DATAPATH 0x03 /* datapath cntrl */ 208 #define ADV748X_IO_DATAPATH_VFREQ_M 0x70 209 #define ADV748X_IO_DATAPATH_VFREQ_SHIFT 4 210 211 #define ADV748X_IO_VID_STD 0x05 212 213 #define ADV748X_IO_10 0x10 /* io_reg_10 */ 214 #define ADV748X_IO_10_CSI4_EN BIT(7) 215 #define ADV748X_IO_10_CSI1_EN BIT(6) 216 #define ADV748X_IO_10_PIX_OUT_EN BIT(5) 217 218 #define ADV748X_IO_CHIP_REV_ID_1 0xdf 219 #define ADV748X_IO_CHIP_REV_ID_2 0xe0 220 221 #define ADV748X_IO_SLAVE_ADDR_BASE 0xf2 222 223 /* HDMI RX Map */ 224 #define ADV748X_HDMI_LW1 0x07 /* line width_1 */ 225 #define ADV748X_HDMI_LW1_VERT_FILTER BIT(7) 226 #define ADV748X_HDMI_LW1_DE_REGEN BIT(5) 227 #define ADV748X_HDMI_LW1_WIDTH_MASK 0x1fff 228 229 #define ADV748X_HDMI_F0H1 0x09 /* field0 height_1 */ 230 #define ADV748X_HDMI_F0H1_HEIGHT_MASK 0x1fff 231 232 #define ADV748X_HDMI_F1H1 0x0b /* field1 height_1 */ 233 #define ADV748X_HDMI_F1H1_INTERLACED BIT(5) 234 235 #define ADV748X_HDMI_HFRONT_PORCH 0x20 /* hsync_front_porch_1 */ 236 #define ADV748X_HDMI_HFRONT_PORCH_MASK 0x1fff 237 238 #define ADV748X_HDMI_HSYNC_WIDTH 0x22 /* hsync_pulse_width_1 */ 239 #define ADV748X_HDMI_HSYNC_WIDTH_MASK 0x1fff 240 241 #define ADV748X_HDMI_HBACK_PORCH 0x24 /* hsync_back_porch_1 */ 242 #define ADV748X_HDMI_HBACK_PORCH_MASK 0x1fff 243 244 #define ADV748X_HDMI_VFRONT_PORCH 0x2a /* field0_vs_front_porch_1 */ 245 #define ADV748X_HDMI_VFRONT_PORCH_MASK 0x3fff 246 247 #define ADV748X_HDMI_VSYNC_WIDTH 0x2e /* field0_vs_pulse_width_1 */ 248 #define ADV748X_HDMI_VSYNC_WIDTH_MASK 0x3fff 249 250 #define ADV748X_HDMI_VBACK_PORCH 0x32 /* field0_vs_back_porch_1 */ 251 #define ADV748X_HDMI_VBACK_PORCH_MASK 0x3fff 252 253 #define ADV748X_HDMI_TMDS_1 0x51 /* hdmi_reg_51 */ 254 #define ADV748X_HDMI_TMDS_2 0x52 /* hdmi_reg_52 */ 255 256 /* HDMI RX Repeater Map */ 257 #define ADV748X_REPEATER_EDID_SZ 0x70 /* primary_edid_size */ 258 #define ADV748X_REPEATER_EDID_SZ_SHIFT 4 259 260 #define ADV748X_REPEATER_EDID_CTL 0x74 /* hdcp edid controls */ 261 #define ADV748X_REPEATER_EDID_CTL_EN BIT(0) /* man_edid_a_enable */ 262 263 /* SDP Main Map */ 264 #define ADV748X_SDP_INSEL 0x00 /* user_map_rw_reg_00 */ 265 266 #define ADV748X_SDP_VID_SEL 0x02 /* user_map_rw_reg_02 */ 267 #define ADV748X_SDP_VID_SEL_MASK 0xf0 268 #define ADV748X_SDP_VID_SEL_SHIFT 4 269 270 /* Contrast - Unsigned*/ 271 #define ADV748X_SDP_CON 0x08 /* user_map_rw_reg_08 */ 272 #define ADV748X_SDP_CON_MIN 0 273 #define ADV748X_SDP_CON_DEF 128 274 #define ADV748X_SDP_CON_MAX 255 275 276 /* Brightness - Signed */ 277 #define ADV748X_SDP_BRI 0x0a /* user_map_rw_reg_0a */ 278 #define ADV748X_SDP_BRI_MIN -128 279 #define ADV748X_SDP_BRI_DEF 0 280 #define ADV748X_SDP_BRI_MAX 127 281 282 /* Hue - Signed, inverted*/ 283 #define ADV748X_SDP_HUE 0x0b /* user_map_rw_reg_0b */ 284 #define ADV748X_SDP_HUE_MIN -127 285 #define ADV748X_SDP_HUE_DEF 0 286 #define ADV748X_SDP_HUE_MAX 128 287 288 /* Test Patterns / Default Values */ 289 #define ADV748X_SDP_DEF 0x0c /* user_map_rw_reg_0c */ 290 #define ADV748X_SDP_DEF_VAL_EN BIT(0) /* Force free run mode */ 291 #define ADV748X_SDP_DEF_VAL_AUTO_EN BIT(1) /* Free run when no signal */ 292 293 #define ADV748X_SDP_MAP_SEL 0x0e /* user_map_rw_reg_0e */ 294 #define ADV748X_SDP_MAP_SEL_RO_MAIN 1 295 296 /* Free run pattern select */ 297 #define ADV748X_SDP_FRP 0x14 298 #define ADV748X_SDP_FRP_MASK GENMASK(3, 1) 299 300 /* Saturation */ 301 #define ADV748X_SDP_SD_SAT_U 0xe3 /* user_map_rw_reg_e3 */ 302 #define ADV748X_SDP_SD_SAT_V 0xe4 /* user_map_rw_reg_e4 */ 303 #define ADV748X_SDP_SAT_MIN 0 304 #define ADV748X_SDP_SAT_DEF 128 305 #define ADV748X_SDP_SAT_MAX 255 306 307 /* SDP RO Main Map */ 308 #define ADV748X_SDP_RO_10 0x10 309 #define ADV748X_SDP_RO_10_IN_LOCK BIT(0) 310 311 /* CP Map */ 312 #define ADV748X_CP_PAT_GEN 0x37 /* int_pat_gen_1 */ 313 #define ADV748X_CP_PAT_GEN_EN BIT(7) 314 315 /* Contrast Control - Unsigned */ 316 #define ADV748X_CP_CON 0x3a /* contrast_cntrl */ 317 #define ADV748X_CP_CON_MIN 0 /* Minimum contrast */ 318 #define ADV748X_CP_CON_DEF 128 /* Default */ 319 #define ADV748X_CP_CON_MAX 255 /* Maximum contrast */ 320 321 /* Saturation Control - Unsigned */ 322 #define ADV748X_CP_SAT 0x3b /* saturation_cntrl */ 323 #define ADV748X_CP_SAT_MIN 0 /* Minimum saturation */ 324 #define ADV748X_CP_SAT_DEF 128 /* Default */ 325 #define ADV748X_CP_SAT_MAX 255 /* Maximum saturation */ 326 327 /* Brightness Control - Signed */ 328 #define ADV748X_CP_BRI 0x3c /* brightness_cntrl */ 329 #define ADV748X_CP_BRI_MIN -128 /* Luma is -512d */ 330 #define ADV748X_CP_BRI_DEF 0 /* Luma is 0 */ 331 #define ADV748X_CP_BRI_MAX 127 /* Luma is 508d */ 332 333 /* Hue Control */ 334 #define ADV748X_CP_HUE 0x3d /* hue_cntrl */ 335 #define ADV748X_CP_HUE_MIN 0 /* -90 degree */ 336 #define ADV748X_CP_HUE_DEF 0 /* -90 degree */ 337 #define ADV748X_CP_HUE_MAX 255 /* +90 degree */ 338 339 #define ADV748X_CP_VID_ADJ 0x3e /* vid_adj_0 */ 340 #define ADV748X_CP_VID_ADJ_ENABLE BIT(7) /* Enable colour controls */ 341 342 #define ADV748X_CP_DE_POS_HIGH 0x8b /* de_pos_adj_6 */ 343 #define ADV748X_CP_DE_POS_HIGH_SET BIT(6) 344 #define ADV748X_CP_DE_POS_END_LOW 0x8c /* de_pos_adj_7 */ 345 #define ADV748X_CP_DE_POS_START_LOW 0x8d /* de_pos_adj_8 */ 346 347 #define ADV748X_CP_VID_ADJ_2 0x91 348 #define ADV748X_CP_VID_ADJ_2_INTERLACED BIT(6) 349 #define ADV748X_CP_VID_ADJ_2_INTERLACED_3D BIT(4) 350 351 #define ADV748X_CP_CLMP_POS 0xc9 /* clmp_pos_cntrl_4 */ 352 #define ADV748X_CP_CLMP_POS_DIS_AUTO BIT(0) /* dis_auto_param_buff */ 353 354 /* CSI : TXA/TXB Maps */ 355 #define ADV748X_CSI_VC_REF 0x0d /* csi_tx_top_reg_0d */ 356 #define ADV748X_CSI_VC_REF_SHIFT 6 357 358 #define ADV748X_CSI_FS_AS_LS 0x1e /* csi_tx_top_reg_1e */ 359 #define ADV748X_CSI_FS_AS_LS_UNKNOWN BIT(6) /* Undocumented bit */ 360 361 /* Register handling */ 362 363 int adv748x_read(struct adv748x_state *state, u8 addr, u8 reg); 364 int adv748x_write(struct adv748x_state *state, u8 page, u8 reg, u8 value); 365 int adv748x_write_block(struct adv748x_state *state, int client_page, 366 unsigned int init_reg, const void *val, 367 size_t val_len); 368 369 #define io_read(s, r) adv748x_read(s, ADV748X_PAGE_IO, r) 370 #define io_write(s, r, v) adv748x_write(s, ADV748X_PAGE_IO, r, v) 371 #define io_clrset(s, r, m, v) io_write(s, r, (io_read(s, r) & ~m) | v) 372 373 #define hdmi_read(s, r) adv748x_read(s, ADV748X_PAGE_HDMI, r) 374 #define hdmi_read16(s, r, m) (((hdmi_read(s, r) << 8) | hdmi_read(s, r+1)) & m) 375 #define hdmi_write(s, r, v) adv748x_write(s, ADV748X_PAGE_HDMI, r, v) 376 377 #define repeater_read(s, r) adv748x_read(s, ADV748X_PAGE_REPEATER, r) 378 #define repeater_write(s, r, v) adv748x_write(s, ADV748X_PAGE_REPEATER, r, v) 379 380 #define sdp_read(s, r) adv748x_read(s, ADV748X_PAGE_SDP, r) 381 #define sdp_write(s, r, v) adv748x_write(s, ADV748X_PAGE_SDP, r, v) 382 #define sdp_clrset(s, r, m, v) sdp_write(s, r, (sdp_read(s, r) & ~m) | v) 383 384 #define cp_read(s, r) adv748x_read(s, ADV748X_PAGE_CP, r) 385 #define cp_write(s, r, v) adv748x_write(s, ADV748X_PAGE_CP, r, v) 386 #define cp_clrset(s, r, m, v) cp_write(s, r, (cp_read(s, r) & ~m) | v) 387 388 #define tx_read(t, r) adv748x_read(t->state, t->page, r) 389 #define tx_write(t, r, v) adv748x_write(t->state, t->page, r, v) 390 391 static inline struct v4l2_subdev *adv748x_get_remote_sd(struct media_pad *pad) 392 { 393 pad = media_entity_remote_pad(pad); 394 if (!pad) 395 return NULL; 396 397 return media_entity_to_v4l2_subdev(pad->entity); 398 } 399 400 void adv748x_subdev_init(struct v4l2_subdev *sd, struct adv748x_state *state, 401 const struct v4l2_subdev_ops *ops, u32 function, 402 const char *ident); 403 404 int adv748x_register_subdevs(struct adv748x_state *state, 405 struct v4l2_device *v4l2_dev); 406 407 int adv748x_tx_power(struct adv748x_csi2 *tx, bool on); 408 409 int adv748x_afe_init(struct adv748x_afe *afe); 410 void adv748x_afe_cleanup(struct adv748x_afe *afe); 411 412 int adv748x_csi2_init(struct adv748x_state *state, struct adv748x_csi2 *tx); 413 void adv748x_csi2_cleanup(struct adv748x_csi2 *tx); 414 int adv748x_csi2_set_pixelrate(struct v4l2_subdev *sd, s64 rate); 415 416 int adv748x_hdmi_init(struct adv748x_hdmi *hdmi); 417 void adv748x_hdmi_cleanup(struct adv748x_hdmi *hdmi); 418 419 #endif /* _ADV748X_H_ */ 420