1 /* 2 * Driver for Analog Devices ADV748X HDMI receiver with AFE 3 * 4 * Copyright (C) 2017 Renesas Electronics Corp. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the 8 * Free Software Foundation; either version 2 of the License, or (at your 9 * option) any later version. 10 * 11 * Authors: 12 * Koji Matsuoka <koji.matsuoka.xm@renesas.com> 13 * Niklas Söderlund <niklas.soderlund@ragnatech.se> 14 * Kieran Bingham <kieran.bingham@ideasonboard.com> 15 */ 16 17 #include <linux/delay.h> 18 #include <linux/errno.h> 19 #include <linux/i2c.h> 20 #include <linux/module.h> 21 #include <linux/mutex.h> 22 #include <linux/of_graph.h> 23 #include <linux/regmap.h> 24 #include <linux/slab.h> 25 #include <linux/v4l2-dv-timings.h> 26 27 #include <media/v4l2-ctrls.h> 28 #include <media/v4l2-device.h> 29 #include <media/v4l2-dv-timings.h> 30 #include <media/v4l2-ioctl.h> 31 32 #include "adv748x.h" 33 34 /* ----------------------------------------------------------------------------- 35 * Register manipulation 36 */ 37 38 static const struct regmap_config adv748x_regmap_cnf[] = { 39 { 40 .name = "io", 41 .reg_bits = 8, 42 .val_bits = 8, 43 44 .max_register = 0xff, 45 .cache_type = REGCACHE_NONE, 46 }, 47 { 48 .name = "dpll", 49 .reg_bits = 8, 50 .val_bits = 8, 51 52 .max_register = 0xff, 53 .cache_type = REGCACHE_NONE, 54 }, 55 { 56 .name = "cp", 57 .reg_bits = 8, 58 .val_bits = 8, 59 60 .max_register = 0xff, 61 .cache_type = REGCACHE_NONE, 62 }, 63 { 64 .name = "hdmi", 65 .reg_bits = 8, 66 .val_bits = 8, 67 68 .max_register = 0xff, 69 .cache_type = REGCACHE_NONE, 70 }, 71 { 72 .name = "edid", 73 .reg_bits = 8, 74 .val_bits = 8, 75 76 .max_register = 0xff, 77 .cache_type = REGCACHE_NONE, 78 }, 79 { 80 .name = "repeater", 81 .reg_bits = 8, 82 .val_bits = 8, 83 84 .max_register = 0xff, 85 .cache_type = REGCACHE_NONE, 86 }, 87 { 88 .name = "infoframe", 89 .reg_bits = 8, 90 .val_bits = 8, 91 92 .max_register = 0xff, 93 .cache_type = REGCACHE_NONE, 94 }, 95 { 96 .name = "cec", 97 .reg_bits = 8, 98 .val_bits = 8, 99 100 .max_register = 0xff, 101 .cache_type = REGCACHE_NONE, 102 }, 103 { 104 .name = "sdp", 105 .reg_bits = 8, 106 .val_bits = 8, 107 108 .max_register = 0xff, 109 .cache_type = REGCACHE_NONE, 110 }, 111 112 { 113 .name = "txb", 114 .reg_bits = 8, 115 .val_bits = 8, 116 117 .max_register = 0xff, 118 .cache_type = REGCACHE_NONE, 119 }, 120 { 121 .name = "txa", 122 .reg_bits = 8, 123 .val_bits = 8, 124 125 .max_register = 0xff, 126 .cache_type = REGCACHE_NONE, 127 }, 128 }; 129 130 static int adv748x_configure_regmap(struct adv748x_state *state, int region) 131 { 132 int err; 133 134 if (!state->i2c_clients[region]) 135 return -ENODEV; 136 137 state->regmap[region] = 138 devm_regmap_init_i2c(state->i2c_clients[region], 139 &adv748x_regmap_cnf[region]); 140 141 if (IS_ERR(state->regmap[region])) { 142 err = PTR_ERR(state->regmap[region]); 143 adv_err(state, 144 "Error initializing regmap %d with error %d\n", 145 region, err); 146 return -EINVAL; 147 } 148 149 return 0; 150 } 151 152 /* Default addresses for the I2C pages */ 153 static int adv748x_i2c_addresses[ADV748X_PAGE_MAX] = { 154 ADV748X_I2C_IO, 155 ADV748X_I2C_DPLL, 156 ADV748X_I2C_CP, 157 ADV748X_I2C_HDMI, 158 ADV748X_I2C_EDID, 159 ADV748X_I2C_REPEATER, 160 ADV748X_I2C_INFOFRAME, 161 ADV748X_I2C_CEC, 162 ADV748X_I2C_SDP, 163 ADV748X_I2C_TXB, 164 ADV748X_I2C_TXA, 165 }; 166 167 static int adv748x_read_check(struct adv748x_state *state, 168 int client_page, u8 reg) 169 { 170 struct i2c_client *client = state->i2c_clients[client_page]; 171 int err; 172 unsigned int val; 173 174 err = regmap_read(state->regmap[client_page], reg, &val); 175 176 if (err) { 177 adv_err(state, "error reading %02x, %02x\n", 178 client->addr, reg); 179 return err; 180 } 181 182 return val; 183 } 184 185 int adv748x_read(struct adv748x_state *state, u8 page, u8 reg) 186 { 187 return adv748x_read_check(state, page, reg); 188 } 189 190 int adv748x_write(struct adv748x_state *state, u8 page, u8 reg, u8 value) 191 { 192 return regmap_write(state->regmap[page], reg, value); 193 } 194 195 /* adv748x_write_block(): Write raw data with a maximum of I2C_SMBUS_BLOCK_MAX 196 * size to one or more registers. 197 * 198 * A value of zero will be returned on success, a negative errno will 199 * be returned in error cases. 200 */ 201 int adv748x_write_block(struct adv748x_state *state, int client_page, 202 unsigned int init_reg, const void *val, 203 size_t val_len) 204 { 205 struct regmap *regmap = state->regmap[client_page]; 206 207 if (val_len > I2C_SMBUS_BLOCK_MAX) 208 val_len = I2C_SMBUS_BLOCK_MAX; 209 210 return regmap_raw_write(regmap, init_reg, val, val_len); 211 } 212 213 static struct i2c_client *adv748x_dummy_client(struct adv748x_state *state, 214 u8 addr, u8 io_reg) 215 { 216 struct i2c_client *client = state->client; 217 218 if (addr) 219 io_write(state, io_reg, addr << 1); 220 221 return i2c_new_dummy(client->adapter, io_read(state, io_reg) >> 1); 222 } 223 224 static void adv748x_unregister_clients(struct adv748x_state *state) 225 { 226 unsigned int i; 227 228 for (i = 1; i < ARRAY_SIZE(state->i2c_clients); ++i) 229 i2c_unregister_device(state->i2c_clients[i]); 230 } 231 232 static int adv748x_initialise_clients(struct adv748x_state *state) 233 { 234 int i; 235 int ret; 236 237 for (i = ADV748X_PAGE_DPLL; i < ADV748X_PAGE_MAX; ++i) { 238 state->i2c_clients[i] = 239 adv748x_dummy_client(state, adv748x_i2c_addresses[i], 240 ADV748X_IO_SLAVE_ADDR_BASE + i); 241 if (state->i2c_clients[i] == NULL) { 242 adv_err(state, "failed to create i2c client %u\n", i); 243 return -ENOMEM; 244 } 245 246 ret = adv748x_configure_regmap(state, i); 247 if (ret) 248 return ret; 249 } 250 251 return 0; 252 } 253 254 /** 255 * struct adv748x_reg_value - Register write instruction 256 * @page: Regmap page identifier 257 * @reg: I2C register 258 * @value: value to write to @page at @reg 259 */ 260 struct adv748x_reg_value { 261 u8 page; 262 u8 reg; 263 u8 value; 264 }; 265 266 static int adv748x_write_regs(struct adv748x_state *state, 267 const struct adv748x_reg_value *regs) 268 { 269 int ret; 270 271 while (regs->page != ADV748X_PAGE_EOR) { 272 if (regs->page == ADV748X_PAGE_WAIT) { 273 msleep(regs->value); 274 } else { 275 ret = adv748x_write(state, regs->page, regs->reg, 276 regs->value); 277 if (ret < 0) { 278 adv_err(state, 279 "Error regs page: 0x%02x reg: 0x%02x\n", 280 regs->page, regs->reg); 281 return ret; 282 } 283 } 284 regs++; 285 } 286 287 return 0; 288 } 289 290 /* ----------------------------------------------------------------------------- 291 * TXA and TXB 292 */ 293 294 static const struct adv748x_reg_value adv748x_power_up_txa_4lane[] = { 295 296 {ADV748X_PAGE_TXA, 0x00, 0x84}, /* Enable 4-lane MIPI */ 297 {ADV748X_PAGE_TXA, 0x00, 0xa4}, /* Set Auto DPHY Timing */ 298 299 {ADV748X_PAGE_TXA, 0x31, 0x82}, /* ADI Required Write */ 300 {ADV748X_PAGE_TXA, 0x1e, 0x40}, /* ADI Required Write */ 301 {ADV748X_PAGE_TXA, 0xda, 0x01}, /* i2c_mipi_pll_en - 1'b1 */ 302 {ADV748X_PAGE_WAIT, 0x00, 0x02},/* delay 2 */ 303 {ADV748X_PAGE_TXA, 0x00, 0x24 },/* Power-up CSI-TX */ 304 {ADV748X_PAGE_WAIT, 0x00, 0x01},/* delay 1 */ 305 {ADV748X_PAGE_TXA, 0xc1, 0x2b}, /* ADI Required Write */ 306 {ADV748X_PAGE_WAIT, 0x00, 0x01},/* delay 1 */ 307 {ADV748X_PAGE_TXA, 0x31, 0x80}, /* ADI Required Write */ 308 309 {ADV748X_PAGE_EOR, 0xff, 0xff} /* End of register table */ 310 }; 311 312 static const struct adv748x_reg_value adv748x_power_down_txa_4lane[] = { 313 314 {ADV748X_PAGE_TXA, 0x31, 0x82}, /* ADI Required Write */ 315 {ADV748X_PAGE_TXA, 0x1e, 0x00}, /* ADI Required Write */ 316 {ADV748X_PAGE_TXA, 0x00, 0x84}, /* Enable 4-lane MIPI */ 317 {ADV748X_PAGE_TXA, 0xda, 0x01}, /* i2c_mipi_pll_en - 1'b1 */ 318 {ADV748X_PAGE_TXA, 0xc1, 0x3b}, /* ADI Required Write */ 319 320 {ADV748X_PAGE_EOR, 0xff, 0xff} /* End of register table */ 321 }; 322 323 static const struct adv748x_reg_value adv748x_power_up_txb_1lane[] = { 324 325 {ADV748X_PAGE_TXB, 0x00, 0x81}, /* Enable 1-lane MIPI */ 326 {ADV748X_PAGE_TXB, 0x00, 0xa1}, /* Set Auto DPHY Timing */ 327 328 {ADV748X_PAGE_TXB, 0x31, 0x82}, /* ADI Required Write */ 329 {ADV748X_PAGE_TXB, 0x1e, 0x40}, /* ADI Required Write */ 330 {ADV748X_PAGE_TXB, 0xda, 0x01}, /* i2c_mipi_pll_en - 1'b1 */ 331 {ADV748X_PAGE_WAIT, 0x00, 0x02},/* delay 2 */ 332 {ADV748X_PAGE_TXB, 0x00, 0x21 },/* Power-up CSI-TX */ 333 {ADV748X_PAGE_WAIT, 0x00, 0x01},/* delay 1 */ 334 {ADV748X_PAGE_TXB, 0xc1, 0x2b}, /* ADI Required Write */ 335 {ADV748X_PAGE_WAIT, 0x00, 0x01},/* delay 1 */ 336 {ADV748X_PAGE_TXB, 0x31, 0x80}, /* ADI Required Write */ 337 338 {ADV748X_PAGE_EOR, 0xff, 0xff} /* End of register table */ 339 }; 340 341 static const struct adv748x_reg_value adv748x_power_down_txb_1lane[] = { 342 343 {ADV748X_PAGE_TXB, 0x31, 0x82}, /* ADI Required Write */ 344 {ADV748X_PAGE_TXB, 0x1e, 0x00}, /* ADI Required Write */ 345 {ADV748X_PAGE_TXB, 0x00, 0x81}, /* Enable 4-lane MIPI */ 346 {ADV748X_PAGE_TXB, 0xda, 0x01}, /* i2c_mipi_pll_en - 1'b1 */ 347 {ADV748X_PAGE_TXB, 0xc1, 0x3b}, /* ADI Required Write */ 348 349 {ADV748X_PAGE_EOR, 0xff, 0xff} /* End of register table */ 350 }; 351 352 int adv748x_txa_power(struct adv748x_state *state, bool on) 353 { 354 int val; 355 356 val = txa_read(state, ADV748X_CSI_FS_AS_LS); 357 if (val < 0) 358 return val; 359 360 /* 361 * This test against BIT(6) is not documented by the datasheet, but was 362 * specified in the downstream driver. 363 * Track with a WARN_ONCE to determine if it is ever set by HW. 364 */ 365 WARN_ONCE((on && val & ADV748X_CSI_FS_AS_LS_UNKNOWN), 366 "Enabling with unknown bit set"); 367 368 if (on) 369 return adv748x_write_regs(state, adv748x_power_up_txa_4lane); 370 371 return adv748x_write_regs(state, adv748x_power_down_txa_4lane); 372 } 373 374 int adv748x_txb_power(struct adv748x_state *state, bool on) 375 { 376 int val; 377 378 val = txb_read(state, ADV748X_CSI_FS_AS_LS); 379 if (val < 0) 380 return val; 381 382 /* 383 * This test against BIT(6) is not documented by the datasheet, but was 384 * specified in the downstream driver. 385 * Track with a WARN_ONCE to determine if it is ever set by HW. 386 */ 387 WARN_ONCE((on && val & ADV748X_CSI_FS_AS_LS_UNKNOWN), 388 "Enabling with unknown bit set"); 389 390 if (on) 391 return adv748x_write_regs(state, adv748x_power_up_txb_1lane); 392 393 return adv748x_write_regs(state, adv748x_power_down_txb_1lane); 394 } 395 396 /* ----------------------------------------------------------------------------- 397 * Media Operations 398 */ 399 400 static const struct media_entity_operations adv748x_media_ops = { 401 .link_validate = v4l2_subdev_link_validate, 402 }; 403 404 /* ----------------------------------------------------------------------------- 405 * HW setup 406 */ 407 408 static const struct adv748x_reg_value adv748x_sw_reset[] = { 409 410 {ADV748X_PAGE_IO, 0xff, 0xff}, /* SW reset */ 411 {ADV748X_PAGE_WAIT, 0x00, 0x05},/* delay 5 */ 412 {ADV748X_PAGE_IO, 0x01, 0x76}, /* ADI Required Write */ 413 {ADV748X_PAGE_IO, 0xf2, 0x01}, /* Enable I2C Read Auto-Increment */ 414 {ADV748X_PAGE_EOR, 0xff, 0xff} /* End of register table */ 415 }; 416 417 static const struct adv748x_reg_value adv748x_set_slave_address[] = { 418 {ADV748X_PAGE_IO, 0xf3, ADV748X_I2C_DPLL << 1}, 419 {ADV748X_PAGE_IO, 0xf4, ADV748X_I2C_CP << 1}, 420 {ADV748X_PAGE_IO, 0xf5, ADV748X_I2C_HDMI << 1}, 421 {ADV748X_PAGE_IO, 0xf6, ADV748X_I2C_EDID << 1}, 422 {ADV748X_PAGE_IO, 0xf7, ADV748X_I2C_REPEATER << 1}, 423 {ADV748X_PAGE_IO, 0xf8, ADV748X_I2C_INFOFRAME << 1}, 424 {ADV748X_PAGE_IO, 0xfa, ADV748X_I2C_CEC << 1}, 425 {ADV748X_PAGE_IO, 0xfb, ADV748X_I2C_SDP << 1}, 426 {ADV748X_PAGE_IO, 0xfc, ADV748X_I2C_TXB << 1}, 427 {ADV748X_PAGE_IO, 0xfd, ADV748X_I2C_TXA << 1}, 428 {ADV748X_PAGE_EOR, 0xff, 0xff} /* End of register table */ 429 }; 430 431 /* Supported Formats For Script Below */ 432 /* - 01-29 HDMI to MIPI TxA CSI 4-Lane - RGB888: */ 433 static const struct adv748x_reg_value adv748x_init_txa_4lane[] = { 434 /* Disable chip powerdown & Enable HDMI Rx block */ 435 {ADV748X_PAGE_IO, 0x00, 0x40}, 436 437 {ADV748X_PAGE_REPEATER, 0x40, 0x83}, /* Enable HDCP 1.1 */ 438 439 {ADV748X_PAGE_HDMI, 0x00, 0x08},/* Foreground Channel = A */ 440 {ADV748X_PAGE_HDMI, 0x98, 0xff},/* ADI Required Write */ 441 {ADV748X_PAGE_HDMI, 0x99, 0xa3},/* ADI Required Write */ 442 {ADV748X_PAGE_HDMI, 0x9a, 0x00},/* ADI Required Write */ 443 {ADV748X_PAGE_HDMI, 0x9b, 0x0a},/* ADI Required Write */ 444 {ADV748X_PAGE_HDMI, 0x9d, 0x40},/* ADI Required Write */ 445 {ADV748X_PAGE_HDMI, 0xcb, 0x09},/* ADI Required Write */ 446 {ADV748X_PAGE_HDMI, 0x3d, 0x10},/* ADI Required Write */ 447 {ADV748X_PAGE_HDMI, 0x3e, 0x7b},/* ADI Required Write */ 448 {ADV748X_PAGE_HDMI, 0x3f, 0x5e},/* ADI Required Write */ 449 {ADV748X_PAGE_HDMI, 0x4e, 0xfe},/* ADI Required Write */ 450 {ADV748X_PAGE_HDMI, 0x4f, 0x18},/* ADI Required Write */ 451 {ADV748X_PAGE_HDMI, 0x57, 0xa3},/* ADI Required Write */ 452 {ADV748X_PAGE_HDMI, 0x58, 0x04},/* ADI Required Write */ 453 {ADV748X_PAGE_HDMI, 0x85, 0x10},/* ADI Required Write */ 454 455 {ADV748X_PAGE_HDMI, 0x83, 0x00},/* Enable All Terminations */ 456 {ADV748X_PAGE_HDMI, 0xa3, 0x01},/* ADI Required Write */ 457 {ADV748X_PAGE_HDMI, 0xbe, 0x00},/* ADI Required Write */ 458 459 {ADV748X_PAGE_HDMI, 0x6c, 0x01},/* HPA Manual Enable */ 460 {ADV748X_PAGE_HDMI, 0xf8, 0x01},/* HPA Asserted */ 461 {ADV748X_PAGE_HDMI, 0x0f, 0x00},/* Audio Mute Speed Set to Fastest */ 462 /* (Smallest Step Size) */ 463 464 {ADV748X_PAGE_IO, 0x04, 0x02}, /* RGB Out of CP */ 465 {ADV748X_PAGE_IO, 0x12, 0xf0}, /* CSC Depends on ip Packets, SDR 444 */ 466 {ADV748X_PAGE_IO, 0x17, 0x80}, /* Luma & Chroma can reach 254d */ 467 {ADV748X_PAGE_IO, 0x03, 0x86}, /* CP-Insert_AV_Code */ 468 469 {ADV748X_PAGE_CP, 0x7c, 0x00}, /* ADI Required Write */ 470 471 {ADV748X_PAGE_IO, 0x0c, 0xe0}, /* Enable LLC_DLL & Double LLC Timing */ 472 {ADV748X_PAGE_IO, 0x0e, 0xdd}, /* LLC/PIX/SPI PINS TRISTATED AUD */ 473 /* Outputs Enabled */ 474 {ADV748X_PAGE_IO, 0x10, 0xa0}, /* Enable 4-lane CSI Tx & Pixel Port */ 475 476 {ADV748X_PAGE_TXA, 0x00, 0x84}, /* Enable 4-lane MIPI */ 477 {ADV748X_PAGE_TXA, 0x00, 0xa4}, /* Set Auto DPHY Timing */ 478 {ADV748X_PAGE_TXA, 0xdb, 0x10}, /* ADI Required Write */ 479 {ADV748X_PAGE_TXA, 0xd6, 0x07}, /* ADI Required Write */ 480 {ADV748X_PAGE_TXA, 0xc4, 0x0a}, /* ADI Required Write */ 481 {ADV748X_PAGE_TXA, 0x71, 0x33}, /* ADI Required Write */ 482 {ADV748X_PAGE_TXA, 0x72, 0x11}, /* ADI Required Write */ 483 {ADV748X_PAGE_TXA, 0xf0, 0x00}, /* i2c_dphy_pwdn - 1'b0 */ 484 485 {ADV748X_PAGE_TXA, 0x31, 0x82}, /* ADI Required Write */ 486 {ADV748X_PAGE_TXA, 0x1e, 0x40}, /* ADI Required Write */ 487 {ADV748X_PAGE_TXA, 0xda, 0x01}, /* i2c_mipi_pll_en - 1'b1 */ 488 {ADV748X_PAGE_WAIT, 0x00, 0x02},/* delay 2 */ 489 {ADV748X_PAGE_TXA, 0x00, 0x24 },/* Power-up CSI-TX */ 490 {ADV748X_PAGE_WAIT, 0x00, 0x01},/* delay 1 */ 491 {ADV748X_PAGE_TXA, 0xc1, 0x2b}, /* ADI Required Write */ 492 {ADV748X_PAGE_WAIT, 0x00, 0x01},/* delay 1 */ 493 {ADV748X_PAGE_TXA, 0x31, 0x80}, /* ADI Required Write */ 494 495 {ADV748X_PAGE_EOR, 0xff, 0xff} /* End of register table */ 496 }; 497 498 /* 02-01 Analog CVBS to MIPI TX-B CSI 1-Lane - */ 499 /* Autodetect CVBS Single Ended In Ain 1 - MIPI Out */ 500 static const struct adv748x_reg_value adv748x_init_txb_1lane[] = { 501 502 {ADV748X_PAGE_IO, 0x00, 0x30}, /* Disable chip powerdown Rx */ 503 {ADV748X_PAGE_IO, 0xf2, 0x01}, /* Enable I2C Read Auto-Increment */ 504 505 {ADV748X_PAGE_IO, 0x0e, 0xff}, /* LLC/PIX/AUD/SPI PINS TRISTATED */ 506 507 {ADV748X_PAGE_SDP, 0x0f, 0x00}, /* Exit Power Down Mode */ 508 {ADV748X_PAGE_SDP, 0x52, 0xcd}, /* ADI Required Write */ 509 510 {ADV748X_PAGE_SDP, 0x0e, 0x80}, /* ADI Required Write */ 511 {ADV748X_PAGE_SDP, 0x9c, 0x00}, /* ADI Required Write */ 512 {ADV748X_PAGE_SDP, 0x9c, 0xff}, /* ADI Required Write */ 513 {ADV748X_PAGE_SDP, 0x0e, 0x00}, /* ADI Required Write */ 514 515 /* ADI recommended writes for improved video quality */ 516 {ADV748X_PAGE_SDP, 0x80, 0x51}, /* ADI Required Write */ 517 {ADV748X_PAGE_SDP, 0x81, 0x51}, /* ADI Required Write */ 518 {ADV748X_PAGE_SDP, 0x82, 0x68}, /* ADI Required Write */ 519 520 {ADV748X_PAGE_SDP, 0x03, 0x42}, /* Tri-S Output , PwrDwn 656 pads */ 521 {ADV748X_PAGE_SDP, 0x04, 0xb5}, /* ITU-R BT.656-4 compatible */ 522 {ADV748X_PAGE_SDP, 0x13, 0x00}, /* ADI Required Write */ 523 524 {ADV748X_PAGE_SDP, 0x17, 0x41}, /* Select SH1 */ 525 {ADV748X_PAGE_SDP, 0x31, 0x12}, /* ADI Required Write */ 526 {ADV748X_PAGE_SDP, 0xe6, 0x4f}, /* V bit end pos manually in NTSC */ 527 528 /* Enable 1-Lane MIPI Tx, */ 529 /* enable pixel output and route SD through Pixel port */ 530 {ADV748X_PAGE_IO, 0x10, 0x70}, 531 532 {ADV748X_PAGE_TXB, 0x00, 0x81}, /* Enable 1-lane MIPI */ 533 {ADV748X_PAGE_TXB, 0x00, 0xa1}, /* Set Auto DPHY Timing */ 534 {ADV748X_PAGE_TXB, 0xd2, 0x40}, /* ADI Required Write */ 535 {ADV748X_PAGE_TXB, 0xc4, 0x0a}, /* ADI Required Write */ 536 {ADV748X_PAGE_TXB, 0x71, 0x33}, /* ADI Required Write */ 537 {ADV748X_PAGE_TXB, 0x72, 0x11}, /* ADI Required Write */ 538 {ADV748X_PAGE_TXB, 0xf0, 0x00}, /* i2c_dphy_pwdn - 1'b0 */ 539 {ADV748X_PAGE_TXB, 0x31, 0x82}, /* ADI Required Write */ 540 {ADV748X_PAGE_TXB, 0x1e, 0x40}, /* ADI Required Write */ 541 {ADV748X_PAGE_TXB, 0xda, 0x01}, /* i2c_mipi_pll_en - 1'b1 */ 542 543 {ADV748X_PAGE_WAIT, 0x00, 0x02},/* delay 2 */ 544 {ADV748X_PAGE_TXB, 0x00, 0x21 },/* Power-up CSI-TX */ 545 {ADV748X_PAGE_WAIT, 0x00, 0x01},/* delay 1 */ 546 {ADV748X_PAGE_TXB, 0xc1, 0x2b}, /* ADI Required Write */ 547 {ADV748X_PAGE_WAIT, 0x00, 0x01},/* delay 1 */ 548 {ADV748X_PAGE_TXB, 0x31, 0x80}, /* ADI Required Write */ 549 550 {ADV748X_PAGE_EOR, 0xff, 0xff} /* End of register table */ 551 }; 552 553 static int adv748x_reset(struct adv748x_state *state) 554 { 555 int ret; 556 557 ret = adv748x_write_regs(state, adv748x_sw_reset); 558 if (ret < 0) 559 return ret; 560 561 ret = adv748x_write_regs(state, adv748x_set_slave_address); 562 if (ret < 0) 563 return ret; 564 565 /* Init and power down TXA */ 566 ret = adv748x_write_regs(state, adv748x_init_txa_4lane); 567 if (ret) 568 return ret; 569 570 adv748x_txa_power(state, 0); 571 572 /* Init and power down TXB */ 573 ret = adv748x_write_regs(state, adv748x_init_txb_1lane); 574 if (ret) 575 return ret; 576 577 adv748x_txb_power(state, 0); 578 579 /* Disable chip powerdown & Enable HDMI Rx block */ 580 io_write(state, ADV748X_IO_PD, ADV748X_IO_PD_RX_EN); 581 582 /* Enable 4-lane CSI Tx & Pixel Port */ 583 io_write(state, ADV748X_IO_10, ADV748X_IO_10_CSI4_EN | 584 ADV748X_IO_10_CSI1_EN | 585 ADV748X_IO_10_PIX_OUT_EN); 586 587 /* Use vid_std and v_freq as freerun resolution for CP */ 588 cp_clrset(state, ADV748X_CP_CLMP_POS, ADV748X_CP_CLMP_POS_DIS_AUTO, 589 ADV748X_CP_CLMP_POS_DIS_AUTO); 590 591 return 0; 592 } 593 594 static int adv748x_identify_chip(struct adv748x_state *state) 595 { 596 int msb, lsb; 597 598 lsb = io_read(state, ADV748X_IO_CHIP_REV_ID_1); 599 msb = io_read(state, ADV748X_IO_CHIP_REV_ID_2); 600 601 if (lsb < 0 || msb < 0) { 602 adv_err(state, "Failed to read chip revision\n"); 603 return -EIO; 604 } 605 606 adv_info(state, "chip found @ 0x%02x revision %02x%02x\n", 607 state->client->addr << 1, lsb, msb); 608 609 return 0; 610 } 611 612 /* ----------------------------------------------------------------------------- 613 * i2c driver 614 */ 615 616 void adv748x_subdev_init(struct v4l2_subdev *sd, struct adv748x_state *state, 617 const struct v4l2_subdev_ops *ops, u32 function, 618 const char *ident) 619 { 620 v4l2_subdev_init(sd, ops); 621 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; 622 623 /* the owner is the same as the i2c_client's driver owner */ 624 sd->owner = state->dev->driver->owner; 625 sd->dev = state->dev; 626 627 v4l2_set_subdevdata(sd, state); 628 629 /* initialize name */ 630 snprintf(sd->name, sizeof(sd->name), "%s %d-%04x %s", 631 state->dev->driver->name, 632 i2c_adapter_id(state->client->adapter), 633 state->client->addr, ident); 634 635 sd->entity.function = function; 636 sd->entity.ops = &adv748x_media_ops; 637 } 638 639 static int adv748x_parse_dt(struct adv748x_state *state) 640 { 641 struct device_node *ep_np = NULL; 642 struct of_endpoint ep; 643 bool found = false; 644 645 for_each_endpoint_of_node(state->dev->of_node, ep_np) { 646 of_graph_parse_endpoint(ep_np, &ep); 647 adv_info(state, "Endpoint %pOF on port %d", ep.local_node, 648 ep.port); 649 650 if (ep.port >= ADV748X_PORT_MAX) { 651 adv_err(state, "Invalid endpoint %pOF on port %d", 652 ep.local_node, ep.port); 653 654 continue; 655 } 656 657 if (state->endpoints[ep.port]) { 658 adv_err(state, 659 "Multiple port endpoints are not supported"); 660 continue; 661 } 662 663 of_node_get(ep_np); 664 state->endpoints[ep.port] = ep_np; 665 666 found = true; 667 } 668 669 return found ? 0 : -ENODEV; 670 } 671 672 static void adv748x_dt_cleanup(struct adv748x_state *state) 673 { 674 unsigned int i; 675 676 for (i = 0; i < ADV748X_PORT_MAX; i++) 677 of_node_put(state->endpoints[i]); 678 } 679 680 static int adv748x_probe(struct i2c_client *client, 681 const struct i2c_device_id *id) 682 { 683 struct adv748x_state *state; 684 int ret; 685 686 /* Check if the adapter supports the needed features */ 687 if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA)) 688 return -EIO; 689 690 state = kzalloc(sizeof(struct adv748x_state), GFP_KERNEL); 691 if (!state) 692 return -ENOMEM; 693 694 mutex_init(&state->mutex); 695 696 state->dev = &client->dev; 697 state->client = client; 698 state->i2c_clients[ADV748X_PAGE_IO] = client; 699 i2c_set_clientdata(client, state); 700 701 /* Discover and process ports declared by the Device tree endpoints */ 702 ret = adv748x_parse_dt(state); 703 if (ret) { 704 adv_err(state, "Failed to parse device tree"); 705 goto err_free_mutex; 706 } 707 708 /* Configure IO Regmap region */ 709 ret = adv748x_configure_regmap(state, ADV748X_PAGE_IO); 710 if (ret) { 711 adv_err(state, "Error configuring IO regmap region"); 712 goto err_cleanup_dt; 713 } 714 715 ret = adv748x_identify_chip(state); 716 if (ret) { 717 adv_err(state, "Failed to identify chip"); 718 goto err_cleanup_clients; 719 } 720 721 /* Configure remaining pages as I2C clients with regmap access */ 722 ret = adv748x_initialise_clients(state); 723 if (ret) { 724 adv_err(state, "Failed to setup client regmap pages"); 725 goto err_cleanup_clients; 726 } 727 728 /* SW reset ADV748X to its default values */ 729 ret = adv748x_reset(state); 730 if (ret) { 731 adv_err(state, "Failed to reset hardware"); 732 goto err_cleanup_clients; 733 } 734 735 /* Initialise HDMI */ 736 ret = adv748x_hdmi_init(&state->hdmi); 737 if (ret) { 738 adv_err(state, "Failed to probe HDMI"); 739 goto err_cleanup_clients; 740 } 741 742 /* Initialise AFE */ 743 ret = adv748x_afe_init(&state->afe); 744 if (ret) { 745 adv_err(state, "Failed to probe AFE"); 746 goto err_cleanup_hdmi; 747 } 748 749 /* Initialise TXA */ 750 ret = adv748x_csi2_init(state, &state->txa); 751 if (ret) { 752 adv_err(state, "Failed to probe TXA"); 753 goto err_cleanup_afe; 754 } 755 756 /* Initialise TXB */ 757 ret = adv748x_csi2_init(state, &state->txb); 758 if (ret) { 759 adv_err(state, "Failed to probe TXB"); 760 goto err_cleanup_txa; 761 } 762 763 return 0; 764 765 err_cleanup_txa: 766 adv748x_csi2_cleanup(&state->txa); 767 err_cleanup_afe: 768 adv748x_afe_cleanup(&state->afe); 769 err_cleanup_hdmi: 770 adv748x_hdmi_cleanup(&state->hdmi); 771 err_cleanup_clients: 772 adv748x_unregister_clients(state); 773 err_cleanup_dt: 774 adv748x_dt_cleanup(state); 775 err_free_mutex: 776 mutex_destroy(&state->mutex); 777 kfree(state); 778 779 return ret; 780 } 781 782 static int adv748x_remove(struct i2c_client *client) 783 { 784 struct adv748x_state *state = i2c_get_clientdata(client); 785 786 adv748x_afe_cleanup(&state->afe); 787 adv748x_hdmi_cleanup(&state->hdmi); 788 789 adv748x_csi2_cleanup(&state->txa); 790 adv748x_csi2_cleanup(&state->txb); 791 792 adv748x_unregister_clients(state); 793 adv748x_dt_cleanup(state); 794 mutex_destroy(&state->mutex); 795 796 kfree(state); 797 798 return 0; 799 } 800 801 static const struct i2c_device_id adv748x_id[] = { 802 { "adv7481", 0 }, 803 { "adv7482", 0 }, 804 { }, 805 }; 806 MODULE_DEVICE_TABLE(i2c, adv748x_id); 807 808 static const struct of_device_id adv748x_of_table[] = { 809 { .compatible = "adi,adv7481", }, 810 { .compatible = "adi,adv7482", }, 811 { } 812 }; 813 MODULE_DEVICE_TABLE(of, adv748x_of_table); 814 815 static struct i2c_driver adv748x_driver = { 816 .driver = { 817 .name = "adv748x", 818 .of_match_table = adv748x_of_table, 819 }, 820 .probe = adv748x_probe, 821 .remove = adv748x_remove, 822 .id_table = adv748x_id, 823 }; 824 825 module_i2c_driver(adv748x_driver); 826 827 MODULE_AUTHOR("Kieran Bingham <kieran.bingham@ideasonboard.com>"); 828 MODULE_DESCRIPTION("ADV748X video decoder"); 829 MODULE_LICENSE("GPL v2"); 830