xref: /openbmc/linux/drivers/media/i2c/adv7393.c (revision aaeb31c0)
1cb7a01acSMauro Carvalho Chehab /*
2cb7a01acSMauro Carvalho Chehab  * adv7393 - ADV7393 Video Encoder Driver
3cb7a01acSMauro Carvalho Chehab  *
4cb7a01acSMauro Carvalho Chehab  * The encoder hardware does not support SECAM.
5cb7a01acSMauro Carvalho Chehab  *
6cb7a01acSMauro Carvalho Chehab  * Copyright (C) 2010-2012 ADVANSEE - http://www.advansee.com/
7cb7a01acSMauro Carvalho Chehab  * Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
8cb7a01acSMauro Carvalho Chehab  *
9cb7a01acSMauro Carvalho Chehab  * Based on ADV7343 driver,
10cb7a01acSMauro Carvalho Chehab  *
11cb7a01acSMauro Carvalho Chehab  * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
12cb7a01acSMauro Carvalho Chehab  *
13cb7a01acSMauro Carvalho Chehab  * This program is free software; you can redistribute it and/or
14cb7a01acSMauro Carvalho Chehab  * modify it under the terms of the GNU General Public License as
15cb7a01acSMauro Carvalho Chehab  * published by the Free Software Foundation version 2.
16cb7a01acSMauro Carvalho Chehab  *
17cb7a01acSMauro Carvalho Chehab  * This program is distributed .as is. WITHOUT ANY WARRANTY of any
18cb7a01acSMauro Carvalho Chehab  * kind, whether express or implied; without even the implied warranty
19cb7a01acSMauro Carvalho Chehab  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
20cb7a01acSMauro Carvalho Chehab  * GNU General Public License for more details.
21cb7a01acSMauro Carvalho Chehab  */
22cb7a01acSMauro Carvalho Chehab 
23cb7a01acSMauro Carvalho Chehab #include <linux/kernel.h>
24cb7a01acSMauro Carvalho Chehab #include <linux/init.h>
25cb7a01acSMauro Carvalho Chehab #include <linux/ctype.h>
26cb7a01acSMauro Carvalho Chehab #include <linux/slab.h>
27cb7a01acSMauro Carvalho Chehab #include <linux/i2c.h>
28cb7a01acSMauro Carvalho Chehab #include <linux/device.h>
29cb7a01acSMauro Carvalho Chehab #include <linux/delay.h>
30cb7a01acSMauro Carvalho Chehab #include <linux/module.h>
31cb7a01acSMauro Carvalho Chehab #include <linux/videodev2.h>
32cb7a01acSMauro Carvalho Chehab #include <linux/uaccess.h>
33cb7a01acSMauro Carvalho Chehab 
34b5dcee22SMauro Carvalho Chehab #include <media/i2c/adv7393.h>
35cb7a01acSMauro Carvalho Chehab #include <media/v4l2-device.h>
36cb7a01acSMauro Carvalho Chehab #include <media/v4l2-ctrls.h>
37cb7a01acSMauro Carvalho Chehab 
38cb7a01acSMauro Carvalho Chehab #include "adv7393_regs.h"
39cb7a01acSMauro Carvalho Chehab 
40cb7a01acSMauro Carvalho Chehab MODULE_DESCRIPTION("ADV7393 video encoder driver");
41cb7a01acSMauro Carvalho Chehab MODULE_LICENSE("GPL");
42cb7a01acSMauro Carvalho Chehab 
43cb7a01acSMauro Carvalho Chehab static bool debug;
44cb7a01acSMauro Carvalho Chehab module_param(debug, bool, 0644);
45cb7a01acSMauro Carvalho Chehab MODULE_PARM_DESC(debug, "Debug level 0-1");
46cb7a01acSMauro Carvalho Chehab 
47cb7a01acSMauro Carvalho Chehab struct adv7393_state {
48cb7a01acSMauro Carvalho Chehab 	struct v4l2_subdev sd;
49cb7a01acSMauro Carvalho Chehab 	struct v4l2_ctrl_handler hdl;
50cb7a01acSMauro Carvalho Chehab 	u8 reg00;
51cb7a01acSMauro Carvalho Chehab 	u8 reg01;
52cb7a01acSMauro Carvalho Chehab 	u8 reg02;
53cb7a01acSMauro Carvalho Chehab 	u8 reg35;
54cb7a01acSMauro Carvalho Chehab 	u8 reg80;
55cb7a01acSMauro Carvalho Chehab 	u8 reg82;
56cb7a01acSMauro Carvalho Chehab 	u32 output;
57cb7a01acSMauro Carvalho Chehab 	v4l2_std_id std;
58cb7a01acSMauro Carvalho Chehab };
59cb7a01acSMauro Carvalho Chehab 
to_state(struct v4l2_subdev * sd)60cb7a01acSMauro Carvalho Chehab static inline struct adv7393_state *to_state(struct v4l2_subdev *sd)
61cb7a01acSMauro Carvalho Chehab {
62cb7a01acSMauro Carvalho Chehab 	return container_of(sd, struct adv7393_state, sd);
63cb7a01acSMauro Carvalho Chehab }
64cb7a01acSMauro Carvalho Chehab 
to_sd(struct v4l2_ctrl * ctrl)65cb7a01acSMauro Carvalho Chehab static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
66cb7a01acSMauro Carvalho Chehab {
67cb7a01acSMauro Carvalho Chehab 	return &container_of(ctrl->handler, struct adv7393_state, hdl)->sd;
68cb7a01acSMauro Carvalho Chehab }
69cb7a01acSMauro Carvalho Chehab 
adv7393_write(struct v4l2_subdev * sd,u8 reg,u8 value)70cb7a01acSMauro Carvalho Chehab static inline int adv7393_write(struct v4l2_subdev *sd, u8 reg, u8 value)
71cb7a01acSMauro Carvalho Chehab {
72cb7a01acSMauro Carvalho Chehab 	struct i2c_client *client = v4l2_get_subdevdata(sd);
73cb7a01acSMauro Carvalho Chehab 
74cb7a01acSMauro Carvalho Chehab 	return i2c_smbus_write_byte_data(client, reg, value);
75cb7a01acSMauro Carvalho Chehab }
76cb7a01acSMauro Carvalho Chehab 
77cb7a01acSMauro Carvalho Chehab static const u8 adv7393_init_reg_val[] = {
78cb7a01acSMauro Carvalho Chehab 	ADV7393_SOFT_RESET, ADV7393_SOFT_RESET_DEFAULT,
79cb7a01acSMauro Carvalho Chehab 	ADV7393_POWER_MODE_REG, ADV7393_POWER_MODE_REG_DEFAULT,
80cb7a01acSMauro Carvalho Chehab 
81cb7a01acSMauro Carvalho Chehab 	ADV7393_HD_MODE_REG1, ADV7393_HD_MODE_REG1_DEFAULT,
82cb7a01acSMauro Carvalho Chehab 	ADV7393_HD_MODE_REG2, ADV7393_HD_MODE_REG2_DEFAULT,
83cb7a01acSMauro Carvalho Chehab 	ADV7393_HD_MODE_REG3, ADV7393_HD_MODE_REG3_DEFAULT,
84cb7a01acSMauro Carvalho Chehab 	ADV7393_HD_MODE_REG4, ADV7393_HD_MODE_REG4_DEFAULT,
85cb7a01acSMauro Carvalho Chehab 	ADV7393_HD_MODE_REG5, ADV7393_HD_MODE_REG5_DEFAULT,
86cb7a01acSMauro Carvalho Chehab 	ADV7393_HD_MODE_REG6, ADV7393_HD_MODE_REG6_DEFAULT,
87cb7a01acSMauro Carvalho Chehab 	ADV7393_HD_MODE_REG7, ADV7393_HD_MODE_REG7_DEFAULT,
88cb7a01acSMauro Carvalho Chehab 
89cb7a01acSMauro Carvalho Chehab 	ADV7393_SD_MODE_REG1, ADV7393_SD_MODE_REG1_DEFAULT,
90cb7a01acSMauro Carvalho Chehab 	ADV7393_SD_MODE_REG2, ADV7393_SD_MODE_REG2_DEFAULT,
91cb7a01acSMauro Carvalho Chehab 	ADV7393_SD_MODE_REG3, ADV7393_SD_MODE_REG3_DEFAULT,
92cb7a01acSMauro Carvalho Chehab 	ADV7393_SD_MODE_REG4, ADV7393_SD_MODE_REG4_DEFAULT,
93cb7a01acSMauro Carvalho Chehab 	ADV7393_SD_MODE_REG5, ADV7393_SD_MODE_REG5_DEFAULT,
94cb7a01acSMauro Carvalho Chehab 	ADV7393_SD_MODE_REG6, ADV7393_SD_MODE_REG6_DEFAULT,
95cb7a01acSMauro Carvalho Chehab 	ADV7393_SD_MODE_REG7, ADV7393_SD_MODE_REG7_DEFAULT,
96cb7a01acSMauro Carvalho Chehab 	ADV7393_SD_MODE_REG8, ADV7393_SD_MODE_REG8_DEFAULT,
97cb7a01acSMauro Carvalho Chehab 
98cb7a01acSMauro Carvalho Chehab 	ADV7393_SD_TIMING_REG0, ADV7393_SD_TIMING_REG0_DEFAULT,
99cb7a01acSMauro Carvalho Chehab 
100cb7a01acSMauro Carvalho Chehab 	ADV7393_SD_HUE_ADJUST, ADV7393_SD_HUE_ADJUST_DEFAULT,
101cb7a01acSMauro Carvalho Chehab 	ADV7393_SD_CGMS_WSS0, ADV7393_SD_CGMS_WSS0_DEFAULT,
102cb7a01acSMauro Carvalho Chehab 	ADV7393_SD_BRIGHTNESS_WSS, ADV7393_SD_BRIGHTNESS_WSS_DEFAULT,
103cb7a01acSMauro Carvalho Chehab };
104cb7a01acSMauro Carvalho Chehab 
105cb7a01acSMauro Carvalho Chehab /*
106cb7a01acSMauro Carvalho Chehab  *			    2^32
107cb7a01acSMauro Carvalho Chehab  * FSC(reg) =  FSC (HZ) * --------
108cb7a01acSMauro Carvalho Chehab  *			  27000000
109cb7a01acSMauro Carvalho Chehab  */
110cb7a01acSMauro Carvalho Chehab static const struct adv7393_std_info stdinfo[] = {
111cb7a01acSMauro Carvalho Chehab 	{
112cb7a01acSMauro Carvalho Chehab 		/* FSC(Hz) = 4,433,618.75 Hz */
113cb7a01acSMauro Carvalho Chehab 		SD_STD_NTSC, 705268427, V4L2_STD_NTSC_443,
114cb7a01acSMauro Carvalho Chehab 	}, {
115cb7a01acSMauro Carvalho Chehab 		/* FSC(Hz) = 3,579,545.45 Hz */
116cb7a01acSMauro Carvalho Chehab 		SD_STD_NTSC, 569408542, V4L2_STD_NTSC,
117cb7a01acSMauro Carvalho Chehab 	}, {
118cb7a01acSMauro Carvalho Chehab 		/* FSC(Hz) = 3,575,611.00 Hz */
119cb7a01acSMauro Carvalho Chehab 		SD_STD_PAL_M, 568782678, V4L2_STD_PAL_M,
120cb7a01acSMauro Carvalho Chehab 	}, {
121cb7a01acSMauro Carvalho Chehab 		/* FSC(Hz) = 3,582,056.00 Hz */
122cb7a01acSMauro Carvalho Chehab 		SD_STD_PAL_N, 569807903, V4L2_STD_PAL_Nc,
123cb7a01acSMauro Carvalho Chehab 	}, {
124cb7a01acSMauro Carvalho Chehab 		/* FSC(Hz) = 4,433,618.75 Hz */
125cb7a01acSMauro Carvalho Chehab 		SD_STD_PAL_N, 705268427, V4L2_STD_PAL_N,
126cb7a01acSMauro Carvalho Chehab 	}, {
127cb7a01acSMauro Carvalho Chehab 		/* FSC(Hz) = 4,433,618.75 Hz */
128cb7a01acSMauro Carvalho Chehab 		SD_STD_PAL_M, 705268427, V4L2_STD_PAL_60,
129cb7a01acSMauro Carvalho Chehab 	}, {
130cb7a01acSMauro Carvalho Chehab 		/* FSC(Hz) = 4,433,618.75 Hz */
131cb7a01acSMauro Carvalho Chehab 		SD_STD_PAL_BDGHI, 705268427, V4L2_STD_PAL,
132cb7a01acSMauro Carvalho Chehab 	},
133cb7a01acSMauro Carvalho Chehab };
134cb7a01acSMauro Carvalho Chehab 
adv7393_setstd(struct v4l2_subdev * sd,v4l2_std_id std)135cb7a01acSMauro Carvalho Chehab static int adv7393_setstd(struct v4l2_subdev *sd, v4l2_std_id std)
136cb7a01acSMauro Carvalho Chehab {
137cb7a01acSMauro Carvalho Chehab 	struct adv7393_state *state = to_state(sd);
138cb7a01acSMauro Carvalho Chehab 	const struct adv7393_std_info *std_info;
139cb7a01acSMauro Carvalho Chehab 	int num_std;
140cb7a01acSMauro Carvalho Chehab 	u8 reg;
141cb7a01acSMauro Carvalho Chehab 	u32 val;
142cb7a01acSMauro Carvalho Chehab 	int err = 0;
143cb7a01acSMauro Carvalho Chehab 	int i;
144cb7a01acSMauro Carvalho Chehab 
145cb7a01acSMauro Carvalho Chehab 	num_std = ARRAY_SIZE(stdinfo);
146cb7a01acSMauro Carvalho Chehab 
147cb7a01acSMauro Carvalho Chehab 	for (i = 0; i < num_std; i++) {
148cb7a01acSMauro Carvalho Chehab 		if (stdinfo[i].stdid & std)
149cb7a01acSMauro Carvalho Chehab 			break;
150cb7a01acSMauro Carvalho Chehab 	}
151cb7a01acSMauro Carvalho Chehab 
152cb7a01acSMauro Carvalho Chehab 	if (i == num_std) {
153cb7a01acSMauro Carvalho Chehab 		v4l2_dbg(1, debug, sd,
154cb7a01acSMauro Carvalho Chehab 				"Invalid std or std is not supported: %llx\n",
155cb7a01acSMauro Carvalho Chehab 						(unsigned long long)std);
156cb7a01acSMauro Carvalho Chehab 		return -EINVAL;
157cb7a01acSMauro Carvalho Chehab 	}
158cb7a01acSMauro Carvalho Chehab 
159cb7a01acSMauro Carvalho Chehab 	std_info = &stdinfo[i];
160cb7a01acSMauro Carvalho Chehab 
161cb7a01acSMauro Carvalho Chehab 	/* Set the standard */
162cb7a01acSMauro Carvalho Chehab 	val = state->reg80 & ~SD_STD_MASK;
163cb7a01acSMauro Carvalho Chehab 	val |= std_info->standard_val3;
164cb7a01acSMauro Carvalho Chehab 	err = adv7393_write(sd, ADV7393_SD_MODE_REG1, val);
165cb7a01acSMauro Carvalho Chehab 	if (err < 0)
166cb7a01acSMauro Carvalho Chehab 		goto setstd_exit;
167cb7a01acSMauro Carvalho Chehab 
168cb7a01acSMauro Carvalho Chehab 	state->reg80 = val;
169cb7a01acSMauro Carvalho Chehab 
170cb7a01acSMauro Carvalho Chehab 	/* Configure the input mode register */
171cb7a01acSMauro Carvalho Chehab 	val = state->reg01 & ~INPUT_MODE_MASK;
172cb7a01acSMauro Carvalho Chehab 	val |= SD_INPUT_MODE;
173cb7a01acSMauro Carvalho Chehab 	err = adv7393_write(sd, ADV7393_MODE_SELECT_REG, val);
174cb7a01acSMauro Carvalho Chehab 	if (err < 0)
175cb7a01acSMauro Carvalho Chehab 		goto setstd_exit;
176cb7a01acSMauro Carvalho Chehab 
177cb7a01acSMauro Carvalho Chehab 	state->reg01 = val;
178cb7a01acSMauro Carvalho Chehab 
179cb7a01acSMauro Carvalho Chehab 	/* Program the sub carrier frequency registers */
180cb7a01acSMauro Carvalho Chehab 	val = std_info->fsc_val;
181cb7a01acSMauro Carvalho Chehab 	for (reg = ADV7393_FSC_REG0; reg <= ADV7393_FSC_REG3; reg++) {
182cb7a01acSMauro Carvalho Chehab 		err = adv7393_write(sd, reg, val);
183cb7a01acSMauro Carvalho Chehab 		if (err < 0)
184cb7a01acSMauro Carvalho Chehab 			goto setstd_exit;
185cb7a01acSMauro Carvalho Chehab 		val >>= 8;
186cb7a01acSMauro Carvalho Chehab 	}
187cb7a01acSMauro Carvalho Chehab 
188cb7a01acSMauro Carvalho Chehab 	val = state->reg82;
189cb7a01acSMauro Carvalho Chehab 
190cb7a01acSMauro Carvalho Chehab 	/* Pedestal settings */
191cb7a01acSMauro Carvalho Chehab 	if (std & (V4L2_STD_NTSC | V4L2_STD_NTSC_443))
192cb7a01acSMauro Carvalho Chehab 		val |= SD_PEDESTAL_EN;
193cb7a01acSMauro Carvalho Chehab 	else
194cb7a01acSMauro Carvalho Chehab 		val &= SD_PEDESTAL_DI;
195cb7a01acSMauro Carvalho Chehab 
196cb7a01acSMauro Carvalho Chehab 	err = adv7393_write(sd, ADV7393_SD_MODE_REG2, val);
197cb7a01acSMauro Carvalho Chehab 	if (err < 0)
198cb7a01acSMauro Carvalho Chehab 		goto setstd_exit;
199cb7a01acSMauro Carvalho Chehab 
200cb7a01acSMauro Carvalho Chehab 	state->reg82 = val;
201cb7a01acSMauro Carvalho Chehab 
202cb7a01acSMauro Carvalho Chehab setstd_exit:
203cb7a01acSMauro Carvalho Chehab 	if (err != 0)
204cb7a01acSMauro Carvalho Chehab 		v4l2_err(sd, "Error setting std, write failed\n");
205cb7a01acSMauro Carvalho Chehab 
206cb7a01acSMauro Carvalho Chehab 	return err;
207cb7a01acSMauro Carvalho Chehab }
208cb7a01acSMauro Carvalho Chehab 
adv7393_setoutput(struct v4l2_subdev * sd,u32 output_type)209cb7a01acSMauro Carvalho Chehab static int adv7393_setoutput(struct v4l2_subdev *sd, u32 output_type)
210cb7a01acSMauro Carvalho Chehab {
211cb7a01acSMauro Carvalho Chehab 	struct adv7393_state *state = to_state(sd);
212cb7a01acSMauro Carvalho Chehab 	u8 val;
213cb7a01acSMauro Carvalho Chehab 	int err = 0;
214cb7a01acSMauro Carvalho Chehab 
215cb7a01acSMauro Carvalho Chehab 	if (output_type > ADV7393_SVIDEO_ID) {
216cb7a01acSMauro Carvalho Chehab 		v4l2_dbg(1, debug, sd,
217cb7a01acSMauro Carvalho Chehab 			"Invalid output type or output type not supported:%d\n",
218cb7a01acSMauro Carvalho Chehab 								output_type);
219cb7a01acSMauro Carvalho Chehab 		return -EINVAL;
220cb7a01acSMauro Carvalho Chehab 	}
221cb7a01acSMauro Carvalho Chehab 
222cb7a01acSMauro Carvalho Chehab 	/* Enable Appropriate DAC */
223cb7a01acSMauro Carvalho Chehab 	val = state->reg00 & 0x03;
224cb7a01acSMauro Carvalho Chehab 
225cb7a01acSMauro Carvalho Chehab 	if (output_type == ADV7393_COMPOSITE_ID)
226cb7a01acSMauro Carvalho Chehab 		val |= ADV7393_COMPOSITE_POWER_VALUE;
227cb7a01acSMauro Carvalho Chehab 	else if (output_type == ADV7393_COMPONENT_ID)
228cb7a01acSMauro Carvalho Chehab 		val |= ADV7393_COMPONENT_POWER_VALUE;
229cb7a01acSMauro Carvalho Chehab 	else
230cb7a01acSMauro Carvalho Chehab 		val |= ADV7393_SVIDEO_POWER_VALUE;
231cb7a01acSMauro Carvalho Chehab 
232cb7a01acSMauro Carvalho Chehab 	err = adv7393_write(sd, ADV7393_POWER_MODE_REG, val);
233cb7a01acSMauro Carvalho Chehab 	if (err < 0)
234cb7a01acSMauro Carvalho Chehab 		goto setoutput_exit;
235cb7a01acSMauro Carvalho Chehab 
236cb7a01acSMauro Carvalho Chehab 	state->reg00 = val;
237cb7a01acSMauro Carvalho Chehab 
238cb7a01acSMauro Carvalho Chehab 	/* Enable YUV output */
239cb7a01acSMauro Carvalho Chehab 	val = state->reg02 | YUV_OUTPUT_SELECT;
240cb7a01acSMauro Carvalho Chehab 	err = adv7393_write(sd, ADV7393_MODE_REG0, val);
241cb7a01acSMauro Carvalho Chehab 	if (err < 0)
242cb7a01acSMauro Carvalho Chehab 		goto setoutput_exit;
243cb7a01acSMauro Carvalho Chehab 
244cb7a01acSMauro Carvalho Chehab 	state->reg02 = val;
245cb7a01acSMauro Carvalho Chehab 
246cb7a01acSMauro Carvalho Chehab 	/* configure SD DAC Output 1 bit */
247cb7a01acSMauro Carvalho Chehab 	val = state->reg82;
248cb7a01acSMauro Carvalho Chehab 	if (output_type == ADV7393_COMPONENT_ID)
249cb7a01acSMauro Carvalho Chehab 		val &= SD_DAC_OUT1_DI;
250cb7a01acSMauro Carvalho Chehab 	else
251cb7a01acSMauro Carvalho Chehab 		val |= SD_DAC_OUT1_EN;
252cb7a01acSMauro Carvalho Chehab 	err = adv7393_write(sd, ADV7393_SD_MODE_REG2, val);
253cb7a01acSMauro Carvalho Chehab 	if (err < 0)
254cb7a01acSMauro Carvalho Chehab 		goto setoutput_exit;
255cb7a01acSMauro Carvalho Chehab 
256cb7a01acSMauro Carvalho Chehab 	state->reg82 = val;
257cb7a01acSMauro Carvalho Chehab 
258cb7a01acSMauro Carvalho Chehab 	/* configure ED/HD Color DAC Swap bit to zero */
259cb7a01acSMauro Carvalho Chehab 	val = state->reg35 & HD_DAC_SWAP_DI;
260cb7a01acSMauro Carvalho Chehab 	err = adv7393_write(sd, ADV7393_HD_MODE_REG6, val);
261cb7a01acSMauro Carvalho Chehab 	if (err < 0)
262cb7a01acSMauro Carvalho Chehab 		goto setoutput_exit;
263cb7a01acSMauro Carvalho Chehab 
264cb7a01acSMauro Carvalho Chehab 	state->reg35 = val;
265cb7a01acSMauro Carvalho Chehab 
266cb7a01acSMauro Carvalho Chehab setoutput_exit:
267cb7a01acSMauro Carvalho Chehab 	if (err != 0)
268cb7a01acSMauro Carvalho Chehab 		v4l2_err(sd, "Error setting output, write failed\n");
269cb7a01acSMauro Carvalho Chehab 
270cb7a01acSMauro Carvalho Chehab 	return err;
271cb7a01acSMauro Carvalho Chehab }
272cb7a01acSMauro Carvalho Chehab 
adv7393_log_status(struct v4l2_subdev * sd)273cb7a01acSMauro Carvalho Chehab static int adv7393_log_status(struct v4l2_subdev *sd)
274cb7a01acSMauro Carvalho Chehab {
275cb7a01acSMauro Carvalho Chehab 	struct adv7393_state *state = to_state(sd);
276cb7a01acSMauro Carvalho Chehab 
277cb7a01acSMauro Carvalho Chehab 	v4l2_info(sd, "Standard: %llx\n", (unsigned long long)state->std);
278cb7a01acSMauro Carvalho Chehab 	v4l2_info(sd, "Output: %s\n", (state->output == 0) ? "Composite" :
279cb7a01acSMauro Carvalho Chehab 			((state->output == 1) ? "Component" : "S-Video"));
280cb7a01acSMauro Carvalho Chehab 	return 0;
281cb7a01acSMauro Carvalho Chehab }
282cb7a01acSMauro Carvalho Chehab 
adv7393_s_ctrl(struct v4l2_ctrl * ctrl)283cb7a01acSMauro Carvalho Chehab static int adv7393_s_ctrl(struct v4l2_ctrl *ctrl)
284cb7a01acSMauro Carvalho Chehab {
285cb7a01acSMauro Carvalho Chehab 	struct v4l2_subdev *sd = to_sd(ctrl);
286cb7a01acSMauro Carvalho Chehab 
287cb7a01acSMauro Carvalho Chehab 	switch (ctrl->id) {
288cb7a01acSMauro Carvalho Chehab 	case V4L2_CID_BRIGHTNESS:
289cb7a01acSMauro Carvalho Chehab 		return adv7393_write(sd, ADV7393_SD_BRIGHTNESS_WSS,
290cb7a01acSMauro Carvalho Chehab 					ctrl->val & SD_BRIGHTNESS_VALUE_MASK);
291cb7a01acSMauro Carvalho Chehab 
292cb7a01acSMauro Carvalho Chehab 	case V4L2_CID_HUE:
293cb7a01acSMauro Carvalho Chehab 		return adv7393_write(sd, ADV7393_SD_HUE_ADJUST,
294cb7a01acSMauro Carvalho Chehab 					ctrl->val - ADV7393_HUE_MIN);
295cb7a01acSMauro Carvalho Chehab 
296cb7a01acSMauro Carvalho Chehab 	case V4L2_CID_GAIN:
297cb7a01acSMauro Carvalho Chehab 		return adv7393_write(sd, ADV7393_DAC123_OUTPUT_LEVEL,
298cb7a01acSMauro Carvalho Chehab 					ctrl->val);
299cb7a01acSMauro Carvalho Chehab 	}
300cb7a01acSMauro Carvalho Chehab 	return -EINVAL;
301cb7a01acSMauro Carvalho Chehab }
302cb7a01acSMauro Carvalho Chehab 
303cb7a01acSMauro Carvalho Chehab static const struct v4l2_ctrl_ops adv7393_ctrl_ops = {
304cb7a01acSMauro Carvalho Chehab 	.s_ctrl = adv7393_s_ctrl,
305cb7a01acSMauro Carvalho Chehab };
306cb7a01acSMauro Carvalho Chehab 
307cb7a01acSMauro Carvalho Chehab static const struct v4l2_subdev_core_ops adv7393_core_ops = {
308cb7a01acSMauro Carvalho Chehab 	.log_status = adv7393_log_status,
309cb7a01acSMauro Carvalho Chehab };
310cb7a01acSMauro Carvalho Chehab 
adv7393_s_std_output(struct v4l2_subdev * sd,v4l2_std_id std)311cb7a01acSMauro Carvalho Chehab static int adv7393_s_std_output(struct v4l2_subdev *sd, v4l2_std_id std)
312cb7a01acSMauro Carvalho Chehab {
313cb7a01acSMauro Carvalho Chehab 	struct adv7393_state *state = to_state(sd);
314cb7a01acSMauro Carvalho Chehab 	int err = 0;
315cb7a01acSMauro Carvalho Chehab 
316cb7a01acSMauro Carvalho Chehab 	if (state->std == std)
317cb7a01acSMauro Carvalho Chehab 		return 0;
318cb7a01acSMauro Carvalho Chehab 
319cb7a01acSMauro Carvalho Chehab 	err = adv7393_setstd(sd, std);
320cb7a01acSMauro Carvalho Chehab 	if (!err)
321cb7a01acSMauro Carvalho Chehab 		state->std = std;
322cb7a01acSMauro Carvalho Chehab 
323cb7a01acSMauro Carvalho Chehab 	return err;
324cb7a01acSMauro Carvalho Chehab }
325cb7a01acSMauro Carvalho Chehab 
adv7393_s_routing(struct v4l2_subdev * sd,u32 input,u32 output,u32 config)326cb7a01acSMauro Carvalho Chehab static int adv7393_s_routing(struct v4l2_subdev *sd,
327cb7a01acSMauro Carvalho Chehab 		u32 input, u32 output, u32 config)
328cb7a01acSMauro Carvalho Chehab {
329cb7a01acSMauro Carvalho Chehab 	struct adv7393_state *state = to_state(sd);
330cb7a01acSMauro Carvalho Chehab 	int err = 0;
331cb7a01acSMauro Carvalho Chehab 
332cb7a01acSMauro Carvalho Chehab 	if (state->output == output)
333cb7a01acSMauro Carvalho Chehab 		return 0;
334cb7a01acSMauro Carvalho Chehab 
335cb7a01acSMauro Carvalho Chehab 	err = adv7393_setoutput(sd, output);
336cb7a01acSMauro Carvalho Chehab 	if (!err)
337cb7a01acSMauro Carvalho Chehab 		state->output = output;
338cb7a01acSMauro Carvalho Chehab 
339cb7a01acSMauro Carvalho Chehab 	return err;
340cb7a01acSMauro Carvalho Chehab }
341cb7a01acSMauro Carvalho Chehab 
342cb7a01acSMauro Carvalho Chehab static const struct v4l2_subdev_video_ops adv7393_video_ops = {
343cb7a01acSMauro Carvalho Chehab 	.s_std_output	= adv7393_s_std_output,
344cb7a01acSMauro Carvalho Chehab 	.s_routing	= adv7393_s_routing,
345cb7a01acSMauro Carvalho Chehab };
346cb7a01acSMauro Carvalho Chehab 
347cb7a01acSMauro Carvalho Chehab static const struct v4l2_subdev_ops adv7393_ops = {
348cb7a01acSMauro Carvalho Chehab 	.core	= &adv7393_core_ops,
349cb7a01acSMauro Carvalho Chehab 	.video	= &adv7393_video_ops,
350cb7a01acSMauro Carvalho Chehab };
351cb7a01acSMauro Carvalho Chehab 
adv7393_initialize(struct v4l2_subdev * sd)352cb7a01acSMauro Carvalho Chehab static int adv7393_initialize(struct v4l2_subdev *sd)
353cb7a01acSMauro Carvalho Chehab {
354cb7a01acSMauro Carvalho Chehab 	struct adv7393_state *state = to_state(sd);
355cb7a01acSMauro Carvalho Chehab 	int err = 0;
356cb7a01acSMauro Carvalho Chehab 	int i;
357cb7a01acSMauro Carvalho Chehab 
358cb7a01acSMauro Carvalho Chehab 	for (i = 0; i < ARRAY_SIZE(adv7393_init_reg_val); i += 2) {
359cb7a01acSMauro Carvalho Chehab 
360cb7a01acSMauro Carvalho Chehab 		err = adv7393_write(sd, adv7393_init_reg_val[i],
361cb7a01acSMauro Carvalho Chehab 					adv7393_init_reg_val[i+1]);
362cb7a01acSMauro Carvalho Chehab 		if (err) {
363cb7a01acSMauro Carvalho Chehab 			v4l2_err(sd, "Error initializing\n");
364cb7a01acSMauro Carvalho Chehab 			return err;
365cb7a01acSMauro Carvalho Chehab 		}
366cb7a01acSMauro Carvalho Chehab 	}
367cb7a01acSMauro Carvalho Chehab 
368cb7a01acSMauro Carvalho Chehab 	/* Configure for default video standard */
369cb7a01acSMauro Carvalho Chehab 	err = adv7393_setoutput(sd, state->output);
370cb7a01acSMauro Carvalho Chehab 	if (err < 0) {
371cb7a01acSMauro Carvalho Chehab 		v4l2_err(sd, "Error setting output during init\n");
372cb7a01acSMauro Carvalho Chehab 		return -EINVAL;
373cb7a01acSMauro Carvalho Chehab 	}
374cb7a01acSMauro Carvalho Chehab 
375cb7a01acSMauro Carvalho Chehab 	err = adv7393_setstd(sd, state->std);
376cb7a01acSMauro Carvalho Chehab 	if (err < 0) {
377cb7a01acSMauro Carvalho Chehab 		v4l2_err(sd, "Error setting std during init\n");
378cb7a01acSMauro Carvalho Chehab 		return -EINVAL;
379cb7a01acSMauro Carvalho Chehab 	}
380cb7a01acSMauro Carvalho Chehab 
381cb7a01acSMauro Carvalho Chehab 	return err;
382cb7a01acSMauro Carvalho Chehab }
383cb7a01acSMauro Carvalho Chehab 
adv7393_probe(struct i2c_client * client)38460622dd6SUwe Kleine-König static int adv7393_probe(struct i2c_client *client)
385cb7a01acSMauro Carvalho Chehab {
386cb7a01acSMauro Carvalho Chehab 	struct adv7393_state *state;
387cb7a01acSMauro Carvalho Chehab 	int err;
388cb7a01acSMauro Carvalho Chehab 
389cb7a01acSMauro Carvalho Chehab 	if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
390cb7a01acSMauro Carvalho Chehab 		return -ENODEV;
391cb7a01acSMauro Carvalho Chehab 
392cb7a01acSMauro Carvalho Chehab 	v4l_info(client, "chip found @ 0x%x (%s)\n",
393cb7a01acSMauro Carvalho Chehab 			client->addr << 1, client->adapter->name);
394cb7a01acSMauro Carvalho Chehab 
395c02b211dSLaurent Pinchart 	state = devm_kzalloc(&client->dev, sizeof(*state), GFP_KERNEL);
396cb7a01acSMauro Carvalho Chehab 	if (state == NULL)
397cb7a01acSMauro Carvalho Chehab 		return -ENOMEM;
398cb7a01acSMauro Carvalho Chehab 
399cb7a01acSMauro Carvalho Chehab 	state->reg00	= ADV7393_POWER_MODE_REG_DEFAULT;
400cb7a01acSMauro Carvalho Chehab 	state->reg01	= 0x00;
401cb7a01acSMauro Carvalho Chehab 	state->reg02	= 0x20;
402cb7a01acSMauro Carvalho Chehab 	state->reg35	= ADV7393_HD_MODE_REG6_DEFAULT;
403cb7a01acSMauro Carvalho Chehab 	state->reg80	= ADV7393_SD_MODE_REG1_DEFAULT;
404cb7a01acSMauro Carvalho Chehab 	state->reg82	= ADV7393_SD_MODE_REG2_DEFAULT;
405cb7a01acSMauro Carvalho Chehab 
406cb7a01acSMauro Carvalho Chehab 	state->output = ADV7393_COMPOSITE_ID;
407cb7a01acSMauro Carvalho Chehab 	state->std = V4L2_STD_NTSC;
408cb7a01acSMauro Carvalho Chehab 
409cb7a01acSMauro Carvalho Chehab 	v4l2_i2c_subdev_init(&state->sd, client, &adv7393_ops);
410cb7a01acSMauro Carvalho Chehab 
411cb7a01acSMauro Carvalho Chehab 	v4l2_ctrl_handler_init(&state->hdl, 3);
412cb7a01acSMauro Carvalho Chehab 	v4l2_ctrl_new_std(&state->hdl, &adv7393_ctrl_ops,
413cb7a01acSMauro Carvalho Chehab 			V4L2_CID_BRIGHTNESS, ADV7393_BRIGHTNESS_MIN,
414cb7a01acSMauro Carvalho Chehab 					     ADV7393_BRIGHTNESS_MAX, 1,
415cb7a01acSMauro Carvalho Chehab 					     ADV7393_BRIGHTNESS_DEF);
416cb7a01acSMauro Carvalho Chehab 	v4l2_ctrl_new_std(&state->hdl, &adv7393_ctrl_ops,
417cb7a01acSMauro Carvalho Chehab 			V4L2_CID_HUE, ADV7393_HUE_MIN,
418cb7a01acSMauro Carvalho Chehab 				      ADV7393_HUE_MAX, 1,
419cb7a01acSMauro Carvalho Chehab 				      ADV7393_HUE_DEF);
420cb7a01acSMauro Carvalho Chehab 	v4l2_ctrl_new_std(&state->hdl, &adv7393_ctrl_ops,
421cb7a01acSMauro Carvalho Chehab 			V4L2_CID_GAIN, ADV7393_GAIN_MIN,
422cb7a01acSMauro Carvalho Chehab 				       ADV7393_GAIN_MAX, 1,
423cb7a01acSMauro Carvalho Chehab 				       ADV7393_GAIN_DEF);
424cb7a01acSMauro Carvalho Chehab 	state->sd.ctrl_handler = &state->hdl;
425cb7a01acSMauro Carvalho Chehab 	if (state->hdl.error) {
426cb7a01acSMauro Carvalho Chehab 		int err = state->hdl.error;
427cb7a01acSMauro Carvalho Chehab 
428cb7a01acSMauro Carvalho Chehab 		v4l2_ctrl_handler_free(&state->hdl);
429cb7a01acSMauro Carvalho Chehab 		return err;
430cb7a01acSMauro Carvalho Chehab 	}
431cb7a01acSMauro Carvalho Chehab 	v4l2_ctrl_handler_setup(&state->hdl);
432cb7a01acSMauro Carvalho Chehab 
433cb7a01acSMauro Carvalho Chehab 	err = adv7393_initialize(&state->sd);
434c02b211dSLaurent Pinchart 	if (err)
435cb7a01acSMauro Carvalho Chehab 		v4l2_ctrl_handler_free(&state->hdl);
436cb7a01acSMauro Carvalho Chehab 	return err;
437cb7a01acSMauro Carvalho Chehab }
438cb7a01acSMauro Carvalho Chehab 
adv7393_remove(struct i2c_client * client)439ed5c2f5fSUwe Kleine-König static void adv7393_remove(struct i2c_client *client)
440cb7a01acSMauro Carvalho Chehab {
441cb7a01acSMauro Carvalho Chehab 	struct v4l2_subdev *sd = i2c_get_clientdata(client);
442cb7a01acSMauro Carvalho Chehab 	struct adv7393_state *state = to_state(sd);
443cb7a01acSMauro Carvalho Chehab 
444cb7a01acSMauro Carvalho Chehab 	v4l2_device_unregister_subdev(sd);
445cb7a01acSMauro Carvalho Chehab 	v4l2_ctrl_handler_free(&state->hdl);
446cb7a01acSMauro Carvalho Chehab }
447cb7a01acSMauro Carvalho Chehab 
448cb7a01acSMauro Carvalho Chehab static const struct i2c_device_id adv7393_id[] = {
449cb7a01acSMauro Carvalho Chehab 	{"adv7393", 0},
450cb7a01acSMauro Carvalho Chehab 	{},
451cb7a01acSMauro Carvalho Chehab };
452cb7a01acSMauro Carvalho Chehab MODULE_DEVICE_TABLE(i2c, adv7393_id);
453cb7a01acSMauro Carvalho Chehab 
454cb7a01acSMauro Carvalho Chehab static struct i2c_driver adv7393_driver = {
455cb7a01acSMauro Carvalho Chehab 	.driver = {
456cb7a01acSMauro Carvalho Chehab 		.name	= "adv7393",
457cb7a01acSMauro Carvalho Chehab 	},
458*aaeb31c0SUwe Kleine-König 	.probe		= adv7393_probe,
459cb7a01acSMauro Carvalho Chehab 	.remove		= adv7393_remove,
460cb7a01acSMauro Carvalho Chehab 	.id_table	= adv7393_id,
461cb7a01acSMauro Carvalho Chehab };
462cb7a01acSMauro Carvalho Chehab module_i2c_driver(adv7393_driver);
463