1*2aec85b2SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 2cb7a01acSMauro Carvalho Chehab /* 3cb7a01acSMauro Carvalho Chehab * ADV7343 encoder related structure and register definitions 4cb7a01acSMauro Carvalho Chehab * 5cb7a01acSMauro Carvalho Chehab * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/ 6cb7a01acSMauro Carvalho Chehab */ 7cb7a01acSMauro Carvalho Chehab 8825fd08dSRasmus Villemoes #ifndef ADV7343_REGS_H 9cb7a01acSMauro Carvalho Chehab #define ADV7343_REGS_H 10cb7a01acSMauro Carvalho Chehab 11cb7a01acSMauro Carvalho Chehab struct adv7343_std_info { 12cb7a01acSMauro Carvalho Chehab u32 standard_val3; 13cb7a01acSMauro Carvalho Chehab u32 fsc_val; 14cb7a01acSMauro Carvalho Chehab v4l2_std_id stdid; 15cb7a01acSMauro Carvalho Chehab }; 16cb7a01acSMauro Carvalho Chehab 17cb7a01acSMauro Carvalho Chehab /* Register offset macros */ 18cb7a01acSMauro Carvalho Chehab #define ADV7343_POWER_MODE_REG (0x00) 19cb7a01acSMauro Carvalho Chehab #define ADV7343_MODE_SELECT_REG (0x01) 20cb7a01acSMauro Carvalho Chehab #define ADV7343_MODE_REG0 (0x02) 21cb7a01acSMauro Carvalho Chehab 22cb7a01acSMauro Carvalho Chehab #define ADV7343_DAC2_OUTPUT_LEVEL (0x0b) 23cb7a01acSMauro Carvalho Chehab 24cb7a01acSMauro Carvalho Chehab #define ADV7343_SOFT_RESET (0x17) 25cb7a01acSMauro Carvalho Chehab 26cb7a01acSMauro Carvalho Chehab #define ADV7343_HD_MODE_REG1 (0x30) 27cb7a01acSMauro Carvalho Chehab #define ADV7343_HD_MODE_REG2 (0x31) 28cb7a01acSMauro Carvalho Chehab #define ADV7343_HD_MODE_REG3 (0x32) 29cb7a01acSMauro Carvalho Chehab #define ADV7343_HD_MODE_REG4 (0x33) 30cb7a01acSMauro Carvalho Chehab #define ADV7343_HD_MODE_REG5 (0x34) 31cb7a01acSMauro Carvalho Chehab #define ADV7343_HD_MODE_REG6 (0x35) 32cb7a01acSMauro Carvalho Chehab 33cb7a01acSMauro Carvalho Chehab #define ADV7343_HD_MODE_REG7 (0x39) 34cb7a01acSMauro Carvalho Chehab 35cb7a01acSMauro Carvalho Chehab #define ADV7343_SD_MODE_REG1 (0x80) 36cb7a01acSMauro Carvalho Chehab #define ADV7343_SD_MODE_REG2 (0x82) 37cb7a01acSMauro Carvalho Chehab #define ADV7343_SD_MODE_REG3 (0x83) 38cb7a01acSMauro Carvalho Chehab #define ADV7343_SD_MODE_REG4 (0x84) 39cb7a01acSMauro Carvalho Chehab #define ADV7343_SD_MODE_REG5 (0x86) 40cb7a01acSMauro Carvalho Chehab #define ADV7343_SD_MODE_REG6 (0x87) 41cb7a01acSMauro Carvalho Chehab #define ADV7343_SD_MODE_REG7 (0x88) 42cb7a01acSMauro Carvalho Chehab #define ADV7343_SD_MODE_REG8 (0x89) 43cb7a01acSMauro Carvalho Chehab 44cb7a01acSMauro Carvalho Chehab #define ADV7343_FSC_REG0 (0x8C) 45cb7a01acSMauro Carvalho Chehab #define ADV7343_FSC_REG1 (0x8D) 46cb7a01acSMauro Carvalho Chehab #define ADV7343_FSC_REG2 (0x8E) 47cb7a01acSMauro Carvalho Chehab #define ADV7343_FSC_REG3 (0x8F) 48cb7a01acSMauro Carvalho Chehab 49cb7a01acSMauro Carvalho Chehab #define ADV7343_SD_CGMS_WSS0 (0x99) 50cb7a01acSMauro Carvalho Chehab 51cb7a01acSMauro Carvalho Chehab #define ADV7343_SD_HUE_REG (0xA0) 52cb7a01acSMauro Carvalho Chehab #define ADV7343_SD_BRIGHTNESS_WSS (0xA1) 53cb7a01acSMauro Carvalho Chehab 54cb7a01acSMauro Carvalho Chehab /* Default values for the registers */ 55cb7a01acSMauro Carvalho Chehab #define ADV7343_POWER_MODE_REG_DEFAULT (0x10) 56cb7a01acSMauro Carvalho Chehab #define ADV7343_HD_MODE_REG1_DEFAULT (0x3C) /* Changed Default 57cb7a01acSMauro Carvalho Chehab 720p EAVSAV code*/ 58cb7a01acSMauro Carvalho Chehab #define ADV7343_HD_MODE_REG2_DEFAULT (0x01) /* Changed Pixel data 59cb7a01acSMauro Carvalho Chehab valid */ 60cb7a01acSMauro Carvalho Chehab #define ADV7343_HD_MODE_REG3_DEFAULT (0x00) /* Color delay 0 clks */ 61cb7a01acSMauro Carvalho Chehab #define ADV7343_HD_MODE_REG4_DEFAULT (0xE8) /* Changed */ 62cb7a01acSMauro Carvalho Chehab #define ADV7343_HD_MODE_REG5_DEFAULT (0x08) 63cb7a01acSMauro Carvalho Chehab #define ADV7343_HD_MODE_REG6_DEFAULT (0x00) 64cb7a01acSMauro Carvalho Chehab #define ADV7343_HD_MODE_REG7_DEFAULT (0x00) 65cb7a01acSMauro Carvalho Chehab #define ADV7343_SD_MODE_REG8_DEFAULT (0x00) 66cb7a01acSMauro Carvalho Chehab #define ADV7343_SOFT_RESET_DEFAULT (0x02) 67cb7a01acSMauro Carvalho Chehab #define ADV7343_COMPOSITE_POWER_VALUE (0x80) 68cb7a01acSMauro Carvalho Chehab #define ADV7343_COMPONENT_POWER_VALUE (0x1C) 69cb7a01acSMauro Carvalho Chehab #define ADV7343_SVIDEO_POWER_VALUE (0x60) 70cb7a01acSMauro Carvalho Chehab #define ADV7343_SD_HUE_REG_DEFAULT (127) 71cb7a01acSMauro Carvalho Chehab #define ADV7343_SD_BRIGHTNESS_WSS_DEFAULT (0x03) 72cb7a01acSMauro Carvalho Chehab 73cb7a01acSMauro Carvalho Chehab #define ADV7343_SD_CGMS_WSS0_DEFAULT (0x10) 74cb7a01acSMauro Carvalho Chehab 75cb7a01acSMauro Carvalho Chehab #define ADV7343_SD_MODE_REG1_DEFAULT (0x00) 76cb7a01acSMauro Carvalho Chehab #define ADV7343_SD_MODE_REG2_DEFAULT (0xC9) 77cb7a01acSMauro Carvalho Chehab #define ADV7343_SD_MODE_REG3_DEFAULT (0x10) 78cb7a01acSMauro Carvalho Chehab #define ADV7343_SD_MODE_REG4_DEFAULT (0x01) 79cb7a01acSMauro Carvalho Chehab #define ADV7343_SD_MODE_REG5_DEFAULT (0x02) 80cb7a01acSMauro Carvalho Chehab #define ADV7343_SD_MODE_REG6_DEFAULT (0x0C) 81cb7a01acSMauro Carvalho Chehab #define ADV7343_SD_MODE_REG7_DEFAULT (0x04) 82cb7a01acSMauro Carvalho Chehab #define ADV7343_SD_MODE_REG8_DEFAULT (0x00) 83cb7a01acSMauro Carvalho Chehab 84cb7a01acSMauro Carvalho Chehab /* Bit masks for Mode Select Register */ 85cb7a01acSMauro Carvalho Chehab #define INPUT_MODE_MASK (0x70) 86cb7a01acSMauro Carvalho Chehab #define SD_INPUT_MODE (0x00) 87cb7a01acSMauro Carvalho Chehab #define HD_720P_INPUT_MODE (0x10) 88cb7a01acSMauro Carvalho Chehab #define HD_1080I_INPUT_MODE (0x10) 89cb7a01acSMauro Carvalho Chehab 90cb7a01acSMauro Carvalho Chehab /* Bit masks for Mode Register 0 */ 91cb7a01acSMauro Carvalho Chehab #define TEST_PATTERN_BLACK_BAR_EN (0x04) 92cb7a01acSMauro Carvalho Chehab #define YUV_OUTPUT_SELECT (0x20) 93cb7a01acSMauro Carvalho Chehab #define RGB_OUTPUT_SELECT (0xDF) 94cb7a01acSMauro Carvalho Chehab 95cb7a01acSMauro Carvalho Chehab /* Bit masks for DAC output levels */ 96cb7a01acSMauro Carvalho Chehab #define DAC_OUTPUT_LEVEL_MASK (0xFF) 97cb7a01acSMauro Carvalho Chehab 98cb7a01acSMauro Carvalho Chehab /* Bit masks for soft reset register */ 99cb7a01acSMauro Carvalho Chehab #define SOFT_RESET (0x02) 100cb7a01acSMauro Carvalho Chehab 101cb7a01acSMauro Carvalho Chehab /* Bit masks for HD Mode Register 1 */ 102cb7a01acSMauro Carvalho Chehab #define OUTPUT_STD_MASK (0x03) 103cb7a01acSMauro Carvalho Chehab #define OUTPUT_STD_SHIFT (0) 104cb7a01acSMauro Carvalho Chehab #define OUTPUT_STD_EIA0_2 (0x00) 105cb7a01acSMauro Carvalho Chehab #define OUTPUT_STD_EIA0_1 (0x01) 106cb7a01acSMauro Carvalho Chehab #define OUTPUT_STD_FULL (0x02) 107cb7a01acSMauro Carvalho Chehab #define EMBEDDED_SYNC (0x04) 108cb7a01acSMauro Carvalho Chehab #define EXTERNAL_SYNC (0xFB) 109cb7a01acSMauro Carvalho Chehab #define STD_MODE_SHIFT (3) 110cb7a01acSMauro Carvalho Chehab #define STD_MODE_MASK (0x1F) 111cb7a01acSMauro Carvalho Chehab #define STD_MODE_720P (0x05) 112cb7a01acSMauro Carvalho Chehab #define STD_MODE_720P_25 (0x08) 113cb7a01acSMauro Carvalho Chehab #define STD_MODE_720P_30 (0x07) 114cb7a01acSMauro Carvalho Chehab #define STD_MODE_720P_50 (0x06) 115cb7a01acSMauro Carvalho Chehab #define STD_MODE_1080I (0x0D) 116cb7a01acSMauro Carvalho Chehab #define STD_MODE_1080I_25fps (0x0E) 117cb7a01acSMauro Carvalho Chehab #define STD_MODE_1080P_24 (0x12) 118cb7a01acSMauro Carvalho Chehab #define STD_MODE_1080P_25 (0x10) 119cb7a01acSMauro Carvalho Chehab #define STD_MODE_1080P_30 (0x0F) 120cb7a01acSMauro Carvalho Chehab #define STD_MODE_525P (0x00) 121cb7a01acSMauro Carvalho Chehab #define STD_MODE_625P (0x03) 122cb7a01acSMauro Carvalho Chehab 123cb7a01acSMauro Carvalho Chehab /* Bit masks for SD Mode Register 1 */ 124cb7a01acSMauro Carvalho Chehab #define SD_STD_MASK (0x03) 125cb7a01acSMauro Carvalho Chehab #define SD_STD_NTSC (0x00) 126cb7a01acSMauro Carvalho Chehab #define SD_STD_PAL_BDGHI (0x01) 127cb7a01acSMauro Carvalho Chehab #define SD_STD_PAL_M (0x02) 128cb7a01acSMauro Carvalho Chehab #define SD_STD_PAL_N (0x03) 129cb7a01acSMauro Carvalho Chehab #define SD_LUMA_FLTR_MASK (0x7) 130cb7a01acSMauro Carvalho Chehab #define SD_LUMA_FLTR_SHIFT (0x2) 131cb7a01acSMauro Carvalho Chehab #define SD_CHROMA_FLTR_MASK (0x7) 132cb7a01acSMauro Carvalho Chehab #define SD_CHROMA_FLTR_SHIFT (0x5) 133cb7a01acSMauro Carvalho Chehab 134cb7a01acSMauro Carvalho Chehab /* Bit masks for SD Mode Register 2 */ 135cb7a01acSMauro Carvalho Chehab #define SD_PBPR_SSAF_EN (0x01) 136cb7a01acSMauro Carvalho Chehab #define SD_PBPR_SSAF_DI (0xFE) 137cb7a01acSMauro Carvalho Chehab #define SD_DAC_1_DI (0xFD) 138cb7a01acSMauro Carvalho Chehab #define SD_DAC_2_DI (0xFB) 139cb7a01acSMauro Carvalho Chehab #define SD_PEDESTAL_EN (0x08) 140cb7a01acSMauro Carvalho Chehab #define SD_PEDESTAL_DI (0xF7) 141cb7a01acSMauro Carvalho Chehab #define SD_SQUARE_PIXEL_EN (0x10) 142cb7a01acSMauro Carvalho Chehab #define SD_SQUARE_PIXEL_DI (0xEF) 143cb7a01acSMauro Carvalho Chehab #define SD_PIXEL_DATA_VALID (0x40) 144cb7a01acSMauro Carvalho Chehab #define SD_ACTIVE_EDGE_EN (0x80) 145cb7a01acSMauro Carvalho Chehab #define SD_ACTIVE_EDGE_DI (0x7F) 146cb7a01acSMauro Carvalho Chehab 147cb7a01acSMauro Carvalho Chehab /* Bit masks for HD Mode Register 6 */ 148cb7a01acSMauro Carvalho Chehab #define HD_RGB_INPUT_EN (0x02) 149cb7a01acSMauro Carvalho Chehab #define HD_RGB_INPUT_DI (0xFD) 150cb7a01acSMauro Carvalho Chehab #define HD_PBPR_SYNC_EN (0x04) 151cb7a01acSMauro Carvalho Chehab #define HD_PBPR_SYNC_DI (0xFB) 152cb7a01acSMauro Carvalho Chehab #define HD_DAC_SWAP_EN (0x08) 153cb7a01acSMauro Carvalho Chehab #define HD_DAC_SWAP_DI (0xF7) 154cb7a01acSMauro Carvalho Chehab #define HD_GAMMA_CURVE_A (0xEF) 155cb7a01acSMauro Carvalho Chehab #define HD_GAMMA_CURVE_B (0x10) 156cb7a01acSMauro Carvalho Chehab #define HD_GAMMA_EN (0x20) 157cb7a01acSMauro Carvalho Chehab #define HD_GAMMA_DI (0xDF) 158cb7a01acSMauro Carvalho Chehab #define HD_ADPT_FLTR_MODEB (0x40) 159cb7a01acSMauro Carvalho Chehab #define HD_ADPT_FLTR_MODEA (0xBF) 160cb7a01acSMauro Carvalho Chehab #define HD_ADPT_FLTR_EN (0x80) 161cb7a01acSMauro Carvalho Chehab #define HD_ADPT_FLTR_DI (0x7F) 162cb7a01acSMauro Carvalho Chehab 163cb7a01acSMauro Carvalho Chehab #define ADV7343_BRIGHTNESS_MAX (127) 164cb7a01acSMauro Carvalho Chehab #define ADV7343_BRIGHTNESS_MIN (0) 165cb7a01acSMauro Carvalho Chehab #define ADV7343_BRIGHTNESS_DEF (3) 166cb7a01acSMauro Carvalho Chehab #define ADV7343_HUE_MAX (255) 167cb7a01acSMauro Carvalho Chehab #define ADV7343_HUE_MIN (0) 168cb7a01acSMauro Carvalho Chehab #define ADV7343_HUE_DEF (127) 169cb7a01acSMauro Carvalho Chehab #define ADV7343_GAIN_MAX (64) 170cb7a01acSMauro Carvalho Chehab #define ADV7343_GAIN_MIN (-64) 171cb7a01acSMauro Carvalho Chehab #define ADV7343_GAIN_DEF (0) 172cb7a01acSMauro Carvalho Chehab 173cb7a01acSMauro Carvalho Chehab #endif 174