xref: /openbmc/linux/drivers/media/i2c/adv7343.c (revision 861e10be)
1 /*
2  * adv7343 - ADV7343 Video Encoder Driver
3  *
4  * The encoder hardware does not support SECAM.
5  *
6  * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
7  *
8  * This program is free software; you can redistribute it and/or
9  * modify it under the terms of the GNU General Public License as
10  * published by the Free Software Foundation version 2.
11  *
12  * This program is distributed .as is. WITHOUT ANY WARRANTY of any
13  * kind, whether express or implied; without even the implied warranty
14  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15  * GNU General Public License for more details.
16  */
17 
18 #include <linux/kernel.h>
19 #include <linux/init.h>
20 #include <linux/ctype.h>
21 #include <linux/slab.h>
22 #include <linux/i2c.h>
23 #include <linux/device.h>
24 #include <linux/delay.h>
25 #include <linux/module.h>
26 #include <linux/videodev2.h>
27 #include <linux/uaccess.h>
28 
29 #include <media/adv7343.h>
30 #include <media/v4l2-device.h>
31 #include <media/v4l2-chip-ident.h>
32 #include <media/v4l2-ctrls.h>
33 
34 #include "adv7343_regs.h"
35 
36 MODULE_DESCRIPTION("ADV7343 video encoder driver");
37 MODULE_LICENSE("GPL");
38 
39 static int debug;
40 module_param(debug, int, 0644);
41 MODULE_PARM_DESC(debug, "Debug level 0-1");
42 
43 struct adv7343_state {
44 	struct v4l2_subdev sd;
45 	struct v4l2_ctrl_handler hdl;
46 	u8 reg00;
47 	u8 reg01;
48 	u8 reg02;
49 	u8 reg35;
50 	u8 reg80;
51 	u8 reg82;
52 	u32 output;
53 	v4l2_std_id std;
54 };
55 
56 static inline struct adv7343_state *to_state(struct v4l2_subdev *sd)
57 {
58 	return container_of(sd, struct adv7343_state, sd);
59 }
60 
61 static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
62 {
63 	return &container_of(ctrl->handler, struct adv7343_state, hdl)->sd;
64 }
65 
66 static inline int adv7343_write(struct v4l2_subdev *sd, u8 reg, u8 value)
67 {
68 	struct i2c_client *client = v4l2_get_subdevdata(sd);
69 
70 	return i2c_smbus_write_byte_data(client, reg, value);
71 }
72 
73 static const u8 adv7343_init_reg_val[] = {
74 	ADV7343_SOFT_RESET, ADV7343_SOFT_RESET_DEFAULT,
75 	ADV7343_POWER_MODE_REG, ADV7343_POWER_MODE_REG_DEFAULT,
76 
77 	ADV7343_HD_MODE_REG1, ADV7343_HD_MODE_REG1_DEFAULT,
78 	ADV7343_HD_MODE_REG2, ADV7343_HD_MODE_REG2_DEFAULT,
79 	ADV7343_HD_MODE_REG3, ADV7343_HD_MODE_REG3_DEFAULT,
80 	ADV7343_HD_MODE_REG4, ADV7343_HD_MODE_REG4_DEFAULT,
81 	ADV7343_HD_MODE_REG5, ADV7343_HD_MODE_REG5_DEFAULT,
82 	ADV7343_HD_MODE_REG6, ADV7343_HD_MODE_REG6_DEFAULT,
83 	ADV7343_HD_MODE_REG7, ADV7343_HD_MODE_REG7_DEFAULT,
84 
85 	ADV7343_SD_MODE_REG1, ADV7343_SD_MODE_REG1_DEFAULT,
86 	ADV7343_SD_MODE_REG2, ADV7343_SD_MODE_REG2_DEFAULT,
87 	ADV7343_SD_MODE_REG3, ADV7343_SD_MODE_REG3_DEFAULT,
88 	ADV7343_SD_MODE_REG4, ADV7343_SD_MODE_REG4_DEFAULT,
89 	ADV7343_SD_MODE_REG5, ADV7343_SD_MODE_REG5_DEFAULT,
90 	ADV7343_SD_MODE_REG6, ADV7343_SD_MODE_REG6_DEFAULT,
91 	ADV7343_SD_MODE_REG7, ADV7343_SD_MODE_REG7_DEFAULT,
92 	ADV7343_SD_MODE_REG8, ADV7343_SD_MODE_REG8_DEFAULT,
93 
94 	ADV7343_SD_HUE_REG, ADV7343_SD_HUE_REG_DEFAULT,
95 	ADV7343_SD_CGMS_WSS0, ADV7343_SD_CGMS_WSS0_DEFAULT,
96 	ADV7343_SD_BRIGHTNESS_WSS, ADV7343_SD_BRIGHTNESS_WSS_DEFAULT,
97 };
98 
99 /*
100  * 			    2^32
101  * FSC(reg) =  FSC (HZ) * --------
102  *			  27000000
103  */
104 static const struct adv7343_std_info stdinfo[] = {
105 	{
106 		/* FSC(Hz) = 3,579,545.45 Hz */
107 		SD_STD_NTSC, 569408542, V4L2_STD_NTSC,
108 	}, {
109 		/* FSC(Hz) = 3,575,611.00 Hz */
110 		SD_STD_PAL_M, 568782678, V4L2_STD_PAL_M,
111 	}, {
112 		/* FSC(Hz) = 3,582,056.00 */
113 		SD_STD_PAL_N, 569807903, V4L2_STD_PAL_Nc,
114 	}, {
115 		/* FSC(Hz) = 4,433,618.75 Hz */
116 		SD_STD_PAL_N, 705268427, V4L2_STD_PAL_N,
117 	}, {
118 		/* FSC(Hz) = 4,433,618.75 Hz */
119 		SD_STD_PAL_BDGHI, 705268427, V4L2_STD_PAL,
120 	}, {
121 		/* FSC(Hz) = 4,433,618.75 Hz */
122 		SD_STD_NTSC, 705268427, V4L2_STD_NTSC_443,
123 	}, {
124 		/* FSC(Hz) = 4,433,618.75 Hz */
125 		SD_STD_PAL_M, 705268427, V4L2_STD_PAL_60,
126 	},
127 };
128 
129 static int adv7343_setstd(struct v4l2_subdev *sd, v4l2_std_id std)
130 {
131 	struct adv7343_state *state = to_state(sd);
132 	struct adv7343_std_info *std_info;
133 	int num_std;
134 	char *fsc_ptr;
135 	u8 reg, val;
136 	int err = 0;
137 	int i = 0;
138 
139 	std_info = (struct adv7343_std_info *)stdinfo;
140 	num_std = ARRAY_SIZE(stdinfo);
141 
142 	for (i = 0; i < num_std; i++) {
143 		if (std_info[i].stdid & std)
144 			break;
145 	}
146 
147 	if (i == num_std) {
148 		v4l2_dbg(1, debug, sd,
149 				"Invalid std or std is not supported: %llx\n",
150 						(unsigned long long)std);
151 		return -EINVAL;
152 	}
153 
154 	/* Set the standard */
155 	val = state->reg80 & (~(SD_STD_MASK));
156 	val |= std_info[i].standard_val3;
157 	err = adv7343_write(sd, ADV7343_SD_MODE_REG1, val);
158 	if (err < 0)
159 		goto setstd_exit;
160 
161 	state->reg80 = val;
162 
163 	/* Configure the input mode register */
164 	val = state->reg01 & (~((u8) INPUT_MODE_MASK));
165 	val |= SD_INPUT_MODE;
166 	err = adv7343_write(sd, ADV7343_MODE_SELECT_REG, val);
167 	if (err < 0)
168 		goto setstd_exit;
169 
170 	state->reg01 = val;
171 
172 	/* Program the sub carrier frequency registers */
173 	fsc_ptr = (unsigned char *)&std_info[i].fsc_val;
174 	reg = ADV7343_FSC_REG0;
175 	for (i = 0; i < 4; i++, reg++, fsc_ptr++) {
176 		err = adv7343_write(sd, reg, *fsc_ptr);
177 		if (err < 0)
178 			goto setstd_exit;
179 	}
180 
181 	val = state->reg80;
182 
183 	/* Filter settings */
184 	if (std & (V4L2_STD_NTSC | V4L2_STD_NTSC_443))
185 		val &= 0x03;
186 	else if (std & ~V4L2_STD_SECAM)
187 		val |= 0x04;
188 
189 	err = adv7343_write(sd, ADV7343_SD_MODE_REG1, val);
190 	if (err < 0)
191 		goto setstd_exit;
192 
193 	state->reg80 = val;
194 
195 setstd_exit:
196 	if (err != 0)
197 		v4l2_err(sd, "Error setting std, write failed\n");
198 
199 	return err;
200 }
201 
202 static int adv7343_setoutput(struct v4l2_subdev *sd, u32 output_type)
203 {
204 	struct adv7343_state *state = to_state(sd);
205 	unsigned char val;
206 	int err = 0;
207 
208 	if (output_type > ADV7343_SVIDEO_ID) {
209 		v4l2_dbg(1, debug, sd,
210 			"Invalid output type or output type not supported:%d\n",
211 								output_type);
212 		return -EINVAL;
213 	}
214 
215 	/* Enable Appropriate DAC */
216 	val = state->reg00 & 0x03;
217 
218 	if (output_type == ADV7343_COMPOSITE_ID)
219 		val |= ADV7343_COMPOSITE_POWER_VALUE;
220 	else if (output_type == ADV7343_COMPONENT_ID)
221 		val |= ADV7343_COMPONENT_POWER_VALUE;
222 	else
223 		val |= ADV7343_SVIDEO_POWER_VALUE;
224 
225 	err = adv7343_write(sd, ADV7343_POWER_MODE_REG, val);
226 	if (err < 0)
227 		goto setoutput_exit;
228 
229 	state->reg00 = val;
230 
231 	/* Enable YUV output */
232 	val = state->reg02 | YUV_OUTPUT_SELECT;
233 	err = adv7343_write(sd, ADV7343_MODE_REG0, val);
234 	if (err < 0)
235 		goto setoutput_exit;
236 
237 	state->reg02 = val;
238 
239 	/* configure SD DAC Output 2 and SD DAC Output 1 bit to zero */
240 	val = state->reg82 & (SD_DAC_1_DI & SD_DAC_2_DI);
241 	err = adv7343_write(sd, ADV7343_SD_MODE_REG2, val);
242 	if (err < 0)
243 		goto setoutput_exit;
244 
245 	state->reg82 = val;
246 
247 	/* configure ED/HD Color DAC Swap and ED/HD RGB Input Enable bit to
248 	 * zero */
249 	val = state->reg35 & (HD_RGB_INPUT_DI & HD_DAC_SWAP_DI);
250 	err = adv7343_write(sd, ADV7343_HD_MODE_REG6, val);
251 	if (err < 0)
252 		goto setoutput_exit;
253 
254 	state->reg35 = val;
255 
256 setoutput_exit:
257 	if (err != 0)
258 		v4l2_err(sd, "Error setting output, write failed\n");
259 
260 	return err;
261 }
262 
263 static int adv7343_log_status(struct v4l2_subdev *sd)
264 {
265 	struct adv7343_state *state = to_state(sd);
266 
267 	v4l2_info(sd, "Standard: %llx\n", (unsigned long long)state->std);
268 	v4l2_info(sd, "Output: %s\n", (state->output == 0) ? "Composite" :
269 			((state->output == 1) ? "Component" : "S-Video"));
270 	return 0;
271 }
272 
273 static int adv7343_s_ctrl(struct v4l2_ctrl *ctrl)
274 {
275 	struct v4l2_subdev *sd = to_sd(ctrl);
276 
277 	switch (ctrl->id) {
278 	case V4L2_CID_BRIGHTNESS:
279 		return adv7343_write(sd, ADV7343_SD_BRIGHTNESS_WSS,
280 					ctrl->val);
281 
282 	case V4L2_CID_HUE:
283 		return adv7343_write(sd, ADV7343_SD_HUE_REG, ctrl->val);
284 
285 	case V4L2_CID_GAIN:
286 		return adv7343_write(sd, ADV7343_DAC2_OUTPUT_LEVEL, ctrl->val);
287 	}
288 	return -EINVAL;
289 }
290 
291 static int adv7343_g_chip_ident(struct v4l2_subdev *sd,
292 				struct v4l2_dbg_chip_ident *chip)
293 {
294 	struct i2c_client *client = v4l2_get_subdevdata(sd);
295 
296 	return v4l2_chip_ident_i2c_client(client, chip, V4L2_IDENT_ADV7343, 0);
297 }
298 
299 static const struct v4l2_ctrl_ops adv7343_ctrl_ops = {
300 	.s_ctrl = adv7343_s_ctrl,
301 };
302 
303 static const struct v4l2_subdev_core_ops adv7343_core_ops = {
304 	.log_status = adv7343_log_status,
305 	.g_chip_ident = adv7343_g_chip_ident,
306 	.g_ext_ctrls = v4l2_subdev_g_ext_ctrls,
307 	.try_ext_ctrls = v4l2_subdev_try_ext_ctrls,
308 	.s_ext_ctrls = v4l2_subdev_s_ext_ctrls,
309 	.g_ctrl = v4l2_subdev_g_ctrl,
310 	.s_ctrl = v4l2_subdev_s_ctrl,
311 	.queryctrl = v4l2_subdev_queryctrl,
312 	.querymenu = v4l2_subdev_querymenu,
313 };
314 
315 static int adv7343_s_std_output(struct v4l2_subdev *sd, v4l2_std_id std)
316 {
317 	struct adv7343_state *state = to_state(sd);
318 	int err = 0;
319 
320 	if (state->std == std)
321 		return 0;
322 
323 	err = adv7343_setstd(sd, std);
324 	if (!err)
325 		state->std = std;
326 
327 	return err;
328 }
329 
330 static int adv7343_s_routing(struct v4l2_subdev *sd,
331 		u32 input, u32 output, u32 config)
332 {
333 	struct adv7343_state *state = to_state(sd);
334 	int err = 0;
335 
336 	if (state->output == output)
337 		return 0;
338 
339 	err = adv7343_setoutput(sd, output);
340 	if (!err)
341 		state->output = output;
342 
343 	return err;
344 }
345 
346 static const struct v4l2_subdev_video_ops adv7343_video_ops = {
347 	.s_std_output	= adv7343_s_std_output,
348 	.s_routing	= adv7343_s_routing,
349 };
350 
351 static const struct v4l2_subdev_ops adv7343_ops = {
352 	.core	= &adv7343_core_ops,
353 	.video	= &adv7343_video_ops,
354 };
355 
356 static int adv7343_initialize(struct v4l2_subdev *sd)
357 {
358 	struct adv7343_state *state = to_state(sd);
359 	int err = 0;
360 	int i;
361 
362 	for (i = 0; i < ARRAY_SIZE(adv7343_init_reg_val); i += 2) {
363 
364 		err = adv7343_write(sd, adv7343_init_reg_val[i],
365 					adv7343_init_reg_val[i+1]);
366 		if (err) {
367 			v4l2_err(sd, "Error initializing\n");
368 			return err;
369 		}
370 	}
371 
372 	/* Configure for default video standard */
373 	err = adv7343_setoutput(sd, state->output);
374 	if (err < 0) {
375 		v4l2_err(sd, "Error setting output during init\n");
376 		return -EINVAL;
377 	}
378 
379 	err = adv7343_setstd(sd, state->std);
380 	if (err < 0) {
381 		v4l2_err(sd, "Error setting std during init\n");
382 		return -EINVAL;
383 	}
384 
385 	return err;
386 }
387 
388 static int adv7343_probe(struct i2c_client *client,
389 				const struct i2c_device_id *id)
390 {
391 	struct adv7343_state *state;
392 	int err;
393 
394 	if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
395 		return -ENODEV;
396 
397 	v4l_info(client, "chip found @ 0x%x (%s)\n",
398 			client->addr << 1, client->adapter->name);
399 
400 	state = kzalloc(sizeof(struct adv7343_state), GFP_KERNEL);
401 	if (state == NULL)
402 		return -ENOMEM;
403 
404 	state->reg00	= 0x80;
405 	state->reg01	= 0x00;
406 	state->reg02	= 0x20;
407 	state->reg35	= 0x00;
408 	state->reg80	= ADV7343_SD_MODE_REG1_DEFAULT;
409 	state->reg82	= ADV7343_SD_MODE_REG2_DEFAULT;
410 
411 	state->output = ADV7343_COMPOSITE_ID;
412 	state->std = V4L2_STD_NTSC;
413 
414 	v4l2_i2c_subdev_init(&state->sd, client, &adv7343_ops);
415 
416 	v4l2_ctrl_handler_init(&state->hdl, 2);
417 	v4l2_ctrl_new_std(&state->hdl, &adv7343_ctrl_ops,
418 			V4L2_CID_BRIGHTNESS, ADV7343_BRIGHTNESS_MIN,
419 					     ADV7343_BRIGHTNESS_MAX, 1,
420 					     ADV7343_BRIGHTNESS_DEF);
421 	v4l2_ctrl_new_std(&state->hdl, &adv7343_ctrl_ops,
422 			V4L2_CID_HUE, ADV7343_HUE_MIN,
423 				      ADV7343_HUE_MAX, 1,
424 				      ADV7343_HUE_DEF);
425 	v4l2_ctrl_new_std(&state->hdl, &adv7343_ctrl_ops,
426 			V4L2_CID_GAIN, ADV7343_GAIN_MIN,
427 				       ADV7343_GAIN_MAX, 1,
428 				       ADV7343_GAIN_DEF);
429 	state->sd.ctrl_handler = &state->hdl;
430 	if (state->hdl.error) {
431 		int err = state->hdl.error;
432 
433 		v4l2_ctrl_handler_free(&state->hdl);
434 		kfree(state);
435 		return err;
436 	}
437 	v4l2_ctrl_handler_setup(&state->hdl);
438 
439 	err = adv7343_initialize(&state->sd);
440 	if (err) {
441 		v4l2_ctrl_handler_free(&state->hdl);
442 		kfree(state);
443 	}
444 	return err;
445 }
446 
447 static int adv7343_remove(struct i2c_client *client)
448 {
449 	struct v4l2_subdev *sd = i2c_get_clientdata(client);
450 	struct adv7343_state *state = to_state(sd);
451 
452 	v4l2_device_unregister_subdev(sd);
453 	v4l2_ctrl_handler_free(&state->hdl);
454 	kfree(state);
455 
456 	return 0;
457 }
458 
459 static const struct i2c_device_id adv7343_id[] = {
460 	{"adv7343", 0},
461 	{},
462 };
463 
464 MODULE_DEVICE_TABLE(i2c, adv7343_id);
465 
466 static struct i2c_driver adv7343_driver = {
467 	.driver = {
468 		.owner	= THIS_MODULE,
469 		.name	= "adv7343",
470 	},
471 	.probe		= adv7343_probe,
472 	.remove		= adv7343_remove,
473 	.id_table	= adv7343_id,
474 };
475 
476 module_i2c_driver(adv7343_driver);
477