1cb7a01acSMauro Carvalho Chehab /*
2cb7a01acSMauro Carvalho Chehab * adv7343 - ADV7343 Video Encoder Driver
3cb7a01acSMauro Carvalho Chehab *
4cb7a01acSMauro Carvalho Chehab * The encoder hardware does not support SECAM.
5cb7a01acSMauro Carvalho Chehab *
6cb7a01acSMauro Carvalho Chehab * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
7cb7a01acSMauro Carvalho Chehab *
8cb7a01acSMauro Carvalho Chehab * This program is free software; you can redistribute it and/or
9cb7a01acSMauro Carvalho Chehab * modify it under the terms of the GNU General Public License as
10cb7a01acSMauro Carvalho Chehab * published by the Free Software Foundation version 2.
11cb7a01acSMauro Carvalho Chehab *
12cb7a01acSMauro Carvalho Chehab * This program is distributed .as is. WITHOUT ANY WARRANTY of any
13cb7a01acSMauro Carvalho Chehab * kind, whether express or implied; without even the implied warranty
14cb7a01acSMauro Carvalho Chehab * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15cb7a01acSMauro Carvalho Chehab * GNU General Public License for more details.
16cb7a01acSMauro Carvalho Chehab */
17cb7a01acSMauro Carvalho Chehab
18cb7a01acSMauro Carvalho Chehab #include <linux/kernel.h>
19cb7a01acSMauro Carvalho Chehab #include <linux/init.h>
20cb7a01acSMauro Carvalho Chehab #include <linux/ctype.h>
21cb7a01acSMauro Carvalho Chehab #include <linux/slab.h>
22cb7a01acSMauro Carvalho Chehab #include <linux/i2c.h>
23cb7a01acSMauro Carvalho Chehab #include <linux/device.h>
24cb7a01acSMauro Carvalho Chehab #include <linux/delay.h>
25cb7a01acSMauro Carvalho Chehab #include <linux/module.h>
26cb7a01acSMauro Carvalho Chehab #include <linux/videodev2.h>
27cb7a01acSMauro Carvalho Chehab #include <linux/uaccess.h>
285cc6685aSSachin Kamat #include <linux/of.h>
29fd9fdb78SPhilipp Zabel #include <linux/of_graph.h>
30cb7a01acSMauro Carvalho Chehab
31b5dcee22SMauro Carvalho Chehab #include <media/i2c/adv7343.h>
326555cfc5SLad, Prabhakar #include <media/v4l2-async.h>
33cb7a01acSMauro Carvalho Chehab #include <media/v4l2-device.h>
34cb7a01acSMauro Carvalho Chehab #include <media/v4l2-ctrls.h>
35cb7a01acSMauro Carvalho Chehab
36cb7a01acSMauro Carvalho Chehab #include "adv7343_regs.h"
37cb7a01acSMauro Carvalho Chehab
38cb7a01acSMauro Carvalho Chehab MODULE_DESCRIPTION("ADV7343 video encoder driver");
39cb7a01acSMauro Carvalho Chehab MODULE_LICENSE("GPL");
40cb7a01acSMauro Carvalho Chehab
41cb7a01acSMauro Carvalho Chehab static int debug;
42cb7a01acSMauro Carvalho Chehab module_param(debug, int, 0644);
43cb7a01acSMauro Carvalho Chehab MODULE_PARM_DESC(debug, "Debug level 0-1");
44cb7a01acSMauro Carvalho Chehab
45cb7a01acSMauro Carvalho Chehab struct adv7343_state {
46cb7a01acSMauro Carvalho Chehab struct v4l2_subdev sd;
47cb7a01acSMauro Carvalho Chehab struct v4l2_ctrl_handler hdl;
480b302d88SLad, Prabhakar const struct adv7343_platform_data *pdata;
49cb7a01acSMauro Carvalho Chehab u8 reg00;
50cb7a01acSMauro Carvalho Chehab u8 reg01;
51cb7a01acSMauro Carvalho Chehab u8 reg02;
52cb7a01acSMauro Carvalho Chehab u8 reg35;
53cb7a01acSMauro Carvalho Chehab u8 reg80;
54cb7a01acSMauro Carvalho Chehab u8 reg82;
55cb7a01acSMauro Carvalho Chehab u32 output;
56cb7a01acSMauro Carvalho Chehab v4l2_std_id std;
57cb7a01acSMauro Carvalho Chehab };
58cb7a01acSMauro Carvalho Chehab
to_state(struct v4l2_subdev * sd)59cb7a01acSMauro Carvalho Chehab static inline struct adv7343_state *to_state(struct v4l2_subdev *sd)
60cb7a01acSMauro Carvalho Chehab {
61cb7a01acSMauro Carvalho Chehab return container_of(sd, struct adv7343_state, sd);
62cb7a01acSMauro Carvalho Chehab }
63cb7a01acSMauro Carvalho Chehab
to_sd(struct v4l2_ctrl * ctrl)64cb7a01acSMauro Carvalho Chehab static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
65cb7a01acSMauro Carvalho Chehab {
66cb7a01acSMauro Carvalho Chehab return &container_of(ctrl->handler, struct adv7343_state, hdl)->sd;
67cb7a01acSMauro Carvalho Chehab }
68cb7a01acSMauro Carvalho Chehab
adv7343_write(struct v4l2_subdev * sd,u8 reg,u8 value)69cb7a01acSMauro Carvalho Chehab static inline int adv7343_write(struct v4l2_subdev *sd, u8 reg, u8 value)
70cb7a01acSMauro Carvalho Chehab {
71cb7a01acSMauro Carvalho Chehab struct i2c_client *client = v4l2_get_subdevdata(sd);
72cb7a01acSMauro Carvalho Chehab
73cb7a01acSMauro Carvalho Chehab return i2c_smbus_write_byte_data(client, reg, value);
74cb7a01acSMauro Carvalho Chehab }
75cb7a01acSMauro Carvalho Chehab
76cb7a01acSMauro Carvalho Chehab static const u8 adv7343_init_reg_val[] = {
77cb7a01acSMauro Carvalho Chehab ADV7343_SOFT_RESET, ADV7343_SOFT_RESET_DEFAULT,
78cb7a01acSMauro Carvalho Chehab ADV7343_POWER_MODE_REG, ADV7343_POWER_MODE_REG_DEFAULT,
79cb7a01acSMauro Carvalho Chehab
80cb7a01acSMauro Carvalho Chehab ADV7343_HD_MODE_REG1, ADV7343_HD_MODE_REG1_DEFAULT,
81cb7a01acSMauro Carvalho Chehab ADV7343_HD_MODE_REG2, ADV7343_HD_MODE_REG2_DEFAULT,
82cb7a01acSMauro Carvalho Chehab ADV7343_HD_MODE_REG3, ADV7343_HD_MODE_REG3_DEFAULT,
83cb7a01acSMauro Carvalho Chehab ADV7343_HD_MODE_REG4, ADV7343_HD_MODE_REG4_DEFAULT,
84cb7a01acSMauro Carvalho Chehab ADV7343_HD_MODE_REG5, ADV7343_HD_MODE_REG5_DEFAULT,
85cb7a01acSMauro Carvalho Chehab ADV7343_HD_MODE_REG6, ADV7343_HD_MODE_REG6_DEFAULT,
86cb7a01acSMauro Carvalho Chehab ADV7343_HD_MODE_REG7, ADV7343_HD_MODE_REG7_DEFAULT,
87cb7a01acSMauro Carvalho Chehab
88cb7a01acSMauro Carvalho Chehab ADV7343_SD_MODE_REG1, ADV7343_SD_MODE_REG1_DEFAULT,
89cb7a01acSMauro Carvalho Chehab ADV7343_SD_MODE_REG2, ADV7343_SD_MODE_REG2_DEFAULT,
90cb7a01acSMauro Carvalho Chehab ADV7343_SD_MODE_REG3, ADV7343_SD_MODE_REG3_DEFAULT,
91cb7a01acSMauro Carvalho Chehab ADV7343_SD_MODE_REG4, ADV7343_SD_MODE_REG4_DEFAULT,
92cb7a01acSMauro Carvalho Chehab ADV7343_SD_MODE_REG5, ADV7343_SD_MODE_REG5_DEFAULT,
93cb7a01acSMauro Carvalho Chehab ADV7343_SD_MODE_REG6, ADV7343_SD_MODE_REG6_DEFAULT,
94cb7a01acSMauro Carvalho Chehab ADV7343_SD_MODE_REG7, ADV7343_SD_MODE_REG7_DEFAULT,
95cb7a01acSMauro Carvalho Chehab ADV7343_SD_MODE_REG8, ADV7343_SD_MODE_REG8_DEFAULT,
96cb7a01acSMauro Carvalho Chehab
97cb7a01acSMauro Carvalho Chehab ADV7343_SD_HUE_REG, ADV7343_SD_HUE_REG_DEFAULT,
98cb7a01acSMauro Carvalho Chehab ADV7343_SD_CGMS_WSS0, ADV7343_SD_CGMS_WSS0_DEFAULT,
99cb7a01acSMauro Carvalho Chehab ADV7343_SD_BRIGHTNESS_WSS, ADV7343_SD_BRIGHTNESS_WSS_DEFAULT,
100cb7a01acSMauro Carvalho Chehab };
101cb7a01acSMauro Carvalho Chehab
102cb7a01acSMauro Carvalho Chehab /*
103cb7a01acSMauro Carvalho Chehab * 2^32
104cb7a01acSMauro Carvalho Chehab * FSC(reg) = FSC (HZ) * --------
105cb7a01acSMauro Carvalho Chehab * 27000000
106cb7a01acSMauro Carvalho Chehab */
107cb7a01acSMauro Carvalho Chehab static const struct adv7343_std_info stdinfo[] = {
108cb7a01acSMauro Carvalho Chehab {
109cb7a01acSMauro Carvalho Chehab /* FSC(Hz) = 3,579,545.45 Hz */
110cb7a01acSMauro Carvalho Chehab SD_STD_NTSC, 569408542, V4L2_STD_NTSC,
111cb7a01acSMauro Carvalho Chehab }, {
112cb7a01acSMauro Carvalho Chehab /* FSC(Hz) = 3,575,611.00 Hz */
113cb7a01acSMauro Carvalho Chehab SD_STD_PAL_M, 568782678, V4L2_STD_PAL_M,
114cb7a01acSMauro Carvalho Chehab }, {
115cb7a01acSMauro Carvalho Chehab /* FSC(Hz) = 3,582,056.00 */
116cb7a01acSMauro Carvalho Chehab SD_STD_PAL_N, 569807903, V4L2_STD_PAL_Nc,
117cb7a01acSMauro Carvalho Chehab }, {
118cb7a01acSMauro Carvalho Chehab /* FSC(Hz) = 4,433,618.75 Hz */
119cb7a01acSMauro Carvalho Chehab SD_STD_PAL_N, 705268427, V4L2_STD_PAL_N,
120cb7a01acSMauro Carvalho Chehab }, {
121cb7a01acSMauro Carvalho Chehab /* FSC(Hz) = 4,433,618.75 Hz */
122cb7a01acSMauro Carvalho Chehab SD_STD_PAL_BDGHI, 705268427, V4L2_STD_PAL,
123cb7a01acSMauro Carvalho Chehab }, {
124cb7a01acSMauro Carvalho Chehab /* FSC(Hz) = 4,433,618.75 Hz */
125cb7a01acSMauro Carvalho Chehab SD_STD_NTSC, 705268427, V4L2_STD_NTSC_443,
126cb7a01acSMauro Carvalho Chehab }, {
127cb7a01acSMauro Carvalho Chehab /* FSC(Hz) = 4,433,618.75 Hz */
128cb7a01acSMauro Carvalho Chehab SD_STD_PAL_M, 705268427, V4L2_STD_PAL_60,
129cb7a01acSMauro Carvalho Chehab },
130cb7a01acSMauro Carvalho Chehab };
131cb7a01acSMauro Carvalho Chehab
adv7343_setstd(struct v4l2_subdev * sd,v4l2_std_id std)132cb7a01acSMauro Carvalho Chehab static int adv7343_setstd(struct v4l2_subdev *sd, v4l2_std_id std)
133cb7a01acSMauro Carvalho Chehab {
134cb7a01acSMauro Carvalho Chehab struct adv7343_state *state = to_state(sd);
135cb7a01acSMauro Carvalho Chehab struct adv7343_std_info *std_info;
136cb7a01acSMauro Carvalho Chehab int num_std;
137cb7a01acSMauro Carvalho Chehab char *fsc_ptr;
138cb7a01acSMauro Carvalho Chehab u8 reg, val;
139cb7a01acSMauro Carvalho Chehab int err = 0;
140cb7a01acSMauro Carvalho Chehab int i = 0;
141cb7a01acSMauro Carvalho Chehab
142cb7a01acSMauro Carvalho Chehab std_info = (struct adv7343_std_info *)stdinfo;
143cb7a01acSMauro Carvalho Chehab num_std = ARRAY_SIZE(stdinfo);
144cb7a01acSMauro Carvalho Chehab
145cb7a01acSMauro Carvalho Chehab for (i = 0; i < num_std; i++) {
146cb7a01acSMauro Carvalho Chehab if (std_info[i].stdid & std)
147cb7a01acSMauro Carvalho Chehab break;
148cb7a01acSMauro Carvalho Chehab }
149cb7a01acSMauro Carvalho Chehab
150cb7a01acSMauro Carvalho Chehab if (i == num_std) {
151cb7a01acSMauro Carvalho Chehab v4l2_dbg(1, debug, sd,
152cb7a01acSMauro Carvalho Chehab "Invalid std or std is not supported: %llx\n",
153cb7a01acSMauro Carvalho Chehab (unsigned long long)std);
154cb7a01acSMauro Carvalho Chehab return -EINVAL;
155cb7a01acSMauro Carvalho Chehab }
156cb7a01acSMauro Carvalho Chehab
157cb7a01acSMauro Carvalho Chehab /* Set the standard */
158cb7a01acSMauro Carvalho Chehab val = state->reg80 & (~(SD_STD_MASK));
159cb7a01acSMauro Carvalho Chehab val |= std_info[i].standard_val3;
160cb7a01acSMauro Carvalho Chehab err = adv7343_write(sd, ADV7343_SD_MODE_REG1, val);
161cb7a01acSMauro Carvalho Chehab if (err < 0)
162cb7a01acSMauro Carvalho Chehab goto setstd_exit;
163cb7a01acSMauro Carvalho Chehab
164cb7a01acSMauro Carvalho Chehab state->reg80 = val;
165cb7a01acSMauro Carvalho Chehab
166cb7a01acSMauro Carvalho Chehab /* Configure the input mode register */
167cb7a01acSMauro Carvalho Chehab val = state->reg01 & (~((u8) INPUT_MODE_MASK));
168cb7a01acSMauro Carvalho Chehab val |= SD_INPUT_MODE;
169cb7a01acSMauro Carvalho Chehab err = adv7343_write(sd, ADV7343_MODE_SELECT_REG, val);
170cb7a01acSMauro Carvalho Chehab if (err < 0)
171cb7a01acSMauro Carvalho Chehab goto setstd_exit;
172cb7a01acSMauro Carvalho Chehab
173cb7a01acSMauro Carvalho Chehab state->reg01 = val;
174cb7a01acSMauro Carvalho Chehab
175cb7a01acSMauro Carvalho Chehab /* Program the sub carrier frequency registers */
176cb7a01acSMauro Carvalho Chehab fsc_ptr = (unsigned char *)&std_info[i].fsc_val;
177cb7a01acSMauro Carvalho Chehab reg = ADV7343_FSC_REG0;
178cb7a01acSMauro Carvalho Chehab for (i = 0; i < 4; i++, reg++, fsc_ptr++) {
179cb7a01acSMauro Carvalho Chehab err = adv7343_write(sd, reg, *fsc_ptr);
180cb7a01acSMauro Carvalho Chehab if (err < 0)
181cb7a01acSMauro Carvalho Chehab goto setstd_exit;
182cb7a01acSMauro Carvalho Chehab }
183cb7a01acSMauro Carvalho Chehab
184cb7a01acSMauro Carvalho Chehab val = state->reg80;
185cb7a01acSMauro Carvalho Chehab
186cb7a01acSMauro Carvalho Chehab /* Filter settings */
187cb7a01acSMauro Carvalho Chehab if (std & (V4L2_STD_NTSC | V4L2_STD_NTSC_443))
188cb7a01acSMauro Carvalho Chehab val &= 0x03;
189cb7a01acSMauro Carvalho Chehab else if (std & ~V4L2_STD_SECAM)
190cb7a01acSMauro Carvalho Chehab val |= 0x04;
191cb7a01acSMauro Carvalho Chehab
192cb7a01acSMauro Carvalho Chehab err = adv7343_write(sd, ADV7343_SD_MODE_REG1, val);
193cb7a01acSMauro Carvalho Chehab if (err < 0)
194cb7a01acSMauro Carvalho Chehab goto setstd_exit;
195cb7a01acSMauro Carvalho Chehab
196cb7a01acSMauro Carvalho Chehab state->reg80 = val;
197cb7a01acSMauro Carvalho Chehab
198cb7a01acSMauro Carvalho Chehab setstd_exit:
199cb7a01acSMauro Carvalho Chehab if (err != 0)
200cb7a01acSMauro Carvalho Chehab v4l2_err(sd, "Error setting std, write failed\n");
201cb7a01acSMauro Carvalho Chehab
202cb7a01acSMauro Carvalho Chehab return err;
203cb7a01acSMauro Carvalho Chehab }
204cb7a01acSMauro Carvalho Chehab
adv7343_setoutput(struct v4l2_subdev * sd,u32 output_type)205cb7a01acSMauro Carvalho Chehab static int adv7343_setoutput(struct v4l2_subdev *sd, u32 output_type)
206cb7a01acSMauro Carvalho Chehab {
207cb7a01acSMauro Carvalho Chehab struct adv7343_state *state = to_state(sd);
208cb7a01acSMauro Carvalho Chehab unsigned char val;
209cb7a01acSMauro Carvalho Chehab int err = 0;
210cb7a01acSMauro Carvalho Chehab
211cb7a01acSMauro Carvalho Chehab if (output_type > ADV7343_SVIDEO_ID) {
212cb7a01acSMauro Carvalho Chehab v4l2_dbg(1, debug, sd,
213cb7a01acSMauro Carvalho Chehab "Invalid output type or output type not supported:%d\n",
214cb7a01acSMauro Carvalho Chehab output_type);
215cb7a01acSMauro Carvalho Chehab return -EINVAL;
216cb7a01acSMauro Carvalho Chehab }
217cb7a01acSMauro Carvalho Chehab
218cb7a01acSMauro Carvalho Chehab /* Enable Appropriate DAC */
219cb7a01acSMauro Carvalho Chehab val = state->reg00 & 0x03;
220cb7a01acSMauro Carvalho Chehab
2210b302d88SLad, Prabhakar /* configure default configuration */
2220b302d88SLad, Prabhakar if (!state->pdata)
223cb7a01acSMauro Carvalho Chehab if (output_type == ADV7343_COMPOSITE_ID)
224cb7a01acSMauro Carvalho Chehab val |= ADV7343_COMPOSITE_POWER_VALUE;
225cb7a01acSMauro Carvalho Chehab else if (output_type == ADV7343_COMPONENT_ID)
226cb7a01acSMauro Carvalho Chehab val |= ADV7343_COMPONENT_POWER_VALUE;
227cb7a01acSMauro Carvalho Chehab else
228cb7a01acSMauro Carvalho Chehab val |= ADV7343_SVIDEO_POWER_VALUE;
2290b302d88SLad, Prabhakar else
2300b302d88SLad, Prabhakar val = state->pdata->mode_config.sleep_mode << 0 |
2310b302d88SLad, Prabhakar state->pdata->mode_config.pll_control << 1 |
2325e95814fSLad, Prabhakar state->pdata->mode_config.dac[2] << 2 |
2335e95814fSLad, Prabhakar state->pdata->mode_config.dac[1] << 3 |
2345e95814fSLad, Prabhakar state->pdata->mode_config.dac[0] << 4 |
2355e95814fSLad, Prabhakar state->pdata->mode_config.dac[5] << 5 |
2365e95814fSLad, Prabhakar state->pdata->mode_config.dac[4] << 6 |
2375e95814fSLad, Prabhakar state->pdata->mode_config.dac[3] << 7;
238cb7a01acSMauro Carvalho Chehab
239cb7a01acSMauro Carvalho Chehab err = adv7343_write(sd, ADV7343_POWER_MODE_REG, val);
240cb7a01acSMauro Carvalho Chehab if (err < 0)
241cb7a01acSMauro Carvalho Chehab goto setoutput_exit;
242cb7a01acSMauro Carvalho Chehab
243cb7a01acSMauro Carvalho Chehab state->reg00 = val;
244cb7a01acSMauro Carvalho Chehab
245cb7a01acSMauro Carvalho Chehab /* Enable YUV output */
246cb7a01acSMauro Carvalho Chehab val = state->reg02 | YUV_OUTPUT_SELECT;
247cb7a01acSMauro Carvalho Chehab err = adv7343_write(sd, ADV7343_MODE_REG0, val);
248cb7a01acSMauro Carvalho Chehab if (err < 0)
249cb7a01acSMauro Carvalho Chehab goto setoutput_exit;
250cb7a01acSMauro Carvalho Chehab
251cb7a01acSMauro Carvalho Chehab state->reg02 = val;
252cb7a01acSMauro Carvalho Chehab
253cb7a01acSMauro Carvalho Chehab /* configure SD DAC Output 2 and SD DAC Output 1 bit to zero */
254cb7a01acSMauro Carvalho Chehab val = state->reg82 & (SD_DAC_1_DI & SD_DAC_2_DI);
2550b302d88SLad, Prabhakar
2565e95814fSLad, Prabhakar if (state->pdata && state->pdata->sd_config.sd_dac_out[0])
2575e95814fSLad, Prabhakar val = val | (state->pdata->sd_config.sd_dac_out[0] << 1);
2585e95814fSLad, Prabhakar else if (state->pdata && !state->pdata->sd_config.sd_dac_out[0])
2595e95814fSLad, Prabhakar val = val & ~(state->pdata->sd_config.sd_dac_out[0] << 1);
2600b302d88SLad, Prabhakar
2615e95814fSLad, Prabhakar if (state->pdata && state->pdata->sd_config.sd_dac_out[1])
2625e95814fSLad, Prabhakar val = val | (state->pdata->sd_config.sd_dac_out[1] << 2);
2635e95814fSLad, Prabhakar else if (state->pdata && !state->pdata->sd_config.sd_dac_out[1])
2645e95814fSLad, Prabhakar val = val & ~(state->pdata->sd_config.sd_dac_out[1] << 2);
2650b302d88SLad, Prabhakar
266cb7a01acSMauro Carvalho Chehab err = adv7343_write(sd, ADV7343_SD_MODE_REG2, val);
267cb7a01acSMauro Carvalho Chehab if (err < 0)
268cb7a01acSMauro Carvalho Chehab goto setoutput_exit;
269cb7a01acSMauro Carvalho Chehab
270cb7a01acSMauro Carvalho Chehab state->reg82 = val;
271cb7a01acSMauro Carvalho Chehab
272cb7a01acSMauro Carvalho Chehab /* configure ED/HD Color DAC Swap and ED/HD RGB Input Enable bit to
273cb7a01acSMauro Carvalho Chehab * zero */
274cb7a01acSMauro Carvalho Chehab val = state->reg35 & (HD_RGB_INPUT_DI & HD_DAC_SWAP_DI);
275cb7a01acSMauro Carvalho Chehab err = adv7343_write(sd, ADV7343_HD_MODE_REG6, val);
276cb7a01acSMauro Carvalho Chehab if (err < 0)
277cb7a01acSMauro Carvalho Chehab goto setoutput_exit;
278cb7a01acSMauro Carvalho Chehab
279cb7a01acSMauro Carvalho Chehab state->reg35 = val;
280cb7a01acSMauro Carvalho Chehab
281cb7a01acSMauro Carvalho Chehab setoutput_exit:
282cb7a01acSMauro Carvalho Chehab if (err != 0)
283cb7a01acSMauro Carvalho Chehab v4l2_err(sd, "Error setting output, write failed\n");
284cb7a01acSMauro Carvalho Chehab
285cb7a01acSMauro Carvalho Chehab return err;
286cb7a01acSMauro Carvalho Chehab }
287cb7a01acSMauro Carvalho Chehab
adv7343_log_status(struct v4l2_subdev * sd)288cb7a01acSMauro Carvalho Chehab static int adv7343_log_status(struct v4l2_subdev *sd)
289cb7a01acSMauro Carvalho Chehab {
290cb7a01acSMauro Carvalho Chehab struct adv7343_state *state = to_state(sd);
291cb7a01acSMauro Carvalho Chehab
292cb7a01acSMauro Carvalho Chehab v4l2_info(sd, "Standard: %llx\n", (unsigned long long)state->std);
293cb7a01acSMauro Carvalho Chehab v4l2_info(sd, "Output: %s\n", (state->output == 0) ? "Composite" :
294cb7a01acSMauro Carvalho Chehab ((state->output == 1) ? "Component" : "S-Video"));
295cb7a01acSMauro Carvalho Chehab return 0;
296cb7a01acSMauro Carvalho Chehab }
297cb7a01acSMauro Carvalho Chehab
adv7343_s_ctrl(struct v4l2_ctrl * ctrl)298cb7a01acSMauro Carvalho Chehab static int adv7343_s_ctrl(struct v4l2_ctrl *ctrl)
299cb7a01acSMauro Carvalho Chehab {
300cb7a01acSMauro Carvalho Chehab struct v4l2_subdev *sd = to_sd(ctrl);
301cb7a01acSMauro Carvalho Chehab
302cb7a01acSMauro Carvalho Chehab switch (ctrl->id) {
303cb7a01acSMauro Carvalho Chehab case V4L2_CID_BRIGHTNESS:
304cb7a01acSMauro Carvalho Chehab return adv7343_write(sd, ADV7343_SD_BRIGHTNESS_WSS,
305cb7a01acSMauro Carvalho Chehab ctrl->val);
306cb7a01acSMauro Carvalho Chehab
307cb7a01acSMauro Carvalho Chehab case V4L2_CID_HUE:
308cb7a01acSMauro Carvalho Chehab return adv7343_write(sd, ADV7343_SD_HUE_REG, ctrl->val);
309cb7a01acSMauro Carvalho Chehab
310cb7a01acSMauro Carvalho Chehab case V4L2_CID_GAIN:
311cb7a01acSMauro Carvalho Chehab return adv7343_write(sd, ADV7343_DAC2_OUTPUT_LEVEL, ctrl->val);
312cb7a01acSMauro Carvalho Chehab }
313cb7a01acSMauro Carvalho Chehab return -EINVAL;
314cb7a01acSMauro Carvalho Chehab }
315cb7a01acSMauro Carvalho Chehab
316cb7a01acSMauro Carvalho Chehab static const struct v4l2_ctrl_ops adv7343_ctrl_ops = {
317cb7a01acSMauro Carvalho Chehab .s_ctrl = adv7343_s_ctrl,
318cb7a01acSMauro Carvalho Chehab };
319cb7a01acSMauro Carvalho Chehab
320cb7a01acSMauro Carvalho Chehab static const struct v4l2_subdev_core_ops adv7343_core_ops = {
321cb7a01acSMauro Carvalho Chehab .log_status = adv7343_log_status,
322cb7a01acSMauro Carvalho Chehab };
323cb7a01acSMauro Carvalho Chehab
adv7343_s_std_output(struct v4l2_subdev * sd,v4l2_std_id std)324cb7a01acSMauro Carvalho Chehab static int adv7343_s_std_output(struct v4l2_subdev *sd, v4l2_std_id std)
325cb7a01acSMauro Carvalho Chehab {
326cb7a01acSMauro Carvalho Chehab struct adv7343_state *state = to_state(sd);
327cb7a01acSMauro Carvalho Chehab int err = 0;
328cb7a01acSMauro Carvalho Chehab
329cb7a01acSMauro Carvalho Chehab if (state->std == std)
330cb7a01acSMauro Carvalho Chehab return 0;
331cb7a01acSMauro Carvalho Chehab
332cb7a01acSMauro Carvalho Chehab err = adv7343_setstd(sd, std);
333cb7a01acSMauro Carvalho Chehab if (!err)
334cb7a01acSMauro Carvalho Chehab state->std = std;
335cb7a01acSMauro Carvalho Chehab
336cb7a01acSMauro Carvalho Chehab return err;
337cb7a01acSMauro Carvalho Chehab }
338cb7a01acSMauro Carvalho Chehab
adv7343_s_routing(struct v4l2_subdev * sd,u32 input,u32 output,u32 config)339cb7a01acSMauro Carvalho Chehab static int adv7343_s_routing(struct v4l2_subdev *sd,
340cb7a01acSMauro Carvalho Chehab u32 input, u32 output, u32 config)
341cb7a01acSMauro Carvalho Chehab {
342cb7a01acSMauro Carvalho Chehab struct adv7343_state *state = to_state(sd);
343cb7a01acSMauro Carvalho Chehab int err = 0;
344cb7a01acSMauro Carvalho Chehab
345cb7a01acSMauro Carvalho Chehab if (state->output == output)
346cb7a01acSMauro Carvalho Chehab return 0;
347cb7a01acSMauro Carvalho Chehab
348cb7a01acSMauro Carvalho Chehab err = adv7343_setoutput(sd, output);
349cb7a01acSMauro Carvalho Chehab if (!err)
350cb7a01acSMauro Carvalho Chehab state->output = output;
351cb7a01acSMauro Carvalho Chehab
352cb7a01acSMauro Carvalho Chehab return err;
353cb7a01acSMauro Carvalho Chehab }
354cb7a01acSMauro Carvalho Chehab
355cb7a01acSMauro Carvalho Chehab static const struct v4l2_subdev_video_ops adv7343_video_ops = {
356cb7a01acSMauro Carvalho Chehab .s_std_output = adv7343_s_std_output,
357cb7a01acSMauro Carvalho Chehab .s_routing = adv7343_s_routing,
358cb7a01acSMauro Carvalho Chehab };
359cb7a01acSMauro Carvalho Chehab
360cb7a01acSMauro Carvalho Chehab static const struct v4l2_subdev_ops adv7343_ops = {
361cb7a01acSMauro Carvalho Chehab .core = &adv7343_core_ops,
362cb7a01acSMauro Carvalho Chehab .video = &adv7343_video_ops,
363cb7a01acSMauro Carvalho Chehab };
364cb7a01acSMauro Carvalho Chehab
adv7343_initialize(struct v4l2_subdev * sd)365cb7a01acSMauro Carvalho Chehab static int adv7343_initialize(struct v4l2_subdev *sd)
366cb7a01acSMauro Carvalho Chehab {
367cb7a01acSMauro Carvalho Chehab struct adv7343_state *state = to_state(sd);
368cb7a01acSMauro Carvalho Chehab int err = 0;
369cb7a01acSMauro Carvalho Chehab int i;
370cb7a01acSMauro Carvalho Chehab
371cb7a01acSMauro Carvalho Chehab for (i = 0; i < ARRAY_SIZE(adv7343_init_reg_val); i += 2) {
372cb7a01acSMauro Carvalho Chehab
373cb7a01acSMauro Carvalho Chehab err = adv7343_write(sd, adv7343_init_reg_val[i],
374cb7a01acSMauro Carvalho Chehab adv7343_init_reg_val[i+1]);
375cb7a01acSMauro Carvalho Chehab if (err) {
376cb7a01acSMauro Carvalho Chehab v4l2_err(sd, "Error initializing\n");
377cb7a01acSMauro Carvalho Chehab return err;
378cb7a01acSMauro Carvalho Chehab }
379cb7a01acSMauro Carvalho Chehab }
380cb7a01acSMauro Carvalho Chehab
381cb7a01acSMauro Carvalho Chehab /* Configure for default video standard */
382cb7a01acSMauro Carvalho Chehab err = adv7343_setoutput(sd, state->output);
383cb7a01acSMauro Carvalho Chehab if (err < 0) {
384cb7a01acSMauro Carvalho Chehab v4l2_err(sd, "Error setting output during init\n");
385cb7a01acSMauro Carvalho Chehab return -EINVAL;
386cb7a01acSMauro Carvalho Chehab }
387cb7a01acSMauro Carvalho Chehab
388cb7a01acSMauro Carvalho Chehab err = adv7343_setstd(sd, state->std);
389cb7a01acSMauro Carvalho Chehab if (err < 0) {
390cb7a01acSMauro Carvalho Chehab v4l2_err(sd, "Error setting std during init\n");
391cb7a01acSMauro Carvalho Chehab return -EINVAL;
392cb7a01acSMauro Carvalho Chehab }
393cb7a01acSMauro Carvalho Chehab
394cb7a01acSMauro Carvalho Chehab return err;
395cb7a01acSMauro Carvalho Chehab }
396cb7a01acSMauro Carvalho Chehab
397187d42d6SLad, Prabhakar static struct adv7343_platform_data *
adv7343_get_pdata(struct i2c_client * client)398187d42d6SLad, Prabhakar adv7343_get_pdata(struct i2c_client *client)
399187d42d6SLad, Prabhakar {
400187d42d6SLad, Prabhakar struct adv7343_platform_data *pdata;
401187d42d6SLad, Prabhakar struct device_node *np;
402187d42d6SLad, Prabhakar
403187d42d6SLad, Prabhakar if (!IS_ENABLED(CONFIG_OF) || !client->dev.of_node)
404187d42d6SLad, Prabhakar return client->dev.platform_data;
405187d42d6SLad, Prabhakar
406fd9fdb78SPhilipp Zabel np = of_graph_get_next_endpoint(client->dev.of_node, NULL);
407187d42d6SLad, Prabhakar if (!np)
408187d42d6SLad, Prabhakar return NULL;
409187d42d6SLad, Prabhakar
410187d42d6SLad, Prabhakar pdata = devm_kzalloc(&client->dev, sizeof(*pdata), GFP_KERNEL);
411187d42d6SLad, Prabhakar if (!pdata)
412187d42d6SLad, Prabhakar goto done;
413187d42d6SLad, Prabhakar
414187d42d6SLad, Prabhakar pdata->mode_config.sleep_mode =
415187d42d6SLad, Prabhakar of_property_read_bool(np, "adi,power-mode-sleep-mode");
416187d42d6SLad, Prabhakar
417187d42d6SLad, Prabhakar pdata->mode_config.pll_control =
418187d42d6SLad, Prabhakar of_property_read_bool(np, "adi,power-mode-pll-ctrl");
419187d42d6SLad, Prabhakar
420187d42d6SLad, Prabhakar of_property_read_u32_array(np, "adi,dac-enable",
421187d42d6SLad, Prabhakar pdata->mode_config.dac, 6);
422187d42d6SLad, Prabhakar
423187d42d6SLad, Prabhakar of_property_read_u32_array(np, "adi,sd-dac-enable",
424187d42d6SLad, Prabhakar pdata->sd_config.sd_dac_out, 2);
425187d42d6SLad, Prabhakar
426187d42d6SLad, Prabhakar done:
427187d42d6SLad, Prabhakar of_node_put(np);
428187d42d6SLad, Prabhakar return pdata;
429187d42d6SLad, Prabhakar }
430187d42d6SLad, Prabhakar
adv7343_probe(struct i2c_client * client)431e6714993SKieran Bingham static int adv7343_probe(struct i2c_client *client)
432cb7a01acSMauro Carvalho Chehab {
433cb7a01acSMauro Carvalho Chehab struct adv7343_state *state;
434cb7a01acSMauro Carvalho Chehab int err;
435cb7a01acSMauro Carvalho Chehab
436cb7a01acSMauro Carvalho Chehab if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
437cb7a01acSMauro Carvalho Chehab return -ENODEV;
438cb7a01acSMauro Carvalho Chehab
439cb7a01acSMauro Carvalho Chehab v4l_info(client, "chip found @ 0x%x (%s)\n",
440cb7a01acSMauro Carvalho Chehab client->addr << 1, client->adapter->name);
441cb7a01acSMauro Carvalho Chehab
442c7a857a0SLad, Prabhakar state = devm_kzalloc(&client->dev, sizeof(struct adv7343_state),
443c7a857a0SLad, Prabhakar GFP_KERNEL);
444cb7a01acSMauro Carvalho Chehab if (state == NULL)
445cb7a01acSMauro Carvalho Chehab return -ENOMEM;
446cb7a01acSMauro Carvalho Chehab
4470b302d88SLad, Prabhakar /* Copy board specific information here */
448187d42d6SLad, Prabhakar state->pdata = adv7343_get_pdata(client);
4490b302d88SLad, Prabhakar
450cb7a01acSMauro Carvalho Chehab state->reg00 = 0x80;
451cb7a01acSMauro Carvalho Chehab state->reg01 = 0x00;
452cb7a01acSMauro Carvalho Chehab state->reg02 = 0x20;
453cb7a01acSMauro Carvalho Chehab state->reg35 = 0x00;
454cb7a01acSMauro Carvalho Chehab state->reg80 = ADV7343_SD_MODE_REG1_DEFAULT;
455cb7a01acSMauro Carvalho Chehab state->reg82 = ADV7343_SD_MODE_REG2_DEFAULT;
456cb7a01acSMauro Carvalho Chehab
457cb7a01acSMauro Carvalho Chehab state->output = ADV7343_COMPOSITE_ID;
458cb7a01acSMauro Carvalho Chehab state->std = V4L2_STD_NTSC;
459cb7a01acSMauro Carvalho Chehab
460cb7a01acSMauro Carvalho Chehab v4l2_i2c_subdev_init(&state->sd, client, &adv7343_ops);
461cb7a01acSMauro Carvalho Chehab
462cb7a01acSMauro Carvalho Chehab v4l2_ctrl_handler_init(&state->hdl, 2);
463cb7a01acSMauro Carvalho Chehab v4l2_ctrl_new_std(&state->hdl, &adv7343_ctrl_ops,
464cb7a01acSMauro Carvalho Chehab V4L2_CID_BRIGHTNESS, ADV7343_BRIGHTNESS_MIN,
465cb7a01acSMauro Carvalho Chehab ADV7343_BRIGHTNESS_MAX, 1,
466cb7a01acSMauro Carvalho Chehab ADV7343_BRIGHTNESS_DEF);
467cb7a01acSMauro Carvalho Chehab v4l2_ctrl_new_std(&state->hdl, &adv7343_ctrl_ops,
468cb7a01acSMauro Carvalho Chehab V4L2_CID_HUE, ADV7343_HUE_MIN,
469cb7a01acSMauro Carvalho Chehab ADV7343_HUE_MAX, 1,
470cb7a01acSMauro Carvalho Chehab ADV7343_HUE_DEF);
471cb7a01acSMauro Carvalho Chehab v4l2_ctrl_new_std(&state->hdl, &adv7343_ctrl_ops,
472cb7a01acSMauro Carvalho Chehab V4L2_CID_GAIN, ADV7343_GAIN_MIN,
473cb7a01acSMauro Carvalho Chehab ADV7343_GAIN_MAX, 1,
474cb7a01acSMauro Carvalho Chehab ADV7343_GAIN_DEF);
475cb7a01acSMauro Carvalho Chehab state->sd.ctrl_handler = &state->hdl;
476cb7a01acSMauro Carvalho Chehab if (state->hdl.error) {
4776555cfc5SLad, Prabhakar err = state->hdl.error;
4786555cfc5SLad, Prabhakar goto done;
479cb7a01acSMauro Carvalho Chehab }
480cb7a01acSMauro Carvalho Chehab v4l2_ctrl_handler_setup(&state->hdl);
481cb7a01acSMauro Carvalho Chehab
482cb7a01acSMauro Carvalho Chehab err = adv7343_initialize(&state->sd);
483c7a857a0SLad, Prabhakar if (err)
4846555cfc5SLad, Prabhakar goto done;
4856555cfc5SLad, Prabhakar
4866555cfc5SLad, Prabhakar err = v4l2_async_register_subdev(&state->sd);
4876555cfc5SLad, Prabhakar
4886555cfc5SLad, Prabhakar done:
4896555cfc5SLad, Prabhakar if (err < 0)
490cb7a01acSMauro Carvalho Chehab v4l2_ctrl_handler_free(&state->hdl);
4916555cfc5SLad, Prabhakar
492cb7a01acSMauro Carvalho Chehab return err;
493cb7a01acSMauro Carvalho Chehab }
494cb7a01acSMauro Carvalho Chehab
adv7343_remove(struct i2c_client * client)495ed5c2f5fSUwe Kleine-König static void adv7343_remove(struct i2c_client *client)
496cb7a01acSMauro Carvalho Chehab {
497cb7a01acSMauro Carvalho Chehab struct v4l2_subdev *sd = i2c_get_clientdata(client);
498cb7a01acSMauro Carvalho Chehab struct adv7343_state *state = to_state(sd);
499cb7a01acSMauro Carvalho Chehab
5006555cfc5SLad, Prabhakar v4l2_async_unregister_subdev(&state->sd);
501cb7a01acSMauro Carvalho Chehab v4l2_ctrl_handler_free(&state->hdl);
502cb7a01acSMauro Carvalho Chehab }
503cb7a01acSMauro Carvalho Chehab
504cb7a01acSMauro Carvalho Chehab static const struct i2c_device_id adv7343_id[] = {
505cb7a01acSMauro Carvalho Chehab {"adv7343", 0},
506cb7a01acSMauro Carvalho Chehab {},
507cb7a01acSMauro Carvalho Chehab };
508cb7a01acSMauro Carvalho Chehab
509cb7a01acSMauro Carvalho Chehab MODULE_DEVICE_TABLE(i2c, adv7343_id);
510cb7a01acSMauro Carvalho Chehab
511187d42d6SLad, Prabhakar #if IS_ENABLED(CONFIG_OF)
512187d42d6SLad, Prabhakar static const struct of_device_id adv7343_of_match[] = {
513187d42d6SLad, Prabhakar {.compatible = "adi,adv7343", },
514187d42d6SLad, Prabhakar { /* sentinel */ },
515187d42d6SLad, Prabhakar };
516187d42d6SLad, Prabhakar MODULE_DEVICE_TABLE(of, adv7343_of_match);
517187d42d6SLad, Prabhakar #endif
518187d42d6SLad, Prabhakar
519cb7a01acSMauro Carvalho Chehab static struct i2c_driver adv7343_driver = {
520cb7a01acSMauro Carvalho Chehab .driver = {
521187d42d6SLad, Prabhakar .of_match_table = of_match_ptr(adv7343_of_match),
522cb7a01acSMauro Carvalho Chehab .name = "adv7343",
523cb7a01acSMauro Carvalho Chehab },
524*aaeb31c0SUwe Kleine-König .probe = adv7343_probe,
525cb7a01acSMauro Carvalho Chehab .remove = adv7343_remove,
526cb7a01acSMauro Carvalho Chehab .id_table = adv7343_id,
527cb7a01acSMauro Carvalho Chehab };
528cb7a01acSMauro Carvalho Chehab
529cb7a01acSMauro Carvalho Chehab module_i2c_driver(adv7343_driver);
530